1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/mach-imx/spi.h>
18 #include <linux/errno.h>
19 #include <asm/gpio.h>
20 #include <mmc.h>
21 #include <i2c.h>
22 #include <fsl_esdhc.h>
23 #include <nand.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/sections.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
32 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
33 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34
35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41
42 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
44
45 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
47 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
48
49 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
50
51 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56
57 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
58 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
59 #define GREEN_LED IMX_GPIO_NR(2, 31)
60 #define RED_LED IMX_GPIO_NR(1, 30)
61 #define IMX6Q_DRIVE_STRENGTH 0x30
62
dram_init(void)63 int dram_init(void)
64 {
65 gd->ram_size = imx_ddr_size();
66 return 0;
67 }
68
69 static iomux_v3_cfg_t const uart4_pads[] = {
70 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
72 };
73
74 static iomux_v3_cfg_t const enet_pads[] = {
75 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
83 MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
92 MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 };
95
96 static iomux_v3_cfg_t const ecspi3_pads[] = {
97 IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
98 IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
99 IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
100 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 };
102
103 static iomux_v3_cfg_t const gpios_pads[] = {
104 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
107 IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
110 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
111 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 };
113
114 #ifdef CONFIG_CMD_NAND
115 /* NAND */
116 static iomux_v3_cfg_t const nfc_pads[] = {
117 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
118 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
119 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
120 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
121 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
122 IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
123 IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
124 IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
126 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
127 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
128 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
129 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
130 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
131 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
132 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
133 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
134 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
136 };
137 #endif
138
139 static struct i2c_pads_info i2c_pad_info = {
140 .scl = {
141 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
142 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
143 .gp = IMX_GPIO_NR(3, 21)
144 },
145 .sda = {
146 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
147 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
148 .gp = IMX_GPIO_NR(3, 28)
149 }
150 };
151
152 static struct fsl_esdhc_cfg usdhc_cfg[] = {
153 {USDHC3_BASE_ADDR,
154 .max_bus_width = 4},
155 {.esdhc_base = USDHC2_BASE_ADDR,
156 .max_bus_width = 4},
157 };
158
159 #if !defined(CONFIG_SPL_BUILD)
160 static iomux_v3_cfg_t const usdhc2_pads[] = {
161 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
162 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
163 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
164 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
165 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
166 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
168 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169 };
170 #endif
171
172 static iomux_v3_cfg_t const usdhc3_pads[] = {
173 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
174 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
175 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
176 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
177 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
178 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
179 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
180 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
181 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
182 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
183 };
184
board_mmc_get_env_dev(int devno)185 int board_mmc_get_env_dev(int devno)
186 {
187 return devno - 1;
188 }
189
board_mmc_getcd(struct mmc * mmc)190 int board_mmc_getcd(struct mmc *mmc)
191 {
192 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
193 int ret = 0;
194
195 switch (cfg->esdhc_base) {
196 case USDHC2_BASE_ADDR:
197 ret = !gpio_get_value(USDHC2_CD_GPIO);
198 ret = 1;
199 break;
200 case USDHC3_BASE_ADDR:
201 ret = 1;
202 break;
203 }
204
205 return ret;
206 }
207
208 #ifndef CONFIG_SPL_BUILD
board_mmc_init(bd_t * bis)209 int board_mmc_init(bd_t *bis)
210 {
211 int ret;
212 int i;
213
214 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
215 switch (i) {
216 case 0:
217 SETUP_IOMUX_PADS(usdhc3_pads);
218 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
219 break;
220 case 1:
221 SETUP_IOMUX_PADS(usdhc2_pads);
222 gpio_direction_input(USDHC2_CD_GPIO);
223 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
224 break;
225 default:
226 printf("Warning: you configured more USDHC controllers"
227 "(%d) then supported by the board (%d)\n",
228 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
229 return -EINVAL;
230 }
231
232 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
233 if (ret)
234 return ret;
235 }
236
237 return 0;
238 }
239 #endif
240
setup_iomux_uart(void)241 static void setup_iomux_uart(void)
242 {
243 SETUP_IOMUX_PADS(uart4_pads);
244 }
245
setup_iomux_enet(void)246 static void setup_iomux_enet(void)
247 {
248 SETUP_IOMUX_PADS(enet_pads);
249
250 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
251 mdelay(10);
252 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
253 mdelay(30);
254 }
255
setup_spi(void)256 static void setup_spi(void)
257 {
258 gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
259 gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
260
261 SETUP_IOMUX_PADS(ecspi3_pads);
262
263 enable_spi_clk(true, 2);
264 }
265
setup_gpios(void)266 static void setup_gpios(void)
267 {
268 SETUP_IOMUX_PADS(gpios_pads);
269 }
270
271 #ifdef CONFIG_CMD_NAND
setup_gpmi_nand(void)272 static void setup_gpmi_nand(void)
273 {
274 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
275
276 /* config gpmi nand iomux */
277 SETUP_IOMUX_PADS(nfc_pads);
278
279 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
280 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
281
282 /* config gpmi and bch clock to 100 MHz */
283 clrsetbits_le32(&mxc_ccm->cs2cdr,
284 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
285 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
286 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
287 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
288 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
289 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
290
291 /* enable ENFC_CLK_ROOT clock */
292 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
293
294 /* enable gpmi and bch clock gating */
295 setbits_le32(&mxc_ccm->CCGR4,
296 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
297 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
298 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
299 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
300 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
301
302 /* enable apbh clock gating */
303 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
304 }
305 #endif
306
307 /*
308 * Board revision is coded in 4 GPIOs
309 */
get_board_rev(void)310 u32 get_board_rev(void)
311 {
312 u32 rev;
313 int i;
314
315 for (i = 0, rev = 0; i < 4; i++)
316 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
317
318 return 16 - rev;
319 }
320
board_spi_cs_gpio(unsigned bus,unsigned cs)321 int board_spi_cs_gpio(unsigned bus, unsigned cs)
322 {
323 if (bus != 2 || (cs != 0))
324 return -EINVAL;
325
326 return IMX_GPIO_NR(4, 24);
327 }
328
board_eth_init(bd_t * bis)329 int board_eth_init(bd_t *bis)
330 {
331 setup_iomux_enet();
332
333 return cpu_eth_init(bis);
334 }
335
board_early_init_f(void)336 int board_early_init_f(void)
337 {
338 setup_iomux_uart();
339
340 return 0;
341 }
342
board_init(void)343 int board_init(void)
344 {
345 /* address of boot parameters */
346 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
347
348 #ifdef CONFIG_SYS_I2C_MXC
349 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
350 #endif
351
352 #ifdef CONFIG_MXC_SPI
353 setup_spi();
354 #endif
355
356 setup_gpios();
357
358 #ifdef CONFIG_CMD_NAND
359 setup_gpmi_nand();
360 #endif
361 return 0;
362 }
363
364
365 #ifdef CONFIG_CMD_BMODE
366 /*
367 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
368 * see Table 8-11 and Table 5-9
369 * BOOT_CFG1[7] = 1 (boot from NAND)
370 * BOOT_CFG1[5] = 0 - raw NAND
371 * BOOT_CFG1[4] = 0 - default pad settings
372 * BOOT_CFG1[3:2] = 00 - devices = 1
373 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
374 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
375 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
376 * BOOT_CFG2[0] = 0 - Reset time 12ms
377 */
378 static const struct boot_mode board_boot_modes[] = {
379 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
380 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
381 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
382 {NULL, 0},
383 };
384 #endif
385
board_late_init(void)386 int board_late_init(void)
387 {
388 char buf[10];
389 #ifdef CONFIG_CMD_BMODE
390 add_board_boot_modes(board_boot_modes);
391 #endif
392
393 snprintf(buf, sizeof(buf), "%d", get_board_rev());
394 env_set("board_rev", buf);
395
396 return 0;
397 }
398
399 #ifdef CONFIG_SPL_BUILD
400 #include <asm/arch/mx6-ddr.h>
401 #include <spl.h>
402 #include <linux/libfdt.h>
403
404 #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
phyflex_err006282_workaround(void)405 static void phyflex_err006282_workaround(void)
406 {
407 /*
408 * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
409 * to the CMIC. If this pin isn't toggled within 10s the boards
410 * reset. The pin is unconnected on older boards, so we do not
411 * need a check for older boards before applying this fixup.
412 */
413
414 gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
415 mdelay(2);
416 gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
417 mdelay(2);
418 gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
419
420 gpio_direction_input(MX6_PHYFLEX_ERR006282);
421 }
422
423 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
424 .dram_sdclk_0 = 0x00000030,
425 .dram_sdclk_1 = 0x00000030,
426 .dram_cas = 0x00000030,
427 .dram_ras = 0x00000030,
428 .dram_reset = 0x00000030,
429 .dram_sdcke0 = 0x00003000,
430 .dram_sdcke1 = 0x00003000,
431 .dram_sdba2 = 0x00000030,
432 .dram_sdodt0 = 0x00000030,
433 .dram_sdodt1 = 0x00000030,
434
435 .dram_sdqs0 = 0x00000028,
436 .dram_sdqs1 = 0x00000028,
437 .dram_sdqs2 = 0x00000028,
438 .dram_sdqs3 = 0x00000028,
439 .dram_sdqs4 = 0x00000028,
440 .dram_sdqs5 = 0x00000028,
441 .dram_sdqs6 = 0x00000028,
442 .dram_sdqs7 = 0x00000028,
443 .dram_dqm0 = 0x00000028,
444 .dram_dqm1 = 0x00000028,
445 .dram_dqm2 = 0x00000028,
446 .dram_dqm3 = 0x00000028,
447 .dram_dqm4 = 0x00000028,
448 .dram_dqm5 = 0x00000028,
449 .dram_dqm6 = 0x00000028,
450 .dram_dqm7 = 0x00000028,
451 };
452
453 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
454 .grp_ddr_type = 0x000C0000,
455 .grp_ddrmode_ctl = 0x00020000,
456 .grp_ddrpke = 0x00000000,
457 .grp_addds = IMX6Q_DRIVE_STRENGTH,
458 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
459 .grp_ddrmode = 0x00020000,
460 .grp_b0ds = 0x00000028,
461 .grp_b1ds = 0x00000028,
462 .grp_b2ds = 0x00000028,
463 .grp_b3ds = 0x00000028,
464 .grp_b4ds = 0x00000028,
465 .grp_b5ds = 0x00000028,
466 .grp_b6ds = 0x00000028,
467 .grp_b7ds = 0x00000028,
468 };
469
470 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
471 .p0_mpwldectrl0 = 0x00110011,
472 .p0_mpwldectrl1 = 0x00240024,
473 .p1_mpwldectrl0 = 0x00260038,
474 .p1_mpwldectrl1 = 0x002C0038,
475 .p0_mpdgctrl0 = 0x03400350,
476 .p0_mpdgctrl1 = 0x03440340,
477 .p1_mpdgctrl0 = 0x034C0354,
478 .p1_mpdgctrl1 = 0x035C033C,
479 .p0_mprddlctl = 0x322A2A2A,
480 .p1_mprddlctl = 0x302C2834,
481 .p0_mpwrdlctl = 0x34303834,
482 .p1_mpwrdlctl = 0x422A3E36,
483 };
484
485 /* Index in RAM Chip array */
486 enum {
487 RAM_MT64K,
488 RAM_MT128K,
489 RAM_MT256K
490 };
491
492 static struct mx6_ddr3_cfg mt41k_xx[] = {
493 /* MT41K64M16JT-125 (1Gb density) */
494 {
495 .mem_speed = 1600,
496 .density = 1,
497 .width = 16,
498 .banks = 8,
499 .rowaddr = 13,
500 .coladdr = 10,
501 .pagesz = 2,
502 .trcd = 1375,
503 .trcmin = 4875,
504 .trasmin = 3500,
505 .SRT = 1,
506 },
507
508 /* MT41K256M16JT-125 (2Gb density) */
509 {
510 .mem_speed = 1600,
511 .density = 2,
512 .width = 16,
513 .banks = 8,
514 .rowaddr = 14,
515 .coladdr = 10,
516 .pagesz = 2,
517 .trcd = 1375,
518 .trcmin = 4875,
519 .trasmin = 3500,
520 .SRT = 1,
521 },
522
523 /* MT41K256M16JT-125 (4Gb density) */
524 {
525 .mem_speed = 1600,
526 .density = 4,
527 .width = 16,
528 .banks = 8,
529 .rowaddr = 15,
530 .coladdr = 10,
531 .pagesz = 2,
532 .trcd = 1375,
533 .trcmin = 4875,
534 .trasmin = 3500,
535 .SRT = 1,
536 }
537 };
538
ccgr_init(void)539 static void ccgr_init(void)
540 {
541 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
542
543 writel(0x00C03F3F, &ccm->CCGR0);
544 writel(0x0030FC03, &ccm->CCGR1);
545 writel(0x0FFFC000, &ccm->CCGR2);
546 writel(0x3FF00000, &ccm->CCGR3);
547 writel(0x00FFF300, &ccm->CCGR4);
548 writel(0x0F0000C3, &ccm->CCGR5);
549 writel(0x000003FF, &ccm->CCGR6);
550 }
551
spl_dram_init(struct mx6_ddr_sysinfo * sysinfo,struct mx6_ddr3_cfg * mem_ddr)552 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
553 struct mx6_ddr3_cfg *mem_ddr)
554 {
555 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
556 mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
557 }
558
board_mmc_init(bd_t * bis)559 int board_mmc_init(bd_t *bis)
560 {
561 if (spl_boot_device() == BOOT_DEVICE_SPI)
562 printf("MMC SEtup, Boot SPI");
563
564 SETUP_IOMUX_PADS(usdhc3_pads);
565 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
566 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
567 usdhc_cfg[0].max_bus_width = 4;
568 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
569
570 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
571 }
572
573
board_boot_order(u32 * spl_boot_list)574 void board_boot_order(u32 *spl_boot_list)
575 {
576 spl_boot_list[0] = spl_boot_device();
577 printf("Boot device %x\n", spl_boot_list[0]);
578 switch (spl_boot_list[0]) {
579 case BOOT_DEVICE_SPI:
580 spl_boot_list[1] = BOOT_DEVICE_UART;
581 break;
582 case BOOT_DEVICE_MMC1:
583 spl_boot_list[1] = BOOT_DEVICE_SPI;
584 spl_boot_list[2] = BOOT_DEVICE_UART;
585 break;
586 default:
587 printf("Boot device %x\n", spl_boot_list[0]);
588 }
589 }
590
591 /*
592 * This is used because get_ram_size() does not
593 * take care of cache, resulting a wrong size
594 * pfla02 has just 1, 2 or 4 GB option
595 * Function checks for mirrors in the first CS
596 */
597 #define RAM_TEST_PATTERN 0xaa5555aa
598 #define MIN_BANK_SIZE (512 * 1024 * 1024)
599
pfla02_detect_chiptype(void)600 static unsigned int pfla02_detect_chiptype(void)
601 {
602 u32 *p, *p1;
603 unsigned int offset = MIN_BANK_SIZE;
604 int i;
605
606 for (i = 0; i < 2; i++) {
607 p = (u32 *)PHYS_SDRAM;
608 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
609
610 *p1 = 0;
611 *p = RAM_TEST_PATTERN;
612
613 /*
614 * This is required to detect mirroring
615 * else we read back values from cache
616 */
617 flush_dcache_all();
618
619 if (*p == *p1)
620 return i;
621 }
622 return RAM_MT256K;
623 }
624
board_init_f(ulong dummy)625 void board_init_f(ulong dummy)
626 {
627 unsigned int ramchip;
628
629 struct mx6_ddr_sysinfo sysinfo = {
630 /* width of data bus:0=16,1=32,2=64 */
631 .dsize = 2,
632 /* config for full 4GB range so that get_mem_size() works */
633 .cs_density = 32, /* 512 MB */
634 /* single chip select */
635 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
636 .ncs = 1,
637 #else
638 .ncs = 2,
639 #endif
640 .cs1_mirror = 1,
641 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
642 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
643 .walat = 1, /* Write additional latency */
644 .ralat = 5, /* Read additional latency */
645 .mif3_mode = 3, /* Command prediction working mode */
646 .bi_on = 1, /* Bank interleaving enabled */
647 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
648 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
649 .ddr_type = DDR_TYPE_DDR3,
650 .refsel = 1, /* Refresh cycles at 32KHz */
651 .refr = 7, /* 8 refresh commands per refresh cycle */
652 };
653
654 #ifdef CONFIG_CMD_NAND
655 /* Enable NAND */
656 setup_gpmi_nand();
657 #endif
658
659 /* setup clock gating */
660 ccgr_init();
661
662 /* setup AIPS and disable watchdog */
663 arch_cpu_init();
664
665 /* setup AXI */
666 gpr_init();
667
668 board_early_init_f();
669
670 /* setup GP timer */
671 timer_init();
672
673 /* UART clocks enabled and gd valid - init serial console */
674 preloader_console_init();
675
676 setup_spi();
677
678 setup_gpios();
679
680 /* DDR initialization */
681 spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
682 ramchip = pfla02_detect_chiptype();
683 debug("Detected chip %d\n", ramchip);
684 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
685 switch (ramchip) {
686 case RAM_MT64K:
687 sysinfo.cs_density = 6;
688 break;
689 case RAM_MT128K:
690 sysinfo.cs_density = 10;
691 break;
692 case RAM_MT256K:
693 sysinfo.cs_density = 18;
694 break;
695 }
696 #endif
697 spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
698
699 /* Clear the BSS. */
700 memset(__bss_start, 0, __bss_end - __bss_start);
701
702 phyflex_err006282_workaround();
703
704 /* load/boot image from boot device */
705 board_init_r(NULL, 0);
706 }
707 #endif
708