1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
79 MODULE_LICENSE("Dual BSD/GPL");
80 
81 unsigned int mlx5_core_debug_mask;
82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
84 
85 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
86 module_param_named(prof_sel, prof_sel, uint, 0444);
87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
88 
89 static u32 sw_owner_id[4];
90 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
91 static DEFINE_IDA(sw_vhca_ida);
92 
93 enum {
94 	MLX5_ATOMIC_REQ_MODE_BE = 0x0,
95 	MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
96 };
97 
98 #define LOG_MAX_SUPPORTED_QPS 0xff
99 
100 static struct mlx5_profile profile[] = {
101 	[0] = {
102 		.mask           = 0,
103 		.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
104 	},
105 	[1] = {
106 		.mask		= MLX5_PROF_MASK_QP_SIZE,
107 		.log_max_qp	= 12,
108 		.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
109 
110 	},
111 	[2] = {
112 		.mask		= MLX5_PROF_MASK_QP_SIZE |
113 				  MLX5_PROF_MASK_MR_CACHE,
114 		.log_max_qp	= LOG_MAX_SUPPORTED_QPS,
115 		.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
116 		.mr_cache[0]	= {
117 			.size	= 500,
118 			.limit	= 250
119 		},
120 		.mr_cache[1]	= {
121 			.size	= 500,
122 			.limit	= 250
123 		},
124 		.mr_cache[2]	= {
125 			.size	= 500,
126 			.limit	= 250
127 		},
128 		.mr_cache[3]	= {
129 			.size	= 500,
130 			.limit	= 250
131 		},
132 		.mr_cache[4]	= {
133 			.size	= 500,
134 			.limit	= 250
135 		},
136 		.mr_cache[5]	= {
137 			.size	= 500,
138 			.limit	= 250
139 		},
140 		.mr_cache[6]	= {
141 			.size	= 500,
142 			.limit	= 250
143 		},
144 		.mr_cache[7]	= {
145 			.size	= 500,
146 			.limit	= 250
147 		},
148 		.mr_cache[8]	= {
149 			.size	= 500,
150 			.limit	= 250
151 		},
152 		.mr_cache[9]	= {
153 			.size	= 500,
154 			.limit	= 250
155 		},
156 		.mr_cache[10]	= {
157 			.size	= 500,
158 			.limit	= 250
159 		},
160 		.mr_cache[11]	= {
161 			.size	= 500,
162 			.limit	= 250
163 		},
164 		.mr_cache[12]	= {
165 			.size	= 64,
166 			.limit	= 32
167 		},
168 		.mr_cache[13]	= {
169 			.size	= 32,
170 			.limit	= 16
171 		},
172 		.mr_cache[14]	= {
173 			.size	= 16,
174 			.limit	= 8
175 		},
176 		.mr_cache[15]	= {
177 			.size	= 8,
178 			.limit	= 4
179 		},
180 	},
181 	[3] = {
182 		.mask		= MLX5_PROF_MASK_QP_SIZE,
183 		.log_max_qp	= LOG_MAX_SUPPORTED_QPS,
184 		.num_cmd_caches = 0,
185 	},
186 };
187 
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
189 			u32 warn_time_mili)
190 {
191 	unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
192 	unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
193 	u32 fw_initializing;
194 	int err = 0;
195 
196 	do {
197 		fw_initializing = ioread32be(&dev->iseg->initializing);
198 		if (!(fw_initializing >> 31))
199 			break;
200 		if (time_after(jiffies, end) ||
201 		    test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
202 			err = -EBUSY;
203 			break;
204 		}
205 		if (warn_time_mili && time_after(jiffies, warn)) {
206 			mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n",
207 				       jiffies_to_msecs(end - warn) / 1000, fw_initializing);
208 			warn = jiffies + msecs_to_jiffies(warn_time_mili);
209 		}
210 		msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
211 	} while (true);
212 
213 	return err;
214 }
215 
mlx5_set_driver_version(struct mlx5_core_dev * dev)216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
217 {
218 	int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
219 					      driver_version);
220 	u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
221 	int remaining_size = driver_ver_sz;
222 	char *string;
223 
224 	if (!MLX5_CAP_GEN(dev, driver_version))
225 		return;
226 
227 	string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
228 
229 	strncpy(string, "Linux", remaining_size);
230 
231 	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 	strncat(string, ",", remaining_size);
233 
234 	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235 	strncat(string, KBUILD_MODNAME, remaining_size);
236 
237 	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
238 	strncat(string, ",", remaining_size);
239 
240 	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
241 
242 	snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
243 		LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
244 		LINUX_VERSION_SUBLEVEL);
245 
246 	/*Send the command*/
247 	MLX5_SET(set_driver_version_in, in, opcode,
248 		 MLX5_CMD_OP_SET_DRIVER_VERSION);
249 
250 	mlx5_cmd_exec_in(dev, set_driver_version, in);
251 }
252 
set_dma_caps(struct pci_dev * pdev)253 static int set_dma_caps(struct pci_dev *pdev)
254 {
255 	int err;
256 
257 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
258 	if (err) {
259 		dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
260 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
261 		if (err) {
262 			dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
263 			return err;
264 		}
265 	}
266 
267 	dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
268 	return err;
269 }
270 
mlx5_pci_enable_device(struct mlx5_core_dev * dev)271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
272 {
273 	struct pci_dev *pdev = dev->pdev;
274 	int err = 0;
275 
276 	mutex_lock(&dev->pci_status_mutex);
277 	if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
278 		err = pci_enable_device(pdev);
279 		if (!err)
280 			dev->pci_status = MLX5_PCI_STATUS_ENABLED;
281 	}
282 	mutex_unlock(&dev->pci_status_mutex);
283 
284 	return err;
285 }
286 
mlx5_pci_disable_device(struct mlx5_core_dev * dev)287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
288 {
289 	struct pci_dev *pdev = dev->pdev;
290 
291 	mutex_lock(&dev->pci_status_mutex);
292 	if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
293 		pci_disable_device(pdev);
294 		dev->pci_status = MLX5_PCI_STATUS_DISABLED;
295 	}
296 	mutex_unlock(&dev->pci_status_mutex);
297 }
298 
request_bar(struct pci_dev * pdev)299 static int request_bar(struct pci_dev *pdev)
300 {
301 	int err = 0;
302 
303 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
304 		dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
305 		return -ENODEV;
306 	}
307 
308 	err = pci_request_regions(pdev, KBUILD_MODNAME);
309 	if (err)
310 		dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
311 
312 	return err;
313 }
314 
release_bar(struct pci_dev * pdev)315 static void release_bar(struct pci_dev *pdev)
316 {
317 	pci_release_regions(pdev);
318 }
319 
320 struct mlx5_reg_host_endianness {
321 	u8	he;
322 	u8      rsvd[15];
323 };
324 
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)325 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
326 {
327 	switch (size) {
328 	case 128:
329 		return 0;
330 	case 256:
331 		return 1;
332 	case 512:
333 		return 2;
334 	case 1024:
335 		return 3;
336 	case 2048:
337 		return 4;
338 	case 4096:
339 		return 5;
340 	default:
341 		mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
342 		return 0;
343 	}
344 }
345 
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)346 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
347 {
348 	mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
349 	dev->mlx5e_res.uplink_netdev = netdev;
350 	mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 					  netdev);
352 	mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)355 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
356 {
357 	mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
358 	mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
359 					  dev->mlx5e_res.uplink_netdev);
360 	mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
361 }
362 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
363 
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)364 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
365 {
366 	mlx5_blocking_notifier_call_chain(dev, event, data);
367 }
368 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
369 
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)370 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
371 			    enum mlx5_cap_mode cap_mode)
372 {
373 	u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
374 	int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
375 	void *out, *hca_caps;
376 	u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
377 	int err;
378 
379 	memset(in, 0, sizeof(in));
380 	out = kzalloc(out_sz, GFP_KERNEL);
381 	if (!out)
382 		return -ENOMEM;
383 
384 	MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
385 	MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
386 	err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
387 	if (err) {
388 		mlx5_core_warn(dev,
389 			       "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
390 			       cap_type, cap_mode, err);
391 		goto query_ex;
392 	}
393 
394 	hca_caps =  MLX5_ADDR_OF(query_hca_cap_out, out, capability);
395 
396 	switch (cap_mode) {
397 	case HCA_CAP_OPMOD_GET_MAX:
398 		memcpy(dev->caps.hca[cap_type]->max, hca_caps,
399 		       MLX5_UN_SZ_BYTES(hca_cap_union));
400 		break;
401 	case HCA_CAP_OPMOD_GET_CUR:
402 		memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
403 		       MLX5_UN_SZ_BYTES(hca_cap_union));
404 		break;
405 	default:
406 		mlx5_core_warn(dev,
407 			       "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
408 			       cap_type, cap_mode);
409 		err = -EINVAL;
410 		break;
411 	}
412 query_ex:
413 	kfree(out);
414 	return err;
415 }
416 
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)417 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
418 {
419 	int ret;
420 
421 	ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
422 	if (ret)
423 		return ret;
424 	return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
425 }
426 
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)427 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
428 {
429 	MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
430 	MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
431 	return mlx5_cmd_exec_in(dev, set_hca_cap, in);
432 }
433 
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)434 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
435 {
436 	void *set_hca_cap;
437 	int req_endianness;
438 	int err;
439 
440 	if (!MLX5_CAP_GEN(dev, atomic))
441 		return 0;
442 
443 	err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
444 	if (err)
445 		return err;
446 
447 	req_endianness =
448 		MLX5_CAP_ATOMIC(dev,
449 				supported_atomic_req_8B_endianness_mode_1);
450 
451 	if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
452 		return 0;
453 
454 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
455 
456 	/* Set requestor to host endianness */
457 	MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
458 		 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
459 
460 	return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
461 }
462 
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)463 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
464 {
465 	void *set_hca_cap;
466 	bool do_set = false;
467 	int err;
468 
469 	if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
470 	    !MLX5_CAP_GEN(dev, pg))
471 		return 0;
472 
473 	err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
474 	if (err)
475 		return err;
476 
477 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
478 	memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
479 	       MLX5_ST_SZ_BYTES(odp_cap));
480 
481 #define ODP_CAP_SET_MAX(dev, field)                                            \
482 	do {                                                                   \
483 		u32 _res = MLX5_CAP_ODP_MAX(dev, field);                       \
484 		if (_res) {                                                    \
485 			do_set = true;                                         \
486 			MLX5_SET(odp_cap, set_hca_cap, field, _res);           \
487 		}                                                              \
488 	} while (0)
489 
490 	ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
491 	ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
492 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
493 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
494 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
495 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
496 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
497 	ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
498 	ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
499 	ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
500 	ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
501 	ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
502 	ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
503 	ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
504 
505 	if (!do_set)
506 		return 0;
507 
508 	return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
509 }
510 
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)511 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
512 {
513 	struct devlink *devlink = priv_to_devlink(dev);
514 	union devlink_param_value val;
515 	int err;
516 
517 	err = devl_param_driverinit_value_get(devlink,
518 					      DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
519 					      &val);
520 	if (!err)
521 		return val.vu32;
522 	mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
523 	return err;
524 }
525 
mlx5_is_roce_on(struct mlx5_core_dev * dev)526 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
527 {
528 	struct devlink *devlink = priv_to_devlink(dev);
529 	union devlink_param_value val;
530 	int err;
531 
532 	err = devl_param_driverinit_value_get(devlink,
533 					      DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
534 					      &val);
535 
536 	if (!err)
537 		return val.vbool;
538 
539 	mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
540 	return MLX5_CAP_GEN(dev, roce);
541 }
542 EXPORT_SYMBOL(mlx5_is_roce_on);
543 
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)544 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
545 {
546 	void *set_hca_cap;
547 	int err;
548 
549 	if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
550 		return 0;
551 
552 	err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
553 	if (err)
554 		return err;
555 
556 	if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
557 	    !(dev->priv.sw_vhca_id > 0))
558 		return 0;
559 
560 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
561 				   capability);
562 	memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
563 	       MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
564 	MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
565 
566 	return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
567 }
568 
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)569 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
570 {
571 	struct mlx5_profile *prof = &dev->profile;
572 	void *set_hca_cap;
573 	int max_uc_list;
574 	int err;
575 
576 	err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
577 	if (err)
578 		return err;
579 
580 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
581 				   capability);
582 	memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
583 	       MLX5_ST_SZ_BYTES(cmd_hca_cap));
584 
585 	mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
586 		      mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
587 		      128);
588 	/* we limit the size of the pkey table to 128 entries for now */
589 	MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
590 		 to_fw_pkey_sz(dev, 128));
591 
592 	/* Check log_max_qp from HCA caps to set in current profile */
593 	if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
594 		prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
595 	} else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
596 		mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
597 			       prof->log_max_qp,
598 			       MLX5_CAP_GEN_MAX(dev, log_max_qp));
599 		prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
600 	}
601 	if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
602 		MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
603 			 prof->log_max_qp);
604 
605 	/* disable cmdif checksum */
606 	MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
607 
608 	/* Enable 4K UAR only when HCA supports it and page size is bigger
609 	 * than 4K.
610 	 */
611 	if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
612 		MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
613 
614 	MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
615 
616 	if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
617 		MLX5_SET(cmd_hca_cap,
618 			 set_hca_cap,
619 			 cache_line_128byte,
620 			 cache_line_size() >= 128 ? 1 : 0);
621 
622 	if (MLX5_CAP_GEN_MAX(dev, dct))
623 		MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
624 
625 	if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
626 		MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
627 	if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
628 		MLX5_SET(cmd_hca_cap, set_hca_cap,
629 			 pci_sync_for_fw_update_with_driver_unload, 1);
630 
631 	if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
632 		MLX5_SET(cmd_hca_cap,
633 			 set_hca_cap,
634 			 num_vhca_ports,
635 			 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
636 
637 	if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
638 		MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
639 
640 	if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
641 		MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
642 
643 	mlx5_vhca_state_cap_handle(dev, set_hca_cap);
644 
645 	if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
646 		MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
647 			 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
648 
649 	if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
650 		MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
651 			 mlx5_is_roce_on(dev));
652 
653 	max_uc_list = max_uc_list_get_devlink_param(dev);
654 	if (max_uc_list > 0)
655 		MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
656 			 ilog2(max_uc_list));
657 
658 	return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
659 }
660 
661 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
662  * boot process.
663  * In case RoCE cap is writable in FW and user/devlink requested to change the
664  * cap, we are yet to query the final state of the above cap.
665  * Hence, the need for this function.
666  *
667  * Returns
668  * True:
669  * 1) RoCE cap is read only in FW and already disabled
670  * OR:
671  * 2) RoCE cap is writable in FW and user/devlink requested it off.
672  *
673  * In any other case, return False.
674  */
is_roce_fw_disabled(struct mlx5_core_dev * dev)675 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
676 {
677 	return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
678 		(!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
679 }
680 
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)681 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
682 {
683 	void *set_hca_cap;
684 	int err;
685 
686 	if (is_roce_fw_disabled(dev))
687 		return 0;
688 
689 	err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
690 	if (err)
691 		return err;
692 
693 	if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
694 	    !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
695 		return 0;
696 
697 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
698 	memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
699 	       MLX5_ST_SZ_BYTES(roce_cap));
700 	MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
701 
702 	if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
703 		MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
704 
705 	err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
706 	return err;
707 }
708 
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)709 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
710 					 void *set_ctx)
711 {
712 	void *set_hca_cap;
713 	int err;
714 
715 	if (!MLX5_CAP_GEN(dev, port_selection_cap))
716 		return 0;
717 
718 	err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
719 	if (err)
720 		return err;
721 
722 	if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
723 	    !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
724 		return 0;
725 
726 	set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
727 	memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
728 	       MLX5_ST_SZ_BYTES(port_selection_cap));
729 	MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
730 
731 	err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
732 
733 	return err;
734 }
735 
set_hca_cap(struct mlx5_core_dev * dev)736 static int set_hca_cap(struct mlx5_core_dev *dev)
737 {
738 	int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
739 	void *set_ctx;
740 	int err;
741 
742 	set_ctx = kzalloc(set_sz, GFP_KERNEL);
743 	if (!set_ctx)
744 		return -ENOMEM;
745 
746 	err = handle_hca_cap(dev, set_ctx);
747 	if (err) {
748 		mlx5_core_err(dev, "handle_hca_cap failed\n");
749 		goto out;
750 	}
751 
752 	memset(set_ctx, 0, set_sz);
753 	err = handle_hca_cap_atomic(dev, set_ctx);
754 	if (err) {
755 		mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
756 		goto out;
757 	}
758 
759 	memset(set_ctx, 0, set_sz);
760 	err = handle_hca_cap_odp(dev, set_ctx);
761 	if (err) {
762 		mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
763 		goto out;
764 	}
765 
766 	memset(set_ctx, 0, set_sz);
767 	err = handle_hca_cap_roce(dev, set_ctx);
768 	if (err) {
769 		mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
770 		goto out;
771 	}
772 
773 	memset(set_ctx, 0, set_sz);
774 	err = handle_hca_cap_2(dev, set_ctx);
775 	if (err) {
776 		mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
777 		goto out;
778 	}
779 
780 	memset(set_ctx, 0, set_sz);
781 	err = handle_hca_cap_port_selection(dev, set_ctx);
782 	if (err) {
783 		mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
784 		goto out;
785 	}
786 
787 out:
788 	kfree(set_ctx);
789 	return err;
790 }
791 
set_hca_ctrl(struct mlx5_core_dev * dev)792 static int set_hca_ctrl(struct mlx5_core_dev *dev)
793 {
794 	struct mlx5_reg_host_endianness he_in;
795 	struct mlx5_reg_host_endianness he_out;
796 	int err;
797 
798 	if (!mlx5_core_is_pf(dev))
799 		return 0;
800 
801 	memset(&he_in, 0, sizeof(he_in));
802 	he_in.he = MLX5_SET_HOST_ENDIANNESS;
803 	err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
804 					&he_out, sizeof(he_out),
805 					MLX5_REG_HOST_ENDIANNESS, 0, 1);
806 	return err;
807 }
808 
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)809 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
810 {
811 	int ret = 0;
812 
813 	/* Disable local_lb by default */
814 	if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
815 		ret = mlx5_nic_vport_update_local_lb(dev, false);
816 
817 	return ret;
818 }
819 
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)820 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
821 {
822 	u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
823 
824 	MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
825 	MLX5_SET(enable_hca_in, in, function_id, func_id);
826 	MLX5_SET(enable_hca_in, in, embedded_cpu_function,
827 		 dev->caps.embedded_cpu);
828 	return mlx5_cmd_exec_in(dev, enable_hca, in);
829 }
830 
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)831 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
832 {
833 	u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
834 
835 	MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
836 	MLX5_SET(disable_hca_in, in, function_id, func_id);
837 	MLX5_SET(enable_hca_in, in, embedded_cpu_function,
838 		 dev->caps.embedded_cpu);
839 	return mlx5_cmd_exec_in(dev, disable_hca, in);
840 }
841 
mlx5_core_set_issi(struct mlx5_core_dev * dev)842 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
843 {
844 	u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
845 	u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
846 	u32 sup_issi;
847 	int err;
848 
849 	MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
850 	err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
851 	if (err) {
852 		u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
853 		u8 status = MLX5_GET(query_issi_out, query_out, status);
854 
855 		if (!status || syndrome == MLX5_DRIVER_SYND) {
856 			mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
857 				      err, status, syndrome);
858 			return err;
859 		}
860 
861 		mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
862 		dev->issi = 0;
863 		return 0;
864 	}
865 
866 	sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
867 
868 	if (sup_issi & (1 << 1)) {
869 		u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
870 
871 		MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
872 		MLX5_SET(set_issi_in, set_in, current_issi, 1);
873 		err = mlx5_cmd_exec_in(dev, set_issi, set_in);
874 		if (err) {
875 			mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
876 				      err);
877 			return err;
878 		}
879 
880 		dev->issi = 1;
881 
882 		return 0;
883 	} else if (sup_issi & (1 << 0) || !sup_issi) {
884 		return 0;
885 	}
886 
887 	return -EOPNOTSUPP;
888 }
889 
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)890 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
891 			 const struct pci_device_id *id)
892 {
893 	int err = 0;
894 
895 	mutex_init(&dev->pci_status_mutex);
896 	pci_set_drvdata(dev->pdev, dev);
897 
898 	dev->bar_addr = pci_resource_start(pdev, 0);
899 
900 	err = mlx5_pci_enable_device(dev);
901 	if (err) {
902 		mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
903 		return err;
904 	}
905 
906 	err = request_bar(pdev);
907 	if (err) {
908 		mlx5_core_err(dev, "error requesting BARs, aborting\n");
909 		goto err_disable;
910 	}
911 
912 	pci_set_master(pdev);
913 
914 	err = set_dma_caps(pdev);
915 	if (err) {
916 		mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
917 		goto err_clr_master;
918 	}
919 
920 	if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
921 	    pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
922 	    pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
923 		mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
924 
925 	dev->iseg_base = dev->bar_addr;
926 	dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
927 	if (!dev->iseg) {
928 		err = -ENOMEM;
929 		mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
930 		goto err_clr_master;
931 	}
932 
933 	mlx5_pci_vsc_init(dev);
934 	return 0;
935 
936 err_clr_master:
937 	release_bar(dev->pdev);
938 err_disable:
939 	mlx5_pci_disable_device(dev);
940 	return err;
941 }
942 
mlx5_pci_close(struct mlx5_core_dev * dev)943 static void mlx5_pci_close(struct mlx5_core_dev *dev)
944 {
945 	/* health work might still be active, and it needs pci bar in
946 	 * order to know the NIC state. Therefore, drain the health WQ
947 	 * before removing the pci bars
948 	 */
949 	mlx5_drain_health_wq(dev);
950 	iounmap(dev->iseg);
951 	release_bar(dev->pdev);
952 	mlx5_pci_disable_device(dev);
953 }
954 
mlx5_init_once(struct mlx5_core_dev * dev)955 static int mlx5_init_once(struct mlx5_core_dev *dev)
956 {
957 	int err;
958 
959 	dev->priv.devc = mlx5_devcom_register_device(dev);
960 	if (IS_ERR(dev->priv.devc))
961 		mlx5_core_warn(dev, "failed to register devcom device %ld\n",
962 			       PTR_ERR(dev->priv.devc));
963 
964 	err = mlx5_query_board_id(dev);
965 	if (err) {
966 		mlx5_core_err(dev, "query board id failed\n");
967 		goto err_devcom;
968 	}
969 
970 	err = mlx5_irq_table_init(dev);
971 	if (err) {
972 		mlx5_core_err(dev, "failed to initialize irq table\n");
973 		goto err_devcom;
974 	}
975 
976 	err = mlx5_eq_table_init(dev);
977 	if (err) {
978 		mlx5_core_err(dev, "failed to initialize eq\n");
979 		goto err_irq_cleanup;
980 	}
981 
982 	err = mlx5_events_init(dev);
983 	if (err) {
984 		mlx5_core_err(dev, "failed to initialize events\n");
985 		goto err_eq_cleanup;
986 	}
987 
988 	err = mlx5_fw_reset_init(dev);
989 	if (err) {
990 		mlx5_core_err(dev, "failed to initialize fw reset events\n");
991 		goto err_events_cleanup;
992 	}
993 
994 	mlx5_cq_debugfs_init(dev);
995 
996 	mlx5_init_reserved_gids(dev);
997 
998 	mlx5_init_clock(dev);
999 
1000 	dev->vxlan = mlx5_vxlan_create(dev);
1001 	dev->geneve = mlx5_geneve_create(dev);
1002 
1003 	err = mlx5_init_rl_table(dev);
1004 	if (err) {
1005 		mlx5_core_err(dev, "Failed to init rate limiting\n");
1006 		goto err_tables_cleanup;
1007 	}
1008 
1009 	err = mlx5_mpfs_init(dev);
1010 	if (err) {
1011 		mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1012 		goto err_rl_cleanup;
1013 	}
1014 
1015 	err = mlx5_sriov_init(dev);
1016 	if (err) {
1017 		mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1018 		goto err_mpfs_cleanup;
1019 	}
1020 
1021 	err = mlx5_eswitch_init(dev);
1022 	if (err) {
1023 		mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1024 		goto err_sriov_cleanup;
1025 	}
1026 
1027 	err = mlx5_fpga_init(dev);
1028 	if (err) {
1029 		mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1030 		goto err_eswitch_cleanup;
1031 	}
1032 
1033 	err = mlx5_vhca_event_init(dev);
1034 	if (err) {
1035 		mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1036 		goto err_fpga_cleanup;
1037 	}
1038 
1039 	err = mlx5_sf_hw_table_init(dev);
1040 	if (err) {
1041 		mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1042 		goto err_sf_hw_table_cleanup;
1043 	}
1044 
1045 	err = mlx5_sf_table_init(dev);
1046 	if (err) {
1047 		mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1048 		goto err_sf_table_cleanup;
1049 	}
1050 
1051 	err = mlx5_fs_core_alloc(dev);
1052 	if (err) {
1053 		mlx5_core_err(dev, "Failed to alloc flow steering\n");
1054 		goto err_fs;
1055 	}
1056 
1057 	dev->dm = mlx5_dm_create(dev);
1058 	if (IS_ERR(dev->dm))
1059 		mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
1060 
1061 	dev->tracer = mlx5_fw_tracer_create(dev);
1062 	dev->hv_vhca = mlx5_hv_vhca_create(dev);
1063 	dev->rsc_dump = mlx5_rsc_dump_create(dev);
1064 
1065 	return 0;
1066 
1067 err_fs:
1068 	mlx5_sf_table_cleanup(dev);
1069 err_sf_table_cleanup:
1070 	mlx5_sf_hw_table_cleanup(dev);
1071 err_sf_hw_table_cleanup:
1072 	mlx5_vhca_event_cleanup(dev);
1073 err_fpga_cleanup:
1074 	mlx5_fpga_cleanup(dev);
1075 err_eswitch_cleanup:
1076 	mlx5_eswitch_cleanup(dev->priv.eswitch);
1077 err_sriov_cleanup:
1078 	mlx5_sriov_cleanup(dev);
1079 err_mpfs_cleanup:
1080 	mlx5_mpfs_cleanup(dev);
1081 err_rl_cleanup:
1082 	mlx5_cleanup_rl_table(dev);
1083 err_tables_cleanup:
1084 	mlx5_geneve_destroy(dev->geneve);
1085 	mlx5_vxlan_destroy(dev->vxlan);
1086 	mlx5_cleanup_clock(dev);
1087 	mlx5_cleanup_reserved_gids(dev);
1088 	mlx5_cq_debugfs_cleanup(dev);
1089 	mlx5_fw_reset_cleanup(dev);
1090 err_events_cleanup:
1091 	mlx5_events_cleanup(dev);
1092 err_eq_cleanup:
1093 	mlx5_eq_table_cleanup(dev);
1094 err_irq_cleanup:
1095 	mlx5_irq_table_cleanup(dev);
1096 err_devcom:
1097 	mlx5_devcom_unregister_device(dev->priv.devc);
1098 
1099 	return err;
1100 }
1101 
mlx5_cleanup_once(struct mlx5_core_dev * dev)1102 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1103 {
1104 	mlx5_rsc_dump_destroy(dev);
1105 	mlx5_hv_vhca_destroy(dev->hv_vhca);
1106 	mlx5_fw_tracer_destroy(dev->tracer);
1107 	mlx5_dm_cleanup(dev);
1108 	mlx5_fs_core_free(dev);
1109 	mlx5_sf_table_cleanup(dev);
1110 	mlx5_sf_hw_table_cleanup(dev);
1111 	mlx5_vhca_event_cleanup(dev);
1112 	mlx5_fpga_cleanup(dev);
1113 	mlx5_eswitch_cleanup(dev->priv.eswitch);
1114 	mlx5_sriov_cleanup(dev);
1115 	mlx5_mpfs_cleanup(dev);
1116 	mlx5_cleanup_rl_table(dev);
1117 	mlx5_geneve_destroy(dev->geneve);
1118 	mlx5_vxlan_destroy(dev->vxlan);
1119 	mlx5_cleanup_clock(dev);
1120 	mlx5_cleanup_reserved_gids(dev);
1121 	mlx5_cq_debugfs_cleanup(dev);
1122 	mlx5_fw_reset_cleanup(dev);
1123 	mlx5_events_cleanup(dev);
1124 	mlx5_eq_table_cleanup(dev);
1125 	mlx5_irq_table_cleanup(dev);
1126 	mlx5_devcom_unregister_device(dev->priv.devc);
1127 }
1128 
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1129 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1130 {
1131 	int err;
1132 
1133 	mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1134 		       fw_rev_min(dev), fw_rev_sub(dev));
1135 
1136 	/* Only PFs hold the relevant PCIe information for this query */
1137 	if (mlx5_core_is_pf(dev))
1138 		pcie_print_link_status(dev->pdev);
1139 
1140 	/* wait for firmware to accept initialization segments configurations
1141 	 */
1142 	err = wait_fw_init(dev, timeout,
1143 			   mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1144 	if (err) {
1145 		mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1146 			      timeout);
1147 		return err;
1148 	}
1149 
1150 	err = mlx5_cmd_enable(dev);
1151 	if (err) {
1152 		mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1153 		return err;
1154 	}
1155 
1156 	mlx5_tout_query_iseg(dev);
1157 
1158 	err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1159 	if (err) {
1160 		mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1161 			      mlx5_tout_ms(dev, FW_INIT));
1162 		goto err_cmd_cleanup;
1163 	}
1164 
1165 	dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1166 	mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1167 
1168 	mlx5_start_health_poll(dev);
1169 
1170 	err = mlx5_core_enable_hca(dev, 0);
1171 	if (err) {
1172 		mlx5_core_err(dev, "enable hca failed\n");
1173 		goto stop_health_poll;
1174 	}
1175 
1176 	err = mlx5_core_set_issi(dev);
1177 	if (err) {
1178 		mlx5_core_err(dev, "failed to set issi\n");
1179 		goto err_disable_hca;
1180 	}
1181 
1182 	err = mlx5_satisfy_startup_pages(dev, 1);
1183 	if (err) {
1184 		mlx5_core_err(dev, "failed to allocate boot pages\n");
1185 		goto err_disable_hca;
1186 	}
1187 
1188 	err = mlx5_tout_query_dtor(dev);
1189 	if (err) {
1190 		mlx5_core_err(dev, "failed to read dtor\n");
1191 		goto reclaim_boot_pages;
1192 	}
1193 
1194 	return 0;
1195 
1196 reclaim_boot_pages:
1197 	mlx5_reclaim_startup_pages(dev);
1198 err_disable_hca:
1199 	mlx5_core_disable_hca(dev, 0);
1200 stop_health_poll:
1201 	mlx5_stop_health_poll(dev, boot);
1202 err_cmd_cleanup:
1203 	mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1204 	mlx5_cmd_disable(dev);
1205 
1206 	return err;
1207 }
1208 
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1209 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1210 {
1211 	mlx5_reclaim_startup_pages(dev);
1212 	mlx5_core_disable_hca(dev, 0);
1213 	mlx5_stop_health_poll(dev, boot);
1214 	mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1215 	mlx5_cmd_disable(dev);
1216 }
1217 
mlx5_function_open(struct mlx5_core_dev * dev)1218 static int mlx5_function_open(struct mlx5_core_dev *dev)
1219 {
1220 	int err;
1221 
1222 	err = set_hca_ctrl(dev);
1223 	if (err) {
1224 		mlx5_core_err(dev, "set_hca_ctrl failed\n");
1225 		return err;
1226 	}
1227 
1228 	err = set_hca_cap(dev);
1229 	if (err) {
1230 		mlx5_core_err(dev, "set_hca_cap failed\n");
1231 		return err;
1232 	}
1233 
1234 	err = mlx5_satisfy_startup_pages(dev, 0);
1235 	if (err) {
1236 		mlx5_core_err(dev, "failed to allocate init pages\n");
1237 		return err;
1238 	}
1239 
1240 	err = mlx5_cmd_init_hca(dev, sw_owner_id);
1241 	if (err) {
1242 		mlx5_core_err(dev, "init hca failed\n");
1243 		return err;
1244 	}
1245 
1246 	mlx5_set_driver_version(dev);
1247 
1248 	err = mlx5_query_hca_caps(dev);
1249 	if (err) {
1250 		mlx5_core_err(dev, "query hca failed\n");
1251 		return err;
1252 	}
1253 	mlx5_start_health_fw_log_up(dev);
1254 	return 0;
1255 }
1256 
mlx5_function_close(struct mlx5_core_dev * dev)1257 static int mlx5_function_close(struct mlx5_core_dev *dev)
1258 {
1259 	int err;
1260 
1261 	err = mlx5_cmd_teardown_hca(dev);
1262 	if (err) {
1263 		mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1264 		return err;
1265 	}
1266 
1267 	return 0;
1268 }
1269 
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1270 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1271 {
1272 	int err;
1273 
1274 	err = mlx5_function_enable(dev, boot, timeout);
1275 	if (err)
1276 		return err;
1277 
1278 	err = mlx5_function_open(dev);
1279 	if (err)
1280 		mlx5_function_disable(dev, boot);
1281 	return err;
1282 }
1283 
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1284 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1285 {
1286 	int err = mlx5_function_close(dev);
1287 
1288 	if (!err)
1289 		mlx5_function_disable(dev, boot);
1290 	else
1291 		mlx5_stop_health_poll(dev, boot);
1292 
1293 	return err;
1294 }
1295 
mlx5_load(struct mlx5_core_dev * dev)1296 static int mlx5_load(struct mlx5_core_dev *dev)
1297 {
1298 	int err;
1299 
1300 	dev->priv.uar = mlx5_get_uars_page(dev);
1301 	if (IS_ERR(dev->priv.uar)) {
1302 		mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1303 		err = PTR_ERR(dev->priv.uar);
1304 		return err;
1305 	}
1306 
1307 	mlx5_events_start(dev);
1308 	mlx5_pagealloc_start(dev);
1309 
1310 	err = mlx5_irq_table_create(dev);
1311 	if (err) {
1312 		mlx5_core_err(dev, "Failed to alloc IRQs\n");
1313 		goto err_irq_table;
1314 	}
1315 
1316 	err = mlx5_eq_table_create(dev);
1317 	if (err) {
1318 		mlx5_core_err(dev, "Failed to create EQs\n");
1319 		goto err_eq_table;
1320 	}
1321 
1322 	err = mlx5_fw_tracer_init(dev->tracer);
1323 	if (err) {
1324 		mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1325 		mlx5_fw_tracer_destroy(dev->tracer);
1326 		dev->tracer = NULL;
1327 	}
1328 
1329 	mlx5_fw_reset_events_start(dev);
1330 	mlx5_hv_vhca_init(dev->hv_vhca);
1331 
1332 	err = mlx5_rsc_dump_init(dev);
1333 	if (err) {
1334 		mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1335 		mlx5_rsc_dump_destroy(dev);
1336 		dev->rsc_dump = NULL;
1337 	}
1338 
1339 	err = mlx5_fpga_device_start(dev);
1340 	if (err) {
1341 		mlx5_core_err(dev, "fpga device start failed %d\n", err);
1342 		goto err_fpga_start;
1343 	}
1344 
1345 	err = mlx5_fs_core_init(dev);
1346 	if (err) {
1347 		mlx5_core_err(dev, "Failed to init flow steering\n");
1348 		goto err_fs;
1349 	}
1350 
1351 	err = mlx5_core_set_hca_defaults(dev);
1352 	if (err) {
1353 		mlx5_core_err(dev, "Failed to set hca defaults\n");
1354 		goto err_set_hca;
1355 	}
1356 
1357 	mlx5_vhca_event_start(dev);
1358 
1359 	err = mlx5_sf_hw_table_create(dev);
1360 	if (err) {
1361 		mlx5_core_err(dev, "sf table create failed %d\n", err);
1362 		goto err_vhca;
1363 	}
1364 
1365 	err = mlx5_ec_init(dev);
1366 	if (err) {
1367 		mlx5_core_err(dev, "Failed to init embedded CPU\n");
1368 		goto err_ec;
1369 	}
1370 
1371 	mlx5_lag_add_mdev(dev);
1372 	err = mlx5_sriov_attach(dev);
1373 	if (err) {
1374 		mlx5_core_err(dev, "sriov init failed %d\n", err);
1375 		goto err_sriov;
1376 	}
1377 
1378 	mlx5_sf_dev_table_create(dev);
1379 
1380 	err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1381 	if (err)
1382 		goto err_traps_reg;
1383 
1384 	return 0;
1385 
1386 err_traps_reg:
1387 	mlx5_sf_dev_table_destroy(dev);
1388 	mlx5_sriov_detach(dev);
1389 err_sriov:
1390 	mlx5_lag_remove_mdev(dev);
1391 	mlx5_ec_cleanup(dev);
1392 err_ec:
1393 	mlx5_sf_hw_table_destroy(dev);
1394 err_vhca:
1395 	mlx5_vhca_event_stop(dev);
1396 err_set_hca:
1397 	mlx5_fs_core_cleanup(dev);
1398 err_fs:
1399 	mlx5_fpga_device_stop(dev);
1400 err_fpga_start:
1401 	mlx5_rsc_dump_cleanup(dev);
1402 	mlx5_hv_vhca_cleanup(dev->hv_vhca);
1403 	mlx5_fw_reset_events_stop(dev);
1404 	mlx5_fw_tracer_cleanup(dev->tracer);
1405 	mlx5_eq_table_destroy(dev);
1406 err_eq_table:
1407 	mlx5_irq_table_destroy(dev);
1408 err_irq_table:
1409 	mlx5_pagealloc_stop(dev);
1410 	mlx5_events_stop(dev);
1411 	mlx5_put_uars_page(dev, dev->priv.uar);
1412 	return err;
1413 }
1414 
mlx5_unload(struct mlx5_core_dev * dev)1415 static void mlx5_unload(struct mlx5_core_dev *dev)
1416 {
1417 	mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1418 	mlx5_sf_dev_table_destroy(dev);
1419 	mlx5_eswitch_disable(dev->priv.eswitch);
1420 	mlx5_sriov_detach(dev);
1421 	mlx5_lag_remove_mdev(dev);
1422 	mlx5_ec_cleanup(dev);
1423 	mlx5_sf_hw_table_destroy(dev);
1424 	mlx5_vhca_event_stop(dev);
1425 	mlx5_fs_core_cleanup(dev);
1426 	mlx5_fpga_device_stop(dev);
1427 	mlx5_rsc_dump_cleanup(dev);
1428 	mlx5_hv_vhca_cleanup(dev->hv_vhca);
1429 	mlx5_fw_reset_events_stop(dev);
1430 	mlx5_fw_tracer_cleanup(dev->tracer);
1431 	mlx5_eq_table_destroy(dev);
1432 	mlx5_irq_table_destroy(dev);
1433 	mlx5_pagealloc_stop(dev);
1434 	mlx5_events_stop(dev);
1435 	mlx5_put_uars_page(dev, dev->priv.uar);
1436 }
1437 
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1438 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1439 {
1440 	bool light_probe = mlx5_dev_is_lightweight(dev);
1441 	int err = 0;
1442 
1443 	mutex_lock(&dev->intf_state_mutex);
1444 	dev->state = MLX5_DEVICE_STATE_UP;
1445 
1446 	err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1447 	if (err)
1448 		goto err_function;
1449 
1450 	err = mlx5_init_once(dev);
1451 	if (err) {
1452 		mlx5_core_err(dev, "sw objs init failed\n");
1453 		goto function_teardown;
1454 	}
1455 
1456 	/* In case of light_probe, mlx5_devlink is already registered.
1457 	 * Hence, don't register devlink again.
1458 	 */
1459 	if (!light_probe) {
1460 		err = mlx5_devlink_params_register(priv_to_devlink(dev));
1461 		if (err)
1462 			goto err_devlink_params_reg;
1463 	}
1464 
1465 	err = mlx5_load(dev);
1466 	if (err)
1467 		goto err_load;
1468 
1469 	set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1470 
1471 	err = mlx5_register_device(dev);
1472 	if (err)
1473 		goto err_register;
1474 
1475 	err = mlx5_crdump_enable(dev);
1476 	if (err)
1477 		mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1478 
1479 	err = mlx5_hwmon_dev_register(dev);
1480 	if (err)
1481 		mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1482 
1483 	mutex_unlock(&dev->intf_state_mutex);
1484 	return 0;
1485 
1486 err_register:
1487 	clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1488 	mlx5_unload(dev);
1489 err_load:
1490 	if (!light_probe)
1491 		mlx5_devlink_params_unregister(priv_to_devlink(dev));
1492 err_devlink_params_reg:
1493 	mlx5_cleanup_once(dev);
1494 function_teardown:
1495 	mlx5_function_teardown(dev, true);
1496 err_function:
1497 	dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1498 	mutex_unlock(&dev->intf_state_mutex);
1499 	return err;
1500 }
1501 
mlx5_init_one(struct mlx5_core_dev * dev)1502 int mlx5_init_one(struct mlx5_core_dev *dev)
1503 {
1504 	struct devlink *devlink = priv_to_devlink(dev);
1505 	int err;
1506 
1507 	devl_lock(devlink);
1508 	devl_register(devlink);
1509 	err = mlx5_init_one_devl_locked(dev);
1510 	if (err)
1511 		devl_unregister(devlink);
1512 	devl_unlock(devlink);
1513 	return err;
1514 }
1515 
mlx5_uninit_one(struct mlx5_core_dev * dev)1516 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1517 {
1518 	struct devlink *devlink = priv_to_devlink(dev);
1519 
1520 	devl_lock(devlink);
1521 	mutex_lock(&dev->intf_state_mutex);
1522 
1523 	mlx5_hwmon_dev_unregister(dev);
1524 	mlx5_crdump_disable(dev);
1525 	mlx5_unregister_device(dev);
1526 
1527 	if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1528 		mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1529 			       __func__);
1530 		mlx5_devlink_params_unregister(priv_to_devlink(dev));
1531 		mlx5_cleanup_once(dev);
1532 		goto out;
1533 	}
1534 
1535 	clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1536 	mlx5_unload(dev);
1537 	mlx5_devlink_params_unregister(priv_to_devlink(dev));
1538 	mlx5_cleanup_once(dev);
1539 	mlx5_function_teardown(dev, true);
1540 out:
1541 	mutex_unlock(&dev->intf_state_mutex);
1542 	devl_unregister(devlink);
1543 	devl_unlock(devlink);
1544 }
1545 
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1546 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1547 {
1548 	int err = 0;
1549 	u64 timeout;
1550 
1551 	devl_assert_locked(priv_to_devlink(dev));
1552 	mutex_lock(&dev->intf_state_mutex);
1553 	if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1554 		mlx5_core_warn(dev, "interface is up, NOP\n");
1555 		goto out;
1556 	}
1557 	/* remove any previous indication of internal error */
1558 	dev->state = MLX5_DEVICE_STATE_UP;
1559 
1560 	if (recovery)
1561 		timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1562 	else
1563 		timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1564 	err = mlx5_function_setup(dev, false, timeout);
1565 	if (err)
1566 		goto err_function;
1567 
1568 	err = mlx5_load(dev);
1569 	if (err)
1570 		goto err_load;
1571 
1572 	set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1573 
1574 	err = mlx5_attach_device(dev);
1575 	if (err)
1576 		goto err_attach;
1577 
1578 	mutex_unlock(&dev->intf_state_mutex);
1579 	return 0;
1580 
1581 err_attach:
1582 	clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1583 	mlx5_unload(dev);
1584 err_load:
1585 	mlx5_function_teardown(dev, false);
1586 err_function:
1587 	dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1588 out:
1589 	mutex_unlock(&dev->intf_state_mutex);
1590 	return err;
1591 }
1592 
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1593 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1594 {
1595 	struct devlink *devlink = priv_to_devlink(dev);
1596 	int ret;
1597 
1598 	devl_lock(devlink);
1599 	ret = mlx5_load_one_devl_locked(dev, recovery);
1600 	devl_unlock(devlink);
1601 	return ret;
1602 }
1603 
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1604 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1605 {
1606 	devl_assert_locked(priv_to_devlink(dev));
1607 	mutex_lock(&dev->intf_state_mutex);
1608 
1609 	mlx5_detach_device(dev, suspend);
1610 
1611 	if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1612 		mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1613 			       __func__);
1614 		goto out;
1615 	}
1616 
1617 	clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1618 	mlx5_unload(dev);
1619 	mlx5_function_teardown(dev, false);
1620 out:
1621 	mutex_unlock(&dev->intf_state_mutex);
1622 }
1623 
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1624 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1625 {
1626 	struct devlink *devlink = priv_to_devlink(dev);
1627 
1628 	devl_lock(devlink);
1629 	mlx5_unload_one_devl_locked(dev, suspend);
1630 	devl_unlock(devlink);
1631 }
1632 
1633 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1634  * A full query of hca_caps will be done when the device will reload.
1635  */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1636 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1637 {
1638 	int err;
1639 
1640 	err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1641 	if (err)
1642 		return err;
1643 
1644 	if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1645 		err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1646 					      HCA_CAP_OPMOD_GET_CUR);
1647 		if (err)
1648 			return err;
1649 	}
1650 
1651 	if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1652 	    MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1653 		err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1654 					      HCA_CAP_OPMOD_GET_CUR);
1655 		if (err)
1656 			return err;
1657 	}
1658 
1659 	if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1660 		MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1661 		err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1662 					      HCA_CAP_OPMOD_GET_CUR);
1663 		if (err)
1664 			return err;
1665 	}
1666 
1667 	return 0;
1668 }
1669 
mlx5_init_one_light(struct mlx5_core_dev * dev)1670 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1671 {
1672 	struct devlink *devlink = priv_to_devlink(dev);
1673 	int err;
1674 
1675 	dev->state = MLX5_DEVICE_STATE_UP;
1676 	err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1677 	if (err) {
1678 		mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1679 		goto out;
1680 	}
1681 
1682 	err = mlx5_query_hca_caps_light(dev);
1683 	if (err) {
1684 		mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1685 		goto query_hca_caps_err;
1686 	}
1687 
1688 	devl_lock(devlink);
1689 	devl_register(devlink);
1690 
1691 	err = mlx5_devlink_params_register(priv_to_devlink(dev));
1692 	if (err) {
1693 		mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1694 		goto query_hca_caps_err;
1695 	}
1696 
1697 	devl_unlock(devlink);
1698 	return 0;
1699 
1700 query_hca_caps_err:
1701 	devl_unregister(devlink);
1702 	devl_unlock(devlink);
1703 	mlx5_function_disable(dev, true);
1704 out:
1705 	dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1706 	return err;
1707 }
1708 
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1709 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1710 {
1711 	struct devlink *devlink = priv_to_devlink(dev);
1712 
1713 	devl_lock(devlink);
1714 	mlx5_devlink_params_unregister(priv_to_devlink(dev));
1715 	devl_unregister(devlink);
1716 	devl_unlock(devlink);
1717 	if (dev->state != MLX5_DEVICE_STATE_UP)
1718 		return;
1719 	mlx5_function_disable(dev, true);
1720 }
1721 
1722 /* xxx_light() function are used in order to configure the device without full
1723  * init (light init). e.g.: There isn't a point in reload a device to light state.
1724  * Hence, mlx5_load_one_light() isn't needed.
1725  */
1726 
mlx5_unload_one_light(struct mlx5_core_dev * dev)1727 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1728 {
1729 	if (dev->state != MLX5_DEVICE_STATE_UP)
1730 		return;
1731 	mlx5_function_disable(dev, false);
1732 	dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1733 }
1734 
1735 static const int types[] = {
1736 	MLX5_CAP_GENERAL,
1737 	MLX5_CAP_GENERAL_2,
1738 	MLX5_CAP_ETHERNET_OFFLOADS,
1739 	MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1740 	MLX5_CAP_ODP,
1741 	MLX5_CAP_ATOMIC,
1742 	MLX5_CAP_ROCE,
1743 	MLX5_CAP_IPOIB_OFFLOADS,
1744 	MLX5_CAP_FLOW_TABLE,
1745 	MLX5_CAP_ESWITCH_FLOW_TABLE,
1746 	MLX5_CAP_ESWITCH,
1747 	MLX5_CAP_QOS,
1748 	MLX5_CAP_DEBUG,
1749 	MLX5_CAP_DEV_MEM,
1750 	MLX5_CAP_DEV_EVENT,
1751 	MLX5_CAP_TLS,
1752 	MLX5_CAP_VDPA_EMULATION,
1753 	MLX5_CAP_IPSEC,
1754 	MLX5_CAP_PORT_SELECTION,
1755 	MLX5_CAP_MACSEC,
1756 	MLX5_CAP_ADV_VIRTUALIZATION,
1757 	MLX5_CAP_CRYPTO,
1758 };
1759 
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1760 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1761 {
1762 	int type;
1763 	int i;
1764 
1765 	for (i = 0; i < ARRAY_SIZE(types); i++) {
1766 		type = types[i];
1767 		kfree(dev->caps.hca[type]);
1768 	}
1769 }
1770 
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1771 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1772 {
1773 	struct mlx5_hca_cap *cap;
1774 	int type;
1775 	int i;
1776 
1777 	for (i = 0; i < ARRAY_SIZE(types); i++) {
1778 		cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1779 		if (!cap)
1780 			goto err;
1781 		type = types[i];
1782 		dev->caps.hca[type] = cap;
1783 	}
1784 
1785 	return 0;
1786 
1787 err:
1788 	mlx5_hca_caps_free(dev);
1789 	return -ENOMEM;
1790 }
1791 
vhca_id_show(struct seq_file * file,void * priv)1792 static int vhca_id_show(struct seq_file *file, void *priv)
1793 {
1794 	struct mlx5_core_dev *dev = file->private;
1795 
1796 	seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1797 	return 0;
1798 }
1799 
1800 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1801 
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1802 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1803 {
1804 	struct mlx5_priv *priv = &dev->priv;
1805 	int err;
1806 
1807 	memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1808 	lockdep_register_key(&dev->lock_key);
1809 	mutex_init(&dev->intf_state_mutex);
1810 	lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1811 	mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1812 
1813 	mutex_init(&priv->bfregs.reg_head.lock);
1814 	mutex_init(&priv->bfregs.wc_head.lock);
1815 	INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1816 	INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1817 
1818 	mutex_init(&priv->alloc_mutex);
1819 	mutex_init(&priv->pgdir_mutex);
1820 	INIT_LIST_HEAD(&priv->pgdir_list);
1821 
1822 	priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1823 	priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1824 						mlx5_debugfs_root);
1825 	debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1826 	INIT_LIST_HEAD(&priv->traps);
1827 
1828 	err = mlx5_cmd_init(dev);
1829 	if (err) {
1830 		mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1831 		goto err_cmd_init;
1832 	}
1833 
1834 	err = mlx5_tout_init(dev);
1835 	if (err) {
1836 		mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1837 		goto err_timeout_init;
1838 	}
1839 
1840 	err = mlx5_health_init(dev);
1841 	if (err)
1842 		goto err_health_init;
1843 
1844 	err = mlx5_pagealloc_init(dev);
1845 	if (err)
1846 		goto err_pagealloc_init;
1847 
1848 	err = mlx5_adev_init(dev);
1849 	if (err)
1850 		goto err_adev_init;
1851 
1852 	err = mlx5_hca_caps_alloc(dev);
1853 	if (err)
1854 		goto err_hca_caps;
1855 
1856 	/* The conjunction of sw_vhca_id with sw_owner_id will be a global
1857 	 * unique id per function which uses mlx5_core.
1858 	 * Those values are supplied to FW as part of the init HCA command to
1859 	 * be used by both driver and FW when it's applicable.
1860 	 */
1861 	dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1862 					       MAX_SW_VHCA_ID,
1863 					       GFP_KERNEL);
1864 	if (dev->priv.sw_vhca_id < 0)
1865 		mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1866 			      dev->priv.sw_vhca_id);
1867 
1868 	return 0;
1869 
1870 err_hca_caps:
1871 	mlx5_adev_cleanup(dev);
1872 err_adev_init:
1873 	mlx5_pagealloc_cleanup(dev);
1874 err_pagealloc_init:
1875 	mlx5_health_cleanup(dev);
1876 err_health_init:
1877 	mlx5_tout_cleanup(dev);
1878 err_timeout_init:
1879 	mlx5_cmd_cleanup(dev);
1880 err_cmd_init:
1881 	debugfs_remove(dev->priv.dbg.dbg_root);
1882 	mutex_destroy(&priv->pgdir_mutex);
1883 	mutex_destroy(&priv->alloc_mutex);
1884 	mutex_destroy(&priv->bfregs.wc_head.lock);
1885 	mutex_destroy(&priv->bfregs.reg_head.lock);
1886 	mutex_destroy(&dev->intf_state_mutex);
1887 	lockdep_unregister_key(&dev->lock_key);
1888 	return err;
1889 }
1890 
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1891 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1892 {
1893 	struct mlx5_priv *priv = &dev->priv;
1894 
1895 	if (priv->sw_vhca_id > 0)
1896 		ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1897 
1898 	mlx5_hca_caps_free(dev);
1899 	mlx5_adev_cleanup(dev);
1900 	mlx5_pagealloc_cleanup(dev);
1901 	mlx5_health_cleanup(dev);
1902 	mlx5_tout_cleanup(dev);
1903 	mlx5_cmd_cleanup(dev);
1904 	debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1905 	mutex_destroy(&priv->pgdir_mutex);
1906 	mutex_destroy(&priv->alloc_mutex);
1907 	mutex_destroy(&priv->bfregs.wc_head.lock);
1908 	mutex_destroy(&priv->bfregs.reg_head.lock);
1909 	mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1910 	mutex_destroy(&dev->intf_state_mutex);
1911 	lockdep_unregister_key(&dev->lock_key);
1912 }
1913 
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1914 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1915 {
1916 	struct mlx5_core_dev *dev;
1917 	struct devlink *devlink;
1918 	int err;
1919 
1920 	devlink = mlx5_devlink_alloc(&pdev->dev);
1921 	if (!devlink) {
1922 		dev_err(&pdev->dev, "devlink alloc failed\n");
1923 		return -ENOMEM;
1924 	}
1925 
1926 	dev = devlink_priv(devlink);
1927 	dev->device = &pdev->dev;
1928 	dev->pdev = pdev;
1929 
1930 	dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1931 			 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1932 
1933 	dev->priv.adev_idx = mlx5_adev_idx_alloc();
1934 	if (dev->priv.adev_idx < 0) {
1935 		err = dev->priv.adev_idx;
1936 		goto adev_init_err;
1937 	}
1938 
1939 	err = mlx5_mdev_init(dev, prof_sel);
1940 	if (err)
1941 		goto mdev_init_err;
1942 
1943 	err = mlx5_pci_init(dev, pdev, id);
1944 	if (err) {
1945 		mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1946 			      err);
1947 		goto pci_init_err;
1948 	}
1949 
1950 	err = mlx5_init_one(dev);
1951 	if (err) {
1952 		mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1953 			      err);
1954 		goto err_init_one;
1955 	}
1956 
1957 	pci_save_state(pdev);
1958 	return 0;
1959 
1960 err_init_one:
1961 	mlx5_pci_close(dev);
1962 pci_init_err:
1963 	mlx5_mdev_uninit(dev);
1964 mdev_init_err:
1965 	mlx5_adev_idx_free(dev->priv.adev_idx);
1966 adev_init_err:
1967 	mlx5_devlink_free(devlink);
1968 
1969 	return err;
1970 }
1971 
remove_one(struct pci_dev * pdev)1972 static void remove_one(struct pci_dev *pdev)
1973 {
1974 	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
1975 	struct devlink *devlink = priv_to_devlink(dev);
1976 
1977 	set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1978 	mlx5_drain_fw_reset(dev);
1979 	mlx5_drain_health_wq(dev);
1980 	mlx5_sriov_disable(pdev, false);
1981 	mlx5_uninit_one(dev);
1982 	mlx5_pci_close(dev);
1983 	mlx5_mdev_uninit(dev);
1984 	mlx5_adev_idx_free(dev->priv.adev_idx);
1985 	mlx5_devlink_free(devlink);
1986 }
1987 
1988 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1989 	struct mlx5_core_dev *__dev = (dev); \
1990 	mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1991 		       __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1992 		       __dev->pci_status, ##__VA_ARGS__); \
1993 })
1994 
result2str(enum pci_ers_result result)1995 static const char *result2str(enum pci_ers_result result)
1996 {
1997 	return  result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1998 		result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1999 		result == PCI_ERS_RESULT_RECOVERED  ? "recovered" :
2000 		"unknown";
2001 }
2002 
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2003 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2004 					      pci_channel_state_t state)
2005 {
2006 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2007 	enum pci_ers_result res;
2008 
2009 	mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2010 
2011 	mlx5_enter_error_state(dev, false);
2012 	mlx5_error_sw_reset(dev);
2013 	mlx5_unload_one(dev, false);
2014 	mlx5_drain_health_wq(dev);
2015 	mlx5_pci_disable_device(dev);
2016 
2017 	res = state == pci_channel_io_perm_failure ?
2018 		PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2019 
2020 	mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2021 		       __func__, dev->state, dev->pci_status, res, result2str(res));
2022 	return res;
2023 }
2024 
2025 /* wait for the device to show vital signs by waiting
2026  * for the health counter to start counting.
2027  */
wait_vital(struct pci_dev * pdev)2028 static int wait_vital(struct pci_dev *pdev)
2029 {
2030 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2031 	struct mlx5_core_health *health = &dev->priv.health;
2032 	const int niter = 100;
2033 	u32 last_count = 0;
2034 	u32 count;
2035 	int i;
2036 
2037 	for (i = 0; i < niter; i++) {
2038 		count = ioread32be(health->health_counter);
2039 		if (count && count != 0xffffffff) {
2040 			if (last_count && last_count != count) {
2041 				mlx5_core_info(dev,
2042 					       "wait vital counter value 0x%x after %d iterations\n",
2043 					       count, i);
2044 				return 0;
2045 			}
2046 			last_count = count;
2047 		}
2048 		msleep(50);
2049 	}
2050 
2051 	return -ETIMEDOUT;
2052 }
2053 
mlx5_pci_slot_reset(struct pci_dev * pdev)2054 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2055 {
2056 	enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2057 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2058 	int err;
2059 
2060 	mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2061 		       __func__, dev->state, dev->pci_status);
2062 
2063 	err = mlx5_pci_enable_device(dev);
2064 	if (err) {
2065 		mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2066 			      __func__, err);
2067 		goto out;
2068 	}
2069 
2070 	pci_set_master(pdev);
2071 	pci_restore_state(pdev);
2072 	pci_save_state(pdev);
2073 
2074 	err = wait_vital(pdev);
2075 	if (err) {
2076 		mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2077 			      __func__, err);
2078 		goto out;
2079 	}
2080 
2081 	res = PCI_ERS_RESULT_RECOVERED;
2082 out:
2083 	mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2084 		       __func__, dev->state, dev->pci_status, err, res, result2str(res));
2085 	return res;
2086 }
2087 
mlx5_pci_resume(struct pci_dev * pdev)2088 static void mlx5_pci_resume(struct pci_dev *pdev)
2089 {
2090 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2091 	int err;
2092 
2093 	mlx5_pci_trace(dev, "Enter, loading driver..\n");
2094 
2095 	err = mlx5_load_one(dev, false);
2096 
2097 	if (!err)
2098 		devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2099 						     DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2100 
2101 	mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2102 		       !err ? "recovered" : "Failed");
2103 }
2104 
2105 static const struct pci_error_handlers mlx5_err_handler = {
2106 	.error_detected = mlx5_pci_err_detected,
2107 	.slot_reset	= mlx5_pci_slot_reset,
2108 	.resume		= mlx5_pci_resume
2109 };
2110 
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2111 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2112 {
2113 	bool fast_teardown = false, force_teardown = false;
2114 	int ret = 1;
2115 
2116 	fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2117 	force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2118 
2119 	mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2120 	mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2121 
2122 	if (!fast_teardown && !force_teardown)
2123 		return -EOPNOTSUPP;
2124 
2125 	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2126 		mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2127 		return -EAGAIN;
2128 	}
2129 
2130 	/* Panic tear down fw command will stop the PCI bus communication
2131 	 * with the HCA, so the health poll is no longer needed.
2132 	 */
2133 	mlx5_stop_health_poll(dev, false);
2134 
2135 	ret = mlx5_cmd_fast_teardown_hca(dev);
2136 	if (!ret)
2137 		goto succeed;
2138 
2139 	ret = mlx5_cmd_force_teardown_hca(dev);
2140 	if (!ret)
2141 		goto succeed;
2142 
2143 	mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2144 	mlx5_start_health_poll(dev);
2145 	return ret;
2146 
2147 succeed:
2148 	mlx5_enter_error_state(dev, true);
2149 
2150 	/* Some platforms requiring freeing the IRQ's in the shutdown
2151 	 * flow. If they aren't freed they can't be allocated after
2152 	 * kexec. There is no need to cleanup the mlx5_core software
2153 	 * contexts.
2154 	 */
2155 	mlx5_core_eq_free_irqs(dev);
2156 
2157 	return 0;
2158 }
2159 
shutdown(struct pci_dev * pdev)2160 static void shutdown(struct pci_dev *pdev)
2161 {
2162 	struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
2163 	int err;
2164 
2165 	mlx5_core_info(dev, "Shutdown was called\n");
2166 	set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2167 	mlx5_drain_health_wq(dev);
2168 	err = mlx5_try_fast_unload(dev);
2169 	if (err)
2170 		mlx5_unload_one(dev, false);
2171 	mlx5_pci_disable_device(dev);
2172 }
2173 
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2174 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2175 {
2176 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2177 
2178 	mlx5_unload_one(dev, true);
2179 
2180 	return 0;
2181 }
2182 
mlx5_resume(struct pci_dev * pdev)2183 static int mlx5_resume(struct pci_dev *pdev)
2184 {
2185 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2186 
2187 	return mlx5_load_one(dev, false);
2188 }
2189 
2190 static const struct pci_device_id mlx5_core_pci_table[] = {
2191 	{ PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2192 	{ PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},	/* Connect-IB VF */
2193 	{ PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2194 	{ PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},	/* ConnectX-4 VF */
2195 	{ PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2196 	{ PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},	/* ConnectX-4LX VF */
2197 	{ PCI_VDEVICE(MELLANOX, 0x1017) },			/* ConnectX-5, PCIe 3.0 */
2198 	{ PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},	/* ConnectX-5 VF */
2199 	{ PCI_VDEVICE(MELLANOX, 0x1019) },			/* ConnectX-5 Ex */
2200 	{ PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF},	/* ConnectX-5 Ex VF */
2201 	{ PCI_VDEVICE(MELLANOX, 0x101b) },			/* ConnectX-6 */
2202 	{ PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF},	/* ConnectX-6 VF */
2203 	{ PCI_VDEVICE(MELLANOX, 0x101d) },			/* ConnectX-6 Dx */
2204 	{ PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF},	/* ConnectX Family mlx5Gen Virtual Function */
2205 	{ PCI_VDEVICE(MELLANOX, 0x101f) },			/* ConnectX-6 LX */
2206 	{ PCI_VDEVICE(MELLANOX, 0x1021) },			/* ConnectX-7 */
2207 	{ PCI_VDEVICE(MELLANOX, 0x1023) },			/* ConnectX-8 */
2208 	{ PCI_VDEVICE(MELLANOX, 0x1025) },			/* ConnectX-9 */
2209 	{ PCI_VDEVICE(MELLANOX, 0xa2d2) },			/* BlueField integrated ConnectX-5 network controller */
2210 	{ PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF},	/* BlueField integrated ConnectX-5 network controller VF */
2211 	{ PCI_VDEVICE(MELLANOX, 0xa2d6) },			/* BlueField-2 integrated ConnectX-6 Dx network controller */
2212 	{ PCI_VDEVICE(MELLANOX, 0xa2dc) },			/* BlueField-3 integrated ConnectX-7 network controller */
2213 	{ PCI_VDEVICE(MELLANOX, 0xa2df) },			/* BlueField-4 integrated ConnectX-8 network controller */
2214 	{ 0, }
2215 };
2216 
2217 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2218 
mlx5_disable_device(struct mlx5_core_dev * dev)2219 void mlx5_disable_device(struct mlx5_core_dev *dev)
2220 {
2221 	mlx5_error_sw_reset(dev);
2222 	mlx5_unload_one_devl_locked(dev, false);
2223 }
2224 
mlx5_recover_device(struct mlx5_core_dev * dev)2225 int mlx5_recover_device(struct mlx5_core_dev *dev)
2226 {
2227 	if (!mlx5_core_is_sf(dev)) {
2228 		mlx5_pci_disable_device(dev);
2229 		if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2230 			return -EIO;
2231 	}
2232 
2233 	return mlx5_load_one_devl_locked(dev, true);
2234 }
2235 
2236 static struct pci_driver mlx5_core_driver = {
2237 	.name           = KBUILD_MODNAME,
2238 	.id_table       = mlx5_core_pci_table,
2239 	.probe          = probe_one,
2240 	.remove         = remove_one,
2241 	.suspend        = mlx5_suspend,
2242 	.resume         = mlx5_resume,
2243 	.shutdown	= shutdown,
2244 	.err_handler	= &mlx5_err_handler,
2245 	.sriov_configure   = mlx5_core_sriov_configure,
2246 	.sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2247 	.sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2248 };
2249 
2250 /**
2251  * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2252  *                     mlx5_core is its driver.
2253  * @pdev: The associated PCI device.
2254  *
2255  * Upon return the interface state lock stay held to let caller uses it safely.
2256  * Caller must ensure to use the returned mlx5 device for a narrow window
2257  * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2258  *
2259  * Return: Pointer to the associated mlx5_core_dev or NULL.
2260  */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2261 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2262 {
2263 	struct mlx5_core_dev *mdev;
2264 
2265 	mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2266 	if (IS_ERR(mdev))
2267 		return NULL;
2268 
2269 	mutex_lock(&mdev->intf_state_mutex);
2270 	if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2271 		mutex_unlock(&mdev->intf_state_mutex);
2272 		return NULL;
2273 	}
2274 
2275 	return mdev;
2276 }
2277 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2278 
2279 /**
2280  * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2281  * @mdev: The mlx5 core device.
2282  *
2283  * Upon return the interface state lock is unlocked and caller should not
2284  * access the mdev any more.
2285  */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2286 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2287 {
2288 	mutex_unlock(&mdev->intf_state_mutex);
2289 }
2290 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2291 
mlx5_core_verify_params(void)2292 static void mlx5_core_verify_params(void)
2293 {
2294 	if (prof_sel >= ARRAY_SIZE(profile)) {
2295 		pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2296 			prof_sel,
2297 			ARRAY_SIZE(profile) - 1,
2298 			MLX5_DEFAULT_PROF);
2299 		prof_sel = MLX5_DEFAULT_PROF;
2300 	}
2301 }
2302 
mlx5_init(void)2303 static int __init mlx5_init(void)
2304 {
2305 	int err;
2306 
2307 	WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2308 		  "mlx5_core name not in sync with kernel module name");
2309 
2310 	get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2311 
2312 	mlx5_core_verify_params();
2313 	mlx5_register_debugfs();
2314 
2315 	err = mlx5e_init();
2316 	if (err)
2317 		goto err_debug;
2318 
2319 	err = mlx5_sf_driver_register();
2320 	if (err)
2321 		goto err_sf;
2322 
2323 	err = pci_register_driver(&mlx5_core_driver);
2324 	if (err)
2325 		goto err_pci;
2326 
2327 	return 0;
2328 
2329 err_pci:
2330 	mlx5_sf_driver_unregister();
2331 err_sf:
2332 	mlx5e_cleanup();
2333 err_debug:
2334 	mlx5_unregister_debugfs();
2335 	return err;
2336 }
2337 
mlx5_cleanup(void)2338 static void __exit mlx5_cleanup(void)
2339 {
2340 	pci_unregister_driver(&mlx5_core_driver);
2341 	mlx5_sf_driver_unregister();
2342 	mlx5e_cleanup();
2343 	mlx5_unregister_debugfs();
2344 }
2345 
2346 module_init(mlx5_init);
2347 module_exit(mlx5_cleanup);
2348