1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 display_subsystem: display-subsystem { 133 compatible = "rockchip,display-subsystem"; 134 ports = <&vop_out>; 135 }; 136 137 firmware { 138 scmi: scmi { 139 compatible = "arm,scmi-smc"; 140 arm,smc-id = <0x82000010>; 141 shmem = <&scmi_shmem>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 scmi_clk: protocol@14 { 146 reg = <0x14>; 147 #clock-cells = <1>; 148 }; 149 }; 150 }; 151 152 gpu_opp_table: opp-table-1 { 153 compatible = "operating-points-v2"; 154 155 opp-200000000 { 156 opp-hz = /bits/ 64 <200000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-300000000 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-400000000 { 166 opp-hz = /bits/ 64 <400000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-600000000 { 171 opp-hz = /bits/ 64 <600000000>; 172 opp-microvolt = <825000>; 173 }; 174 175 opp-700000000 { 176 opp-hz = /bits/ 64 <700000000>; 177 opp-microvolt = <900000>; 178 }; 179 180 opp-800000000 { 181 opp-hz = /bits/ 64 <800000000>; 182 opp-microvolt = <1000000>; 183 }; 184 }; 185 186 hdmi_sound: hdmi-sound { 187 compatible = "simple-audio-card"; 188 simple-audio-card,name = "HDMI"; 189 simple-audio-card,format = "i2s"; 190 simple-audio-card,mclk-fs = <256>; 191 status = "disabled"; 192 193 simple-audio-card,codec { 194 sound-dai = <&hdmi>; 195 }; 196 197 simple-audio-card,cpu { 198 sound-dai = <&i2s0_8ch>; 199 }; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a55-pmu"; 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 209 }; 210 211 psci { 212 compatible = "arm,psci-1.0"; 213 method = "smc"; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 222 arm,no-tick-in-suspend; 223 }; 224 225 xin24m: xin24m { 226 compatible = "fixed-clock"; 227 clock-frequency = <24000000>; 228 clock-output-names = "xin24m"; 229 #clock-cells = <0>; 230 }; 231 232 xin32k: xin32k { 233 compatible = "fixed-clock"; 234 clock-frequency = <32768>; 235 clock-output-names = "xin32k"; 236 pinctrl-0 = <&clk32k_out0>; 237 pinctrl-names = "default"; 238 #clock-cells = <0>; 239 }; 240 241 sram@10f000 { 242 compatible = "mmio-sram"; 243 reg = <0x0 0x0010f000 0x0 0x100>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0 0x0 0x0010f000 0x100>; 247 248 scmi_shmem: sram@0 { 249 compatible = "arm,scmi-shmem"; 250 reg = <0x0 0x100>; 251 }; 252 }; 253 254 sata1: sata@fc400000 { 255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 256 reg = <0 0xfc400000 0 0x1000>; 257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 258 <&cru CLK_SATA1_RXOOB>; 259 clock-names = "sata", "pmalive", "rxoob"; 260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 261 phys = <&combphy1 PHY_TYPE_SATA>; 262 phy-names = "sata-phy"; 263 ports-implemented = <0x1>; 264 power-domains = <&power RK3568_PD_PIPE>; 265 status = "disabled"; 266 }; 267 268 sata2: sata@fc800000 { 269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 270 reg = <0 0xfc800000 0 0x1000>; 271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 272 <&cru CLK_SATA2_RXOOB>; 273 clock-names = "sata", "pmalive", "rxoob"; 274 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 275 phys = <&combphy2 PHY_TYPE_SATA>; 276 phy-names = "sata-phy"; 277 ports-implemented = <0x1>; 278 power-domains = <&power RK3568_PD_PIPE>; 279 status = "disabled"; 280 }; 281 282 usb_host0_xhci: usb@fcc00000 { 283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 284 reg = <0x0 0xfcc00000 0x0 0x400000>; 285 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 287 <&cru ACLK_USB3OTG0>; 288 clock-names = "ref_clk", "suspend_clk", 289 "bus_clk"; 290 dr_mode = "otg"; 291 phy_type = "utmi_wide"; 292 power-domains = <&power RK3568_PD_PIPE>; 293 resets = <&cru SRST_USB3OTG0>; 294 snps,dis_u2_susphy_quirk; 295 status = "disabled"; 296 }; 297 298 usb_host1_xhci: usb@fd000000 { 299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 300 reg = <0x0 0xfd000000 0x0 0x400000>; 301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 303 <&cru ACLK_USB3OTG1>; 304 clock-names = "ref_clk", "suspend_clk", 305 "bus_clk"; 306 dr_mode = "host"; 307 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 308 phy-names = "usb2-phy", "usb3-phy"; 309 phy_type = "utmi_wide"; 310 power-domains = <&power RK3568_PD_PIPE>; 311 resets = <&cru SRST_USB3OTG1>; 312 snps,dis_u2_susphy_quirk; 313 status = "disabled"; 314 }; 315 316 gic: interrupt-controller@fd400000 { 317 compatible = "arm,gic-v3"; 318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 319 <0x0 0xfd460000 0 0x80000>; /* GICR */ 320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <3>; 323 mbi-alias = <0x0 0xfd410000>; 324 mbi-ranges = <296 24>; 325 msi-controller; 326 }; 327 328 usb_host0_ehci: usb@fd800000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfd800000 0x0 0x40000>; 331 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 333 <&cru PCLK_USB>; 334 phys = <&usb2phy1_otg>; 335 phy-names = "usb"; 336 status = "disabled"; 337 }; 338 339 usb_host0_ohci: usb@fd840000 { 340 compatible = "generic-ohci"; 341 reg = <0x0 0xfd840000 0x0 0x40000>; 342 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 344 <&cru PCLK_USB>; 345 phys = <&usb2phy1_otg>; 346 phy-names = "usb"; 347 status = "disabled"; 348 }; 349 350 usb_host1_ehci: usb@fd880000 { 351 compatible = "generic-ehci"; 352 reg = <0x0 0xfd880000 0x0 0x40000>; 353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 355 <&cru PCLK_USB>; 356 phys = <&usb2phy1_host>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ohci: usb@fd8c0000 { 362 compatible = "generic-ohci"; 363 reg = <0x0 0xfd8c0000 0x0 0x40000>; 364 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 366 <&cru PCLK_USB>; 367 phys = <&usb2phy1_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 pmugrf: syscon@fdc20000 { 373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 374 reg = <0x0 0xfdc20000 0x0 0x10000>; 375 376 pmu_io_domains: io-domains { 377 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 378 status = "disabled"; 379 }; 380 }; 381 382 pipegrf: syscon@fdc50000 { 383 reg = <0x0 0xfdc50000 0x0 0x1000>; 384 }; 385 386 grf: syscon@fdc60000 { 387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 388 reg = <0x0 0xfdc60000 0x0 0x10000>; 389 }; 390 391 pipe_phy_grf1: syscon@fdc80000 { 392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 393 reg = <0x0 0xfdc80000 0x0 0x1000>; 394 }; 395 396 pipe_phy_grf2: syscon@fdc90000 { 397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 398 reg = <0x0 0xfdc90000 0x0 0x1000>; 399 }; 400 401 usb2phy0_grf: syscon@fdca0000 { 402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 403 reg = <0x0 0xfdca0000 0x0 0x8000>; 404 }; 405 406 usb2phy1_grf: syscon@fdca8000 { 407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 408 reg = <0x0 0xfdca8000 0x0 0x8000>; 409 }; 410 411 pmucru: clock-controller@fdd00000 { 412 compatible = "rockchip,rk3568-pmucru"; 413 reg = <0x0 0xfdd00000 0x0 0x1000>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 }; 417 418 cru: clock-controller@fdd20000 { 419 compatible = "rockchip,rk3568-cru"; 420 reg = <0x0 0xfdd20000 0x0 0x1000>; 421 clocks = <&xin24m>; 422 clock-names = "xin24m"; 423 #clock-cells = <1>; 424 #reset-cells = <1>; 425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 426 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 428 rockchip,grf = <&grf>; 429 }; 430 431 i2c0: i2c@fdd40000 { 432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 433 reg = <0x0 0xfdd40000 0x0 0x1000>; 434 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 436 clock-names = "i2c", "pclk"; 437 pinctrl-0 = <&i2c0_xfer>; 438 pinctrl-names = "default"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 uart0: serial@fdd50000 { 445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 446 reg = <0x0 0xfdd50000 0x0 0x100>; 447 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 449 clock-names = "baudclk", "apb_pclk"; 450 dmas = <&dmac0 0>, <&dmac0 1>; 451 pinctrl-0 = <&uart0_xfer>; 452 pinctrl-names = "default"; 453 reg-io-width = <4>; 454 reg-shift = <2>; 455 status = "disabled"; 456 }; 457 458 pwm0: pwm@fdd70000 { 459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 460 reg = <0x0 0xfdd70000 0x0 0x10>; 461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-0 = <&pwm0m0_pins>; 464 pinctrl-names = "default"; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm1: pwm@fdd70010 { 470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 471 reg = <0x0 0xfdd70010 0x0 0x10>; 472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-0 = <&pwm1m0_pins>; 475 pinctrl-names = "default"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm2: pwm@fdd70020 { 481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 482 reg = <0x0 0xfdd70020 0x0 0x10>; 483 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 484 clock-names = "pwm", "pclk"; 485 pinctrl-0 = <&pwm2m0_pins>; 486 pinctrl-names = "default"; 487 #pwm-cells = <3>; 488 status = "disabled"; 489 }; 490 491 pwm3: pwm@fdd70030 { 492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 493 reg = <0x0 0xfdd70030 0x0 0x10>; 494 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 495 clock-names = "pwm", "pclk"; 496 pinctrl-0 = <&pwm3_pins>; 497 pinctrl-names = "default"; 498 #pwm-cells = <3>; 499 status = "disabled"; 500 }; 501 502 pmu: power-management@fdd90000 { 503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 504 reg = <0x0 0xfdd90000 0x0 0x1000>; 505 506 power: power-controller { 507 compatible = "rockchip,rk3568-power-controller"; 508 #power-domain-cells = <1>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 /* These power domains are grouped by VD_GPU */ 513 power-domain@RK3568_PD_GPU { 514 reg = <RK3568_PD_GPU>; 515 clocks = <&cru ACLK_GPU_PRE>, 516 <&cru PCLK_GPU_PRE>; 517 pm_qos = <&qos_gpu>; 518 #power-domain-cells = <0>; 519 }; 520 521 /* These power domains are grouped by VD_LOGIC */ 522 power-domain@RK3568_PD_VI { 523 reg = <RK3568_PD_VI>; 524 clocks = <&cru HCLK_VI>, 525 <&cru PCLK_VI>; 526 pm_qos = <&qos_isp>, 527 <&qos_vicap0>, 528 <&qos_vicap1>; 529 #power-domain-cells = <0>; 530 }; 531 532 power-domain@RK3568_PD_VO { 533 reg = <RK3568_PD_VO>; 534 clocks = <&cru HCLK_VO>, 535 <&cru PCLK_VO>, 536 <&cru ACLK_VOP_PRE>; 537 pm_qos = <&qos_hdcp>, 538 <&qos_vop_m0>, 539 <&qos_vop_m1>; 540 #power-domain-cells = <0>; 541 }; 542 543 power-domain@RK3568_PD_RGA { 544 reg = <RK3568_PD_RGA>; 545 clocks = <&cru HCLK_RGA_PRE>, 546 <&cru PCLK_RGA_PRE>; 547 pm_qos = <&qos_ebc>, 548 <&qos_iep>, 549 <&qos_jpeg_dec>, 550 <&qos_jpeg_enc>, 551 <&qos_rga_rd>, 552 <&qos_rga_wr>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@RK3568_PD_VPU { 557 reg = <RK3568_PD_VPU>; 558 clocks = <&cru HCLK_VPU_PRE>; 559 pm_qos = <&qos_vpu>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@RK3568_PD_RKVDEC { 564 clocks = <&cru HCLK_RKVDEC_PRE>; 565 reg = <RK3568_PD_RKVDEC>; 566 pm_qos = <&qos_rkvdec>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@RK3568_PD_RKVENC { 571 reg = <RK3568_PD_RKVENC>; 572 clocks = <&cru HCLK_RKVENC_PRE>; 573 pm_qos = <&qos_rkvenc_rd_m0>, 574 <&qos_rkvenc_rd_m1>, 575 <&qos_rkvenc_wr_m0>; 576 #power-domain-cells = <0>; 577 }; 578 }; 579 }; 580 581 gpu: gpu@fde60000 { 582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 583 reg = <0x0 0xfde60000 0x0 0x4000>; 584 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "job", "mmu", "gpu"; 588 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 589 clock-names = "gpu", "bus"; 590 #cooling-cells = <2>; 591 operating-points-v2 = <&gpu_opp_table>; 592 power-domains = <&power RK3568_PD_GPU>; 593 status = "disabled"; 594 }; 595 596 vpu: video-codec@fdea0400 { 597 compatible = "rockchip,rk3568-vpu"; 598 reg = <0x0 0xfdea0000 0x0 0x800>; 599 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 600 interrupt-names = "vdpu"; 601 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 602 clock-names = "aclk", "hclk"; 603 iommus = <&vdpu_mmu>; 604 power-domains = <&power RK3568_PD_VPU>; 605 }; 606 607 vdpu_mmu: iommu@fdea0800 { 608 compatible = "rockchip,rk3568-iommu"; 609 reg = <0x0 0xfdea0800 0x0 0x40>; 610 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 611 clock-names = "aclk", "iface"; 612 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 613 power-domains = <&power RK3568_PD_VPU>; 614 #iommu-cells = <0>; 615 }; 616 617 rga: rga@fdeb0000 { 618 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 619 reg = <0x0 0xfdeb0000 0x0 0x180>; 620 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 622 clock-names = "aclk", "hclk", "sclk"; 623 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 624 reset-names = "core", "axi", "ahb"; 625 power-domains = <&power RK3568_PD_RGA>; 626 }; 627 628 vepu: video-codec@fdee0000 { 629 compatible = "rockchip,rk3568-vepu"; 630 reg = <0x0 0xfdee0000 0x0 0x800>; 631 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 633 clock-names = "aclk", "hclk"; 634 iommus = <&vepu_mmu>; 635 power-domains = <&power RK3568_PD_RGA>; 636 }; 637 638 vepu_mmu: iommu@fdee0800 { 639 compatible = "rockchip,rk3568-iommu"; 640 reg = <0x0 0xfdee0800 0x0 0x40>; 641 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 643 clock-names = "aclk", "iface"; 644 power-domains = <&power RK3568_PD_RGA>; 645 #iommu-cells = <0>; 646 }; 647 648 sdmmc2: mmc@fe000000 { 649 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 650 reg = <0x0 0xfe000000 0x0 0x4000>; 651 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 653 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 654 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 655 fifo-depth = <0x100>; 656 max-frequency = <150000000>; 657 resets = <&cru SRST_SDMMC2>; 658 reset-names = "reset"; 659 status = "disabled"; 660 }; 661 662 gmac1: ethernet@fe010000 { 663 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 664 reg = <0x0 0xfe010000 0x0 0x10000>; 665 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "macirq", "eth_wake_irq"; 668 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 669 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 670 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 671 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 672 clock-names = "stmmaceth", "mac_clk_rx", 673 "mac_clk_tx", "clk_mac_refout", 674 "aclk_mac", "pclk_mac", 675 "clk_mac_speed", "ptp_ref"; 676 resets = <&cru SRST_A_GMAC1>; 677 reset-names = "stmmaceth"; 678 rockchip,grf = <&grf>; 679 snps,axi-config = <&gmac1_stmmac_axi_setup>; 680 snps,mixed-burst; 681 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 682 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 683 snps,tso; 684 status = "disabled"; 685 686 mdio1: mdio { 687 compatible = "snps,dwmac-mdio"; 688 #address-cells = <0x1>; 689 #size-cells = <0x0>; 690 }; 691 692 gmac1_stmmac_axi_setup: stmmac-axi-config { 693 snps,blen = <0 0 0 0 16 8 4>; 694 snps,rd_osr_lmt = <8>; 695 snps,wr_osr_lmt = <4>; 696 }; 697 698 gmac1_mtl_rx_setup: rx-queues-config { 699 snps,rx-queues-to-use = <1>; 700 queue0 {}; 701 }; 702 703 gmac1_mtl_tx_setup: tx-queues-config { 704 snps,tx-queues-to-use = <1>; 705 queue0 {}; 706 }; 707 }; 708 709 vop: vop@fe040000 { 710 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 711 reg-names = "vop", "gamma-lut"; 712 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 714 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 715 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 716 iommus = <&vop_mmu>; 717 power-domains = <&power RK3568_PD_VO>; 718 rockchip,grf = <&grf>; 719 status = "disabled"; 720 721 vop_out: ports { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 vp0: port@0 { 726 reg = <0>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 }; 730 731 vp1: port@1 { 732 reg = <1>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 }; 736 737 vp2: port@2 { 738 reg = <2>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 }; 742 }; 743 }; 744 745 vop_mmu: iommu@fe043e00 { 746 compatible = "rockchip,rk3568-iommu"; 747 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 748 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 750 clock-names = "aclk", "iface"; 751 #iommu-cells = <0>; 752 power-domains = <&power RK3568_PD_VO>; 753 status = "disabled"; 754 }; 755 756 dsi0: dsi@fe060000 { 757 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 758 reg = <0x00 0xfe060000 0x00 0x10000>; 759 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 760 clock-names = "pclk"; 761 clocks = <&cru PCLK_DSITX_0>; 762 phy-names = "dphy"; 763 phys = <&dsi_dphy0>; 764 power-domains = <&power RK3568_PD_VO>; 765 reset-names = "apb"; 766 resets = <&cru SRST_P_DSITX_0>; 767 rockchip,grf = <&grf>; 768 status = "disabled"; 769 770 ports { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 dsi0_in: port@0 { 775 reg = <0>; 776 }; 777 778 dsi0_out: port@1 { 779 reg = <1>; 780 }; 781 }; 782 }; 783 784 dsi1: dsi@fe070000 { 785 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 786 reg = <0x0 0xfe070000 0x0 0x10000>; 787 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 788 clock-names = "pclk"; 789 clocks = <&cru PCLK_DSITX_1>; 790 phy-names = "dphy"; 791 phys = <&dsi_dphy1>; 792 power-domains = <&power RK3568_PD_VO>; 793 reset-names = "apb"; 794 resets = <&cru SRST_P_DSITX_1>; 795 rockchip,grf = <&grf>; 796 status = "disabled"; 797 798 ports { 799 #address-cells = <1>; 800 #size-cells = <0>; 801 802 dsi1_in: port@0 { 803 reg = <0>; 804 }; 805 806 dsi1_out: port@1 { 807 reg = <1>; 808 }; 809 }; 810 }; 811 812 hdmi: hdmi@fe0a0000 { 813 compatible = "rockchip,rk3568-dw-hdmi"; 814 reg = <0x0 0xfe0a0000 0x0 0x20000>; 815 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&cru PCLK_HDMI_HOST>, 817 <&cru CLK_HDMI_SFR>, 818 <&cru CLK_HDMI_CEC>, 819 <&pmucru CLK_HDMI_REF>, 820 <&cru HCLK_VO>; 821 clock-names = "iahb", "isfr", "cec", "ref"; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 824 power-domains = <&power RK3568_PD_VO>; 825 reg-io-width = <4>; 826 rockchip,grf = <&grf>; 827 #sound-dai-cells = <0>; 828 status = "disabled"; 829 830 ports { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 834 hdmi_in: port@0 { 835 reg = <0>; 836 }; 837 838 hdmi_out: port@1 { 839 reg = <1>; 840 }; 841 }; 842 }; 843 844 qos_gpu: qos@fe128000 { 845 compatible = "rockchip,rk3568-qos", "syscon"; 846 reg = <0x0 0xfe128000 0x0 0x20>; 847 }; 848 849 qos_rkvenc_rd_m0: qos@fe138080 { 850 compatible = "rockchip,rk3568-qos", "syscon"; 851 reg = <0x0 0xfe138080 0x0 0x20>; 852 }; 853 854 qos_rkvenc_rd_m1: qos@fe138100 { 855 compatible = "rockchip,rk3568-qos", "syscon"; 856 reg = <0x0 0xfe138100 0x0 0x20>; 857 }; 858 859 qos_rkvenc_wr_m0: qos@fe138180 { 860 compatible = "rockchip,rk3568-qos", "syscon"; 861 reg = <0x0 0xfe138180 0x0 0x20>; 862 }; 863 864 qos_isp: qos@fe148000 { 865 compatible = "rockchip,rk3568-qos", "syscon"; 866 reg = <0x0 0xfe148000 0x0 0x20>; 867 }; 868 869 qos_vicap0: qos@fe148080 { 870 compatible = "rockchip,rk3568-qos", "syscon"; 871 reg = <0x0 0xfe148080 0x0 0x20>; 872 }; 873 874 qos_vicap1: qos@fe148100 { 875 compatible = "rockchip,rk3568-qos", "syscon"; 876 reg = <0x0 0xfe148100 0x0 0x20>; 877 }; 878 879 qos_vpu: qos@fe150000 { 880 compatible = "rockchip,rk3568-qos", "syscon"; 881 reg = <0x0 0xfe150000 0x0 0x20>; 882 }; 883 884 qos_ebc: qos@fe158000 { 885 compatible = "rockchip,rk3568-qos", "syscon"; 886 reg = <0x0 0xfe158000 0x0 0x20>; 887 }; 888 889 qos_iep: qos@fe158100 { 890 compatible = "rockchip,rk3568-qos", "syscon"; 891 reg = <0x0 0xfe158100 0x0 0x20>; 892 }; 893 894 qos_jpeg_dec: qos@fe158180 { 895 compatible = "rockchip,rk3568-qos", "syscon"; 896 reg = <0x0 0xfe158180 0x0 0x20>; 897 }; 898 899 qos_jpeg_enc: qos@fe158200 { 900 compatible = "rockchip,rk3568-qos", "syscon"; 901 reg = <0x0 0xfe158200 0x0 0x20>; 902 }; 903 904 qos_rga_rd: qos@fe158280 { 905 compatible = "rockchip,rk3568-qos", "syscon"; 906 reg = <0x0 0xfe158280 0x0 0x20>; 907 }; 908 909 qos_rga_wr: qos@fe158300 { 910 compatible = "rockchip,rk3568-qos", "syscon"; 911 reg = <0x0 0xfe158300 0x0 0x20>; 912 }; 913 914 qos_npu: qos@fe180000 { 915 compatible = "rockchip,rk3568-qos", "syscon"; 916 reg = <0x0 0xfe180000 0x0 0x20>; 917 }; 918 919 qos_pcie2x1: qos@fe190000 { 920 compatible = "rockchip,rk3568-qos", "syscon"; 921 reg = <0x0 0xfe190000 0x0 0x20>; 922 }; 923 924 qos_sata1: qos@fe190280 { 925 compatible = "rockchip,rk3568-qos", "syscon"; 926 reg = <0x0 0xfe190280 0x0 0x20>; 927 }; 928 929 qos_sata2: qos@fe190300 { 930 compatible = "rockchip,rk3568-qos", "syscon"; 931 reg = <0x0 0xfe190300 0x0 0x20>; 932 }; 933 934 qos_usb3_0: qos@fe190380 { 935 compatible = "rockchip,rk3568-qos", "syscon"; 936 reg = <0x0 0xfe190380 0x0 0x20>; 937 }; 938 939 qos_usb3_1: qos@fe190400 { 940 compatible = "rockchip,rk3568-qos", "syscon"; 941 reg = <0x0 0xfe190400 0x0 0x20>; 942 }; 943 944 qos_rkvdec: qos@fe198000 { 945 compatible = "rockchip,rk3568-qos", "syscon"; 946 reg = <0x0 0xfe198000 0x0 0x20>; 947 }; 948 949 qos_hdcp: qos@fe1a8000 { 950 compatible = "rockchip,rk3568-qos", "syscon"; 951 reg = <0x0 0xfe1a8000 0x0 0x20>; 952 }; 953 954 qos_vop_m0: qos@fe1a8080 { 955 compatible = "rockchip,rk3568-qos", "syscon"; 956 reg = <0x0 0xfe1a8080 0x0 0x20>; 957 }; 958 959 qos_vop_m1: qos@fe1a8100 { 960 compatible = "rockchip,rk3568-qos", "syscon"; 961 reg = <0x0 0xfe1a8100 0x0 0x20>; 962 }; 963 964 pcie2x1: pcie@fe260000 { 965 compatible = "rockchip,rk3568-pcie"; 966 reg = <0x3 0xc0000000 0x0 0x00400000>, 967 <0x0 0xfe260000 0x0 0x00010000>, 968 <0x0 0xf4000000 0x0 0x00100000>; 969 reg-names = "dbi", "apb", "config"; 970 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 976 bus-range = <0x0 0xf>; 977 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 978 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 979 <&cru CLK_PCIE20_AUX_NDFT>; 980 clock-names = "aclk_mst", "aclk_slv", 981 "aclk_dbi", "pclk", "aux"; 982 device_type = "pci"; 983 #interrupt-cells = <1>; 984 interrupt-map-mask = <0 0 0 7>; 985 interrupt-map = <0 0 0 1 &pcie_intc 0>, 986 <0 0 0 2 &pcie_intc 1>, 987 <0 0 0 3 &pcie_intc 2>, 988 <0 0 0 4 &pcie_intc 3>; 989 linux,pci-domain = <0>; 990 num-ib-windows = <6>; 991 num-ob-windows = <2>; 992 max-link-speed = <2>; 993 msi-map = <0x0 &gic 0x0 0x1000>; 994 num-lanes = <1>; 995 phys = <&combphy2 PHY_TYPE_PCIE>; 996 phy-names = "pcie-phy"; 997 power-domains = <&power RK3568_PD_PIPE>; 998 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 999 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 1000 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 1001 resets = <&cru SRST_PCIE20_POWERUP>; 1002 reset-names = "pipe"; 1003 #address-cells = <3>; 1004 #size-cells = <2>; 1005 status = "disabled"; 1006 1007 pcie_intc: legacy-interrupt-controller { 1008 #address-cells = <0>; 1009 #interrupt-cells = <1>; 1010 interrupt-controller; 1011 interrupt-parent = <&gic>; 1012 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 1013 }; 1014 }; 1015 1016 sdmmc0: mmc@fe2b0000 { 1017 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1018 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1019 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1021 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1022 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1023 fifo-depth = <0x100>; 1024 max-frequency = <150000000>; 1025 resets = <&cru SRST_SDMMC0>; 1026 reset-names = "reset"; 1027 status = "disabled"; 1028 }; 1029 1030 sdmmc1: mmc@fe2c0000 { 1031 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1032 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1033 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1035 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1036 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1037 fifo-depth = <0x100>; 1038 max-frequency = <150000000>; 1039 resets = <&cru SRST_SDMMC1>; 1040 reset-names = "reset"; 1041 status = "disabled"; 1042 }; 1043 1044 sfc: spi@fe300000 { 1045 compatible = "rockchip,sfc"; 1046 reg = <0x0 0xfe300000 0x0 0x4000>; 1047 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1049 clock-names = "clk_sfc", "hclk_sfc"; 1050 pinctrl-0 = <&fspi_pins>; 1051 pinctrl-names = "default"; 1052 status = "disabled"; 1053 }; 1054 1055 sdhci: mmc@fe310000 { 1056 compatible = "rockchip,rk3568-dwcmshc"; 1057 reg = <0x0 0xfe310000 0x0 0x10000>; 1058 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1059 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1060 assigned-clock-rates = <200000000>, <24000000>; 1061 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1062 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1063 <&cru TCLK_EMMC>; 1064 clock-names = "core", "bus", "axi", "block", "timer"; 1065 status = "disabled"; 1066 }; 1067 1068 i2s0_8ch: i2s@fe400000 { 1069 compatible = "rockchip,rk3568-i2s-tdm"; 1070 reg = <0x0 0xfe400000 0x0 0x1000>; 1071 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1072 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1073 assigned-clock-rates = <1188000000>, <1188000000>; 1074 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1075 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1076 dmas = <&dmac1 0>; 1077 dma-names = "tx"; 1078 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1079 reset-names = "tx-m", "rx-m"; 1080 rockchip,grf = <&grf>; 1081 #sound-dai-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 i2s1_8ch: i2s@fe410000 { 1086 compatible = "rockchip,rk3568-i2s-tdm"; 1087 reg = <0x0 0xfe410000 0x0 0x1000>; 1088 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1089 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1090 assigned-clock-rates = <1188000000>, <1188000000>; 1091 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1092 <&cru HCLK_I2S1_8CH>; 1093 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1094 dmas = <&dmac1 3>, <&dmac1 2>; 1095 dma-names = "rx", "tx"; 1096 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1097 reset-names = "tx-m", "rx-m"; 1098 rockchip,grf = <&grf>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1101 &i2s1m0_lrcktx &i2s1m0_lrckrx 1102 &i2s1m0_sdi0 &i2s1m0_sdi1 1103 &i2s1m0_sdi2 &i2s1m0_sdi3 1104 &i2s1m0_sdo0 &i2s1m0_sdo1 1105 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1106 #sound-dai-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2s2_2ch: i2s@fe420000 { 1111 compatible = "rockchip,rk3568-i2s-tdm"; 1112 reg = <0x0 0xfe420000 0x0 0x1000>; 1113 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1114 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1115 assigned-clock-rates = <1188000000>; 1116 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1117 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1118 dmas = <&dmac1 4>, <&dmac1 5>; 1119 dma-names = "tx", "rx"; 1120 resets = <&cru SRST_M_I2S2_2CH>; 1121 reset-names = "tx-m"; 1122 rockchip,grf = <&grf>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&i2s2m0_sclktx 1125 &i2s2m0_lrcktx 1126 &i2s2m0_sdi 1127 &i2s2m0_sdo>; 1128 #sound-dai-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2s3_2ch: i2s@fe430000 { 1133 compatible = "rockchip,rk3568-i2s-tdm"; 1134 reg = <0x0 0xfe430000 0x0 0x1000>; 1135 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1137 <&cru HCLK_I2S3_2CH>; 1138 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1139 dmas = <&dmac1 6>, <&dmac1 7>; 1140 dma-names = "tx", "rx"; 1141 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1142 reset-names = "tx-m", "rx-m"; 1143 rockchip,grf = <&grf>; 1144 #sound-dai-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 pdm: pdm@fe440000 { 1149 compatible = "rockchip,rk3568-pdm"; 1150 reg = <0x0 0xfe440000 0x0 0x1000>; 1151 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1153 clock-names = "pdm_clk", "pdm_hclk"; 1154 dmas = <&dmac1 9>; 1155 dma-names = "rx"; 1156 pinctrl-0 = <&pdmm0_clk 1157 &pdmm0_clk1 1158 &pdmm0_sdi0 1159 &pdmm0_sdi1 1160 &pdmm0_sdi2 1161 &pdmm0_sdi3>; 1162 pinctrl-names = "default"; 1163 resets = <&cru SRST_M_PDM>; 1164 reset-names = "pdm-m"; 1165 #sound-dai-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 spdif: spdif@fe460000 { 1170 compatible = "rockchip,rk3568-spdif"; 1171 reg = <0x0 0xfe460000 0x0 0x1000>; 1172 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1173 clock-names = "mclk", "hclk"; 1174 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1175 dmas = <&dmac1 1>; 1176 dma-names = "tx"; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&spdifm0_tx>; 1179 #sound-dai-cells = <0>; 1180 status = "disabled"; 1181 }; 1182 1183 dmac0: dma-controller@fe530000 { 1184 compatible = "arm,pl330", "arm,primecell"; 1185 reg = <0x0 0xfe530000 0x0 0x4000>; 1186 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1188 arm,pl330-periph-burst; 1189 clocks = <&cru ACLK_BUS>; 1190 clock-names = "apb_pclk"; 1191 #dma-cells = <1>; 1192 }; 1193 1194 dmac1: dma-controller@fe550000 { 1195 compatible = "arm,pl330", "arm,primecell"; 1196 reg = <0x0 0xfe550000 0x0 0x4000>; 1197 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1199 arm,pl330-periph-burst; 1200 clocks = <&cru ACLK_BUS>; 1201 clock-names = "apb_pclk"; 1202 #dma-cells = <1>; 1203 }; 1204 1205 i2c1: i2c@fe5a0000 { 1206 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1207 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1208 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1210 clock-names = "i2c", "pclk"; 1211 pinctrl-0 = <&i2c1_xfer>; 1212 pinctrl-names = "default"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c2: i2c@fe5b0000 { 1219 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1220 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1221 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1223 clock-names = "i2c", "pclk"; 1224 pinctrl-0 = <&i2c2m0_xfer>; 1225 pinctrl-names = "default"; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 i2c3: i2c@fe5c0000 { 1232 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1233 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1234 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1236 clock-names = "i2c", "pclk"; 1237 pinctrl-0 = <&i2c3m0_xfer>; 1238 pinctrl-names = "default"; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 status = "disabled"; 1242 }; 1243 1244 i2c4: i2c@fe5d0000 { 1245 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1246 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1247 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1249 clock-names = "i2c", "pclk"; 1250 pinctrl-0 = <&i2c4m0_xfer>; 1251 pinctrl-names = "default"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 i2c5: i2c@fe5e0000 { 1258 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1259 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1260 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1262 clock-names = "i2c", "pclk"; 1263 pinctrl-0 = <&i2c5m0_xfer>; 1264 pinctrl-names = "default"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 wdt: watchdog@fe600000 { 1271 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1272 reg = <0x0 0xfe600000 0x0 0x100>; 1273 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1275 clock-names = "tclk", "pclk"; 1276 }; 1277 1278 spi0: spi@fe610000 { 1279 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1280 reg = <0x0 0xfe610000 0x0 0x1000>; 1281 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1283 clock-names = "spiclk", "apb_pclk"; 1284 dmas = <&dmac0 20>, <&dmac0 21>; 1285 dma-names = "tx", "rx"; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 spi1: spi@fe620000 { 1294 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1295 reg = <0x0 0xfe620000 0x0 0x1000>; 1296 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1298 clock-names = "spiclk", "apb_pclk"; 1299 dmas = <&dmac0 22>, <&dmac0 23>; 1300 dma-names = "tx", "rx"; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 spi2: spi@fe630000 { 1309 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1310 reg = <0x0 0xfe630000 0x0 0x1000>; 1311 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1313 clock-names = "spiclk", "apb_pclk"; 1314 dmas = <&dmac0 24>, <&dmac0 25>; 1315 dma-names = "tx", "rx"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 spi3: spi@fe640000 { 1324 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1325 reg = <0x0 0xfe640000 0x0 0x1000>; 1326 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1328 clock-names = "spiclk", "apb_pclk"; 1329 dmas = <&dmac0 26>, <&dmac0 27>; 1330 dma-names = "tx", "rx"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 uart1: serial@fe650000 { 1339 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1340 reg = <0x0 0xfe650000 0x0 0x100>; 1341 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1343 clock-names = "baudclk", "apb_pclk"; 1344 dmas = <&dmac0 2>, <&dmac0 3>; 1345 pinctrl-0 = <&uart1m0_xfer>; 1346 pinctrl-names = "default"; 1347 reg-io-width = <4>; 1348 reg-shift = <2>; 1349 status = "disabled"; 1350 }; 1351 1352 uart2: serial@fe660000 { 1353 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1354 reg = <0x0 0xfe660000 0x0 0x100>; 1355 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1357 clock-names = "baudclk", "apb_pclk"; 1358 dmas = <&dmac0 4>, <&dmac0 5>; 1359 pinctrl-0 = <&uart2m0_xfer>; 1360 pinctrl-names = "default"; 1361 reg-io-width = <4>; 1362 reg-shift = <2>; 1363 status = "disabled"; 1364 }; 1365 1366 uart3: serial@fe670000 { 1367 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1368 reg = <0x0 0xfe670000 0x0 0x100>; 1369 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1371 clock-names = "baudclk", "apb_pclk"; 1372 dmas = <&dmac0 6>, <&dmac0 7>; 1373 pinctrl-0 = <&uart3m0_xfer>; 1374 pinctrl-names = "default"; 1375 reg-io-width = <4>; 1376 reg-shift = <2>; 1377 status = "disabled"; 1378 }; 1379 1380 uart4: serial@fe680000 { 1381 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1382 reg = <0x0 0xfe680000 0x0 0x100>; 1383 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1385 clock-names = "baudclk", "apb_pclk"; 1386 dmas = <&dmac0 8>, <&dmac0 9>; 1387 pinctrl-0 = <&uart4m0_xfer>; 1388 pinctrl-names = "default"; 1389 reg-io-width = <4>; 1390 reg-shift = <2>; 1391 status = "disabled"; 1392 }; 1393 1394 uart5: serial@fe690000 { 1395 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1396 reg = <0x0 0xfe690000 0x0 0x100>; 1397 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1399 clock-names = "baudclk", "apb_pclk"; 1400 dmas = <&dmac0 10>, <&dmac0 11>; 1401 pinctrl-0 = <&uart5m0_xfer>; 1402 pinctrl-names = "default"; 1403 reg-io-width = <4>; 1404 reg-shift = <2>; 1405 status = "disabled"; 1406 }; 1407 1408 uart6: serial@fe6a0000 { 1409 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1410 reg = <0x0 0xfe6a0000 0x0 0x100>; 1411 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1413 clock-names = "baudclk", "apb_pclk"; 1414 dmas = <&dmac0 12>, <&dmac0 13>; 1415 pinctrl-0 = <&uart6m0_xfer>; 1416 pinctrl-names = "default"; 1417 reg-io-width = <4>; 1418 reg-shift = <2>; 1419 status = "disabled"; 1420 }; 1421 1422 uart7: serial@fe6b0000 { 1423 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1424 reg = <0x0 0xfe6b0000 0x0 0x100>; 1425 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1427 clock-names = "baudclk", "apb_pclk"; 1428 dmas = <&dmac0 14>, <&dmac0 15>; 1429 pinctrl-0 = <&uart7m0_xfer>; 1430 pinctrl-names = "default"; 1431 reg-io-width = <4>; 1432 reg-shift = <2>; 1433 status = "disabled"; 1434 }; 1435 1436 uart8: serial@fe6c0000 { 1437 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1438 reg = <0x0 0xfe6c0000 0x0 0x100>; 1439 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1441 clock-names = "baudclk", "apb_pclk"; 1442 dmas = <&dmac0 16>, <&dmac0 17>; 1443 pinctrl-0 = <&uart8m0_xfer>; 1444 pinctrl-names = "default"; 1445 reg-io-width = <4>; 1446 reg-shift = <2>; 1447 status = "disabled"; 1448 }; 1449 1450 uart9: serial@fe6d0000 { 1451 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1452 reg = <0x0 0xfe6d0000 0x0 0x100>; 1453 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1454 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1455 clock-names = "baudclk", "apb_pclk"; 1456 dmas = <&dmac0 18>, <&dmac0 19>; 1457 pinctrl-0 = <&uart9m0_xfer>; 1458 pinctrl-names = "default"; 1459 reg-io-width = <4>; 1460 reg-shift = <2>; 1461 status = "disabled"; 1462 }; 1463 1464 thermal_zones: thermal-zones { 1465 cpu_thermal: cpu-thermal { 1466 polling-delay-passive = <100>; 1467 polling-delay = <1000>; 1468 1469 thermal-sensors = <&tsadc 0>; 1470 1471 trips { 1472 cpu_alert0: cpu_alert0 { 1473 temperature = <70000>; 1474 hysteresis = <2000>; 1475 type = "passive"; 1476 }; 1477 cpu_alert1: cpu_alert1 { 1478 temperature = <75000>; 1479 hysteresis = <2000>; 1480 type = "passive"; 1481 }; 1482 cpu_crit: cpu_crit { 1483 temperature = <95000>; 1484 hysteresis = <2000>; 1485 type = "critical"; 1486 }; 1487 }; 1488 1489 cooling-maps { 1490 map0 { 1491 trip = <&cpu_alert0>; 1492 cooling-device = 1493 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1494 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1495 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1496 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1497 }; 1498 }; 1499 }; 1500 1501 gpu_thermal: gpu-thermal { 1502 polling-delay-passive = <20>; /* milliseconds */ 1503 polling-delay = <1000>; /* milliseconds */ 1504 1505 thermal-sensors = <&tsadc 1>; 1506 1507 trips { 1508 gpu_threshold: gpu-threshold { 1509 temperature = <70000>; 1510 hysteresis = <2000>; 1511 type = "passive"; 1512 }; 1513 gpu_target: gpu-target { 1514 temperature = <75000>; 1515 hysteresis = <2000>; 1516 type = "passive"; 1517 }; 1518 gpu_crit: gpu-crit { 1519 temperature = <95000>; 1520 hysteresis = <2000>; 1521 type = "critical"; 1522 }; 1523 }; 1524 1525 cooling-maps { 1526 map0 { 1527 trip = <&gpu_target>; 1528 cooling-device = 1529 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1530 }; 1531 }; 1532 }; 1533 }; 1534 1535 tsadc: tsadc@fe710000 { 1536 compatible = "rockchip,rk3568-tsadc"; 1537 reg = <0x0 0xfe710000 0x0 0x100>; 1538 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1539 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1540 assigned-clock-rates = <17000000>, <700000>; 1541 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1542 clock-names = "tsadc", "apb_pclk"; 1543 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1544 <&cru SRST_TSADCPHY>; 1545 rockchip,grf = <&grf>; 1546 rockchip,hw-tshut-temp = <95000>; 1547 pinctrl-names = "init", "default", "sleep"; 1548 pinctrl-0 = <&tsadc_pin>; 1549 pinctrl-1 = <&tsadc_shutorg>; 1550 pinctrl-2 = <&tsadc_pin>; 1551 #thermal-sensor-cells = <1>; 1552 status = "disabled"; 1553 }; 1554 1555 saradc: saradc@fe720000 { 1556 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1557 reg = <0x0 0xfe720000 0x0 0x100>; 1558 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1560 clock-names = "saradc", "apb_pclk"; 1561 resets = <&cru SRST_P_SARADC>; 1562 reset-names = "saradc-apb"; 1563 #io-channel-cells = <1>; 1564 status = "disabled"; 1565 }; 1566 1567 pwm4: pwm@fe6e0000 { 1568 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1569 reg = <0x0 0xfe6e0000 0x0 0x10>; 1570 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1571 clock-names = "pwm", "pclk"; 1572 pinctrl-0 = <&pwm4_pins>; 1573 pinctrl-names = "default"; 1574 #pwm-cells = <3>; 1575 status = "disabled"; 1576 }; 1577 1578 pwm5: pwm@fe6e0010 { 1579 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1580 reg = <0x0 0xfe6e0010 0x0 0x10>; 1581 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1582 clock-names = "pwm", "pclk"; 1583 pinctrl-0 = <&pwm5_pins>; 1584 pinctrl-names = "default"; 1585 #pwm-cells = <3>; 1586 status = "disabled"; 1587 }; 1588 1589 pwm6: pwm@fe6e0020 { 1590 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1591 reg = <0x0 0xfe6e0020 0x0 0x10>; 1592 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1593 clock-names = "pwm", "pclk"; 1594 pinctrl-0 = <&pwm6_pins>; 1595 pinctrl-names = "default"; 1596 #pwm-cells = <3>; 1597 status = "disabled"; 1598 }; 1599 1600 pwm7: pwm@fe6e0030 { 1601 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1602 reg = <0x0 0xfe6e0030 0x0 0x10>; 1603 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1604 clock-names = "pwm", "pclk"; 1605 pinctrl-0 = <&pwm7_pins>; 1606 pinctrl-names = "default"; 1607 #pwm-cells = <3>; 1608 status = "disabled"; 1609 }; 1610 1611 pwm8: pwm@fe6f0000 { 1612 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1613 reg = <0x0 0xfe6f0000 0x0 0x10>; 1614 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1615 clock-names = "pwm", "pclk"; 1616 pinctrl-0 = <&pwm8m0_pins>; 1617 pinctrl-names = "default"; 1618 #pwm-cells = <3>; 1619 status = "disabled"; 1620 }; 1621 1622 pwm9: pwm@fe6f0010 { 1623 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1624 reg = <0x0 0xfe6f0010 0x0 0x10>; 1625 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1626 clock-names = "pwm", "pclk"; 1627 pinctrl-0 = <&pwm9m0_pins>; 1628 pinctrl-names = "default"; 1629 #pwm-cells = <3>; 1630 status = "disabled"; 1631 }; 1632 1633 pwm10: pwm@fe6f0020 { 1634 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1635 reg = <0x0 0xfe6f0020 0x0 0x10>; 1636 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1637 clock-names = "pwm", "pclk"; 1638 pinctrl-0 = <&pwm10m0_pins>; 1639 pinctrl-names = "default"; 1640 #pwm-cells = <3>; 1641 status = "disabled"; 1642 }; 1643 1644 pwm11: pwm@fe6f0030 { 1645 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1646 reg = <0x0 0xfe6f0030 0x0 0x10>; 1647 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1648 clock-names = "pwm", "pclk"; 1649 pinctrl-0 = <&pwm11m0_pins>; 1650 pinctrl-names = "default"; 1651 #pwm-cells = <3>; 1652 status = "disabled"; 1653 }; 1654 1655 pwm12: pwm@fe700000 { 1656 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1657 reg = <0x0 0xfe700000 0x0 0x10>; 1658 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1659 clock-names = "pwm", "pclk"; 1660 pinctrl-0 = <&pwm12m0_pins>; 1661 pinctrl-names = "default"; 1662 #pwm-cells = <3>; 1663 status = "disabled"; 1664 }; 1665 1666 pwm13: pwm@fe700010 { 1667 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1668 reg = <0x0 0xfe700010 0x0 0x10>; 1669 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1670 clock-names = "pwm", "pclk"; 1671 pinctrl-0 = <&pwm13m0_pins>; 1672 pinctrl-names = "default"; 1673 #pwm-cells = <3>; 1674 status = "disabled"; 1675 }; 1676 1677 pwm14: pwm@fe700020 { 1678 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1679 reg = <0x0 0xfe700020 0x0 0x10>; 1680 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1681 clock-names = "pwm", "pclk"; 1682 pinctrl-0 = <&pwm14m0_pins>; 1683 pinctrl-names = "default"; 1684 #pwm-cells = <3>; 1685 status = "disabled"; 1686 }; 1687 1688 pwm15: pwm@fe700030 { 1689 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1690 reg = <0x0 0xfe700030 0x0 0x10>; 1691 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1692 clock-names = "pwm", "pclk"; 1693 pinctrl-0 = <&pwm15m0_pins>; 1694 pinctrl-names = "default"; 1695 #pwm-cells = <3>; 1696 status = "disabled"; 1697 }; 1698 1699 combphy1: phy@fe830000 { 1700 compatible = "rockchip,rk3568-naneng-combphy"; 1701 reg = <0x0 0xfe830000 0x0 0x100>; 1702 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1703 <&cru PCLK_PIPEPHY1>, 1704 <&cru PCLK_PIPE>; 1705 clock-names = "ref", "apb", "pipe"; 1706 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1707 assigned-clock-rates = <100000000>; 1708 resets = <&cru SRST_PIPEPHY1>; 1709 rockchip,pipe-grf = <&pipegrf>; 1710 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1711 #phy-cells = <1>; 1712 status = "disabled"; 1713 }; 1714 1715 combphy2: phy@fe840000 { 1716 compatible = "rockchip,rk3568-naneng-combphy"; 1717 reg = <0x0 0xfe840000 0x0 0x100>; 1718 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1719 <&cru PCLK_PIPEPHY2>, 1720 <&cru PCLK_PIPE>; 1721 clock-names = "ref", "apb", "pipe"; 1722 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1723 assigned-clock-rates = <100000000>; 1724 resets = <&cru SRST_PIPEPHY2>; 1725 rockchip,pipe-grf = <&pipegrf>; 1726 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1727 #phy-cells = <1>; 1728 status = "disabled"; 1729 }; 1730 1731 csi_dphy: phy@fe870000 { 1732 compatible = "rockchip,rk3568-csi-dphy"; 1733 reg = <0x0 0xfe870000 0x0 0x10000>; 1734 clocks = <&cru PCLK_MIPICSIPHY>; 1735 clock-names = "pclk"; 1736 #phy-cells = <0>; 1737 resets = <&cru SRST_P_MIPICSIPHY>; 1738 reset-names = "apb"; 1739 rockchip,grf = <&grf>; 1740 status = "disabled"; 1741 }; 1742 1743 dsi_dphy0: mipi-dphy@fe850000 { 1744 compatible = "rockchip,rk3568-dsi-dphy"; 1745 reg = <0x0 0xfe850000 0x0 0x10000>; 1746 clock-names = "ref", "pclk"; 1747 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1748 #phy-cells = <0>; 1749 power-domains = <&power RK3568_PD_VO>; 1750 reset-names = "apb"; 1751 resets = <&cru SRST_P_MIPIDSIPHY0>; 1752 status = "disabled"; 1753 }; 1754 1755 dsi_dphy1: mipi-dphy@fe860000 { 1756 compatible = "rockchip,rk3568-dsi-dphy"; 1757 reg = <0x0 0xfe860000 0x0 0x10000>; 1758 clock-names = "ref", "pclk"; 1759 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1760 #phy-cells = <0>; 1761 power-domains = <&power RK3568_PD_VO>; 1762 reset-names = "apb"; 1763 resets = <&cru SRST_P_MIPIDSIPHY1>; 1764 status = "disabled"; 1765 }; 1766 1767 usb2phy0: usb2phy@fe8a0000 { 1768 compatible = "rockchip,rk3568-usb2phy"; 1769 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1770 clocks = <&pmucru CLK_USBPHY0_REF>; 1771 clock-names = "phyclk"; 1772 clock-output-names = "clk_usbphy0_480m"; 1773 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1774 rockchip,usbgrf = <&usb2phy0_grf>; 1775 #clock-cells = <0>; 1776 status = "disabled"; 1777 1778 usb2phy0_host: host-port { 1779 #phy-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 usb2phy0_otg: otg-port { 1784 #phy-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 }; 1788 1789 usb2phy1: usb2phy@fe8b0000 { 1790 compatible = "rockchip,rk3568-usb2phy"; 1791 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1792 clocks = <&pmucru CLK_USBPHY1_REF>; 1793 clock-names = "phyclk"; 1794 clock-output-names = "clk_usbphy1_480m"; 1795 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1796 rockchip,usbgrf = <&usb2phy1_grf>; 1797 #clock-cells = <0>; 1798 status = "disabled"; 1799 1800 usb2phy1_host: host-port { 1801 #phy-cells = <0>; 1802 status = "disabled"; 1803 }; 1804 1805 usb2phy1_otg: otg-port { 1806 #phy-cells = <0>; 1807 status = "disabled"; 1808 }; 1809 }; 1810 1811 pinctrl: pinctrl { 1812 compatible = "rockchip,rk3568-pinctrl"; 1813 rockchip,grf = <&grf>; 1814 rockchip,pmu = <&pmugrf>; 1815 #address-cells = <2>; 1816 #size-cells = <2>; 1817 ranges; 1818 1819 gpio0: gpio@fdd60000 { 1820 compatible = "rockchip,gpio-bank"; 1821 reg = <0x0 0xfdd60000 0x0 0x100>; 1822 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1824 gpio-controller; 1825 gpio-ranges = <&pinctrl 0 0 32>; 1826 #gpio-cells = <2>; 1827 interrupt-controller; 1828 #interrupt-cells = <2>; 1829 }; 1830 1831 gpio1: gpio@fe740000 { 1832 compatible = "rockchip,gpio-bank"; 1833 reg = <0x0 0xfe740000 0x0 0x100>; 1834 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1835 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1836 gpio-controller; 1837 gpio-ranges = <&pinctrl 0 32 32>; 1838 #gpio-cells = <2>; 1839 interrupt-controller; 1840 #interrupt-cells = <2>; 1841 }; 1842 1843 gpio2: gpio@fe750000 { 1844 compatible = "rockchip,gpio-bank"; 1845 reg = <0x0 0xfe750000 0x0 0x100>; 1846 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1848 gpio-controller; 1849 gpio-ranges = <&pinctrl 0 64 32>; 1850 #gpio-cells = <2>; 1851 interrupt-controller; 1852 #interrupt-cells = <2>; 1853 }; 1854 1855 gpio3: gpio@fe760000 { 1856 compatible = "rockchip,gpio-bank"; 1857 reg = <0x0 0xfe760000 0x0 0x100>; 1858 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1859 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1860 gpio-controller; 1861 gpio-ranges = <&pinctrl 0 96 32>; 1862 #gpio-cells = <2>; 1863 interrupt-controller; 1864 #interrupt-cells = <2>; 1865 }; 1866 1867 gpio4: gpio@fe770000 { 1868 compatible = "rockchip,gpio-bank"; 1869 reg = <0x0 0xfe770000 0x0 0x100>; 1870 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1871 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1872 gpio-controller; 1873 gpio-ranges = <&pinctrl 0 128 32>; 1874 #gpio-cells = <2>; 1875 interrupt-controller; 1876 #interrupt-cells = <2>; 1877 }; 1878 }; 1879}; 1880 1881#include "rk3568-pinctrl.dtsi" 1882