xref: /openbmc/linux/drivers/gpio/gpio-pxa.c (revision f0575116)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/arch/arm/plat-pxa/gpio.c
4  *
5  *  Generic PXA GPIO handling
6  *
7  *  Author:	Nicolas Pitre
8  *  Created:	Jun 15, 2001
9  *  Copyright:	MontaVista Software Inc.
10  */
11 #include <linux/module.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio-pxa.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/slab.h>
27 
28 /*
29  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
30  * one set of registers. The register offsets are organized below:
31  *
32  *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
33  * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
34  * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
35  * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
36  *
37  * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
38  * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
39  * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
40  *
41  * BANK 6 - 0x0200  0x020C  0x0218  0x0224  0x0230  0x023C  0x0248
42  *
43  * NOTE:
44  *   BANK 3 is only available on PXA27x and later processors.
45  *   BANK 4 and 5 are only available on PXA935, PXA1928
46  *   BANK 6 is only available on PXA1928
47  */
48 
49 #define GPLR_OFFSET	0x00
50 #define GPDR_OFFSET	0x0C
51 #define GPSR_OFFSET	0x18
52 #define GPCR_OFFSET	0x24
53 #define GRER_OFFSET	0x30
54 #define GFER_OFFSET	0x3C
55 #define GEDR_OFFSET	0x48
56 #define GAFR_OFFSET	0x54
57 #define ED_MASK_OFFSET	0x9C	/* GPIO edge detection for AP side */
58 
59 #define BANK_OFF(n)	(((n) / 3) << 8) + (((n) % 3) << 2)
60 
61 int pxa_last_gpio;
62 static int irq_base;
63 
64 struct pxa_gpio_bank {
65 	void __iomem	*regbase;
66 	unsigned long	irq_mask;
67 	unsigned long	irq_edge_rise;
68 	unsigned long	irq_edge_fall;
69 
70 #ifdef CONFIG_PM
71 	unsigned long	saved_gplr;
72 	unsigned long	saved_gpdr;
73 	unsigned long	saved_grer;
74 	unsigned long	saved_gfer;
75 #endif
76 };
77 
78 struct pxa_gpio_chip {
79 	struct device *dev;
80 	struct gpio_chip chip;
81 	struct pxa_gpio_bank *banks;
82 	struct irq_domain *irqdomain;
83 
84 	int irq0;
85 	int irq1;
86 	int (*set_wake)(unsigned int gpio, unsigned int on);
87 };
88 
89 enum pxa_gpio_type {
90 	PXA25X_GPIO = 0,
91 	PXA26X_GPIO,
92 	PXA27X_GPIO,
93 	PXA3XX_GPIO,
94 	PXA93X_GPIO,
95 	MMP_GPIO = 0x10,
96 	MMP2_GPIO,
97 	PXA1928_GPIO,
98 };
99 
100 struct pxa_gpio_id {
101 	enum pxa_gpio_type	type;
102 	int			gpio_nums;
103 };
104 
105 static DEFINE_SPINLOCK(gpio_lock);
106 static struct pxa_gpio_chip *pxa_gpio_chip;
107 static enum pxa_gpio_type gpio_type;
108 
109 static struct pxa_gpio_id pxa25x_id = {
110 	.type		= PXA25X_GPIO,
111 	.gpio_nums	= 85,
112 };
113 
114 static struct pxa_gpio_id pxa26x_id = {
115 	.type		= PXA26X_GPIO,
116 	.gpio_nums	= 90,
117 };
118 
119 static struct pxa_gpio_id pxa27x_id = {
120 	.type		= PXA27X_GPIO,
121 	.gpio_nums	= 121,
122 };
123 
124 static struct pxa_gpio_id pxa3xx_id = {
125 	.type		= PXA3XX_GPIO,
126 	.gpio_nums	= 128,
127 };
128 
129 static struct pxa_gpio_id pxa93x_id = {
130 	.type		= PXA93X_GPIO,
131 	.gpio_nums	= 192,
132 };
133 
134 static struct pxa_gpio_id mmp_id = {
135 	.type		= MMP_GPIO,
136 	.gpio_nums	= 128,
137 };
138 
139 static struct pxa_gpio_id mmp2_id = {
140 	.type		= MMP2_GPIO,
141 	.gpio_nums	= 192,
142 };
143 
144 static struct pxa_gpio_id pxa1928_id = {
145 	.type		= PXA1928_GPIO,
146 	.gpio_nums	= 224,
147 };
148 
149 #define for_each_gpio_bank(i, b, pc)					\
150 	for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
151 
chip_to_pxachip(struct gpio_chip * c)152 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
153 {
154 	struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
155 
156 	return pxa_chip;
157 }
158 
gpio_bank_base(struct gpio_chip * c,int gpio)159 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
160 {
161 	struct pxa_gpio_chip *p = gpiochip_get_data(c);
162 	struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
163 
164 	return bank->regbase;
165 }
166 
gpio_to_pxabank(struct gpio_chip * c,unsigned gpio)167 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
168 						    unsigned gpio)
169 {
170 	return chip_to_pxachip(c)->banks + gpio / 32;
171 }
172 
gpio_is_mmp_type(int type)173 static inline int gpio_is_mmp_type(int type)
174 {
175 	return (type & MMP_GPIO) != 0;
176 }
177 
178 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
179  * as well as their Alternate Function value being '1' for GPIO in GAFRx.
180  */
__gpio_is_inverted(int gpio)181 static inline int __gpio_is_inverted(int gpio)
182 {
183 	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
184 		return 1;
185 	return 0;
186 }
187 
188 /*
189  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
190  * function of a GPIO, and GPDRx cannot be altered once configured. It
191  * is attributed as "occupied" here (I know this terminology isn't
192  * accurate, you are welcome to propose a better one :-)
193  */
__gpio_is_occupied(struct pxa_gpio_chip * pchip,unsigned gpio)194 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
195 {
196 	void __iomem *base;
197 	unsigned long gafr = 0, gpdr = 0;
198 	int ret, af = 0, dir = 0;
199 
200 	base = gpio_bank_base(&pchip->chip, gpio);
201 	gpdr = readl_relaxed(base + GPDR_OFFSET);
202 
203 	switch (gpio_type) {
204 	case PXA25X_GPIO:
205 	case PXA26X_GPIO:
206 	case PXA27X_GPIO:
207 		gafr = readl_relaxed(base + GAFR_OFFSET);
208 		af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
209 		dir = gpdr & GPIO_bit(gpio);
210 
211 		if (__gpio_is_inverted(gpio))
212 			ret = (af != 1) || (dir == 0);
213 		else
214 			ret = (af != 0) || (dir != 0);
215 		break;
216 	default:
217 		ret = gpdr & GPIO_bit(gpio);
218 		break;
219 	}
220 	return ret;
221 }
222 
pxa_irq_to_gpio(int irq)223 int pxa_irq_to_gpio(int irq)
224 {
225 	struct pxa_gpio_chip *pchip = pxa_gpio_chip;
226 	int irq_gpio0;
227 
228 	irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
229 	if (irq_gpio0 > 0)
230 		return irq - irq_gpio0;
231 
232 	return irq_gpio0;
233 }
234 
pxa_gpio_has_pinctrl(void)235 static bool pxa_gpio_has_pinctrl(void)
236 {
237 	switch (gpio_type) {
238 	case PXA3XX_GPIO:
239 	case MMP2_GPIO:
240 	case MMP_GPIO:
241 		return false;
242 
243 	default:
244 		return true;
245 	}
246 }
247 
pxa_gpio_to_irq(struct gpio_chip * chip,unsigned offset)248 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
249 {
250 	struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
251 
252 	return irq_find_mapping(pchip->irqdomain, offset);
253 }
254 
pxa_gpio_direction_input(struct gpio_chip * chip,unsigned offset)255 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
256 {
257 	void __iomem *base = gpio_bank_base(chip, offset);
258 	uint32_t value, mask = GPIO_bit(offset);
259 	unsigned long flags;
260 	int ret;
261 
262 	if (pxa_gpio_has_pinctrl()) {
263 		ret = pinctrl_gpio_direction_input(chip->base + offset);
264 		if (ret)
265 			return ret;
266 	}
267 
268 	spin_lock_irqsave(&gpio_lock, flags);
269 
270 	value = readl_relaxed(base + GPDR_OFFSET);
271 	if (__gpio_is_inverted(chip->base + offset))
272 		value |= mask;
273 	else
274 		value &= ~mask;
275 	writel_relaxed(value, base + GPDR_OFFSET);
276 
277 	spin_unlock_irqrestore(&gpio_lock, flags);
278 	return 0;
279 }
280 
pxa_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)281 static int pxa_gpio_direction_output(struct gpio_chip *chip,
282 				     unsigned offset, int value)
283 {
284 	void __iomem *base = gpio_bank_base(chip, offset);
285 	uint32_t tmp, mask = GPIO_bit(offset);
286 	unsigned long flags;
287 	int ret;
288 
289 	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
290 
291 	if (pxa_gpio_has_pinctrl()) {
292 		ret = pinctrl_gpio_direction_output(chip->base + offset);
293 		if (ret)
294 			return ret;
295 	}
296 
297 	spin_lock_irqsave(&gpio_lock, flags);
298 
299 	tmp = readl_relaxed(base + GPDR_OFFSET);
300 	if (__gpio_is_inverted(chip->base + offset))
301 		tmp &= ~mask;
302 	else
303 		tmp |= mask;
304 	writel_relaxed(tmp, base + GPDR_OFFSET);
305 
306 	spin_unlock_irqrestore(&gpio_lock, flags);
307 	return 0;
308 }
309 
pxa_gpio_get(struct gpio_chip * chip,unsigned offset)310 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
311 {
312 	void __iomem *base = gpio_bank_base(chip, offset);
313 	u32 gplr = readl_relaxed(base + GPLR_OFFSET);
314 
315 	return !!(gplr & GPIO_bit(offset));
316 }
317 
pxa_gpio_set(struct gpio_chip * chip,unsigned offset,int value)318 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
319 {
320 	void __iomem *base = gpio_bank_base(chip, offset);
321 
322 	writel_relaxed(GPIO_bit(offset),
323 		       base + (value ? GPSR_OFFSET : GPCR_OFFSET));
324 }
325 
326 #ifdef CONFIG_OF_GPIO
pxa_gpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)327 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
328 			     const struct of_phandle_args *gpiospec,
329 			     u32 *flags)
330 {
331 	if (gpiospec->args[0] > pxa_last_gpio)
332 		return -EINVAL;
333 
334 	if (flags)
335 		*flags = gpiospec->args[1];
336 
337 	return gpiospec->args[0];
338 }
339 #endif
340 
pxa_init_gpio_chip(struct pxa_gpio_chip * pchip,int ngpio,void __iomem * regbase)341 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
342 {
343 	int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
344 	struct pxa_gpio_bank *bank;
345 
346 	pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
347 				    GFP_KERNEL);
348 	if (!pchip->banks)
349 		return -ENOMEM;
350 
351 	pchip->chip.parent = pchip->dev;
352 	pchip->chip.label = "gpio-pxa";
353 	pchip->chip.direction_input  = pxa_gpio_direction_input;
354 	pchip->chip.direction_output = pxa_gpio_direction_output;
355 	pchip->chip.get = pxa_gpio_get;
356 	pchip->chip.set = pxa_gpio_set;
357 	pchip->chip.to_irq = pxa_gpio_to_irq;
358 	pchip->chip.ngpio = ngpio;
359 	pchip->chip.request = gpiochip_generic_request;
360 	pchip->chip.free = gpiochip_generic_free;
361 
362 #ifdef CONFIG_OF_GPIO
363 	pchip->chip.of_xlate = pxa_gpio_of_xlate;
364 	pchip->chip.of_gpio_n_cells = 2;
365 #endif
366 
367 	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
368 		bank = pchip->banks + i;
369 		bank->regbase = regbase + BANK_OFF(i);
370 	}
371 
372 	return gpiochip_add_data(&pchip->chip, pchip);
373 }
374 
375 /* Update only those GRERx and GFERx edge detection register bits if those
376  * bits are set in c->irq_mask
377  */
update_edge_detect(struct pxa_gpio_bank * c)378 static inline void update_edge_detect(struct pxa_gpio_bank *c)
379 {
380 	uint32_t grer, gfer;
381 
382 	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
383 	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
384 	grer |= c->irq_edge_rise & c->irq_mask;
385 	gfer |= c->irq_edge_fall & c->irq_mask;
386 	writel_relaxed(grer, c->regbase + GRER_OFFSET);
387 	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
388 }
389 
pxa_gpio_irq_type(struct irq_data * d,unsigned int type)390 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
391 {
392 	struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
393 	unsigned int gpio = irqd_to_hwirq(d);
394 	struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
395 	unsigned long gpdr, mask = GPIO_bit(gpio);
396 
397 	if (type == IRQ_TYPE_PROBE) {
398 		/* Don't mess with enabled GPIOs using preconfigured edges or
399 		 * GPIOs set to alternate function or to output during probe
400 		 */
401 		if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
402 			return 0;
403 
404 		if (__gpio_is_occupied(pchip, gpio))
405 			return 0;
406 
407 		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
408 	}
409 
410 	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
411 
412 	if (__gpio_is_inverted(gpio))
413 		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
414 	else
415 		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
416 
417 	if (type & IRQ_TYPE_EDGE_RISING)
418 		c->irq_edge_rise |= mask;
419 	else
420 		c->irq_edge_rise &= ~mask;
421 
422 	if (type & IRQ_TYPE_EDGE_FALLING)
423 		c->irq_edge_fall |= mask;
424 	else
425 		c->irq_edge_fall &= ~mask;
426 
427 	update_edge_detect(c);
428 
429 	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
430 		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
431 		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
432 	return 0;
433 }
434 
pxa_gpio_demux_handler(int in_irq,void * d)435 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
436 {
437 	int loop, gpio, n, handled = 0;
438 	unsigned long gedr;
439 	struct pxa_gpio_chip *pchip = d;
440 	struct pxa_gpio_bank *c;
441 
442 	do {
443 		loop = 0;
444 		for_each_gpio_bank(gpio, c, pchip) {
445 			gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
446 			gedr = gedr & c->irq_mask;
447 			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
448 
449 			for_each_set_bit(n, &gedr, BITS_PER_LONG) {
450 				loop = 1;
451 
452 				generic_handle_domain_irq(pchip->irqdomain,
453 							  gpio + n);
454 			}
455 		}
456 		handled += loop;
457 	} while (loop);
458 
459 	return handled ? IRQ_HANDLED : IRQ_NONE;
460 }
461 
pxa_gpio_direct_handler(int in_irq,void * d)462 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
463 {
464 	struct pxa_gpio_chip *pchip = d;
465 
466 	if (in_irq == pchip->irq0) {
467 		generic_handle_domain_irq(pchip->irqdomain, 0);
468 	} else if (in_irq == pchip->irq1) {
469 		generic_handle_domain_irq(pchip->irqdomain, 1);
470 	} else {
471 		pr_err("%s() unknown irq %d\n", __func__, in_irq);
472 		return IRQ_NONE;
473 	}
474 	return IRQ_HANDLED;
475 }
476 
pxa_ack_muxed_gpio(struct irq_data * d)477 static void pxa_ack_muxed_gpio(struct irq_data *d)
478 {
479 	struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
480 	unsigned int gpio = irqd_to_hwirq(d);
481 	void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
482 
483 	writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
484 }
485 
pxa_mask_muxed_gpio(struct irq_data * d)486 static void pxa_mask_muxed_gpio(struct irq_data *d)
487 {
488 	struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
489 	unsigned int gpio = irqd_to_hwirq(d);
490 	struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
491 	void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
492 	uint32_t grer, gfer;
493 
494 	b->irq_mask &= ~GPIO_bit(gpio);
495 
496 	grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
497 	gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
498 	writel_relaxed(grer, base + GRER_OFFSET);
499 	writel_relaxed(gfer, base + GFER_OFFSET);
500 }
501 
pxa_gpio_set_wake(struct irq_data * d,unsigned int on)502 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
503 {
504 	struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
505 	unsigned int gpio = irqd_to_hwirq(d);
506 
507 	if (pchip->set_wake)
508 		return pchip->set_wake(gpio, on);
509 	else
510 		return 0;
511 }
512 
pxa_unmask_muxed_gpio(struct irq_data * d)513 static void pxa_unmask_muxed_gpio(struct irq_data *d)
514 {
515 	struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
516 	unsigned int gpio = irqd_to_hwirq(d);
517 	struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
518 
519 	c->irq_mask |= GPIO_bit(gpio);
520 	update_edge_detect(c);
521 }
522 
523 static struct irq_chip pxa_muxed_gpio_chip = {
524 	.name		= "GPIO",
525 	.irq_ack	= pxa_ack_muxed_gpio,
526 	.irq_mask	= pxa_mask_muxed_gpio,
527 	.irq_unmask	= pxa_unmask_muxed_gpio,
528 	.irq_set_type	= pxa_gpio_irq_type,
529 	.irq_set_wake	= pxa_gpio_set_wake,
530 };
531 
pxa_gpio_nums(struct platform_device * pdev)532 static int pxa_gpio_nums(struct platform_device *pdev)
533 {
534 	const struct platform_device_id *id = platform_get_device_id(pdev);
535 	struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
536 	int count = 0;
537 
538 	switch (pxa_id->type) {
539 	case PXA25X_GPIO:
540 	case PXA26X_GPIO:
541 	case PXA27X_GPIO:
542 	case PXA3XX_GPIO:
543 	case PXA93X_GPIO:
544 	case MMP_GPIO:
545 	case MMP2_GPIO:
546 	case PXA1928_GPIO:
547 		gpio_type = pxa_id->type;
548 		count = pxa_id->gpio_nums - 1;
549 		break;
550 	default:
551 		count = -EINVAL;
552 		break;
553 	}
554 	return count;
555 }
556 
pxa_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)557 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
558 			      irq_hw_number_t hw)
559 {
560 	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
561 				 handle_edge_irq);
562 	irq_set_chip_data(irq, d->host_data);
563 	irq_set_noprobe(irq);
564 	return 0;
565 }
566 
567 static const struct irq_domain_ops pxa_irq_domain_ops = {
568 	.map	= pxa_irq_domain_map,
569 	.xlate	= irq_domain_xlate_twocell,
570 };
571 
572 #ifdef CONFIG_OF
573 static const struct of_device_id pxa_gpio_dt_ids[] = {
574 	{ .compatible = "intel,pxa25x-gpio",	.data = &pxa25x_id, },
575 	{ .compatible = "intel,pxa26x-gpio",	.data = &pxa26x_id, },
576 	{ .compatible = "intel,pxa27x-gpio",	.data = &pxa27x_id, },
577 	{ .compatible = "intel,pxa3xx-gpio",	.data = &pxa3xx_id, },
578 	{ .compatible = "marvell,pxa93x-gpio",	.data = &pxa93x_id, },
579 	{ .compatible = "marvell,mmp-gpio",	.data = &mmp_id, },
580 	{ .compatible = "marvell,mmp2-gpio",	.data = &mmp2_id, },
581 	{ .compatible = "marvell,pxa1928-gpio",	.data = &pxa1928_id, },
582 	{}
583 };
584 
pxa_gpio_probe_dt(struct platform_device * pdev,struct pxa_gpio_chip * pchip)585 static int pxa_gpio_probe_dt(struct platform_device *pdev,
586 			     struct pxa_gpio_chip *pchip)
587 {
588 	int nr_gpios;
589 	const struct pxa_gpio_id *gpio_id;
590 
591 	gpio_id = of_device_get_match_data(&pdev->dev);
592 	gpio_type = gpio_id->type;
593 
594 	nr_gpios = gpio_id->gpio_nums;
595 	pxa_last_gpio = nr_gpios - 1;
596 
597 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
598 	if (irq_base < 0) {
599 		dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
600 		return irq_base;
601 	}
602 	return irq_base;
603 }
604 #else
605 #define pxa_gpio_probe_dt(pdev, pchip)		(-1)
606 #endif
607 
pxa_gpio_probe(struct platform_device * pdev)608 static int pxa_gpio_probe(struct platform_device *pdev)
609 {
610 	struct pxa_gpio_chip *pchip;
611 	struct pxa_gpio_bank *c;
612 	struct clk *clk;
613 	struct pxa_gpio_platform_data *info;
614 	void __iomem *gpio_reg_base;
615 	int gpio, ret;
616 	int irq0 = 0, irq1 = 0, irq_mux;
617 
618 	pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
619 	if (!pchip)
620 		return -ENOMEM;
621 	pchip->dev = &pdev->dev;
622 
623 	info = dev_get_platdata(&pdev->dev);
624 	if (info) {
625 		irq_base = info->irq_base;
626 		if (irq_base <= 0)
627 			return -EINVAL;
628 		pxa_last_gpio = pxa_gpio_nums(pdev);
629 		pchip->set_wake = info->gpio_set_wake;
630 	} else {
631 		irq_base = pxa_gpio_probe_dt(pdev, pchip);
632 		if (irq_base < 0)
633 			return -EINVAL;
634 	}
635 
636 	if (!pxa_last_gpio)
637 		return -EINVAL;
638 
639 	pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
640 						 pxa_last_gpio + 1, irq_base,
641 						 0, &pxa_irq_domain_ops, pchip);
642 	if (!pchip->irqdomain)
643 		return -ENOMEM;
644 
645 	irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
646 	irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
647 	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
648 	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
649 		|| (irq_mux <= 0))
650 		return -EINVAL;
651 
652 	pchip->irq0 = irq0;
653 	pchip->irq1 = irq1;
654 
655 	gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
656 	if (IS_ERR(gpio_reg_base))
657 		return PTR_ERR(gpio_reg_base);
658 
659 	clk = devm_clk_get_enabled(&pdev->dev, NULL);
660 	if (IS_ERR(clk)) {
661 		dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
662 			PTR_ERR(clk));
663 		return PTR_ERR(clk);
664 	}
665 
666 	/* Initialize GPIO chips */
667 	ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
668 	if (ret)
669 		return ret;
670 
671 	/* clear all GPIO edge detects */
672 	for_each_gpio_bank(gpio, c, pchip) {
673 		writel_relaxed(0, c->regbase + GFER_OFFSET);
674 		writel_relaxed(0, c->regbase + GRER_OFFSET);
675 		writel_relaxed(~0, c->regbase + GEDR_OFFSET);
676 		/* unmask GPIO edge detect for AP side */
677 		if (gpio_is_mmp_type(gpio_type))
678 			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
679 	}
680 
681 	if (irq0 > 0) {
682 		ret = devm_request_irq(&pdev->dev,
683 				       irq0, pxa_gpio_direct_handler, 0,
684 				       "gpio-0", pchip);
685 		if (ret)
686 			dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
687 				ret);
688 	}
689 	if (irq1 > 0) {
690 		ret = devm_request_irq(&pdev->dev,
691 				       irq1, pxa_gpio_direct_handler, 0,
692 				       "gpio-1", pchip);
693 		if (ret)
694 			dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
695 				ret);
696 	}
697 	ret = devm_request_irq(&pdev->dev,
698 			       irq_mux, pxa_gpio_demux_handler, 0,
699 				       "gpio-mux", pchip);
700 	if (ret)
701 		dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
702 				ret);
703 
704 	pxa_gpio_chip = pchip;
705 
706 	return 0;
707 }
708 
709 static const struct platform_device_id gpio_id_table[] = {
710 	{ "pxa25x-gpio",	(unsigned long)&pxa25x_id },
711 	{ "pxa26x-gpio",	(unsigned long)&pxa26x_id },
712 	{ "pxa27x-gpio",	(unsigned long)&pxa27x_id },
713 	{ "pxa3xx-gpio",	(unsigned long)&pxa3xx_id },
714 	{ "pxa93x-gpio",	(unsigned long)&pxa93x_id },
715 	{ "mmp-gpio",		(unsigned long)&mmp_id },
716 	{ "mmp2-gpio",		(unsigned long)&mmp2_id },
717 	{ "pxa1928-gpio",	(unsigned long)&pxa1928_id },
718 	{ },
719 };
720 
721 static struct platform_driver pxa_gpio_driver = {
722 	.probe		= pxa_gpio_probe,
723 	.driver		= {
724 		.name	= "pxa-gpio",
725 		.of_match_table = of_match_ptr(pxa_gpio_dt_ids),
726 	},
727 	.id_table	= gpio_id_table,
728 };
729 
pxa_gpio_legacy_init(void)730 static int __init pxa_gpio_legacy_init(void)
731 {
732 	if (of_have_populated_dt())
733 		return 0;
734 
735 	return platform_driver_register(&pxa_gpio_driver);
736 }
737 postcore_initcall(pxa_gpio_legacy_init);
738 
pxa_gpio_dt_init(void)739 static int __init pxa_gpio_dt_init(void)
740 {
741 	if (of_have_populated_dt())
742 		return platform_driver_register(&pxa_gpio_driver);
743 
744 	return 0;
745 }
746 device_initcall(pxa_gpio_dt_init);
747 
748 #ifdef CONFIG_PM
pxa_gpio_suspend(void)749 static int pxa_gpio_suspend(void)
750 {
751 	struct pxa_gpio_chip *pchip = pxa_gpio_chip;
752 	struct pxa_gpio_bank *c;
753 	int gpio;
754 
755 	if (!pchip)
756 		return 0;
757 
758 	for_each_gpio_bank(gpio, c, pchip) {
759 		c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
760 		c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
761 		c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
762 		c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
763 
764 		/* Clear GPIO transition detect bits */
765 		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
766 	}
767 	return 0;
768 }
769 
pxa_gpio_resume(void)770 static void pxa_gpio_resume(void)
771 {
772 	struct pxa_gpio_chip *pchip = pxa_gpio_chip;
773 	struct pxa_gpio_bank *c;
774 	int gpio;
775 
776 	if (!pchip)
777 		return;
778 
779 	for_each_gpio_bank(gpio, c, pchip) {
780 		/* restore level with set/clear */
781 		writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
782 		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
783 
784 		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
785 		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
786 		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
787 	}
788 }
789 #else
790 #define pxa_gpio_suspend	NULL
791 #define pxa_gpio_resume		NULL
792 #endif
793 
794 static struct syscore_ops pxa_gpio_syscore_ops = {
795 	.suspend	= pxa_gpio_suspend,
796 	.resume		= pxa_gpio_resume,
797 };
798 
pxa_gpio_sysinit(void)799 static int __init pxa_gpio_sysinit(void)
800 {
801 	register_syscore_ops(&pxa_gpio_syscore_ops);
802 	return 0;
803 }
804 postcore_initcall(pxa_gpio_sysinit);
805