1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; 3 power-domains = <&prm_wkup>; 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 10 reg-names = "ap", "la", "ia0", "ia1"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 16 17 segment@0 { /* 0x44c00000 */ 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 24 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 25 }; 26 27 segment@100000 { /* 0x44d00000 */ 28 compatible = "simple-pm-bus"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 32 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 33 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 34 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 35 36 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 37 compatible = "ti,sysc-omap4", "ti,sysc"; 38 reg = <0x0 0x4>; 39 reg-names = "rev"; 40 clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; 41 clock-names = "fck"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x00000000 0x00000000 0x4000>, 45 <0x00080000 0x00080000 0x2000>; 46 47 wkup_m3: cpu@0 { 48 compatible = "ti,am3352-wkup-m3"; 49 reg = <0x00000000 0x4000>, 50 <0x00080000 0x2000>; 51 reg-names = "umem", "dmem"; 52 resets = <&prm_wkup 3>; 53 reset-names = "rstctrl"; 54 ti,pm-firmware = "am335x-pm-firmware.elf"; 55 }; 56 }; 57 }; 58 59 segment@200000 { /* 0x44e00000 */ 60 compatible = "simple-pm-bus"; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 64 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 65 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 66 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 67 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 68 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 69 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 70 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 71 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 72 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 73 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 74 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 75 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 76 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 77 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 78 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 79 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 80 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 81 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 82 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 83 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 84 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 85 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 86 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 87 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 88 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 89 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 90 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 91 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 92 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 93 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 94 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 95 96 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 97 compatible = "ti,sysc-omap4", "ti,sysc"; 98 reg = <0 0x4>; 99 reg-names = "rev"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0x0 0x0 0x2000>; 103 104 prcm: prcm@0 { 105 compatible = "ti,am3-prcm", "simple-bus"; 106 reg = <0 0x2000>; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0 0x2000>; 110 111 prcm_clocks: clocks { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 }; 115 116 prcm_clockdomains: clockdomains { 117 }; 118 }; 119 }; 120 121 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 122 compatible = "ti,sysc"; 123 status = "disabled"; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 ranges = <0x0 0x3000 0x1000>; 127 }; 128 129 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 130 compatible = "ti,sysc"; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges = <0x0 0x5000 0x1000>; 135 }; 136 137 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 138 compatible = "ti,sysc-omap2", "ti,sysc"; 139 reg = <0x7000 0x4>, 140 <0x7010 0x4>, 141 <0x7114 0x4>; 142 reg-names = "rev", "sysc", "syss"; 143 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 144 SYSC_OMAP2_SOFTRESET | 145 SYSC_OMAP2_AUTOIDLE)>; 146 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 147 <SYSC_IDLE_NO>, 148 <SYSC_IDLE_SMART>, 149 <SYSC_IDLE_SMART_WKUP>; 150 ti,syss-mask = <1>; 151 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 152 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 153 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 154 clock-names = "fck", "dbclk"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0x0 0x7000 0x1000>; 158 159 gpio0: gpio@0 { 160 compatible = "ti,omap4-gpio"; 161 gpio-ranges = <&am33xx_pinmux 0 82 8>, 162 <&am33xx_pinmux 8 52 4>, 163 <&am33xx_pinmux 12 94 4>, 164 <&am33xx_pinmux 16 71 2>, 165 <&am33xx_pinmux 18 135 1>, 166 <&am33xx_pinmux 19 108 2>, 167 <&am33xx_pinmux 21 73 1>, 168 <&am33xx_pinmux 22 8 2>, 169 <&am33xx_pinmux 26 10 2>, 170 <&am33xx_pinmux 28 74 1>, 171 <&am33xx_pinmux 29 81 1>, 172 <&am33xx_pinmux 30 28 2>; 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 reg = <0x0 0x1000>; 178 interrupts = <96>; 179 }; 180 }; 181 182 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 183 compatible = "ti,sysc-omap2", "ti,sysc"; 184 reg = <0x9050 0x4>, 185 <0x9054 0x4>, 186 <0x9058 0x4>; 187 reg-names = "rev", "sysc", "syss"; 188 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 189 SYSC_OMAP2_SOFTRESET | 190 SYSC_OMAP2_AUTOIDLE)>; 191 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 192 <SYSC_IDLE_NO>, 193 <SYSC_IDLE_SMART>, 194 <SYSC_IDLE_SMART_WKUP>; 195 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 196 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 197 clock-names = "fck"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0x0 0x9000 0x1000>; 201 202 uart0: serial@0 { 203 compatible = "ti,am3352-uart", "ti,omap3-uart"; 204 clock-frequency = <48000000>; 205 reg = <0x0 0x1000>; 206 interrupts = <72>; 207 status = "disabled"; 208 dmas = <&edma 26 0>, <&edma 27 0>; 209 dma-names = "tx", "rx"; 210 }; 211 }; 212 213 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 214 compatible = "ti,sysc-omap2", "ti,sysc"; 215 reg = <0xb000 0x8>, 216 <0xb010 0x8>, 217 <0xb090 0x8>; 218 reg-names = "rev", "sysc", "syss"; 219 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 220 SYSC_OMAP2_ENAWAKEUP | 221 SYSC_OMAP2_SOFTRESET | 222 SYSC_OMAP2_AUTOIDLE)>; 223 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224 <SYSC_IDLE_NO>, 225 <SYSC_IDLE_SMART>, 226 <SYSC_IDLE_SMART_WKUP>; 227 ti,syss-mask = <1>; 228 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 229 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 230 clock-names = "fck"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0x0 0xb000 0x1000>; 234 235 i2c0: i2c@0 { 236 compatible = "ti,omap4-i2c"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 reg = <0x0 0x1000>; 240 interrupts = <70>; 241 status = "disabled"; 242 }; 243 }; 244 245 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 246 compatible = "ti,sysc-omap4", "ti,sysc"; 247 reg = <0xd000 0x4>, 248 <0xd010 0x4>; 249 reg-names = "rev", "sysc"; 250 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 251 <SYSC_IDLE_NO>, 252 <SYSC_IDLE_SMART>, 253 <SYSC_IDLE_SMART_WKUP>; 254 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 255 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 256 clock-names = "fck"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0x00000000 0x0000d000 0x00001000>, 260 <0x00001000 0x0000e000 0x00001000>; 261 262 tscadc: tscadc@0 { 263 compatible = "ti,am3359-tscadc"; 264 reg = <0x0 0x1000>; 265 interrupts = <16>; 266 clocks = <&adc_tsc_fck>; 267 clock-names = "fck"; 268 status = "disabled"; 269 dmas = <&edma 53 0>, <&edma 57 0>; 270 dma-names = "fifo0", "fifo1"; 271 272 tsc { 273 compatible = "ti,am3359-tsc"; 274 }; 275 am335x_adc: adc { 276 #io-channel-cells = <1>; 277 compatible = "ti,am3359-adc"; 278 }; 279 }; 280 }; 281 282 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 283 compatible = "ti,sysc-omap4", "ti,sysc"; 284 reg = <0x10000 0x4>; 285 reg-names = "rev"; 286 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; 287 clock-names = "fck"; 288 ti,no-idle; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0x00000000 0x00010000 0x00010000>, 292 <0x00010000 0x00020000 0x00010000>; 293 294 scm: scm@0 { 295 compatible = "ti,am3-scm", "simple-bus"; 296 reg = <0x0 0x2000>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 #pinctrl-cells = <1>; 300 ranges = <0 0 0x2000>; 301 302 am33xx_pinmux: pinmux@800 { 303 compatible = "pinctrl-single"; 304 reg = <0x800 0x238>; 305 #pinctrl-cells = <2>; 306 pinctrl-single,register-width = <32>; 307 pinctrl-single,function-mask = <0x7f>; 308 }; 309 310 scm_conf: scm_conf@0 { 311 compatible = "syscon", "simple-bus"; 312 reg = <0x0 0x800>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0 0x800>; 316 317 phy_gmii_sel: phy-gmii-sel { 318 compatible = "ti,am3352-phy-gmii-sel"; 319 reg = <0x650 0x4>; 320 #phy-cells = <2>; 321 }; 322 323 scm_clocks: clocks { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 }; 328 329 usb_ctrl_mod: control@620 { 330 compatible = "ti,am335x-usb-ctrl-module"; 331 reg = <0x620 0x10>, 332 <0x648 0x4>; 333 reg-names = "phy_ctrl", "wakeup"; 334 }; 335 336 wkup_m3_ipc: wkup_m3_ipc@1324 { 337 compatible = "ti,am3352-wkup-m3-ipc"; 338 reg = <0x1324 0x24>; 339 interrupts = <78>; 340 ti,rproc = <&wkup_m3>; 341 mboxes = <&mailbox &mbox_wkupm3>; 342 }; 343 344 edma_xbar: dma-router@f90 { 345 compatible = "ti,am335x-edma-crossbar"; 346 reg = <0xf90 0x40>; 347 #dma-cells = <3>; 348 dma-requests = <32>; 349 dma-masters = <&edma>; 350 }; 351 352 scm_clockdomains: clockdomains { 353 }; 354 }; 355 }; 356 357 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 358 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 359 reg = <0x31000 0x4>, 360 <0x31010 0x4>, 361 <0x31014 0x4>; 362 reg-names = "rev", "sysc", "syss"; 363 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 364 SYSC_OMAP2_SOFTRESET | 365 SYSC_OMAP2_AUTOIDLE)>; 366 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 367 <SYSC_IDLE_NO>, 368 <SYSC_IDLE_SMART>; 369 ti,syss-mask = <1>; 370 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 371 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 372 clock-names = "fck"; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0x0 0x31000 0x1000>; 376 377 timer1: timer@0 { 378 compatible = "ti,am335x-timer-1ms"; 379 reg = <0x0 0x400>; 380 interrupts = <67>; 381 ti,timer-alwon; 382 clocks = <&timer1_fck>; 383 clock-names = "fck"; 384 }; 385 }; 386 387 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 388 compatible = "ti,sysc"; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0x33000 0x1000>; 393 }; 394 395 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 396 compatible = "ti,sysc-omap2", "ti,sysc"; 397 reg = <0x35000 0x4>, 398 <0x35010 0x4>, 399 <0x35014 0x4>; 400 reg-names = "rev", "sysc", "syss"; 401 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 402 SYSC_OMAP2_SOFTRESET)>; 403 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 404 <SYSC_IDLE_NO>, 405 <SYSC_IDLE_SMART>, 406 <SYSC_IDLE_SMART_WKUP>; 407 ti,syss-mask = <1>; 408 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 409 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 410 clock-names = "fck"; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0x0 0x35000 0x1000>; 414 415 wdt2: wdt@0 { 416 compatible = "ti,omap3-wdt"; 417 reg = <0x0 0x1000>; 418 interrupts = <91>; 419 }; 420 }; 421 422 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 423 compatible = "ti,sysc"; 424 status = "disabled"; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges = <0x0 0x37000 0x1000>; 428 }; 429 430 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 431 compatible = "ti,sysc"; 432 status = "disabled"; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges = <0x0 0x39000 0x1000>; 436 }; 437 438 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 439 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 440 reg = <0x3e074 0x4>, 441 <0x3e078 0x4>; 442 reg-names = "rev", "sysc"; 443 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 444 <SYSC_IDLE_NO>, 445 <SYSC_IDLE_SMART>, 446 <SYSC_IDLE_SMART_WKUP>; 447 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 448 power-domains = <&prm_rtc>; 449 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 450 clock-names = "fck"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0x0 0x3e000 0x1000>; 454 455 rtc: rtc@0 { 456 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 457 reg = <0x0 0x1000>; 458 interrupts = <75>, 459 <76>; 460 }; 461 }; 462 463 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 464 compatible = "ti,sysc"; 465 status = "disabled"; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 ranges = <0x0 0x40000 0x40000>; 469 }; 470 }; 471}; 472 473&l4_fw { /* 0x47c00000 */ 474 compatible = "ti,am33xx-l4-fw", "simple-bus"; 475 reg = <0x47c00000 0x800>, 476 <0x47c00800 0x800>, 477 <0x47c01000 0x400>; 478 reg-names = "ap", "la", "ia0"; 479 #address-cells = <1>; 480 #size-cells = <1>; 481 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 482 483 segment@0 { /* 0x47c00000 */ 484 compatible = "simple-bus"; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 488 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 489 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 490 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 491 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 492 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 493 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 494 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 495 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 496 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 497 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 498 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 499 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 500 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 501 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 502 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 503 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 504 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 505 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 506 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 507 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 508 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 509 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 510 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 511 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 512 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 513 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 514 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 515 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 516 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 517 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 518 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 519 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 520 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 521 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 522 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 523 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 524 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 525 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 526 527 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 528 compatible = "ti,sysc"; 529 status = "disabled"; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges = <0x0 0xc000 0x1000>; 533 }; 534 535 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 536 compatible = "ti,sysc"; 537 status = "disabled"; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 ranges = <0x0 0xe000 0x1000>; 541 }; 542 543 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 544 compatible = "ti,sysc"; 545 status = "disabled"; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 ranges = <0x0 0x10000 0x1000>; 549 }; 550 551 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 552 compatible = "ti,sysc"; 553 status = "disabled"; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges = <0x0 0x14000 0x1000>; 557 }; 558 559 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 560 compatible = "ti,sysc"; 561 status = "disabled"; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges = <0x0 0x1a000 0x1000>; 565 }; 566 567 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 568 compatible = "ti,sysc"; 569 status = "disabled"; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges = <0x0 0x24000 0x1000>; 573 }; 574 575 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 576 compatible = "ti,sysc"; 577 status = "disabled"; 578 #address-cells = <1>; 579 #size-cells = <1>; 580 ranges = <0x0 0x26000 0x1000>; 581 }; 582 583 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 584 compatible = "ti,sysc"; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0x0 0x28000 0x1000>; 589 }; 590 591 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 592 compatible = "ti,sysc"; 593 status = "disabled"; 594 #address-cells = <1>; 595 #size-cells = <1>; 596 ranges = <0x0 0x30000 0x1000>; 597 }; 598 599 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 600 compatible = "ti,sysc"; 601 status = "disabled"; 602 #address-cells = <1>; 603 #size-cells = <1>; 604 ranges = <0x0 0x32000 0x1000>; 605 }; 606 607 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 608 compatible = "ti,sysc"; 609 status = "disabled"; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0x0 0x38000 0x1000>; 613 }; 614 615 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 616 compatible = "ti,sysc"; 617 status = "disabled"; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges = <0x0 0x3a000 0x1000>; 621 }; 622 623 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 624 compatible = "ti,sysc"; 625 status = "disabled"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges = <0x0 0x3c000 0x1000>; 629 }; 630 631 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 632 compatible = "ti,sysc"; 633 status = "disabled"; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 ranges = <0x0 0x3e000 0x1000>; 637 }; 638 639 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 640 compatible = "ti,sysc"; 641 status = "disabled"; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 ranges = <0x0 0x40000 0x1000>; 645 }; 646 647 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 648 compatible = "ti,sysc"; 649 status = "disabled"; 650 #address-cells = <1>; 651 #size-cells = <1>; 652 ranges = <0x0 0x42000 0x1000>; 653 }; 654 655 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 656 compatible = "ti,sysc"; 657 status = "disabled"; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges = <0x0 0x44000 0x1000>; 661 }; 662 663 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 664 compatible = "ti,sysc"; 665 status = "disabled"; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 ranges = <0x0 0x46000 0x1000>; 669 }; 670 }; 671}; 672 673&l4_fast { /* 0x4a000000 */ 674 compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; 675 power-domains = <&prm_per>; 676 clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; 677 clock-names = "fck"; 678 reg = <0x4a000000 0x800>, 679 <0x4a000800 0x800>, 680 <0x4a001000 0x400>; 681 reg-names = "ap", "la", "ia0"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 685 686 segment@0 { /* 0x4a000000 */ 687 compatible = "simple-pm-bus"; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 691 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 692 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 693 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 694 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 695 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 696 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 697 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 698 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 699 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 700 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 701 702 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 703 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 704 reg = <0x101200 0x4>, 705 <0x101208 0x4>, 706 <0x101204 0x4>; 707 reg-names = "rev", "sysc", "syss"; 708 ti,sysc-mask = <0>; 709 ti,sysc-midle = <SYSC_IDLE_FORCE>, 710 <SYSC_IDLE_NO>; 711 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 712 <SYSC_IDLE_NO>; 713 ti,syss-mask = <1>; 714 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 715 clock-names = "fck"; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges = <0x0 0x100000 0x8000>; 719 720 mac: ethernet@0 { 721 compatible = "ti,am335x-cpsw","ti,cpsw"; 722 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 723 clock-names = "fck", "cpts"; 724 cpdma_channels = <8>; 725 ale_entries = <1024>; 726 bd_ram_size = <0x2000>; 727 mac_control = <0x20>; 728 slaves = <2>; 729 active_slave = <0>; 730 cpts_clock_mult = <0x80000000>; 731 cpts_clock_shift = <29>; 732 reg = <0x0 0x800 733 0x1200 0x100>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 /* 737 * c0_rx_thresh_pend 738 * c0_rx_pend 739 * c0_tx_pend 740 * c0_misc_pend 741 */ 742 interrupts = <40>, <41>, <42>, <43>; 743 ranges = <0 0 0x8000>; 744 syscon = <&scm_conf>; 745 status = "disabled"; 746 747 davinci_mdio: mdio@1000 { 748 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 749 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 750 clock-names = "fck"; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 bus_freq = <1000000>; 754 reg = <0x1000 0x100>; 755 status = "disabled"; 756 }; 757 758 cpsw_emac0: slave@200 { 759 /* Filled in by U-Boot */ 760 mac-address = [ 00 00 00 00 00 00 ]; 761 phys = <&phy_gmii_sel 1 1>; 762 }; 763 764 cpsw_emac1: slave@300 { 765 /* Filled in by U-Boot */ 766 mac-address = [ 00 00 00 00 00 00 ]; 767 phys = <&phy_gmii_sel 2 1>; 768 }; 769 }; 770 771 mac_sw: switch@0 { 772 compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; 773 reg = <0x0 0x4000>; 774 ranges = <0 0 0x4000>; 775 clocks = <&cpsw_125mhz_gclk>; 776 clock-names = "fck"; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 syscon = <&scm_conf>; 780 status = "disabled"; 781 782 interrupts = <40>, <41>, <42>, <43>; 783 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 784 785 ethernet-ports { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 789 cpsw_port1: port@1 { 790 reg = <1>; 791 label = "port1"; 792 mac-address = [ 00 00 00 00 00 00 ]; 793 phys = <&phy_gmii_sel 1 1>; 794 }; 795 796 cpsw_port2: port@2 { 797 reg = <2>; 798 label = "port2"; 799 mac-address = [ 00 00 00 00 00 00 ]; 800 phys = <&phy_gmii_sel 2 1>; 801 }; 802 }; 803 804 davinci_mdio_sw: mdio@1000 { 805 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 806 clocks = <&cpsw_125mhz_gclk>; 807 clock-names = "fck"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 bus_freq = <1000000>; 811 reg = <0x1000 0x100>; 812 }; 813 814 cpts { 815 clocks = <&cpsw_cpts_rft_clk>; 816 clock-names = "cpts"; 817 }; 818 }; 819 }; 820 821 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 822 compatible = "ti,sysc"; 823 status = "disabled"; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 ranges = <0x0 0x180000 0x20000>; 827 }; 828 829 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 830 compatible = "ti,sysc"; 831 status = "disabled"; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges = <0x0 0x200000 0x80000>; 835 }; 836 837 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 838 compatible = "ti,sysc-pruss", "ti,sysc"; 839 reg = <0x326000 0x4>, 840 <0x326004 0x4>; 841 reg-names = "rev", "sysc"; 842 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 843 SYSC_PRUSS_SUB_MWAIT)>; 844 ti,sysc-midle = <SYSC_IDLE_FORCE>, 845 <SYSC_IDLE_NO>, 846 <SYSC_IDLE_SMART>; 847 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 848 <SYSC_IDLE_NO>, 849 <SYSC_IDLE_SMART>; 850 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 851 clock-names = "fck"; 852 resets = <&prm_per 1>; 853 reset-names = "rstctrl"; 854 #address-cells = <1>; 855 #size-cells = <1>; 856 ranges = <0x0 0x300000 0x80000>; 857 status = "disabled"; 858 859 pruss: pruss@0 { 860 compatible = "ti,am3356-pruss"; 861 reg = <0x0 0x80000>; 862 #address-cells = <1>; 863 #size-cells = <1>; 864 ranges; 865 866 pruss_mem: memories@0 { 867 reg = <0x0 0x2000>, 868 <0x2000 0x2000>, 869 <0x10000 0x3000>; 870 reg-names = "dram0", "dram1", 871 "shrdram2"; 872 }; 873 874 pruss_cfg: cfg@26000 { 875 compatible = "ti,pruss-cfg", "syscon"; 876 reg = <0x26000 0x2000>; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 ranges = <0x0 0x26000 0x2000>; 880 881 clocks { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 pruss_iepclk_mux: iepclk-mux@30 { 886 reg = <0x30>; 887 #clock-cells = <0>; 888 clocks = <&l3_gclk>, /* icss_iep_gclk */ 889 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 890 }; 891 }; 892 }; 893 894 pruss_mii_rt: mii-rt@32000 { 895 compatible = "ti,pruss-mii", "syscon"; 896 reg = <0x32000 0x58>; 897 }; 898 899 pruss_intc: interrupt-controller@20000 { 900 compatible = "ti,pruss-intc"; 901 reg = <0x20000 0x2000>; 902 interrupts = <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>; 903 interrupt-names = "host_intr0", "host_intr1", 904 "host_intr2", "host_intr3", 905 "host_intr4", "host_intr5", 906 "host_intr6", "host_intr7"; 907 interrupt-controller; 908 #interrupt-cells = <3>; 909 }; 910 911 pru0: pru@34000 { 912 compatible = "ti,am3356-pru"; 913 reg = <0x34000 0x2000>, 914 <0x22000 0x400>, 915 <0x22400 0x100>; 916 reg-names = "iram", "control", "debug"; 917 firmware-name = "am335x-pru0-fw"; 918 }; 919 920 pru1: pru@38000 { 921 compatible = "ti,am3356-pru"; 922 reg = <0x38000 0x2000>, 923 <0x24000 0x400>, 924 <0x24400 0x100>; 925 reg-names = "iram", "control", "debug"; 926 firmware-name = "am335x-pru1-fw"; 927 }; 928 929 pruss_mdio: mdio@32400 { 930 compatible = "ti,davinci_mdio"; 931 reg = <0x32400 0x90>; 932 clocks = <&dpll_core_m4_ck>; 933 clock-names = "fck"; 934 bus_freq = <1000000>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 status = "disabled"; 938 }; 939 }; 940 }; 941 }; 942}; 943 944&l4_mpuss { /* 0x4b140000 */ 945 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 946 reg = <0x4b144400 0x100>, 947 <0x4b144800 0x400>; 948 reg-names = "la", "ap"; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 952 953 segment@0 { /* 0x4b140000 */ 954 compatible = "simple-bus"; 955 #address-cells = <1>; 956 #size-cells = <1>; 957 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 958 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 959 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 960 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 961 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 962 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 963 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 964 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 965 966 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 967 compatible = "ti,sysc"; 968 status = "disabled"; 969 #address-cells = <1>; 970 #size-cells = <1>; 971 ranges = <0x00000000 0x00000000 0x00001000>, 972 <0x00001000 0x00001000 0x00001000>, 973 <0x00002000 0x00002000 0x00001000>; 974 }; 975 976 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 977 compatible = "ti,sysc"; 978 status = "disabled"; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 ranges = <0x0 0x3000 0x1000>; 982 }; 983 }; 984}; 985 986&l4_per { /* 0x48000000 */ 987 compatible = "ti,am33xx-l4-per", "simple-pm-bus"; 988 power-domains = <&prm_per>; 989 clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 990 clock-names = "fck"; 991 reg = <0x48000000 0x800>, 992 <0x48000800 0x800>, 993 <0x48001000 0x400>, 994 <0x48001400 0x400>, 995 <0x48001800 0x400>, 996 <0x48001c00 0x400>; 997 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 1001 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 1002 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 1003 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 1004 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1005 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1006 1007 segment@0 { /* 0x48000000 */ 1008 compatible = "simple-pm-bus"; 1009 #address-cells = <1>; 1010 #size-cells = <1>; 1011 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1012 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 1013 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 1014 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 1015 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 1016 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 1017 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 1018 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 1019 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 1020 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 1021 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 1022 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 1023 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 1024 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 1025 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 1026 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 1027 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 1028 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 1029 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 1030 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 1031 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 1032 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 1033 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 1034 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 1035 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 1036 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 1037 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 1038 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 1039 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 1040 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 1041 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 1042 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 1043 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 1044 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 1045 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 1046 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 1047 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 1048 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 1049 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 1050 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 1051 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 1052 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 1053 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 1054 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 1055 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 1056 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 1057 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 1058 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 1059 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 1060 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 1061 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 1062 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 1063 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1064 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1065 1066 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 1067 compatible = "ti,sysc"; 1068 status = "disabled"; 1069 #address-cells = <1>; 1070 #size-cells = <1>; 1071 ranges = <0x0 0x8000 0x1000>; 1072 }; 1073 1074 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 1075 compatible = "ti,sysc"; 1076 status = "disabled"; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 ranges = <0x0 0x14000 0x1000>; 1080 }; 1081 1082 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 1083 compatible = "ti,sysc"; 1084 status = "disabled"; 1085 #address-cells = <1>; 1086 #size-cells = <1>; 1087 ranges = <0x0 0x16000 0x1000>; 1088 }; 1089 1090 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 1091 compatible = "ti,sysc-omap2", "ti,sysc"; 1092 reg = <0x22050 0x4>, 1093 <0x22054 0x4>, 1094 <0x22058 0x4>; 1095 reg-names = "rev", "sysc", "syss"; 1096 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1097 SYSC_OMAP2_SOFTRESET | 1098 SYSC_OMAP2_AUTOIDLE)>; 1099 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1100 <SYSC_IDLE_NO>, 1101 <SYSC_IDLE_SMART>, 1102 <SYSC_IDLE_SMART_WKUP>; 1103 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1104 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 1105 clock-names = "fck"; 1106 #address-cells = <1>; 1107 #size-cells = <1>; 1108 ranges = <0x0 0x22000 0x1000>; 1109 1110 uart1: serial@0 { 1111 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1112 clock-frequency = <48000000>; 1113 reg = <0x0 0x1000>; 1114 interrupts = <73>; 1115 status = "disabled"; 1116 dmas = <&edma 28 0>, <&edma 29 0>; 1117 dma-names = "tx", "rx"; 1118 }; 1119 }; 1120 1121 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 1122 compatible = "ti,sysc-omap2", "ti,sysc"; 1123 reg = <0x24050 0x4>, 1124 <0x24054 0x4>, 1125 <0x24058 0x4>; 1126 reg-names = "rev", "sysc", "syss"; 1127 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1128 SYSC_OMAP2_SOFTRESET | 1129 SYSC_OMAP2_AUTOIDLE)>; 1130 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1131 <SYSC_IDLE_NO>, 1132 <SYSC_IDLE_SMART>, 1133 <SYSC_IDLE_SMART_WKUP>; 1134 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1135 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 1136 clock-names = "fck"; 1137 #address-cells = <1>; 1138 #size-cells = <1>; 1139 ranges = <0x0 0x24000 0x1000>; 1140 1141 uart2: serial@0 { 1142 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1143 clock-frequency = <48000000>; 1144 reg = <0x0 0x1000>; 1145 interrupts = <74>; 1146 status = "disabled"; 1147 dmas = <&edma 30 0>, <&edma 31 0>; 1148 dma-names = "tx", "rx"; 1149 }; 1150 }; 1151 1152 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 1153 compatible = "ti,sysc-omap2", "ti,sysc"; 1154 reg = <0x2a000 0x8>, 1155 <0x2a010 0x8>, 1156 <0x2a090 0x8>; 1157 reg-names = "rev", "sysc", "syss"; 1158 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1159 SYSC_OMAP2_ENAWAKEUP | 1160 SYSC_OMAP2_SOFTRESET | 1161 SYSC_OMAP2_AUTOIDLE)>; 1162 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1163 <SYSC_IDLE_NO>, 1164 <SYSC_IDLE_SMART>, 1165 <SYSC_IDLE_SMART_WKUP>; 1166 ti,syss-mask = <1>; 1167 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1168 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 1169 clock-names = "fck"; 1170 #address-cells = <1>; 1171 #size-cells = <1>; 1172 ranges = <0x0 0x2a000 0x1000>; 1173 1174 i2c1: i2c@0 { 1175 compatible = "ti,omap4-i2c"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 reg = <0x0 0x1000>; 1179 interrupts = <71>; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1185 compatible = "ti,sysc-omap2", "ti,sysc"; 1186 reg = <0x30000 0x4>, 1187 <0x30110 0x4>, 1188 <0x30114 0x4>; 1189 reg-names = "rev", "sysc", "syss"; 1190 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1191 SYSC_OMAP2_SOFTRESET | 1192 SYSC_OMAP2_AUTOIDLE)>; 1193 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1194 <SYSC_IDLE_NO>, 1195 <SYSC_IDLE_SMART>; 1196 ti,syss-mask = <1>; 1197 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1198 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1199 clock-names = "fck"; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 ranges = <0x0 0x30000 0x1000>; 1203 1204 spi0: spi@0 { 1205 compatible = "ti,omap4-mcspi"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 reg = <0x0 0x400>; 1209 interrupts = <65>; 1210 ti,spi-num-cs = <2>; 1211 dmas = <&edma 16 0 1212 &edma 17 0 1213 &edma 18 0 1214 &edma 19 0>; 1215 dma-names = "tx0", "rx0", "tx1", "rx1"; 1216 status = "disabled"; 1217 }; 1218 }; 1219 1220 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1221 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1222 reg = <0x38000 0x4>, 1223 <0x38004 0x4>; 1224 reg-names = "rev", "sysc"; 1225 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1226 <SYSC_IDLE_NO>, 1227 <SYSC_IDLE_SMART>; 1228 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1229 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1230 clock-names = "fck"; 1231 #address-cells = <1>; 1232 #size-cells = <1>; 1233 ranges = <0x0 0x38000 0x2000>, 1234 <0x46000000 0x46000000 0x400000>; 1235 1236 mcasp0: mcasp@0 { 1237 compatible = "ti,am33xx-mcasp-audio"; 1238 reg = <0x0 0x2000>, 1239 <0x46000000 0x400000>; 1240 reg-names = "mpu", "dat"; 1241 interrupts = <80>, <81>; 1242 interrupt-names = "tx", "rx"; 1243 status = "disabled"; 1244 dmas = <&edma 8 2>, 1245 <&edma 9 2>; 1246 dma-names = "tx", "rx"; 1247 }; 1248 }; 1249 1250 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1251 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1252 reg = <0x3c000 0x4>, 1253 <0x3c004 0x4>; 1254 reg-names = "rev", "sysc"; 1255 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1256 <SYSC_IDLE_NO>, 1257 <SYSC_IDLE_SMART>; 1258 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1259 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1260 clock-names = "fck"; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 ranges = <0x0 0x3c000 0x2000>, 1264 <0x46400000 0x46400000 0x400000>; 1265 1266 mcasp1: mcasp@0 { 1267 compatible = "ti,am33xx-mcasp-audio"; 1268 reg = <0x0 0x2000>, 1269 <0x46400000 0x400000>; 1270 reg-names = "mpu", "dat"; 1271 interrupts = <82>, <83>; 1272 interrupt-names = "tx", "rx"; 1273 status = "disabled"; 1274 dmas = <&edma 10 2>, 1275 <&edma 11 2>; 1276 dma-names = "tx", "rx"; 1277 }; 1278 }; 1279 1280 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1281 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1282 reg = <0x40000 0x4>, 1283 <0x40010 0x4>, 1284 <0x40014 0x4>; 1285 reg-names = "rev", "sysc", "syss"; 1286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1287 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1288 <SYSC_IDLE_NO>, 1289 <SYSC_IDLE_SMART>, 1290 <SYSC_IDLE_SMART_WKUP>; 1291 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1292 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1293 clock-names = "fck"; 1294 #address-cells = <1>; 1295 #size-cells = <1>; 1296 ranges = <0x0 0x40000 0x1000>; 1297 1298 timer2: timer@0 { 1299 compatible = "ti,am335x-timer"; 1300 reg = <0x0 0x400>; 1301 interrupts = <68>; 1302 clocks = <&timer2_fck>; 1303 clock-names = "fck"; 1304 }; 1305 }; 1306 1307 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1308 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1309 reg = <0x42000 0x4>, 1310 <0x42010 0x4>, 1311 <0x42014 0x4>; 1312 reg-names = "rev", "sysc", "syss"; 1313 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1314 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1315 <SYSC_IDLE_NO>, 1316 <SYSC_IDLE_SMART>, 1317 <SYSC_IDLE_SMART_WKUP>; 1318 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1319 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1320 clock-names = "fck"; 1321 #address-cells = <1>; 1322 #size-cells = <1>; 1323 ranges = <0x0 0x42000 0x1000>; 1324 1325 timer3: timer@0 { 1326 compatible = "ti,am335x-timer"; 1327 reg = <0x0 0x400>; 1328 interrupts = <69>; 1329 }; 1330 }; 1331 1332 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1333 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1334 reg = <0x44000 0x4>, 1335 <0x44010 0x4>, 1336 <0x44014 0x4>; 1337 reg-names = "rev", "sysc", "syss"; 1338 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1339 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1340 <SYSC_IDLE_NO>, 1341 <SYSC_IDLE_SMART>, 1342 <SYSC_IDLE_SMART_WKUP>; 1343 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1344 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1345 clock-names = "fck"; 1346 #address-cells = <1>; 1347 #size-cells = <1>; 1348 ranges = <0x0 0x44000 0x1000>; 1349 1350 timer4: timer@0 { 1351 compatible = "ti,am335x-timer"; 1352 reg = <0x0 0x400>; 1353 interrupts = <92>; 1354 ti,timer-pwm; 1355 }; 1356 }; 1357 1358 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1359 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1360 reg = <0x46000 0x4>, 1361 <0x46010 0x4>, 1362 <0x46014 0x4>; 1363 reg-names = "rev", "sysc", "syss"; 1364 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1365 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1366 <SYSC_IDLE_NO>, 1367 <SYSC_IDLE_SMART>, 1368 <SYSC_IDLE_SMART_WKUP>; 1369 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1370 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1371 clock-names = "fck"; 1372 #address-cells = <1>; 1373 #size-cells = <1>; 1374 ranges = <0x0 0x46000 0x1000>; 1375 1376 timer5: timer@0 { 1377 compatible = "ti,am335x-timer"; 1378 reg = <0x0 0x400>; 1379 interrupts = <93>; 1380 ti,timer-pwm; 1381 }; 1382 }; 1383 1384 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1385 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1386 reg = <0x48000 0x4>, 1387 <0x48010 0x4>, 1388 <0x48014 0x4>; 1389 reg-names = "rev", "sysc", "syss"; 1390 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1391 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1392 <SYSC_IDLE_NO>, 1393 <SYSC_IDLE_SMART>, 1394 <SYSC_IDLE_SMART_WKUP>; 1395 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1396 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1397 clock-names = "fck"; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 ranges = <0x0 0x48000 0x1000>; 1401 1402 timer6: timer@0 { 1403 compatible = "ti,am335x-timer"; 1404 reg = <0x0 0x400>; 1405 interrupts = <94>; 1406 ti,timer-pwm; 1407 }; 1408 }; 1409 1410 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1411 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1412 reg = <0x4a000 0x4>, 1413 <0x4a010 0x4>, 1414 <0x4a014 0x4>; 1415 reg-names = "rev", "sysc", "syss"; 1416 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1417 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1418 <SYSC_IDLE_NO>, 1419 <SYSC_IDLE_SMART>, 1420 <SYSC_IDLE_SMART_WKUP>; 1421 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1422 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1423 clock-names = "fck"; 1424 #address-cells = <1>; 1425 #size-cells = <1>; 1426 ranges = <0x0 0x4a000 0x1000>; 1427 1428 timer7: timer@0 { 1429 compatible = "ti,am335x-timer"; 1430 reg = <0x0 0x400>; 1431 interrupts = <95>; 1432 ti,timer-pwm; 1433 }; 1434 }; 1435 1436 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1437 compatible = "ti,sysc-omap2", "ti,sysc"; 1438 reg = <0x4c000 0x4>, 1439 <0x4c010 0x4>, 1440 <0x4c114 0x4>; 1441 reg-names = "rev", "sysc", "syss"; 1442 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1443 SYSC_OMAP2_SOFTRESET | 1444 SYSC_OMAP2_AUTOIDLE)>; 1445 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1446 <SYSC_IDLE_NO>, 1447 <SYSC_IDLE_SMART>, 1448 <SYSC_IDLE_SMART_WKUP>; 1449 ti,syss-mask = <1>; 1450 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1451 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1452 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1453 clock-names = "fck", "dbclk"; 1454 #address-cells = <1>; 1455 #size-cells = <1>; 1456 ranges = <0x0 0x4c000 0x1000>; 1457 1458 gpio1: gpio@0 { 1459 compatible = "ti,omap4-gpio"; 1460 gpio-ranges = <&am33xx_pinmux 0 0 8>, 1461 <&am33xx_pinmux 8 90 4>, 1462 <&am33xx_pinmux 12 12 16>, 1463 <&am33xx_pinmux 28 30 4>; 1464 gpio-controller; 1465 #gpio-cells = <2>; 1466 interrupt-controller; 1467 #interrupt-cells = <2>; 1468 reg = <0x0 0x1000>; 1469 interrupts = <98>; 1470 }; 1471 }; 1472 1473 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1474 compatible = "ti,sysc"; 1475 status = "disabled"; 1476 #address-cells = <1>; 1477 #size-cells = <1>; 1478 ranges = <0x0 0x50000 0x2000>; 1479 }; 1480 1481 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1482 compatible = "ti,sysc-omap2", "ti,sysc"; 1483 reg = <0x602fc 0x4>, 1484 <0x60110 0x4>, 1485 <0x60114 0x4>; 1486 reg-names = "rev", "sysc", "syss"; 1487 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1488 SYSC_OMAP2_ENAWAKEUP | 1489 SYSC_OMAP2_SOFTRESET | 1490 SYSC_OMAP2_AUTOIDLE)>; 1491 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1492 <SYSC_IDLE_NO>, 1493 <SYSC_IDLE_SMART>; 1494 ti,syss-mask = <1>; 1495 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1496 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1497 clock-names = "fck"; 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 ranges = <0x0 0x60000 0x1000>; 1501 1502 mmc1: mmc@0 { 1503 compatible = "ti,am335-sdhci"; 1504 ti,needs-special-reset; 1505 dmas = <&edma 24 0>, <&edma 25 0>; 1506 dma-names = "tx", "rx"; 1507 interrupts = <64>; 1508 reg = <0x0 0x1000>; 1509 status = "disabled"; 1510 }; 1511 }; 1512 1513 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1514 compatible = "ti,sysc-omap2", "ti,sysc"; 1515 reg = <0x80000 0x4>, 1516 <0x80010 0x4>, 1517 <0x80014 0x4>; 1518 reg-names = "rev", "sysc", "syss"; 1519 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1520 SYSC_OMAP2_SOFTRESET | 1521 SYSC_OMAP2_AUTOIDLE)>; 1522 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1523 <SYSC_IDLE_NO>, 1524 <SYSC_IDLE_SMART>; 1525 ti,syss-mask = <1>; 1526 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1527 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1528 clock-names = "fck"; 1529 #address-cells = <1>; 1530 #size-cells = <1>; 1531 ranges = <0x0 0x80000 0x10000>; 1532 1533 elm: elm@0 { 1534 compatible = "ti,am3352-elm"; 1535 reg = <0x0 0x2000>; 1536 interrupts = <4>; 1537 status = "disabled"; 1538 }; 1539 }; 1540 1541 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1542 compatible = "ti,sysc"; 1543 status = "disabled"; 1544 #address-cells = <1>; 1545 #size-cells = <1>; 1546 ranges = <0x0 0xa0000 0x10000>; 1547 }; 1548 1549 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1550 compatible = "ti,sysc-omap4", "ti,sysc"; 1551 reg = <0xc8000 0x4>, 1552 <0xc8010 0x4>; 1553 reg-names = "rev", "sysc"; 1554 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1555 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1556 <SYSC_IDLE_NO>, 1557 <SYSC_IDLE_SMART>; 1558 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1559 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1560 clock-names = "fck"; 1561 #address-cells = <1>; 1562 #size-cells = <1>; 1563 ranges = <0x0 0xc8000 0x1000>; 1564 1565 mailbox: mailbox@0 { 1566 compatible = "ti,omap4-mailbox"; 1567 reg = <0x0 0x200>; 1568 interrupts = <77>; 1569 #mbox-cells = <1>; 1570 ti,mbox-num-users = <4>; 1571 ti,mbox-num-fifos = <8>; 1572 mbox_wkupm3: mbox-wkup-m3 { 1573 ti,mbox-send-noirq; 1574 ti,mbox-tx = <0 0 0>; 1575 ti,mbox-rx = <0 0 3>; 1576 }; 1577 }; 1578 }; 1579 1580 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1581 compatible = "ti,sysc-omap2", "ti,sysc"; 1582 reg = <0xca000 0x4>, 1583 <0xca010 0x4>, 1584 <0xca014 0x4>; 1585 reg-names = "rev", "sysc", "syss"; 1586 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1587 SYSC_OMAP2_ENAWAKEUP | 1588 SYSC_OMAP2_SOFTRESET | 1589 SYSC_OMAP2_AUTOIDLE)>; 1590 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1591 <SYSC_IDLE_NO>, 1592 <SYSC_IDLE_SMART>; 1593 ti,syss-mask = <1>; 1594 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1595 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1596 clock-names = "fck"; 1597 #address-cells = <1>; 1598 #size-cells = <1>; 1599 ranges = <0x0 0xca000 0x1000>; 1600 1601 hwspinlock: spinlock@0 { 1602 compatible = "ti,omap4-hwspinlock"; 1603 reg = <0x0 0x1000>; 1604 #hwlock-cells = <1>; 1605 }; 1606 }; 1607 1608 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1609 compatible = "ti,sysc"; 1610 status = "disabled"; 1611 #address-cells = <1>; 1612 #size-cells = <1>; 1613 ranges = <0x0 0xcc000 0x1000>; 1614 }; 1615 }; 1616 1617 segment@100000 { /* 0x48100000 */ 1618 compatible = "simple-pm-bus"; 1619 #address-cells = <1>; 1620 #size-cells = <1>; 1621 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1622 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1623 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1624 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1625 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1626 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1627 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1628 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1629 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1630 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1631 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1632 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1633 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1634 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1635 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1636 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1637 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1638 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1639 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1640 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1641 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1642 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1643 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1644 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1645 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1646 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1647 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1648 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1649 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1650 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1651 1652 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1653 compatible = "ti,sysc"; 1654 status = "disabled"; 1655 #address-cells = <1>; 1656 #size-cells = <1>; 1657 ranges = <0x0 0x8c000 0x1000>; 1658 }; 1659 1660 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1661 compatible = "ti,sysc"; 1662 status = "disabled"; 1663 #address-cells = <1>; 1664 #size-cells = <1>; 1665 ranges = <0x0 0x8e000 0x1000>; 1666 }; 1667 1668 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1669 compatible = "ti,sysc-omap2", "ti,sysc"; 1670 reg = <0x9c000 0x8>, 1671 <0x9c010 0x8>, 1672 <0x9c090 0x8>; 1673 reg-names = "rev", "sysc", "syss"; 1674 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1675 SYSC_OMAP2_ENAWAKEUP | 1676 SYSC_OMAP2_SOFTRESET | 1677 SYSC_OMAP2_AUTOIDLE)>; 1678 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1679 <SYSC_IDLE_NO>, 1680 <SYSC_IDLE_SMART>, 1681 <SYSC_IDLE_SMART_WKUP>; 1682 ti,syss-mask = <1>; 1683 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1684 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1685 clock-names = "fck"; 1686 #address-cells = <1>; 1687 #size-cells = <1>; 1688 ranges = <0x0 0x9c000 0x1000>; 1689 1690 i2c2: i2c@0 { 1691 compatible = "ti,omap4-i2c"; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 reg = <0x0 0x1000>; 1695 interrupts = <30>; 1696 status = "disabled"; 1697 }; 1698 }; 1699 1700 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1701 compatible = "ti,sysc-omap2", "ti,sysc"; 1702 reg = <0xa0000 0x4>, 1703 <0xa0110 0x4>, 1704 <0xa0114 0x4>; 1705 reg-names = "rev", "sysc", "syss"; 1706 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1707 SYSC_OMAP2_SOFTRESET | 1708 SYSC_OMAP2_AUTOIDLE)>; 1709 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1710 <SYSC_IDLE_NO>, 1711 <SYSC_IDLE_SMART>; 1712 ti,syss-mask = <1>; 1713 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1714 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1715 clock-names = "fck"; 1716 #address-cells = <1>; 1717 #size-cells = <1>; 1718 ranges = <0x0 0xa0000 0x1000>; 1719 1720 spi1: spi@0 { 1721 compatible = "ti,omap4-mcspi"; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 reg = <0x0 0x400>; 1725 interrupts = <125>; 1726 ti,spi-num-cs = <2>; 1727 dmas = <&edma 42 0 1728 &edma 43 0 1729 &edma 44 0 1730 &edma 45 0>; 1731 dma-names = "tx0", "rx0", "tx1", "rx1"; 1732 status = "disabled"; 1733 }; 1734 }; 1735 1736 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1737 compatible = "ti,sysc"; 1738 status = "disabled"; 1739 #address-cells = <1>; 1740 #size-cells = <1>; 1741 ranges = <0x0 0xa2000 0x1000>; 1742 }; 1743 1744 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1745 compatible = "ti,sysc"; 1746 status = "disabled"; 1747 #address-cells = <1>; 1748 #size-cells = <1>; 1749 ranges = <0x0 0xa4000 0x1000>; 1750 }; 1751 1752 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1753 compatible = "ti,sysc-omap2", "ti,sysc"; 1754 reg = <0xa6050 0x4>, 1755 <0xa6054 0x4>, 1756 <0xa6058 0x4>; 1757 reg-names = "rev", "sysc", "syss"; 1758 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1759 SYSC_OMAP2_SOFTRESET | 1760 SYSC_OMAP2_AUTOIDLE)>; 1761 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1762 <SYSC_IDLE_NO>, 1763 <SYSC_IDLE_SMART>, 1764 <SYSC_IDLE_SMART_WKUP>; 1765 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1766 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1767 clock-names = "fck"; 1768 #address-cells = <1>; 1769 #size-cells = <1>; 1770 ranges = <0x0 0xa6000 0x1000>; 1771 1772 uart3: serial@0 { 1773 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1774 clock-frequency = <48000000>; 1775 reg = <0x0 0x1000>; 1776 interrupts = <44>; 1777 status = "disabled"; 1778 }; 1779 }; 1780 1781 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1782 compatible = "ti,sysc-omap2", "ti,sysc"; 1783 reg = <0xa8050 0x4>, 1784 <0xa8054 0x4>, 1785 <0xa8058 0x4>; 1786 reg-names = "rev", "sysc", "syss"; 1787 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1788 SYSC_OMAP2_SOFTRESET | 1789 SYSC_OMAP2_AUTOIDLE)>; 1790 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1791 <SYSC_IDLE_NO>, 1792 <SYSC_IDLE_SMART>, 1793 <SYSC_IDLE_SMART_WKUP>; 1794 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1795 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1796 clock-names = "fck"; 1797 #address-cells = <1>; 1798 #size-cells = <1>; 1799 ranges = <0x0 0xa8000 0x1000>; 1800 1801 uart4: serial@0 { 1802 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1803 clock-frequency = <48000000>; 1804 reg = <0x0 0x1000>; 1805 interrupts = <45>; 1806 status = "disabled"; 1807 }; 1808 }; 1809 1810 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1811 compatible = "ti,sysc-omap2", "ti,sysc"; 1812 reg = <0xaa050 0x4>, 1813 <0xaa054 0x4>, 1814 <0xaa058 0x4>; 1815 reg-names = "rev", "sysc", "syss"; 1816 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1817 SYSC_OMAP2_SOFTRESET | 1818 SYSC_OMAP2_AUTOIDLE)>; 1819 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1820 <SYSC_IDLE_NO>, 1821 <SYSC_IDLE_SMART>, 1822 <SYSC_IDLE_SMART_WKUP>; 1823 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1824 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1825 clock-names = "fck"; 1826 #address-cells = <1>; 1827 #size-cells = <1>; 1828 ranges = <0x0 0xaa000 0x1000>; 1829 1830 uart5: serial@0 { 1831 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1832 clock-frequency = <48000000>; 1833 reg = <0x0 0x1000>; 1834 interrupts = <46>; 1835 status = "disabled"; 1836 }; 1837 }; 1838 1839 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1840 compatible = "ti,sysc-omap2", "ti,sysc"; 1841 reg = <0xac000 0x4>, 1842 <0xac010 0x4>, 1843 <0xac114 0x4>; 1844 reg-names = "rev", "sysc", "syss"; 1845 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1846 SYSC_OMAP2_SOFTRESET | 1847 SYSC_OMAP2_AUTOIDLE)>; 1848 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1849 <SYSC_IDLE_NO>, 1850 <SYSC_IDLE_SMART>, 1851 <SYSC_IDLE_SMART_WKUP>; 1852 ti,syss-mask = <1>; 1853 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1854 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1855 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1856 clock-names = "fck", "dbclk"; 1857 #address-cells = <1>; 1858 #size-cells = <1>; 1859 ranges = <0x0 0xac000 0x1000>; 1860 1861 gpio2: gpio@0 { 1862 compatible = "ti,omap4-gpio"; 1863 gpio-ranges = <&am33xx_pinmux 0 34 18>, 1864 <&am33xx_pinmux 18 77 4>, 1865 <&am33xx_pinmux 22 56 10>; 1866 gpio-controller; 1867 #gpio-cells = <2>; 1868 interrupt-controller; 1869 #interrupt-cells = <2>; 1870 reg = <0x0 0x1000>; 1871 interrupts = <32>; 1872 }; 1873 }; 1874 1875 gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1876 compatible = "ti,sysc-omap2", "ti,sysc"; 1877 reg = <0xae000 0x4>, 1878 <0xae010 0x4>, 1879 <0xae114 0x4>; 1880 reg-names = "rev", "sysc", "syss"; 1881 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1882 SYSC_OMAP2_SOFTRESET | 1883 SYSC_OMAP2_AUTOIDLE)>; 1884 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1885 <SYSC_IDLE_NO>, 1886 <SYSC_IDLE_SMART>, 1887 <SYSC_IDLE_SMART_WKUP>; 1888 ti,syss-mask = <1>; 1889 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1890 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1891 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1892 clock-names = "fck", "dbclk"; 1893 #address-cells = <1>; 1894 #size-cells = <1>; 1895 ranges = <0x0 0xae000 0x1000>; 1896 1897 gpio3: gpio@0 { 1898 compatible = "ti,omap4-gpio"; 1899 gpio-ranges = <&am33xx_pinmux 0 66 5>, 1900 <&am33xx_pinmux 5 98 2>, 1901 <&am33xx_pinmux 7 75 2>, 1902 <&am33xx_pinmux 13 141 1>, 1903 <&am33xx_pinmux 14 100 8>; 1904 gpio-controller; 1905 #gpio-cells = <2>; 1906 interrupt-controller; 1907 #interrupt-cells = <2>; 1908 reg = <0x0 0x1000>; 1909 interrupts = <62>; 1910 }; 1911 }; 1912 1913 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1914 compatible = "ti,sysc"; 1915 status = "disabled"; 1916 #address-cells = <1>; 1917 #size-cells = <1>; 1918 ranges = <0x0 0xb0000 0x10000>; 1919 }; 1920 1921 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1922 compatible = "ti,sysc-omap4", "ti,sysc"; 1923 reg = <0xcc020 0x4>; 1924 reg-names = "rev"; 1925 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1926 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1927 <&dcan0_fck>; 1928 clock-names = "fck", "osc"; 1929 #address-cells = <1>; 1930 #size-cells = <1>; 1931 ranges = <0x0 0xcc000 0x2000>; 1932 1933 dcan0: can@0 { 1934 compatible = "ti,am3352-d_can"; 1935 reg = <0x0 0x2000>; 1936 clocks = <&dcan0_fck>; 1937 clock-names = "fck"; 1938 syscon-raminit = <&scm_conf 0x644 0>; 1939 interrupts = <52>; 1940 status = "disabled"; 1941 }; 1942 }; 1943 1944 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1945 compatible = "ti,sysc-omap4", "ti,sysc"; 1946 reg = <0xd0020 0x4>; 1947 reg-names = "rev"; 1948 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1949 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1950 <&dcan1_fck>; 1951 clock-names = "fck", "osc"; 1952 #address-cells = <1>; 1953 #size-cells = <1>; 1954 ranges = <0x0 0xd0000 0x2000>; 1955 1956 dcan1: can@0 { 1957 compatible = "ti,am3352-d_can"; 1958 reg = <0x0 0x2000>; 1959 clocks = <&dcan1_fck>; 1960 clock-names = "fck"; 1961 syscon-raminit = <&scm_conf 0x644 1>; 1962 interrupts = <55>; 1963 status = "disabled"; 1964 }; 1965 }; 1966 1967 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1968 compatible = "ti,sysc-omap2", "ti,sysc"; 1969 reg = <0xd82fc 0x4>, 1970 <0xd8110 0x4>, 1971 <0xd8114 0x4>; 1972 reg-names = "rev", "sysc", "syss"; 1973 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1974 SYSC_OMAP2_ENAWAKEUP | 1975 SYSC_OMAP2_SOFTRESET | 1976 SYSC_OMAP2_AUTOIDLE)>; 1977 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1978 <SYSC_IDLE_NO>, 1979 <SYSC_IDLE_SMART>; 1980 ti,syss-mask = <1>; 1981 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1982 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1983 clock-names = "fck"; 1984 #address-cells = <1>; 1985 #size-cells = <1>; 1986 ranges = <0x0 0xd8000 0x1000>; 1987 1988 mmc2: mmc@0 { 1989 compatible = "ti,am335-sdhci"; 1990 ti,needs-special-reset; 1991 dmas = <&edma 2 0 1992 &edma 3 0>; 1993 dma-names = "tx", "rx"; 1994 interrupts = <28>; 1995 reg = <0x0 0x1000>; 1996 status = "disabled"; 1997 }; 1998 }; 1999 }; 2000 2001 segment@200000 { /* 0x48200000 */ 2002 compatible = "simple-pm-bus"; 2003 #address-cells = <1>; 2004 #size-cells = <1>; 2005 ranges = <0x00000000 0x00200000 0x010000>; 2006 2007 target-module@0 { 2008 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 2009 power-domains = <&prm_mpu>; 2010 clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; 2011 clock-names = "fck"; 2012 ti,no-idle; 2013 #address-cells = <1>; 2014 #size-cells = <1>; 2015 ranges = <0 0 0x10000>; 2016 2017 mpu@0 { 2018 compatible = "ti,omap3-mpu"; 2019 pm-sram = <&pm_sram_code 2020 &pm_sram_data>; 2021 }; 2022 }; 2023 }; 2024 2025 segment@300000 { /* 0x48300000 */ 2026 compatible = "simple-pm-bus"; 2027 #address-cells = <1>; 2028 #size-cells = <1>; 2029 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 2030 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 2031 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 2032 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 2033 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 2034 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 2035 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 2036 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 2037 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 2038 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 2039 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 2040 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 2041 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 2042 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 2043 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 2044 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 2045 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 2046 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 2047 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 2048 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 2049 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 2050 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 2051 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 2052 2053 target-module@0 { /* 0x48300000, ap 66 48.0 */ 2054 compatible = "ti,sysc-omap4", "ti,sysc"; 2055 reg = <0x0 0x4>, 2056 <0x4 0x4>; 2057 reg-names = "rev", "sysc"; 2058 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2059 <SYSC_IDLE_NO>, 2060 <SYSC_IDLE_SMART>, 2061 <SYSC_IDLE_SMART_WKUP>; 2062 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2063 <SYSC_IDLE_NO>, 2064 <SYSC_IDLE_SMART>, 2065 <SYSC_IDLE_SMART_WKUP>; 2066 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2067 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 2068 clock-names = "fck"; 2069 #address-cells = <1>; 2070 #size-cells = <1>; 2071 ranges = <0x0 0x0 0x1000>; 2072 2073 epwmss0: epwmss@0 { 2074 compatible = "ti,am33xx-pwmss"; 2075 reg = <0x0 0x10>; 2076 #address-cells = <1>; 2077 #size-cells = <1>; 2078 status = "disabled"; 2079 ranges = <0 0 0x1000>; 2080 2081 ecap0: pwm@100 { 2082 compatible = "ti,am3352-ecap"; 2083 #pwm-cells = <3>; 2084 reg = <0x100 0x80>; 2085 clocks = <&l4ls_gclk>; 2086 clock-names = "fck"; 2087 status = "disabled"; 2088 }; 2089 2090 eqep0: counter@180 { 2091 compatible = "ti,am3352-eqep"; 2092 reg = <0x180 0x80>; 2093 clocks = <&l4ls_gclk>; 2094 clock-names = "sysclkout"; 2095 interrupts = <79>; 2096 status = "disabled"; 2097 }; 2098 2099 ehrpwm0: pwm@200 { 2100 compatible = "ti,am3352-ehrpwm"; 2101 #pwm-cells = <3>; 2102 reg = <0x200 0x80>; 2103 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 2104 clock-names = "tbclk", "fck"; 2105 status = "disabled"; 2106 }; 2107 }; 2108 }; 2109 2110 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 2111 compatible = "ti,sysc-omap4", "ti,sysc"; 2112 reg = <0x2000 0x4>, 2113 <0x2004 0x4>; 2114 reg-names = "rev", "sysc"; 2115 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2116 <SYSC_IDLE_NO>, 2117 <SYSC_IDLE_SMART>, 2118 <SYSC_IDLE_SMART_WKUP>; 2119 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2120 <SYSC_IDLE_NO>, 2121 <SYSC_IDLE_SMART>, 2122 <SYSC_IDLE_SMART_WKUP>; 2123 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2124 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 2125 clock-names = "fck"; 2126 #address-cells = <1>; 2127 #size-cells = <1>; 2128 ranges = <0x0 0x2000 0x1000>; 2129 2130 epwmss1: epwmss@0 { 2131 compatible = "ti,am33xx-pwmss"; 2132 reg = <0x0 0x10>; 2133 #address-cells = <1>; 2134 #size-cells = <1>; 2135 status = "disabled"; 2136 ranges = <0 0 0x1000>; 2137 2138 ecap1: pwm@100 { 2139 compatible = "ti,am3352-ecap"; 2140 #pwm-cells = <3>; 2141 reg = <0x100 0x80>; 2142 clocks = <&l4ls_gclk>; 2143 clock-names = "fck"; 2144 status = "disabled"; 2145 }; 2146 2147 eqep1: counter@180 { 2148 compatible = "ti,am3352-eqep"; 2149 reg = <0x180 0x80>; 2150 clocks = <&l4ls_gclk>; 2151 clock-names = "sysclkout"; 2152 interrupts = <88>; 2153 status = "disabled"; 2154 }; 2155 2156 ehrpwm1: pwm@200 { 2157 compatible = "ti,am3352-ehrpwm"; 2158 #pwm-cells = <3>; 2159 reg = <0x200 0x80>; 2160 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 2161 clock-names = "tbclk", "fck"; 2162 status = "disabled"; 2163 }; 2164 }; 2165 }; 2166 2167 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 2168 compatible = "ti,sysc-omap4", "ti,sysc"; 2169 reg = <0x4000 0x4>, 2170 <0x4004 0x4>; 2171 reg-names = "rev", "sysc"; 2172 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2173 <SYSC_IDLE_NO>, 2174 <SYSC_IDLE_SMART>, 2175 <SYSC_IDLE_SMART_WKUP>; 2176 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2177 <SYSC_IDLE_NO>, 2178 <SYSC_IDLE_SMART>, 2179 <SYSC_IDLE_SMART_WKUP>; 2180 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2181 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 2182 clock-names = "fck"; 2183 #address-cells = <1>; 2184 #size-cells = <1>; 2185 ranges = <0x0 0x4000 0x1000>; 2186 2187 epwmss2: epwmss@0 { 2188 compatible = "ti,am33xx-pwmss"; 2189 reg = <0x0 0x10>; 2190 #address-cells = <1>; 2191 #size-cells = <1>; 2192 status = "disabled"; 2193 ranges = <0 0 0x1000>; 2194 2195 ecap2: pwm@100 { 2196 compatible = "ti,am3352-ecap"; 2197 #pwm-cells = <3>; 2198 reg = <0x100 0x80>; 2199 clocks = <&l4ls_gclk>; 2200 clock-names = "fck"; 2201 status = "disabled"; 2202 }; 2203 2204 eqep2: counter@180 { 2205 compatible = "ti,am3352-eqep"; 2206 reg = <0x180 0x80>; 2207 clocks = <&l4ls_gclk>; 2208 clock-names = "sysclkout"; 2209 interrupts = <89>; 2210 status = "disabled"; 2211 }; 2212 2213 ehrpwm2: pwm@200 { 2214 compatible = "ti,am3352-ehrpwm"; 2215 #pwm-cells = <3>; 2216 reg = <0x200 0x80>; 2217 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2218 clock-names = "tbclk", "fck"; 2219 status = "disabled"; 2220 }; 2221 }; 2222 }; 2223 2224 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2225 compatible = "ti,sysc-omap4", "ti,sysc"; 2226 reg = <0xe000 0x4>, 2227 <0xe054 0x4>; 2228 reg-names = "rev", "sysc"; 2229 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2230 <SYSC_IDLE_NO>, 2231 <SYSC_IDLE_SMART>; 2232 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2233 <SYSC_IDLE_NO>, 2234 <SYSC_IDLE_SMART>; 2235 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2236 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2237 clock-names = "fck"; 2238 #address-cells = <1>; 2239 #size-cells = <1>; 2240 ranges = <0x0 0xe000 0x1000>; 2241 2242 lcdc: lcdc@0 { 2243 compatible = "ti,am33xx-tilcdc"; 2244 reg = <0x0 0x1000>; 2245 interrupts = <36>; 2246 status = "disabled"; 2247 }; 2248 }; 2249 2250 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2251 compatible = "ti,sysc-omap2", "ti,sysc"; 2252 reg = <0x11fe0 0x4>, 2253 <0x11fe4 0x4>; 2254 reg-names = "rev", "sysc"; 2255 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2256 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2257 <SYSC_IDLE_NO>; 2258 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2259 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2260 clock-names = "fck"; 2261 #address-cells = <1>; 2262 #size-cells = <1>; 2263 ranges = <0x0 0x10000 0x2000>; 2264 2265 rng: rng@0 { 2266 compatible = "ti,omap4-rng"; 2267 reg = <0x0 0x2000>; 2268 interrupts = <111>; 2269 }; 2270 }; 2271 2272 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2273 compatible = "ti,sysc"; 2274 status = "disabled"; 2275 #address-cells = <1>; 2276 #size-cells = <1>; 2277 ranges = <0x0 0x13000 0x1000>; 2278 }; 2279 2280 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2281 compatible = "ti,sysc"; 2282 status = "disabled"; 2283 #address-cells = <1>; 2284 #size-cells = <1>; 2285 ranges = <0x00000000 0x00015000 0x00001000>, 2286 <0x00001000 0x00016000 0x00001000>; 2287 }; 2288 2289 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2290 compatible = "ti,sysc"; 2291 status = "disabled"; 2292 #address-cells = <1>; 2293 #size-cells = <1>; 2294 ranges = <0x0 0x18000 0x4000>; 2295 }; 2296 2297 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2298 compatible = "ti,sysc"; 2299 status = "disabled"; 2300 #address-cells = <1>; 2301 #size-cells = <1>; 2302 ranges = <0x0 0x20000 0x1000>; 2303 }; 2304 2305 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2306 compatible = "ti,sysc"; 2307 status = "disabled"; 2308 #address-cells = <1>; 2309 #size-cells = <1>; 2310 ranges = <0x0 0x22000 0x1000>; 2311 }; 2312 2313 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2314 compatible = "ti,sysc"; 2315 status = "disabled"; 2316 #address-cells = <1>; 2317 #size-cells = <1>; 2318 ranges = <0x0 0x24000 0x1000>; 2319 }; 2320 }; 2321}; 2322 2323