1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 General Electric Company
4 *
5 * Based on board/freescale/mx53loco/mx53loco.c:
6 *
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jason Liu <r64343@freescale.com>
9 */
10
11 #include <common.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/clock.h>
19 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/mx5_video.h>
22 #include <environment.h>
23 #include <netdev.h>
24 #include <i2c.h>
25 #include <mmc.h>
26 #include <fsl_esdhc.h>
27 #include <asm/gpio.h>
28 #include <power/pmic.h>
29 #include <dialog_pmic.h>
30 #include <fsl_pmic.h>
31 #include <linux/fb.h>
32 #include <ipu_pixfmt.h>
33 #include <watchdog.h>
34 #include "ppd_gpio.h"
35 #include <stdlib.h>
36 #include "../../ge/common/ge_common.h"
37 #include "../../ge/common/vpd_reader.h"
38
39 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 static u32 mx53_dram_size[2];
44
get_effective_memsize(void)45 phys_size_t get_effective_memsize(void)
46 {
47 /*
48 * WARNING: We must override get_effective_memsize() function here
49 * to report only the size of the first DRAM bank. This is to make
50 * U-Boot relocator place U-Boot into valid memory, that is, at the
51 * end of the first DRAM bank. If we did not override this function
52 * like so, U-Boot would be placed at the address of the first DRAM
53 * bank + total DRAM size - sizeof(uboot), which in the setup where
54 * each DRAM bank contains 512MiB of DRAM would result in placing
55 * U-Boot into invalid memory area close to the end of the first
56 * DRAM bank.
57 */
58 return mx53_dram_size[0];
59 }
60
dram_init(void)61 int dram_init(void)
62 {
63 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
64 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
65
66 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
67
68 return 0;
69 }
70
dram_init_banksize(void)71 int dram_init_banksize(void)
72 {
73 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
74 gd->bd->bi_dram[0].size = mx53_dram_size[0];
75
76 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
77 gd->bd->bi_dram[1].size = mx53_dram_size[1];
78
79 return 0;
80 }
81
get_board_rev(void)82 u32 get_board_rev(void)
83 {
84 return get_cpu_rev() & ~(0xF << 8);
85 }
86
87 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
88 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
89
90 #ifdef CONFIG_USB_EHCI_MX5
board_ehci_hcd_init(int port)91 int board_ehci_hcd_init(int port)
92 {
93 /* request VBUS power enable pin, GPIO7_8 */
94 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
95 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
96 return 0;
97 }
98 #endif
99
setup_iomux_fec(void)100 static void setup_iomux_fec(void)
101 {
102 static const iomux_v3_cfg_t fec_pads[] = {
103 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
104 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
105 PAD_CTL_ODE),
106 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
107 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
108 PAD_CTL_HYS | PAD_CTL_PKE),
109 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
110 PAD_CTL_HYS | PAD_CTL_PKE),
111 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
112 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
113 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
114 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
115 PAD_CTL_HYS | PAD_CTL_PKE),
116 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
117 PAD_CTL_HYS | PAD_CTL_PKE),
118 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
119 PAD_CTL_HYS | PAD_CTL_PKE),
120 };
121
122 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
123 }
124
125 #ifdef CONFIG_FSL_ESDHC
126 struct fsl_esdhc_cfg esdhc_cfg[2] = {
127 {MMC_SDHC3_BASE_ADDR},
128 {MMC_SDHC1_BASE_ADDR},
129 };
130
board_mmc_getcd(struct mmc * mmc)131 int board_mmc_getcd(struct mmc *mmc)
132 {
133 return 1;
134 }
135
136 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
137 PAD_CTL_PUS_100K_UP)
138 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
139 PAD_CTL_DSE_HIGH)
140
board_mmc_init(bd_t * bis)141 int board_mmc_init(bd_t *bis)
142 {
143 static const iomux_v3_cfg_t sd1_pads[] = {
144 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
145 SD_CMD_PAD_CTRL),
146 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
147 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
148 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
149 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
150 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
151 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
152 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
153 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
154 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
155 MX53_PAD_EIM_DA11__GPIO3_11,
156 };
157
158 static const iomux_v3_cfg_t sd2_pads[] = {
159 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
160 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
161 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
162 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
163 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
164 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
165 MX53_PAD_EIM_DA13__GPIO3_13,
166 };
167
168 u32 index;
169 int ret;
170
171 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
172 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
173
174 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
175 switch (index) {
176 case 0:
177 imx_iomux_v3_setup_multiple_pads(sd1_pads,
178 ARRAY_SIZE(sd1_pads));
179 break;
180 case 1:
181 imx_iomux_v3_setup_multiple_pads(sd2_pads,
182 ARRAY_SIZE(sd2_pads));
183 break;
184 default:
185 printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
186 CONFIG_SYS_FSL_ESDHC_NUM);
187 return -EINVAL;
188 }
189 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
190 if (ret)
191 return ret;
192 }
193
194 return 0;
195 }
196 #endif
197
198 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
199 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
200
setup_iomux_i2c(void)201 static void setup_iomux_i2c(void)
202 {
203 static const iomux_v3_cfg_t i2c1_pads[] = {
204 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
205 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
206 };
207
208 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
209 }
210
211 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
212
213 static struct i2c_pads_info i2c_pad_info1 = {
214 .scl = {
215 .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
216 .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
217 .gp = IMX_GPIO_NR(3, 28)
218 },
219 .sda = {
220 .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
221 .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
222 .gp = IMX_GPIO_NR(3, 21)
223 }
224 };
225
clock_1GHz(void)226 static int clock_1GHz(void)
227 {
228 int ret;
229 u32 ref_clk = MXC_HCLK;
230 /*
231 * After increasing voltage to 1.25V, we can switch
232 * CPU clock to 1GHz and DDR to 400MHz safely
233 */
234 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
235 if (ret) {
236 printf("CPU: Switch CPU clock to 1GHZ failed\n");
237 return -1;
238 }
239
240 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
241 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
242 if (ret) {
243 printf("CPU: Switch DDR clock to 400MHz failed\n");
244 return -1;
245 }
246
247 return 0;
248 }
249
ppd_gpio_init(void)250 void ppd_gpio_init(void)
251 {
252 int i;
253
254 imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
255 for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
256 gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
257 }
258
board_early_init_f(void)259 int board_early_init_f(void)
260 {
261 setup_iomux_fec();
262 setup_iomux_lcd();
263 ppd_gpio_init();
264
265 return 0;
266 }
267
268 /*
269 * Do not overwrite the console
270 * Use always serial for U-Boot console
271 */
overwrite_console(void)272 int overwrite_console(void)
273 {
274 return 1;
275 }
276
277 #define VPD_TYPE_INVALID 0x00
278 #define VPD_BLOCK_NETWORK 0x20
279 #define VPD_BLOCK_HWID 0x44
280 #define VPD_PRODUCT_PPD 4
281 #define VPD_HAS_MAC1 0x1
282 #define VPD_MAC_ADDRESS_LENGTH 6
283
284 struct vpd_cache {
285 u8 product_id;
286 u8 has;
287 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
288 };
289
290 /*
291 * Extracts MAC and product information from the VPD.
292 */
vpd_callback(struct vpd_cache * userdata,u8 id,u8 version,u8 type,size_t size,u8 const * data)293 static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
294 u8 type, size_t size, u8 const *data)
295 {
296 struct vpd_cache *vpd = userdata;
297
298 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
299 size >= 1) {
300 vpd->product_id = data[0];
301
302 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
303 type != VPD_TYPE_INVALID) {
304 if (size >= 6) {
305 vpd->has |= VPD_HAS_MAC1;
306 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
307 }
308 }
309
310 return 0;
311 }
312
process_vpd(struct vpd_cache * vpd)313 static void process_vpd(struct vpd_cache *vpd)
314 {
315 int fec_index = -1;
316
317 if (vpd->product_id == VPD_PRODUCT_PPD)
318 fec_index = 0;
319
320 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
321 eth_env_set_enetaddr("ethaddr", vpd->mac1);
322 }
323
board_init(void)324 int board_init(void)
325 {
326 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
327
328 mxc_set_sata_internal_clock();
329 setup_iomux_i2c();
330
331 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
332
333 return 0;
334 }
335
misc_init_r(void)336 int misc_init_r(void)
337 {
338 const char *cause;
339
340 /* We care about WDOG only, treating everything else as
341 * a power-on-reset.
342 */
343 if (get_imx_reset_cause() & 0x0010)
344 cause = "WDOG";
345 else
346 cause = "POR";
347
348 env_set("bootcause", cause);
349
350 return 0;
351 }
352
board_late_init(void)353 int board_late_init(void)
354 {
355 int res;
356 struct vpd_cache vpd;
357
358 memset(&vpd, 0, sizeof(vpd));
359 res = read_vpd(&vpd, vpd_callback);
360 if (!res)
361 process_vpd(&vpd);
362 else
363 printf("Can't read VPD");
364
365 res = clock_1GHz();
366 if (res != 0)
367 return res;
368
369 print_cpuinfo();
370 hw_watchdog_init();
371
372 check_time();
373
374 return 0;
375 }
376
checkboard(void)377 int checkboard(void)
378 {
379 puts("Board: GE PPD\n");
380
381 return 0;
382 }
383