1
2 /*
3 * PowerPC CPU initialization for qemu.
4 *
5 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "disas/dis-asm.h"
24 #include "gdbstub/helpers.h"
25 #include "system/cpus.h"
26 #include "system/hw_accel.h"
27 #include "system/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qobject/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "exec/watchpoint.h"
44 #include "helper_regs.h"
45 #include "internal.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
48 #ifndef CONFIG_USER_ONLY
49 #include "hw/boards.h"
50 #include "hw/intc/intc.h"
51 #include "kvm_ppc.h"
52 #endif
53
54 #include "cpu_init.h"
55 /* #define PPC_DEBUG_SPR */
56 /* #define USE_APPLE_GDB */
57
58 static const Property powerpc_cpu_properties[] = {
59 DEFINE_PROP_BOOL("rtas-stopped-state", PowerPCCPU,
60 rtas_stopped_state, true),
61 };
62
vscr_init(CPUPPCState * env,uint32_t val)63 static inline void vscr_init(CPUPPCState *env, uint32_t val)
64 {
65 /* Altivec always uses round-to-nearest */
66 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
67 ppc_store_vscr(env, val);
68 }
69
register_745_sprs(CPUPPCState * env)70 static void register_745_sprs(CPUPPCState *env)
71 {
72 /* SGPRs */
73 spr_register(env, SPR_SPRG4, "SPRG4",
74 SPR_NOACCESS, SPR_NOACCESS,
75 &spr_read_generic, &spr_write_generic,
76 0x00000000);
77 spr_register(env, SPR_SPRG5, "SPRG5",
78 SPR_NOACCESS, SPR_NOACCESS,
79 &spr_read_generic, &spr_write_generic,
80 0x00000000);
81 spr_register(env, SPR_SPRG6, "SPRG6",
82 SPR_NOACCESS, SPR_NOACCESS,
83 &spr_read_generic, &spr_write_generic,
84 0x00000000);
85 spr_register(env, SPR_SPRG7, "SPRG7",
86 SPR_NOACCESS, SPR_NOACCESS,
87 &spr_read_generic, &spr_write_generic,
88 0x00000000);
89
90 /* Hardware implementation registers */
91 spr_register(env, SPR_HID0, "HID0",
92 SPR_NOACCESS, SPR_NOACCESS,
93 &spr_read_generic, &spr_write_generic,
94 0x00000000);
95
96 spr_register(env, SPR_HID1, "HID1",
97 SPR_NOACCESS, SPR_NOACCESS,
98 &spr_read_generic, &spr_write_generic,
99 0x00000000);
100
101 spr_register(env, SPR_HID2, "HID2",
102 SPR_NOACCESS, SPR_NOACCESS,
103 &spr_read_generic, &spr_write_generic,
104 0x00000000);
105 }
106
register_755_sprs(CPUPPCState * env)107 static void register_755_sprs(CPUPPCState *env)
108 {
109 /* L2 cache control */
110 spr_register(env, SPR_L2CR, "L2CR",
111 SPR_NOACCESS, SPR_NOACCESS,
112 &spr_read_generic, spr_access_nop,
113 0x00000000);
114
115 spr_register(env, SPR_L2PMCR, "L2PMCR",
116 SPR_NOACCESS, SPR_NOACCESS,
117 &spr_read_generic, &spr_write_generic,
118 0x00000000);
119 }
120
121 /* SPR common to all 7xx PowerPC implementations */
register_7xx_sprs(CPUPPCState * env)122 static void register_7xx_sprs(CPUPPCState *env)
123 {
124 /* Breakpoints */
125 spr_register_kvm(env, SPR_DABR, "DABR",
126 SPR_NOACCESS, SPR_NOACCESS,
127 &spr_read_generic, &spr_write_generic,
128 KVM_REG_PPC_DABR, 0x00000000);
129
130 spr_register(env, SPR_IABR, "IABR",
131 SPR_NOACCESS, SPR_NOACCESS,
132 &spr_read_generic, &spr_write_generic,
133 0x00000000);
134 /* Cache management */
135 spr_register(env, SPR_ICTC, "ICTC",
136 SPR_NOACCESS, SPR_NOACCESS,
137 &spr_read_generic, &spr_write_generic,
138 0x00000000);
139 /* Performance monitors */
140 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
141 SPR_NOACCESS, SPR_NOACCESS,
142 &spr_read_generic, &spr_write_generic,
143 0x00000000);
144
145 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
146 SPR_NOACCESS, SPR_NOACCESS,
147 &spr_read_generic, &spr_write_generic,
148 0x00000000);
149
150 spr_register(env, SPR_7XX_PMC1, "PMC1",
151 SPR_NOACCESS, SPR_NOACCESS,
152 &spr_read_generic, &spr_write_generic,
153 0x00000000);
154
155 spr_register(env, SPR_7XX_PMC2, "PMC2",
156 SPR_NOACCESS, SPR_NOACCESS,
157 &spr_read_generic, &spr_write_generic,
158 0x00000000);
159
160 spr_register(env, SPR_7XX_PMC3, "PMC3",
161 SPR_NOACCESS, SPR_NOACCESS,
162 &spr_read_generic, &spr_write_generic,
163 0x00000000);
164
165 spr_register(env, SPR_7XX_PMC4, "PMC4",
166 SPR_NOACCESS, SPR_NOACCESS,
167 &spr_read_generic, &spr_write_generic,
168 0x00000000);
169
170 spr_register(env, SPR_7XX_SIAR, "SIAR",
171 SPR_NOACCESS, SPR_NOACCESS,
172 &spr_read_generic, SPR_NOACCESS,
173 0x00000000);
174
175 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
176 &spr_read_ureg, SPR_NOACCESS,
177 &spr_read_ureg, SPR_NOACCESS,
178 0x00000000);
179
180 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
181 &spr_read_ureg, SPR_NOACCESS,
182 &spr_read_ureg, SPR_NOACCESS,
183 0x00000000);
184
185 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
186 &spr_read_ureg, SPR_NOACCESS,
187 &spr_read_ureg, SPR_NOACCESS,
188 0x00000000);
189
190 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
191 &spr_read_ureg, SPR_NOACCESS,
192 &spr_read_ureg, SPR_NOACCESS,
193 0x00000000);
194
195 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
196 &spr_read_ureg, SPR_NOACCESS,
197 &spr_read_ureg, SPR_NOACCESS,
198 0x00000000);
199
200 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
201 &spr_read_ureg, SPR_NOACCESS,
202 &spr_read_ureg, SPR_NOACCESS,
203 0x00000000);
204
205 spr_register(env, SPR_7XX_USIAR, "USIAR",
206 &spr_read_ureg, SPR_NOACCESS,
207 &spr_read_ureg, SPR_NOACCESS,
208 0x00000000);
209 /* External access control */
210 spr_register(env, SPR_EAR, "EAR",
211 SPR_NOACCESS, SPR_NOACCESS,
212 &spr_read_generic, &spr_write_generic,
213 0x00000000);
214
215 /* Hardware implementation registers */
216 spr_register(env, SPR_HID0, "HID0",
217 SPR_NOACCESS, SPR_NOACCESS,
218 &spr_read_generic, &spr_write_generic,
219 0x00000000);
220
221 spr_register(env, SPR_HID1, "HID1",
222 SPR_NOACCESS, SPR_NOACCESS,
223 &spr_read_generic, &spr_write_generic,
224 0x00000000);
225 }
226
227 #ifdef TARGET_PPC64
register_amr_sprs(CPUPPCState * env)228 static void register_amr_sprs(CPUPPCState *env)
229 {
230 #ifndef CONFIG_USER_ONLY
231 /*
232 * Virtual Page Class Key protection
233 *
234 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
235 * userspace accessible, 29 is privileged. So we only need to set
236 * the kvm ONE_REG id on one of them, we use 29
237 */
238 spr_register(env, SPR_UAMR, "UAMR",
239 &spr_read_generic, &spr_write_amr,
240 &spr_read_generic, &spr_write_amr,
241 0);
242 spr_register_kvm_hv(env, SPR_AMR, "AMR",
243 SPR_NOACCESS, SPR_NOACCESS,
244 &spr_read_generic, &spr_write_amr,
245 &spr_read_generic, &spr_write_generic,
246 KVM_REG_PPC_AMR, 0);
247 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
248 SPR_NOACCESS, SPR_NOACCESS,
249 &spr_read_generic, &spr_write_uamor,
250 &spr_read_generic, &spr_write_generic,
251 KVM_REG_PPC_UAMOR, 0);
252 spr_register_hv(env, SPR_AMOR, "AMOR",
253 SPR_NOACCESS, SPR_NOACCESS,
254 SPR_NOACCESS, SPR_NOACCESS,
255 &spr_read_generic, &spr_core_lpar_write_generic,
256 0);
257 #endif /* !CONFIG_USER_ONLY */
258 }
259
register_iamr_sprs(CPUPPCState * env)260 static void register_iamr_sprs(CPUPPCState *env)
261 {
262 #ifndef CONFIG_USER_ONLY
263 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
264 SPR_NOACCESS, SPR_NOACCESS,
265 &spr_read_generic, &spr_write_iamr,
266 &spr_read_generic, &spr_write_generic,
267 KVM_REG_PPC_IAMR, 0);
268 #endif /* !CONFIG_USER_ONLY */
269 }
270 #endif /* TARGET_PPC64 */
271
272 /* SPR specific to PowerPC 604 implementation */
register_604_sprs(CPUPPCState * env)273 static void register_604_sprs(CPUPPCState *env)
274 {
275 /* Processor identification */
276 spr_register(env, SPR_PIR, "PIR",
277 SPR_NOACCESS, SPR_NOACCESS,
278 &spr_read_generic, &spr_write_pir,
279 0x00000000);
280 /* Breakpoints */
281 spr_register(env, SPR_IABR, "IABR",
282 SPR_NOACCESS, SPR_NOACCESS,
283 &spr_read_generic, &spr_write_generic,
284 0x00000000);
285
286 spr_register_kvm(env, SPR_DABR, "DABR",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_generic, &spr_write_generic,
289 KVM_REG_PPC_DABR, 0x00000000);
290 /* Performance counters */
291 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
292 SPR_NOACCESS, SPR_NOACCESS,
293 &spr_read_generic, &spr_write_generic,
294 0x00000000);
295
296 spr_register(env, SPR_7XX_PMC1, "PMC1",
297 SPR_NOACCESS, SPR_NOACCESS,
298 &spr_read_generic, &spr_write_generic,
299 0x00000000);
300
301 spr_register(env, SPR_7XX_PMC2, "PMC2",
302 SPR_NOACCESS, SPR_NOACCESS,
303 &spr_read_generic, &spr_write_generic,
304 0x00000000);
305
306 spr_register(env, SPR_7XX_SIAR, "SIAR",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_generic, SPR_NOACCESS,
309 0x00000000);
310
311 spr_register(env, SPR_SDA, "SDA",
312 SPR_NOACCESS, SPR_NOACCESS,
313 &spr_read_generic, SPR_NOACCESS,
314 0x00000000);
315 /* External access control */
316 spr_register(env, SPR_EAR, "EAR",
317 SPR_NOACCESS, SPR_NOACCESS,
318 &spr_read_generic, &spr_write_generic,
319 0x00000000);
320
321 /* Hardware implementation registers */
322 spr_register(env, SPR_HID0, "HID0",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_generic, &spr_write_generic,
325 0x00000000);
326 }
327
register_604e_sprs(CPUPPCState * env)328 static void register_604e_sprs(CPUPPCState *env)
329 {
330 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_generic, &spr_write_generic,
333 0x00000000);
334
335 spr_register(env, SPR_7XX_PMC3, "PMC3",
336 SPR_NOACCESS, SPR_NOACCESS,
337 &spr_read_generic, &spr_write_generic,
338 0x00000000);
339
340 spr_register(env, SPR_7XX_PMC4, "PMC4",
341 SPR_NOACCESS, SPR_NOACCESS,
342 &spr_read_generic, &spr_write_generic,
343 0x00000000);
344 /* Hardware implementation registers */
345 spr_register(env, SPR_HID1, "HID1",
346 SPR_NOACCESS, SPR_NOACCESS,
347 &spr_read_generic, &spr_write_generic,
348 0x00000000);
349 }
350
351 /* SPR specific to PowerPC 603 implementation */
register_603_sprs(CPUPPCState * env)352 static void register_603_sprs(CPUPPCState *env)
353 {
354 /* External access control */
355 spr_register(env, SPR_EAR, "EAR",
356 SPR_NOACCESS, SPR_NOACCESS,
357 &spr_read_generic, &spr_write_generic,
358 0x00000000);
359 /* Breakpoints */
360 spr_register(env, SPR_IABR, "IABR",
361 SPR_NOACCESS, SPR_NOACCESS,
362 &spr_read_generic, &spr_write_generic,
363 0x00000000);
364
365 spr_register(env, SPR_HID0, "HID0",
366 SPR_NOACCESS, SPR_NOACCESS,
367 &spr_read_generic, &spr_write_generic,
368 0x00000000);
369
370 spr_register(env, SPR_HID1, "HID1",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_generic, &spr_write_generic,
373 0x00000000);
374 }
375
register_e300_sprs(CPUPPCState * env)376 static void register_e300_sprs(CPUPPCState *env)
377 {
378 /* hardware implementation registers */
379 spr_register(env, SPR_HID2, "HID2",
380 SPR_NOACCESS, SPR_NOACCESS,
381 &spr_read_generic, &spr_write_generic,
382 0x00000000);
383 /* Breakpoints */
384 spr_register(env, SPR_DABR, "DABR",
385 SPR_NOACCESS, SPR_NOACCESS,
386 &spr_read_generic, &spr_write_generic,
387 0x00000000);
388
389 spr_register(env, SPR_DABR2, "DABR2",
390 SPR_NOACCESS, SPR_NOACCESS,
391 &spr_read_generic, &spr_write_generic,
392 0x00000000);
393
394 spr_register(env, SPR_IABR2, "IABR2",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_generic, &spr_write_generic,
397 0x00000000);
398
399 spr_register(env, SPR_IBCR, "IBCR",
400 SPR_NOACCESS, SPR_NOACCESS,
401 &spr_read_generic, &spr_write_generic,
402 0x00000000);
403
404 spr_register(env, SPR_DBCR, "DBCR",
405 SPR_NOACCESS, SPR_NOACCESS,
406 &spr_read_generic, &spr_write_generic,
407 0x00000000);
408 }
409
410 /* SPR specific to PowerPC G2 implementation */
register_G2_sprs(CPUPPCState * env)411 static void register_G2_sprs(CPUPPCState *env)
412 {
413 /* Memory base address */
414 /* MBAR */
415 spr_register(env, SPR_MBAR, "MBAR",
416 SPR_NOACCESS, SPR_NOACCESS,
417 &spr_read_generic, &spr_write_generic,
418 0x00000000);
419 /* Exception processing */
420 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
421 SPR_NOACCESS, SPR_NOACCESS,
422 &spr_read_generic, &spr_write_generic,
423 0x00000000);
424 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
425 SPR_NOACCESS, SPR_NOACCESS,
426 &spr_read_generic, &spr_write_generic,
427 0x00000000);
428 /* Breakpoints */
429 spr_register(env, SPR_DABR, "DABR",
430 SPR_NOACCESS, SPR_NOACCESS,
431 &spr_read_generic, &spr_write_generic,
432 0x00000000);
433
434 spr_register(env, SPR_DABR2, "DABR2",
435 SPR_NOACCESS, SPR_NOACCESS,
436 &spr_read_generic, &spr_write_generic,
437 0x00000000);
438
439 spr_register(env, SPR_IABR, "IABR",
440 SPR_NOACCESS, SPR_NOACCESS,
441 &spr_read_generic, &spr_write_generic,
442 0x00000000);
443
444 spr_register(env, SPR_IABR2, "IABR2",
445 SPR_NOACCESS, SPR_NOACCESS,
446 &spr_read_generic, &spr_write_generic,
447 0x00000000);
448
449 spr_register(env, SPR_IBCR, "IBCR",
450 SPR_NOACCESS, SPR_NOACCESS,
451 &spr_read_generic, &spr_write_generic,
452 0x00000000);
453
454 spr_register(env, SPR_DBCR, "DBCR",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458
459 /* External access control */
460 spr_register(env, SPR_EAR, "EAR",
461 SPR_NOACCESS, SPR_NOACCESS,
462 &spr_read_generic, &spr_write_generic,
463 0x00000000);
464 /* Hardware implementation register */
465 spr_register(env, SPR_HID0, "HID0",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_generic, &spr_write_generic,
468 0x00000000);
469
470 spr_register(env, SPR_HID1, "HID1",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
473 0x00000000);
474
475 spr_register(env, SPR_HID2, "HID2",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479
480 /* SGPRs */
481 spr_register(env, SPR_SPRG4, "SPRG4",
482 SPR_NOACCESS, SPR_NOACCESS,
483 &spr_read_generic, &spr_write_generic,
484 0x00000000);
485 spr_register(env, SPR_SPRG5, "SPRG5",
486 SPR_NOACCESS, SPR_NOACCESS,
487 &spr_read_generic, &spr_write_generic,
488 0x00000000);
489 spr_register(env, SPR_SPRG6, "SPRG6",
490 SPR_NOACCESS, SPR_NOACCESS,
491 &spr_read_generic, &spr_write_generic,
492 0x00000000);
493 spr_register(env, SPR_SPRG7, "SPRG7",
494 SPR_NOACCESS, SPR_NOACCESS,
495 &spr_read_generic, &spr_write_generic,
496 0x00000000);
497 }
498
register_74xx_sprs(CPUPPCState * env)499 static void register_74xx_sprs(CPUPPCState *env)
500 {
501 /* Breakpoints */
502 spr_register_kvm(env, SPR_DABR, "DABR",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 KVM_REG_PPC_DABR, 0x00000000);
506
507 spr_register(env, SPR_IABR, "IABR",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_generic, &spr_write_generic,
510 0x00000000);
511 /* Cache management */
512 spr_register(env, SPR_ICTC, "ICTC",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 /* Performance monitors */
517 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521
522 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_generic, &spr_write_generic,
525 0x00000000);
526
527 spr_register(env, SPR_7XX_PMC1, "PMC1",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_generic, &spr_write_generic,
530 0x00000000);
531
532 spr_register(env, SPR_7XX_PMC2, "PMC2",
533 SPR_NOACCESS, SPR_NOACCESS,
534 &spr_read_generic, &spr_write_generic,
535 0x00000000);
536
537 spr_register(env, SPR_7XX_PMC3, "PMC3",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_generic, &spr_write_generic,
540 0x00000000);
541
542 spr_register(env, SPR_7XX_PMC4, "PMC4",
543 SPR_NOACCESS, SPR_NOACCESS,
544 &spr_read_generic, &spr_write_generic,
545 0x00000000);
546
547 spr_register(env, SPR_7XX_SIAR, "SIAR",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_generic, SPR_NOACCESS,
550 0x00000000);
551
552 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
553 &spr_read_ureg, SPR_NOACCESS,
554 &spr_read_ureg, SPR_NOACCESS,
555 0x00000000);
556
557 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
558 &spr_read_ureg, SPR_NOACCESS,
559 &spr_read_ureg, SPR_NOACCESS,
560 0x00000000);
561
562 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
563 &spr_read_ureg, SPR_NOACCESS,
564 &spr_read_ureg, SPR_NOACCESS,
565 0x00000000);
566
567 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
568 &spr_read_ureg, SPR_NOACCESS,
569 &spr_read_ureg, SPR_NOACCESS,
570 0x00000000);
571
572 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
573 &spr_read_ureg, SPR_NOACCESS,
574 &spr_read_ureg, SPR_NOACCESS,
575 0x00000000);
576
577 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
578 &spr_read_ureg, SPR_NOACCESS,
579 &spr_read_ureg, SPR_NOACCESS,
580 0x00000000);
581
582 spr_register(env, SPR_7XX_USIAR, "USIAR",
583 &spr_read_ureg, SPR_NOACCESS,
584 &spr_read_ureg, SPR_NOACCESS,
585 0x00000000);
586 /* External access control */
587 spr_register(env, SPR_EAR, "EAR",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_generic, &spr_write_generic,
590 0x00000000);
591
592 /* Processor identification */
593 spr_register(env, SPR_PIR, "PIR",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_generic, &spr_write_pir,
596 0x00000000);
597
598 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_generic, &spr_write_generic,
601 0x00000000);
602
603 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
604 &spr_read_ureg, SPR_NOACCESS,
605 &spr_read_ureg, SPR_NOACCESS,
606 0x00000000);
607
608 spr_register(env, SPR_BAMR, "BAMR",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_generic, &spr_write_generic,
611 0x00000000);
612
613 spr_register(env, SPR_MSSCR0, "MSSCR0",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_generic, &spr_write_generic,
616 0x00000000);
617 /* Hardware implementation registers */
618 spr_register(env, SPR_HID0, "HID0",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_generic, &spr_write_generic,
621 0x00000000);
622
623 spr_register(env, SPR_HID1, "HID1",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_generic, &spr_write_generic,
626 0x00000000);
627 /* Altivec */
628 spr_register(env, SPR_VRSAVE, "VRSAVE",
629 &spr_read_generic, &spr_write_generic,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632
633 spr_register(env, SPR_L2CR, "L2CR",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, spr_access_nop,
636 0x00000000);
637 }
638
register_l3_ctrl(CPUPPCState * env)639 static void register_l3_ctrl(CPUPPCState *env)
640 {
641 /* L3CR */
642 spr_register(env, SPR_L3CR, "L3CR",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 /* L3ITCR0 */
647 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_generic, &spr_write_generic,
650 0x00000000);
651 /* L3PM */
652 spr_register(env, SPR_L3PM, "L3PM",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0x00000000);
656 }
657
658 /* PowerPC BookE SPR */
register_BookE_sprs(CPUPPCState * env,uint64_t ivor_mask)659 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
660 {
661 const char *ivor_names[64] = {
662 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
663 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
664 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
665 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
666 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
667 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
668 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
669 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
670 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
671 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
672 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
673 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
674 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
675 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
676 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
677 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
678 };
679 #define SPR_BOOKE_IVORxx (-1)
680 int ivor_sprn[64] = {
681 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
682 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
683 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
684 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
685 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
690 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
691 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
693 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
694 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
695 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
696 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
697 };
698 int i;
699
700 /* Interrupt processing */
701 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, &spr_write_generic,
704 0x00000000);
705 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 /* Debug */
710 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714
715 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719
720 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724
725 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729
730 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_40x_dbcr0,
733 0x00000000);
734
735 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_generic, &spr_write_generic,
738 0x00000000);
739
740 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752
753 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_clear,
756 0x00000000);
757 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_BOOKE_ESR, "ESR",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_excp_prefix,
768 0x00000000);
769 /* Exception vectors */
770 for (i = 0; i < 64; i++) {
771 if (ivor_mask & (1ULL << i)) {
772 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
773 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
774 exit(1);
775 }
776 spr_register(env, ivor_sprn[i], ivor_names[i],
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_generic, &spr_write_excp_vector,
779 0x00000000);
780 }
781 }
782 spr_register(env, SPR_BOOKE_PID, "PID",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, &spr_write_booke_pid,
785 0x00000000);
786 spr_register(env, SPR_BOOKE_TCR, "TCR",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_booke_tcr,
789 0x00000000);
790 spr_register(env, SPR_BOOKE_TSR, "TSR",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_booke_tsr,
793 0x00000000);
794 /* Timer */
795 spr_register(env, SPR_DECR, "DECR",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_decr, &spr_write_decr,
798 0x00000000);
799 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
800 SPR_NOACCESS, SPR_NOACCESS,
801 SPR_NOACCESS, &spr_write_generic32,
802 0x00000000);
803 /* SPRGs */
804 spr_register(env, SPR_USPRG0, "USPRG0",
805 &spr_read_generic, &spr_write_generic,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 spr_register(env, SPR_SPRG4, "SPRG4",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, &spr_write_generic,
811 0x00000000);
812 spr_register(env, SPR_SPRG5, "SPRG5",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 spr_register(env, SPR_SPRG6, "SPRG6",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 spr_register(env, SPR_SPRG7, "SPRG7",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, &spr_write_generic,
823 0x00000000);
824 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_generic, &spr_write_generic,
831 0x00000000);
832 }
833
834 #if !defined(CONFIG_USER_ONLY)
register_tlbncfg(uint32_t assoc,uint32_t minsize,uint32_t maxsize,uint32_t flags,uint32_t nentries)835 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
836 uint32_t maxsize, uint32_t flags,
837 uint32_t nentries)
838 {
839 return (assoc << TLBnCFG_ASSOC_SHIFT) |
840 (minsize << TLBnCFG_MINSIZE_SHIFT) |
841 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
842 flags | nentries;
843 }
844 #endif /* !CONFIG_USER_ONLY */
845
846 /* BookE 2.06 storage control registers */
register_BookE206_sprs(CPUPPCState * env,uint32_t mas_mask,uint32_t * tlbncfg,uint32_t mmucfg)847 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
848 uint32_t *tlbncfg, uint32_t mmucfg)
849 {
850 #if !defined(CONFIG_USER_ONLY)
851 const char *mas_names[8] = {
852 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
853 };
854 int mas_sprn[8] = {
855 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
856 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
857 };
858 const char *tlbcfg_names[4] = {
859 "TLB0CFG", "TLB1CFG", "TLB2CFG", "TLB3CFG",
860 };
861 const int tlbcfg_sprn[4] = {
862 SPR_BOOKE_TLB0CFG, SPR_BOOKE_TLB1CFG,
863 SPR_BOOKE_TLB2CFG, SPR_BOOKE_TLB3CFG,
864 };
865 int i;
866
867 /* TLB assist registers */
868 for (i = 0; i < 8; i++) {
869 if (mas_mask & (1 << i)) {
870 spr_register(env, mas_sprn[i], mas_names[i],
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic,
873 (i == 2 && (env->insns_flags & PPC_64B))
874 ? &spr_write_generic : &spr_write_generic32,
875 0x00000000);
876 }
877 }
878 if (env->nb_pids > 1) {
879 spr_register(env, SPR_BOOKE_PID1, "PID1",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_booke_pid,
882 0x00000000);
883 }
884 if (env->nb_pids > 2) {
885 spr_register(env, SPR_BOOKE_PID2, "PID2",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, &spr_write_booke_pid,
888 0x00000000);
889 }
890
891 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_eplc,
894 0x00000000);
895 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_epsc,
898 0x00000000);
899
900 spr_register(env, SPR_MMUCFG, "MMUCFG",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 mmucfg);
904
905 assert(env->nb_ways <= ARRAY_SIZE(tlbcfg_names));
906 for (i = 0; i < env->nb_ways; i++) {
907 spr_register(env, tlbcfg_sprn[i], tlbcfg_names[i],
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
910 tlbncfg[i]);
911 }
912 #endif
913 }
914
register_atb_sprs(CPUPPCState * env)915 static void register_atb_sprs(CPUPPCState *env)
916 {
917 spr_register(env, SPR_ATBL, "ATBL",
918 &spr_read_atbl, SPR_NOACCESS,
919 &spr_read_atbl, SPR_NOACCESS,
920 0x00000000);
921 spr_register(env, SPR_ATBU, "ATBU",
922 &spr_read_atbu, SPR_NOACCESS,
923 &spr_read_atbu, SPR_NOACCESS,
924 0x00000000);
925 }
926
927 /* SPR specific to PowerPC 440 implementation */
register_440_sprs(CPUPPCState * env)928 static void register_440_sprs(CPUPPCState *env)
929 {
930 /* Cache control */
931 spr_register(env, SPR_440_DNV0, "DNV0",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935
936 spr_register(env, SPR_440_DNV1, "DNV1",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940
941 spr_register(env, SPR_440_DNV2, "DNV2",
942 SPR_NOACCESS, SPR_NOACCESS,
943 &spr_read_generic, &spr_write_generic,
944 0x00000000);
945
946 spr_register(env, SPR_440_DNV3, "DNV3",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950
951 spr_register(env, SPR_440_DTV0, "DTV0",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955
956 spr_register(env, SPR_440_DTV1, "DTV1",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960
961 spr_register(env, SPR_440_DTV2, "DTV2",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965
966 spr_register(env, SPR_440_DTV3, "DTV3",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970
971 spr_register(env, SPR_440_DVLIM, "DVLIM",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975
976 spr_register(env, SPR_440_INV0, "INV0",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980
981 spr_register(env, SPR_440_INV1, "INV1",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985
986 spr_register(env, SPR_440_INV2, "INV2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990
991 spr_register(env, SPR_440_INV3, "INV3",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995
996 spr_register(env, SPR_440_ITV0, "ITV0",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000
1001 spr_register(env, SPR_440_ITV1, "ITV1",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005
1006 spr_register(env, SPR_440_ITV2, "ITV2",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010
1011 spr_register(env, SPR_440_ITV3, "ITV3",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015
1016 spr_register(env, SPR_440_IVLIM, "IVLIM",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* Cache debug */
1021 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, SPR_NOACCESS,
1024 0x00000000);
1025
1026 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, SPR_NOACCESS,
1029 0x00000000);
1030
1031 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, SPR_NOACCESS,
1034 0x00000000);
1035
1036 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, SPR_NOACCESS,
1039 0x00000000);
1040
1041 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, SPR_NOACCESS,
1044 0x00000000);
1045
1046 spr_register(env, SPR_440_DBDR, "DBDR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* Processor control */
1051 spr_register(env, SPR_4xx_CCR0, "CCR0",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, SPR_NOACCESS,
1058 0x00000000);
1059 /* Storage control */
1060 spr_register(env, SPR_440_MMUCR, "MMUCR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064
1065 /* Processor identification */
1066 spr_register(env, SPR_BOOKE_PIR, "PIR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_pir,
1069 0x00000000);
1070
1071 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 0x00000000);
1075
1076 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080
1081 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 &spr_read_generic, &spr_write_generic,
1084 0x00000000);
1085
1086 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_generic, &spr_write_generic,
1089 0x00000000);
1090 }
1091
1092 /* SPR shared between PowerPC 40x implementations */
register_40x_sprs(CPUPPCState * env)1093 static void register_40x_sprs(CPUPPCState *env)
1094 {
1095 /* Cache */
1096 /* not emulated, as QEMU do not emulate caches */
1097 spr_register(env, SPR_40x_DCCR, "DCCR",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* not emulated, as QEMU do not emulate caches */
1102 spr_register(env, SPR_40x_ICCR, "ICCR",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 /* not emulated, as QEMU do not emulate caches */
1107 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_generic, SPR_NOACCESS,
1110 0x00000000);
1111 /* Exception */
1112 spr_register(env, SPR_40x_DEAR, "DEAR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 spr_register(env, SPR_40x_ESR, "ESR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 spr_register(env, SPR_40x_EVPR, "EVPR",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_excp_prefix,
1123 0x00000000);
1124 spr_register(env, SPR_40x_SRR2, "SRR2",
1125 &spr_read_generic, &spr_write_generic,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 spr_register(env, SPR_40x_SRR3, "SRR3",
1129 &spr_read_generic, &spr_write_generic,
1130 &spr_read_generic, &spr_write_generic,
1131 0x00000000);
1132 /* Timers */
1133 spr_register(env, SPR_40x_PIT, "PIT",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_40x_pit, &spr_write_40x_pit,
1136 0x00000000);
1137 spr_register(env, SPR_40x_TCR, "TCR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_40x_tcr,
1140 0x00000000);
1141 spr_register(env, SPR_40x_TSR, "TSR",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_40x_tsr,
1144 0x00000000);
1145 }
1146
1147 /* SPR specific to PowerPC 405 implementation */
register_405_sprs(CPUPPCState * env)1148 static void register_405_sprs(CPUPPCState *env)
1149 {
1150 /* MMU */
1151 spr_register(env, SPR_40x_PID, "PID",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_40x_pid,
1154 0x00000000);
1155 spr_register(env, SPR_4xx_CCR0, "CCR0",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_generic,
1158 0x00700000);
1159 /* Debug interface */
1160 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_40x_dbcr0,
1163 0x00000000);
1164
1165 spr_register(env, SPR_405_DBCR1, "DBCR1",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
1169
1170 spr_register(env, SPR_40x_DBSR, "DBSR",
1171 SPR_NOACCESS, SPR_NOACCESS,
1172 &spr_read_generic, &spr_write_clear,
1173 /* Last reset was system reset */
1174 0x00000300);
1175
1176 spr_register(env, SPR_40x_DAC1, "DAC1",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 spr_register(env, SPR_40x_DAC2, "DAC2",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184
1185 spr_register(env, SPR_405_DVC1, "DVC1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189
1190 spr_register(env, SPR_405_DVC2, "DVC2",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194
1195 spr_register(env, SPR_40x_IAC1, "IAC1",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 spr_register(env, SPR_40x_IAC2, "IAC2",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203
1204 spr_register(env, SPR_405_IAC3, "IAC3",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208
1209 spr_register(env, SPR_405_IAC4, "IAC4",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 /* Storage control */
1214 spr_register(env, SPR_405_SLER, "SLER",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_40x_sler,
1217 0x00000000);
1218 spr_register(env, SPR_40x_ZPR, "ZPR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222
1223 spr_register(env, SPR_405_SU0R, "SU0R",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* SPRG */
1228 spr_register(env, SPR_USPRG0, "USPRG0",
1229 &spr_read_ureg, SPR_NOACCESS,
1230 &spr_read_ureg, SPR_NOACCESS,
1231 0x00000000);
1232 spr_register(env, SPR_SPRG4, "SPRG4",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 spr_register(env, SPR_SPRG5, "SPRG5",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240 spr_register(env, SPR_SPRG6, "SPRG6",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244 spr_register(env, SPR_SPRG7, "SPRG7",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 spr_read_generic, &spr_write_generic,
1247 0x00000000);
1248
1249 /* Bus access control */
1250 /* not emulated, as QEMU never does speculative access */
1251 spr_register(env, SPR_40x_SGR, "SGR",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0xFFFFFFFF);
1255 /* not emulated, as QEMU do not emulate caches */
1256 spr_register(env, SPR_40x_DCWR, "DCWR",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1259 0x00000000);
1260 }
1261
1262
register_5xx_8xx_sprs(CPUPPCState * env)1263 static void register_5xx_8xx_sprs(CPUPPCState *env)
1264 {
1265 /* Exception processing */
1266 spr_register_kvm(env, SPR_DSISR, "DSISR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 KVM_REG_PPC_DSISR, 0x00000000);
1270 spr_register_kvm(env, SPR_DAR, "DAR",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 KVM_REG_PPC_DAR, 0x00000000);
1274 /* Timer */
1275 spr_register(env, SPR_DECR, "DECR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_decr, &spr_write_decr,
1278 0x00000000);
1279
1280 spr_register(env, SPR_MPC_EIE, "EIE",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284
1285 spr_register(env, SPR_MPC_EID, "EID",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289
1290 spr_register(env, SPR_MPC_NRI, "NRI",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294
1295 spr_register(env, SPR_MPC_CMPA, "CMPA",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299
1300 spr_register(env, SPR_MPC_CMPB, "CMPB",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304
1305 spr_register(env, SPR_MPC_CMPC, "CMPC",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309
1310 spr_register(env, SPR_MPC_CMPD, "CMPD",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314
1315 spr_register(env, SPR_MPC_ECR, "ECR",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319
1320 spr_register(env, SPR_MPC_DER, "DER",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324
1325 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329
1330 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334
1335 spr_register(env, SPR_MPC_CMPE, "CMPE",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339
1340 spr_register(env, SPR_MPC_CMPF, "CMPF",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344
1345 spr_register(env, SPR_MPC_CMPG, "CMPG",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349
1350 spr_register(env, SPR_MPC_CMPH, "CMPH",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354
1355 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359
1360 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364
1365 spr_register(env, SPR_MPC_BAR, "BAR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369
1370 spr_register(env, SPR_MPC_DPDR, "DPDR",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374
1375 spr_register(env, SPR_MPC_IMMR, "IMMR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 }
1380
register_5xx_sprs(CPUPPCState * env)1381 static void register_5xx_sprs(CPUPPCState *env)
1382 {
1383 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387
1388 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392
1393 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397
1398 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, &spr_write_generic,
1401 0x00000000);
1402
1403 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407
1408 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412
1413 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417
1418 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422
1423 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427
1428 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
1432
1433 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1434 SPR_NOACCESS, SPR_NOACCESS,
1435 &spr_read_generic, &spr_write_generic,
1436 0x00000000);
1437
1438 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_generic,
1441 0x00000000);
1442
1443 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_generic, &spr_write_generic,
1446 0x00000000);
1447
1448 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452
1453 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457
1458 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462
1463 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467
1468 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472
1473 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477
1478 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482
1483 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 }
1488
register_8xx_sprs(CPUPPCState * env)1489 static void register_8xx_sprs(CPUPPCState *env)
1490 {
1491
1492 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_generic,
1495 0x00000000);
1496
1497 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501
1502 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506
1507 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_generic, &spr_write_generic,
1510 0x00000000);
1511
1512 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516
1517 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
1521
1522 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526
1527 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1530 0x00000000);
1531
1532 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536
1537 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541
1542 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546
1547 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551
1552 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556
1557 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561
1562 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566
1567 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571
1572 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576
1577 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581
1582 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586
1587 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591
1592 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596
1597 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, &spr_write_generic,
1600 0x00000000);
1601
1602 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_generic,
1605 0x00000000);
1606
1607 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_generic,
1610 0x00000000);
1611
1612 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, &spr_write_generic,
1615 0x00000000);
1616 }
1617
1618 /*
1619 * AMR => SPR 29 (Power 2.04)
1620 * CTRL => SPR 136 (Power 2.04)
1621 * CTRL => SPR 152 (Power 2.04)
1622 * SCOMC => SPR 276 (64 bits ?)
1623 * SCOMD => SPR 277 (64 bits ?)
1624 * TBU40 => SPR 286 (Power 2.04 hypv)
1625 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1626 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1627 * HDSISR => SPR 306 (Power 2.04 hypv)
1628 * HDAR => SPR 307 (Power 2.04 hypv)
1629 * PURR => SPR 309 (Power 2.04 hypv)
1630 * HDEC => SPR 310 (Power 2.04 hypv)
1631 * HIOR => SPR 311 (hypv)
1632 * RMOR => SPR 312 (970)
1633 * HRMOR => SPR 313 (Power 2.04 hypv)
1634 * HSRR0 => SPR 314 (Power 2.04 hypv)
1635 * HSRR1 => SPR 315 (Power 2.04 hypv)
1636 * LPIDR => SPR 317 (970)
1637 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1638 * EPR => SPR 702 (Power 2.04 emb)
1639 * perf => 768-783 (Power 2.04)
1640 * perf => 784-799 (Power 2.04)
1641 * PPR => SPR 896 (Power 2.04)
1642 * DABRX => 1015 (Power 2.04 hypv)
1643 * FPECR => SPR 1022 (?)
1644 * ... and more (thermal management, performance counters, ...)
1645 */
1646
register_ppe42_sprs(CPUPPCState * env)1647 static void register_ppe42_sprs(CPUPPCState *env)
1648 {
1649 spr_register(env, SPR_PPE42_EDR, "EDR",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 spr_register(env, SPR_PPE42_ISR, "ISR",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, &spr_write_generic,
1656 0x00000000);
1657 spr_register(env, SPR_PPE42_IVPR, "IVPR",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, SPR_NOACCESS,
1660 0xfff80000);
1661 spr_register(env, SPR_PPE42_PIR, "PIR",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_pir,
1664 0x00000000);
1665 spr_register(env, SPR_PPE42_DBCR, "DBCR",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_40x_dbcr0,
1668 0x00000000);
1669 spr_register(env, SPR_PPE42_DACR, "DACR",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* Timer */
1674 spr_register(env, SPR_DECR, "DECR",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_decr, &spr_write_decr,
1677 0x00000000);
1678 spr_register(env, SPR_PPE42_TSR, "TSR",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_booke_tsr,
1681 0x00000000);
1682 spr_register(env, SPR_BOOKE_TCR, "TCR",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_booke_tcr,
1685 0x00000000);
1686 }
1687
1688 /*****************************************************************************/
1689 /* Exception vectors models */
init_excp_4xx(CPUPPCState * env)1690 static void init_excp_4xx(CPUPPCState *env)
1691 {
1692 #if !defined(CONFIG_USER_ONLY)
1693 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1694 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1695 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1696 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1697 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1698 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1699 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1700 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1701 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1702 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1703 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1704 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1705 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1706 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1707 env->ivor_mask = 0x0000FFF0UL;
1708 env->ivpr_mask = 0xFFFF0000UL;
1709 /* Hardware reset vector */
1710 env->hreset_vector = 0xFFFFFFFCUL;
1711 #endif
1712 }
1713
init_excp_ppe42(CPUPPCState * env)1714 static void init_excp_ppe42(CPUPPCState *env)
1715 {
1716 #if !defined(CONFIG_USER_ONLY)
1717 /* Machine Check vector changed after version 0 */
1718 if (((env->spr[SPR_PVR] & 0xf00000ul) >> 20) == 0) {
1719 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1720 } else {
1721 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000020;
1722 }
1723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000040;
1724 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000060;
1725 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000080;
1726 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x000000A0;
1727 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x000000C0;
1728 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x000000E0;
1729 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000100;
1730 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000120;
1731 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000140;
1732 env->ivpr_mask = 0xFFFFFE00UL;
1733 /* Hardware reset vector */
1734 env->hreset_vector = 0x00000040UL;
1735 #endif
1736 }
1737
init_excp_MPC5xx(CPUPPCState * env)1738 static void init_excp_MPC5xx(CPUPPCState *env)
1739 {
1740 #if !defined(CONFIG_USER_ONLY)
1741 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1742 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1743 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1744 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1745 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1746 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1747 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1748 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1749 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1750 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1751 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1752 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1753 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1754 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1755 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1756 env->ivor_mask = 0x0000FFF0UL;
1757 env->ivpr_mask = 0xFFFF0000UL;
1758 /* Hardware reset vector */
1759 env->hreset_vector = 0x00000100UL;
1760 #endif
1761 }
1762
init_excp_MPC8xx(CPUPPCState * env)1763 static void init_excp_MPC8xx(CPUPPCState *env)
1764 {
1765 #if !defined(CONFIG_USER_ONLY)
1766 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1767 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1768 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1769 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1770 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1771 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1772 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1773 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1774 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1775 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1776 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1777 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1778 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1779 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1780 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1781 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1782 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1783 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1784 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1785 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1786 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1787 env->ivor_mask = 0x0000FFF0UL;
1788 env->ivpr_mask = 0xFFFF0000UL;
1789 /* Hardware reset vector */
1790 env->hreset_vector = 0x00000100UL;
1791 #endif
1792 }
1793
init_excp_G2(CPUPPCState * env)1794 static void init_excp_G2(CPUPPCState *env)
1795 {
1796 #if !defined(CONFIG_USER_ONLY)
1797 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1798 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1799 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1800 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1801 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1802 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1803 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1804 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1805 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1806 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1807 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1808 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1809 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1810 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1811 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1812 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1813 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1814 /* Hardware reset vector */
1815 env->hreset_vector = 0x00000100UL;
1816 #endif
1817 }
1818
init_excp_e500(CPUPPCState * env,target_ulong ivpr_mask)1819 static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
1820 {
1821 #if !defined(CONFIG_USER_ONLY)
1822 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1823 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1824 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1825 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1826 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1831 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1832 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1833 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1834 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1835 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1836 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1837 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1838 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1839 /*
1840 * These two are the same IVOR as POWERPC_EXCP_VPU and
1841 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1842 * powerpc_excp().
1843 */
1844 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1845 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1846
1847 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1848 env->ivor_mask = 0x0000FFF7UL;
1849 env->ivpr_mask = ivpr_mask;
1850 /* Hardware reset vector */
1851 env->hreset_vector = 0xFFFFFFFCUL;
1852 #endif
1853 }
1854
init_excp_BookE(CPUPPCState * env)1855 static void init_excp_BookE(CPUPPCState *env)
1856 {
1857 #if !defined(CONFIG_USER_ONLY)
1858 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1859 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1860 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1861 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1862 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1863 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1864 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1865 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1866 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1867 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1868 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1869 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1870 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1871 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1872 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1873 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1874 env->ivor_mask = 0x0000FFF0UL;
1875 env->ivpr_mask = 0xFFFF0000UL;
1876 /* Hardware reset vector */
1877 env->hreset_vector = 0xFFFFFFFCUL;
1878 #endif
1879 }
1880
init_excp_603(CPUPPCState * env)1881 static void init_excp_603(CPUPPCState *env)
1882 {
1883 #if !defined(CONFIG_USER_ONLY)
1884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1895 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1896 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1897 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1900 /* Hardware reset vector */
1901 env->hreset_vector = 0x00000100UL;
1902 #endif
1903 }
1904
init_excp_604(CPUPPCState * env)1905 static void init_excp_604(CPUPPCState *env)
1906 {
1907 #if !defined(CONFIG_USER_ONLY)
1908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1918 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1919 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1920 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1921 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1922 /* Hardware reset vector */
1923 env->hreset_vector = 0x00000100UL;
1924 #endif
1925 }
1926
init_excp_7x0(CPUPPCState * env)1927 static void init_excp_7x0(CPUPPCState *env)
1928 {
1929 #if !defined(CONFIG_USER_ONLY)
1930 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1931 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1932 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1933 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1934 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1935 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1936 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1937 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1938 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1939 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1940 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1941 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1942 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1943 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1944 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1945 /* Hardware reset vector */
1946 env->hreset_vector = 0x00000100UL;
1947 #endif
1948 }
1949
init_excp_750cl(CPUPPCState * env)1950 static void init_excp_750cl(CPUPPCState *env)
1951 {
1952 #if !defined(CONFIG_USER_ONLY)
1953 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1954 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1955 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1956 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1957 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1958 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1959 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1960 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1961 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1962 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1963 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1964 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1965 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1966 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1967 /* Hardware reset vector */
1968 env->hreset_vector = 0x00000100UL;
1969 #endif
1970 }
1971
init_excp_750cx(CPUPPCState * env)1972 static void init_excp_750cx(CPUPPCState *env)
1973 {
1974 #if !defined(CONFIG_USER_ONLY)
1975 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1976 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1977 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1978 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1979 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1980 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1981 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1982 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1983 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1984 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1985 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1986 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1987 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1988 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1989 /* Hardware reset vector */
1990 env->hreset_vector = 0x00000100UL;
1991 #endif
1992 }
1993
1994 /* XXX: Check if this is correct */
init_excp_7x5(CPUPPCState * env)1995 static void init_excp_7x5(CPUPPCState *env)
1996 {
1997 #if !defined(CONFIG_USER_ONLY)
1998 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1999 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2000 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2001 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2002 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2003 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2004 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2005 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2006 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2007 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2008 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2009 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2010 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2011 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2012 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2013 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2014 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2015 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2016 /* Hardware reset vector */
2017 env->hreset_vector = 0x00000100UL;
2018 #endif
2019 }
2020
init_excp_7400(CPUPPCState * env)2021 static void init_excp_7400(CPUPPCState *env)
2022 {
2023 #if !defined(CONFIG_USER_ONLY)
2024 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2025 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2026 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2027 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2033 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2034 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2035 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2036 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2037 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2038 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2039 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2040 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2041 /* Hardware reset vector */
2042 env->hreset_vector = 0x00000100UL;
2043 #endif
2044 }
2045
init_excp_7450(CPUPPCState * env)2046 static void init_excp_7450(CPUPPCState *env)
2047 {
2048 #if !defined(CONFIG_USER_ONLY)
2049 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2050 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2051 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2052 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2053 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2054 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2055 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2056 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2058 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2059 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2060 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2061 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2062 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2063 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2064 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2065 /* Hardware reset vector */
2066 env->hreset_vector = 0x00000100UL;
2067 #endif
2068 }
2069
2070 #if defined(TARGET_PPC64)
init_excp_970(CPUPPCState * env)2071 static void init_excp_970(CPUPPCState *env)
2072 {
2073 #if !defined(CONFIG_USER_ONLY)
2074 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2075 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2076 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2077 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2078 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2079 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2080 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2081 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2082 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2083 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2084 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2085 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2086 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2087 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2088 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2089 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2090 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2091 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2092 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2093 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2094 /* Hardware reset vector */
2095 env->hreset_vector = 0x0000000000000100ULL;
2096 #endif
2097 }
2098
init_excp_POWER7(CPUPPCState * env)2099 static void init_excp_POWER7(CPUPPCState *env)
2100 {
2101 #if !defined(CONFIG_USER_ONLY)
2102 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2103 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2104 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2105 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2106 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2107 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2108 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2109 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2110 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2111 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2112 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2113 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2114 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2115 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2116 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2117 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2118 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2119 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2120 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2121 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2122 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2123 /* Hardware reset vector */
2124 env->hreset_vector = 0x0000000000000100ULL;
2125 #endif
2126 }
2127
init_excp_POWER8(CPUPPCState * env)2128 static void init_excp_POWER8(CPUPPCState *env)
2129 {
2130 init_excp_POWER7(env);
2131
2132 #if !defined(CONFIG_USER_ONLY)
2133 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2134 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2135 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2136 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2137
2138 /* Userland exceptions without vector value in PowerISA v3.1 */
2139 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2140 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2141 #endif
2142 }
2143
init_excp_POWER9(CPUPPCState * env)2144 static void init_excp_POWER9(CPUPPCState *env)
2145 {
2146 init_excp_POWER8(env);
2147
2148 #if !defined(CONFIG_USER_ONLY)
2149 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2150 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2151 #endif
2152 }
2153
init_excp_POWER10(CPUPPCState * env)2154 static void init_excp_POWER10(CPUPPCState *env)
2155 {
2156 init_excp_POWER9(env);
2157 }
2158
2159 #endif
2160
check_pow_hid0(CPUPPCState * env)2161 static int check_pow_hid0(CPUPPCState *env)
2162 {
2163 if (env->spr[SPR_HID0] & 0x00E00000) {
2164 return 1;
2165 }
2166
2167 return 0;
2168 }
2169
check_pow_hid0_74xx(CPUPPCState * env)2170 static int check_pow_hid0_74xx(CPUPPCState *env)
2171 {
2172 if (env->spr[SPR_HID0] & 0x00600000) {
2173 return 1;
2174 }
2175
2176 return 0;
2177 }
2178
2179 #if defined(TARGET_PPC64)
check_attn_hid0(CPUPPCState * env)2180 static int check_attn_hid0(CPUPPCState *env)
2181 {
2182 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) {
2183 return 1;
2184 }
2185
2186 return 0;
2187 }
2188
check_attn_hid0_power9(CPUPPCState * env)2189 static int check_attn_hid0_power9(CPUPPCState *env)
2190 {
2191 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) {
2192 return 1;
2193 }
2194
2195 return 0;
2196 }
2197 #endif
2198
init_tlbs_emb(CPUPPCState * env)2199 static void init_tlbs_emb(CPUPPCState *env)
2200 {
2201 #ifndef CONFIG_USER_ONLY
2202 env->nb_tlb = 64;
2203 env->nb_ways = 1;
2204 env->tlb_type = TLB_EMB;
2205 #endif
2206 }
2207
init_proc_405(CPUPPCState * env)2208 static void init_proc_405(CPUPPCState *env)
2209 {
2210 register_40x_sprs(env);
2211 register_405_sprs(env);
2212 register_usprgh_sprs(env);
2213
2214 init_tlbs_emb(env);
2215 init_excp_4xx(env);
2216 env->dcache_line_size = 32;
2217 env->icache_line_size = 32;
2218 /* Allocate hardware IRQ controller */
2219 ppc40x_irq_init(env_archcpu(env));
2220
2221 SET_FIT_PERIOD(8, 12, 16, 20);
2222 SET_WDT_PERIOD(16, 20, 24, 28);
2223 }
2224
2225 POWERPC_FAMILY(405)(ObjectClass *oc, const void *data)
2226 {
2227 DeviceClass *dc = DEVICE_CLASS(oc);
2228 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2229
2230 dc->desc = "PowerPC 405";
2231 pcc->init_proc = init_proc_405;
2232 pcc->check_pow = check_pow_nocheck;
2233 pcc->check_attn = check_attn_none;
2234 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2235 PPC_DCR | PPC_WRTEE |
2236 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2237 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2238 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2239 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2240 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2241 pcc->msr_mask = (1ull << MSR_WE) |
2242 (1ull << MSR_CE) |
2243 (1ull << MSR_EE) |
2244 (1ull << MSR_PR) |
2245 (1ull << MSR_FP) |
2246 (1ull << MSR_ME) |
2247 (1ull << MSR_DWE) |
2248 (1ull << MSR_DE) |
2249 (1ull << MSR_IR) |
2250 (1ull << MSR_DR);
2251 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2252 pcc->excp_model = POWERPC_EXCP_40x;
2253 pcc->bus_model = PPC_FLAGS_INPUT_405;
2254 pcc->bfd_mach = bfd_mach_ppc_403;
2255 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2256 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2257 }
2258
init_proc_ppe42(CPUPPCState * env)2259 static void init_proc_ppe42(CPUPPCState *env)
2260 {
2261 register_ppe42_sprs(env);
2262
2263 init_excp_ppe42(env);
2264 env->dcache_line_size = 32;
2265 env->icache_line_size = 32;
2266 /* Allocate hardware IRQ controller */
2267 ppc40x_irq_init(env_archcpu(env));
2268
2269 SET_FIT_PERIOD(8, 12, 16, 20);
2270 SET_WDT_PERIOD(16, 20, 24, 28);
2271 }
2272
ppe42_class_common_init(PowerPCCPUClass * pcc)2273 static void ppe42_class_common_init(PowerPCCPUClass *pcc)
2274 {
2275 pcc->init_proc = init_proc_ppe42;
2276 pcc->check_pow = check_pow_nocheck;
2277 pcc->check_attn = check_attn_none;
2278 pcc->insns_flags = PPC_INSNS_BASE |
2279 PPC_WRTEE |
2280 PPC_CACHE |
2281 PPC_CACHE_DCBZ |
2282 PPC_MEM_SYNC;
2283 pcc->msr_mask = R_MSR_SEM_MASK |
2284 (1ull << MSR_IS0) |
2285 R_MSR_SIBRC_MASK |
2286 (1ull << MSR_LP) |
2287 (1ull << MSR_WE) |
2288 (1ull << MSR_IS1) |
2289 (1ull << MSR_UIE) |
2290 (1ull << MSR_EE) |
2291 (1ull << MSR_ME) |
2292 (1ull << MSR_IS2) |
2293 (1ull << MSR_IS3) |
2294 (1ull << MSR_IPE) |
2295 R_MSR_SIBRCA_MASK;
2296 pcc->mmu_model = POWERPC_MMU_REAL;
2297 pcc->excp_model = POWERPC_EXCP_PPE42;
2298 pcc->bus_model = PPC_FLAGS_INPUT_PPE42;
2299 pcc->bfd_mach = bfd_mach_ppc_403;
2300 pcc->flags = POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK;
2301 }
2302
POWERPC_FAMILY(ppe42)2303 POWERPC_FAMILY(ppe42)(ObjectClass *oc, const void *data)
2304 {
2305 DeviceClass *dc = DEVICE_CLASS(oc);
2306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2307
2308 dc->desc = "PPE 42";
2309 pcc->insns_flags2 = PPC2_PPE42;
2310 ppe42_class_common_init(pcc);
2311 }
2312
POWERPC_FAMILY(ppe42x)2313 POWERPC_FAMILY(ppe42x)(ObjectClass *oc, const void *data)
2314 {
2315 DeviceClass *dc = DEVICE_CLASS(oc);
2316 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2317
2318 dc->desc = "PPE 42X";
2319 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X;
2320 ppe42_class_common_init(pcc);
2321 }
2322
POWERPC_FAMILY(ppe42xm)2323 POWERPC_FAMILY(ppe42xm)(ObjectClass *oc, const void *data)
2324 {
2325 DeviceClass *dc = DEVICE_CLASS(oc);
2326 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2327
2328 dc->desc = "PPE 42XM";
2329 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X | PPC2_PPE42XM;
2330 ppe42_class_common_init(pcc);
2331 }
2332
init_proc_440EP(CPUPPCState * env)2333 static void init_proc_440EP(CPUPPCState *env)
2334 {
2335 register_BookE_sprs(env, 0x000000000000FFFFULL);
2336 register_440_sprs(env);
2337 register_usprgh_sprs(env);
2338
2339 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351
2352 spr_register(env, SPR_440_CCR1, "CCR1",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356
2357 init_tlbs_emb(env);
2358 init_excp_BookE(env);
2359 env->dcache_line_size = 32;
2360 env->icache_line_size = 32;
2361 ppc40x_irq_init(env_archcpu(env));
2362
2363 SET_FIT_PERIOD(12, 16, 20, 24);
2364 SET_WDT_PERIOD(20, 24, 28, 32);
2365 }
2366
2367 POWERPC_FAMILY(440EP)(ObjectClass *oc, const void *data)
2368 {
2369 DeviceClass *dc = DEVICE_CLASS(oc);
2370 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2371
2372 dc->desc = "PowerPC 440 EP";
2373 pcc->init_proc = init_proc_440EP;
2374 pcc->check_pow = check_pow_nocheck;
2375 pcc->check_attn = check_attn_none;
2376 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2377 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2378 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2379 PPC_FLOAT_STFIWX |
2380 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2381 PPC_CACHE | PPC_CACHE_ICBI |
2382 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2383 PPC_MEM_TLBSYNC | PPC_MFTB |
2384 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2385 PPC_440_SPEC;
2386 pcc->msr_mask = (1ull << MSR_POW) |
2387 (1ull << MSR_CE) |
2388 (1ull << MSR_EE) |
2389 (1ull << MSR_PR) |
2390 (1ull << MSR_FP) |
2391 (1ull << MSR_ME) |
2392 (1ull << MSR_FE0) |
2393 (1ull << MSR_DWE) |
2394 (1ull << MSR_DE) |
2395 (1ull << MSR_FE1) |
2396 (1ull << MSR_IR) |
2397 (1ull << MSR_DR);
2398 pcc->mmu_model = POWERPC_MMU_BOOKE;
2399 pcc->excp_model = POWERPC_EXCP_BOOKE;
2400 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2401 pcc->bfd_mach = bfd_mach_ppc_403;
2402 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2403 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2404 }
2405
2406 POWERPC_FAMILY(460EX)(ObjectClass *oc, const void *data)
2407 {
2408 DeviceClass *dc = DEVICE_CLASS(oc);
2409 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2410
2411 dc->desc = "PowerPC 460 EX";
2412 pcc->init_proc = init_proc_440EP;
2413 pcc->check_pow = check_pow_nocheck;
2414 pcc->check_attn = check_attn_none;
2415 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2416 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2417 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2418 PPC_FLOAT_STFIWX |
2419 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2420 PPC_CACHE | PPC_CACHE_ICBI |
2421 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2422 PPC_MEM_TLBSYNC | PPC_MFTB |
2423 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2424 PPC_440_SPEC;
2425 pcc->msr_mask = (1ull << MSR_POW) |
2426 (1ull << MSR_CE) |
2427 (1ull << MSR_EE) |
2428 (1ull << MSR_PR) |
2429 (1ull << MSR_FP) |
2430 (1ull << MSR_ME) |
2431 (1ull << MSR_FE0) |
2432 (1ull << MSR_DWE) |
2433 (1ull << MSR_DE) |
2434 (1ull << MSR_FE1) |
2435 (1ull << MSR_IR) |
2436 (1ull << MSR_DR);
2437 pcc->mmu_model = POWERPC_MMU_BOOKE;
2438 pcc->excp_model = POWERPC_EXCP_BOOKE;
2439 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2440 pcc->bfd_mach = bfd_mach_ppc_403;
2441 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2442 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2443 }
2444
init_proc_440GP(CPUPPCState * env)2445 static void init_proc_440GP(CPUPPCState *env)
2446 {
2447 register_BookE_sprs(env, 0x000000000000FFFFULL);
2448 register_440_sprs(env);
2449 register_usprgh_sprs(env);
2450
2451 init_tlbs_emb(env);
2452 init_excp_BookE(env);
2453 env->dcache_line_size = 32;
2454 env->icache_line_size = 32;
2455 /* XXX: TODO: allocate internal IRQ controller */
2456
2457 SET_FIT_PERIOD(12, 16, 20, 24);
2458 SET_WDT_PERIOD(20, 24, 28, 32);
2459 }
2460
2461 POWERPC_FAMILY(440GP)(ObjectClass *oc, const void *data)
2462 {
2463 DeviceClass *dc = DEVICE_CLASS(oc);
2464 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2465
2466 dc->desc = "PowerPC 440 GP";
2467 pcc->init_proc = init_proc_440GP;
2468 pcc->check_pow = check_pow_nocheck;
2469 pcc->check_attn = check_attn_none;
2470 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2471 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2472 PPC_CACHE | PPC_CACHE_ICBI |
2473 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2474 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2475 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2476 PPC_440_SPEC;
2477 pcc->msr_mask = (1ull << MSR_POW) |
2478 (1ull << MSR_CE) |
2479 (1ull << MSR_EE) |
2480 (1ull << MSR_PR) |
2481 (1ull << MSR_FP) |
2482 (1ull << MSR_ME) |
2483 (1ull << MSR_FE0) |
2484 (1ull << MSR_DWE) |
2485 (1ull << MSR_DE) |
2486 (1ull << MSR_FE1) |
2487 (1ull << MSR_IR) |
2488 (1ull << MSR_DR);
2489 pcc->mmu_model = POWERPC_MMU_BOOKE;
2490 pcc->excp_model = POWERPC_EXCP_BOOKE;
2491 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2492 pcc->bfd_mach = bfd_mach_ppc_403;
2493 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2494 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2495 }
2496
init_proc_440x5(CPUPPCState * env)2497 static void init_proc_440x5(CPUPPCState *env)
2498 {
2499 register_BookE_sprs(env, 0x000000000000FFFFULL);
2500 register_440_sprs(env);
2501 register_usprgh_sprs(env);
2502
2503 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515
2516 spr_register(env, SPR_440_CCR1, "CCR1",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520
2521 init_tlbs_emb(env);
2522 init_excp_BookE(env);
2523 env->dcache_line_size = 32;
2524 env->icache_line_size = 32;
2525 ppc40x_irq_init(env_archcpu(env));
2526
2527 SET_FIT_PERIOD(12, 16, 20, 24);
2528 SET_WDT_PERIOD(20, 24, 28, 32);
2529 }
2530
2531 POWERPC_FAMILY(440x5)(ObjectClass *oc, const void *data)
2532 {
2533 DeviceClass *dc = DEVICE_CLASS(oc);
2534 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2535
2536 dc->desc = "PowerPC 440x5";
2537 pcc->init_proc = init_proc_440x5;
2538 pcc->check_pow = check_pow_nocheck;
2539 pcc->check_attn = check_attn_none;
2540 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2541 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2542 PPC_CACHE | PPC_CACHE_ICBI |
2543 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2544 PPC_MEM_TLBSYNC | PPC_MFTB |
2545 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2546 PPC_440_SPEC;
2547 pcc->msr_mask = (1ull << MSR_POW) |
2548 (1ull << MSR_CE) |
2549 (1ull << MSR_EE) |
2550 (1ull << MSR_PR) |
2551 (1ull << MSR_FP) |
2552 (1ull << MSR_ME) |
2553 (1ull << MSR_FE0) |
2554 (1ull << MSR_DWE) |
2555 (1ull << MSR_DE) |
2556 (1ull << MSR_FE1) |
2557 (1ull << MSR_IR) |
2558 (1ull << MSR_DR);
2559 pcc->mmu_model = POWERPC_MMU_BOOKE;
2560 pcc->excp_model = POWERPC_EXCP_BOOKE;
2561 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2562 pcc->bfd_mach = bfd_mach_ppc_403;
2563 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2564 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2565 }
2566
2567 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, const void *data)
2568 {
2569 DeviceClass *dc = DEVICE_CLASS(oc);
2570 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2571
2572 dc->desc = "PowerPC 440x5 with double precision FPU";
2573 pcc->init_proc = init_proc_440x5;
2574 pcc->check_pow = check_pow_nocheck;
2575 pcc->check_attn = check_attn_none;
2576 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2577 PPC_FLOAT | PPC_FLOAT_FSQRT |
2578 PPC_FLOAT_STFIWX |
2579 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2580 PPC_CACHE | PPC_CACHE_ICBI |
2581 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2582 PPC_MEM_TLBSYNC | PPC_MFTB |
2583 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2584 PPC_440_SPEC;
2585 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2586 pcc->msr_mask = (1ull << MSR_POW) |
2587 (1ull << MSR_CE) |
2588 (1ull << MSR_EE) |
2589 (1ull << MSR_PR) |
2590 (1ull << MSR_FP) |
2591 (1ull << MSR_ME) |
2592 (1ull << MSR_FE0) |
2593 (1ull << MSR_DWE) |
2594 (1ull << MSR_DE) |
2595 (1ull << MSR_FE1) |
2596 (1ull << MSR_IR) |
2597 (1ull << MSR_DR);
2598 pcc->mmu_model = POWERPC_MMU_BOOKE;
2599 pcc->excp_model = POWERPC_EXCP_BOOKE;
2600 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2601 pcc->bfd_mach = bfd_mach_ppc_403;
2602 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2603 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2604 }
2605
init_proc_MPC5xx(CPUPPCState * env)2606 static void init_proc_MPC5xx(CPUPPCState *env)
2607 {
2608 register_5xx_8xx_sprs(env);
2609 register_5xx_sprs(env);
2610 init_excp_MPC5xx(env);
2611 env->dcache_line_size = 32;
2612 env->icache_line_size = 32;
2613 /* XXX: TODO: allocate internal IRQ controller */
2614 }
2615
POWERPC_FAMILY(MPC5xx)2616 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, const void *data)
2617 {
2618 DeviceClass *dc = DEVICE_CLASS(oc);
2619 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2620
2621 dc->desc = "Freescale 5xx cores (aka RCPU)";
2622 pcc->init_proc = init_proc_MPC5xx;
2623 pcc->check_pow = check_pow_none;
2624 pcc->check_attn = check_attn_none;
2625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2626 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2627 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2628 PPC_MFTB;
2629 pcc->msr_mask = (1ull << MSR_ILE) |
2630 (1ull << MSR_EE) |
2631 (1ull << MSR_PR) |
2632 (1ull << MSR_FP) |
2633 (1ull << MSR_ME) |
2634 (1ull << MSR_FE0) |
2635 (1ull << MSR_SE) |
2636 (1ull << MSR_DE) |
2637 (1ull << MSR_FE1) |
2638 (1ull << MSR_EP) |
2639 (1ull << MSR_RI) |
2640 (1ull << MSR_LE);
2641 pcc->mmu_model = POWERPC_MMU_REAL;
2642 pcc->excp_model = POWERPC_EXCP_6xx;
2643 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2644 pcc->bfd_mach = bfd_mach_ppc_505;
2645 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2646 POWERPC_FLAG_BUS_CLK;
2647 }
2648
init_proc_MPC8xx(CPUPPCState * env)2649 static void init_proc_MPC8xx(CPUPPCState *env)
2650 {
2651 register_5xx_8xx_sprs(env);
2652 register_8xx_sprs(env);
2653 init_excp_MPC8xx(env);
2654 env->dcache_line_size = 32;
2655 env->icache_line_size = 32;
2656 /* XXX: TODO: allocate internal IRQ controller */
2657 }
2658
POWERPC_FAMILY(MPC8xx)2659 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, const void *data)
2660 {
2661 DeviceClass *dc = DEVICE_CLASS(oc);
2662 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2663
2664 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2665 pcc->init_proc = init_proc_MPC8xx;
2666 pcc->check_pow = check_pow_none;
2667 pcc->check_attn = check_attn_none;
2668 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2669 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2670 PPC_CACHE_ICBI | PPC_MFTB;
2671 pcc->msr_mask = (1ull << MSR_ILE) |
2672 (1ull << MSR_EE) |
2673 (1ull << MSR_PR) |
2674 (1ull << MSR_FP) |
2675 (1ull << MSR_ME) |
2676 (1ull << MSR_SE) |
2677 (1ull << MSR_DE) |
2678 (1ull << MSR_EP) |
2679 (1ull << MSR_IR) |
2680 (1ull << MSR_DR) |
2681 (1ull << MSR_RI) |
2682 (1ull << MSR_LE);
2683 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2684 pcc->excp_model = POWERPC_EXCP_6xx;
2685 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2686 pcc->bfd_mach = bfd_mach_ppc_860;
2687 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2688 POWERPC_FLAG_BUS_CLK;
2689 }
2690
2691 /* Freescale 82xx cores (aka PowerQUICC-II) */
2692
init_proc_G2(CPUPPCState * env)2693 static void init_proc_G2(CPUPPCState *env)
2694 {
2695 register_non_embedded_sprs(env);
2696 register_sdr1_sprs(env);
2697 register_G2_sprs(env);
2698
2699 /* Memory management */
2700 register_low_BATs(env);
2701 register_high_BATs(env);
2702 register_6xx_7xx_soft_tlb(env, 64, 2);
2703 init_excp_G2(env);
2704 env->dcache_line_size = 32;
2705 env->icache_line_size = 32;
2706 /* Allocate hardware IRQ controller */
2707 ppc6xx_irq_init(env_archcpu(env));
2708 }
2709
POWERPC_FAMILY(G2)2710 POWERPC_FAMILY(G2)(ObjectClass *oc, const void *data)
2711 {
2712 DeviceClass *dc = DEVICE_CLASS(oc);
2713 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2714
2715 dc->desc = "PowerPC G2";
2716 pcc->init_proc = init_proc_G2;
2717 pcc->check_pow = check_pow_hid0;
2718 pcc->check_attn = check_attn_none;
2719 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2720 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2721 PPC_FLOAT_STFIWX |
2722 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2723 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2724 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2725 PPC_SEGMENT | PPC_EXTERN;
2726 pcc->msr_mask = (1ull << MSR_POW) |
2727 (1ull << MSR_TGPR) |
2728 (1ull << MSR_EE) |
2729 (1ull << MSR_PR) |
2730 (1ull << MSR_FP) |
2731 (1ull << MSR_ME) |
2732 (1ull << MSR_FE0) |
2733 (1ull << MSR_SE) |
2734 (1ull << MSR_DE) |
2735 (1ull << MSR_FE1) |
2736 (1ull << MSR_AL) |
2737 (1ull << MSR_EP) |
2738 (1ull << MSR_IR) |
2739 (1ull << MSR_DR) |
2740 (1ull << MSR_RI);
2741 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2742 pcc->excp_model = POWERPC_EXCP_6xx;
2743 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2744 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2745 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2746 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2747 }
2748
POWERPC_FAMILY(G2LE)2749 POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
2750 {
2751 DeviceClass *dc = DEVICE_CLASS(oc);
2752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2753
2754 dc->desc = "PowerPC G2LE";
2755 pcc->init_proc = init_proc_G2;
2756 pcc->check_pow = check_pow_hid0;
2757 pcc->check_attn = check_attn_none;
2758 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2759 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2760 PPC_FLOAT_STFIWX |
2761 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2762 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2763 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2764 PPC_SEGMENT | PPC_EXTERN;
2765 pcc->msr_mask = (1ull << MSR_POW) |
2766 (1ull << MSR_TGPR) |
2767 (1ull << MSR_ILE) |
2768 (1ull << MSR_EE) |
2769 (1ull << MSR_PR) |
2770 (1ull << MSR_FP) |
2771 (1ull << MSR_ME) |
2772 (1ull << MSR_FE0) |
2773 (1ull << MSR_SE) |
2774 (1ull << MSR_DE) |
2775 (1ull << MSR_FE1) |
2776 (1ull << MSR_AL) |
2777 (1ull << MSR_EP) |
2778 (1ull << MSR_IR) |
2779 (1ull << MSR_DR) |
2780 (1ull << MSR_RI) |
2781 (1ull << MSR_LE);
2782 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2783 pcc->excp_model = POWERPC_EXCP_6xx;
2784 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2785 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2786 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2787 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2788 }
2789
2790 enum fsl_e500_version {
2791 fsl_e500v1,
2792 fsl_e500v2,
2793 fsl_e500mc,
2794 fsl_e5500,
2795 fsl_e6500,
2796 };
2797
init_proc_e500(CPUPPCState * env,int version)2798 static void init_proc_e500(CPUPPCState *env, int version)
2799 {
2800 uint32_t tlbncfg[2];
2801 uint64_t ivor_mask;
2802 uint64_t ivpr_mask = 0xFFFF0000ULL;
2803 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2804 | 0x0020; /* 32 kb */
2805 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2806 | 0x0020; /* 32 kb */
2807 uint32_t mmucfg = 0;
2808 #if !defined(CONFIG_USER_ONLY)
2809 int i;
2810 #endif
2811
2812 /*
2813 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2814 * complain when accessing them.
2815 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2816 */
2817 switch (version) {
2818 case fsl_e500v1:
2819 case fsl_e500v2:
2820 default:
2821 ivor_mask = 0x0000000F0000FFFFULL;
2822 break;
2823 case fsl_e500mc:
2824 case fsl_e5500:
2825 ivor_mask = 0x000003FE0000FFFFULL;
2826 break;
2827 case fsl_e6500:
2828 ivor_mask = 0x000003FF0000FFFFULL;
2829 break;
2830 }
2831 register_BookE_sprs(env, ivor_mask);
2832
2833 spr_register(env, SPR_USPRG3, "USPRG3",
2834 &spr_read_ureg, SPR_NOACCESS,
2835 &spr_read_ureg, SPR_NOACCESS,
2836 0x00000000);
2837
2838 /* Processor identification */
2839 spr_register(env, SPR_BOOKE_PIR, "PIR",
2840 SPR_NOACCESS, SPR_NOACCESS,
2841 &spr_read_generic, &spr_write_pir,
2842 0x00000000);
2843
2844 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2845 &spr_read_spefscr, &spr_write_spefscr,
2846 &spr_read_spefscr, &spr_write_spefscr,
2847 0x00000000);
2848 #if !defined(CONFIG_USER_ONLY)
2849 /* Memory management */
2850 env->nb_pids = 3;
2851 env->nb_ways = 2;
2852 switch (version) {
2853 case fsl_e500v1:
2854 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2855 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2856 break;
2857 case fsl_e500v2:
2858 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2859 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2860 break;
2861 case fsl_e500mc:
2862 case fsl_e5500:
2863 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2864 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2865 break;
2866 case fsl_e6500:
2867 mmucfg = 0x6510B45;
2868 env->nb_pids = 1;
2869 tlbncfg[0] = 0x08052400;
2870 tlbncfg[1] = 0x40028040;
2871 break;
2872 default:
2873 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2874 env->spr[SPR_PVR]);
2875 }
2876 #endif
2877 /* Cache sizes */
2878 switch (version) {
2879 case fsl_e500v1:
2880 case fsl_e500v2:
2881 env->dcache_line_size = 32;
2882 env->icache_line_size = 32;
2883 break;
2884 case fsl_e500mc:
2885 case fsl_e5500:
2886 env->dcache_line_size = 64;
2887 env->icache_line_size = 64;
2888 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2889 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2890 break;
2891 case fsl_e6500:
2892 env->dcache_line_size = 32;
2893 env->icache_line_size = 32;
2894 l1cfg0 |= 0x0F83820;
2895 l1cfg1 |= 0x0B83820;
2896 break;
2897 default:
2898 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2899 env->spr[SPR_PVR]);
2900 }
2901 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2902 register_usprgh_sprs(env);
2903
2904 if (version != fsl_e500v1) {
2905 /* e500v1 has no support for alternate timebase */
2906 register_atb_sprs(env);
2907 }
2908
2909 spr_register(env, SPR_HID0, "HID0",
2910 SPR_NOACCESS, SPR_NOACCESS,
2911 &spr_read_generic, &spr_write_generic,
2912 0x00000000);
2913
2914 spr_register(env, SPR_HID1, "HID1",
2915 SPR_NOACCESS, SPR_NOACCESS,
2916 &spr_read_generic, &spr_write_generic,
2917 0x00000000);
2918
2919 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2920 SPR_NOACCESS, SPR_NOACCESS,
2921 &spr_read_generic, &spr_write_generic,
2922 0x00000000);
2923
2924 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2925 SPR_NOACCESS, SPR_NOACCESS,
2926 &spr_read_generic, &spr_write_generic,
2927 0x00000000);
2928
2929 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2930 SPR_NOACCESS, SPR_NOACCESS,
2931 &spr_read_generic, &spr_write_generic,
2932 0x00000000);
2933
2934 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2935 SPR_NOACCESS, SPR_NOACCESS,
2936 &spr_read_generic, &spr_write_generic,
2937 0x00000000);
2938
2939 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2940 SPR_NOACCESS, SPR_NOACCESS,
2941 &spr_read_generic, &spr_write_generic,
2942 0x00000000);
2943
2944 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2945 SPR_NOACCESS, SPR_NOACCESS,
2946 &spr_read_generic, &spr_write_generic,
2947 0x00000000);
2948
2949 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2950 &spr_read_generic, SPR_NOACCESS,
2951 &spr_read_generic, SPR_NOACCESS,
2952 l1cfg0);
2953 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2954 &spr_read_generic, SPR_NOACCESS,
2955 &spr_read_generic, SPR_NOACCESS,
2956 l1cfg1);
2957 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2958 SPR_NOACCESS, SPR_NOACCESS,
2959 &spr_read_generic, &spr_write_e500_l1csr0,
2960 0x00000000);
2961 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2962 SPR_NOACCESS, SPR_NOACCESS,
2963 &spr_read_generic, &spr_write_e500_l1csr1,
2964 0x00000000);
2965 if (version != fsl_e500v1 && version != fsl_e500v2) {
2966 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2967 SPR_NOACCESS, SPR_NOACCESS,
2968 &spr_read_generic, &spr_write_e500_l2csr0,
2969 0x00000000);
2970 }
2971 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2972 SPR_NOACCESS, SPR_NOACCESS,
2973 &spr_read_generic, &spr_write_generic,
2974 0x00000000);
2975 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2976 SPR_NOACCESS, SPR_NOACCESS,
2977 &spr_read_generic, &spr_write_generic,
2978 0x00000000);
2979 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2980 SPR_NOACCESS, SPR_NOACCESS,
2981 &spr_read_generic, &spr_write_booke206_mmucsr0,
2982 0x00000000);
2983 spr_register(env, SPR_BOOKE_EPR, "EPR",
2984 SPR_NOACCESS, SPR_NOACCESS,
2985 &spr_read_generic, SPR_NOACCESS,
2986 0x00000000);
2987 /* XXX better abstract into Emb.xxx features */
2988 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2989 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2990 SPR_NOACCESS, SPR_NOACCESS,
2991 &spr_read_generic, &spr_write_generic,
2992 0x00000000);
2993 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2994 SPR_NOACCESS, SPR_NOACCESS,
2995 &spr_read_mas73, &spr_write_mas73,
2996 0x00000000);
2997 ivpr_mask = (target_ulong)~0xFFFFULL;
2998 }
2999
3000 if (version == fsl_e6500) {
3001 /* Thread identification */
3002 spr_register(env, SPR_TIR, "TIR",
3003 SPR_NOACCESS, SPR_NOACCESS,
3004 &spr_read_generic, SPR_NOACCESS,
3005 0x00000000);
3006 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3007 SPR_NOACCESS, SPR_NOACCESS,
3008 &spr_read_generic, SPR_NOACCESS,
3009 0x00000004);
3010 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3011 SPR_NOACCESS, SPR_NOACCESS,
3012 &spr_read_generic, SPR_NOACCESS,
3013 0x7FFFFFFC);
3014 }
3015
3016 #if !defined(CONFIG_USER_ONLY)
3017 env->nb_tlb = 0;
3018 env->tlb_type = TLB_MAS;
3019 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3020 env->nb_tlb += booke206_tlb_size(env, i);
3021 }
3022 #endif
3023
3024 init_excp_e500(env, ivpr_mask);
3025 /* Allocate hardware IRQ controller */
3026 ppce500_irq_init(env_archcpu(env));
3027 }
3028
init_proc_e500v1(CPUPPCState * env)3029 static void init_proc_e500v1(CPUPPCState *env)
3030 {
3031 init_proc_e500(env, fsl_e500v1);
3032 }
3033
POWERPC_FAMILY(e500v1)3034 POWERPC_FAMILY(e500v1)(ObjectClass *oc, const void *data)
3035 {
3036 DeviceClass *dc = DEVICE_CLASS(oc);
3037 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3038
3039 dc->desc = "e500v1 core";
3040 pcc->init_proc = init_proc_e500v1;
3041 pcc->check_pow = check_pow_hid0;
3042 pcc->check_attn = check_attn_none;
3043 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3044 PPC_SPE | PPC_SPE_SINGLE |
3045 PPC_WRTEE | PPC_RFDI |
3046 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3047 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3048 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3049 pcc->insns_flags2 = PPC2_BOOKE206;
3050 pcc->msr_mask = (1ull << MSR_UCLE) |
3051 (1ull << MSR_SPE) |
3052 (1ull << MSR_POW) |
3053 (1ull << MSR_CE) |
3054 (1ull << MSR_EE) |
3055 (1ull << MSR_PR) |
3056 (1ull << MSR_FP) |
3057 (1ull << MSR_ME) |
3058 (1ull << MSR_FE0) |
3059 (1ull << MSR_DWE) |
3060 (1ull << MSR_DE) |
3061 (1ull << MSR_FE1) |
3062 (1ull << MSR_IR) |
3063 (1ull << MSR_DR);
3064 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3065 pcc->excp_model = POWERPC_EXCP_BOOKE;
3066 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3067 pcc->bfd_mach = bfd_mach_ppc_860;
3068 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3069 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3070 POWERPC_FLAG_BUS_CLK;
3071 }
3072
init_proc_e500v2(CPUPPCState * env)3073 static void init_proc_e500v2(CPUPPCState *env)
3074 {
3075 init_proc_e500(env, fsl_e500v2);
3076 }
3077
POWERPC_FAMILY(e500v2)3078 POWERPC_FAMILY(e500v2)(ObjectClass *oc, const void *data)
3079 {
3080 DeviceClass *dc = DEVICE_CLASS(oc);
3081 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3082
3083 dc->desc = "e500v2 core";
3084 pcc->init_proc = init_proc_e500v2;
3085 pcc->check_pow = check_pow_hid0;
3086 pcc->check_attn = check_attn_none;
3087 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3088 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3089 PPC_WRTEE | PPC_RFDI |
3090 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3091 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3092 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3093 pcc->insns_flags2 = PPC2_BOOKE206;
3094 pcc->msr_mask = (1ull << MSR_UCLE) |
3095 (1ull << MSR_SPE) |
3096 (1ull << MSR_POW) |
3097 (1ull << MSR_CE) |
3098 (1ull << MSR_EE) |
3099 (1ull << MSR_PR) |
3100 (1ull << MSR_FP) |
3101 (1ull << MSR_ME) |
3102 (1ull << MSR_FE0) |
3103 (1ull << MSR_DWE) |
3104 (1ull << MSR_DE) |
3105 (1ull << MSR_FE1) |
3106 (1ull << MSR_IR) |
3107 (1ull << MSR_DR);
3108 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3109 pcc->excp_model = POWERPC_EXCP_BOOKE;
3110 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3111 pcc->bfd_mach = bfd_mach_ppc_860;
3112 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3113 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3114 POWERPC_FLAG_BUS_CLK;
3115 }
3116
init_proc_e500mc(CPUPPCState * env)3117 static void init_proc_e500mc(CPUPPCState *env)
3118 {
3119 init_proc_e500(env, fsl_e500mc);
3120 }
3121
POWERPC_FAMILY(e500mc)3122 POWERPC_FAMILY(e500mc)(ObjectClass *oc, const void *data)
3123 {
3124 DeviceClass *dc = DEVICE_CLASS(oc);
3125 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3126
3127 dc->desc = "e500mc core";
3128 pcc->init_proc = init_proc_e500mc;
3129 pcc->check_pow = check_pow_none;
3130 pcc->check_attn = check_attn_none;
3131 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3132 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3133 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3134 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3135 PPC_FLOAT | PPC_FLOAT_FRES |
3136 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3137 PPC_FLOAT_STFIWX | PPC_WAIT |
3138 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3139 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3140 pcc->msr_mask = (1ull << MSR_GS) |
3141 (1ull << MSR_UCLE) |
3142 (1ull << MSR_CE) |
3143 (1ull << MSR_EE) |
3144 (1ull << MSR_PR) |
3145 (1ull << MSR_FP) |
3146 (1ull << MSR_ME) |
3147 (1ull << MSR_FE0) |
3148 (1ull << MSR_DE) |
3149 (1ull << MSR_FE1) |
3150 (1ull << MSR_IR) |
3151 (1ull << MSR_DR) |
3152 (1ull << MSR_PX) |
3153 (1ull << MSR_RI);
3154 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3155 pcc->excp_model = POWERPC_EXCP_BOOKE;
3156 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3157 /* FIXME: figure out the correct flag for e500mc */
3158 pcc->bfd_mach = bfd_mach_ppc_e500;
3159 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3160 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3161 }
3162
3163 #ifdef TARGET_PPC64
init_proc_e5500(CPUPPCState * env)3164 static void init_proc_e5500(CPUPPCState *env)
3165 {
3166 init_proc_e500(env, fsl_e5500);
3167 }
3168
POWERPC_FAMILY(e5500)3169 POWERPC_FAMILY(e5500)(ObjectClass *oc, const void *data)
3170 {
3171 DeviceClass *dc = DEVICE_CLASS(oc);
3172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3173
3174 dc->desc = "e5500 core";
3175 pcc->init_proc = init_proc_e5500;
3176 pcc->check_pow = check_pow_none;
3177 pcc->check_attn = check_attn_none;
3178 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3179 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3180 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3181 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3182 PPC_FLOAT | PPC_FLOAT_FRES |
3183 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3184 PPC_FLOAT_STFIWX | PPC_WAIT |
3185 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3186 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3187 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3188 PPC2_FP_CVT_S64;
3189 pcc->msr_mask = (1ull << MSR_CM) |
3190 (1ull << MSR_GS) |
3191 (1ull << MSR_UCLE) |
3192 (1ull << MSR_CE) |
3193 (1ull << MSR_EE) |
3194 (1ull << MSR_PR) |
3195 (1ull << MSR_FP) |
3196 (1ull << MSR_ME) |
3197 (1ull << MSR_FE0) |
3198 (1ull << MSR_DE) |
3199 (1ull << MSR_FE1) |
3200 (1ull << MSR_IR) |
3201 (1ull << MSR_DR) |
3202 (1ull << MSR_PX) |
3203 (1ull << MSR_RI);
3204 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3205 pcc->excp_model = POWERPC_EXCP_BOOKE;
3206 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3207 /* FIXME: figure out the correct flag for e5500 */
3208 pcc->bfd_mach = bfd_mach_ppc_e500;
3209 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3210 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3211 }
3212
init_proc_e6500(CPUPPCState * env)3213 static void init_proc_e6500(CPUPPCState *env)
3214 {
3215 init_proc_e500(env, fsl_e6500);
3216 }
3217
POWERPC_FAMILY(e6500)3218 POWERPC_FAMILY(e6500)(ObjectClass *oc, const void *data)
3219 {
3220 DeviceClass *dc = DEVICE_CLASS(oc);
3221 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3222
3223 dc->desc = "e6500 core";
3224 pcc->init_proc = init_proc_e6500;
3225 pcc->check_pow = check_pow_none;
3226 pcc->check_attn = check_attn_none;
3227 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3228 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3229 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3230 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3231 PPC_FLOAT | PPC_FLOAT_FRES |
3232 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3233 PPC_FLOAT_STFIWX | PPC_WAIT |
3234 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3235 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3236 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3237 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3238 pcc->msr_mask = (1ull << MSR_CM) |
3239 (1ull << MSR_GS) |
3240 (1ull << MSR_UCLE) |
3241 (1ull << MSR_CE) |
3242 (1ull << MSR_EE) |
3243 (1ull << MSR_PR) |
3244 (1ull << MSR_FP) |
3245 (1ull << MSR_ME) |
3246 (1ull << MSR_FE0) |
3247 (1ull << MSR_DE) |
3248 (1ull << MSR_FE1) |
3249 (1ull << MSR_IS) |
3250 (1ull << MSR_DS) |
3251 (1ull << MSR_PX) |
3252 (1ull << MSR_RI) |
3253 (1ull << MSR_VR);
3254 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3255 pcc->excp_model = POWERPC_EXCP_BOOKE;
3256 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3257 pcc->bfd_mach = bfd_mach_ppc_e500;
3258 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3259 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3260 }
3261
3262 #endif
3263
3264 /* Non-embedded PowerPC */
init_proc_603(CPUPPCState * env)3265 static void init_proc_603(CPUPPCState *env)
3266 {
3267 register_non_embedded_sprs(env);
3268 register_sdr1_sprs(env);
3269 register_603_sprs(env);
3270
3271 /* Memory management */
3272 register_low_BATs(env);
3273 register_6xx_7xx_soft_tlb(env, 64, 2);
3274 init_excp_603(env);
3275 env->dcache_line_size = 32;
3276 env->icache_line_size = 32;
3277 /* Allocate hardware IRQ controller */
3278 ppc6xx_irq_init(env_archcpu(env));
3279 }
3280
3281 POWERPC_FAMILY(603)(ObjectClass *oc, const void *data)
3282 {
3283 DeviceClass *dc = DEVICE_CLASS(oc);
3284 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3285
3286 dc->desc = "PowerPC 603";
3287 pcc->init_proc = init_proc_603;
3288 pcc->check_pow = check_pow_hid0;
3289 pcc->check_attn = check_attn_none;
3290 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3291 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3292 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3293 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3294 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3295 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3296 PPC_SEGMENT | PPC_EXTERN;
3297 pcc->msr_mask = (1ull << MSR_POW) |
3298 (1ull << MSR_TGPR) |
3299 (1ull << MSR_ILE) |
3300 (1ull << MSR_EE) |
3301 (1ull << MSR_PR) |
3302 (1ull << MSR_FP) |
3303 (1ull << MSR_ME) |
3304 (1ull << MSR_FE0) |
3305 (1ull << MSR_SE) |
3306 (1ull << MSR_DE) |
3307 (1ull << MSR_FE1) |
3308 (1ull << MSR_EP) |
3309 (1ull << MSR_IR) |
3310 (1ull << MSR_DR) |
3311 (1ull << MSR_RI) |
3312 (1ull << MSR_LE);
3313 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3314 pcc->excp_model = POWERPC_EXCP_6xx;
3315 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3316 pcc->bfd_mach = bfd_mach_ppc_603;
3317 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3318 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3319 }
3320
3321 POWERPC_FAMILY(603E)(ObjectClass *oc, const void *data)
3322 {
3323 DeviceClass *dc = DEVICE_CLASS(oc);
3324 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3325
3326 dc->desc = "PowerPC 603e";
3327 pcc->init_proc = init_proc_603;
3328 pcc->check_pow = check_pow_hid0;
3329 pcc->check_attn = check_attn_none;
3330 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3331 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3332 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3333 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3334 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3335 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3336 PPC_SEGMENT | PPC_EXTERN;
3337 pcc->msr_mask = (1ull << MSR_POW) |
3338 (1ull << MSR_TGPR) |
3339 (1ull << MSR_ILE) |
3340 (1ull << MSR_EE) |
3341 (1ull << MSR_PR) |
3342 (1ull << MSR_FP) |
3343 (1ull << MSR_ME) |
3344 (1ull << MSR_FE0) |
3345 (1ull << MSR_SE) |
3346 (1ull << MSR_DE) |
3347 (1ull << MSR_FE1) |
3348 (1ull << MSR_EP) |
3349 (1ull << MSR_IR) |
3350 (1ull << MSR_DR) |
3351 (1ull << MSR_RI) |
3352 (1ull << MSR_LE);
3353 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3354 pcc->excp_model = POWERPC_EXCP_6xx;
3355 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3356 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3357 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3358 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3359 }
3360
init_proc_e300(CPUPPCState * env)3361 static void init_proc_e300(CPUPPCState *env)
3362 {
3363 init_proc_603(env);
3364 register_e300_sprs(env);
3365 }
3366
POWERPC_FAMILY(e300)3367 POWERPC_FAMILY(e300)(ObjectClass *oc, const void *data)
3368 {
3369 DeviceClass *dc = DEVICE_CLASS(oc);
3370 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3371
3372 dc->desc = "e300 core";
3373 pcc->init_proc = init_proc_e300;
3374 pcc->check_pow = check_pow_hid0;
3375 pcc->check_attn = check_attn_none;
3376 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3377 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3378 PPC_FLOAT_STFIWX |
3379 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3380 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3381 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3382 PPC_SEGMENT | PPC_EXTERN;
3383 pcc->msr_mask = (1ull << MSR_POW) |
3384 (1ull << MSR_TGPR) |
3385 (1ull << MSR_ILE) |
3386 (1ull << MSR_EE) |
3387 (1ull << MSR_PR) |
3388 (1ull << MSR_FP) |
3389 (1ull << MSR_ME) |
3390 (1ull << MSR_FE0) |
3391 (1ull << MSR_SE) |
3392 (1ull << MSR_DE) |
3393 (1ull << MSR_FE1) |
3394 (1ull << MSR_AL) |
3395 (1ull << MSR_EP) |
3396 (1ull << MSR_IR) |
3397 (1ull << MSR_DR) |
3398 (1ull << MSR_RI) |
3399 (1ull << MSR_LE);
3400 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3401 pcc->excp_model = POWERPC_EXCP_6xx;
3402 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3403 pcc->bfd_mach = bfd_mach_ppc_603;
3404 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3405 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3406 }
3407
init_proc_604(CPUPPCState * env)3408 static void init_proc_604(CPUPPCState *env)
3409 {
3410 register_non_embedded_sprs(env);
3411 register_sdr1_sprs(env);
3412 register_604_sprs(env);
3413
3414 /* Memory management */
3415 register_low_BATs(env);
3416 init_excp_604(env);
3417 env->dcache_line_size = 32;
3418 env->icache_line_size = 32;
3419 /* Allocate hardware IRQ controller */
3420 ppc6xx_irq_init(env_archcpu(env));
3421 }
3422
3423 POWERPC_FAMILY(604)(ObjectClass *oc, const void *data)
3424 {
3425 DeviceClass *dc = DEVICE_CLASS(oc);
3426 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3427
3428 dc->desc = "PowerPC 604";
3429 pcc->init_proc = init_proc_604;
3430 pcc->check_pow = check_pow_nocheck;
3431 pcc->check_attn = check_attn_none;
3432 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3433 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3434 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3435 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3436 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3437 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3438 PPC_SEGMENT | PPC_EXTERN;
3439 pcc->msr_mask = (1ull << MSR_POW) |
3440 (1ull << MSR_ILE) |
3441 (1ull << MSR_EE) |
3442 (1ull << MSR_PR) |
3443 (1ull << MSR_FP) |
3444 (1ull << MSR_ME) |
3445 (1ull << MSR_FE0) |
3446 (1ull << MSR_SE) |
3447 (1ull << MSR_DE) |
3448 (1ull << MSR_FE1) |
3449 (1ull << MSR_EP) |
3450 (1ull << MSR_IR) |
3451 (1ull << MSR_DR) |
3452 (1ull << MSR_PMM) |
3453 (1ull << MSR_RI) |
3454 (1ull << MSR_LE);
3455 pcc->mmu_model = POWERPC_MMU_32B;
3456 pcc->excp_model = POWERPC_EXCP_6xx;
3457 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3458 pcc->bfd_mach = bfd_mach_ppc_604;
3459 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3460 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3461 }
3462
init_proc_604E(CPUPPCState * env)3463 static void init_proc_604E(CPUPPCState *env)
3464 {
3465 init_proc_604(env);
3466 register_604e_sprs(env);
3467 }
3468
3469 POWERPC_FAMILY(604E)(ObjectClass *oc, const void *data)
3470 {
3471 DeviceClass *dc = DEVICE_CLASS(oc);
3472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3473
3474 dc->desc = "PowerPC 604E";
3475 pcc->init_proc = init_proc_604E;
3476 pcc->check_pow = check_pow_nocheck;
3477 pcc->check_attn = check_attn_none;
3478 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3479 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3480 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3481 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3482 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3483 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3484 PPC_SEGMENT | PPC_EXTERN;
3485 pcc->msr_mask = (1ull << MSR_POW) |
3486 (1ull << MSR_ILE) |
3487 (1ull << MSR_EE) |
3488 (1ull << MSR_PR) |
3489 (1ull << MSR_FP) |
3490 (1ull << MSR_ME) |
3491 (1ull << MSR_FE0) |
3492 (1ull << MSR_SE) |
3493 (1ull << MSR_DE) |
3494 (1ull << MSR_FE1) |
3495 (1ull << MSR_EP) |
3496 (1ull << MSR_IR) |
3497 (1ull << MSR_DR) |
3498 (1ull << MSR_PMM) |
3499 (1ull << MSR_RI) |
3500 (1ull << MSR_LE);
3501 pcc->mmu_model = POWERPC_MMU_32B;
3502 pcc->excp_model = POWERPC_EXCP_6xx;
3503 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3504 pcc->bfd_mach = bfd_mach_ppc_604;
3505 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3506 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3507 }
3508
init_proc_740(CPUPPCState * env)3509 static void init_proc_740(CPUPPCState *env)
3510 {
3511 register_non_embedded_sprs(env);
3512 register_sdr1_sprs(env);
3513 register_7xx_sprs(env);
3514 /* Thermal management */
3515 register_thrm_sprs(env);
3516
3517 /* Memory management */
3518 register_low_BATs(env);
3519 init_excp_7x0(env);
3520 env->dcache_line_size = 32;
3521 env->icache_line_size = 32;
3522 /* Allocate hardware IRQ controller */
3523 ppc6xx_irq_init(env_archcpu(env));
3524 }
3525
3526 POWERPC_FAMILY(740)(ObjectClass *oc, const void *data)
3527 {
3528 DeviceClass *dc = DEVICE_CLASS(oc);
3529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3530
3531 dc->desc = "PowerPC 740";
3532 pcc->init_proc = init_proc_740;
3533 pcc->check_pow = check_pow_hid0;
3534 pcc->check_attn = check_attn_none;
3535 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3536 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3537 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3538 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3539 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3540 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3541 PPC_SEGMENT | PPC_EXTERN;
3542 pcc->msr_mask = (1ull << MSR_POW) |
3543 (1ull << MSR_ILE) |
3544 (1ull << MSR_EE) |
3545 (1ull << MSR_PR) |
3546 (1ull << MSR_FP) |
3547 (1ull << MSR_ME) |
3548 (1ull << MSR_FE0) |
3549 (1ull << MSR_SE) |
3550 (1ull << MSR_DE) |
3551 (1ull << MSR_FE1) |
3552 (1ull << MSR_EP) |
3553 (1ull << MSR_IR) |
3554 (1ull << MSR_DR) |
3555 (1ull << MSR_PMM) |
3556 (1ull << MSR_RI) |
3557 (1ull << MSR_LE);
3558 pcc->mmu_model = POWERPC_MMU_32B;
3559 pcc->excp_model = POWERPC_EXCP_7xx;
3560 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3561 pcc->bfd_mach = bfd_mach_ppc_750;
3562 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3563 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3564 }
3565
init_proc_750(CPUPPCState * env)3566 static void init_proc_750(CPUPPCState *env)
3567 {
3568 register_non_embedded_sprs(env);
3569 register_sdr1_sprs(env);
3570 register_7xx_sprs(env);
3571
3572 spr_register(env, SPR_L2CR, "L2CR",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, spr_access_nop,
3575 0x00000000);
3576 /* Thermal management */
3577 register_thrm_sprs(env);
3578
3579 /* Memory management */
3580 register_low_BATs(env);
3581 /*
3582 * XXX: high BATs are also present but are known to be bugged on
3583 * die version 1.x
3584 */
3585 init_excp_7x0(env);
3586 env->dcache_line_size = 32;
3587 env->icache_line_size = 32;
3588 /* Allocate hardware IRQ controller */
3589 ppc6xx_irq_init(env_archcpu(env));
3590 }
3591
3592 POWERPC_FAMILY(750)(ObjectClass *oc, const void *data)
3593 {
3594 DeviceClass *dc = DEVICE_CLASS(oc);
3595 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3596
3597 dc->desc = "PowerPC 750";
3598 pcc->init_proc = init_proc_750;
3599 pcc->check_pow = check_pow_hid0;
3600 pcc->check_attn = check_attn_none;
3601 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3602 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3603 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3604 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3605 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3606 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3607 PPC_SEGMENT | PPC_EXTERN;
3608 pcc->msr_mask = (1ull << MSR_POW) |
3609 (1ull << MSR_ILE) |
3610 (1ull << MSR_EE) |
3611 (1ull << MSR_PR) |
3612 (1ull << MSR_FP) |
3613 (1ull << MSR_ME) |
3614 (1ull << MSR_FE0) |
3615 (1ull << MSR_SE) |
3616 (1ull << MSR_DE) |
3617 (1ull << MSR_FE1) |
3618 (1ull << MSR_EP) |
3619 (1ull << MSR_IR) |
3620 (1ull << MSR_DR) |
3621 (1ull << MSR_PMM) |
3622 (1ull << MSR_RI) |
3623 (1ull << MSR_LE);
3624 pcc->mmu_model = POWERPC_MMU_32B;
3625 pcc->excp_model = POWERPC_EXCP_7xx;
3626 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3627 pcc->bfd_mach = bfd_mach_ppc_750;
3628 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3629 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3630 }
3631
init_proc_750cl(CPUPPCState * env)3632 static void init_proc_750cl(CPUPPCState *env)
3633 {
3634 register_non_embedded_sprs(env);
3635 register_sdr1_sprs(env);
3636 register_7xx_sprs(env);
3637
3638 spr_register(env, SPR_L2CR, "L2CR",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, spr_access_nop,
3641 0x00000000);
3642 /* Thermal management */
3643 /* Those registers are fake on 750CL */
3644 spr_register(env, SPR_THRM1, "THRM1",
3645 SPR_NOACCESS, SPR_NOACCESS,
3646 &spr_read_generic, &spr_write_generic,
3647 0x00000000);
3648 spr_register(env, SPR_THRM2, "THRM2",
3649 SPR_NOACCESS, SPR_NOACCESS,
3650 &spr_read_generic, &spr_write_generic,
3651 0x00000000);
3652 spr_register(env, SPR_THRM3, "THRM3",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656
3657 spr_register(env, SPR_750_TDCL, "TDCL",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 spr_register(env, SPR_750_TDCH, "TDCH",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* DMA */
3666 spr_register(env, SPR_750_WPAR, "WPAR",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 spr_register(env, SPR_750_DMAL, "DMAL",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674 spr_register(env, SPR_750_DMAU, "DMAU",
3675 SPR_NOACCESS, SPR_NOACCESS,
3676 &spr_read_generic, &spr_write_generic,
3677 0x00000000);
3678 /* Hardware implementation registers */
3679 spr_register(env, SPR_750CL_HID2, "HID2",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683
3684 spr_register(env, SPR_750CL_HID4, "HID4",
3685 SPR_NOACCESS, SPR_NOACCESS,
3686 &spr_read_generic, &spr_write_generic,
3687 0x00000000);
3688 /* Quantization registers */
3689 spr_register(env, SPR_750_GQR0, "GQR0",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693
3694 spr_register(env, SPR_750_GQR1, "GQR1",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3697 0x00000000);
3698
3699 spr_register(env, SPR_750_GQR2, "GQR2",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_generic,
3702 0x00000000);
3703
3704 spr_register(env, SPR_750_GQR3, "GQR3",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_generic,
3707 0x00000000);
3708
3709 spr_register(env, SPR_750_GQR4, "GQR4",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713
3714 spr_register(env, SPR_750_GQR5, "GQR5",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718
3719 spr_register(env, SPR_750_GQR6, "GQR6",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723
3724 spr_register(env, SPR_750_GQR7, "GQR7",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* Memory management */
3729 register_low_BATs(env);
3730 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3731 register_high_BATs(env);
3732 init_excp_750cl(env);
3733 env->dcache_line_size = 32;
3734 env->icache_line_size = 32;
3735 /* Allocate hardware IRQ controller */
3736 ppc6xx_irq_init(env_archcpu(env));
3737 }
3738
3739 POWERPC_FAMILY(750cl)(ObjectClass *oc, const void *data)
3740 {
3741 DeviceClass *dc = DEVICE_CLASS(oc);
3742 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3743
3744 dc->desc = "PowerPC 750 CL";
3745 pcc->init_proc = init_proc_750cl;
3746 pcc->check_pow = check_pow_hid0;
3747 pcc->check_attn = check_attn_none;
3748 /*
3749 * XXX: not implemented:
3750 * cache lock instructions:
3751 * dcbz_l
3752 * floating point paired instructions
3753 * psq_lux
3754 * psq_lx
3755 * psq_stux
3756 * psq_stx
3757 * ps_abs
3758 * ps_add
3759 * ps_cmpo0
3760 * ps_cmpo1
3761 * ps_cmpu0
3762 * ps_cmpu1
3763 * ps_div
3764 * ps_madd
3765 * ps_madds0
3766 * ps_madds1
3767 * ps_merge00
3768 * ps_merge01
3769 * ps_merge10
3770 * ps_merge11
3771 * ps_mr
3772 * ps_msub
3773 * ps_mul
3774 * ps_muls0
3775 * ps_muls1
3776 * ps_nabs
3777 * ps_neg
3778 * ps_nmadd
3779 * ps_nmsub
3780 * ps_res
3781 * ps_rsqrte
3782 * ps_sel
3783 * ps_sub
3784 * ps_sum0
3785 * ps_sum1
3786 */
3787 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3788 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3789 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3790 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3791 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3792 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3793 PPC_SEGMENT | PPC_EXTERN;
3794 pcc->msr_mask = (1ull << MSR_POW) |
3795 (1ull << MSR_ILE) |
3796 (1ull << MSR_EE) |
3797 (1ull << MSR_PR) |
3798 (1ull << MSR_FP) |
3799 (1ull << MSR_ME) |
3800 (1ull << MSR_FE0) |
3801 (1ull << MSR_SE) |
3802 (1ull << MSR_DE) |
3803 (1ull << MSR_FE1) |
3804 (1ull << MSR_EP) |
3805 (1ull << MSR_IR) |
3806 (1ull << MSR_DR) |
3807 (1ull << MSR_PMM) |
3808 (1ull << MSR_RI) |
3809 (1ull << MSR_LE);
3810 pcc->mmu_model = POWERPC_MMU_32B;
3811 pcc->excp_model = POWERPC_EXCP_7xx;
3812 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3813 pcc->bfd_mach = bfd_mach_ppc_750;
3814 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3815 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3816 }
3817
init_proc_750cx(CPUPPCState * env)3818 static void init_proc_750cx(CPUPPCState *env)
3819 {
3820 register_non_embedded_sprs(env);
3821 register_sdr1_sprs(env);
3822 register_7xx_sprs(env);
3823
3824 spr_register(env, SPR_L2CR, "L2CR",
3825 SPR_NOACCESS, SPR_NOACCESS,
3826 &spr_read_generic, spr_access_nop,
3827 0x00000000);
3828 /* Thermal management */
3829 register_thrm_sprs(env);
3830
3831 spr_register(env, SPR_SDA, "SDA",
3832 SPR_NOACCESS, SPR_NOACCESS,
3833 &spr_read_generic, &spr_write_generic,
3834 0x00000000);
3835
3836 /* Memory management */
3837 register_low_BATs(env);
3838 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3839 register_high_BATs(env);
3840 init_excp_750cx(env);
3841 env->dcache_line_size = 32;
3842 env->icache_line_size = 32;
3843 /* Allocate hardware IRQ controller */
3844 ppc6xx_irq_init(env_archcpu(env));
3845 }
3846
3847 POWERPC_FAMILY(750cx)(ObjectClass *oc, const void *data)
3848 {
3849 DeviceClass *dc = DEVICE_CLASS(oc);
3850 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3851
3852 dc->desc = "PowerPC 750CX";
3853 pcc->init_proc = init_proc_750cx;
3854 pcc->check_pow = check_pow_hid0;
3855 pcc->check_attn = check_attn_none;
3856 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3857 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3858 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3859 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3860 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3861 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3862 PPC_SEGMENT | PPC_EXTERN;
3863 pcc->msr_mask = (1ull << MSR_POW) |
3864 (1ull << MSR_ILE) |
3865 (1ull << MSR_EE) |
3866 (1ull << MSR_PR) |
3867 (1ull << MSR_FP) |
3868 (1ull << MSR_ME) |
3869 (1ull << MSR_FE0) |
3870 (1ull << MSR_SE) |
3871 (1ull << MSR_DE) |
3872 (1ull << MSR_FE1) |
3873 (1ull << MSR_EP) |
3874 (1ull << MSR_IR) |
3875 (1ull << MSR_DR) |
3876 (1ull << MSR_PMM) |
3877 (1ull << MSR_RI) |
3878 (1ull << MSR_LE);
3879 pcc->mmu_model = POWERPC_MMU_32B;
3880 pcc->excp_model = POWERPC_EXCP_7xx;
3881 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3882 pcc->bfd_mach = bfd_mach_ppc_750;
3883 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3884 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3885 }
3886
init_proc_750fx(CPUPPCState * env)3887 static void init_proc_750fx(CPUPPCState *env)
3888 {
3889 register_non_embedded_sprs(env);
3890 register_sdr1_sprs(env);
3891 register_7xx_sprs(env);
3892
3893 spr_register(env, SPR_L2CR, "L2CR",
3894 SPR_NOACCESS, SPR_NOACCESS,
3895 &spr_read_generic, spr_access_nop,
3896 0x00000000);
3897 /* Thermal management */
3898 register_thrm_sprs(env);
3899
3900 spr_register(env, SPR_750_THRM4, "THRM4",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* Hardware implementation registers */
3905 spr_register(env, SPR_750FX_HID2, "HID2",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* Memory management */
3910 register_low_BATs(env);
3911 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3912 register_high_BATs(env);
3913 init_excp_7x0(env);
3914 env->dcache_line_size = 32;
3915 env->icache_line_size = 32;
3916 /* Allocate hardware IRQ controller */
3917 ppc6xx_irq_init(env_archcpu(env));
3918 }
3919
3920 POWERPC_FAMILY(750fx)(ObjectClass *oc, const void *data)
3921 {
3922 DeviceClass *dc = DEVICE_CLASS(oc);
3923 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3924
3925 dc->desc = "PowerPC 750FX";
3926 pcc->init_proc = init_proc_750fx;
3927 pcc->check_pow = check_pow_hid0;
3928 pcc->check_attn = check_attn_none;
3929 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3930 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3931 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3932 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3933 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3934 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3935 PPC_SEGMENT | PPC_EXTERN;
3936 pcc->msr_mask = (1ull << MSR_POW) |
3937 (1ull << MSR_ILE) |
3938 (1ull << MSR_EE) |
3939 (1ull << MSR_PR) |
3940 (1ull << MSR_FP) |
3941 (1ull << MSR_ME) |
3942 (1ull << MSR_FE0) |
3943 (1ull << MSR_SE) |
3944 (1ull << MSR_DE) |
3945 (1ull << MSR_FE1) |
3946 (1ull << MSR_EP) |
3947 (1ull << MSR_IR) |
3948 (1ull << MSR_DR) |
3949 (1ull << MSR_PMM) |
3950 (1ull << MSR_RI) |
3951 (1ull << MSR_LE);
3952 pcc->mmu_model = POWERPC_MMU_32B;
3953 pcc->excp_model = POWERPC_EXCP_7xx;
3954 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3955 pcc->bfd_mach = bfd_mach_ppc_750;
3956 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3957 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3958 }
3959
init_proc_750gx(CPUPPCState * env)3960 static void init_proc_750gx(CPUPPCState *env)
3961 {
3962 register_non_embedded_sprs(env);
3963 register_sdr1_sprs(env);
3964 register_7xx_sprs(env);
3965
3966 spr_register(env, SPR_L2CR, "L2CR",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, spr_access_nop,
3969 0x00000000);
3970 /* Thermal management */
3971 register_thrm_sprs(env);
3972
3973 spr_register(env, SPR_750_THRM4, "THRM4",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
3977 /* Hardware implementation registers */
3978 spr_register(env, SPR_750FX_HID2, "HID2",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* Memory management */
3983 register_low_BATs(env);
3984 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3985 register_high_BATs(env);
3986 init_excp_7x0(env);
3987 env->dcache_line_size = 32;
3988 env->icache_line_size = 32;
3989 /* Allocate hardware IRQ controller */
3990 ppc6xx_irq_init(env_archcpu(env));
3991 }
3992
3993 POWERPC_FAMILY(750gx)(ObjectClass *oc, const void *data)
3994 {
3995 DeviceClass *dc = DEVICE_CLASS(oc);
3996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3997
3998 dc->desc = "PowerPC 750GX";
3999 pcc->init_proc = init_proc_750gx;
4000 pcc->check_pow = check_pow_hid0;
4001 pcc->check_attn = check_attn_none;
4002 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4003 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4004 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4005 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4006 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4007 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4008 PPC_SEGMENT | PPC_EXTERN;
4009 pcc->msr_mask = (1ull << MSR_POW) |
4010 (1ull << MSR_ILE) |
4011 (1ull << MSR_EE) |
4012 (1ull << MSR_PR) |
4013 (1ull << MSR_FP) |
4014 (1ull << MSR_ME) |
4015 (1ull << MSR_FE0) |
4016 (1ull << MSR_SE) |
4017 (1ull << MSR_DE) |
4018 (1ull << MSR_FE1) |
4019 (1ull << MSR_EP) |
4020 (1ull << MSR_IR) |
4021 (1ull << MSR_DR) |
4022 (1ull << MSR_PMM) |
4023 (1ull << MSR_RI) |
4024 (1ull << MSR_LE);
4025 pcc->mmu_model = POWERPC_MMU_32B;
4026 pcc->excp_model = POWERPC_EXCP_7xx;
4027 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4028 pcc->bfd_mach = bfd_mach_ppc_750;
4029 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4030 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4031 }
4032
init_proc_745(CPUPPCState * env)4033 static void init_proc_745(CPUPPCState *env)
4034 {
4035 register_non_embedded_sprs(env);
4036 register_sdr1_sprs(env);
4037 register_7xx_sprs(env);
4038 register_745_sprs(env);
4039 /* Thermal management */
4040 register_thrm_sprs(env);
4041
4042 /* Memory management */
4043 register_low_BATs(env);
4044 register_high_BATs(env);
4045 register_6xx_7xx_soft_tlb(env, 64, 2);
4046 init_excp_7x5(env);
4047 env->dcache_line_size = 32;
4048 env->icache_line_size = 32;
4049 /* Allocate hardware IRQ controller */
4050 ppc6xx_irq_init(env_archcpu(env));
4051 }
4052
4053 POWERPC_FAMILY(745)(ObjectClass *oc, const void *data)
4054 {
4055 DeviceClass *dc = DEVICE_CLASS(oc);
4056 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4057
4058 dc->desc = "PowerPC 745";
4059 pcc->init_proc = init_proc_745;
4060 pcc->check_pow = check_pow_hid0;
4061 pcc->check_attn = check_attn_none;
4062 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4064 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4066 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4068 PPC_SEGMENT | PPC_EXTERN;
4069 pcc->msr_mask = (1ull << MSR_POW) |
4070 (1ull << MSR_ILE) |
4071 (1ull << MSR_EE) |
4072 (1ull << MSR_PR) |
4073 (1ull << MSR_FP) |
4074 (1ull << MSR_ME) |
4075 (1ull << MSR_FE0) |
4076 (1ull << MSR_SE) |
4077 (1ull << MSR_DE) |
4078 (1ull << MSR_FE1) |
4079 (1ull << MSR_EP) |
4080 (1ull << MSR_IR) |
4081 (1ull << MSR_DR) |
4082 (1ull << MSR_PMM) |
4083 (1ull << MSR_RI) |
4084 (1ull << MSR_LE);
4085 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4086 pcc->excp_model = POWERPC_EXCP_7xx;
4087 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4088 pcc->bfd_mach = bfd_mach_ppc_750;
4089 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4090 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4091 }
4092
init_proc_755(CPUPPCState * env)4093 static void init_proc_755(CPUPPCState *env)
4094 {
4095 init_proc_745(env);
4096 register_755_sprs(env);
4097 }
4098
4099 POWERPC_FAMILY(755)(ObjectClass *oc, const void *data)
4100 {
4101 DeviceClass *dc = DEVICE_CLASS(oc);
4102 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4103
4104 dc->desc = "PowerPC 755";
4105 pcc->init_proc = init_proc_755;
4106 pcc->check_pow = check_pow_hid0;
4107 pcc->check_attn = check_attn_none;
4108 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4109 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4110 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4111 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4112 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4113 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4114 PPC_SEGMENT | PPC_EXTERN;
4115 pcc->msr_mask = (1ull << MSR_POW) |
4116 (1ull << MSR_ILE) |
4117 (1ull << MSR_EE) |
4118 (1ull << MSR_PR) |
4119 (1ull << MSR_FP) |
4120 (1ull << MSR_ME) |
4121 (1ull << MSR_FE0) |
4122 (1ull << MSR_SE) |
4123 (1ull << MSR_DE) |
4124 (1ull << MSR_FE1) |
4125 (1ull << MSR_EP) |
4126 (1ull << MSR_IR) |
4127 (1ull << MSR_DR) |
4128 (1ull << MSR_PMM) |
4129 (1ull << MSR_RI) |
4130 (1ull << MSR_LE);
4131 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4132 pcc->excp_model = POWERPC_EXCP_7xx;
4133 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4134 pcc->bfd_mach = bfd_mach_ppc_750;
4135 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4136 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4137 }
4138
init_proc_7400(CPUPPCState * env)4139 static void init_proc_7400(CPUPPCState *env)
4140 {
4141 register_non_embedded_sprs(env);
4142 register_sdr1_sprs(env);
4143 register_74xx_sprs(env);
4144 vscr_init(env, 0x00010000);
4145
4146 spr_register(env, SPR_UBAMR, "UBAMR",
4147 &spr_read_ureg, SPR_NOACCESS,
4148 &spr_read_ureg, SPR_NOACCESS,
4149 0x00000000);
4150
4151 spr_register(env, SPR_MSSCR1, "MSSCR1",
4152 SPR_NOACCESS, SPR_NOACCESS,
4153 &spr_read_generic, &spr_write_generic,
4154 0x00000000);
4155 /* Thermal management */
4156 register_thrm_sprs(env);
4157 /* Memory management */
4158 register_low_BATs(env);
4159 init_excp_7400(env);
4160 env->dcache_line_size = 32;
4161 env->icache_line_size = 32;
4162 /* Allocate hardware IRQ controller */
4163 ppc6xx_irq_init(env_archcpu(env));
4164 }
4165
4166 POWERPC_FAMILY(7400)(ObjectClass *oc, const void *data)
4167 {
4168 DeviceClass *dc = DEVICE_CLASS(oc);
4169 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4170
4171 dc->desc = "PowerPC 7400 (aka G4)";
4172 pcc->init_proc = init_proc_7400;
4173 pcc->check_pow = check_pow_hid0;
4174 pcc->check_attn = check_attn_none;
4175 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4176 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4177 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4178 PPC_FLOAT_STFIWX |
4179 PPC_CACHE | PPC_CACHE_ICBI |
4180 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4181 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4182 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4183 PPC_MEM_TLBIA |
4184 PPC_SEGMENT | PPC_EXTERN |
4185 PPC_ALTIVEC;
4186 pcc->msr_mask = (1ull << MSR_VR) |
4187 (1ull << MSR_POW) |
4188 (1ull << MSR_ILE) |
4189 (1ull << MSR_EE) |
4190 (1ull << MSR_PR) |
4191 (1ull << MSR_FP) |
4192 (1ull << MSR_ME) |
4193 (1ull << MSR_FE0) |
4194 (1ull << MSR_SE) |
4195 (1ull << MSR_DE) |
4196 (1ull << MSR_FE1) |
4197 (1ull << MSR_EP) |
4198 (1ull << MSR_IR) |
4199 (1ull << MSR_DR) |
4200 (1ull << MSR_PMM) |
4201 (1ull << MSR_RI) |
4202 (1ull << MSR_LE);
4203 pcc->mmu_model = POWERPC_MMU_32B;
4204 pcc->excp_model = POWERPC_EXCP_74xx;
4205 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4206 pcc->bfd_mach = bfd_mach_ppc_7400;
4207 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4208 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4209 POWERPC_FLAG_BUS_CLK;
4210 }
4211
init_proc_7410(CPUPPCState * env)4212 static void init_proc_7410(CPUPPCState *env)
4213 {
4214 register_non_embedded_sprs(env);
4215 register_sdr1_sprs(env);
4216 register_74xx_sprs(env);
4217 vscr_init(env, 0x00010000);
4218
4219 spr_register(env, SPR_UBAMR, "UBAMR",
4220 &spr_read_ureg, SPR_NOACCESS,
4221 &spr_read_ureg, SPR_NOACCESS,
4222 0x00000000);
4223 /* Thermal management */
4224 register_thrm_sprs(env);
4225 /* L2PMCR */
4226
4227 spr_register(env, SPR_L2PMCR, "L2PMCR",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
4231 /* LDSTDB */
4232
4233 spr_register(env, SPR_LDSTDB, "LDSTDB",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* Memory management */
4238 register_low_BATs(env);
4239 init_excp_7400(env);
4240 env->dcache_line_size = 32;
4241 env->icache_line_size = 32;
4242 /* Allocate hardware IRQ controller */
4243 ppc6xx_irq_init(env_archcpu(env));
4244 }
4245
4246 POWERPC_FAMILY(7410)(ObjectClass *oc, const void *data)
4247 {
4248 DeviceClass *dc = DEVICE_CLASS(oc);
4249 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4250
4251 dc->desc = "PowerPC 7410 (aka G4)";
4252 pcc->init_proc = init_proc_7410;
4253 pcc->check_pow = check_pow_hid0;
4254 pcc->check_attn = check_attn_none;
4255 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4256 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4257 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4258 PPC_FLOAT_STFIWX |
4259 PPC_CACHE | PPC_CACHE_ICBI |
4260 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4261 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4262 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4263 PPC_MEM_TLBIA |
4264 PPC_SEGMENT | PPC_EXTERN |
4265 PPC_ALTIVEC;
4266 pcc->msr_mask = (1ull << MSR_VR) |
4267 (1ull << MSR_POW) |
4268 (1ull << MSR_ILE) |
4269 (1ull << MSR_EE) |
4270 (1ull << MSR_PR) |
4271 (1ull << MSR_FP) |
4272 (1ull << MSR_ME) |
4273 (1ull << MSR_FE0) |
4274 (1ull << MSR_SE) |
4275 (1ull << MSR_DE) |
4276 (1ull << MSR_FE1) |
4277 (1ull << MSR_EP) |
4278 (1ull << MSR_IR) |
4279 (1ull << MSR_DR) |
4280 (1ull << MSR_PMM) |
4281 (1ull << MSR_RI) |
4282 (1ull << MSR_LE);
4283 pcc->mmu_model = POWERPC_MMU_32B;
4284 pcc->excp_model = POWERPC_EXCP_74xx;
4285 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4286 pcc->bfd_mach = bfd_mach_ppc_7400;
4287 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4288 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4289 POWERPC_FLAG_BUS_CLK;
4290 }
4291
init_proc_7440(CPUPPCState * env)4292 static void init_proc_7440(CPUPPCState *env)
4293 {
4294 register_non_embedded_sprs(env);
4295 register_sdr1_sprs(env);
4296 register_74xx_sprs(env);
4297 vscr_init(env, 0x00010000);
4298
4299 spr_register(env, SPR_UBAMR, "UBAMR",
4300 &spr_read_ureg, SPR_NOACCESS,
4301 &spr_read_ureg, SPR_NOACCESS,
4302 0x00000000);
4303 /* LDSTCR */
4304 spr_register(env, SPR_LDSTCR, "LDSTCR",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
4308 /* ICTRL */
4309 spr_register(env, SPR_ICTRL, "ICTRL",
4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* MSSSR0 */
4314 spr_register(env, SPR_MSSSR0, "MSSSR0",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, &spr_write_generic,
4317 0x00000000);
4318 /* PMC */
4319 spr_register(env, SPR_7XX_PMC5, "PMC5",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_generic,
4322 0x00000000);
4323
4324 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4325 &spr_read_ureg, SPR_NOACCESS,
4326 &spr_read_ureg, SPR_NOACCESS,
4327 0x00000000);
4328
4329 spr_register(env, SPR_7XX_PMC6, "PMC6",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333
4334 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4335 &spr_read_ureg, SPR_NOACCESS,
4336 &spr_read_ureg, SPR_NOACCESS,
4337 0x00000000);
4338 /* Memory management */
4339 register_low_BATs(env);
4340 init_excp_7450(env);
4341 env->dcache_line_size = 32;
4342 env->icache_line_size = 32;
4343 /* Allocate hardware IRQ controller */
4344 ppc6xx_irq_init(env_archcpu(env));
4345 }
4346
4347 POWERPC_FAMILY(7440)(ObjectClass *oc, const void *data)
4348 {
4349 DeviceClass *dc = DEVICE_CLASS(oc);
4350 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4351
4352 dc->desc = "PowerPC 7440 (aka G4)";
4353 pcc->init_proc = init_proc_7440;
4354 pcc->check_pow = check_pow_hid0_74xx;
4355 pcc->check_attn = check_attn_none;
4356 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4357 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4358 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4359 PPC_FLOAT_STFIWX |
4360 PPC_CACHE | PPC_CACHE_ICBI |
4361 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4362 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4363 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4364 PPC_MEM_TLBIA |
4365 PPC_SEGMENT | PPC_EXTERN |
4366 PPC_ALTIVEC;
4367 pcc->msr_mask = (1ull << MSR_VR) |
4368 (1ull << MSR_POW) |
4369 (1ull << MSR_ILE) |
4370 (1ull << MSR_EE) |
4371 (1ull << MSR_PR) |
4372 (1ull << MSR_FP) |
4373 (1ull << MSR_ME) |
4374 (1ull << MSR_FE0) |
4375 (1ull << MSR_SE) |
4376 (1ull << MSR_DE) |
4377 (1ull << MSR_FE1) |
4378 (1ull << MSR_EP) |
4379 (1ull << MSR_IR) |
4380 (1ull << MSR_DR) |
4381 (1ull << MSR_PMM) |
4382 (1ull << MSR_RI) |
4383 (1ull << MSR_LE);
4384 pcc->mmu_model = POWERPC_MMU_32B;
4385 pcc->excp_model = POWERPC_EXCP_74xx;
4386 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4387 pcc->bfd_mach = bfd_mach_ppc_7400;
4388 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4389 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4390 POWERPC_FLAG_BUS_CLK;
4391 }
4392
init_proc_7450(CPUPPCState * env)4393 static void init_proc_7450(CPUPPCState *env)
4394 {
4395 register_non_embedded_sprs(env);
4396 register_sdr1_sprs(env);
4397 register_74xx_sprs(env);
4398 vscr_init(env, 0x00010000);
4399 /* Level 3 cache control */
4400 register_l3_ctrl(env);
4401 /* L3ITCR1 */
4402 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4403 SPR_NOACCESS, SPR_NOACCESS,
4404 &spr_read_generic, &spr_write_generic,
4405 0x00000000);
4406 /* L3ITCR2 */
4407 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411 /* L3ITCR3 */
4412 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* L3OHCR */
4417 spr_register(env, SPR_L3OHCR, "L3OHCR",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421
4422 spr_register(env, SPR_UBAMR, "UBAMR",
4423 &spr_read_ureg, SPR_NOACCESS,
4424 &spr_read_ureg, SPR_NOACCESS,
4425 0x00000000);
4426 /* LDSTCR */
4427 spr_register(env, SPR_LDSTCR, "LDSTCR",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
4431 /* ICTRL */
4432 spr_register(env, SPR_ICTRL, "ICTRL",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000);
4436 /* MSSSR0 */
4437 spr_register(env, SPR_MSSSR0, "MSSSR0",
4438 SPR_NOACCESS, SPR_NOACCESS,
4439 &spr_read_generic, &spr_write_generic,
4440 0x00000000);
4441 /* PMC */
4442 spr_register(env, SPR_7XX_PMC5, "PMC5",
4443 SPR_NOACCESS, SPR_NOACCESS,
4444 &spr_read_generic, &spr_write_generic,
4445 0x00000000);
4446
4447 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4448 &spr_read_ureg, SPR_NOACCESS,
4449 &spr_read_ureg, SPR_NOACCESS,
4450 0x00000000);
4451
4452 spr_register(env, SPR_7XX_PMC6, "PMC6",
4453 SPR_NOACCESS, SPR_NOACCESS,
4454 &spr_read_generic, &spr_write_generic,
4455 0x00000000);
4456
4457 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4458 &spr_read_ureg, SPR_NOACCESS,
4459 &spr_read_ureg, SPR_NOACCESS,
4460 0x00000000);
4461 /* Memory management */
4462 register_low_BATs(env);
4463 init_excp_7450(env);
4464 env->dcache_line_size = 32;
4465 env->icache_line_size = 32;
4466 /* Allocate hardware IRQ controller */
4467 ppc6xx_irq_init(env_archcpu(env));
4468 }
4469
4470 POWERPC_FAMILY(7450)(ObjectClass *oc, const void *data)
4471 {
4472 DeviceClass *dc = DEVICE_CLASS(oc);
4473 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4474
4475 dc->desc = "PowerPC 7450 (aka G4)";
4476 pcc->init_proc = init_proc_7450;
4477 pcc->check_pow = check_pow_hid0_74xx;
4478 pcc->check_attn = check_attn_none;
4479 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4480 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4481 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4482 PPC_FLOAT_STFIWX |
4483 PPC_CACHE | PPC_CACHE_ICBI |
4484 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4485 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4486 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4487 PPC_MEM_TLBIA |
4488 PPC_SEGMENT | PPC_EXTERN |
4489 PPC_ALTIVEC;
4490 pcc->msr_mask = (1ull << MSR_VR) |
4491 (1ull << MSR_POW) |
4492 (1ull << MSR_ILE) |
4493 (1ull << MSR_EE) |
4494 (1ull << MSR_PR) |
4495 (1ull << MSR_FP) |
4496 (1ull << MSR_ME) |
4497 (1ull << MSR_FE0) |
4498 (1ull << MSR_SE) |
4499 (1ull << MSR_DE) |
4500 (1ull << MSR_FE1) |
4501 (1ull << MSR_EP) |
4502 (1ull << MSR_IR) |
4503 (1ull << MSR_DR) |
4504 (1ull << MSR_PMM) |
4505 (1ull << MSR_RI) |
4506 (1ull << MSR_LE);
4507 pcc->mmu_model = POWERPC_MMU_32B;
4508 pcc->excp_model = POWERPC_EXCP_74xx;
4509 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4510 pcc->bfd_mach = bfd_mach_ppc_7400;
4511 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4512 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4513 POWERPC_FLAG_BUS_CLK;
4514 }
4515
init_proc_7445(CPUPPCState * env)4516 static void init_proc_7445(CPUPPCState *env)
4517 {
4518 register_non_embedded_sprs(env);
4519 register_sdr1_sprs(env);
4520 register_74xx_sprs(env);
4521 vscr_init(env, 0x00010000);
4522 /* LDSTCR */
4523 spr_register(env, SPR_LDSTCR, "LDSTCR",
4524 SPR_NOACCESS, SPR_NOACCESS,
4525 &spr_read_generic, &spr_write_generic,
4526 0x00000000);
4527 /* ICTRL */
4528 spr_register(env, SPR_ICTRL, "ICTRL",
4529 SPR_NOACCESS, SPR_NOACCESS,
4530 &spr_read_generic, &spr_write_generic,
4531 0x00000000);
4532 /* MSSSR0 */
4533 spr_register(env, SPR_MSSSR0, "MSSSR0",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 /* PMC */
4538 spr_register(env, SPR_7XX_PMC5, "PMC5",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542
4543 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4544 &spr_read_ureg, SPR_NOACCESS,
4545 &spr_read_ureg, SPR_NOACCESS,
4546 0x00000000);
4547
4548 spr_register(env, SPR_7XX_PMC6, "PMC6",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_generic,
4551 0x00000000);
4552
4553 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4554 &spr_read_ureg, SPR_NOACCESS,
4555 &spr_read_ureg, SPR_NOACCESS,
4556 0x00000000);
4557 /* SPRGs */
4558 spr_register(env, SPR_SPRG4, "SPRG4",
4559 SPR_NOACCESS, SPR_NOACCESS,
4560 &spr_read_generic, &spr_write_generic,
4561 0x00000000);
4562 spr_register(env, SPR_USPRG4, "USPRG4",
4563 &spr_read_ureg, SPR_NOACCESS,
4564 &spr_read_ureg, SPR_NOACCESS,
4565 0x00000000);
4566 spr_register(env, SPR_SPRG5, "SPRG5",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_generic, &spr_write_generic,
4569 0x00000000);
4570 spr_register(env, SPR_USPRG5, "USPRG5",
4571 &spr_read_ureg, SPR_NOACCESS,
4572 &spr_read_ureg, SPR_NOACCESS,
4573 0x00000000);
4574 spr_register(env, SPR_SPRG6, "SPRG6",
4575 SPR_NOACCESS, SPR_NOACCESS,
4576 &spr_read_generic, &spr_write_generic,
4577 0x00000000);
4578 spr_register(env, SPR_USPRG6, "USPRG6",
4579 &spr_read_ureg, SPR_NOACCESS,
4580 &spr_read_ureg, SPR_NOACCESS,
4581 0x00000000);
4582 spr_register(env, SPR_SPRG7, "SPRG7",
4583 SPR_NOACCESS, SPR_NOACCESS,
4584 &spr_read_generic, &spr_write_generic,
4585 0x00000000);
4586 spr_register(env, SPR_USPRG7, "USPRG7",
4587 &spr_read_ureg, SPR_NOACCESS,
4588 &spr_read_ureg, SPR_NOACCESS,
4589 0x00000000);
4590 /* Memory management */
4591 register_low_BATs(env);
4592 register_high_BATs(env);
4593 init_excp_7450(env);
4594 env->dcache_line_size = 32;
4595 env->icache_line_size = 32;
4596 /* Allocate hardware IRQ controller */
4597 ppc6xx_irq_init(env_archcpu(env));
4598 }
4599
4600 POWERPC_FAMILY(7445)(ObjectClass *oc, const void *data)
4601 {
4602 DeviceClass *dc = DEVICE_CLASS(oc);
4603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4604
4605 dc->desc = "PowerPC 7445 (aka G4)";
4606 pcc->init_proc = init_proc_7445;
4607 pcc->check_pow = check_pow_hid0_74xx;
4608 pcc->check_attn = check_attn_none;
4609 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4610 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4611 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4612 PPC_FLOAT_STFIWX |
4613 PPC_CACHE | PPC_CACHE_ICBI |
4614 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4615 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4617 PPC_MEM_TLBIA |
4618 PPC_SEGMENT | PPC_EXTERN |
4619 PPC_ALTIVEC;
4620 pcc->msr_mask = (1ull << MSR_VR) |
4621 (1ull << MSR_POW) |
4622 (1ull << MSR_ILE) |
4623 (1ull << MSR_EE) |
4624 (1ull << MSR_PR) |
4625 (1ull << MSR_FP) |
4626 (1ull << MSR_ME) |
4627 (1ull << MSR_FE0) |
4628 (1ull << MSR_SE) |
4629 (1ull << MSR_DE) |
4630 (1ull << MSR_FE1) |
4631 (1ull << MSR_EP) |
4632 (1ull << MSR_IR) |
4633 (1ull << MSR_DR) |
4634 (1ull << MSR_PMM) |
4635 (1ull << MSR_RI) |
4636 (1ull << MSR_LE);
4637 pcc->mmu_model = POWERPC_MMU_32B;
4638 pcc->excp_model = POWERPC_EXCP_74xx;
4639 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4640 pcc->bfd_mach = bfd_mach_ppc_7400;
4641 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4642 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4643 POWERPC_FLAG_BUS_CLK;
4644 }
4645
init_proc_7455(CPUPPCState * env)4646 static void init_proc_7455(CPUPPCState *env)
4647 {
4648 register_non_embedded_sprs(env);
4649 register_sdr1_sprs(env);
4650 register_74xx_sprs(env);
4651 vscr_init(env, 0x00010000);
4652 /* Level 3 cache control */
4653 register_l3_ctrl(env);
4654 /* LDSTCR */
4655 spr_register(env, SPR_LDSTCR, "LDSTCR",
4656 SPR_NOACCESS, SPR_NOACCESS,
4657 &spr_read_generic, &spr_write_generic,
4658 0x00000000);
4659 /* ICTRL */
4660 spr_register(env, SPR_ICTRL, "ICTRL",
4661 SPR_NOACCESS, SPR_NOACCESS,
4662 &spr_read_generic, &spr_write_generic,
4663 0x00000000);
4664 /* MSSSR0 */
4665 spr_register(env, SPR_MSSSR0, "MSSSR0",
4666 SPR_NOACCESS, SPR_NOACCESS,
4667 &spr_read_generic, &spr_write_generic,
4668 0x00000000);
4669 /* PMC */
4670 spr_register(env, SPR_7XX_PMC5, "PMC5",
4671 SPR_NOACCESS, SPR_NOACCESS,
4672 &spr_read_generic, &spr_write_generic,
4673 0x00000000);
4674
4675 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4676 &spr_read_ureg, SPR_NOACCESS,
4677 &spr_read_ureg, SPR_NOACCESS,
4678 0x00000000);
4679
4680 spr_register(env, SPR_7XX_PMC6, "PMC6",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
4684
4685 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4686 &spr_read_ureg, SPR_NOACCESS,
4687 &spr_read_ureg, SPR_NOACCESS,
4688 0x00000000);
4689 /* SPRGs */
4690 spr_register(env, SPR_SPRG4, "SPRG4",
4691 SPR_NOACCESS, SPR_NOACCESS,
4692 &spr_read_generic, &spr_write_generic,
4693 0x00000000);
4694 spr_register(env, SPR_USPRG4, "USPRG4",
4695 &spr_read_ureg, SPR_NOACCESS,
4696 &spr_read_ureg, SPR_NOACCESS,
4697 0x00000000);
4698 spr_register(env, SPR_SPRG5, "SPRG5",
4699 SPR_NOACCESS, SPR_NOACCESS,
4700 &spr_read_generic, &spr_write_generic,
4701 0x00000000);
4702 spr_register(env, SPR_USPRG5, "USPRG5",
4703 &spr_read_ureg, SPR_NOACCESS,
4704 &spr_read_ureg, SPR_NOACCESS,
4705 0x00000000);
4706 spr_register(env, SPR_SPRG6, "SPRG6",
4707 SPR_NOACCESS, SPR_NOACCESS,
4708 &spr_read_generic, &spr_write_generic,
4709 0x00000000);
4710 spr_register(env, SPR_USPRG6, "USPRG6",
4711 &spr_read_ureg, SPR_NOACCESS,
4712 &spr_read_ureg, SPR_NOACCESS,
4713 0x00000000);
4714 spr_register(env, SPR_SPRG7, "SPRG7",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 spr_register(env, SPR_USPRG7, "USPRG7",
4719 &spr_read_ureg, SPR_NOACCESS,
4720 &spr_read_ureg, SPR_NOACCESS,
4721 0x00000000);
4722 /* Memory management */
4723 register_low_BATs(env);
4724 register_high_BATs(env);
4725 init_excp_7450(env);
4726 env->dcache_line_size = 32;
4727 env->icache_line_size = 32;
4728 /* Allocate hardware IRQ controller */
4729 ppc6xx_irq_init(env_archcpu(env));
4730 }
4731
4732 POWERPC_FAMILY(7455)(ObjectClass *oc, const void *data)
4733 {
4734 DeviceClass *dc = DEVICE_CLASS(oc);
4735 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4736
4737 dc->desc = "PowerPC 7455 (aka G4)";
4738 pcc->init_proc = init_proc_7455;
4739 pcc->check_pow = check_pow_hid0_74xx;
4740 pcc->check_attn = check_attn_none;
4741 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4743 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4744 PPC_FLOAT_STFIWX |
4745 PPC_CACHE | PPC_CACHE_ICBI |
4746 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4747 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4748 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4749 PPC_MEM_TLBIA |
4750 PPC_SEGMENT | PPC_EXTERN |
4751 PPC_ALTIVEC;
4752 pcc->msr_mask = (1ull << MSR_VR) |
4753 (1ull << MSR_POW) |
4754 (1ull << MSR_ILE) |
4755 (1ull << MSR_EE) |
4756 (1ull << MSR_PR) |
4757 (1ull << MSR_FP) |
4758 (1ull << MSR_ME) |
4759 (1ull << MSR_FE0) |
4760 (1ull << MSR_SE) |
4761 (1ull << MSR_DE) |
4762 (1ull << MSR_FE1) |
4763 (1ull << MSR_EP) |
4764 (1ull << MSR_IR) |
4765 (1ull << MSR_DR) |
4766 (1ull << MSR_PMM) |
4767 (1ull << MSR_RI) |
4768 (1ull << MSR_LE);
4769 pcc->mmu_model = POWERPC_MMU_32B;
4770 pcc->excp_model = POWERPC_EXCP_74xx;
4771 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4772 pcc->bfd_mach = bfd_mach_ppc_7400;
4773 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4774 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4775 POWERPC_FLAG_BUS_CLK;
4776 }
4777
init_proc_7457(CPUPPCState * env)4778 static void init_proc_7457(CPUPPCState *env)
4779 {
4780 register_non_embedded_sprs(env);
4781 register_sdr1_sprs(env);
4782 register_74xx_sprs(env);
4783 vscr_init(env, 0x00010000);
4784 /* Level 3 cache control */
4785 register_l3_ctrl(env);
4786 /* L3ITCR1 */
4787 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 /* L3ITCR2 */
4792 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 /* L3ITCR3 */
4797 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801 /* L3OHCR */
4802 spr_register(env, SPR_L3OHCR, "L3OHCR",
4803 SPR_NOACCESS, SPR_NOACCESS,
4804 &spr_read_generic, &spr_write_generic,
4805 0x00000000);
4806 /* LDSTCR */
4807 spr_register(env, SPR_LDSTCR, "LDSTCR",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 /* ICTRL */
4812 spr_register(env, SPR_ICTRL, "ICTRL",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* MSSSR0 */
4817 spr_register(env, SPR_MSSSR0, "MSSSR0",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* PMC */
4822 spr_register(env, SPR_7XX_PMC5, "PMC5",
4823 SPR_NOACCESS, SPR_NOACCESS,
4824 &spr_read_generic, &spr_write_generic,
4825 0x00000000);
4826
4827 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4828 &spr_read_ureg, SPR_NOACCESS,
4829 &spr_read_ureg, SPR_NOACCESS,
4830 0x00000000);
4831
4832 spr_register(env, SPR_7XX_PMC6, "PMC6",
4833 SPR_NOACCESS, SPR_NOACCESS,
4834 &spr_read_generic, &spr_write_generic,
4835 0x00000000);
4836
4837 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4838 &spr_read_ureg, SPR_NOACCESS,
4839 &spr_read_ureg, SPR_NOACCESS,
4840 0x00000000);
4841 /* SPRGs */
4842 spr_register(env, SPR_SPRG4, "SPRG4",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
4846 spr_register(env, SPR_USPRG4, "USPRG4",
4847 &spr_read_ureg, SPR_NOACCESS,
4848 &spr_read_ureg, SPR_NOACCESS,
4849 0x00000000);
4850 spr_register(env, SPR_SPRG5, "SPRG5",
4851 SPR_NOACCESS, SPR_NOACCESS,
4852 &spr_read_generic, &spr_write_generic,
4853 0x00000000);
4854 spr_register(env, SPR_USPRG5, "USPRG5",
4855 &spr_read_ureg, SPR_NOACCESS,
4856 &spr_read_ureg, SPR_NOACCESS,
4857 0x00000000);
4858 spr_register(env, SPR_SPRG6, "SPRG6",
4859 SPR_NOACCESS, SPR_NOACCESS,
4860 &spr_read_generic, &spr_write_generic,
4861 0x00000000);
4862 spr_register(env, SPR_USPRG6, "USPRG6",
4863 &spr_read_ureg, SPR_NOACCESS,
4864 &spr_read_ureg, SPR_NOACCESS,
4865 0x00000000);
4866 spr_register(env, SPR_SPRG7, "SPRG7",
4867 SPR_NOACCESS, SPR_NOACCESS,
4868 &spr_read_generic, &spr_write_generic,
4869 0x00000000);
4870 spr_register(env, SPR_USPRG7, "USPRG7",
4871 &spr_read_ureg, SPR_NOACCESS,
4872 &spr_read_ureg, SPR_NOACCESS,
4873 0x00000000);
4874 /* Memory management */
4875 register_low_BATs(env);
4876 register_high_BATs(env);
4877 init_excp_7450(env);
4878 env->dcache_line_size = 32;
4879 env->icache_line_size = 32;
4880 /* Allocate hardware IRQ controller */
4881 ppc6xx_irq_init(env_archcpu(env));
4882 }
4883
4884 POWERPC_FAMILY(7457)(ObjectClass *oc, const void *data)
4885 {
4886 DeviceClass *dc = DEVICE_CLASS(oc);
4887 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4888
4889 dc->desc = "PowerPC 7457 (aka G4)";
4890 pcc->init_proc = init_proc_7457;
4891 pcc->check_pow = check_pow_hid0_74xx;
4892 pcc->check_attn = check_attn_none;
4893 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4894 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4895 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4896 PPC_FLOAT_STFIWX |
4897 PPC_CACHE | PPC_CACHE_ICBI |
4898 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4899 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4900 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4901 PPC_MEM_TLBIA |
4902 PPC_SEGMENT | PPC_EXTERN |
4903 PPC_ALTIVEC;
4904 pcc->msr_mask = (1ull << MSR_VR) |
4905 (1ull << MSR_POW) |
4906 (1ull << MSR_ILE) |
4907 (1ull << MSR_EE) |
4908 (1ull << MSR_PR) |
4909 (1ull << MSR_FP) |
4910 (1ull << MSR_ME) |
4911 (1ull << MSR_FE0) |
4912 (1ull << MSR_SE) |
4913 (1ull << MSR_DE) |
4914 (1ull << MSR_FE1) |
4915 (1ull << MSR_EP) |
4916 (1ull << MSR_IR) |
4917 (1ull << MSR_DR) |
4918 (1ull << MSR_PMM) |
4919 (1ull << MSR_RI) |
4920 (1ull << MSR_LE);
4921 pcc->mmu_model = POWERPC_MMU_32B;
4922 pcc->excp_model = POWERPC_EXCP_74xx;
4923 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4924 pcc->bfd_mach = bfd_mach_ppc_7400;
4925 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4926 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4927 POWERPC_FLAG_BUS_CLK;
4928 }
4929
init_proc_e600(CPUPPCState * env)4930 static void init_proc_e600(CPUPPCState *env)
4931 {
4932 register_non_embedded_sprs(env);
4933 register_sdr1_sprs(env);
4934 register_74xx_sprs(env);
4935 vscr_init(env, 0x00010000);
4936
4937 spr_register(env, SPR_UBAMR, "UBAMR",
4938 &spr_read_ureg, SPR_NOACCESS,
4939 &spr_read_ureg, SPR_NOACCESS,
4940 0x00000000);
4941
4942 spr_register(env, SPR_LDSTCR, "LDSTCR",
4943 SPR_NOACCESS, SPR_NOACCESS,
4944 &spr_read_generic, &spr_write_generic,
4945 0x00000000);
4946
4947 spr_register(env, SPR_ICTRL, "ICTRL",
4948 SPR_NOACCESS, SPR_NOACCESS,
4949 &spr_read_generic, &spr_write_generic,
4950 0x00000000);
4951
4952 spr_register(env, SPR_MSSSR0, "MSSSR0",
4953 SPR_NOACCESS, SPR_NOACCESS,
4954 &spr_read_generic, &spr_write_generic,
4955 0x00000000);
4956
4957 spr_register(env, SPR_7XX_PMC5, "PMC5",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961
4962 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4963 &spr_read_ureg, SPR_NOACCESS,
4964 &spr_read_ureg, SPR_NOACCESS,
4965 0x00000000);
4966
4967 spr_register(env, SPR_7XX_PMC6, "PMC6",
4968 SPR_NOACCESS, SPR_NOACCESS,
4969 &spr_read_generic, &spr_write_generic,
4970 0x00000000);
4971
4972 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4973 &spr_read_ureg, SPR_NOACCESS,
4974 &spr_read_ureg, SPR_NOACCESS,
4975 0x00000000);
4976 /* SPRGs */
4977 spr_register(env, SPR_SPRG4, "SPRG4",
4978 SPR_NOACCESS, SPR_NOACCESS,
4979 &spr_read_generic, &spr_write_generic,
4980 0x00000000);
4981 spr_register(env, SPR_USPRG4, "USPRG4",
4982 &spr_read_ureg, SPR_NOACCESS,
4983 &spr_read_ureg, SPR_NOACCESS,
4984 0x00000000);
4985 spr_register(env, SPR_SPRG5, "SPRG5",
4986 SPR_NOACCESS, SPR_NOACCESS,
4987 &spr_read_generic, &spr_write_generic,
4988 0x00000000);
4989 spr_register(env, SPR_USPRG5, "USPRG5",
4990 &spr_read_ureg, SPR_NOACCESS,
4991 &spr_read_ureg, SPR_NOACCESS,
4992 0x00000000);
4993 spr_register(env, SPR_SPRG6, "SPRG6",
4994 SPR_NOACCESS, SPR_NOACCESS,
4995 &spr_read_generic, &spr_write_generic,
4996 0x00000000);
4997 spr_register(env, SPR_USPRG6, "USPRG6",
4998 &spr_read_ureg, SPR_NOACCESS,
4999 &spr_read_ureg, SPR_NOACCESS,
5000 0x00000000);
5001 spr_register(env, SPR_SPRG7, "SPRG7",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005 spr_register(env, SPR_USPRG7, "USPRG7",
5006 &spr_read_ureg, SPR_NOACCESS,
5007 &spr_read_ureg, SPR_NOACCESS,
5008 0x00000000);
5009 /* Memory management */
5010 register_low_BATs(env);
5011 register_high_BATs(env);
5012 init_excp_7450(env);
5013 env->dcache_line_size = 32;
5014 env->icache_line_size = 32;
5015 /* Allocate hardware IRQ controller */
5016 ppc6xx_irq_init(env_archcpu(env));
5017 }
5018
POWERPC_FAMILY(e600)5019 POWERPC_FAMILY(e600)(ObjectClass *oc, const void *data)
5020 {
5021 DeviceClass *dc = DEVICE_CLASS(oc);
5022 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5023
5024 dc->desc = "PowerPC e600";
5025 pcc->init_proc = init_proc_e600;
5026 pcc->check_pow = check_pow_hid0_74xx;
5027 pcc->check_attn = check_attn_none;
5028 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5029 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5030 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5031 PPC_FLOAT_STFIWX |
5032 PPC_CACHE | PPC_CACHE_ICBI |
5033 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5034 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5035 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5036 PPC_MEM_TLBIA |
5037 PPC_SEGMENT | PPC_EXTERN |
5038 PPC_ALTIVEC;
5039 pcc->insns_flags2 = PPC_NONE;
5040 pcc->msr_mask = (1ull << MSR_VR) |
5041 (1ull << MSR_POW) |
5042 (1ull << MSR_ILE) |
5043 (1ull << MSR_EE) |
5044 (1ull << MSR_PR) |
5045 (1ull << MSR_FP) |
5046 (1ull << MSR_ME) |
5047 (1ull << MSR_FE0) |
5048 (1ull << MSR_SE) |
5049 (1ull << MSR_DE) |
5050 (1ull << MSR_FE1) |
5051 (1ull << MSR_EP) |
5052 (1ull << MSR_IR) |
5053 (1ull << MSR_DR) |
5054 (1ull << MSR_PMM) |
5055 (1ull << MSR_RI) |
5056 (1ull << MSR_LE);
5057 pcc->mmu_model = POWERPC_MMU_32B;
5058 pcc->excp_model = POWERPC_EXCP_74xx;
5059 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5060 pcc->bfd_mach = bfd_mach_ppc_7400;
5061 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5062 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5063 POWERPC_FLAG_BUS_CLK;
5064 }
5065
5066 #if defined(TARGET_PPC64)
5067 #if defined(CONFIG_USER_ONLY)
5068 #define POWERPC970_HID5_INIT 0x00000080
5069 #else
5070 #define POWERPC970_HID5_INIT 0x00000000
5071 #endif
5072
check_pow_970(CPUPPCState * env)5073 static int check_pow_970(CPUPPCState *env)
5074 {
5075 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5076 return 1;
5077 }
5078
5079 return 0;
5080 }
5081
register_970_hid_sprs(CPUPPCState * env)5082 static void register_970_hid_sprs(CPUPPCState *env)
5083 {
5084 /* Hardware implementation registers */
5085 spr_register(env, SPR_HID0, "HID0",
5086 SPR_NOACCESS, SPR_NOACCESS,
5087 &spr_read_generic, &spr_write_clear,
5088 0x60000000);
5089 spr_register(env, SPR_HID1, "HID1",
5090 SPR_NOACCESS, SPR_NOACCESS,
5091 &spr_read_generic, &spr_write_generic,
5092 0x00000000);
5093 spr_register(env, SPR_970_HID5, "HID5",
5094 SPR_NOACCESS, SPR_NOACCESS,
5095 &spr_read_generic, &spr_write_generic,
5096 POWERPC970_HID5_INIT);
5097 }
5098
register_970_hior_sprs(CPUPPCState * env)5099 static void register_970_hior_sprs(CPUPPCState *env)
5100 {
5101 spr_register(env, SPR_HIOR, "HIOR",
5102 SPR_NOACCESS, SPR_NOACCESS,
5103 &spr_read_hior, &spr_write_hior,
5104 0x00000000);
5105 }
5106
register_book3s_ctrl_sprs(CPUPPCState * env)5107 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5108 {
5109 spr_register(env, SPR_CTRL, "CTRL",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 SPR_NOACCESS, &spr_write_CTRL,
5112 0x00000000);
5113 spr_register(env, SPR_UCTRL, "UCTRL",
5114 &spr_read_ureg, SPR_NOACCESS,
5115 &spr_read_ureg, SPR_NOACCESS,
5116 0x00000000);
5117 }
5118
register_book3s_altivec_sprs(CPUPPCState * env)5119 static void register_book3s_altivec_sprs(CPUPPCState *env)
5120 {
5121 if (!(env->insns_flags & PPC_ALTIVEC)) {
5122 return;
5123 }
5124
5125 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5126 &spr_read_generic, &spr_write_generic32,
5127 &spr_read_generic, &spr_write_generic32,
5128 KVM_REG_PPC_VRSAVE, 0x00000000);
5129
5130 }
5131
register_book3s_dbg_sprs(CPUPPCState * env)5132 static void register_book3s_dbg_sprs(CPUPPCState *env)
5133 {
5134 /*
5135 * TODO: different specs define different scopes for these,
5136 * will have to address this:
5137 * 970: super/write and super/read
5138 * powerisa 2.03..2.04: hypv/write and super/read.
5139 * powerisa 2.05 and newer: hypv/write and hypv/read.
5140 */
5141 spr_register_kvm(env, SPR_DABR, "DABR",
5142 SPR_NOACCESS, SPR_NOACCESS,
5143 &spr_read_generic, &spr_write_generic,
5144 KVM_REG_PPC_DABR, 0x00000000);
5145 spr_register_kvm(env, SPR_DABRX, "DABRX",
5146 SPR_NOACCESS, SPR_NOACCESS,
5147 &spr_read_generic, &spr_write_generic,
5148 KVM_REG_PPC_DABRX, 0x00000000);
5149 }
5150
register_book3s_207_dbg_sprs(CPUPPCState * env)5151 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5152 {
5153 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5154 SPR_NOACCESS, SPR_NOACCESS,
5155 SPR_NOACCESS, SPR_NOACCESS,
5156 &spr_read_generic, &spr_write_dawr0,
5157 KVM_REG_PPC_DAWR, 0x00000000);
5158 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 SPR_NOACCESS, SPR_NOACCESS,
5161 &spr_read_generic, &spr_write_dawrx0,
5162 KVM_REG_PPC_DAWRX, 0x00000000);
5163 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_ciabr,
5167 KVM_REG_PPC_CIABR, 0x00000000);
5168 }
5169
register_book3s_310_dbg_sprs(CPUPPCState * env)5170 static void register_book3s_310_dbg_sprs(CPUPPCState *env)
5171 {
5172 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 SPR_NOACCESS, SPR_NOACCESS,
5175 &spr_read_generic, &spr_write_dawr1,
5176 KVM_REG_PPC_DAWR1, 0x00000000);
5177 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_dawrx1,
5181 KVM_REG_PPC_DAWRX1, 0x00000000);
5182 }
5183
register_970_dbg_sprs(CPUPPCState * env)5184 static void register_970_dbg_sprs(CPUPPCState *env)
5185 {
5186 /* Breakpoints */
5187 spr_register(env, SPR_IABR, "IABR",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 0x00000000);
5191 }
5192
register_book3s_pmu_sup_sprs(CPUPPCState * env)5193 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5194 {
5195 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5196 SPR_NOACCESS, SPR_NOACCESS,
5197 &spr_read_generic, &spr_write_MMCR0,
5198 KVM_REG_PPC_MMCR0, 0x80000000);
5199 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_MMCR1,
5202 KVM_REG_PPC_MMCR1, 0x00000000);
5203 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5204 SPR_NOACCESS, SPR_NOACCESS,
5205 &spr_read_generic, &spr_write_MMCRA,
5206 KVM_REG_PPC_MMCRA, 0x00000000);
5207 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5208 SPR_NOACCESS, SPR_NOACCESS,
5209 &spr_read_PMC, &spr_write_PMC,
5210 KVM_REG_PPC_PMC1, 0x00000000);
5211 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5212 SPR_NOACCESS, SPR_NOACCESS,
5213 &spr_read_PMC, &spr_write_PMC,
5214 KVM_REG_PPC_PMC2, 0x00000000);
5215 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5216 SPR_NOACCESS, SPR_NOACCESS,
5217 &spr_read_PMC, &spr_write_PMC,
5218 KVM_REG_PPC_PMC3, 0x00000000);
5219 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5220 SPR_NOACCESS, SPR_NOACCESS,
5221 &spr_read_PMC, &spr_write_PMC,
5222 KVM_REG_PPC_PMC4, 0x00000000);
5223 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5224 SPR_NOACCESS, SPR_NOACCESS,
5225 &spr_read_PMC, &spr_write_PMC,
5226 KVM_REG_PPC_PMC5, 0x00000000);
5227 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_PMC, &spr_write_PMC,
5230 KVM_REG_PPC_PMC6, 0x00000000);
5231 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5232 SPR_NOACCESS, SPR_NOACCESS,
5233 &spr_read_generic, &spr_write_generic,
5234 KVM_REG_PPC_SIAR, 0x00000000);
5235 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 KVM_REG_PPC_SDAR, 0x00000000);
5239 }
5240
register_book3s_pmu_user_sprs(CPUPPCState * env)5241 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5242 {
5243 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5244 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5245 &spr_read_ureg, &spr_write_ureg,
5246 0x80000000);
5247 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5248 &spr_read_ureg, SPR_NOACCESS,
5249 &spr_read_ureg, &spr_write_ureg,
5250 0x00000000);
5251 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5252 &spr_read_ureg, SPR_NOACCESS,
5253 &spr_read_ureg, &spr_write_ureg,
5254 0x00000000);
5255 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5256 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5257 &spr_read_ureg, &spr_write_ureg,
5258 0x00000000);
5259 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5260 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5261 &spr_read_ureg, &spr_write_ureg,
5262 0x00000000);
5263 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5264 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5265 &spr_read_ureg, &spr_write_ureg,
5266 0x00000000);
5267 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5268 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5269 &spr_read_ureg, &spr_write_ureg,
5270 0x00000000);
5271 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5272 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5273 &spr_read_ureg, &spr_write_ureg,
5274 0x00000000);
5275 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5276 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5277 &spr_read_ureg, &spr_write_ureg,
5278 0x00000000);
5279 spr_register(env, SPR_POWER_USIAR, "USIAR",
5280 &spr_read_ureg, SPR_NOACCESS,
5281 &spr_read_ureg, &spr_write_ureg,
5282 0x00000000);
5283 spr_register(env, SPR_POWER_USDAR, "USDAR",
5284 &spr_read_ureg, SPR_NOACCESS,
5285 &spr_read_ureg, &spr_write_ureg,
5286 0x00000000);
5287 }
5288
register_970_pmu_sup_sprs(CPUPPCState * env)5289 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5290 {
5291 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5292 SPR_NOACCESS, SPR_NOACCESS,
5293 &spr_read_generic, &spr_write_generic,
5294 KVM_REG_PPC_PMC7, 0x00000000);
5295 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5296 SPR_NOACCESS, SPR_NOACCESS,
5297 &spr_read_generic, &spr_write_generic,
5298 KVM_REG_PPC_PMC8, 0x00000000);
5299 }
5300
register_970_pmu_user_sprs(CPUPPCState * env)5301 static void register_970_pmu_user_sprs(CPUPPCState *env)
5302 {
5303 spr_register(env, SPR_970_UPMC7, "UPMC7",
5304 &spr_read_ureg, SPR_NOACCESS,
5305 &spr_read_ureg, &spr_write_ureg,
5306 0x00000000);
5307 spr_register(env, SPR_970_UPMC8, "UPMC8",
5308 &spr_read_ureg, SPR_NOACCESS,
5309 &spr_read_ureg, &spr_write_ureg,
5310 0x00000000);
5311 }
5312
register_power8_pmu_sup_sprs(CPUPPCState * env)5313 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5314 {
5315 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5316 SPR_NOACCESS, SPR_NOACCESS,
5317 &spr_read_generic, &spr_write_generic,
5318 KVM_REG_PPC_MMCR2, 0x00000000);
5319 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 &spr_read_generic, &spr_write_generic,
5322 KVM_REG_PPC_MMCRS, 0x00000000);
5323 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 &spr_read_generic, &spr_write_generic,
5326 KVM_REG_PPC_SIER, 0x00000000);
5327 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5328 SPR_NOACCESS, SPR_NOACCESS,
5329 &spr_read_generic, &spr_write_generic,
5330 KVM_REG_PPC_SPMC1, 0x00000000);
5331 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5332 SPR_NOACCESS, SPR_NOACCESS,
5333 &spr_read_generic, &spr_write_generic,
5334 KVM_REG_PPC_SPMC2, 0x00000000);
5335 spr_register_kvm(env, SPR_TACR, "TACR",
5336 SPR_NOACCESS, SPR_NOACCESS,
5337 &spr_read_generic, &spr_write_generic,
5338 KVM_REG_PPC_TACR, 0x00000000);
5339 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 KVM_REG_PPC_TCSCR, 0x00000000);
5343 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5344 SPR_NOACCESS, SPR_NOACCESS,
5345 &spr_read_generic, &spr_write_generic,
5346 KVM_REG_PPC_CSIGR, 0x00000000);
5347 }
5348
register_power8_pmu_user_sprs(CPUPPCState * env)5349 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5350 {
5351 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5352 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5353 &spr_read_ureg, &spr_write_ureg,
5354 0x00000000);
5355 spr_register(env, SPR_POWER_USIER, "USIER",
5356 &spr_read_generic, SPR_NOACCESS,
5357 &spr_read_generic, &spr_write_generic,
5358 0x00000000);
5359 }
5360
register_power10_pmu_sup_sprs(CPUPPCState * env)5361 static void register_power10_pmu_sup_sprs(CPUPPCState *env)
5362 {
5363 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
5364 SPR_NOACCESS, SPR_NOACCESS,
5365 &spr_read_generic, &spr_write_generic,
5366 KVM_REG_PPC_MMCR3, 0x00000000);
5367 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 KVM_REG_PPC_SIER2, 0x00000000);
5371 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
5372 SPR_NOACCESS, SPR_NOACCESS,
5373 &spr_read_generic, &spr_write_generic,
5374 KVM_REG_PPC_SIER3, 0x00000000);
5375 }
5376
register_power10_pmu_user_sprs(CPUPPCState * env)5377 static void register_power10_pmu_user_sprs(CPUPPCState *env)
5378 {
5379 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
5380 &spr_read_generic, &spr_write_generic,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 spr_register(env, SPR_POWER_USIER2, "USIER2",
5384 &spr_read_generic, SPR_NOACCESS,
5385 &spr_read_generic, &spr_write_generic,
5386 0x00000000);
5387 spr_register(env, SPR_POWER_USIER3, "USIER3",
5388 &spr_read_generic, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 }
5392
register_power5p_ear_sprs(CPUPPCState * env)5393 static void register_power5p_ear_sprs(CPUPPCState *env)
5394 {
5395 /* External access control */
5396 spr_register(env, SPR_EAR, "EAR",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 &spr_read_generic, &spr_write_generic,
5399 0x00000000);
5400 }
5401
register_power5p_tb_sprs(CPUPPCState * env)5402 static void register_power5p_tb_sprs(CPUPPCState *env)
5403 {
5404 /* TBU40 (High 40 bits of the Timebase register */
5405 spr_register_hv(env, SPR_TBU40, "TBU40",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 SPR_NOACCESS, &spr_write_tbu40,
5409 0x00000000);
5410 }
5411
register_970_lpar_sprs(CPUPPCState * env)5412 static void register_970_lpar_sprs(CPUPPCState *env)
5413 {
5414 #if !defined(CONFIG_USER_ONLY)
5415 /*
5416 * PPC970: HID4 covers things later controlled by the LPCR and
5417 * RMOR in later CPUs, but with a different encoding. We only
5418 * support the 970 in "Apple mode" which has all hypervisor
5419 * facilities disabled by strapping, so we can basically just
5420 * ignore it
5421 */
5422 spr_register(env, SPR_970_HID4, "HID4",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_generic, &spr_write_generic,
5425 0x00000000);
5426 #endif
5427 }
5428
register_power5p_lpar_sprs(CPUPPCState * env)5429 static void register_power5p_lpar_sprs(CPUPPCState *env)
5430 {
5431 #if !defined(CONFIG_USER_ONLY)
5432 /* Logical partitioning */
5433 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_lpcr,
5437 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5438 spr_register_hv(env, SPR_HDEC, "HDEC",
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_hdecr, &spr_write_hdecr, 0);
5442 #endif
5443 }
5444
register_book3s_ids_sprs(CPUPPCState * env)5445 static void register_book3s_ids_sprs(CPUPPCState *env)
5446 {
5447 /* FIXME: Will need to deal with thread vs core only SPRs */
5448
5449 /* Processor identification */
5450 spr_register_hv(env, SPR_PIR, "PIR",
5451 SPR_NOACCESS, SPR_NOACCESS,
5452 &spr_read_generic, SPR_NOACCESS,
5453 &spr_read_generic, NULL,
5454 0x00000000);
5455 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_lpidr,
5459 0x00000000);
5460 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5461 SPR_NOACCESS, SPR_NOACCESS,
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, &spr_core_write_generic32,
5469 0x00000000);
5470 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 SPR_NOACCESS, SPR_NOACCESS,
5473 &spr_read_generic, &spr_write_generic,
5474 0x00000000);
5475 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 &spr_read_generic, &spr_write_generic,
5479 0x00000000);
5480 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5481 SPR_NOACCESS, SPR_NOACCESS,
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5486 SPR_NOACCESS, SPR_NOACCESS,
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5491 SPR_NOACCESS, SPR_NOACCESS,
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_generic, &spr_write_generic,
5494 0x00000000);
5495 spr_register_hv(env, SPR_HDAR, "HDAR",
5496 SPR_NOACCESS, SPR_NOACCESS,
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, &spr_write_generic,
5499 0x00000000);
5500 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5501 SPR_NOACCESS, SPR_NOACCESS,
5502 SPR_NOACCESS, SPR_NOACCESS,
5503 &spr_read_generic, &spr_write_generic32,
5504 0x00000000);
5505 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5506 SPR_NOACCESS, SPR_NOACCESS,
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_core_write_generic,
5509 0x00000000);
5510 }
5511
register_rmor_sprs(CPUPPCState * env)5512 static void register_rmor_sprs(CPUPPCState *env)
5513 {
5514 spr_register_hv(env, SPR_RMOR, "RMOR",
5515 SPR_NOACCESS, SPR_NOACCESS,
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, &spr_write_generic,
5518 0x00000000);
5519 }
5520
register_power8_ids_sprs(CPUPPCState * env)5521 static void register_power8_ids_sprs(CPUPPCState *env)
5522 {
5523 /* Thread identification */
5524 spr_register(env, SPR_TIR, "TIR",
5525 SPR_NOACCESS, SPR_NOACCESS,
5526 &spr_read_generic, SPR_NOACCESS,
5527 0x00000000);
5528 }
5529
register_book3s_purr_sprs(CPUPPCState * env)5530 static void register_book3s_purr_sprs(CPUPPCState *env)
5531 {
5532 #if !defined(CONFIG_USER_ONLY)
5533 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5534 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5535 &spr_read_purr, SPR_NOACCESS,
5536 &spr_read_purr, SPR_NOACCESS,
5537 &spr_read_purr, &spr_write_purr,
5538 KVM_REG_PPC_PURR, 0x00000000);
5539 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5540 &spr_read_purr, SPR_NOACCESS,
5541 &spr_read_purr, SPR_NOACCESS,
5542 &spr_read_purr, &spr_write_purr,
5543 KVM_REG_PPC_SPURR, 0x00000000);
5544 #endif
5545 }
5546
register_power6_dbg_sprs(CPUPPCState * env)5547 static void register_power6_dbg_sprs(CPUPPCState *env)
5548 {
5549 #if !defined(CONFIG_USER_ONLY)
5550 spr_register(env, SPR_CFAR, "CFAR",
5551 SPR_NOACCESS, SPR_NOACCESS,
5552 &spr_read_cfar, &spr_write_cfar,
5553 0x00000000);
5554 #endif
5555 }
5556
register_power5p_common_sprs(CPUPPCState * env)5557 static void register_power5p_common_sprs(CPUPPCState *env)
5558 {
5559 spr_register_kvm(env, SPR_PPR, "PPR",
5560 &spr_read_generic, &spr_write_generic,
5561 &spr_read_generic, &spr_write_generic,
5562 KVM_REG_PPC_PPR, 0x00000000);
5563 }
5564
register_power6_common_sprs(CPUPPCState * env)5565 static void register_power6_common_sprs(CPUPPCState *env)
5566 {
5567 #if !defined(CONFIG_USER_ONLY)
5568 spr_register_kvm(env, SPR_DSCR, "DSCR",
5569 SPR_NOACCESS, SPR_NOACCESS,
5570 &spr_read_generic, &spr_write_generic,
5571 KVM_REG_PPC_DSCR, 0x00000000);
5572 #endif
5573 /*
5574 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5575 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5576 */
5577 spr_register_hv(env, SPR_PCR, "PCR",
5578 SPR_NOACCESS, SPR_NOACCESS,
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_pcr,
5581 0x00000000);
5582 }
5583
register_HEIR32_spr(CPUPPCState * env)5584 static void register_HEIR32_spr(CPUPPCState *env)
5585 {
5586 spr_register_hv(env, SPR_HEIR, "HEIR",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic32,
5590 0x00000000);
5591 }
5592
register_HEIR64_spr(CPUPPCState * env)5593 static void register_HEIR64_spr(CPUPPCState *env)
5594 {
5595 spr_register_hv(env, SPR_HEIR, "HEIR",
5596 SPR_NOACCESS, SPR_NOACCESS,
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 }
5601
register_power7_common_sprs(CPUPPCState * env)5602 static void register_power7_common_sprs(CPUPPCState *env)
5603 {
5604 spr_register(env, SPR_PPR32, "PPR32",
5605 &spr_read_ppr32, &spr_write_ppr32,
5606 &spr_read_ppr32, &spr_write_ppr32,
5607 0x00000000);
5608 }
5609
register_power8_tce_address_control_sprs(CPUPPCState * env)5610 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5611 {
5612 spr_register_kvm(env, SPR_TAR, "TAR",
5613 &spr_read_tar, &spr_write_tar,
5614 &spr_read_generic, &spr_write_generic,
5615 KVM_REG_PPC_TAR, 0x00000000);
5616 }
5617
register_power8_tm_sprs(CPUPPCState * env)5618 static void register_power8_tm_sprs(CPUPPCState *env)
5619 {
5620 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5621 &spr_read_tm, &spr_write_tm,
5622 &spr_read_tm, &spr_write_tm,
5623 KVM_REG_PPC_TFHAR, 0x00000000);
5624 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5625 &spr_read_tm, &spr_write_tm,
5626 &spr_read_tm, &spr_write_tm,
5627 KVM_REG_PPC_TFIAR, 0x00000000);
5628 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5629 &spr_read_tm, &spr_write_tm,
5630 &spr_read_tm, &spr_write_tm,
5631 KVM_REG_PPC_TEXASR, 0x00000000);
5632 spr_register(env, SPR_TEXASRU, "TEXASRU",
5633 &spr_read_tm_upper32, &spr_write_tm_upper32,
5634 &spr_read_tm_upper32, &spr_write_tm_upper32,
5635 0x00000000);
5636 }
5637
register_power8_ebb_sprs(CPUPPCState * env)5638 static void register_power8_ebb_sprs(CPUPPCState *env)
5639 {
5640 spr_register(env, SPR_BESCRS, "BESCRS",
5641 &spr_read_ebb, &spr_write_ebb,
5642 &spr_read_generic, &spr_write_generic,
5643 0x00000000);
5644 spr_register(env, SPR_BESCRSU, "BESCRSU",
5645 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5646 &spr_read_prev_upper32, &spr_write_prev_upper32,
5647 0x00000000);
5648 spr_register(env, SPR_BESCRR, "BESCRR",
5649 &spr_read_ebb, &spr_write_ebb,
5650 &spr_read_generic, &spr_write_generic,
5651 0x00000000);
5652 spr_register(env, SPR_BESCRRU, "BESCRRU",
5653 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5654 &spr_read_prev_upper32, &spr_write_prev_upper32,
5655 0x00000000);
5656 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5657 &spr_read_ebb, &spr_write_ebb,
5658 &spr_read_generic, &spr_write_generic,
5659 KVM_REG_PPC_EBBHR, 0x00000000);
5660 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5661 &spr_read_ebb, &spr_write_ebb,
5662 &spr_read_generic, &spr_write_generic,
5663 KVM_REG_PPC_EBBRR, 0x00000000);
5664 spr_register_kvm(env, SPR_BESCR, "BESCR",
5665 &spr_read_ebb, &spr_write_ebb,
5666 &spr_read_generic, &spr_write_generic,
5667 KVM_REG_PPC_BESCR, 0x00000000);
5668 }
5669
5670 /* Virtual Time Base */
register_vtb_sprs(CPUPPCState * env)5671 static void register_vtb_sprs(CPUPPCState *env)
5672 {
5673 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_vtb, SPR_NOACCESS,
5676 &spr_read_vtb, &spr_write_vtb,
5677 KVM_REG_PPC_VTB, 0x00000000);
5678 }
5679
register_power8_fscr_sprs(CPUPPCState * env)5680 static void register_power8_fscr_sprs(CPUPPCState *env)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 target_ulong initval = 1ULL << FSCR_TAR;
5684 #else
5685 target_ulong initval = 0;
5686 #endif
5687 spr_register_kvm(env, SPR_FSCR, "FSCR",
5688 SPR_NOACCESS, SPR_NOACCESS,
5689 &spr_read_generic, &spr_write_generic,
5690 KVM_REG_PPC_FSCR, initval);
5691 }
5692
register_power8_pspb_sprs(CPUPPCState * env)5693 static void register_power8_pspb_sprs(CPUPPCState *env)
5694 {
5695 spr_register_kvm(env, SPR_PSPB, "PSPB",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic32,
5698 KVM_REG_PPC_PSPB, 0);
5699 }
5700
register_power8_dpdes_sprs(CPUPPCState * env)5701 static void register_power8_dpdes_sprs(CPUPPCState *env)
5702 {
5703 #if !defined(CONFIG_USER_ONLY)
5704 /* Directed Privileged Door-bell Exception State, used for IPI */
5705 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_dpdes, SPR_NOACCESS,
5708 &spr_read_dpdes, &spr_write_dpdes,
5709 KVM_REG_PPC_DPDES, 0x00000000);
5710 #endif
5711 }
5712
register_power8_ic_sprs(CPUPPCState * env)5713 static void register_power8_ic_sprs(CPUPPCState *env)
5714 {
5715 #if !defined(CONFIG_USER_ONLY)
5716 spr_register_hv(env, SPR_IC, "IC",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, SPR_NOACCESS,
5719 &spr_read_generic, &spr_write_generic,
5720 0);
5721 #endif
5722 }
5723
5724 /* SPRs specific to IBM POWER CPUs */
register_power_common_book4_sprs(CPUPPCState * env)5725 static void register_power_common_book4_sprs(CPUPPCState *env)
5726 {
5727 #if !defined(CONFIG_USER_ONLY)
5728 spr_register_hv(env, SPR_HID0, "HID0",
5729 SPR_NOACCESS, SPR_NOACCESS,
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, &spr_core_write_generic,
5732 0x00000000);
5733 spr_register_hv(env, SPR_TSCR, "TSCR",
5734 SPR_NOACCESS, SPR_NOACCESS,
5735 SPR_NOACCESS, SPR_NOACCESS,
5736 &spr_read_generic, &spr_core_write_generic32,
5737 0x00000000);
5738 spr_register_hv(env, SPR_HMER, "HMER",
5739 SPR_NOACCESS, SPR_NOACCESS,
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, &spr_write_hmer,
5742 0x00000000);
5743 spr_register_hv(env, SPR_HMEER, "HMEER",
5744 SPR_NOACCESS, SPR_NOACCESS,
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_core_write_generic,
5747 0x00000000);
5748 spr_register_hv(env, SPR_TFMR, "TFMR",
5749 SPR_NOACCESS, SPR_NOACCESS,
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_tfmr, &spr_write_tfmr,
5752 0x00000000);
5753 spr_register_hv(env, SPR_TRIG1, "TRIG1",
5754 SPR_NOACCESS, SPR_NOACCESS,
5755 &spr_access_nop, &spr_write_generic,
5756 &spr_access_nop, &spr_write_generic,
5757 0x00000000);
5758 spr_register_hv(env, SPR_TRIG2, "TRIG2",
5759 SPR_NOACCESS, SPR_NOACCESS,
5760 &spr_access_nop, &spr_write_generic,
5761 &spr_access_nop, &spr_write_generic,
5762 0x00000000);
5763 spr_register_hv(env, SPR_LDBAR, "LDBAR",
5764 SPR_NOACCESS, SPR_NOACCESS,
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_core_lpar_write_generic,
5767 0x00000000);
5768 spr_register_hv(env, SPR_POWER_TTR, "TTR",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 SPR_NOACCESS, SPR_NOACCESS,
5771 &spr_read_generic, &spr_core_write_generic,
5772 0x00000000);
5773 #endif
5774 }
5775
register_power9_book4_sprs(CPUPPCState * env)5776 static void register_power9_book4_sprs(CPUPPCState *env)
5777 {
5778 /* Add a number of P9 book4 registers */
5779 register_power_common_book4_sprs(env);
5780 #if !defined(CONFIG_USER_ONLY)
5781 spr_register_kvm(env, SPR_WORT, "WORT",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 KVM_REG_PPC_WORT, 0);
5785 spr_register_hv(env, SPR_RWMR, "RWMR",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 &spr_read_generic, &spr_write_generic,
5789 0x00000000);
5790
5791 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
5792 spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
5793 SPR_NOACCESS, SPR_NOACCESS,
5794 SPR_NOACCESS, SPR_NOACCESS,
5795 &spr_read_generic, &spr_write_sprc,
5796 0x00000000);
5797 spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
5798 SPR_NOACCESS, SPR_NOACCESS,
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 &spr_read_sprd, &spr_write_sprd,
5801 0x00000000);
5802 #endif
5803 }
5804
register_power8_book4_sprs(CPUPPCState * env)5805 static void register_power8_book4_sprs(CPUPPCState *env)
5806 {
5807 /* Add a number of P8 book4 registers */
5808 register_power_common_book4_sprs(env);
5809 #if !defined(CONFIG_USER_ONLY)
5810 spr_register_kvm(env, SPR_ACOP, "ACOP",
5811 SPR_NOACCESS, SPR_NOACCESS,
5812 &spr_read_generic, &spr_write_generic,
5813 KVM_REG_PPC_ACOP, 0);
5814 /* PID is only in BookE in ISA v2.07 */
5815 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5816 SPR_NOACCESS, SPR_NOACCESS,
5817 &spr_read_generic, &spr_write_pidr,
5818 KVM_REG_PPC_PID, 0);
5819 spr_register_kvm(env, SPR_WORT, "WORT",
5820 SPR_NOACCESS, SPR_NOACCESS,
5821 &spr_read_generic, &spr_write_generic,
5822 KVM_REG_PPC_WORT, 0);
5823 #endif
5824 }
5825
register_power7_book4_sprs(CPUPPCState * env)5826 static void register_power7_book4_sprs(CPUPPCState *env)
5827 {
5828 /* Add a number of P7 book4 registers */
5829 #if !defined(CONFIG_USER_ONLY)
5830 register_power_common_book4_sprs(env);
5831 spr_register_kvm(env, SPR_ACOP, "ACOP",
5832 SPR_NOACCESS, SPR_NOACCESS,
5833 &spr_read_generic, &spr_write_generic,
5834 KVM_REG_PPC_ACOP, 0);
5835 /* PID is only in BookE in ISA v2.06 */
5836 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_generic32,
5839 KVM_REG_PPC_PID, 0);
5840 #endif
5841 }
5842
register_power8_rpr_sprs(CPUPPCState * env)5843 static void register_power8_rpr_sprs(CPUPPCState *env)
5844 {
5845 #if !defined(CONFIG_USER_ONLY)
5846 spr_register_hv(env, SPR_RPR, "RPR",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_core_write_generic,
5850 0x00000103070F1F3F);
5851 #endif
5852 }
5853
register_power9_mmu_sprs(CPUPPCState * env)5854 static void register_power9_mmu_sprs(CPUPPCState *env)
5855 {
5856 #if !defined(CONFIG_USER_ONLY)
5857 /* Partition Table Control */
5858 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, &spr_write_ptcr,
5862 KVM_REG_PPC_PTCR, 0x00000000);
5863 /* Address Segment Descriptor Register */
5864 spr_register_hv(env, SPR_ASDR, "ASDR",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 SPR_NOACCESS, SPR_NOACCESS,
5867 &spr_read_generic, &spr_write_generic,
5868 0x0000000000000000);
5869 /* PID is part of the BookS ISA from v3.0 */
5870 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_pidr,
5873 KVM_REG_PPC_PID, 0);
5874 #endif
5875 }
5876
register_power10_hash_sprs(CPUPPCState * env)5877 static void register_power10_hash_sprs(CPUPPCState *env)
5878 {
5879 /*
5880 * it's the OS responsibility to generate a random value for the registers
5881 * in each process' context. So, initialize it with 0 here.
5882 */
5883 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5884 #if defined(CONFIG_USER_ONLY)
5885 /* in linux-user, setup the hash register with a random value */
5886 GRand *rand = g_rand_new();
5887 hashkeyr_initial_value =
5888 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5889 hashpkeyr_initial_value =
5890 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5891 g_rand_free(rand);
5892 #endif
5893 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 &spr_read_generic, &spr_write_generic,
5896 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value);
5897 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5898 SPR_NOACCESS, SPR_NOACCESS,
5899 SPR_NOACCESS, SPR_NOACCESS,
5900 &spr_read_generic, &spr_write_generic,
5901 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value);
5902 }
5903
register_power10_dexcr_sprs(CPUPPCState * env)5904 static void register_power10_dexcr_sprs(CPUPPCState *env)
5905 {
5906 spr_register_kvm(env, SPR_DEXCR, "DEXCR",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR,
5909 0);
5910
5911 spr_register(env, SPR_UDEXCR, "UDEXCR",
5912 &spr_read_dexcr_ureg, SPR_NOACCESS,
5913 &spr_read_dexcr_ureg, SPR_NOACCESS,
5914 0);
5915
5916 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 &spr_read_generic, &spr_write_generic,
5920 0);
5921
5922 spr_register(env, SPR_UHDEXCR, "UHDEXCR",
5923 &spr_read_dexcr_ureg, SPR_NOACCESS,
5924 &spr_read_dexcr_ureg, SPR_NOACCESS,
5925 0);
5926 }
5927
5928 /*
5929 * Initialize PMU counter overflow timers for Power8 and
5930 * newer Power chips when using TCG.
5931 */
init_tcg_pmu_power8(CPUPPCState * env)5932 static void init_tcg_pmu_power8(CPUPPCState *env)
5933 {
5934 /* Init PMU overflow timers */
5935 if (tcg_enabled()) {
5936 cpu_ppc_pmu_init(env);
5937 }
5938 }
5939
init_proc_book3s_common(CPUPPCState * env)5940 static void init_proc_book3s_common(CPUPPCState *env)
5941 {
5942 register_non_embedded_sprs(env);
5943 register_book3s_altivec_sprs(env);
5944 register_book3s_pmu_sup_sprs(env);
5945 register_book3s_pmu_user_sprs(env);
5946 register_book3s_ctrl_sprs(env);
5947 /*
5948 * Can't find information on what this should be on reset. This
5949 * value is the one used by 74xx processors.
5950 */
5951 vscr_init(env, 0x00010000);
5952
5953 spr_register(env, SPR_USPRG3, "USPRG3",
5954 &spr_read_ureg, SPR_NOACCESS,
5955 &spr_read_ureg, SPR_NOACCESS,
5956 0x00000000);
5957 }
5958
init_proc_970(CPUPPCState * env)5959 static void init_proc_970(CPUPPCState *env)
5960 {
5961 /* Common Registers */
5962 init_proc_book3s_common(env);
5963 register_sdr1_sprs(env);
5964 register_book3s_dbg_sprs(env);
5965
5966 /* 970 Specific Registers */
5967 register_970_hid_sprs(env);
5968 register_970_hior_sprs(env);
5969 register_low_BATs(env);
5970 register_970_pmu_sup_sprs(env);
5971 register_970_pmu_user_sprs(env);
5972 register_970_lpar_sprs(env);
5973 register_970_dbg_sprs(env);
5974
5975 /* env variables */
5976 env->dcache_line_size = 128;
5977 env->icache_line_size = 128;
5978
5979 /* Allocate hardware IRQ controller */
5980 init_excp_970(env);
5981 ppc970_irq_init(env_archcpu(env));
5982 }
5983
5984 POWERPC_FAMILY(970)(ObjectClass *oc, const void *data)
5985 {
5986 DeviceClass *dc = DEVICE_CLASS(oc);
5987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5988
5989 dc->desc = "PowerPC 970";
5990 pcc->init_proc = init_proc_970;
5991 pcc->check_pow = check_pow_970;
5992 pcc->check_attn = check_attn_hid0;
5993 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5994 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5995 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5996 PPC_FLOAT_STFIWX |
5997 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5998 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5999 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6000 PPC_64B | PPC_ALTIVEC |
6001 PPC_SEGMENT_64B | PPC_SLBI;
6002 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6003 pcc->msr_mask = (1ull << MSR_SF) |
6004 (1ull << MSR_VR) |
6005 (1ull << MSR_POW) |
6006 (1ull << MSR_EE) |
6007 (1ull << MSR_PR) |
6008 (1ull << MSR_FP) |
6009 (1ull << MSR_ME) |
6010 (1ull << MSR_FE0) |
6011 (1ull << MSR_SE) |
6012 (1ull << MSR_DE) |
6013 (1ull << MSR_FE1) |
6014 (1ull << MSR_IR) |
6015 (1ull << MSR_DR) |
6016 (1ull << MSR_PMM) |
6017 (1ull << MSR_RI);
6018 pcc->mmu_model = POWERPC_MMU_64B;
6019 #if !defined(CONFIG_USER_ONLY)
6020 pcc->hash64_opts = &ppc_hash64_opts_basic;
6021 #endif
6022 pcc->excp_model = POWERPC_EXCP_970;
6023 pcc->bus_model = PPC_FLAGS_INPUT_970;
6024 pcc->bfd_mach = bfd_mach_ppc64;
6025 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6027 POWERPC_FLAG_BUS_CLK;
6028 pcc->l1_dcache_size = 0x8000;
6029 pcc->l1_icache_size = 0x10000;
6030 }
6031
init_proc_power5plus(CPUPPCState * env)6032 static void init_proc_power5plus(CPUPPCState *env)
6033 {
6034 /* Common Registers */
6035 init_proc_book3s_common(env);
6036 register_sdr1_sprs(env);
6037 register_book3s_dbg_sprs(env);
6038
6039 /* POWER5+ Specific Registers */
6040 register_970_hid_sprs(env);
6041 register_970_hior_sprs(env);
6042 register_low_BATs(env);
6043 register_970_pmu_sup_sprs(env);
6044 register_970_pmu_user_sprs(env);
6045 register_power5p_common_sprs(env);
6046 register_power5p_lpar_sprs(env);
6047 register_power5p_ear_sprs(env);
6048 register_power5p_tb_sprs(env);
6049
6050 /* env variables */
6051 env->dcache_line_size = 128;
6052 env->icache_line_size = 128;
6053
6054 /* Allocate hardware IRQ controller */
6055 init_excp_970(env);
6056 ppc970_irq_init(env_archcpu(env));
6057 }
6058
POWERPC_FAMILY(POWER5P)6059 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, const void *data)
6060 {
6061 DeviceClass *dc = DEVICE_CLASS(oc);
6062 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6063
6064 dc->fw_name = "PowerPC,POWER5";
6065 dc->desc = "POWER5+";
6066 pcc->init_proc = init_proc_power5plus;
6067 pcc->check_pow = check_pow_970;
6068 pcc->check_attn = check_attn_hid0;
6069 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6070 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6071 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6072 PPC_FLOAT_STFIWX |
6073 PPC_FLOAT_EXT |
6074 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6075 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6077 PPC_64B |
6078 PPC_POPCNTB |
6079 PPC_SEGMENT_64B | PPC_SLBI;
6080 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6081 pcc->msr_mask = (1ull << MSR_SF) |
6082 (1ull << MSR_VR) |
6083 (1ull << MSR_POW) |
6084 (1ull << MSR_EE) |
6085 (1ull << MSR_PR) |
6086 (1ull << MSR_FP) |
6087 (1ull << MSR_ME) |
6088 (1ull << MSR_FE0) |
6089 (1ull << MSR_SE) |
6090 (1ull << MSR_DE) |
6091 (1ull << MSR_FE1) |
6092 (1ull << MSR_IR) |
6093 (1ull << MSR_DR) |
6094 (1ull << MSR_PMM) |
6095 (1ull << MSR_RI);
6096 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6097 LPCR_RMI | LPCR_HDICE;
6098 pcc->mmu_model = POWERPC_MMU_2_03;
6099 #if !defined(CONFIG_USER_ONLY)
6100 pcc->hash64_opts = &ppc_hash64_opts_basic;
6101 pcc->lrg_decr_bits = 32;
6102 #endif
6103 pcc->excp_model = POWERPC_EXCP_970;
6104 pcc->bus_model = PPC_FLAGS_INPUT_970;
6105 pcc->bfd_mach = bfd_mach_ppc64;
6106 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6107 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6108 POWERPC_FLAG_BUS_CLK;
6109 pcc->l1_dcache_size = 0x8000;
6110 pcc->l1_icache_size = 0x10000;
6111 }
6112
init_proc_POWER7(CPUPPCState * env)6113 static void init_proc_POWER7(CPUPPCState *env)
6114 {
6115 /* Common Registers */
6116 init_proc_book3s_common(env);
6117 register_sdr1_sprs(env);
6118 register_book3s_dbg_sprs(env);
6119
6120 /* POWER7 Specific Registers */
6121 register_book3s_ids_sprs(env);
6122 register_rmor_sprs(env);
6123 register_amr_sprs(env);
6124 register_book3s_purr_sprs(env);
6125 register_power5p_common_sprs(env);
6126 register_power5p_lpar_sprs(env);
6127 register_power5p_ear_sprs(env);
6128 register_power5p_tb_sprs(env);
6129 register_power6_common_sprs(env);
6130 register_HEIR32_spr(env);
6131 register_power6_dbg_sprs(env);
6132 register_power7_common_sprs(env);
6133 register_power7_book4_sprs(env);
6134
6135 /* env variables */
6136 env->dcache_line_size = 128;
6137 env->icache_line_size = 128;
6138
6139 /* Allocate hardware IRQ controller */
6140 init_excp_POWER7(env);
6141 ppcPOWER7_irq_init(env_archcpu(env));
6142 }
6143
ppc_pvr_match_power7(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6144 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6145 {
6146 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6147 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6148
6149 if (!best) {
6150 if (base == CPU_POWERPC_POWER7_BASE) {
6151 return true;
6152 }
6153 if (base == CPU_POWERPC_POWER7P_BASE) {
6154 return true;
6155 }
6156 }
6157
6158 if (base != pcc_base) {
6159 return false;
6160 }
6161
6162 return true;
6163 }
6164
POWERPC_FAMILY(POWER7)6165 POWERPC_FAMILY(POWER7)(ObjectClass *oc, const void *data)
6166 {
6167 DeviceClass *dc = DEVICE_CLASS(oc);
6168 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6169
6170 dc->fw_name = "PowerPC,POWER7";
6171 dc->desc = "POWER7";
6172 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS;
6173 pcc->pvr_match = ppc_pvr_match_power7;
6174 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6175 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6176 pcc->init_proc = init_proc_POWER7;
6177 pcc->check_pow = check_pow_nocheck;
6178 pcc->check_attn = check_attn_hid0;
6179 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6180 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6181 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6182 PPC_FLOAT_FRSQRTES |
6183 PPC_FLOAT_STFIWX |
6184 PPC_FLOAT_EXT |
6185 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6186 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6187 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6188 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6189 PPC_SEGMENT_64B | PPC_SLBI |
6190 PPC_POPCNTB | PPC_POPCNTWD |
6191 PPC_CILDST;
6192 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6193 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6194 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6195 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6196 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6197 pcc->msr_mask = (1ull << MSR_SF) |
6198 (1ull << MSR_VR) |
6199 (1ull << MSR_VSX) |
6200 (1ull << MSR_EE) |
6201 (1ull << MSR_PR) |
6202 (1ull << MSR_FP) |
6203 (1ull << MSR_ME) |
6204 (1ull << MSR_FE0) |
6205 (1ull << MSR_SE) |
6206 (1ull << MSR_DE) |
6207 (1ull << MSR_FE1) |
6208 (1ull << MSR_IR) |
6209 (1ull << MSR_DR) |
6210 (1ull << MSR_PMM) |
6211 (1ull << MSR_RI) |
6212 (1ull << MSR_LE);
6213 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6214 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6215 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6216 LPCR_MER | LPCR_TC |
6217 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6218 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6219 pcc->mmu_model = POWERPC_MMU_2_06;
6220 #if !defined(CONFIG_USER_ONLY)
6221 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6222 pcc->lrg_decr_bits = 32;
6223 #endif
6224 pcc->excp_model = POWERPC_EXCP_POWER7;
6225 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6226 pcc->bfd_mach = bfd_mach_ppc64;
6227 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6228 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6229 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6230 POWERPC_FLAG_VSX;
6231 pcc->l1_dcache_size = 0x8000;
6232 pcc->l1_icache_size = 0x8000;
6233 }
6234
bhrb_init_state(CPUPPCState * env,target_long num_entries_log2)6235 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2)
6236 {
6237 if (env->flags & POWERPC_FLAG_BHRB) {
6238 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) {
6239 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2;
6240 }
6241 env->bhrb_num_entries = 1 << num_entries_log2;
6242 env->bhrb_base = (intptr_t)&env->bhrb[0];
6243 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1;
6244 }
6245 }
6246
bhrb_reset_state(CPUPPCState * env)6247 static void bhrb_reset_state(CPUPPCState *env)
6248 {
6249 if (env->flags & POWERPC_FLAG_BHRB) {
6250 env->bhrb_offset = 0;
6251 env->bhrb_filter = 0;
6252 memset(env->bhrb, 0, sizeof(env->bhrb));
6253 }
6254 }
6255
6256 #define POWER8_BHRB_ENTRIES_LOG2 5
init_proc_POWER8(CPUPPCState * env)6257 static void init_proc_POWER8(CPUPPCState *env)
6258 {
6259 /* Common Registers */
6260 init_proc_book3s_common(env);
6261 register_sdr1_sprs(env);
6262 register_book3s_207_dbg_sprs(env);
6263
6264 /* Common TCG PMU */
6265 init_tcg_pmu_power8(env);
6266
6267 /* POWER8 Specific Registers */
6268 register_book3s_ids_sprs(env);
6269 register_rmor_sprs(env);
6270 register_amr_sprs(env);
6271 register_iamr_sprs(env);
6272 register_book3s_purr_sprs(env);
6273 register_power5p_common_sprs(env);
6274 register_power5p_lpar_sprs(env);
6275 register_power5p_ear_sprs(env);
6276 register_power5p_tb_sprs(env);
6277 register_power6_common_sprs(env);
6278 register_HEIR32_spr(env);
6279 register_power6_dbg_sprs(env);
6280 register_power7_common_sprs(env);
6281 register_power8_tce_address_control_sprs(env);
6282 register_power8_ids_sprs(env);
6283 register_power8_ebb_sprs(env);
6284 register_power8_fscr_sprs(env);
6285 register_power8_pmu_sup_sprs(env);
6286 register_power8_pmu_user_sprs(env);
6287 register_power8_tm_sprs(env);
6288 register_power8_pspb_sprs(env);
6289 register_power8_dpdes_sprs(env);
6290 register_vtb_sprs(env);
6291 register_power8_ic_sprs(env);
6292 register_power8_book4_sprs(env);
6293 register_power8_rpr_sprs(env);
6294
6295 /* env variables */
6296 env->dcache_line_size = 128;
6297 env->icache_line_size = 128;
6298
6299 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2);
6300
6301 /* Allocate hardware IRQ controller */
6302 init_excp_POWER8(env);
6303 ppcPOWER7_irq_init(env_archcpu(env));
6304 }
6305
ppc_pvr_match_power8(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6306 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6307 {
6308 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6309 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6310
6311 if (!best) {
6312 if (base == CPU_POWERPC_POWER8_BASE) {
6313 return true;
6314 }
6315 if (base == CPU_POWERPC_POWER8E_BASE) {
6316 return true;
6317 }
6318 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6319 return true;
6320 }
6321 }
6322 if (base != pcc_base) {
6323 return false;
6324 }
6325
6326 return true;
6327 }
6328
POWERPC_FAMILY(POWER8)6329 POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
6330 {
6331 DeviceClass *dc = DEVICE_CLASS(oc);
6332 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6333
6334 dc->fw_name = "PowerPC,POWER8";
6335 dc->desc = "POWER8";
6336 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07;
6337 pcc->pvr_match = ppc_pvr_match_power8;
6338 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6339 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6340 pcc->init_proc = init_proc_POWER8;
6341 pcc->check_pow = check_pow_nocheck;
6342 pcc->check_attn = check_attn_hid0;
6343 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6344 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6345 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6346 PPC_FLOAT_FRSQRTES |
6347 PPC_FLOAT_STFIWX |
6348 PPC_FLOAT_EXT |
6349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6350 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6352 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6353 PPC_SEGMENT_64B | PPC_SLBI |
6354 PPC_POPCNTB | PPC_POPCNTWD |
6355 PPC_CILDST;
6356 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6357 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6358 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6359 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6360 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6361 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6362 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6363 PPC2_BCDA_ISA206;
6364 pcc->msr_mask = (1ull << MSR_SF) |
6365 (1ull << MSR_HV) |
6366 (1ull << MSR_TM) |
6367 (1ull << MSR_VR) |
6368 (1ull << MSR_VSX) |
6369 (1ull << MSR_EE) |
6370 (1ull << MSR_PR) |
6371 (1ull << MSR_FP) |
6372 (1ull << MSR_ME) |
6373 (1ull << MSR_FE0) |
6374 (1ull << MSR_SE) |
6375 (1ull << MSR_DE) |
6376 (1ull << MSR_FE1) |
6377 (1ull << MSR_IR) |
6378 (1ull << MSR_DR) |
6379 (1ull << MSR_PMM) |
6380 (1ull << MSR_RI) |
6381 (1ull << MSR_TS0) |
6382 (1ull << MSR_TS1) |
6383 (1ull << MSR_LE);
6384 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6385 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6386 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6387 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6388 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6389 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6390 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6391 pcc->mmu_model = POWERPC_MMU_2_07;
6392 #if !defined(CONFIG_USER_ONLY)
6393 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6394 pcc->lrg_decr_bits = 32;
6395 pcc->n_host_threads = 8;
6396 #endif
6397 pcc->excp_model = POWERPC_EXCP_POWER8;
6398 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6399 pcc->bfd_mach = bfd_mach_ppc64;
6400 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6401 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6402 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6403 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6404 pcc->l1_dcache_size = 0x8000;
6405 pcc->l1_icache_size = 0x8000;
6406 }
6407
6408 #ifndef CONFIG_USER_ONLY
6409 /*
6410 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6411 * Encoded as array of int_32s in the form:
6412 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6413 * x -> AP encoding
6414 * y -> radix mode supported page size (encoded as a shift)
6415 */
6416 static struct ppc_radix_page_info POWER9_radix_page_info = {
6417 .count = 4,
6418 .entries = {
6419 0x0000000c, /* 4K - enc: 0x0 */
6420 0xa0000010, /* 64K - enc: 0x5 */
6421 0x20000015, /* 2M - enc: 0x1 */
6422 0x4000001e /* 1G - enc: 0x2 */
6423 }
6424 };
6425 #endif /* CONFIG_USER_ONLY */
6426
6427 #define POWER9_BHRB_ENTRIES_LOG2 5
register_power9_common_sprs(CPUPPCState * env)6428 static void register_power9_common_sprs(CPUPPCState *env)
6429 {
6430 /* Common Registers */
6431 init_proc_book3s_common(env);
6432 register_book3s_207_dbg_sprs(env);
6433
6434 /* Common TCG PMU */
6435 init_tcg_pmu_power8(env);
6436
6437 /* POWER8 Specific Registers */
6438 register_book3s_ids_sprs(env);
6439 register_amr_sprs(env);
6440 register_iamr_sprs(env);
6441 register_book3s_purr_sprs(env);
6442 register_power5p_common_sprs(env);
6443 register_power5p_lpar_sprs(env);
6444 register_power5p_ear_sprs(env);
6445 register_power5p_tb_sprs(env);
6446 register_power6_common_sprs(env);
6447 register_power6_dbg_sprs(env);
6448 register_power7_common_sprs(env);
6449 register_power8_tce_address_control_sprs(env);
6450 register_power8_ids_sprs(env);
6451 register_power8_ebb_sprs(env);
6452 register_power8_fscr_sprs(env);
6453 register_power8_pmu_sup_sprs(env);
6454 register_power8_pmu_user_sprs(env);
6455 register_power8_tm_sprs(env);
6456 register_power8_pspb_sprs(env);
6457 register_power8_dpdes_sprs(env);
6458 register_vtb_sprs(env);
6459 register_power8_ic_sprs(env);
6460 register_power9_book4_sprs(env);
6461 register_power8_rpr_sprs(env);
6462 register_power9_mmu_sprs(env);
6463
6464 /* FIXME: Filter fields properly based on privilege level */
6465 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6466 spr_read_generic, spr_write_generic,
6467 KVM_REG_PPC_PSSCR, 0);
6468
6469 spr_register_hv(env, SPR_PMSR, "PMSR",
6470 SPR_NOACCESS, SPR_NOACCESS,
6471 SPR_NOACCESS, SPR_NOACCESS,
6472 &spr_read_pmsr, SPR_NOACCESS,
6473 0);
6474 spr_register_hv(env, SPR_PMCR, "PMCR",
6475 SPR_NOACCESS, SPR_NOACCESS,
6476 SPR_NOACCESS, SPR_NOACCESS,
6477 &spr_read_generic, &spr_write_pmcr,
6478 PPC_BIT(63)); /* Version 1 (POWER9/10) */
6479
6480 }
6481
init_proc_POWER9(CPUPPCState * env)6482 static void init_proc_POWER9(CPUPPCState *env)
6483 {
6484 register_power9_common_sprs(env);
6485 register_HEIR32_spr(env);
6486 /* POWER9 Specific registers */
6487 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6488 spr_read_generic, spr_write_generic,
6489 KVM_REG_PPC_TIDR, 0);
6490 /* env variables */
6491 env->dcache_line_size = 128;
6492 env->icache_line_size = 128;
6493
6494 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2);
6495
6496 /* Allocate hardware IRQ controller */
6497 init_excp_POWER9(env);
6498 ppcPOWER9_irq_init(env_archcpu(env));
6499 }
6500
ppc_pvr_match_power9(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6501 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6502 {
6503 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6504 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6505
6506 if (!best) {
6507 if (base == CPU_POWERPC_POWER9_BASE) {
6508 return true;
6509 }
6510 }
6511
6512 if (base != pcc_base) {
6513 return false;
6514 }
6515
6516 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) {
6517 /* Major DD version does not match */
6518 return false;
6519 }
6520
6521 if ((pvr & 0x0f00) == 0x200) {
6522 if ((pvr & 0xf) < 2) {
6523 /* DD2.0, DD2.1 match power9_v2.0 */
6524 if ((pcc->pvr & 0xf) == 0) {
6525 return true;
6526 }
6527 } else {
6528 /* DD2.2, DD2.3 match power9_v2.2 */
6529 if ((pcc->pvr & 0xf) == 2) {
6530 return true;
6531 }
6532 }
6533 }
6534
6535 return false;
6536 }
6537
POWERPC_FAMILY(POWER9)6538 POWERPC_FAMILY(POWER9)(ObjectClass *oc, const void *data)
6539 {
6540 DeviceClass *dc = DEVICE_CLASS(oc);
6541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6542
6543 dc->fw_name = "PowerPC,POWER9";
6544 dc->desc = "POWER9";
6545 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00;
6546 pcc->pvr_match = ppc_pvr_match_power9;
6547 pcc->pcr_mask = PPC_PCR_MASK_POWER9;
6548 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9;
6549 pcc->init_proc = init_proc_POWER9;
6550 pcc->check_pow = check_pow_nocheck;
6551 pcc->check_attn = check_attn_hid0_power9;
6552 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9;
6553 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9;
6554 pcc->msr_mask = PPC_MSR_MASK_POWER9;
6555 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9;
6556 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6557 pcc->mmu_model = POWERPC_MMU_3_00;
6558 #if !defined(CONFIG_USER_ONLY)
6559 /* segment page size remain the same */
6560 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6561 pcc->radix_page_info = &POWER9_radix_page_info;
6562 pcc->lrg_decr_bits = 56;
6563 pcc->n_host_threads = 4;
6564 #endif
6565 pcc->excp_model = POWERPC_EXCP_POWER9;
6566 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6567 pcc->bfd_mach = bfd_mach_ppc64;
6568 pcc->flags = POWERPC_FLAGS_POWER9;
6569 pcc->l1_dcache_size = 0x8000;
6570 pcc->l1_icache_size = 0x8000;
6571 }
6572
6573 #ifndef CONFIG_USER_ONLY
6574 /*
6575 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6576 * Encoded as array of int_32s in the form:
6577 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6578 * x -> AP encoding
6579 * y -> radix mode supported page size (encoded as a shift)
6580 */
6581 static struct ppc_radix_page_info POWER10_radix_page_info = {
6582 .count = 4,
6583 .entries = {
6584 0x0000000c, /* 4K - enc: 0x0 */
6585 0xa0000010, /* 64K - enc: 0x5 */
6586 0x20000015, /* 2M - enc: 0x1 */
6587 0x4000001e /* 1G - enc: 0x2 */
6588 }
6589 };
6590 #endif /* !CONFIG_USER_ONLY */
6591
6592 #define POWER10_BHRB_ENTRIES_LOG2 5
init_proc_POWER10(CPUPPCState * env)6593 static void init_proc_POWER10(CPUPPCState *env)
6594 {
6595 register_power9_common_sprs(env);
6596 register_HEIR64_spr(env);
6597 register_book3s_310_dbg_sprs(env);
6598 register_power10_hash_sprs(env);
6599 register_power10_dexcr_sprs(env);
6600 register_power10_pmu_sup_sprs(env);
6601 register_power10_pmu_user_sprs(env);
6602 /* env variables */
6603 env->dcache_line_size = 128;
6604 env->icache_line_size = 128;
6605
6606 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2);
6607
6608 /* Allocate hardware IRQ controller */
6609 init_excp_POWER10(env);
6610 ppcPOWER9_irq_init(env_archcpu(env));
6611 }
6612
ppc_pvr_match_power10(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6613 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6614 {
6615 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6616 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6617
6618 if (!best) {
6619 if (base == CPU_POWERPC_POWER10_BASE) {
6620 return true;
6621 }
6622 }
6623
6624 if (base != pcc_base) {
6625 return false;
6626 }
6627
6628 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6629 /* Major DD version matches power10_v2.0 */
6630 return true;
6631 }
6632
6633 return false;
6634 }
6635
POWERPC_FAMILY(POWER10)6636 POWERPC_FAMILY(POWER10)(ObjectClass *oc, const void *data)
6637 {
6638 DeviceClass *dc = DEVICE_CLASS(oc);
6639 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6640
6641 dc->fw_name = "PowerPC,POWER10";
6642 dc->desc = "POWER10";
6643 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10;
6644 pcc->pvr_match = ppc_pvr_match_power10;
6645 pcc->pcr_mask = PPC_PCR_MASK_POWER10;
6646 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10;
6647 pcc->init_proc = init_proc_POWER10;
6648 pcc->check_pow = check_pow_nocheck;
6649 pcc->check_attn = check_attn_hid0_power9;
6650 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10;
6651 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10;
6652 pcc->msr_mask = PPC_MSR_MASK_POWER10;
6653 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10;
6654
6655 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6656 pcc->mmu_model = POWERPC_MMU_3_00;
6657 #if !defined(CONFIG_USER_ONLY)
6658 /* segment page size remain the same */
6659 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6660 pcc->radix_page_info = &POWER10_radix_page_info;
6661 pcc->lrg_decr_bits = 56;
6662 #endif
6663 pcc->excp_model = POWERPC_EXCP_POWER10;
6664 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6665 pcc->bfd_mach = bfd_mach_ppc64;
6666 pcc->flags = POWERPC_FLAGS_POWER10;
6667 pcc->l1_dcache_size = 0x8000;
6668 pcc->l1_icache_size = 0x8000;
6669 }
6670
init_proc_POWER11(CPUPPCState * env)6671 static void init_proc_POWER11(CPUPPCState *env)
6672 {
6673 init_proc_POWER10(env);
6674 }
6675
ppc_pvr_match_power11(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6676 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6677 {
6678 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6679 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6680
6681 if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
6682 return true;
6683 }
6684
6685 if (base != pcc_base) {
6686 return false;
6687 }
6688
6689 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6690 return true;
6691 }
6692
6693 return false;
6694 }
6695
POWERPC_FAMILY(POWER11)6696 POWERPC_FAMILY(POWER11)(ObjectClass *oc, const void *data)
6697 {
6698 DeviceClass *dc = DEVICE_CLASS(oc);
6699 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6700
6701 dc->fw_name = "PowerPC,POWER11";
6702 dc->desc = "POWER11";
6703 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11;
6704 pcc->pvr_match = ppc_pvr_match_power11;
6705 pcc->pcr_mask = PPC_PCR_MASK_POWER11;
6706 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11;
6707 pcc->init_proc = init_proc_POWER11;
6708 pcc->check_pow = check_pow_nocheck;
6709 pcc->check_attn = check_attn_hid0_power9;
6710 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11;
6711 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11;
6712 pcc->msr_mask = PPC_MSR_MASK_POWER11;
6713 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11;
6714
6715 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6716 pcc->mmu_model = POWERPC_MMU_3_00;
6717 #if !defined(CONFIG_USER_ONLY)
6718 /* segment page size remain the same */
6719 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6720 pcc->radix_page_info = &POWER10_radix_page_info;
6721 pcc->lrg_decr_bits = 56;
6722 #endif
6723 pcc->excp_model = POWERPC_EXCP_POWER11;
6724 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6725 pcc->bfd_mach = bfd_mach_ppc64;
6726 pcc->flags = POWERPC_FLAGS_POWER11;
6727 pcc->l1_dcache_size = 0x8000;
6728 pcc->l1_icache_size = 0x8000;
6729 }
6730
6731 #if !defined(CONFIG_USER_ONLY)
cpu_ppc_set_vhyp(PowerPCCPU * cpu,PPCVirtualHypervisor * vhyp)6732 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6733 {
6734 CPUPPCState *env = &cpu->env;
6735
6736 cpu->vhyp = vhyp;
6737 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp);
6738
6739 /*
6740 * With a virtual hypervisor mode we never allow the CPU to go
6741 * hypervisor mode itself
6742 */
6743 env->msr_mask &= ~MSR_HVB;
6744 }
6745
cpu_ppc_set_1lpar(PowerPCCPU * cpu)6746 void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
6747 {
6748 CPUPPCState *env = &cpu->env;
6749
6750 /*
6751 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6752 * between threads. powernv be in either mode, and it mostly affects
6753 * supervisor visible registers and instructions.
6754 */
6755 if (env->flags & POWERPC_FLAG_SMT) {
6756 env->flags |= POWERPC_FLAG_SMT_1LPAR;
6757 }
6758 }
6759 #endif /* !defined(CONFIG_USER_ONLY) */
6760
6761 #endif /* defined(TARGET_PPC64) */
6762
6763 /*****************************************************************************/
6764 /* Generic CPU instantiation routine */
init_ppc_proc(PowerPCCPU * cpu)6765 static void init_ppc_proc(PowerPCCPU *cpu)
6766 {
6767 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6768 CPUPPCState *env = &cpu->env;
6769 #if !defined(CONFIG_USER_ONLY)
6770 int i;
6771
6772 /* Set all exception vectors to an invalid address */
6773 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6774 env->excp_vectors[i] = (target_ulong)(-1ULL);
6775 }
6776 env->ivor_mask = 0x00000000;
6777 env->ivpr_mask = 0x00000000;
6778 /* Default MMU definitions */
6779 env->nb_BATs = 0;
6780 env->nb_tlb = 0;
6781 env->nb_ways = 0;
6782 env->tlb_type = TLB_NONE;
6783 #endif
6784 /* Register SPR common to all PowerPC implementations */
6785 register_generic_sprs(cpu);
6786
6787 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6788 (*pcc->init_proc)(env);
6789
6790 /* MSR bits & flags consistency checks */
6791 if (env->msr_mask & (1 << 25)) {
6792 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE |
6793 POWERPC_FLAG_PPE42)) {
6794 case POWERPC_FLAG_SPE:
6795 case POWERPC_FLAG_VRE:
6796 case POWERPC_FLAG_PPE42:
6797 break;
6798 default:
6799 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6800 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"
6801 "or POWERPC_FLAG_PPE42\n");
6802 exit(1);
6803 }
6804 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE |
6805 POWERPC_FLAG_PPE42)) {
6806 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6807 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"
6808 "nor POWERPC_FLAG_PPE42\n");
6809 exit(1);
6810 }
6811 if (env->msr_mask & (1 << 17)) {
6812 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE |
6813 POWERPC_FLAG_PPE42)) {
6814 case POWERPC_FLAG_TGPR:
6815 case POWERPC_FLAG_CE:
6816 case POWERPC_FLAG_PPE42:
6817 break;
6818 default:
6819 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6820 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"
6821 "or POWERPC_FLAG_PPE42\n");
6822 exit(1);
6823 }
6824 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE |
6825 POWERPC_FLAG_PPE42)) {
6826 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6827 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"
6828 "nor POWERPC_FLAG_PPE42\n");
6829 exit(1);
6830 }
6831 if (env->msr_mask & (1 << 10)) {
6832 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6833 POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) {
6834 case POWERPC_FLAG_SE:
6835 case POWERPC_FLAG_DWE:
6836 case POWERPC_FLAG_UBLE:
6837 case POWERPC_FLAG_PPE42:
6838 break;
6839 default:
6840 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6841 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6842 "POWERPC_FLAG_UBLE or POWERPC_FLAG_PPE42\n");
6843 exit(1);
6844 }
6845 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6846 POWERPC_FLAG_UBLE | POWERPC_FLAG_PPE42)) {
6847 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6848 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6849 "POWERPC_FLAG_UBLE nor POWERPC_FLAG_PPE42\n");
6850 exit(1);
6851 }
6852 if (env->msr_mask & (1 << 9)) {
6853 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6854 case POWERPC_FLAG_BE:
6855 case POWERPC_FLAG_DE:
6856 break;
6857 default:
6858 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6859 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6860 exit(1);
6861 }
6862 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6863 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6864 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6865 exit(1);
6866 }
6867 if (env->msr_mask & (1 << 2)) {
6868 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM |
6869 POWERPC_FLAG_PPE42)) {
6870 case POWERPC_FLAG_PX:
6871 case POWERPC_FLAG_PMM:
6872 case POWERPC_FLAG_PPE42:
6873 break;
6874 default:
6875 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6876 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"
6877 "or POWERPC_FLAG_PPE42\n");
6878 exit(1);
6879 }
6880 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM |
6881 POWERPC_FLAG_PPE42)) {
6882 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6883 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"
6884 "nor POWERPC_FLAG_PPE42\n");
6885 exit(1);
6886 }
6887 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6888 fprintf(stderr, "PowerPC flags inconsistency\n"
6889 "Should define the time-base and decrementer clock source\n");
6890 exit(1);
6891 }
6892 /* Allocate TLBs buffer when needed */
6893 #if !defined(CONFIG_USER_ONLY)
6894 if (env->nb_tlb) {
6895 switch (env->tlb_type) {
6896 case TLB_6XX:
6897 /* 6xx has separate TLBs for instructions and data hence times 2 */
6898 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
6899 break;
6900 case TLB_EMB:
6901 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
6902 break;
6903 case TLB_MAS:
6904 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
6905 break;
6906 }
6907 /* Pre-compute some useful values */
6908 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6909 }
6910 #endif
6911 if (env->check_pow == NULL) {
6912 warn_report("no power management check handler registered."
6913 " Attempt QEMU to crash very soon !");
6914 }
6915
6916 if (env->check_attn == NULL) {
6917 warn_report("no attn check handler registered."
6918 " Attempt QEMU to crash very soon !");
6919 }
6920 }
6921
6922
ppc_cpu_realize(DeviceState * dev,Error ** errp)6923 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6924 {
6925 CPUState *cs = CPU(dev);
6926 PowerPCCPU *cpu = POWERPC_CPU(dev);
6927 CPUPPCState *env = &cpu->env;
6928 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6929 Error *local_err = NULL;
6930
6931 cpu_exec_realizefn(cs, &local_err);
6932 if (local_err != NULL) {
6933 error_propagate(errp, local_err);
6934 return;
6935 }
6936 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6937 cpu->vcpu_id = cs->cpu_index;
6938 }
6939
6940 if (tcg_enabled()) {
6941 if (ppc_fixup_cpu(cpu) != 0) {
6942 error_setg(errp, "Unable to emulate selected CPU with TCG");
6943 goto unrealize;
6944 }
6945 }
6946
6947 create_ppc_opcodes(cpu, &local_err);
6948 if (local_err != NULL) {
6949 error_propagate(errp, local_err);
6950 goto unrealize;
6951 }
6952 init_ppc_proc(cpu);
6953
6954 ppc_gdb_init(cs, pcc);
6955 qemu_init_vcpu(cs);
6956
6957 pcc->parent_realize(dev, errp);
6958
6959 if (!ppc_cpu_core_single_threaded(cs)) {
6960 env->flags |= POWERPC_FLAG_SMT;
6961 }
6962
6963 return;
6964
6965 unrealize:
6966 cpu_exec_unrealizefn(cs);
6967 }
6968
ppc_cpu_unrealize(DeviceState * dev)6969 static void ppc_cpu_unrealize(DeviceState *dev)
6970 {
6971 PowerPCCPU *cpu = POWERPC_CPU(dev);
6972 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6973
6974 pcc->parent_unrealize(dev);
6975
6976 cpu_remove_sync(CPU(cpu));
6977
6978 destroy_ppc_opcodes(cpu);
6979 }
6980
ppc_cpu_compare_class_pvr(gconstpointer a,gconstpointer b)6981 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6982 {
6983 ObjectClass *oc = (ObjectClass *)a;
6984 uint32_t pvr = *(uint32_t *)b;
6985 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6986
6987 /* -cpu host does a PVR lookup during construction */
6988 if (unlikely(strcmp(object_class_get_name(oc),
6989 TYPE_HOST_POWERPC_CPU) == 0)) {
6990 return -1;
6991 }
6992
6993 return pcc->pvr == pvr ? 0 : -1;
6994 }
6995
ppc_cpu_class_by_pvr(uint32_t pvr)6996 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6997 {
6998 GSList *list, *item;
6999 PowerPCCPUClass *pcc = NULL;
7000
7001 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7002 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7003 if (item != NULL) {
7004 pcc = POWERPC_CPU_CLASS(item->data);
7005 }
7006 g_slist_free(list);
7007
7008 return pcc;
7009 }
7010
ppc_cpu_compare_class_pvr_mask(gconstpointer a,gconstpointer b)7011 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7012 {
7013 ObjectClass *oc = (ObjectClass *)a;
7014 uint32_t pvr = *(uint32_t *)b;
7015 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7016
7017 /* -cpu host does a PVR lookup during construction */
7018 if (unlikely(strcmp(object_class_get_name(oc),
7019 TYPE_HOST_POWERPC_CPU) == 0)) {
7020 return -1;
7021 }
7022
7023 if (pcc->pvr_match(pcc, pvr, true)) {
7024 return 0;
7025 }
7026
7027 return -1;
7028 }
7029
ppc_cpu_class_by_pvr_mask(uint32_t pvr)7030 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7031 {
7032 GSList *list, *item;
7033 PowerPCCPUClass *pcc = NULL;
7034
7035 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7036 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7037 if (item != NULL) {
7038 pcc = POWERPC_CPU_CLASS(item->data);
7039 }
7040 g_slist_free(list);
7041
7042 return pcc;
7043 }
7044
ppc_cpu_lookup_alias(const char * alias)7045 static const char *ppc_cpu_lookup_alias(const char *alias)
7046 {
7047 int ai;
7048
7049 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7050 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7051 return ppc_cpu_aliases[ai].model;
7052 }
7053 }
7054
7055 return NULL;
7056 }
7057
ppc_cpu_class_by_name(const char * name)7058 ObjectClass *ppc_cpu_class_by_name(const char *name)
7059 {
7060 char *cpu_model, *typename;
7061 ObjectClass *oc;
7062 const char *p;
7063 unsigned long pvr;
7064
7065 /*
7066 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7067 * 0x prefix if present)
7068 */
7069 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7070 int len = p - name;
7071 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7072 if ((len == 8) && (*p == '\0')) {
7073 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7074 }
7075 }
7076
7077 /*
7078 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
7079 * do not have a "max" CPU with all possible emulated features enabled.
7080 * Return the default CPU type for the machine because that has greater
7081 * chance of being useful as the "max" CPU.
7082 */
7083 #if !defined(CONFIG_USER_ONLY)
7084 if (strcmp(name, "max") == 0) {
7085 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
7086 if (mc) {
7087 return object_class_by_name(machine_class_default_cpu_type(mc));
7088 }
7089 }
7090 #endif
7091
7092 cpu_model = g_ascii_strdown(name, -1);
7093 p = ppc_cpu_lookup_alias(cpu_model);
7094 if (p) {
7095 g_free(cpu_model);
7096 cpu_model = g_strdup(p);
7097 }
7098
7099 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7100 oc = object_class_by_name(typename);
7101 g_free(typename);
7102 g_free(cpu_model);
7103
7104 return oc;
7105 }
7106
ppc_cpu_get_family_class(PowerPCCPUClass * pcc)7107 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7108 {
7109 ObjectClass *oc = OBJECT_CLASS(pcc);
7110
7111 while (oc && !object_class_is_abstract(oc)) {
7112 oc = object_class_get_parent(oc);
7113 }
7114 assert(oc);
7115
7116 return POWERPC_CPU_CLASS(oc);
7117 }
7118
7119 /* Sort by PVR, ordering special case "host" last. */
ppc_cpu_list_compare(gconstpointer a,gconstpointer b,gpointer d)7120 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d)
7121 {
7122 ObjectClass *oc_a = (ObjectClass *)a;
7123 ObjectClass *oc_b = (ObjectClass *)b;
7124 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7125 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7126 const char *name_a = object_class_get_name(oc_a);
7127 const char *name_b = object_class_get_name(oc_b);
7128
7129 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7130 return 1;
7131 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7132 return -1;
7133 } else {
7134 /* Avoid an integer overflow during subtraction */
7135 if (pcc_a->pvr < pcc_b->pvr) {
7136 return -1;
7137 } else if (pcc_a->pvr > pcc_b->pvr) {
7138 return 1;
7139 } else {
7140 return 0;
7141 }
7142 }
7143 }
7144
ppc_cpu_list_entry(gpointer data,gpointer user_data)7145 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7146 {
7147 ObjectClass *oc = data;
7148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7149 CPUClass *cc = CPU_CLASS(oc);
7150 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7151 const char *typename = object_class_get_name(oc);
7152 char *name;
7153 int i;
7154
7155 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7156 return;
7157 }
7158
7159 name = cpu_model_from_type(typename);
7160 if (cc->deprecation_note) {
7161 qemu_printf(" %-16s PVR %08x (deprecated)\n", name, pcc->pvr);
7162 } else {
7163 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr);
7164 }
7165 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7166 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7167 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7168
7169 if (alias_oc != oc) {
7170 continue;
7171 }
7172 /*
7173 * If running with KVM, we might update the family alias later, so
7174 * avoid printing the wrong alias here and use "preferred" instead
7175 */
7176 if (strcmp(alias->alias, family->desc) == 0) {
7177 qemu_printf(" %-16s (alias for preferred %s CPU)\n",
7178 alias->alias, family->desc);
7179 } else {
7180 qemu_printf(" %-16s (alias for %s)\n",
7181 alias->alias, name);
7182 }
7183 }
7184 g_free(name);
7185 }
7186
ppc_cpu_list(void)7187 static void ppc_cpu_list(void)
7188 {
7189 GSList *list;
7190
7191 qemu_printf("Available CPUs:\n");
7192 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7193 list = g_slist_sort_with_data(list, ppc_cpu_list_compare, NULL);
7194 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7195 g_slist_free(list);
7196
7197 #ifdef CONFIG_KVM
7198 qemu_printf("\n");
7199 qemu_printf(" %s\n", "host");
7200 #endif
7201 }
7202
ppc_cpu_set_pc(CPUState * cs,vaddr value)7203 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7204 {
7205 PowerPCCPU *cpu = POWERPC_CPU(cs);
7206
7207 cpu->env.nip = value;
7208 }
7209
ppc_cpu_get_pc(CPUState * cs)7210 static vaddr ppc_cpu_get_pc(CPUState *cs)
7211 {
7212 PowerPCCPU *cpu = POWERPC_CPU(cs);
7213
7214 return cpu->env.nip;
7215 }
7216
7217 #ifdef CONFIG_TCG
ppc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)7218 static void ppc_restore_state_to_opc(CPUState *cs,
7219 const TranslationBlock *tb,
7220 const uint64_t *data)
7221 {
7222 PowerPCCPU *cpu = POWERPC_CPU(cs);
7223
7224 cpu->env.nip = data[0];
7225 }
7226
ppc_cpu_mmu_index(CPUState * cs,bool ifetch)7227 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
7228 {
7229 return ppc_env_mmu_index(cpu_env(cs), ifetch);
7230 }
7231 #endif /* CONFIG_TCG */
7232
7233 #ifndef CONFIG_USER_ONLY
ppc_cpu_has_work(CPUState * cs)7234 static bool ppc_cpu_has_work(CPUState *cs)
7235 {
7236 return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
7237 }
7238 #endif /* !CONFIG_USER_ONLY */
7239
ppc_cpu_reset_hold(Object * obj,ResetType type)7240 static void ppc_cpu_reset_hold(Object *obj, ResetType type)
7241 {
7242 CPUState *cs = CPU(obj);
7243 PowerPCCPU *cpu = POWERPC_CPU(cs);
7244 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
7245 CPUPPCState *env = &cpu->env;
7246 target_ulong msr;
7247 int i;
7248
7249 if (pcc->parent_phases.hold) {
7250 pcc->parent_phases.hold(obj, type);
7251 }
7252
7253 msr = (target_ulong)0;
7254 if (!(env->flags & POWERPC_FLAG_PPE42)) {
7255 msr |= (target_ulong)MSR_HVB;
7256 msr |= (target_ulong)1 << MSR_EP;
7257 #if defined(DO_SINGLE_STEP) && 0
7258 /* Single step trace mode */
7259 msr |= (target_ulong)1 << MSR_SE;
7260 msr |= (target_ulong)1 << MSR_BE;
7261 #endif
7262 #if defined(CONFIG_USER_ONLY)
7263 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7264 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7265 msr |= (target_ulong)1 << MSR_FE1;
7266 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7267 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7268 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7269 msr |= (target_ulong)1 << MSR_PR;
7270 #if defined(TARGET_PPC64)
7271 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7272 #endif
7273 #if !TARGET_BIG_ENDIAN
7274 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7275 if (!((env->msr_mask >> MSR_LE) & 1)) {
7276 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7277 exit(1);
7278 }
7279 #endif
7280 #endif
7281
7282 #if defined(TARGET_PPC64)
7283 if (mmu_is_64bit(env->mmu_model)) {
7284 msr |= (1ULL << MSR_SF);
7285 }
7286 #endif
7287 }
7288 hreg_store_msr(env, msr, 1);
7289
7290 #if !defined(CONFIG_USER_ONLY)
7291 env->nip = env->hreset_vector | env->excp_prefix;
7292
7293 if (tcg_enabled()) {
7294 cpu_breakpoint_remove_all(cs, BP_CPU);
7295 cpu_watchpoint_remove_all(cs, BP_CPU);
7296 if (env->mmu_model != POWERPC_MMU_REAL) {
7297 ppc_tlb_invalidate_all(env);
7298 }
7299 pmu_mmcr01a_updated(env);
7300 }
7301
7302 /* clean any pending stop state */
7303 env->resume_as_sreset = 0;
7304 #endif
7305 hreg_compute_hflags(env);
7306 env->reserve_addr = (target_ulong)-1ULL;
7307 /* Be sure no exception or interrupt is pending */
7308 env->pending_interrupts = 0;
7309 cs->exception_index = POWERPC_EXCP_NONE;
7310 env->error_code = 0;
7311 ppc_irq_reset(cpu);
7312
7313 /* tininess for underflow is detected before rounding */
7314 set_float_detect_tininess(float_tininess_before_rounding,
7315 &env->fp_status);
7316 /* Similarly for flush-to-zero */
7317 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
7318
7319 /*
7320 * PowerPC propagation rules:
7321 * 1. A if it sNaN or qNaN
7322 * 2. B if it sNaN or qNaN
7323 * A signaling NaN is always silenced before returning it.
7324 */
7325 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
7326 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
7327 /*
7328 * NaN propagation for fused multiply-add:
7329 * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
7330 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
7331 * whereas QEMU labels the operands as (a * b) + c.
7332 */
7333 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
7334 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
7335 /*
7336 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
7337 * to return an input NaN if we have one (ie c) rather than generating
7338 * a default NaN
7339 */
7340 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
7341 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
7342
7343 /* Default NaN: sign bit clear, set frac msb */
7344 set_float_default_nan_pattern(0b01000000, &env->fp_status);
7345 set_float_default_nan_pattern(0b01000000, &env->vec_status);
7346
7347 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7348 ppc_spr_t *spr = &env->spr_cb[i];
7349
7350 if (!spr->name) {
7351 continue;
7352 }
7353 env->spr[i] = spr->default_value;
7354 }
7355
7356 #if defined(TARGET_PPC64)
7357 bhrb_reset_state(env);
7358 #endif
7359 }
7360
7361 #ifndef CONFIG_USER_ONLY
7362
ppc_cpu_is_big_endian(CPUState * cs)7363 static bool ppc_cpu_is_big_endian(CPUState *cs)
7364 {
7365 cpu_synchronize_state(cs);
7366
7367 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
7368 }
7369
ppc_get_irq_stats(InterruptStatsProvider * obj,uint64_t ** irq_counts,unsigned int * nb_irqs)7370 static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
7371 uint64_t **irq_counts, unsigned int *nb_irqs)
7372 {
7373 CPUPPCState *env = &POWERPC_CPU(obj)->env;
7374
7375 *irq_counts = env->excp_stats;
7376 *nb_irqs = ARRAY_SIZE(env->excp_stats);
7377 return true;
7378 }
7379
7380 #ifdef CONFIG_TCG
ppc_cpu_exec_enter(CPUState * cs)7381 static void ppc_cpu_exec_enter(CPUState *cs)
7382 {
7383 PowerPCCPU *cpu = POWERPC_CPU(cs);
7384
7385 if (cpu->vhyp) {
7386 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu);
7387 }
7388 }
7389
ppc_cpu_exec_exit(CPUState * cs)7390 static void ppc_cpu_exec_exit(CPUState *cs)
7391 {
7392 PowerPCCPU *cpu = POWERPC_CPU(cs);
7393
7394 if (cpu->vhyp) {
7395 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
7396 }
7397 }
7398
ppc_pointer_wrap(CPUState * cs,int mmu_idx,vaddr result,vaddr base)7399 static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx,
7400 vaddr result, vaddr base)
7401 {
7402 return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result;
7403 }
7404 #endif /* CONFIG_TCG */
7405
7406 #endif /* !CONFIG_USER_ONLY */
7407
ppc_cpu_instance_init(Object * obj)7408 static void ppc_cpu_instance_init(Object *obj)
7409 {
7410 PowerPCCPU *cpu = POWERPC_CPU(obj);
7411 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7412 CPUPPCState *env = &cpu->env;
7413
7414 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7415
7416 env->msr_mask = pcc->msr_mask;
7417 env->mmu_model = pcc->mmu_model;
7418 env->excp_model = pcc->excp_model;
7419 env->bus_model = pcc->bus_model;
7420 env->insns_flags = pcc->insns_flags;
7421 env->insns_flags2 = pcc->insns_flags2;
7422 env->flags = pcc->flags;
7423 env->bfd_mach = pcc->bfd_mach;
7424 env->check_pow = pcc->check_pow;
7425 env->check_attn = pcc->check_attn;
7426
7427 /*
7428 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7429 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7430 * mode support will remain, thus enforcing that we cannot use
7431 * priv. instructions in guest in PAPR mode. For 970 we currently
7432 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7433 * 970. If we ever want to support 970 HV mode, we'll have to add
7434 * a processor attribute of some sort.
7435 */
7436 #if !defined(CONFIG_USER_ONLY)
7437 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7438 #endif
7439
7440 ppc_hash64_init(cpu);
7441 }
7442
ppc_cpu_instance_finalize(Object * obj)7443 static void ppc_cpu_instance_finalize(Object *obj)
7444 {
7445 PowerPCCPU *cpu = POWERPC_CPU(obj);
7446
7447 ppc_hash64_finalize(cpu);
7448 }
7449
ppc_pvr_match_default(PowerPCCPUClass * pcc,uint32_t pvr,bool best)7450 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7451 {
7452 return pcc->pvr == pvr;
7453 }
7454
ppc_disas_set_info(CPUState * cs,disassemble_info * info)7455 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7456 {
7457 CPUPPCState *env = cpu_env(cs);
7458
7459 if ((env->hflags >> MSR_LE) & 1) {
7460 info->endian = BFD_ENDIAN_LITTLE;
7461 } else {
7462 info->endian = BFD_ENDIAN_BIG;
7463 }
7464 info->mach = env->bfd_mach;
7465 if (!env->bfd_mach) {
7466 #ifdef TARGET_PPC64
7467 info->mach = bfd_mach_ppc64;
7468 #else
7469 info->mach = bfd_mach_ppc;
7470 #endif
7471 }
7472
7473 info->cap_arch = CS_ARCH_PPC;
7474 #ifdef TARGET_PPC64
7475 info->cap_mode = CS_MODE_64;
7476 #endif
7477 }
7478
7479 #ifndef CONFIG_USER_ONLY
7480 #include "hw/core/sysemu-cpu-ops.h"
7481
7482 static const struct SysemuCPUOps ppc_sysemu_ops = {
7483 .has_work = ppc_cpu_has_work,
7484 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7485 .write_elf32_note = ppc32_cpu_write_elf32_note,
7486 .write_elf64_note = ppc64_cpu_write_elf64_note,
7487 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7488 .legacy_vmsd = &vmstate_ppc_cpu,
7489 };
7490 #endif
7491
7492 #ifdef CONFIG_TCG
7493 #include "accel/tcg/cpu-ops.h"
7494
7495 static const TCGCPUOps ppc_tcg_ops = {
7496 .mttcg_supported = TARGET_LONG_BITS == 64,
7497 .guest_default_memory_order = 0,
7498 .initialize = ppc_translate_init,
7499 .translate_code = ppc_translate_code,
7500 .get_tb_cpu_state = ppc_get_tb_cpu_state,
7501 .restore_state_to_opc = ppc_restore_state_to_opc,
7502 .mmu_index = ppc_cpu_mmu_index,
7503
7504 #ifdef CONFIG_USER_ONLY
7505 .record_sigsegv = ppc_cpu_record_sigsegv,
7506 #else
7507 .tlb_fill = ppc_cpu_tlb_fill,
7508 .pointer_wrap = ppc_pointer_wrap,
7509 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7510 .cpu_exec_halt = ppc_cpu_has_work,
7511 .cpu_exec_reset = cpu_reset,
7512 .do_interrupt = ppc_cpu_do_interrupt,
7513 .cpu_exec_enter = ppc_cpu_exec_enter,
7514 .cpu_exec_exit = ppc_cpu_exec_exit,
7515 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7516 .do_transaction_failed = ppc_cpu_do_transaction_failed,
7517 .debug_excp_handler = ppc_cpu_debug_excp_handler,
7518 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
7519 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
7520 #endif /* !CONFIG_USER_ONLY */
7521 };
7522 #endif /* CONFIG_TCG */
7523
ppc_cpu_class_init(ObjectClass * oc,const void * data)7524 static void ppc_cpu_class_init(ObjectClass *oc, const void *data)
7525 {
7526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7527 CPUClass *cc = CPU_CLASS(oc);
7528 DeviceClass *dc = DEVICE_CLASS(oc);
7529 ResettableClass *rc = RESETTABLE_CLASS(oc);
7530
7531 device_class_set_parent_realize(dc, ppc_cpu_realize,
7532 &pcc->parent_realize);
7533 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7534 &pcc->parent_unrealize);
7535 pcc->pvr_match = ppc_pvr_match_default;
7536
7537 device_class_set_props(dc, powerpc_cpu_properties);
7538
7539 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7540 &pcc->parent_phases);
7541
7542 cc->class_by_name = ppc_cpu_class_by_name;
7543 cc->list_cpus = ppc_cpu_list;
7544 cc->dump_state = ppc_cpu_dump_state;
7545 cc->set_pc = ppc_cpu_set_pc;
7546 cc->get_pc = ppc_cpu_get_pc;
7547 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7548 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7549 #ifndef CONFIG_USER_ONLY
7550 cc->sysemu_ops = &ppc_sysemu_ops;
7551 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
7552
7553 /* check_prot_access_type relies on MMU access and PAGE bits relations */
7554 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 &&
7555 MMU_INST_FETCH == 2 && PAGE_READ == 1 &&
7556 PAGE_WRITE == 2 && PAGE_EXEC == 4);
7557 #endif
7558
7559 cc->gdb_num_core_regs = 71;
7560 #ifdef USE_APPLE_GDB
7561 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7562 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7563 cc->gdb_num_core_regs = 71 + 32;
7564 #endif
7565
7566 cc->gdb_arch_name = ppc_gdb_arch_name;
7567 #if defined(TARGET_PPC64)
7568 cc->gdb_core_xml_file = "power64-core.xml";
7569 #else
7570 cc->gdb_core_xml_file = "power-core.xml";
7571 #endif
7572 cc->disas_set_info = ppc_disas_set_info;
7573
7574 dc->fw_name = "PowerPC,UNKNOWN";
7575
7576 #ifdef CONFIG_TCG
7577 cc->tcg_ops = &ppc_tcg_ops;
7578 #endif /* CONFIG_TCG */
7579 }
7580
7581 static const TypeInfo ppc_cpu_type_info = {
7582 .name = TYPE_POWERPC_CPU,
7583 .parent = TYPE_CPU,
7584 .instance_size = sizeof(PowerPCCPU),
7585 .instance_align = __alignof__(PowerPCCPU),
7586 .instance_init = ppc_cpu_instance_init,
7587 .instance_finalize = ppc_cpu_instance_finalize,
7588 .abstract = true,
7589 .class_size = sizeof(PowerPCCPUClass),
7590 .class_init = ppc_cpu_class_init,
7591 #ifndef CONFIG_USER_ONLY
7592 .interfaces = (const InterfaceInfo[]) {
7593 { TYPE_INTERRUPT_STATS_PROVIDER },
7594 { }
7595 },
7596 #endif
7597 };
7598
7599 #ifndef CONFIG_USER_ONLY
7600 static const TypeInfo ppc_vhyp_type_info = {
7601 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7602 .parent = TYPE_INTERFACE,
7603 .class_size = sizeof(PPCVirtualHypervisorClass),
7604 };
7605 #endif
7606
ppc_cpu_register_types(void)7607 static void ppc_cpu_register_types(void)
7608 {
7609 type_register_static(&ppc_cpu_type_info);
7610 #ifndef CONFIG_USER_ONLY
7611 type_register_static(&ppc_vhyp_type_info);
7612 #endif
7613 }
7614
ppc_cpu_dump_state(CPUState * cs,FILE * f,int flags)7615 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7616 {
7617 #define RGPL 4
7618 #define RFPL 4
7619
7620 CPUPPCState *env = cpu_env(cs);
7621 int i;
7622
7623 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7624 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7625 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7626 cs->cpu_index);
7627 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7628 "%08x iidx %d didx %d\n",
7629 env->msr, env->spr[SPR_HID0], env->hflags,
7630 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
7631 #if !defined(CONFIG_USER_ONLY)
7632 if (env->tb_env) {
7633 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7634 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7635 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7636 }
7637 #else
7638 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7639 cpu_ppc_load_tbl(env));
7640 #endif
7641 for (i = 0; i < 32; i++) {
7642 if ((i & (RGPL - 1)) == 0) {
7643 qemu_fprintf(f, "GPR%02d", i);
7644 }
7645 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7646 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7647 qemu_fprintf(f, "\n");
7648 }
7649 }
7650 qemu_fprintf(f, "CR ");
7651 for (i = 0; i < 8; i++)
7652 qemu_fprintf(f, "%01x", env->crf[i]);
7653 qemu_fprintf(f, " [");
7654 for (i = 0; i < 8; i++) {
7655 char a = '-';
7656 if (env->crf[i] & 0x08) {
7657 a = 'L';
7658 } else if (env->crf[i] & 0x04) {
7659 a = 'G';
7660 } else if (env->crf[i] & 0x02) {
7661 a = 'E';
7662 }
7663 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7664 }
7665 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n",
7666 (int)env->reserve_length, env->reserve_addr);
7667
7668 if (flags & CPU_DUMP_FPU) {
7669 for (i = 0; i < 32; i++) {
7670 if ((i & (RFPL - 1)) == 0) {
7671 qemu_fprintf(f, "FPR%02d", i);
7672 }
7673 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7674 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7675 qemu_fprintf(f, "\n");
7676 }
7677 }
7678 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7679 }
7680
7681 #if !defined(CONFIG_USER_ONLY)
7682 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7683 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7684 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7685 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7686
7687 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7688 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7689 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7690 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7691
7692 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7693 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7694 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7695 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7696
7697 switch (env->excp_model) {
7698 #if defined(TARGET_PPC64)
7699 case POWERPC_EXCP_POWER7:
7700 case POWERPC_EXCP_POWER8:
7701 case POWERPC_EXCP_POWER9:
7702 case POWERPC_EXCP_POWER10:
7703 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7704 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7705 break;
7706 #endif
7707 case POWERPC_EXCP_BOOKE:
7708 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7709 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7710 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7711 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7712
7713 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7714 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7715 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7716 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7717
7718 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7719 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7720 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7721 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7722
7723 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7724 " EPR " TARGET_FMT_lx "\n",
7725 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7726 env->spr[SPR_BOOKE_EPR]);
7727
7728 /* FSL-specific */
7729 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7730 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7731 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7732 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7733
7734 /*
7735 * IVORs are left out as they are large and do not change often --
7736 * they can be read with "p $ivor0", "p $ivor1", etc.
7737 */
7738 break;
7739 case POWERPC_EXCP_PPE42:
7740 qemu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx "\n",
7741 env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
7742
7743 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7744 " ISR " TARGET_FMT_lx " EDR " TARGET_FMT_lx "\n",
7745 env->spr[SPR_PPE42_TCR], env->spr[SPR_PPE42_TSR],
7746 env->spr[SPR_PPE42_ISR], env->spr[SPR_PPE42_EDR]);
7747
7748 qemu_fprintf(f, " PIR " TARGET_FMT_lx " IVPR " TARGET_FMT_lx "\n",
7749 env->spr[SPR_PPE42_PIR], env->spr[SPR_PPE42_IVPR]);
7750 break;
7751 case POWERPC_EXCP_40x:
7752 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7753 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7754 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7755 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7756
7757 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7758 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7759 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7760 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7761 break;
7762 default:
7763 break;
7764 }
7765
7766 #if defined(TARGET_PPC64)
7767 if (env->flags & POWERPC_FLAG_CFAR) {
7768 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7769 }
7770 #endif
7771
7772 if (env->spr_cb[SPR_LPCR].name) {
7773 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7774 }
7775
7776 switch (env->mmu_model) {
7777 case POWERPC_MMU_32B:
7778 case POWERPC_MMU_SOFT_6xx:
7779 #if defined(TARGET_PPC64)
7780 case POWERPC_MMU_64B:
7781 case POWERPC_MMU_2_03:
7782 case POWERPC_MMU_2_06:
7783 case POWERPC_MMU_2_07:
7784 case POWERPC_MMU_3_00:
7785 #endif
7786 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7787 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7788 }
7789 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7790 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7791 }
7792 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7793 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7794 break;
7795 case POWERPC_MMU_BOOKE206:
7796 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7797 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7798 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7799 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7800
7801 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7802 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7803 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7804 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7805
7806 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7807 " TLB1CFG " TARGET_FMT_lx "\n",
7808 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7809 env->spr[SPR_BOOKE_TLB1CFG]);
7810 break;
7811 default:
7812 break;
7813 }
7814 #endif
7815
7816 #undef RGPL
7817 #undef RFPL
7818 }
7819 type_init(ppc_cpu_register_types)
7820