1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6 /dts-v1/; 7 #include "sparx5_pcb_common.dtsi" 8 9 /{ 10 gpio-restart { 11 compatible = "gpio-restart"; 12 gpios = <&gpio 37 GPIO_ACTIVE_LOW>; 13 priority = <200>; 14 }; 15 16 leds { 17 compatible = "gpio-leds"; 18 led@0 { 19 label = "twr0:green"; 20 gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; 21 }; 22 led@1 { 23 label = "twr0:yellow"; 24 gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; 25 }; 26 led@2 { 27 label = "twr1:green"; 28 gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; 29 }; 30 led@3 { 31 label = "twr1:yellow"; 32 gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; 33 }; 34 led@4 { 35 label = "twr2:green"; 36 gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; 37 }; 38 led@5 { 39 label = "twr2:yellow"; 40 gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; 41 }; 42 led@6 { 43 label = "twr3:green"; 44 gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; 45 }; 46 led@7 { 47 label = "twr3:yellow"; 48 gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; 49 }; 50 led@8 { 51 label = "eth12:green"; 52 gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; 53 default-state = "off"; 54 }; 55 led@9 { 56 label = "eth12:yellow"; 57 gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; 58 default-state = "off"; 59 }; 60 led@10 { 61 label = "eth13:green"; 62 gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; 63 default-state = "off"; 64 }; 65 led@11 { 66 label = "eth13:yellow"; 67 gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; 68 default-state = "off"; 69 }; 70 led@12 { 71 label = "eth14:green"; 72 gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; 73 default-state = "off"; 74 }; 75 led@13 { 76 label = "eth14:yellow"; 77 gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; 78 default-state = "off"; 79 }; 80 led@14 { 81 label = "eth15:green"; 82 gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; 83 default-state = "off"; 84 }; 85 led@15 { 86 label = "eth15:yellow"; 87 gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; 88 default-state = "off"; 89 }; 90 led@16 { 91 label = "eth48:green"; 92 gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; 93 default-state = "off"; 94 }; 95 led@17 { 96 label = "eth48:yellow"; 97 gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; 98 default-state = "off"; 99 }; 100 led@18 { 101 label = "eth49:green"; 102 gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; 103 default-state = "off"; 104 }; 105 led@19 { 106 label = "eth49:yellow"; 107 gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; 108 default-state = "off"; 109 }; 110 led@20 { 111 label = "eth50:green"; 112 gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; 113 default-state = "off"; 114 }; 115 led@21 { 116 label = "eth50:yellow"; 117 gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; 118 default-state = "off"; 119 }; 120 led@22 { 121 label = "eth51:green"; 122 gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 led@23 { 126 label = "eth51:yellow"; 127 gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; 128 default-state = "off"; 129 }; 130 led@24 { 131 label = "eth52:green"; 132 gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; 133 default-state = "off"; 134 }; 135 led@25 { 136 label = "eth52:yellow"; 137 gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; 138 default-state = "off"; 139 }; 140 led@26 { 141 label = "eth53:green"; 142 gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; 143 default-state = "off"; 144 }; 145 led@27 { 146 label = "eth53:yellow"; 147 gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; 148 default-state = "off"; 149 }; 150 led@28 { 151 label = "eth54:green"; 152 gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; 153 default-state = "off"; 154 }; 155 led@29 { 156 label = "eth54:yellow"; 157 gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; 158 default-state = "off"; 159 }; 160 led@30 { 161 label = "eth55:green"; 162 gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 led@31 { 166 label = "eth55:yellow"; 167 gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; 168 default-state = "off"; 169 }; 170 led@32 { 171 label = "eth56:green"; 172 gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; 173 default-state = "off"; 174 }; 175 led@33 { 176 label = "eth56:yellow"; 177 gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; 178 default-state = "off"; 179 }; 180 led@34 { 181 label = "eth57:green"; 182 gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; 183 default-state = "off"; 184 }; 185 led@35 { 186 label = "eth57:yellow"; 187 gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; 188 default-state = "off"; 189 }; 190 led@36 { 191 label = "eth58:green"; 192 gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; 193 default-state = "off"; 194 }; 195 led@37 { 196 label = "eth58:yellow"; 197 gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; 198 default-state = "off"; 199 }; 200 led@38 { 201 label = "eth59:green"; 202 gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; 203 default-state = "off"; 204 }; 205 led@39 { 206 label = "eth59:yellow"; 207 gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; 208 default-state = "off"; 209 }; 210 led@40 { 211 label = "eth60:green"; 212 gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; 213 default-state = "off"; 214 }; 215 led@41 { 216 label = "eth60:yellow"; 217 gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; 218 default-state = "off"; 219 }; 220 led@42 { 221 label = "eth61:green"; 222 gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; 223 default-state = "off"; 224 }; 225 led@43 { 226 label = "eth61:yellow"; 227 gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; 228 default-state = "off"; 229 }; 230 led@44 { 231 label = "eth62:green"; 232 gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; 233 default-state = "off"; 234 }; 235 led@45 { 236 label = "eth62:yellow"; 237 gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; 238 default-state = "off"; 239 }; 240 led@46 { 241 label = "eth63:green"; 242 gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; 243 default-state = "off"; 244 }; 245 led@47 { 246 label = "eth63:yellow"; 247 gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; 248 default-state = "off"; 249 }; 250 }; 251 }; 252 253 &sgpio0 { 254 status = "okay"; 255 microchip,sgpio-port-ranges = <8 15>; 256 gpio@0 { 257 ngpios = <64>; 258 }; 259 gpio@1 { 260 ngpios = <64>; 261 }; 262 }; 263 264 &sgpio1 { 265 status = "okay"; 266 microchip,sgpio-port-ranges = <24 31>; 267 gpio@0 { 268 ngpios = <64>; 269 }; 270 gpio@1 { 271 ngpios = <64>; 272 }; 273 }; 274 275 &spi0 { 276 status = "okay"; 277 flash@0 { 278 compatible = "jedec,spi-nor"; 279 spi-max-frequency = <8000000>; 280 reg = <0>; 281 }; 282 }; 283 284 &spi0 { 285 status = "okay"; 286 spi@0 { 287 compatible = "spi-mux"; 288 mux-controls = <&mux>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0>; /* CS0 */ 292 flash@9 { 293 compatible = "jedec,spi-nor"; 294 spi-max-frequency = <8000000>; 295 reg = <0x9>; /* SPI */ 296 }; 297 }; 298 }; 299 300 &sgpio0 { 301 status = "okay"; 302 microchip,sgpio-port-ranges = <8 15>; 303 gpio@0 { 304 ngpios = <64>; 305 }; 306 gpio@1 { 307 ngpios = <64>; 308 }; 309 }; 310 311 &sgpio1 { 312 status = "okay"; 313 microchip,sgpio-port-ranges = <24 31>; 314 gpio@0 { 315 ngpios = <64>; 316 }; 317 gpio@1 { 318 ngpios = <64>; 319 }; 320 }; 321 322 &sgpio2 { 323 status = "okay"; 324 microchip,sgpio-port-ranges = <0 0>, <11 31>; 325 }; 326 327 &gpio { 328 i2cmux_pins_i: i2cmux-pins { 329 pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", 330 "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", 331 "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; 332 function = "twi_scl_m"; 333 output-low; 334 }; 335 i2cmux_0: i2cmux-0-pins { 336 pins = "GPIO_16"; 337 function = "twi_scl_m"; 338 output-high; 339 }; 340 i2cmux_1: i2cmux-1-pins { 341 pins = "GPIO_17"; 342 function = "twi_scl_m"; 343 output-high; 344 }; 345 i2cmux_2: i2cmux-2-pins { 346 pins = "GPIO_18"; 347 function = "twi_scl_m"; 348 output-high; 349 }; 350 i2cmux_3: i2cmux-3-pins { 351 pins = "GPIO_19"; 352 function = "twi_scl_m"; 353 output-high; 354 }; 355 i2cmux_4: i2cmux-4-pins { 356 pins = "GPIO_20"; 357 function = "twi_scl_m"; 358 output-high; 359 }; 360 i2cmux_5: i2cmux-5-pins { 361 pins = "GPIO_22"; 362 function = "twi_scl_m"; 363 output-high; 364 }; 365 i2cmux_6: i2cmux-6-pins { 366 pins = "GPIO_36"; 367 function = "twi_scl_m"; 368 output-high; 369 }; 370 i2cmux_7: i2cmux-7-pins { 371 pins = "GPIO_35"; 372 function = "twi_scl_m"; 373 output-high; 374 }; 375 i2cmux_8: i2cmux-8-pins { 376 pins = "GPIO_50"; 377 function = "twi_scl_m"; 378 output-high; 379 }; 380 i2cmux_9: i2cmux-9-pins { 381 pins = "GPIO_51"; 382 function = "twi_scl_m"; 383 output-high; 384 }; 385 i2cmux_10: i2cmux-10-pins { 386 pins = "GPIO_56"; 387 function = "twi_scl_m"; 388 output-high; 389 }; 390 i2cmux_11: i2cmux-11-pins { 391 pins = "GPIO_57"; 392 function = "twi_scl_m"; 393 output-high; 394 }; 395 }; 396 397 &axi { 398 i2c0_imux: i2c0-imux@0 { 399 compatible = "i2c-mux-pinctrl"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 i2c-parent = <&i2c0>; 403 }; 404 i2c0_emux: i2c0-emux@0 { 405 compatible = "i2c-mux-gpio"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 i2c-parent = <&i2c0>; 409 }; 410 }; 411 412 &i2c0_imux { 413 pinctrl-names = 414 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", 415 "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8", 416 "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle"; 417 pinctrl-0 = <&i2cmux_0>; 418 pinctrl-1 = <&i2cmux_1>; 419 pinctrl-2 = <&i2cmux_2>; 420 pinctrl-3 = <&i2cmux_3>; 421 pinctrl-4 = <&i2cmux_4>; 422 pinctrl-5 = <&i2cmux_5>; 423 pinctrl-6 = <&i2cmux_6>; 424 pinctrl-7 = <&i2cmux_7>; 425 pinctrl-8 = <&i2cmux_8>; 426 pinctrl-9 = <&i2cmux_9>; 427 pinctrl-10 = <&i2cmux_10>; 428 pinctrl-11 = <&i2cmux_11>; 429 pinctrl-12 = <&i2cmux_pins_i>; 430 i2c_sfp1: i2c_sfp1 { 431 reg = <0x0>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 }; 435 i2c_sfp2: i2c_sfp2 { 436 reg = <0x1>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 }; 440 i2c_sfp3: i2c_sfp3 { 441 reg = <0x2>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 i2c_sfp4: i2c_sfp4 { 446 reg = <0x3>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 }; 450 i2c_sfp5: i2c_sfp5 { 451 reg = <0x4>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 }; 455 i2c_sfp6: i2c_sfp6 { 456 reg = <0x5>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 }; 460 i2c_sfp7: i2c_sfp7 { 461 reg = <0x6>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 }; 465 i2c_sfp8: i2c_sfp8 { 466 reg = <0x7>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 i2c_sfp9: i2c_sfp9 { 471 reg = <0x8>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 i2c_sfp10: i2c_sfp10 { 476 reg = <0x9>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 }; 480 i2c_sfp11: i2c_sfp11 { 481 reg = <0xa>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 }; 485 i2c_sfp12: i2c_sfp12 { 486 reg = <0xb>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 }; 491 492 &i2c0_emux { 493 mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH 494 &gpio 60 GPIO_ACTIVE_HIGH 495 &gpio 61 GPIO_ACTIVE_HIGH 496 &gpio 54 GPIO_ACTIVE_HIGH>; 497 idle-state = <0x8>; 498 i2c_sfp13: i2c_sfp13 { 499 reg = <0x0>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 }; 503 i2c_sfp14: i2c_sfp14 { 504 reg = <0x1>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 }; 508 i2c_sfp15: i2c_sfp15 { 509 reg = <0x2>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 }; 513 i2c_sfp16: i2c_sfp16 { 514 reg = <0x3>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 }; 518 i2c_sfp17: i2c_sfp17 { 519 reg = <0x4>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 }; 523 i2c_sfp18: i2c_sfp18 { 524 reg = <0x5>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 }; 528 i2c_sfp19: i2c_sfp19 { 529 reg = <0x6>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 }; 533 i2c_sfp20: i2c_sfp20 { 534 reg = <0x7>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 }; 539 540 &mdio3 { 541 status = "okay"; 542 phy64: ethernet-phy@64 { 543 reg = <28>; 544 }; 545 }; 546 547 &axi { 548 sfp_eth12: sfp-eth12 { 549 compatible = "sff,sfp"; 550 i2c-bus = <&i2c_sfp1>; 551 tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; 552 los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; 553 mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; 554 tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; 555 }; 556 sfp_eth13: sfp-eth13 { 557 compatible = "sff,sfp"; 558 i2c-bus = <&i2c_sfp2>; 559 tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; 560 los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; 561 mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; 562 tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; 563 }; 564 sfp_eth14: sfp-eth14 { 565 compatible = "sff,sfp"; 566 i2c-bus = <&i2c_sfp3>; 567 tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; 568 los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; 569 mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; 570 tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; 571 }; 572 sfp_eth15: sfp-eth15 { 573 compatible = "sff,sfp"; 574 i2c-bus = <&i2c_sfp4>; 575 tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; 576 los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; 577 mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; 578 tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; 579 }; 580 sfp_eth48: sfp-eth48 { 581 compatible = "sff,sfp"; 582 i2c-bus = <&i2c_sfp5>; 583 tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; 584 los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; 585 mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; 586 tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; 587 }; 588 sfp_eth49: sfp-eth49 { 589 compatible = "sff,sfp"; 590 i2c-bus = <&i2c_sfp6>; 591 tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; 592 los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; 593 mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; 594 tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; 595 }; 596 sfp_eth50: sfp-eth50 { 597 compatible = "sff,sfp"; 598 i2c-bus = <&i2c_sfp7>; 599 tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; 600 los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; 601 mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; 602 tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; 603 }; 604 sfp_eth51: sfp-eth51 { 605 compatible = "sff,sfp"; 606 i2c-bus = <&i2c_sfp8>; 607 tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; 608 los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; 609 mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; 610 tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; 611 }; 612 sfp_eth52: sfp-eth52 { 613 compatible = "sff,sfp"; 614 i2c-bus = <&i2c_sfp9>; 615 tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; 616 los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; 617 mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; 618 tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; 619 }; 620 sfp_eth53: sfp-eth53 { 621 compatible = "sff,sfp"; 622 i2c-bus = <&i2c_sfp10>; 623 tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; 624 los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; 625 mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; 626 tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; 627 }; 628 sfp_eth54: sfp-eth54 { 629 compatible = "sff,sfp"; 630 i2c-bus = <&i2c_sfp11>; 631 tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; 632 los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; 633 mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; 634 tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; 635 }; 636 sfp_eth55: sfp-eth55 { 637 compatible = "sff,sfp"; 638 i2c-bus = <&i2c_sfp12>; 639 tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; 640 los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; 641 mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; 642 tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; 643 }; 644 sfp_eth56: sfp-eth56 { 645 compatible = "sff,sfp"; 646 i2c-bus = <&i2c_sfp13>; 647 tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; 648 los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; 649 mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; 650 tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; 651 }; 652 sfp_eth57: sfp-eth57 { 653 compatible = "sff,sfp"; 654 i2c-bus = <&i2c_sfp14>; 655 tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; 656 los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; 657 mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; 658 tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; 659 }; 660 sfp_eth58: sfp-eth58 { 661 compatible = "sff,sfp"; 662 i2c-bus = <&i2c_sfp15>; 663 tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; 664 los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; 665 mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; 666 tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; 667 }; 668 sfp_eth59: sfp-eth59 { 669 compatible = "sff,sfp"; 670 i2c-bus = <&i2c_sfp16>; 671 tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; 672 los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; 673 mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; 674 tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; 675 }; 676 sfp_eth60: sfp-eth60 { 677 compatible = "sff,sfp"; 678 i2c-bus = <&i2c_sfp17>; 679 tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; 680 los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; 681 mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; 682 tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; 683 }; 684 sfp_eth61: sfp-eth61 { 685 compatible = "sff,sfp"; 686 i2c-bus = <&i2c_sfp18>; 687 tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; 688 los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; 689 mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; 690 tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; 691 }; 692 sfp_eth62: sfp-eth62 { 693 compatible = "sff,sfp"; 694 i2c-bus = <&i2c_sfp19>; 695 tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; 696 los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; 697 mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; 698 tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; 699 }; 700 sfp_eth63: sfp-eth63 { 701 compatible = "sff,sfp"; 702 i2c-bus = <&i2c_sfp20>; 703 tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; 704 los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; 705 mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; 706 tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; 707 }; 708 }; 709 710 &switch { 711 ethernet-ports { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 /* 10G SFPs */ 716 port12: port@12 { 717 reg = <12>; 718 microchip,bandwidth = <10000>; 719 phys = <&serdes 13>; 720 phy-mode = "10gbase-r"; 721 sfp = <&sfp_eth12>; 722 microchip,sd-sgpio = <301>; 723 managed = "in-band-status"; 724 }; 725 port13: port@13 { 726 reg = <13>; 727 /* Example: CU SFP, 1G speed */ 728 microchip,bandwidth = <10000>; 729 phys = <&serdes 14>; 730 phy-mode = "10gbase-r"; 731 sfp = <&sfp_eth13>; 732 microchip,sd-sgpio = <305>; 733 managed = "in-band-status"; 734 }; 735 port14: port@14 { 736 reg = <14>; 737 microchip,bandwidth = <10000>; 738 phys = <&serdes 15>; 739 phy-mode = "10gbase-r"; 740 sfp = <&sfp_eth14>; 741 microchip,sd-sgpio = <309>; 742 managed = "in-band-status"; 743 }; 744 port15: port@15 { 745 reg = <15>; 746 microchip,bandwidth = <10000>; 747 phys = <&serdes 16>; 748 phy-mode = "10gbase-r"; 749 sfp = <&sfp_eth15>; 750 microchip,sd-sgpio = <313>; 751 managed = "in-band-status"; 752 }; 753 port48: port@48 { 754 reg = <48>; 755 microchip,bandwidth = <10000>; 756 phys = <&serdes 17>; 757 phy-mode = "10gbase-r"; 758 sfp = <&sfp_eth48>; 759 microchip,sd-sgpio = <317>; 760 managed = "in-band-status"; 761 }; 762 port49: port@49 { 763 reg = <49>; 764 microchip,bandwidth = <10000>; 765 phys = <&serdes 18>; 766 phy-mode = "10gbase-r"; 767 sfp = <&sfp_eth49>; 768 microchip,sd-sgpio = <321>; 769 managed = "in-band-status"; 770 }; 771 port50: port@50 { 772 reg = <50>; 773 microchip,bandwidth = <10000>; 774 phys = <&serdes 19>; 775 phy-mode = "10gbase-r"; 776 sfp = <&sfp_eth50>; 777 microchip,sd-sgpio = <325>; 778 managed = "in-band-status"; 779 }; 780 port51: port@51 { 781 reg = <51>; 782 microchip,bandwidth = <10000>; 783 phys = <&serdes 20>; 784 phy-mode = "10gbase-r"; 785 sfp = <&sfp_eth51>; 786 microchip,sd-sgpio = <329>; 787 managed = "in-band-status"; 788 }; 789 port52: port@52 { 790 reg = <52>; 791 microchip,bandwidth = <10000>; 792 phys = <&serdes 21>; 793 phy-mode = "10gbase-r"; 794 sfp = <&sfp_eth52>; 795 microchip,sd-sgpio = <333>; 796 managed = "in-band-status"; 797 }; 798 port53: port@53 { 799 reg = <53>; 800 microchip,bandwidth = <10000>; 801 phys = <&serdes 22>; 802 phy-mode = "10gbase-r"; 803 sfp = <&sfp_eth53>; 804 microchip,sd-sgpio = <337>; 805 managed = "in-band-status"; 806 }; 807 port54: port@54 { 808 reg = <54>; 809 microchip,bandwidth = <10000>; 810 phys = <&serdes 23>; 811 phy-mode = "10gbase-r"; 812 sfp = <&sfp_eth54>; 813 microchip,sd-sgpio = <341>; 814 managed = "in-band-status"; 815 }; 816 port55: port@55 { 817 reg = <55>; 818 microchip,bandwidth = <10000>; 819 phys = <&serdes 24>; 820 phy-mode = "10gbase-r"; 821 sfp = <&sfp_eth55>; 822 microchip,sd-sgpio = <345>; 823 managed = "in-band-status"; 824 }; 825 /* 25G SFPs */ 826 port56: port@56 { 827 reg = <56>; 828 microchip,bandwidth = <10000>; 829 phys = <&serdes 25>; 830 phy-mode = "10gbase-r"; 831 sfp = <&sfp_eth56>; 832 microchip,sd-sgpio = <349>; 833 managed = "in-band-status"; 834 }; 835 port57: port@57 { 836 reg = <57>; 837 microchip,bandwidth = <10000>; 838 phys = <&serdes 26>; 839 phy-mode = "10gbase-r"; 840 sfp = <&sfp_eth57>; 841 microchip,sd-sgpio = <353>; 842 managed = "in-band-status"; 843 }; 844 port58: port@58 { 845 reg = <58>; 846 microchip,bandwidth = <10000>; 847 phys = <&serdes 27>; 848 phy-mode = "10gbase-r"; 849 sfp = <&sfp_eth58>; 850 microchip,sd-sgpio = <357>; 851 managed = "in-band-status"; 852 }; 853 port59: port@59 { 854 reg = <59>; 855 microchip,bandwidth = <10000>; 856 phys = <&serdes 28>; 857 phy-mode = "10gbase-r"; 858 sfp = <&sfp_eth59>; 859 microchip,sd-sgpio = <361>; 860 managed = "in-band-status"; 861 }; 862 port60: port@60 { 863 reg = <60>; 864 microchip,bandwidth = <10000>; 865 phys = <&serdes 29>; 866 phy-mode = "10gbase-r"; 867 sfp = <&sfp_eth60>; 868 microchip,sd-sgpio = <365>; 869 managed = "in-band-status"; 870 }; 871 port61: port@61 { 872 reg = <61>; 873 microchip,bandwidth = <10000>; 874 phys = <&serdes 30>; 875 phy-mode = "10gbase-r"; 876 sfp = <&sfp_eth61>; 877 microchip,sd-sgpio = <369>; 878 managed = "in-band-status"; 879 }; 880 port62: port@62 { 881 reg = <62>; 882 microchip,bandwidth = <10000>; 883 phys = <&serdes 31>; 884 phy-mode = "10gbase-r"; 885 sfp = <&sfp_eth62>; 886 microchip,sd-sgpio = <373>; 887 managed = "in-band-status"; 888 }; 889 port63: port@63 { 890 reg = <63>; 891 microchip,bandwidth = <10000>; 892 phys = <&serdes 32>; 893 phy-mode = "10gbase-r"; 894 sfp = <&sfp_eth63>; 895 microchip,sd-sgpio = <377>; 896 managed = "in-band-status"; 897 }; 898 /* Finally the Management interface */ 899 port64: port@64 { 900 reg = <64>; 901 microchip,bandwidth = <1000>; 902 phys = <&serdes 0>; 903 phy-handle = <&phy64>; 904 phy-mode = "sgmii"; 905 }; 906 }; 907 }; 908