1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
4 *
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18
19/ {
20	model = "ZynqMP SM-K26 Rev1/B/A";
21	compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
22		     "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
23		     "xlnx,zynqmp";
24
25	aliases {
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		mmc0 = &sdhci0;
29		mmc1 = &sdhci1;
30		nvmem0 = &eeprom;
31		nvmem1 = &eeprom_cc;
32		rtc0 = &rtc;
33		serial0 = &uart0;
34		serial1 = &uart1;
35		serial2 = &dcc;
36		spi0 = &qspi;
37		spi1 = &spi0;
38		spi2 = &spi1;
39		usb0 = &usb0;
40		usb1 = &usb1;
41	};
42
43	chosen {
44		bootargs = "earlycon";
45		stdout-path = "serial1:115200n8";
46	};
47
48	memory@0 {
49		device_type = "memory"; /* 4GB */
50		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
51	};
52
53	reserved-memory {
54		#address-cells = <2>;
55		#size-cells = <2>;
56		ranges;
57
58		pmu_region: pmu@7ff00000 {
59			reg = <0x0 0x7ff00000 0x0 0x100000>;
60			no-map;
61		};
62	};
63
64	gpio-keys {
65		compatible = "gpio-keys";
66		autorepeat;
67		key-fwuen {
68			label = "fwuen";
69			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
70			linux,code = <BTN_MISC>;
71			wakeup-source;
72			autorepeat;
73		};
74	};
75
76	leds {
77		compatible = "gpio-leds";
78		ds35-led {
79			label = "heartbeat";
80			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
81			linux,default-trigger = "heartbeat";
82		};
83
84		ds36-led {
85			label = "vbus_det";
86			gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
87			default-state = "on";
88		};
89	};
90
91	ams {
92		compatible = "iio-hwmon";
93		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
94			<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
95			<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
96			<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
97			<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
98			<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
99			<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
100			<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
101			<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
102			<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
103	};
104};
105
106&modepin_gpio {
107	label = "modepin";
108};
109
110&uart1 { /* MIO36/MIO37 */
111	status = "okay";
112};
113
114&pinctrl0 {
115	status = "okay";
116	pinctrl_sdhci0_default: sdhci0-default {
117		conf {
118			groups = "sdio0_0_grp";
119			slew-rate = <SLEW_RATE_SLOW>;
120			power-source = <IO_STANDARD_LVCMOS18>;
121			bias-disable;
122		};
123
124		mux {
125			groups = "sdio0_0_grp";
126			function = "sdio0";
127		};
128	};
129};
130
131&qspi { /* MIO 0-5 - U143 */
132	status = "okay";
133	spi_flash: flash@0 { /* MT25QU512A */
134		compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
135		#address-cells = <1>;
136		#size-cells = <1>;
137		reg = <0>;
138		spi-tx-bus-width = <4>;
139		spi-rx-bus-width = <4>;
140		spi-max-frequency = <40000000>; /* 40MHz */
141
142		partitions {
143			compatible = "fixed-partitions";
144			#address-cells = <1>;
145			#size-cells = <1>;
146
147			partition@0 {
148				label = "Image Selector";
149				reg = <0x0 0x80000>; /* 512KB */
150				read-only;
151				lock;
152			};
153			partition@80000 {
154				label = "Image Selector Golden";
155				reg = <0x80000 0x80000>; /* 512KB */
156				read-only;
157				lock;
158			};
159			partition@100000 {
160				label = "Persistent Register";
161				reg = <0x100000 0x20000>; /* 128KB */
162			};
163			partition@120000 {
164				label = "Persistent Register Backup";
165				reg = <0x120000 0x20000>; /* 128KB */
166			};
167			partition@140000 {
168				label = "Open_1";
169				reg = <0x140000 0xC0000>; /* 768KB */
170			};
171			partition@200000 {
172				label = "Image A (FSBL, PMU, ATF, U-Boot)";
173				reg = <0x200000 0xD00000>; /* 13MB */
174			};
175			partition@f00000 {
176				label = "ImgSel Image A Catch";
177				reg = <0xF00000 0x80000>; /* 512KB */
178				read-only;
179				lock;
180			};
181			partition@f80000 {
182				label = "Image B (FSBL, PMU, ATF, U-Boot)";
183				reg = <0xF80000 0xD00000>; /* 13MB */
184			};
185			partition@1c80000 {
186				label = "ImgSel Image B Catch";
187				reg = <0x1C80000 0x80000>; /* 512KB */
188				read-only;
189				lock;
190			};
191			partition@1d00000 {
192				label = "Open_2";
193				reg = <0x1D00000 0x100000>; /* 1MB */
194			};
195			partition@1e00000 {
196				label = "Recovery Image";
197				reg = <0x1E00000 0x200000>; /* 2MB */
198				read-only;
199				lock;
200			};
201			partition@2000000 {
202				label = "Recovery Image Backup";
203				reg = <0x2000000 0x200000>; /* 2MB */
204				read-only;
205				lock;
206			};
207			partition@2200000 {
208				label = "U-Boot storage variables";
209				reg = <0x2200000 0x20000>; /* 128KB */
210			};
211			partition@2220000 {
212				label = "U-Boot storage variables backup";
213				reg = <0x2220000 0x20000>; /* 128KB */
214			};
215			partition@2240000 {
216				label = "SHA256";
217				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
218				read-only;
219				lock;
220			};
221			partition@2280000 {
222				label = "Secure OS Storage";
223				reg = <0x2280000 0x20000>; /* 128KB */
224			};
225			partition@22A0000 {
226				label = "User";
227				reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
228			};
229		};
230	};
231};
232
233&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
234	status = "okay";
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_sdhci0_default>;
237	non-removable;
238	disable-wp;
239	bus-width = <8>;
240	xlnx,mio-bank = <0>;
241	assigned-clock-rates = <187498123>;
242};
243
244&spi1 { /* MIO6, 9-11 */
245	status = "okay";
246	label = "TPM";
247	num-cs = <1>;
248	tpm@0 { /* slm9670 - U144 */
249		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
250		reg = <0>;
251		spi-max-frequency = <18500000>;
252	};
253};
254
255&i2c1 {
256	status = "okay";
257	bootph-all;
258	clock-frequency = <400000>;
259	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
260	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
261
262	eeprom: eeprom@50 { /* u46 - also at address 0x58 */
263		bootph-all;
264		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
265		reg = <0x50>;
266		/* WP pin EE_WP_EN connected to slg7x644092@68 */
267	};
268
269	eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
270		bootph-all;
271		compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
272		reg = <0x51>;
273	};
274
275	/* da9062@30 - u170 - also at address 0x31 */
276	/* da9131@33 - u167 */
277	da9131: pmic@33 {
278		compatible = "dlg,da9131";
279		reg = <0x33>;
280		regulators {
281			da9131_buck1: buck1 {
282				regulator-name = "da9131_buck1";
283				regulator-boot-on;
284				regulator-always-on;
285			};
286			da9131_buck2: buck2 {
287				regulator-name = "da9131_buck2";
288				regulator-boot-on;
289				regulator-always-on;
290			};
291		};
292	};
293
294	/* da9130@32 - u166 */
295	da9130: pmic@32 {
296		compatible = "dlg,da9130";
297		reg = <0x32>;
298		regulators {
299			da9130_buck1: buck1 {
300				regulator-name = "da9130_buck1";
301				regulator-boot-on;
302				regulator-always-on;
303			};
304		};
305	};
306
307	/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
308	/*
309	 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
310	 * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
311	 * Address conflict with slg7x644091@70 making both the devices NOT accessible.
312	 * With the FW fix, stdp4320 should respond to address 0x73 only.
313	 */
314	/* slg7x644092@68 - u169 */
315	/* Also connected via JA1C as C23/C24 */
316};
317
318&gpio {
319	status = "okay";
320	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
321			  "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
322			  "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
323			  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
324			  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
325			  "I2C1_SDA", "", "", "", "", /* 25 - 29 */
326			  "", "", "", "", "", /* 30 - 34 */
327			  "", "", "", "", "", /* 35 - 39 */
328			  "", "", "", "", "", /* 40 - 44 */
329			  "", "", "", "", "", /* 45 - 49 */
330			  "", "", "", "", "", /* 50 - 54 */
331			  "", "", "", "", "", /* 55 - 59 */
332			  "", "", "", "", "", /* 60 - 64 */
333			  "", "", "", "", "", /* 65 - 69 */
334			  "", "", "", "", "", /* 70 - 74 */
335			  "", "", "", /* 75 - 77, MIO end and EMIO start */
336			  "", "", /* 78 - 79 */
337			  "", "", "", "", "", /* 80 - 84 */
338			  "", "", "", "", "", /* 85 - 89 */
339			  "", "", "", "", "", /* 90 - 94 */
340			  "", "", "", "", "", /* 95 - 99 */
341			  "", "", "", "", "", /* 100 - 104 */
342			  "", "", "", "", "", /* 105 - 109 */
343			  "", "", "", "", "", /* 110 - 114 */
344			  "", "", "", "", "", /* 115 - 119 */
345			  "", "", "", "", "", /* 120 - 124 */
346			  "", "", "", "", "", /* 125 - 129 */
347			  "", "", "", "", "", /* 130 - 134 */
348			  "", "", "", "", "", /* 135 - 139 */
349			  "", "", "", "", "", /* 140 - 144 */
350			  "", "", "", "", "", /* 145 - 149 */
351			  "", "", "", "", "", /* 150 - 154 */
352			  "", "", "", "", "", /* 155 - 159 */
353			  "", "", "", "", "", /* 160 - 164 */
354			  "", "", "", "", "", /* 165 - 169 */
355			  "", "", "", ""; /* 170 - 173 */
356};
357
358&xilinx_ams {
359	status = "okay";
360};
361
362&ams_ps {
363	status = "okay";
364};
365
366&ams_pl {
367	status = "okay";
368};
369
370&zynqmp_dpsub {
371	status = "okay";
372};
373
374&rtc {
375	status = "okay";
376};
377
378&lpd_dma_chan1 {
379	status = "okay";
380};
381
382&lpd_dma_chan2 {
383	status = "okay";
384};
385
386&lpd_dma_chan3 {
387	status = "okay";
388};
389
390&lpd_dma_chan4 {
391	status = "okay";
392};
393
394&lpd_dma_chan5 {
395	status = "okay";
396};
397
398&lpd_dma_chan6 {
399	status = "okay";
400};
401
402&lpd_dma_chan7 {
403	status = "okay";
404};
405
406&lpd_dma_chan8 {
407	status = "okay";
408};
409
410&fpd_dma_chan1 {
411	status = "okay";
412};
413
414&fpd_dma_chan2 {
415	status = "okay";
416};
417
418&fpd_dma_chan3 {
419	status = "okay";
420};
421
422&fpd_dma_chan4 {
423	status = "okay";
424};
425
426&fpd_dma_chan5 {
427	status = "okay";
428};
429
430&fpd_dma_chan6 {
431	status = "okay";
432};
433
434&fpd_dma_chan7 {
435	status = "okay";
436};
437
438&fpd_dma_chan8 {
439	status = "okay";
440};
441
442&gpu {
443	status = "okay";
444};
445
446&lpd_watchdog {
447	status = "okay";
448};
449
450&watchdog0 {
451	status = "okay";
452};
453
454&cpu_opp_table {
455	opp00 {
456		opp-hz = /bits/ 64 <1333333333>;
457	};
458	opp01 {
459		opp-hz = /bits/ 64 <666666666>;
460	};
461	opp02 {
462		opp-hz = /bits/ 64 <444444444>;
463	};
464	opp03 {
465		opp-hz = /bits/ 64 <333333333>;
466	};
467};
468