1 /* 2 * QEMU RISC-V PMP (Physical Memory Protection) 3 * 4 * Author: Daire McNamara, daire.mcnamara@emdalo.com 5 * Ivan Griffin, ivan.griffin@emdalo.com 6 * 7 * This provides a RISC-V Physical Memory Protection interface 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2 or later, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef RISCV_PMP_H 23 #define RISCV_PMP_H 24 25 #include "cpu.h" 26 27 typedef enum { 28 PMP_READ = 1 << 0, 29 PMP_WRITE = 1 << 1, 30 PMP_EXEC = 1 << 2, 31 PMP_AMATCH = (3 << 3), 32 PMP_LOCK = 1 << 7 33 } pmp_priv_t; 34 35 typedef enum { 36 PMP_AMATCH_OFF, /* Null (off) */ 37 PMP_AMATCH_TOR, /* Top of Range */ 38 PMP_AMATCH_NA4, /* Naturally aligned four-byte region */ 39 PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ 40 } pmp_am_t; 41 42 typedef enum { 43 MSECCFG_MML = 1 << 0, 44 MSECCFG_MMWP = 1 << 1, 45 MSECCFG_RLB = 1 << 2, 46 MSECCFG_USEED = 1 << 8, 47 MSECCFG_SSEED = 1 << 9 48 } mseccfg_field_t; 49 50 typedef struct { 51 target_ulong addr_reg; 52 uint8_t cfg_reg; 53 } pmp_entry_t; 54 55 typedef struct { 56 hwaddr sa; 57 hwaddr ea; 58 } pmp_addr_t; 59 60 typedef struct { 61 pmp_entry_t pmp[MAX_RISCV_PMPS]; 62 pmp_addr_t addr[MAX_RISCV_PMPS]; 63 uint32_t num_rules; 64 } pmp_table_t; 65 66 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, 67 target_ulong val); 68 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); 69 70 void mseccfg_csr_write(CPURISCVState *env, target_ulong val); 71 target_ulong mseccfg_csr_read(CPURISCVState *env); 72 73 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, 74 target_ulong val); 75 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); 76 bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, 77 target_ulong size, pmp_priv_t privs, 78 pmp_priv_t *allowed_privs, 79 target_ulong mode); 80 target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr); 81 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); 82 void pmp_update_rule_nums(CPURISCVState *env); 83 uint32_t pmp_get_num_rules(CPURISCVState *env); 84 int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); 85 void pmp_unlock_entries(CPURISCVState *env); 86 87 #define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML) 88 #define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP) 89 #define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB) 90 91 #endif 92