1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: opp-table-0 { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 }; 214 }; 215 216 gpu_thermal: gpu-thermal { 217 polling-delay-passive = <100>; /* milliseconds */ 218 polling-delay = <1000>; /* milliseconds */ 219 thermal-sensors = <&tsadc 1>; 220 221 trips { 222 gpu_threshold: gpu-threshold { 223 temperature = <70000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 gpu_target: gpu-target { 229 temperature = <85000>; 230 hysteresis = <2000>; 231 type = "passive"; 232 }; 233 234 gpu_crit: gpu-crit { 235 temperature = <115000>; 236 hysteresis = <2000>; 237 type = "critical"; 238 }; 239 }; 240 241 cooling-maps { 242 map0 { 243 trip = <&gpu_target>; 244 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 245 }; 246 }; 247 }; 248 }; 249 250 xin24m: xin24m { 251 compatible = "fixed-clock"; 252 #clock-cells = <0>; 253 clock-frequency = <24000000>; 254 clock-output-names = "xin24m"; 255 }; 256 257 pmu: power-management@ff000000 { 258 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 259 reg = <0x0 0xff000000 0x0 0x1000>; 260 261 power: power-controller { 262 compatible = "rockchip,px30-power-controller"; 263 #power-domain-cells = <1>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 /* These power domains are grouped by VD_LOGIC */ 268 power-domain@PX30_PD_USB { 269 reg = <PX30_PD_USB>; 270 clocks = <&cru HCLK_HOST>, 271 <&cru HCLK_OTG>, 272 <&cru SCLK_OTG_ADP>; 273 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 274 #power-domain-cells = <0>; 275 }; 276 power-domain@PX30_PD_SDCARD { 277 reg = <PX30_PD_SDCARD>; 278 clocks = <&cru HCLK_SDMMC>, 279 <&cru SCLK_SDMMC>; 280 pm_qos = <&qos_sdmmc>; 281 #power-domain-cells = <0>; 282 }; 283 power-domain@PX30_PD_GMAC { 284 reg = <PX30_PD_GMAC>; 285 clocks = <&cru ACLK_GMAC>, 286 <&cru PCLK_GMAC>, 287 <&cru SCLK_MAC_REF>, 288 <&cru SCLK_GMAC_RX_TX>; 289 pm_qos = <&qos_gmac>; 290 #power-domain-cells = <0>; 291 }; 292 power-domain@PX30_PD_MMC_NAND { 293 reg = <PX30_PD_MMC_NAND>; 294 clocks = <&cru HCLK_NANDC>, 295 <&cru HCLK_EMMC>, 296 <&cru HCLK_SDIO>, 297 <&cru HCLK_SFC>, 298 <&cru SCLK_EMMC>, 299 <&cru SCLK_NANDC>, 300 <&cru SCLK_SDIO>, 301 <&cru SCLK_SFC>; 302 pm_qos = <&qos_emmc>, <&qos_nand>, 303 <&qos_sdio>, <&qos_sfc>; 304 #power-domain-cells = <0>; 305 }; 306 power-domain@PX30_PD_VPU { 307 reg = <PX30_PD_VPU>; 308 clocks = <&cru ACLK_VPU>, 309 <&cru HCLK_VPU>, 310 <&cru SCLK_CORE_VPU>; 311 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 312 #power-domain-cells = <0>; 313 }; 314 power-domain@PX30_PD_VO { 315 reg = <PX30_PD_VO>; 316 clocks = <&cru ACLK_RGA>, 317 <&cru ACLK_VOPB>, 318 <&cru ACLK_VOPL>, 319 <&cru DCLK_VOPB>, 320 <&cru DCLK_VOPL>, 321 <&cru HCLK_RGA>, 322 <&cru HCLK_VOPB>, 323 <&cru HCLK_VOPL>, 324 <&cru PCLK_MIPI_DSI>, 325 <&cru SCLK_RGA_CORE>, 326 <&cru SCLK_VOPB_PWM>; 327 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 328 <&qos_vop_m0>, <&qos_vop_m1>; 329 #power-domain-cells = <0>; 330 }; 331 power-domain@PX30_PD_VI { 332 reg = <PX30_PD_VI>; 333 clocks = <&cru ACLK_CIF>, 334 <&cru ACLK_ISP>, 335 <&cru HCLK_CIF>, 336 <&cru HCLK_ISP>, 337 <&cru SCLK_ISP>; 338 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 339 <&qos_isp_wr>, <&qos_isp_m1>, 340 <&qos_vip>; 341 #power-domain-cells = <0>; 342 }; 343 power-domain@PX30_PD_GPU { 344 reg = <PX30_PD_GPU>; 345 clocks = <&cru SCLK_GPU>; 346 pm_qos = <&qos_gpu>; 347 #power-domain-cells = <0>; 348 }; 349 }; 350 }; 351 352 pmugrf: syscon@ff010000 { 353 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 354 reg = <0x0 0xff010000 0x0 0x1000>; 355 #address-cells = <1>; 356 #size-cells = <1>; 357 358 pmu_io_domains: io-domains { 359 compatible = "rockchip,px30-pmu-io-voltage-domain"; 360 status = "disabled"; 361 }; 362 363 reboot-mode { 364 compatible = "syscon-reboot-mode"; 365 offset = <0x200>; 366 mode-bootloader = <BOOT_BL_DOWNLOAD>; 367 mode-fastboot = <BOOT_FASTBOOT>; 368 mode-loader = <BOOT_BL_DOWNLOAD>; 369 mode-normal = <BOOT_NORMAL>; 370 mode-recovery = <BOOT_RECOVERY>; 371 }; 372 }; 373 374 uart0: serial@ff030000 { 375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff030000 0x0 0x100>; 377 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 379 clock-names = "baudclk", "apb_pclk"; 380 dmas = <&dmac 0>, <&dmac 1>; 381 dma-names = "tx", "rx"; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 386 status = "disabled"; 387 }; 388 389 i2s0_8ch: i2s@ff060000 { 390 compatible = "rockchip,px30-i2s-tdm"; 391 reg = <0x0 0xff060000 0x0 0x1000>; 392 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; 394 clock-names = "mclk_tx", "mclk_rx", "hclk"; 395 dmas = <&dmac 16>, <&dmac 17>; 396 dma-names = "tx", "rx"; 397 rockchip,grf = <&grf>; 398 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 399 reset-names = "tx-m", "rx-m"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx 402 &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx 403 &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 404 &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 405 &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 406 &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; 407 #sound-dai-cells = <0>; 408 status = "disabled"; 409 }; 410 411 i2s1_2ch: i2s@ff070000 { 412 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 413 reg = <0x0 0xff070000 0x0 0x1000>; 414 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 416 clock-names = "i2s_clk", "i2s_hclk"; 417 dmas = <&dmac 18>, <&dmac 19>; 418 dma-names = "tx", "rx"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 421 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 422 #sound-dai-cells = <0>; 423 status = "disabled"; 424 }; 425 426 i2s2_2ch: i2s@ff080000 { 427 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 428 reg = <0x0 0xff080000 0x0 0x1000>; 429 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 431 clock-names = "i2s_clk", "i2s_hclk"; 432 dmas = <&dmac 20>, <&dmac 21>; 433 dma-names = "tx", "rx"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 436 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 437 #sound-dai-cells = <0>; 438 status = "disabled"; 439 }; 440 441 gic: interrupt-controller@ff131000 { 442 compatible = "arm,gic-400"; 443 #interrupt-cells = <3>; 444 #address-cells = <0>; 445 interrupt-controller; 446 reg = <0x0 0xff131000 0 0x1000>, 447 <0x0 0xff132000 0 0x2000>, 448 <0x0 0xff134000 0 0x2000>, 449 <0x0 0xff136000 0 0x2000>; 450 interrupts = <GIC_PPI 9 451 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 452 }; 453 454 grf: syscon@ff140000 { 455 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 456 reg = <0x0 0xff140000 0x0 0x1000>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 460 io_domains: io-domains { 461 compatible = "rockchip,px30-io-voltage-domain"; 462 status = "disabled"; 463 }; 464 465 lvds: lvds { 466 compatible = "rockchip,px30-lvds"; 467 phys = <&dsi_dphy>; 468 phy-names = "dphy"; 469 rockchip,grf = <&grf>; 470 rockchip,output = "lvds"; 471 status = "disabled"; 472 473 ports { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 lvds_in: port@0 { 478 reg = <0>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 482 lvds_vopb_in: endpoint@0 { 483 reg = <0>; 484 remote-endpoint = <&vopb_out_lvds>; 485 }; 486 487 lvds_vopl_in: endpoint@1 { 488 reg = <1>; 489 remote-endpoint = <&vopl_out_lvds>; 490 }; 491 }; 492 493 lvds_out: port@1 { 494 reg = <1>; 495 }; 496 }; 497 }; 498 }; 499 500 uart1: serial@ff158000 { 501 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 502 reg = <0x0 0xff158000 0x0 0x100>; 503 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 505 clock-names = "baudclk", "apb_pclk"; 506 dmas = <&dmac 2>, <&dmac 3>; 507 dma-names = "tx", "rx"; 508 reg-shift = <2>; 509 reg-io-width = <4>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 512 status = "disabled"; 513 }; 514 515 uart2: serial@ff160000 { 516 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 517 reg = <0x0 0xff160000 0x0 0x100>; 518 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 520 clock-names = "baudclk", "apb_pclk"; 521 dmas = <&dmac 4>, <&dmac 5>; 522 dma-names = "tx", "rx"; 523 reg-shift = <2>; 524 reg-io-width = <4>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&uart2m0_xfer>; 527 status = "disabled"; 528 }; 529 530 uart3: serial@ff168000 { 531 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 532 reg = <0x0 0xff168000 0x0 0x100>; 533 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 535 clock-names = "baudclk", "apb_pclk"; 536 dmas = <&dmac 6>, <&dmac 7>; 537 dma-names = "tx", "rx"; 538 reg-shift = <2>; 539 reg-io-width = <4>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 542 status = "disabled"; 543 }; 544 545 uart4: serial@ff170000 { 546 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 547 reg = <0x0 0xff170000 0x0 0x100>; 548 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 550 clock-names = "baudclk", "apb_pclk"; 551 dmas = <&dmac 8>, <&dmac 9>; 552 dma-names = "tx", "rx"; 553 reg-shift = <2>; 554 reg-io-width = <4>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 557 status = "disabled"; 558 }; 559 560 uart5: serial@ff178000 { 561 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 562 reg = <0x0 0xff178000 0x0 0x100>; 563 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 565 clock-names = "baudclk", "apb_pclk"; 566 dmas = <&dmac 10>, <&dmac 11>; 567 dma-names = "tx", "rx"; 568 reg-shift = <2>; 569 reg-io-width = <4>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 572 status = "disabled"; 573 }; 574 575 i2c0: i2c@ff180000 { 576 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 577 reg = <0x0 0xff180000 0x0 0x1000>; 578 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 579 clock-names = "i2c", "pclk"; 580 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&i2c0_xfer>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c1: i2c@ff190000 { 589 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 590 reg = <0x0 0xff190000 0x0 0x1000>; 591 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 592 clock-names = "i2c", "pclk"; 593 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&i2c1_xfer>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 i2c2: i2c@ff1a0000 { 602 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 603 reg = <0x0 0xff1a0000 0x0 0x1000>; 604 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 605 clock-names = "i2c", "pclk"; 606 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&i2c2_xfer>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 i2c3: i2c@ff1b0000 { 615 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 616 reg = <0x0 0xff1b0000 0x0 0x1000>; 617 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 618 clock-names = "i2c", "pclk"; 619 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&i2c3_xfer>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 spi0: spi@ff1d0000 { 628 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 629 reg = <0x0 0xff1d0000 0x0 0x1000>; 630 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 632 clock-names = "spiclk", "apb_pclk"; 633 dmas = <&dmac 12>, <&dmac 13>; 634 dma-names = "tx", "rx"; 635 num-cs = <2>; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 spi1: spi@ff1d8000 { 644 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 645 reg = <0x0 0xff1d8000 0x0 0x1000>; 646 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 648 clock-names = "spiclk", "apb_pclk"; 649 dmas = <&dmac 14>, <&dmac 15>; 650 dma-names = "tx", "rx"; 651 num-cs = <2>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 status = "disabled"; 657 }; 658 659 wdt: watchdog@ff1e0000 { 660 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 661 reg = <0x0 0xff1e0000 0x0 0x100>; 662 clocks = <&cru PCLK_WDT_NS>; 663 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 664 status = "disabled"; 665 }; 666 667 pwm0: pwm@ff200000 { 668 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 669 reg = <0x0 0xff200000 0x0 0x10>; 670 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 671 clock-names = "pwm", "pclk"; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pwm0_pin>; 674 #pwm-cells = <3>; 675 status = "disabled"; 676 }; 677 678 pwm1: pwm@ff200010 { 679 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 680 reg = <0x0 0xff200010 0x0 0x10>; 681 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 682 clock-names = "pwm", "pclk"; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pwm1_pin>; 685 #pwm-cells = <3>; 686 status = "disabled"; 687 }; 688 689 pwm2: pwm@ff200020 { 690 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 691 reg = <0x0 0xff200020 0x0 0x10>; 692 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 693 clock-names = "pwm", "pclk"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&pwm2_pin>; 696 #pwm-cells = <3>; 697 status = "disabled"; 698 }; 699 700 pwm3: pwm@ff200030 { 701 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 702 reg = <0x0 0xff200030 0x0 0x10>; 703 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 704 clock-names = "pwm", "pclk"; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pwm3_pin>; 707 #pwm-cells = <3>; 708 status = "disabled"; 709 }; 710 711 pwm4: pwm@ff208000 { 712 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 713 reg = <0x0 0xff208000 0x0 0x10>; 714 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 715 clock-names = "pwm", "pclk"; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pwm4_pin>; 718 #pwm-cells = <3>; 719 status = "disabled"; 720 }; 721 722 pwm5: pwm@ff208010 { 723 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 724 reg = <0x0 0xff208010 0x0 0x10>; 725 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 726 clock-names = "pwm", "pclk"; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&pwm5_pin>; 729 #pwm-cells = <3>; 730 status = "disabled"; 731 }; 732 733 pwm6: pwm@ff208020 { 734 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 735 reg = <0x0 0xff208020 0x0 0x10>; 736 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 737 clock-names = "pwm", "pclk"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pwm6_pin>; 740 #pwm-cells = <3>; 741 status = "disabled"; 742 }; 743 744 pwm7: pwm@ff208030 { 745 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 746 reg = <0x0 0xff208030 0x0 0x10>; 747 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 748 clock-names = "pwm", "pclk"; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&pwm7_pin>; 751 #pwm-cells = <3>; 752 status = "disabled"; 753 }; 754 755 rktimer: timer@ff210000 { 756 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 757 reg = <0x0 0xff210000 0x0 0x1000>; 758 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 760 clock-names = "pclk", "timer"; 761 }; 762 763 dmac: dma-controller@ff240000 { 764 compatible = "arm,pl330", "arm,primecell"; 765 reg = <0x0 0xff240000 0x0 0x4000>; 766 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 768 arm,pl330-periph-burst; 769 clocks = <&cru ACLK_DMAC>; 770 clock-names = "apb_pclk"; 771 #dma-cells = <1>; 772 }; 773 774 tsadc: tsadc@ff280000 { 775 compatible = "rockchip,px30-tsadc"; 776 reg = <0x0 0xff280000 0x0 0x100>; 777 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 778 assigned-clocks = <&cru SCLK_TSADC>; 779 assigned-clock-rates = <50000>; 780 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 781 clock-names = "tsadc", "apb_pclk"; 782 resets = <&cru SRST_TSADC>; 783 reset-names = "tsadc-apb"; 784 rockchip,grf = <&grf>; 785 rockchip,hw-tshut-temp = <120000>; 786 pinctrl-names = "init", "default", "sleep"; 787 pinctrl-0 = <&tsadc_otp_pin>; 788 pinctrl-1 = <&tsadc_otp_out>; 789 pinctrl-2 = <&tsadc_otp_pin>; 790 #thermal-sensor-cells = <1>; 791 status = "disabled"; 792 }; 793 794 saradc: saradc@ff288000 { 795 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 796 reg = <0x0 0xff288000 0x0 0x100>; 797 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 798 #io-channel-cells = <1>; 799 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 800 clock-names = "saradc", "apb_pclk"; 801 resets = <&cru SRST_SARADC_P>; 802 reset-names = "saradc-apb"; 803 status = "disabled"; 804 }; 805 806 otp: nvmem@ff290000 { 807 compatible = "rockchip,px30-otp"; 808 reg = <0x0 0xff290000 0x0 0x4000>; 809 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 810 <&cru PCLK_OTP_PHY>; 811 clock-names = "otp", "apb_pclk", "phy"; 812 resets = <&cru SRST_OTP_PHY>; 813 reset-names = "phy"; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 817 /* Data cells */ 818 cpu_id: id@7 { 819 reg = <0x07 0x10>; 820 }; 821 cpu_leakage: cpu-leakage@17 { 822 reg = <0x17 0x1>; 823 }; 824 performance: performance@1e { 825 reg = <0x1e 0x1>; 826 bits = <4 3>; 827 }; 828 }; 829 830 cru: clock-controller@ff2b0000 { 831 compatible = "rockchip,px30-cru"; 832 reg = <0x0 0xff2b0000 0x0 0x1000>; 833 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 834 clock-names = "xin24m", "gpll"; 835 rockchip,grf = <&grf>; 836 #clock-cells = <1>; 837 #reset-cells = <1>; 838 839 assigned-clocks = <&cru PLL_NPLL>, 840 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 841 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 842 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 843 844 assigned-clock-rates = <1188000000>, 845 <200000000>, <200000000>, 846 <150000000>, <150000000>, 847 <100000000>, <200000000>; 848 }; 849 850 pmucru: clock-controller@ff2bc000 { 851 compatible = "rockchip,px30-pmucru"; 852 reg = <0x0 0xff2bc000 0x0 0x1000>; 853 clocks = <&xin24m>; 854 clock-names = "xin24m"; 855 rockchip,grf = <&grf>; 856 #clock-cells = <1>; 857 #reset-cells = <1>; 858 859 assigned-clocks = 860 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 861 <&pmucru SCLK_WIFI_PMU>; 862 assigned-clock-rates = 863 <1200000000>, <100000000>, 864 <26000000>; 865 }; 866 867 usb2phy_grf: syscon@ff2c0000 { 868 compatible = "rockchip,px30-usb2phy-grf", "syscon", 869 "simple-mfd"; 870 reg = <0x0 0xff2c0000 0x0 0x10000>; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 874 u2phy: usb2phy@100 { 875 compatible = "rockchip,px30-usb2phy"; 876 reg = <0x100 0x20>; 877 clocks = <&pmucru SCLK_USBPHY_REF>; 878 clock-names = "phyclk"; 879 #clock-cells = <0>; 880 assigned-clocks = <&cru USB480M>; 881 assigned-clock-parents = <&u2phy>; 882 clock-output-names = "usb480m_phy"; 883 status = "disabled"; 884 885 u2phy_host: host-port { 886 #phy-cells = <0>; 887 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "linestate"; 889 status = "disabled"; 890 }; 891 892 u2phy_otg: otg-port { 893 #phy-cells = <0>; 894 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "otg-bvalid", "otg-id", 898 "linestate"; 899 status = "disabled"; 900 }; 901 }; 902 }; 903 904 dsi_dphy: phy@ff2e0000 { 905 compatible = "rockchip,px30-dsi-dphy"; 906 reg = <0x0 0xff2e0000 0x0 0x10000>; 907 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 908 clock-names = "ref", "pclk"; 909 resets = <&cru SRST_MIPIDSIPHY_P>; 910 reset-names = "apb"; 911 #phy-cells = <0>; 912 power-domains = <&power PX30_PD_VO>; 913 status = "disabled"; 914 }; 915 916 csi_dphy: phy@ff2f0000 { 917 compatible = "rockchip,px30-csi-dphy"; 918 reg = <0x0 0xff2f0000 0x0 0x4000>; 919 clocks = <&cru PCLK_MIPICSIPHY>; 920 clock-names = "pclk"; 921 #phy-cells = <0>; 922 power-domains = <&power PX30_PD_VI>; 923 resets = <&cru SRST_MIPICSIPHY_P>; 924 reset-names = "apb"; 925 rockchip,grf = <&grf>; 926 status = "disabled"; 927 }; 928 929 usb20_otg: usb@ff300000 { 930 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 931 "snps,dwc2"; 932 reg = <0x0 0xff300000 0x0 0x40000>; 933 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cru HCLK_OTG>; 935 clock-names = "otg"; 936 dr_mode = "otg"; 937 g-np-tx-fifo-size = <16>; 938 g-rx-fifo-size = <280>; 939 g-tx-fifo-size = <256 128 128 64 32 16>; 940 phys = <&u2phy_otg>; 941 phy-names = "usb2-phy"; 942 power-domains = <&power PX30_PD_USB>; 943 status = "disabled"; 944 }; 945 946 usb_host0_ehci: usb@ff340000 { 947 compatible = "generic-ehci"; 948 reg = <0x0 0xff340000 0x0 0x10000>; 949 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cru HCLK_HOST>; 951 phys = <&u2phy_host>; 952 phy-names = "usb"; 953 power-domains = <&power PX30_PD_USB>; 954 status = "disabled"; 955 }; 956 957 usb_host0_ohci: usb@ff350000 { 958 compatible = "generic-ohci"; 959 reg = <0x0 0xff350000 0x0 0x10000>; 960 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cru HCLK_HOST>; 962 phys = <&u2phy_host>; 963 phy-names = "usb"; 964 power-domains = <&power PX30_PD_USB>; 965 status = "disabled"; 966 }; 967 968 gmac: ethernet@ff360000 { 969 compatible = "rockchip,px30-gmac"; 970 reg = <0x0 0xff360000 0x0 0x10000>; 971 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "macirq"; 973 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 974 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 975 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 976 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 977 clock-names = "stmmaceth", "mac_clk_rx", 978 "mac_clk_tx", "clk_mac_ref", 979 "clk_mac_refout", "aclk_mac", 980 "pclk_mac", "clk_mac_speed"; 981 rockchip,grf = <&grf>; 982 phy-mode = "rmii"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 985 power-domains = <&power PX30_PD_GMAC>; 986 resets = <&cru SRST_GMAC_A>; 987 reset-names = "stmmaceth"; 988 status = "disabled"; 989 }; 990 991 sdmmc: mmc@ff370000 { 992 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 993 reg = <0x0 0xff370000 0x0 0x4000>; 994 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 996 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 997 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 998 bus-width = <4>; 999 fifo-depth = <0x100>; 1000 max-frequency = <150000000>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1003 power-domains = <&power PX30_PD_SDCARD>; 1004 status = "disabled"; 1005 }; 1006 1007 sdio: mmc@ff380000 { 1008 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1009 reg = <0x0 0xff380000 0x0 0x4000>; 1010 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1012 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1013 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1014 bus-width = <4>; 1015 fifo-depth = <0x100>; 1016 max-frequency = <150000000>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 1019 power-domains = <&power PX30_PD_MMC_NAND>; 1020 status = "disabled"; 1021 }; 1022 1023 emmc: mmc@ff390000 { 1024 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1025 reg = <0x0 0xff390000 0x0 0x4000>; 1026 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1028 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1029 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1030 bus-width = <8>; 1031 fifo-depth = <0x100>; 1032 max-frequency = <150000000>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1035 power-domains = <&power PX30_PD_MMC_NAND>; 1036 status = "disabled"; 1037 }; 1038 1039 sfc: spi@ff3a0000 { 1040 compatible = "rockchip,sfc"; 1041 reg = <0x0 0xff3a0000 0x0 0x4000>; 1042 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1044 clock-names = "clk_sfc", "hclk_sfc"; 1045 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 1046 pinctrl-names = "default"; 1047 power-domains = <&power PX30_PD_MMC_NAND>; 1048 status = "disabled"; 1049 }; 1050 1051 nfc: nand-controller@ff3b0000 { 1052 compatible = "rockchip,px30-nfc"; 1053 reg = <0x0 0xff3b0000 0x0 0x4000>; 1054 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 1056 clock-names = "ahb", "nfc"; 1057 assigned-clocks = <&cru SCLK_NANDC>; 1058 assigned-clock-rates = <150000000>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 1061 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 1062 power-domains = <&power PX30_PD_MMC_NAND>; 1063 status = "disabled"; 1064 }; 1065 1066 gpu_opp_table: opp-table-1 { 1067 compatible = "operating-points-v2"; 1068 1069 opp-200000000 { 1070 opp-hz = /bits/ 64 <200000000>; 1071 opp-microvolt = <950000>; 1072 }; 1073 opp-300000000 { 1074 opp-hz = /bits/ 64 <300000000>; 1075 opp-microvolt = <975000>; 1076 }; 1077 opp-400000000 { 1078 opp-hz = /bits/ 64 <400000000>; 1079 opp-microvolt = <1050000>; 1080 }; 1081 opp-480000000 { 1082 opp-hz = /bits/ 64 <480000000>; 1083 opp-microvolt = <1125000>; 1084 }; 1085 }; 1086 1087 gpu: gpu@ff400000 { 1088 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1089 reg = <0x0 0xff400000 0x0 0x4000>; 1090 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1093 interrupt-names = "job", "mmu", "gpu"; 1094 clocks = <&cru SCLK_GPU>; 1095 #cooling-cells = <2>; 1096 power-domains = <&power PX30_PD_GPU>; 1097 operating-points-v2 = <&gpu_opp_table>; 1098 status = "disabled"; 1099 }; 1100 1101 vpu: video-codec@ff442000 { 1102 compatible = "rockchip,px30-vpu"; 1103 reg = <0x0 0xff442000 0x0 0x800>; 1104 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1106 interrupt-names = "vepu", "vdpu"; 1107 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1108 clock-names = "aclk", "hclk"; 1109 iommus = <&vpu_mmu>; 1110 power-domains = <&power PX30_PD_VPU>; 1111 }; 1112 1113 vpu_mmu: iommu@ff442800 { 1114 compatible = "rockchip,iommu"; 1115 reg = <0x0 0xff442800 0x0 0x100>; 1116 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1118 clock-names = "aclk", "iface"; 1119 #iommu-cells = <0>; 1120 power-domains = <&power PX30_PD_VPU>; 1121 }; 1122 1123 dsi: dsi@ff450000 { 1124 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; 1125 reg = <0x0 0xff450000 0x0 0x10000>; 1126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru PCLK_MIPI_DSI>; 1128 clock-names = "pclk"; 1129 phys = <&dsi_dphy>; 1130 phy-names = "dphy"; 1131 power-domains = <&power PX30_PD_VO>; 1132 resets = <&cru SRST_MIPIDSI_HOST_P>; 1133 reset-names = "apb"; 1134 rockchip,grf = <&grf>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 1139 ports { 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 1143 dsi_in: port@0 { 1144 reg = <0>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 1148 dsi_in_vopb: endpoint@0 { 1149 reg = <0>; 1150 remote-endpoint = <&vopb_out_dsi>; 1151 }; 1152 1153 dsi_in_vopl: endpoint@1 { 1154 reg = <1>; 1155 remote-endpoint = <&vopl_out_dsi>; 1156 }; 1157 }; 1158 1159 dsi_out: port@1 { 1160 reg = <1>; 1161 }; 1162 }; 1163 }; 1164 1165 vopb: vop@ff460000 { 1166 compatible = "rockchip,px30-vop-big"; 1167 reg = <0x0 0xff460000 0x0 0xefc>; 1168 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1170 <&cru HCLK_VOPB>; 1171 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1172 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1173 reset-names = "axi", "ahb", "dclk"; 1174 iommus = <&vopb_mmu>; 1175 power-domains = <&power PX30_PD_VO>; 1176 status = "disabled"; 1177 1178 vopb_out: port { 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 1182 vopb_out_dsi: endpoint@0 { 1183 reg = <0>; 1184 remote-endpoint = <&dsi_in_vopb>; 1185 }; 1186 1187 vopb_out_lvds: endpoint@1 { 1188 reg = <1>; 1189 remote-endpoint = <&lvds_vopb_in>; 1190 }; 1191 }; 1192 }; 1193 1194 vopb_mmu: iommu@ff460f00 { 1195 compatible = "rockchip,iommu"; 1196 reg = <0x0 0xff460f00 0x0 0x100>; 1197 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1199 clock-names = "aclk", "iface"; 1200 power-domains = <&power PX30_PD_VO>; 1201 #iommu-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 vopl: vop@ff470000 { 1206 compatible = "rockchip,px30-vop-lit"; 1207 reg = <0x0 0xff470000 0x0 0xefc>; 1208 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1210 <&cru HCLK_VOPL>; 1211 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1212 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1213 reset-names = "axi", "ahb", "dclk"; 1214 iommus = <&vopl_mmu>; 1215 power-domains = <&power PX30_PD_VO>; 1216 status = "disabled"; 1217 1218 vopl_out: port { 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 vopl_out_dsi: endpoint@0 { 1223 reg = <0>; 1224 remote-endpoint = <&dsi_in_vopl>; 1225 }; 1226 1227 vopl_out_lvds: endpoint@1 { 1228 reg = <1>; 1229 remote-endpoint = <&lvds_vopl_in>; 1230 }; 1231 }; 1232 }; 1233 1234 vopl_mmu: iommu@ff470f00 { 1235 compatible = "rockchip,iommu"; 1236 reg = <0x0 0xff470f00 0x0 0x100>; 1237 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1239 clock-names = "aclk", "iface"; 1240 power-domains = <&power PX30_PD_VO>; 1241 #iommu-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 isp: isp@ff4a0000 { 1246 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ 1247 reg = <0x0 0xff4a0000 0x0 0x8000>; 1248 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1251 interrupt-names = "isp", "mi", "mipi"; 1252 clocks = <&cru SCLK_ISP>, 1253 <&cru ACLK_ISP>, 1254 <&cru HCLK_ISP>, 1255 <&cru PCLK_ISP>; 1256 clock-names = "isp", "aclk", "hclk", "pclk"; 1257 iommus = <&isp_mmu>; 1258 phys = <&csi_dphy>; 1259 phy-names = "dphy"; 1260 power-domains = <&power PX30_PD_VI>; 1261 status = "disabled"; 1262 1263 ports { 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 1267 port@0 { 1268 reg = <0>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 }; 1272 }; 1273 }; 1274 1275 isp_mmu: iommu@ff4a8000 { 1276 compatible = "rockchip,iommu"; 1277 reg = <0x0 0xff4a8000 0x0 0x100>; 1278 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1280 clock-names = "aclk", "iface"; 1281 power-domains = <&power PX30_PD_VI>; 1282 rockchip,disable-mmu-reset; 1283 #iommu-cells = <0>; 1284 }; 1285 1286 qos_gmac: qos@ff518000 { 1287 compatible = "rockchip,px30-qos", "syscon"; 1288 reg = <0x0 0xff518000 0x0 0x20>; 1289 }; 1290 1291 qos_gpu: qos@ff520000 { 1292 compatible = "rockchip,px30-qos", "syscon"; 1293 reg = <0x0 0xff520000 0x0 0x20>; 1294 }; 1295 1296 qos_sdmmc: qos@ff52c000 { 1297 compatible = "rockchip,px30-qos", "syscon"; 1298 reg = <0x0 0xff52c000 0x0 0x20>; 1299 }; 1300 1301 qos_emmc: qos@ff538000 { 1302 compatible = "rockchip,px30-qos", "syscon"; 1303 reg = <0x0 0xff538000 0x0 0x20>; 1304 }; 1305 1306 qos_nand: qos@ff538080 { 1307 compatible = "rockchip,px30-qos", "syscon"; 1308 reg = <0x0 0xff538080 0x0 0x20>; 1309 }; 1310 1311 qos_sdio: qos@ff538100 { 1312 compatible = "rockchip,px30-qos", "syscon"; 1313 reg = <0x0 0xff538100 0x0 0x20>; 1314 }; 1315 1316 qos_sfc: qos@ff538180 { 1317 compatible = "rockchip,px30-qos", "syscon"; 1318 reg = <0x0 0xff538180 0x0 0x20>; 1319 }; 1320 1321 qos_usb_host: qos@ff540000 { 1322 compatible = "rockchip,px30-qos", "syscon"; 1323 reg = <0x0 0xff540000 0x0 0x20>; 1324 }; 1325 1326 qos_usb_otg: qos@ff540080 { 1327 compatible = "rockchip,px30-qos", "syscon"; 1328 reg = <0x0 0xff540080 0x0 0x20>; 1329 }; 1330 1331 qos_isp_128: qos@ff548000 { 1332 compatible = "rockchip,px30-qos", "syscon"; 1333 reg = <0x0 0xff548000 0x0 0x20>; 1334 }; 1335 1336 qos_isp_rd: qos@ff548080 { 1337 compatible = "rockchip,px30-qos", "syscon"; 1338 reg = <0x0 0xff548080 0x0 0x20>; 1339 }; 1340 1341 qos_isp_wr: qos@ff548100 { 1342 compatible = "rockchip,px30-qos", "syscon"; 1343 reg = <0x0 0xff548100 0x0 0x20>; 1344 }; 1345 1346 qos_isp_m1: qos@ff548180 { 1347 compatible = "rockchip,px30-qos", "syscon"; 1348 reg = <0x0 0xff548180 0x0 0x20>; 1349 }; 1350 1351 qos_vip: qos@ff548200 { 1352 compatible = "rockchip,px30-qos", "syscon"; 1353 reg = <0x0 0xff548200 0x0 0x20>; 1354 }; 1355 1356 qos_rga_rd: qos@ff550000 { 1357 compatible = "rockchip,px30-qos", "syscon"; 1358 reg = <0x0 0xff550000 0x0 0x20>; 1359 }; 1360 1361 qos_rga_wr: qos@ff550080 { 1362 compatible = "rockchip,px30-qos", "syscon"; 1363 reg = <0x0 0xff550080 0x0 0x20>; 1364 }; 1365 1366 qos_vop_m0: qos@ff550100 { 1367 compatible = "rockchip,px30-qos", "syscon"; 1368 reg = <0x0 0xff550100 0x0 0x20>; 1369 }; 1370 1371 qos_vop_m1: qos@ff550180 { 1372 compatible = "rockchip,px30-qos", "syscon"; 1373 reg = <0x0 0xff550180 0x0 0x20>; 1374 }; 1375 1376 qos_vpu: qos@ff558000 { 1377 compatible = "rockchip,px30-qos", "syscon"; 1378 reg = <0x0 0xff558000 0x0 0x20>; 1379 }; 1380 1381 qos_vpu_r128: qos@ff558080 { 1382 compatible = "rockchip,px30-qos", "syscon"; 1383 reg = <0x0 0xff558080 0x0 0x20>; 1384 }; 1385 1386 pinctrl: pinctrl { 1387 compatible = "rockchip,px30-pinctrl"; 1388 rockchip,grf = <&grf>; 1389 rockchip,pmu = <&pmugrf>; 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 1394 gpio0: gpio@ff040000 { 1395 compatible = "rockchip,gpio-bank"; 1396 reg = <0x0 0xff040000 0x0 0x100>; 1397 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&pmucru PCLK_GPIO0_PMU>; 1399 gpio-controller; 1400 #gpio-cells = <2>; 1401 1402 interrupt-controller; 1403 #interrupt-cells = <2>; 1404 }; 1405 1406 gpio1: gpio@ff250000 { 1407 compatible = "rockchip,gpio-bank"; 1408 reg = <0x0 0xff250000 0x0 0x100>; 1409 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&cru PCLK_GPIO1>; 1411 gpio-controller; 1412 #gpio-cells = <2>; 1413 1414 interrupt-controller; 1415 #interrupt-cells = <2>; 1416 }; 1417 1418 gpio2: gpio@ff260000 { 1419 compatible = "rockchip,gpio-bank"; 1420 reg = <0x0 0xff260000 0x0 0x100>; 1421 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&cru PCLK_GPIO2>; 1423 gpio-controller; 1424 #gpio-cells = <2>; 1425 1426 interrupt-controller; 1427 #interrupt-cells = <2>; 1428 }; 1429 1430 gpio3: gpio@ff270000 { 1431 compatible = "rockchip,gpio-bank"; 1432 reg = <0x0 0xff270000 0x0 0x100>; 1433 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1434 clocks = <&cru PCLK_GPIO3>; 1435 gpio-controller; 1436 #gpio-cells = <2>; 1437 1438 interrupt-controller; 1439 #interrupt-cells = <2>; 1440 }; 1441 1442 pcfg_pull_up: pcfg-pull-up { 1443 bias-pull-up; 1444 }; 1445 1446 pcfg_pull_down: pcfg-pull-down { 1447 bias-pull-down; 1448 }; 1449 1450 pcfg_pull_none: pcfg-pull-none { 1451 bias-disable; 1452 }; 1453 1454 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1455 bias-disable; 1456 drive-strength = <2>; 1457 }; 1458 1459 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1460 bias-pull-up; 1461 drive-strength = <2>; 1462 }; 1463 1464 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1465 bias-pull-up; 1466 drive-strength = <4>; 1467 }; 1468 1469 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1470 bias-disable; 1471 drive-strength = <4>; 1472 }; 1473 1474 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1475 bias-pull-down; 1476 drive-strength = <4>; 1477 }; 1478 1479 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1480 bias-disable; 1481 drive-strength = <8>; 1482 }; 1483 1484 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1485 bias-pull-up; 1486 drive-strength = <8>; 1487 }; 1488 1489 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1490 bias-disable; 1491 drive-strength = <12>; 1492 }; 1493 1494 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1495 bias-pull-up; 1496 drive-strength = <12>; 1497 }; 1498 1499 pcfg_pull_none_smt: pcfg-pull-none-smt { 1500 bias-disable; 1501 input-schmitt-enable; 1502 }; 1503 1504 pcfg_output_high: pcfg-output-high { 1505 output-high; 1506 }; 1507 1508 pcfg_output_low: pcfg-output-low { 1509 output-low; 1510 }; 1511 1512 pcfg_input_high: pcfg-input-high { 1513 bias-pull-up; 1514 input-enable; 1515 }; 1516 1517 pcfg_input: pcfg-input { 1518 input-enable; 1519 }; 1520 1521 i2c0 { 1522 i2c0_xfer: i2c0-xfer { 1523 rockchip,pins = 1524 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1525 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1526 }; 1527 }; 1528 1529 i2c1 { 1530 i2c1_xfer: i2c1-xfer { 1531 rockchip,pins = 1532 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1533 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1534 }; 1535 }; 1536 1537 i2c2 { 1538 i2c2_xfer: i2c2-xfer { 1539 rockchip,pins = 1540 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1541 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1542 }; 1543 }; 1544 1545 i2c3 { 1546 i2c3_xfer: i2c3-xfer { 1547 rockchip,pins = 1548 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1549 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1550 }; 1551 }; 1552 1553 tsadc { 1554 tsadc_otp_pin: tsadc-otp-pin { 1555 rockchip,pins = 1556 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1557 }; 1558 1559 tsadc_otp_out: tsadc-otp-out { 1560 rockchip,pins = 1561 <0 RK_PA6 1 &pcfg_pull_none>; 1562 }; 1563 }; 1564 1565 uart0 { 1566 uart0_xfer: uart0-xfer { 1567 rockchip,pins = 1568 <0 RK_PB2 1 &pcfg_pull_up>, 1569 <0 RK_PB3 1 &pcfg_pull_up>; 1570 }; 1571 1572 uart0_cts: uart0-cts { 1573 rockchip,pins = 1574 <0 RK_PB4 1 &pcfg_pull_none>; 1575 }; 1576 1577 uart0_rts: uart0-rts { 1578 rockchip,pins = 1579 <0 RK_PB5 1 &pcfg_pull_none>; 1580 }; 1581 }; 1582 1583 uart1 { 1584 uart1_xfer: uart1-xfer { 1585 rockchip,pins = 1586 <1 RK_PC1 1 &pcfg_pull_up>, 1587 <1 RK_PC0 1 &pcfg_pull_up>; 1588 }; 1589 1590 uart1_cts: uart1-cts { 1591 rockchip,pins = 1592 <1 RK_PC2 1 &pcfg_pull_none>; 1593 }; 1594 1595 uart1_rts: uart1-rts { 1596 rockchip,pins = 1597 <1 RK_PC3 1 &pcfg_pull_none>; 1598 }; 1599 }; 1600 1601 uart2-m0 { 1602 uart2m0_xfer: uart2m0-xfer { 1603 rockchip,pins = 1604 <1 RK_PD2 2 &pcfg_pull_up>, 1605 <1 RK_PD3 2 &pcfg_pull_up>; 1606 }; 1607 }; 1608 1609 uart2-m1 { 1610 uart2m1_xfer: uart2m1-xfer { 1611 rockchip,pins = 1612 <2 RK_PB4 2 &pcfg_pull_up>, 1613 <2 RK_PB6 2 &pcfg_pull_up>; 1614 }; 1615 }; 1616 1617 uart3-m0 { 1618 uart3m0_xfer: uart3m0-xfer { 1619 rockchip,pins = 1620 <0 RK_PC0 2 &pcfg_pull_up>, 1621 <0 RK_PC1 2 &pcfg_pull_up>; 1622 }; 1623 1624 uart3m0_cts: uart3m0-cts { 1625 rockchip,pins = 1626 <0 RK_PC2 2 &pcfg_pull_none>; 1627 }; 1628 1629 uart3m0_rts: uart3m0-rts { 1630 rockchip,pins = 1631 <0 RK_PC3 2 &pcfg_pull_none>; 1632 }; 1633 }; 1634 1635 uart3-m1 { 1636 uart3m1_xfer: uart3m1-xfer { 1637 rockchip,pins = 1638 <1 RK_PB6 2 &pcfg_pull_up>, 1639 <1 RK_PB7 2 &pcfg_pull_up>; 1640 }; 1641 1642 uart3m1_cts: uart3m1-cts { 1643 rockchip,pins = 1644 <1 RK_PB4 2 &pcfg_pull_none>; 1645 }; 1646 1647 uart3m1_rts: uart3m1-rts { 1648 rockchip,pins = 1649 <1 RK_PB5 2 &pcfg_pull_none>; 1650 }; 1651 }; 1652 1653 uart4 { 1654 uart4_xfer: uart4-xfer { 1655 rockchip,pins = 1656 <1 RK_PD4 2 &pcfg_pull_up>, 1657 <1 RK_PD5 2 &pcfg_pull_up>; 1658 }; 1659 1660 uart4_cts: uart4-cts { 1661 rockchip,pins = 1662 <1 RK_PD6 2 &pcfg_pull_none>; 1663 }; 1664 1665 uart4_rts: uart4-rts { 1666 rockchip,pins = 1667 <1 RK_PD7 2 &pcfg_pull_none>; 1668 }; 1669 }; 1670 1671 uart5 { 1672 uart5_xfer: uart5-xfer { 1673 rockchip,pins = 1674 <3 RK_PA2 4 &pcfg_pull_up>, 1675 <3 RK_PA1 4 &pcfg_pull_up>; 1676 }; 1677 1678 uart5_cts: uart5-cts { 1679 rockchip,pins = 1680 <3 RK_PA3 4 &pcfg_pull_none>; 1681 }; 1682 1683 uart5_rts: uart5-rts { 1684 rockchip,pins = 1685 <3 RK_PA5 4 &pcfg_pull_none>; 1686 }; 1687 }; 1688 1689 spi0 { 1690 spi0_clk: spi0-clk { 1691 rockchip,pins = 1692 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1693 }; 1694 1695 spi0_csn: spi0-csn { 1696 rockchip,pins = 1697 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1698 }; 1699 1700 spi0_miso: spi0-miso { 1701 rockchip,pins = 1702 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1703 }; 1704 1705 spi0_mosi: spi0-mosi { 1706 rockchip,pins = 1707 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1708 }; 1709 1710 spi0_clk_hs: spi0-clk-hs { 1711 rockchip,pins = 1712 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1713 }; 1714 1715 spi0_miso_hs: spi0-miso-hs { 1716 rockchip,pins = 1717 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1718 }; 1719 1720 spi0_mosi_hs: spi0-mosi-hs { 1721 rockchip,pins = 1722 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1723 }; 1724 }; 1725 1726 spi1 { 1727 spi1_clk: spi1-clk { 1728 rockchip,pins = 1729 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1730 }; 1731 1732 spi1_csn0: spi1-csn0 { 1733 rockchip,pins = 1734 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1735 }; 1736 1737 spi1_csn1: spi1-csn1 { 1738 rockchip,pins = 1739 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1740 }; 1741 1742 spi1_miso: spi1-miso { 1743 rockchip,pins = 1744 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1745 }; 1746 1747 spi1_mosi: spi1-mosi { 1748 rockchip,pins = 1749 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1750 }; 1751 1752 spi1_clk_hs: spi1-clk-hs { 1753 rockchip,pins = 1754 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1755 }; 1756 1757 spi1_miso_hs: spi1-miso-hs { 1758 rockchip,pins = 1759 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1760 }; 1761 1762 spi1_mosi_hs: spi1-mosi-hs { 1763 rockchip,pins = 1764 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1765 }; 1766 }; 1767 1768 pdm { 1769 pdm_clk0m0: pdm-clk0m0 { 1770 rockchip,pins = 1771 <3 RK_PC6 2 &pcfg_pull_none>; 1772 }; 1773 1774 pdm_clk0m1: pdm-clk0m1 { 1775 rockchip,pins = 1776 <2 RK_PC6 1 &pcfg_pull_none>; 1777 }; 1778 1779 pdm_clk1: pdm-clk1 { 1780 rockchip,pins = 1781 <3 RK_PC7 2 &pcfg_pull_none>; 1782 }; 1783 1784 pdm_sdi0m0: pdm-sdi0m0 { 1785 rockchip,pins = 1786 <3 RK_PD3 2 &pcfg_pull_none>; 1787 }; 1788 1789 pdm_sdi0m1: pdm-sdi0m1 { 1790 rockchip,pins = 1791 <2 RK_PC5 2 &pcfg_pull_none>; 1792 }; 1793 1794 pdm_sdi1: pdm-sdi1 { 1795 rockchip,pins = 1796 <3 RK_PD0 2 &pcfg_pull_none>; 1797 }; 1798 1799 pdm_sdi2: pdm-sdi2 { 1800 rockchip,pins = 1801 <3 RK_PD1 2 &pcfg_pull_none>; 1802 }; 1803 1804 pdm_sdi3: pdm-sdi3 { 1805 rockchip,pins = 1806 <3 RK_PD2 2 &pcfg_pull_none>; 1807 }; 1808 1809 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1810 rockchip,pins = 1811 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1812 }; 1813 1814 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1815 rockchip,pins = 1816 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1817 }; 1818 1819 pdm_clk1_sleep: pdm-clk1-sleep { 1820 rockchip,pins = 1821 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1822 }; 1823 1824 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1825 rockchip,pins = 1826 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1827 }; 1828 1829 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1830 rockchip,pins = 1831 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1832 }; 1833 1834 pdm_sdi1_sleep: pdm-sdi1-sleep { 1835 rockchip,pins = 1836 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1837 }; 1838 1839 pdm_sdi2_sleep: pdm-sdi2-sleep { 1840 rockchip,pins = 1841 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1842 }; 1843 1844 pdm_sdi3_sleep: pdm-sdi3-sleep { 1845 rockchip,pins = 1846 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1847 }; 1848 }; 1849 1850 i2s0 { 1851 i2s0_8ch_mclk: i2s0-8ch-mclk { 1852 rockchip,pins = 1853 <3 RK_PC1 2 &pcfg_pull_none>; 1854 }; 1855 1856 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1857 rockchip,pins = 1858 <3 RK_PC3 2 &pcfg_pull_none>; 1859 }; 1860 1861 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1862 rockchip,pins = 1863 <3 RK_PB4 2 &pcfg_pull_none>; 1864 }; 1865 1866 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1867 rockchip,pins = 1868 <3 RK_PC2 2 &pcfg_pull_none>; 1869 }; 1870 1871 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1872 rockchip,pins = 1873 <3 RK_PB5 2 &pcfg_pull_none>; 1874 }; 1875 1876 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1877 rockchip,pins = 1878 <3 RK_PC4 2 &pcfg_pull_none>; 1879 }; 1880 1881 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1882 rockchip,pins = 1883 <3 RK_PC0 2 &pcfg_pull_none>; 1884 }; 1885 1886 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1887 rockchip,pins = 1888 <3 RK_PB7 2 &pcfg_pull_none>; 1889 }; 1890 1891 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1892 rockchip,pins = 1893 <3 RK_PB6 2 &pcfg_pull_none>; 1894 }; 1895 1896 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1897 rockchip,pins = 1898 <3 RK_PC5 2 &pcfg_pull_none>; 1899 }; 1900 1901 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1902 rockchip,pins = 1903 <3 RK_PB3 2 &pcfg_pull_none>; 1904 }; 1905 1906 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1907 rockchip,pins = 1908 <3 RK_PB1 2 &pcfg_pull_none>; 1909 }; 1910 1911 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1912 rockchip,pins = 1913 <3 RK_PB0 2 &pcfg_pull_none>; 1914 }; 1915 }; 1916 1917 i2s1 { 1918 i2s1_2ch_mclk: i2s1-2ch-mclk { 1919 rockchip,pins = 1920 <2 RK_PC3 1 &pcfg_pull_none>; 1921 }; 1922 1923 i2s1_2ch_sclk: i2s1-2ch-sclk { 1924 rockchip,pins = 1925 <2 RK_PC2 1 &pcfg_pull_none>; 1926 }; 1927 1928 i2s1_2ch_lrck: i2s1-2ch-lrck { 1929 rockchip,pins = 1930 <2 RK_PC1 1 &pcfg_pull_none>; 1931 }; 1932 1933 i2s1_2ch_sdi: i2s1-2ch-sdi { 1934 rockchip,pins = 1935 <2 RK_PC5 1 &pcfg_pull_none>; 1936 }; 1937 1938 i2s1_2ch_sdo: i2s1-2ch-sdo { 1939 rockchip,pins = 1940 <2 RK_PC4 1 &pcfg_pull_none>; 1941 }; 1942 }; 1943 1944 i2s2 { 1945 i2s2_2ch_mclk: i2s2-2ch-mclk { 1946 rockchip,pins = 1947 <3 RK_PA1 2 &pcfg_pull_none>; 1948 }; 1949 1950 i2s2_2ch_sclk: i2s2-2ch-sclk { 1951 rockchip,pins = 1952 <3 RK_PA2 2 &pcfg_pull_none>; 1953 }; 1954 1955 i2s2_2ch_lrck: i2s2-2ch-lrck { 1956 rockchip,pins = 1957 <3 RK_PA3 2 &pcfg_pull_none>; 1958 }; 1959 1960 i2s2_2ch_sdi: i2s2-2ch-sdi { 1961 rockchip,pins = 1962 <3 RK_PA5 2 &pcfg_pull_none>; 1963 }; 1964 1965 i2s2_2ch_sdo: i2s2-2ch-sdo { 1966 rockchip,pins = 1967 <3 RK_PA7 2 &pcfg_pull_none>; 1968 }; 1969 }; 1970 1971 sdmmc { 1972 sdmmc_clk: sdmmc-clk { 1973 rockchip,pins = 1974 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1975 }; 1976 1977 sdmmc_cmd: sdmmc-cmd { 1978 rockchip,pins = 1979 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1980 }; 1981 1982 sdmmc_det: sdmmc-det { 1983 rockchip,pins = 1984 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1985 }; 1986 1987 sdmmc_bus1: sdmmc-bus1 { 1988 rockchip,pins = 1989 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1990 }; 1991 1992 sdmmc_bus4: sdmmc-bus4 { 1993 rockchip,pins = 1994 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1995 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1996 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1997 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1998 }; 1999 }; 2000 2001 sdio { 2002 sdio_clk: sdio-clk { 2003 rockchip,pins = 2004 <1 RK_PC5 1 &pcfg_pull_none>; 2005 }; 2006 2007 sdio_cmd: sdio-cmd { 2008 rockchip,pins = 2009 <1 RK_PC4 1 &pcfg_pull_up>; 2010 }; 2011 2012 sdio_bus4: sdio-bus4 { 2013 rockchip,pins = 2014 <1 RK_PC6 1 &pcfg_pull_up>, 2015 <1 RK_PC7 1 &pcfg_pull_up>, 2016 <1 RK_PD0 1 &pcfg_pull_up>, 2017 <1 RK_PD1 1 &pcfg_pull_up>; 2018 }; 2019 }; 2020 2021 emmc { 2022 emmc_clk: emmc-clk { 2023 rockchip,pins = 2024 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 2025 }; 2026 2027 emmc_cmd: emmc-cmd { 2028 rockchip,pins = 2029 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 2030 }; 2031 2032 emmc_rstnout: emmc-rstnout { 2033 rockchip,pins = 2034 <1 RK_PB3 2 &pcfg_pull_none>; 2035 }; 2036 2037 emmc_bus1: emmc-bus1 { 2038 rockchip,pins = 2039 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 2040 }; 2041 2042 emmc_bus4: emmc-bus4 { 2043 rockchip,pins = 2044 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2045 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2046 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2047 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 2048 }; 2049 2050 emmc_bus8: emmc-bus8 { 2051 rockchip,pins = 2052 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2053 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2054 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2055 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 2056 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 2057 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 2058 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 2059 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 2060 }; 2061 }; 2062 2063 flash { 2064 flash_cs0: flash-cs0 { 2065 rockchip,pins = 2066 <1 RK_PB0 1 &pcfg_pull_none>; 2067 }; 2068 2069 flash_rdy: flash-rdy { 2070 rockchip,pins = 2071 <1 RK_PB1 1 &pcfg_pull_none>; 2072 }; 2073 2074 flash_dqs: flash-dqs { 2075 rockchip,pins = 2076 <1 RK_PB2 1 &pcfg_pull_none>; 2077 }; 2078 2079 flash_ale: flash-ale { 2080 rockchip,pins = 2081 <1 RK_PB3 1 &pcfg_pull_none>; 2082 }; 2083 2084 flash_cle: flash-cle { 2085 rockchip,pins = 2086 <1 RK_PB4 1 &pcfg_pull_none>; 2087 }; 2088 2089 flash_wrn: flash-wrn { 2090 rockchip,pins = 2091 <1 RK_PB5 1 &pcfg_pull_none>; 2092 }; 2093 2094 flash_csl: flash-csl { 2095 rockchip,pins = 2096 <1 RK_PB6 1 &pcfg_pull_none>; 2097 }; 2098 2099 flash_rdn: flash-rdn { 2100 rockchip,pins = 2101 <1 RK_PB7 1 &pcfg_pull_none>; 2102 }; 2103 2104 flash_bus8: flash-bus8 { 2105 rockchip,pins = 2106 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 2107 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 2108 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 2109 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 2110 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 2111 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 2112 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 2113 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 2114 }; 2115 }; 2116 2117 sfc { 2118 sfc_bus4: sfc-bus4 { 2119 rockchip,pins = 2120 <1 RK_PA0 3 &pcfg_pull_none>, 2121 <1 RK_PA1 3 &pcfg_pull_none>, 2122 <1 RK_PA2 3 &pcfg_pull_none>, 2123 <1 RK_PA3 3 &pcfg_pull_none>; 2124 }; 2125 2126 sfc_bus2: sfc-bus2 { 2127 rockchip,pins = 2128 <1 RK_PA0 3 &pcfg_pull_none>, 2129 <1 RK_PA1 3 &pcfg_pull_none>; 2130 }; 2131 2132 sfc_cs0: sfc-cs0 { 2133 rockchip,pins = 2134 <1 RK_PA4 3 &pcfg_pull_none>; 2135 }; 2136 2137 sfc_clk: sfc-clk { 2138 rockchip,pins = 2139 <1 RK_PB1 3 &pcfg_pull_none>; 2140 }; 2141 }; 2142 2143 lcdc { 2144 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 2145 rockchip,pins = 2146 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 2147 }; 2148 2149 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 2150 rockchip,pins = 2151 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 2152 }; 2153 2154 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 2155 rockchip,pins = 2156 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 2157 }; 2158 2159 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 2160 rockchip,pins = 2161 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 2162 }; 2163 2164 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 2165 rockchip,pins = 2166 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2167 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2168 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2169 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2170 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2171 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2172 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2173 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2174 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2175 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2176 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2177 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2178 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2179 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2180 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2181 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2182 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2183 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2184 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2185 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2186 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2187 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2188 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2189 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2190 }; 2191 2192 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2193 rockchip,pins = 2194 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2195 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2196 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2197 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2198 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2199 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2200 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2201 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2202 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2203 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2204 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2205 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2206 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2207 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2208 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2209 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2210 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2211 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2212 }; 2213 2214 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2215 rockchip,pins = 2216 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2217 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2218 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2219 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2220 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2221 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2222 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2223 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2224 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2225 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2226 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2227 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2228 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2229 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2230 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2231 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2232 }; 2233 2234 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2235 rockchip,pins = 2236 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2237 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2238 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2239 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2240 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2241 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2242 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2243 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2244 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2245 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2246 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2247 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2248 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2249 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2250 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2251 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2252 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2253 }; 2254 2255 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2256 rockchip,pins = 2257 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2258 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2259 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2260 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2261 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2262 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2263 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2264 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2265 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2266 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2267 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2268 }; 2269 2270 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2271 rockchip,pins = 2272 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2273 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2274 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2275 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2276 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2277 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2278 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2279 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2280 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2281 }; 2282 }; 2283 2284 pwm0 { 2285 pwm0_pin: pwm0-pin { 2286 rockchip,pins = 2287 <0 RK_PB7 1 &pcfg_pull_none>; 2288 }; 2289 }; 2290 2291 pwm1 { 2292 pwm1_pin: pwm1-pin { 2293 rockchip,pins = 2294 <0 RK_PC0 1 &pcfg_pull_none>; 2295 }; 2296 }; 2297 2298 pwm2 { 2299 pwm2_pin: pwm2-pin { 2300 rockchip,pins = 2301 <2 RK_PB5 1 &pcfg_pull_none>; 2302 }; 2303 }; 2304 2305 pwm3 { 2306 pwm3_pin: pwm3-pin { 2307 rockchip,pins = 2308 <0 RK_PC1 1 &pcfg_pull_none>; 2309 }; 2310 }; 2311 2312 pwm4 { 2313 pwm4_pin: pwm4-pin { 2314 rockchip,pins = 2315 <3 RK_PC2 3 &pcfg_pull_none>; 2316 }; 2317 }; 2318 2319 pwm5 { 2320 pwm5_pin: pwm5-pin { 2321 rockchip,pins = 2322 <3 RK_PC3 3 &pcfg_pull_none>; 2323 }; 2324 }; 2325 2326 pwm6 { 2327 pwm6_pin: pwm6-pin { 2328 rockchip,pins = 2329 <3 RK_PC4 3 &pcfg_pull_none>; 2330 }; 2331 }; 2332 2333 pwm7 { 2334 pwm7_pin: pwm7-pin { 2335 rockchip,pins = 2336 <3 RK_PC5 3 &pcfg_pull_none>; 2337 }; 2338 }; 2339 2340 gmac { 2341 rmii_pins: rmii-pins { 2342 rockchip,pins = 2343 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2344 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2345 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2346 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2347 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2348 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2349 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2350 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2351 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2352 }; 2353 2354 mac_refclk_12ma: mac-refclk-12ma { 2355 rockchip,pins = 2356 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2357 }; 2358 2359 mac_refclk: mac-refclk { 2360 rockchip,pins = 2361 <2 RK_PB2 2 &pcfg_pull_none>; 2362 }; 2363 }; 2364 2365 cif-m0 { 2366 cif_clkout_m0: cif-clkout-m0 { 2367 rockchip,pins = 2368 <2 RK_PB3 1 &pcfg_pull_none>; 2369 }; 2370 2371 dvp_d2d9_m0: dvp-d2d9-m0 { 2372 rockchip,pins = 2373 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2374 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2375 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2376 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2377 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2378 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2379 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2380 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2381 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2382 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2383 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2384 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2385 }; 2386 2387 dvp_d0d1_m0: dvp-d0d1-m0 { 2388 rockchip,pins = 2389 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2390 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2391 }; 2392 2393 dvp_d10d11_m0:d10-d11-m0 { 2394 rockchip,pins = 2395 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2396 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2397 }; 2398 }; 2399 2400 cif-m1 { 2401 cif_clkout_m1: cif-clkout-m1 { 2402 rockchip,pins = 2403 <3 RK_PD0 3 &pcfg_pull_none>; 2404 }; 2405 2406 dvp_d2d9_m1: dvp-d2d9-m1 { 2407 rockchip,pins = 2408 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2409 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2410 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2411 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2412 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2413 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2414 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2415 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2416 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2417 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2418 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2419 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2420 }; 2421 2422 dvp_d0d1_m1: dvp-d0d1-m1 { 2423 rockchip,pins = 2424 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2425 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2426 }; 2427 2428 dvp_d10d11_m1:d10-d11-m1 { 2429 rockchip,pins = 2430 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2431 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2432 }; 2433 }; 2434 2435 isp { 2436 isp_prelight: isp-prelight { 2437 rockchip,pins = 2438 <3 RK_PD1 4 &pcfg_pull_none>; 2439 }; 2440 }; 2441 }; 2442}; 2443