xref: /openbmc/u-boot/arch/arm/dts/rk3399.dtsi (revision e5fd39c8)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rk3399-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3399-power.h>
12#include <dt-bindings/thermal/thermal.h>
13#define USB_CLASS_HUB			9
14
15/ {
16	compatible = "rockchip,rk3399";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		i2c2 = &i2c2;
26		i2c3 = &i2c3;
27		i2c4 = &i2c4;
28		i2c5 = &i2c5;
29		i2c6 = &i2c6;
30		i2c7 = &i2c7;
31		i2c8 = &i2c8;
32		serial0 = &uart0;
33		serial1 = &uart1;
34		serial2 = &uart2;
35		serial3 = &uart3;
36		serial4 = &uart4;
37		mmc0 = &sdhci;
38		mmc1 = &sdmmc;
39	};
40
41	cpus {
42		#address-cells = <2>;
43		#size-cells = <0>;
44
45		cpu-map {
46			cluster0 {
47				core0 {
48					cpu = <&cpu_l0>;
49				};
50				core1 {
51					cpu = <&cpu_l1>;
52				};
53				core2 {
54					cpu = <&cpu_l2>;
55				};
56				core3 {
57					cpu = <&cpu_l3>;
58				};
59			};
60
61			cluster1 {
62				core0 {
63					cpu = <&cpu_b0>;
64				};
65				core1 {
66					cpu = <&cpu_b1>;
67				};
68			};
69		};
70
71		cpu_l0: cpu@0 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a53", "arm,armv8";
74			reg = <0x0 0x0>;
75			enable-method = "psci";
76			#cooling-cells = <2>; /* min followed by max */
77			clocks = <&cru ARMCLKL>;
78		};
79
80		cpu_l1: cpu@1 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53", "arm,armv8";
83			reg = <0x0 0x1>;
84			enable-method = "psci";
85			clocks = <&cru ARMCLKL>;
86		};
87
88		cpu_l2: cpu@2 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53", "arm,armv8";
91			reg = <0x0 0x2>;
92			enable-method = "psci";
93			clocks = <&cru ARMCLKL>;
94		};
95
96		cpu_l3: cpu@3 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a53", "arm,armv8";
99			reg = <0x0 0x3>;
100			enable-method = "psci";
101			clocks = <&cru ARMCLKL>;
102		};
103
104		cpu_b0: cpu@100 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a72", "arm,armv8";
107			reg = <0x0 0x100>;
108			enable-method = "psci";
109			#cooling-cells = <2>; /* min followed by max */
110			clocks = <&cru ARMCLKB>;
111		};
112
113		cpu_b1: cpu@101 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a72", "arm,armv8";
116			reg = <0x0 0x101>;
117			enable-method = "psci";
118			clocks = <&cru ARMCLKB>;
119		};
120	};
121
122	pmu_a53 {
123		compatible = "arm,cortex-a53-pmu";
124		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
125	};
126
127	pmu_a72 {
128		compatible = "arm,cortex-a72-pmu";
129		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
130	};
131
132	psci {
133		compatible = "arm,psci-1.0";
134		method = "smc";
135	};
136
137	timer {
138		compatible = "arm,armv8-timer";
139		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
140			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
141			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
142			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
143		arm,no-tick-in-suspend;
144	};
145
146	xin24m: xin24m {
147		compatible = "fixed-clock";
148		clock-frequency = <24000000>;
149		clock-output-names = "xin24m";
150		#clock-cells = <0>;
151	};
152
153	amba {
154		compatible = "simple-bus";
155		#address-cells = <2>;
156		#size-cells = <2>;
157		ranges;
158
159		dmac_bus: dma-controller@ff6d0000 {
160			compatible = "arm,pl330", "arm,primecell";
161			reg = <0x0 0xff6d0000 0x0 0x4000>;
162			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
163				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
164			#dma-cells = <1>;
165			clocks = <&cru ACLK_DMAC0_PERILP>;
166			clock-names = "apb_pclk";
167		};
168
169		dmac_peri: dma-controller@ff6e0000 {
170			compatible = "arm,pl330", "arm,primecell";
171			reg = <0x0 0xff6e0000 0x0 0x4000>;
172			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
173				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
174			#dma-cells = <1>;
175			clocks = <&cru ACLK_DMAC1_PERILP>;
176			clock-names = "apb_pclk";
177		};
178	};
179
180	pcie0: pcie@f8000000 {
181		compatible = "rockchip,rk3399-pcie";
182		reg = <0x0 0xf8000000 0x0 0x2000000>,
183		      <0x0 0xfd000000 0x0 0x1000000>;
184		reg-names = "axi-base", "apb-base";
185		#address-cells = <3>;
186		#size-cells = <2>;
187		#interrupt-cells = <1>;
188		aspm-no-l0s;
189		bus-range = <0x0 0x1>;
190		clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
191			 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
192		clock-names = "aclk", "aclk-perf",
193			      "hclk", "pm";
194		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
195			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
196			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
197		interrupt-names = "sys", "legacy", "client";
198		interrupt-map-mask = <0 0 0 7>;
199		interrupt-map = <0 0 0 1 &pcie0_intc 0>,
200				<0 0 0 2 &pcie0_intc 1>,
201				<0 0 0 3 &pcie0_intc 2>,
202				<0 0 0 4 &pcie0_intc 3>;
203		linux,pci-domain = <0>;
204		max-link-speed = <1>;
205		msi-map = <0x0 &its 0x0 0x1000>;
206		phys = <&pcie_phy>;
207		phy-names = "pcie-phy";
208		ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
209			  0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
210		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
211			 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
212			 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
213			 <&cru SRST_A_PCIE>;
214		reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
215			      "pm", "pclk", "aclk";
216		status = "disabled";
217
218		pcie0_intc: interrupt-controller {
219			interrupt-controller;
220			#address-cells = <0>;
221			#interrupt-cells = <1>;
222		};
223	};
224
225	gmac: ethernet@fe300000 {
226		compatible = "rockchip,rk3399-gmac";
227		reg = <0x0 0xfe300000 0x0 0x10000>;
228		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
229		interrupt-names = "macirq";
230		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
231			 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
232			 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
233			 <&cru PCLK_GMAC>;
234		clock-names = "stmmaceth", "mac_clk_rx",
235			      "mac_clk_tx", "clk_mac_ref",
236			      "clk_mac_refout", "aclk_mac",
237			      "pclk_mac";
238		power-domains = <&power RK3399_PD_GMAC>;
239		resets = <&cru SRST_A_GMAC>;
240		reset-names = "stmmaceth";
241		rockchip,grf = <&grf>;
242		status = "disabled";
243	};
244
245	sdio0: dwmmc@fe310000 {
246		compatible = "rockchip,rk3399-dw-mshc",
247			     "rockchip,rk3288-dw-mshc";
248		reg = <0x0 0xfe310000 0x0 0x4000>;
249		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
250		max-frequency = <150000000>;
251		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
252			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
253		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
254		fifo-depth = <0x100>;
255		power-domains = <&power RK3399_PD_SDIOAUDIO>;
256		resets = <&cru SRST_SDIO0>;
257		reset-names = "reset";
258		status = "disabled";
259	};
260
261	sdmmc: dwmmc@fe320000 {
262		compatible = "rockchip,rk3399-dw-mshc",
263			     "rockchip,rk3288-dw-mshc";
264		reg = <0x0 0xfe320000 0x0 0x4000>;
265		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
266		max-frequency = <150000000>;
267		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
269		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270		fifo-depth = <0x100>;
271		power-domains = <&power RK3399_PD_SD>;
272		resets = <&cru SRST_SDMMC>;
273		reset-names = "reset";
274		status = "disabled";
275	};
276
277	sdhci: sdhci@fe330000 {
278		u-boot,dm-pre-reloc;
279		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
280		reg = <0x0 0xfe330000 0x0 0x10000>;
281		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
282		arasan,soc-ctl-syscon = <&grf>;
283		assigned-clocks = <&cru SCLK_EMMC>;
284		assigned-clock-rates = <200000000>;
285		max-frequency = <200000000>;
286		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
287		clock-names = "clk_xin", "clk_ahb";
288		clock-output-names = "emmc_cardclock";
289		#clock-cells = <0>;
290		phys = <&emmc_phy>;
291		phy-names = "phy_arasan";
292		power-domains = <&power RK3399_PD_EMMC>;
293		status = "disabled";
294	};
295
296	usb_host0_ehci: usb@fe380000 {
297		compatible = "generic-ehci";
298		reg = <0x0 0xfe380000 0x0 0x20000>;
299		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
300		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
301			 <&u2phy0>;
302		clock-names = "usbhost", "arbiter",
303			      "utmi";
304		phys = <&u2phy0_host>;
305		phy-names = "usb";
306		power-domains = <&power RK3399_PD_PERIHP>;
307		status = "disabled";
308	};
309
310	usb_host0_ohci: usb@fe3a0000 {
311		compatible = "generic-ohci";
312		reg = <0x0 0xfe3a0000 0x0 0x20000>;
313		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
314		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
315			 <&u2phy0>;
316		clock-names = "usbhost", "arbiter",
317			      "utmi";
318		phys = <&u2phy0_host>;
319		phy-names = "usb";
320		power-domains = <&power RK3399_PD_PERIHP>;
321		status = "disabled";
322	};
323
324	usb_host1_ehci: usb@fe3c0000 {
325		compatible = "generic-ehci";
326		reg = <0x0 0xfe3c0000 0x0 0x20000>;
327		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
328		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
329			 <&u2phy1>;
330		clock-names = "usbhost", "arbiter",
331			      "utmi";
332		phys = <&u2phy1_host>;
333		phy-names = "usb";
334		power-domains = <&power RK3399_PD_PERIHP>;
335		status = "disabled";
336	};
337
338	usb_host1_ohci: usb@fe3e0000 {
339		compatible = "generic-ohci";
340		reg = <0x0 0xfe3e0000 0x0 0x20000>;
341		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
342		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
343			 <&u2phy1>;
344		clock-names = "usbhost", "arbiter",
345			      "utmi";
346		phys = <&u2phy1_host>;
347		phy-names = "usb";
348		power-domains = <&power RK3399_PD_PERIHP>;
349		status = "disabled";
350	};
351
352	usbdrd3_0: dwc3_typec0: usb@fe800000 {
353		compatible = "rockchip,rk3399-dwc3";
354		#address-cells = <2>;
355		#size-cells = <2>;
356		ranges;
357		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
358			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
359			 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
360		clock-names = "ref_clk", "suspend_clk",
361			      "bus_clk", "aclk_usb3_rksoc_axi_perf",
362			      "aclk_usb3", "grf_clk";
363		resets = <&cru SRST_A_USB3_OTG0>;
364		reset-names = "usb3-otg";
365		status = "disabled";
366
367		usbdrd_dwc3_0: dwc3 {
368			compatible = "snps,dwc3";
369			reg = <0x0 0xfe800000 0x0 0x100000>;
370			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
371			dr_mode = "otg";
372			phys = <&u2phy0_otg>, <&tcphy0_usb3>;
373			phy-names = "usb2-phy", "usb3-phy";
374			phy_type = "utmi_wide";
375			snps,dis_enblslpm_quirk;
376			snps,dis-u2-freeclk-exists-quirk;
377			snps,dis_u2_susphy_quirk;
378			snps,dis-del-phy-power-chg-quirk;
379			snps,dis-tx-ipgap-linecheck-quirk;
380			power-domains = <&power RK3399_PD_USB3>;
381			status = "disabled";
382		};
383	};
384
385	dwc3_typec1: usbdrd3_1: usb@fe900000 {
386		compatible = "rockchip,rk3399-dwc3";
387		#address-cells = <2>;
388		#size-cells = <2>;
389		ranges;
390		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
391			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
392			 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
393		clock-names = "ref_clk", "suspend_clk",
394			      "bus_clk", "aclk_usb3_rksoc_axi_perf",
395			      "aclk_usb3", "grf_clk";
396		resets = <&cru SRST_A_USB3_OTG1>;
397		reset-names = "usb3-otg";
398		status = "disabled";
399
400		usbdrd_dwc3_1: dwc3 {
401			compatible = "snps,dwc3";
402			reg = <0x0 0xfe900000 0x0 0x100000>;
403			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
404			dr_mode = "otg";
405			phys = <&u2phy1_otg>, <&tcphy1_usb3>;
406			phy-names = "usb2-phy", "usb3-phy";
407			phy_type = "utmi_wide";
408			snps,dis_enblslpm_quirk;
409			snps,dis-u2-freeclk-exists-quirk;
410			snps,dis_u2_susphy_quirk;
411			snps,dis-del-phy-power-chg-quirk;
412			snps,dis-tx-ipgap-linecheck-quirk;
413			power-domains = <&power RK3399_PD_USB3>;
414			status = "disabled";
415		};
416	};
417
418	cdn_dp: dp@fec00000 {
419		compatible = "rockchip,rk3399-cdn-dp";
420		reg = <0x0 0xfec00000 0x0 0x100000>;
421		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
422		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
423		assigned-clock-rates = <100000000>, <200000000>;
424		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
425			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
426		clock-names = "core-clk", "pclk", "spdif", "grf";
427		phys = <&tcphy0_dp>, <&tcphy1_dp>;
428		power-domains = <&power RK3399_PD_HDCP>;
429		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
430			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
431		reset-names = "spdif", "dptx", "apb", "core";
432		rockchip,grf = <&grf>;
433		#sound-dai-cells = <1>;
434		status = "disabled";
435
436		ports {
437			dp_in: port {
438				#address-cells = <1>;
439				#size-cells = <0>;
440
441				dp_in_vopb: endpoint@0 {
442					reg = <0>;
443					remote-endpoint = <&vopb_out_dp>;
444				};
445
446				dp_in_vopl: endpoint@1 {
447					reg = <1>;
448					remote-endpoint = <&vopl_out_dp>;
449				};
450			};
451		};
452	};
453
454	gic: interrupt-controller@fee00000 {
455		compatible = "arm,gic-v3";
456		#interrupt-cells = <4>;
457		#address-cells = <2>;
458		#size-cells = <2>;
459		ranges;
460		interrupt-controller;
461
462		reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
463		      <0x0 0xfef00000 0 0xc0000>, /* GICR */
464		      <0x0 0xfff00000 0 0x10000>, /* GICC */
465		      <0x0 0xfff10000 0 0x10000>, /* GICH */
466		      <0x0 0xfff20000 0 0x10000>; /* GICV */
467		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
468		its: interrupt-controller@fee20000 {
469			compatible = "arm,gic-v3-its";
470			msi-controller;
471			reg = <0x0 0xfee20000 0x0 0x20000>;
472		};
473
474		ppi-partitions {
475			ppi_cluster0: interrupt-partition-0 {
476				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
477			};
478
479			ppi_cluster1: interrupt-partition-1 {
480				affinity = <&cpu_b0 &cpu_b1>;
481			};
482		};
483	};
484
485	saradc: saradc@ff100000 {
486		compatible = "rockchip,rk3399-saradc";
487		reg = <0x0 0xff100000 0x0 0x100>;
488		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
489		#io-channel-cells = <1>;
490		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
491		clock-names = "saradc", "apb_pclk";
492		resets = <&cru SRST_P_SARADC>;
493		reset-names = "saradc-apb";
494		status = "disabled";
495	};
496
497	i2c1: i2c@ff110000 {
498		compatible = "rockchip,rk3399-i2c";
499		reg = <0x0 0xff110000 0x0 0x1000>;
500		assigned-clocks = <&cru SCLK_I2C1>;
501		assigned-clock-rates = <200000000>;
502		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
503		clock-names = "i2c", "pclk";
504		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
505		pinctrl-names = "default";
506		pinctrl-0 = <&i2c1_xfer>;
507		#address-cells = <1>;
508		#size-cells = <0>;
509		status = "disabled";
510	};
511
512	i2c2: i2c@ff120000 {
513		compatible = "rockchip,rk3399-i2c";
514		reg = <0x0 0xff120000 0x0 0x1000>;
515		assigned-clocks = <&cru SCLK_I2C2>;
516		assigned-clock-rates = <200000000>;
517		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
518		clock-names = "i2c", "pclk";
519		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
520		pinctrl-names = "default";
521		pinctrl-0 = <&i2c2_xfer>;
522		#address-cells = <1>;
523		#size-cells = <0>;
524		status = "disabled";
525	};
526
527	i2c3: i2c@ff130000 {
528		compatible = "rockchip,rk3399-i2c";
529		reg = <0x0 0xff130000 0x0 0x1000>;
530		assigned-clocks = <&cru SCLK_I2C3>;
531		assigned-clock-rates = <200000000>;
532		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
533		clock-names = "i2c", "pclk";
534		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
535		pinctrl-names = "default";
536		pinctrl-0 = <&i2c3_xfer>;
537		#address-cells = <1>;
538		#size-cells = <0>;
539		status = "disabled";
540	};
541
542	i2c5: i2c@ff140000 {
543		compatible = "rockchip,rk3399-i2c";
544		reg = <0x0 0xff140000 0x0 0x1000>;
545		assigned-clocks = <&cru SCLK_I2C5>;
546		assigned-clock-rates = <200000000>;
547		clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
548		clock-names = "i2c", "pclk";
549		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
550		pinctrl-names = "default";
551		pinctrl-0 = <&i2c5_xfer>;
552		#address-cells = <1>;
553		#size-cells = <0>;
554		status = "disabled";
555	};
556
557	i2c6: i2c@ff150000 {
558		compatible = "rockchip,rk3399-i2c";
559		reg = <0x0 0xff150000 0x0 0x1000>;
560		assigned-clocks = <&cru SCLK_I2C6>;
561		assigned-clock-rates = <200000000>;
562		clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
563		clock-names = "i2c", "pclk";
564		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
565		pinctrl-names = "default";
566		pinctrl-0 = <&i2c6_xfer>;
567		#address-cells = <1>;
568		#size-cells = <0>;
569		status = "disabled";
570	};
571
572	i2c7: i2c@ff160000 {
573		compatible = "rockchip,rk3399-i2c";
574		reg = <0x0 0xff160000 0x0 0x1000>;
575		assigned-clocks = <&cru SCLK_I2C7>;
576		assigned-clock-rates = <200000000>;
577		clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
578		clock-names = "i2c", "pclk";
579		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
580		pinctrl-names = "default";
581		pinctrl-0 = <&i2c7_xfer>;
582		#address-cells = <1>;
583		#size-cells = <0>;
584		status = "disabled";
585	};
586
587	uart0: serial@ff180000 {
588		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
589		reg = <0x0 0xff180000 0x0 0x100>;
590		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
591		clock-names = "baudclk", "apb_pclk";
592		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
593		reg-shift = <2>;
594		reg-io-width = <4>;
595		pinctrl-names = "default";
596		pinctrl-0 = <&uart0_xfer>;
597		status = "disabled";
598	};
599
600	uart1: serial@ff190000 {
601		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
602		reg = <0x0 0xff190000 0x0 0x100>;
603		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
604		clock-names = "baudclk", "apb_pclk";
605		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
606		reg-shift = <2>;
607		reg-io-width = <4>;
608		pinctrl-names = "default";
609		pinctrl-0 = <&uart1_xfer>;
610		status = "disabled";
611	};
612
613	uart2: serial@ff1a0000 {
614		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615		reg = <0x0 0xff1a0000 0x0 0x100>;
616		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
617		clock-names = "baudclk", "apb_pclk";
618		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
619		clock-frequency = <24000000>;
620		reg-shift = <2>;
621		reg-io-width = <4>;
622		pinctrl-names = "default";
623		pinctrl-0 = <&uart2c_xfer>;
624		status = "disabled";
625	};
626
627	uart3: serial@ff1b0000 {
628		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
629		reg = <0x0 0xff1b0000 0x0 0x100>;
630		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
631		clock-names = "baudclk", "apb_pclk";
632		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
633		reg-shift = <2>;
634		reg-io-width = <4>;
635		pinctrl-names = "default";
636		pinctrl-0 = <&uart3_xfer>;
637		status = "disabled";
638	};
639
640	spi0: spi@ff1c0000 {
641		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
642		reg = <0x0 0xff1c0000 0x0 0x1000>;
643		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
644		clock-names = "spiclk", "apb_pclk";
645		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
646		pinctrl-names = "default";
647		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
648		#address-cells = <1>;
649		#size-cells = <0>;
650		status = "disabled";
651	};
652
653	spi1: spi@ff1d0000 {
654		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
655		reg = <0x0 0xff1d0000 0x0 0x1000>;
656		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
657		clock-names = "spiclk", "apb_pclk";
658		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
659		pinctrl-names = "default";
660		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
661		#address-cells = <1>;
662		#size-cells = <0>;
663		status = "disabled";
664	};
665
666	spi2: spi@ff1e0000 {
667		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
668		reg = <0x0 0xff1e0000 0x0 0x1000>;
669		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
670		clock-names = "spiclk", "apb_pclk";
671		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
672		pinctrl-names = "default";
673		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
674		#address-cells = <1>;
675		#size-cells = <0>;
676		status = "disabled";
677	};
678
679	spi4: spi@ff1f0000 {
680		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
681		reg = <0x0 0xff1f0000 0x0 0x1000>;
682		clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
683		clock-names = "spiclk", "apb_pclk";
684		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
685		pinctrl-names = "default";
686		pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
687		#address-cells = <1>;
688		#size-cells = <0>;
689		status = "disabled";
690	};
691
692	spi5: spi@ff200000 {
693		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
694		reg = <0x0 0xff200000 0x0 0x1000>;
695		clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
696		clock-names = "spiclk", "apb_pclk";
697		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
698		pinctrl-names = "default";
699		pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
700		#address-cells = <1>;
701		#size-cells = <0>;
702		status = "disabled";
703	};
704
705	thermal_zones: thermal-zones {
706		cpu_thermal: cpu {
707			polling-delay-passive = <100>;
708			polling-delay = <1000>;
709
710			thermal-sensors = <&tsadc 0>;
711
712			trips {
713				cpu_alert0: cpu_alert0 {
714					temperature = <70000>;
715					hysteresis = <2000>;
716					type = "passive";
717				};
718				cpu_alert1: cpu_alert1 {
719					temperature = <75000>;
720					hysteresis = <2000>;
721					type = "passive";
722				};
723				cpu_crit: cpu_crit {
724					temperature = <95000>;
725					hysteresis = <2000>;
726					type = "critical";
727				};
728			};
729
730			cooling-maps {
731				map0 {
732					trip = <&cpu_alert0>;
733					cooling-device =
734						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
735				};
736				map1 {
737					trip = <&cpu_alert1>;
738					cooling-device =
739						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
740						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
741				};
742			};
743		};
744
745		gpu_thermal: gpu {
746			polling-delay-passive = <100>;
747			polling-delay = <1000>;
748
749			thermal-sensors = <&tsadc 1>;
750
751			trips {
752				gpu_alert0: gpu_alert0 {
753					temperature = <75000>;
754					hysteresis = <2000>;
755					type = "passive";
756				};
757				gpu_crit: gpu_crit {
758					temperature = <95000>;
759					hysteresis = <2000>;
760					type = "critical";
761				};
762			};
763
764			cooling-maps {
765				map0 {
766					trip = <&gpu_alert0>;
767					cooling-device =
768						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
769				};
770			};
771		};
772	};
773
774	tsadc: tsadc@ff260000 {
775		compatible = "rockchip,rk3399-tsadc";
776		reg = <0x0 0xff260000 0x0 0x100>;
777		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
778		assigned-clocks = <&cru SCLK_TSADC>;
779		assigned-clock-rates = <750000>;
780		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
781		clock-names = "tsadc", "apb_pclk";
782		resets = <&cru SRST_TSADC>;
783		reset-names = "tsadc-apb";
784		rockchip,grf = <&grf>;
785		rockchip,hw-tshut-temp = <95000>;
786		pinctrl-names = "init", "default", "sleep";
787		pinctrl-0 = <&otp_gpio>;
788		pinctrl-1 = <&otp_out>;
789		pinctrl-2 = <&otp_gpio>;
790		#thermal-sensor-cells = <1>;
791		status = "disabled";
792	};
793
794	qos_emmc: qos@ffa58000 {
795		compatible = "syscon";
796		reg = <0x0 0xffa58000 0x0 0x20>;
797	};
798
799	qos_gmac: qos@ffa5c000 {
800		compatible = "syscon";
801		reg = <0x0 0xffa5c000 0x0 0x20>;
802	};
803
804	qos_pcie: qos@ffa60080 {
805		compatible = "syscon";
806		reg = <0x0 0xffa60080 0x0 0x20>;
807	};
808
809	qos_usb_host0: qos@ffa60100 {
810		compatible = "syscon";
811		reg = <0x0 0xffa60100 0x0 0x20>;
812	};
813
814	qos_usb_host1: qos@ffa60180 {
815		compatible = "syscon";
816		reg = <0x0 0xffa60180 0x0 0x20>;
817	};
818
819	qos_usb_otg0: qos@ffa70000 {
820		compatible = "syscon";
821		reg = <0x0 0xffa70000 0x0 0x20>;
822	};
823
824	qos_usb_otg1: qos@ffa70080 {
825		compatible = "syscon";
826		reg = <0x0 0xffa70080 0x0 0x20>;
827	};
828
829	qos_sd: qos@ffa74000 {
830		compatible = "syscon";
831		reg = <0x0 0xffa74000 0x0 0x20>;
832	};
833
834	qos_sdioaudio: qos@ffa76000 {
835		compatible = "syscon";
836		reg = <0x0 0xffa76000 0x0 0x20>;
837	};
838
839	qos_hdcp: qos@ffa90000 {
840		compatible = "syscon";
841		reg = <0x0 0xffa90000 0x0 0x20>;
842	};
843
844	qos_iep: qos@ffa98000 {
845		compatible = "syscon";
846		reg = <0x0 0xffa98000 0x0 0x20>;
847	};
848
849	qos_isp0_m0: qos@ffaa0000 {
850		compatible = "syscon";
851		reg = <0x0 0xffaa0000 0x0 0x20>;
852	};
853
854	qos_isp0_m1: qos@ffaa0080 {
855		compatible = "syscon";
856		reg = <0x0 0xffaa0080 0x0 0x20>;
857	};
858
859	qos_isp1_m0: qos@ffaa8000 {
860		compatible = "syscon";
861		reg = <0x0 0xffaa8000 0x0 0x20>;
862	};
863
864	qos_isp1_m1: qos@ffaa8080 {
865		compatible = "syscon";
866		reg = <0x0 0xffaa8080 0x0 0x20>;
867	};
868
869	qos_rga_r: qos@ffab0000 {
870		compatible = "syscon";
871		reg = <0x0 0xffab0000 0x0 0x20>;
872	};
873
874	qos_rga_w: qos@ffab0080 {
875		compatible = "syscon";
876		reg = <0x0 0xffab0080 0x0 0x20>;
877	};
878
879	qos_video_m0: qos@ffab8000 {
880		compatible = "syscon";
881		reg = <0x0 0xffab8000 0x0 0x20>;
882	};
883
884	qos_video_m1_r: qos@ffac0000 {
885		compatible = "syscon";
886		reg = <0x0 0xffac0000 0x0 0x20>;
887	};
888
889	qos_video_m1_w: qos@ffac0080 {
890		compatible = "syscon";
891		reg = <0x0 0xffac0080 0x0 0x20>;
892	};
893
894	qos_vop_big_r: qos@ffac8000 {
895		compatible = "syscon";
896		reg = <0x0 0xffac8000 0x0 0x20>;
897	};
898
899	qos_vop_big_w: qos@ffac8080 {
900		compatible = "syscon";
901		reg = <0x0 0xffac8080 0x0 0x20>;
902	};
903
904	qos_vop_little: qos@ffad0000 {
905		compatible = "syscon";
906		reg = <0x0 0xffad0000 0x0 0x20>;
907	};
908
909	qos_perihp: qos@ffad8080 {
910		compatible = "syscon";
911		reg = <0x0 0xffad8080 0x0 0x20>;
912	};
913
914	qos_gpu: qos@ffae0000 {
915		compatible = "syscon";
916		reg = <0x0 0xffae0000 0x0 0x20>;
917	};
918
919	pmu: power-management@ff310000 {
920		compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
921		reg = <0x0 0xff310000 0x0 0x1000>;
922
923		/*
924		 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
925		 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
926		 * Some of the power domains are grouped together for every
927		 * voltage domain.
928		 * The detail contents as below.
929		 */
930		power: power-controller {
931			compatible = "rockchip,rk3399-power-controller";
932			#power-domain-cells = <1>;
933			#address-cells = <1>;
934			#size-cells = <0>;
935
936			/* These power domains are grouped by VD_CENTER */
937			pd_iep@RK3399_PD_IEP {
938				reg = <RK3399_PD_IEP>;
939				clocks = <&cru ACLK_IEP>,
940					 <&cru HCLK_IEP>;
941				pm_qos = <&qos_iep>;
942			};
943			pd_rga@RK3399_PD_RGA {
944				reg = <RK3399_PD_RGA>;
945				clocks = <&cru ACLK_RGA>,
946					 <&cru HCLK_RGA>;
947				pm_qos = <&qos_rga_r>,
948					 <&qos_rga_w>;
949			};
950			pd_vcodec@RK3399_PD_VCODEC {
951				reg = <RK3399_PD_VCODEC>;
952				clocks = <&cru ACLK_VCODEC>,
953					 <&cru HCLK_VCODEC>;
954				pm_qos = <&qos_video_m0>;
955			};
956			pd_vdu@RK3399_PD_VDU {
957				reg = <RK3399_PD_VDU>;
958				clocks = <&cru ACLK_VDU>,
959					 <&cru HCLK_VDU>;
960				pm_qos = <&qos_video_m1_r>,
961					 <&qos_video_m1_w>;
962			};
963
964			/* These power domains are grouped by VD_GPU */
965			pd_gpu@RK3399_PD_GPU {
966				reg = <RK3399_PD_GPU>;
967				clocks = <&cru ACLK_GPU>;
968				pm_qos = <&qos_gpu>;
969			};
970
971			/* These power domains are grouped by VD_LOGIC */
972			pd_edp@RK3399_PD_EDP {
973				reg = <RK3399_PD_EDP>;
974				clocks = <&cru PCLK_EDP_CTRL>;
975			};
976			pd_emmc@RK3399_PD_EMMC {
977				reg = <RK3399_PD_EMMC>;
978				clocks = <&cru ACLK_EMMC>;
979				pm_qos = <&qos_emmc>;
980			};
981			pd_gmac@RK3399_PD_GMAC {
982				reg = <RK3399_PD_GMAC>;
983				clocks = <&cru ACLK_GMAC>,
984					 <&cru PCLK_GMAC>;
985				pm_qos = <&qos_gmac>;
986			};
987			pd_perihp@RK3399_PD_PERIHP {
988				reg = <RK3399_PD_PERIHP>;
989				#address-cells = <1>;
990				#size-cells = <0>;
991				clocks = <&cru ACLK_PERIHP>;
992				pm_qos = <&qos_perihp>,
993					 <&qos_pcie>,
994					 <&qos_usb_host0>,
995					 <&qos_usb_host1>;
996
997				pd_sd@RK3399_PD_SD {
998					reg = <RK3399_PD_SD>;
999					clocks = <&cru HCLK_SDMMC>,
1000						 <&cru SCLK_SDMMC>;
1001					pm_qos = <&qos_sd>;
1002				};
1003			};
1004			pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1005				reg = <RK3399_PD_SDIOAUDIO>;
1006				clocks = <&cru HCLK_SDIO>;
1007				pm_qos = <&qos_sdioaudio>;
1008			};
1009			pd_usb3@RK3399_PD_USB3 {
1010				reg = <RK3399_PD_USB3>;
1011				clocks = <&cru ACLK_USB3>;
1012				pm_qos = <&qos_usb_otg0>,
1013					 <&qos_usb_otg1>;
1014			};
1015			pd_vio@RK3399_PD_VIO {
1016				reg = <RK3399_PD_VIO>;
1017				#address-cells = <1>;
1018				#size-cells = <0>;
1019
1020				pd_hdcp@RK3399_PD_HDCP {
1021					reg = <RK3399_PD_HDCP>;
1022					clocks = <&cru ACLK_HDCP>,
1023						 <&cru HCLK_HDCP>,
1024						 <&cru PCLK_HDCP>;
1025					pm_qos = <&qos_hdcp>;
1026				};
1027				pd_isp0@RK3399_PD_ISP0 {
1028					reg = <RK3399_PD_ISP0>;
1029					clocks = <&cru ACLK_ISP0>,
1030						 <&cru HCLK_ISP0>;
1031					pm_qos = <&qos_isp0_m0>,
1032						 <&qos_isp0_m1>;
1033				};
1034				pd_isp1@RK3399_PD_ISP1 {
1035					reg = <RK3399_PD_ISP1>;
1036					clocks = <&cru ACLK_ISP1>,
1037						 <&cru HCLK_ISP1>;
1038					pm_qos = <&qos_isp1_m0>,
1039						 <&qos_isp1_m1>;
1040				};
1041				pd_tcpc0@RK3399_PD_TCPC0 {
1042					reg = <RK3399_PD_TCPD0>;
1043					clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1044						 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1045				};
1046				pd_tcpc1@RK3399_PD_TCPC1 {
1047					reg = <RK3399_PD_TCPD1>;
1048					clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1049						 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1050				};
1051				pd_vo@RK3399_PD_VO {
1052					reg = <RK3399_PD_VO>;
1053					#address-cells = <1>;
1054					#size-cells = <0>;
1055
1056					pd_vopb@RK3399_PD_VOPB {
1057						reg = <RK3399_PD_VOPB>;
1058						clocks = <&cru ACLK_VOP0>,
1059							 <&cru HCLK_VOP0>;
1060						pm_qos = <&qos_vop_big_r>,
1061							 <&qos_vop_big_w>;
1062					};
1063					pd_vopl@RK3399_PD_VOPL {
1064						reg = <RK3399_PD_VOPL>;
1065						clocks = <&cru ACLK_VOP1>,
1066							 <&cru HCLK_VOP1>;
1067						pm_qos = <&qos_vop_little>;
1068					};
1069				};
1070			};
1071		};
1072	};
1073
1074	pmugrf: syscon@ff320000 {
1075		u-boot,dm-pre-reloc;
1076		compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1077		reg = <0x0 0xff320000 0x0 0x1000>;
1078
1079		pmu_io_domains: io-domains {
1080			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1081			status = "disabled";
1082		};
1083	};
1084
1085	pmusgrf: syscon@ff330000 {
1086		u-boot,dm-pre-reloc;
1087		compatible = "rockchip,rk3399-pmusgrf", "syscon";
1088		reg = <0x0 0xff330000 0x0 0xe3d4>;
1089	};
1090
1091	spi3: spi@ff350000 {
1092		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1093		reg = <0x0 0xff350000 0x0 0x1000>;
1094		clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1095		clock-names = "spiclk", "apb_pclk";
1096		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1097		pinctrl-names = "default";
1098		pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1099		#address-cells = <1>;
1100		#size-cells = <0>;
1101		status = "disabled";
1102	};
1103
1104	uart4: serial@ff370000 {
1105		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1106		reg = <0x0 0xff370000 0x0 0x100>;
1107		clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1108		clock-names = "baudclk", "apb_pclk";
1109		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1110		reg-shift = <2>;
1111		reg-io-width = <4>;
1112		pinctrl-names = "default";
1113		pinctrl-0 = <&uart4_xfer>;
1114		status = "disabled";
1115	};
1116
1117	i2c0: i2c@ff3c0000 {
1118		compatible = "rockchip,rk3399-i2c";
1119		reg = <0x0 0xff3c0000 0x0 0x1000>;
1120		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1121		assigned-clock-rates = <200000000>;
1122		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1123		clock-names = "i2c", "pclk";
1124		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1125		pinctrl-names = "default";
1126		pinctrl-0 = <&i2c0_xfer>;
1127		#address-cells = <1>;
1128		#size-cells = <0>;
1129		status = "disabled";
1130	};
1131
1132	i2c4: i2c@ff3d0000 {
1133		compatible = "rockchip,rk3399-i2c";
1134		reg = <0x0 0xff3d0000 0x0 0x1000>;
1135		assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1136		assigned-clock-rates = <200000000>;
1137		clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1138		clock-names = "i2c", "pclk";
1139		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1140		pinctrl-names = "default";
1141		pinctrl-0 = <&i2c4_xfer>;
1142		#address-cells = <1>;
1143		#size-cells = <0>;
1144		status = "disabled";
1145	};
1146
1147	i2c8: i2c@ff3e0000 {
1148		compatible = "rockchip,rk3399-i2c";
1149		reg = <0x0 0xff3e0000 0x0 0x1000>;
1150		assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1151		assigned-clock-rates = <200000000>;
1152		clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1153		clock-names = "i2c", "pclk";
1154		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1155		pinctrl-names = "default";
1156		pinctrl-0 = <&i2c8_xfer>;
1157		#address-cells = <1>;
1158		#size-cells = <0>;
1159		status = "disabled";
1160	};
1161
1162	pwm0: pwm@ff420000 {
1163		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1164		reg = <0x0 0xff420000 0x0 0x10>;
1165		#pwm-cells = <3>;
1166		pinctrl-names = "default";
1167		pinctrl-0 = <&pwm0_pin>;
1168		clocks = <&pmucru PCLK_RKPWM_PMU>;
1169		clock-names = "pwm";
1170		status = "disabled";
1171	};
1172
1173	pwm1: pwm@ff420010 {
1174		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1175		reg = <0x0 0xff420010 0x0 0x10>;
1176		#pwm-cells = <3>;
1177		pinctrl-names = "default";
1178		pinctrl-0 = <&pwm1_pin>;
1179		clocks = <&pmucru PCLK_RKPWM_PMU>;
1180		clock-names = "pwm";
1181		status = "disabled";
1182	};
1183
1184	pwm2: pwm@ff420020 {
1185		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1186		reg = <0x0 0xff420020 0x0 0x10>;
1187		#pwm-cells = <3>;
1188		pinctrl-names = "default";
1189		pinctrl-0 = <&pwm2_pin>;
1190		clocks = <&pmucru PCLK_RKPWM_PMU>;
1191		clock-names = "pwm";
1192		status = "disabled";
1193	};
1194
1195	pwm3: pwm@ff420030 {
1196		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1197		reg = <0x0 0xff420030 0x0 0x10>;
1198		#pwm-cells = <3>;
1199		pinctrl-names = "default";
1200		pinctrl-0 = <&pwm3a_pin>;
1201		clocks = <&pmucru PCLK_RKPWM_PMU>;
1202		clock-names = "pwm";
1203		status = "disabled";
1204	};
1205
1206	cic: syscon@ff620000 {
1207		u-boot,dm-pre-reloc;
1208		compatible = "rockchip,rk3399-cic", "syscon";
1209		reg = <0x0 0xff620000 0x0 0x100>;
1210	};
1211
1212	dfi: dfi@ff630000 {
1213		reg = <0x00 0xff630000 0x00 0x4000>;
1214		compatible = "rockchip,rk3399-dfi";
1215		rockchip,pmu = <&pmugrf>;
1216		clocks = <&cru PCLK_DDR_MON>;
1217		clock-names = "pclk_ddr_mon";
1218		status = "disabled";
1219	};
1220
1221	dmc: dmc {
1222		u-boot,dm-pre-reloc;
1223		compatible = "rockchip,rk3399-dmc";
1224		devfreq-events = <&dfi>;
1225		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1226		clocks = <&cru SCLK_DDRCLK>;
1227		clock-names = "dmc_clk";
1228		reg = <0x0 0xffa80000 0x0 0x0800
1229		       0x0 0xffa80800 0x0 0x1800
1230		       0x0 0xffa82000 0x0 0x2000
1231		       0x0 0xffa84000 0x0 0x1000
1232		       0x0 0xffa88000 0x0 0x0800
1233		       0x0 0xffa88800 0x0 0x1800
1234		       0x0 0xffa8a000 0x0 0x2000
1235		       0x0 0xffa8c000 0x0 0x1000>;
1236	};
1237
1238	efuse0: efuse@ff690000 {
1239		compatible = "rockchip,rk3399-efuse";
1240		reg = <0x0 0xff690000 0x0 0x80>;
1241		#address-cells = <1>;
1242		#size-cells = <1>;
1243		clocks = <&cru PCLK_EFUSE1024NS>;
1244		clock-names = "pclk_efuse";
1245
1246		/* Data cells */
1247		cpu_id: cpu-id@7 {
1248			reg = <0x07 0x10>;
1249		};
1250		cpub_leakage: cpu-leakage@17 {
1251			reg = <0x17 0x1>;
1252		};
1253		gpu_leakage: gpu-leakage@18 {
1254			reg = <0x18 0x1>;
1255		};
1256		center_leakage: center-leakage@19 {
1257			reg = <0x19 0x1>;
1258		};
1259		cpul_leakage: cpu-leakage@1a {
1260			reg = <0x1a 0x1>;
1261		};
1262		logic_leakage: logic-leakage@1b {
1263			reg = <0x1b 0x1>;
1264		};
1265		wafer_info: wafer-info@1c {
1266			reg = <0x1c 0x1>;
1267		};
1268	};
1269
1270	pmucru: pmu-clock-controller@ff750000 {
1271		u-boot,dm-pre-reloc;
1272		compatible = "rockchip,rk3399-pmucru";
1273		reg = <0x0 0xff750000 0x0 0x1000>;
1274		rockchip,grf = <&pmugrf>;
1275		#clock-cells = <1>;
1276		#reset-cells = <1>;
1277		assigned-clocks = <&pmucru PLL_PPLL>;
1278		assigned-clock-rates = <676000000>;
1279	};
1280
1281	cru: clock-controller@ff760000 {
1282		u-boot,dm-pre-reloc;
1283		compatible = "rockchip,rk3399-cru";
1284		reg = <0x0 0xff760000 0x0 0x1000>;
1285		rockchip,grf = <&grf>;
1286		#clock-cells = <1>;
1287		#reset-cells = <1>;
1288		assigned-clocks =
1289			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
1290			<&cru PLL_NPLL>,
1291			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1292			<&cru PCLK_PERIHP>,
1293			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1294			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1295			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1296			<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1297			<&cru ACLK_GIC_PRE>,
1298			<&cru PCLK_DDR>;
1299		assigned-clock-rates =
1300			 <594000000>,  <800000000>,
1301			<1000000000>,
1302			 <150000000>,   <75000000>,
1303			  <37500000>,
1304			 <100000000>,  <100000000>,
1305			  <50000000>, <600000000>,
1306			 <100000000>,   <50000000>,
1307			 <400000000>, <400000000>,
1308			 <200000000>,
1309			 <200000000>;
1310	};
1311
1312	grf: syscon@ff770000 {
1313		u-boot,dm-pre-reloc;
1314		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1315		reg = <0x0 0xff770000 0x0 0x10000>;
1316		#address-cells = <1>;
1317		#size-cells = <1>;
1318
1319		io_domains: io-domains {
1320			compatible = "rockchip,rk3399-io-voltage-domain";
1321			status = "disabled";
1322		};
1323
1324		u2phy0: usb2-phy@e450 {
1325			compatible = "rockchip,rk3399-usb2phy";
1326			reg = <0xe450 0x10>;
1327			clocks = <&cru SCLK_USB2PHY0_REF>;
1328			clock-names = "phyclk";
1329			#clock-cells = <0>;
1330			clock-output-names = "clk_usbphy0_480m";
1331			status = "disabled";
1332
1333			u2phy0_host: host-port {
1334				#phy-cells = <0>;
1335				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1336				interrupt-names = "linestate";
1337				status = "disabled";
1338			};
1339
1340			u2phy0_otg: otg-port {
1341				#phy-cells = <0>;
1342				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1343					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1344					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1345				interrupt-names = "otg-bvalid", "otg-id",
1346						  "linestate";
1347				status = "disabled";
1348			};
1349		};
1350
1351		u2phy1: usb2-phy@e460 {
1352			compatible = "rockchip,rk3399-usb2phy";
1353			reg = <0xe460 0x10>;
1354			clocks = <&cru SCLK_USB2PHY1_REF>;
1355			clock-names = "phyclk";
1356			#clock-cells = <0>;
1357			clock-output-names = "clk_usbphy1_480m";
1358			status = "disabled";
1359
1360			u2phy1_host: host-port {
1361				#phy-cells = <0>;
1362				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1363				interrupt-names = "linestate";
1364				status = "disabled";
1365			};
1366
1367			u2phy1_otg: otg-port {
1368				#phy-cells = <0>;
1369				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1370					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1371					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1372				interrupt-names = "otg-bvalid", "otg-id",
1373						  "linestate";
1374				status = "disabled";
1375			};
1376		};
1377
1378		emmc_phy: phy@f780 {
1379			compatible = "rockchip,rk3399-emmc-phy";
1380			reg = <0xf780 0x24>;
1381			clocks = <&sdhci>;
1382			clock-names = "emmcclk";
1383			#phy-cells = <0>;
1384			status = "disabled";
1385		};
1386
1387		pcie_phy: pcie-phy {
1388			compatible = "rockchip,rk3399-pcie-phy";
1389			clocks = <&cru SCLK_PCIEPHY_REF>;
1390			clock-names = "refclk";
1391			#phy-cells = <0>;
1392			resets = <&cru SRST_PCIEPHY>;
1393			reset-names = "phy";
1394			status = "disabled";
1395		};
1396	};
1397
1398	tcphy0: phy@ff7c0000 {
1399		compatible = "rockchip,rk3399-typec-phy";
1400		reg = <0x0 0xff7c0000 0x0 0x40000>;
1401		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1402			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1403		clock-names = "tcpdcore", "tcpdphy-ref";
1404		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1405		assigned-clock-rates = <50000000>;
1406		power-domains = <&power RK3399_PD_TCPD0>;
1407		resets = <&cru SRST_UPHY0>,
1408			 <&cru SRST_UPHY0_PIPE_L00>,
1409			 <&cru SRST_P_UPHY0_TCPHY>;
1410		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1411		rockchip,grf = <&grf>;
1412		status = "disabled";
1413
1414		tcphy0_dp: dp-port {
1415			#phy-cells = <0>;
1416		};
1417
1418		tcphy0_usb3: usb3-port {
1419			#phy-cells = <0>;
1420		};
1421	};
1422
1423	tcphy1: phy@ff800000 {
1424		compatible = "rockchip,rk3399-typec-phy";
1425		reg = <0x0 0xff800000 0x0 0x40000>;
1426		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1427			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1428		clock-names = "tcpdcore", "tcpdphy-ref";
1429		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1430		assigned-clock-rates = <50000000>;
1431		power-domains = <&power RK3399_PD_TCPD1>;
1432		resets = <&cru SRST_UPHY1>,
1433			 <&cru SRST_UPHY1_PIPE_L00>,
1434			 <&cru SRST_P_UPHY1_TCPHY>;
1435		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1436		rockchip,grf = <&grf>;
1437		status = "disabled";
1438
1439		tcphy1_dp: dp-port {
1440			#phy-cells = <0>;
1441		};
1442
1443		tcphy1_usb3: usb3-port {
1444			#phy-cells = <0>;
1445		};
1446	};
1447
1448	watchdog@ff848000 {
1449		compatible = "snps,dw-wdt";
1450		reg = <0x0 0xff848000 0x0 0x100>;
1451		clocks = <&cru PCLK_WDT>;
1452		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1453	};
1454
1455	rktimer: rktimer@ff850000 {
1456		compatible = "rockchip,rk3399-timer";
1457		reg = <0x0 0xff850000 0x0 0x1000>;
1458		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1459		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1460		clock-names = "pclk", "timer";
1461	};
1462
1463	spdif: spdif@ff870000 {
1464		compatible = "rockchip,rk3399-spdif";
1465		reg = <0x0 0xff870000 0x0 0x1000>;
1466		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1467		dmas = <&dmac_bus 7>;
1468		dma-names = "tx";
1469		clock-names = "mclk", "hclk";
1470		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1471		pinctrl-names = "default";
1472		pinctrl-0 = <&spdif_bus>;
1473		power-domains = <&power RK3399_PD_SDIOAUDIO>;
1474		#sound-dai-cells = <0>;
1475		status = "disabled";
1476	};
1477
1478	i2s0: i2s@ff880000 {
1479		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1480		reg = <0x0 0xff880000 0x0 0x1000>;
1481		rockchip,grf = <&grf>;
1482		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1483		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1484		dma-names = "tx", "rx";
1485		clock-names = "i2s_clk", "i2s_hclk";
1486		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1487		pinctrl-names = "default";
1488		pinctrl-0 = <&i2s0_8ch_bus>;
1489		power-domains = <&power RK3399_PD_SDIOAUDIO>;
1490		#sound-dai-cells = <0>;
1491		status = "disabled";
1492	};
1493
1494	i2s1: i2s@ff890000 {
1495		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1496		reg = <0x0 0xff890000 0x0 0x1000>;
1497		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1498		dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1499		dma-names = "tx", "rx";
1500		clock-names = "i2s_clk", "i2s_hclk";
1501		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1502		pinctrl-names = "default";
1503		pinctrl-0 = <&i2s1_2ch_bus>;
1504		power-domains = <&power RK3399_PD_SDIOAUDIO>;
1505		#sound-dai-cells = <0>;
1506		status = "disabled";
1507	};
1508
1509	i2s2: i2s@ff8a0000 {
1510		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1511		reg = <0x0 0xff8a0000 0x0 0x1000>;
1512		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1513		dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1514		dma-names = "tx", "rx";
1515		clock-names = "i2s_clk", "i2s_hclk";
1516		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1517		power-domains = <&power RK3399_PD_SDIOAUDIO>;
1518		#sound-dai-cells = <0>;
1519		status = "disabled";
1520	};
1521
1522	vopl: vop@ff8f0000 {
1523		u-boot,dm-pre-reloc;
1524		compatible = "rockchip,rk3399-vop-lit";
1525		reg = <0x0 0xff8f0000 0x0 0x3efc>;
1526		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1527		assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1528		assigned-clock-rates = <400000000>, <100000000>;
1529		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1530		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1531		iommus = <&vopl_mmu>;
1532		power-domains = <&power RK3399_PD_VOPL>;
1533		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1534		reset-names = "axi", "ahb", "dclk";
1535		status = "disabled";
1536
1537		vopl_out: port {
1538			#address-cells = <1>;
1539			#size-cells = <0>;
1540
1541			vopl_out_mipi: endpoint@0 {
1542				reg = <0>;
1543				remote-endpoint = <&mipi_in_vopl>;
1544			};
1545
1546			vopl_out_edp: endpoint@1 {
1547				reg = <1>;
1548				remote-endpoint = <&edp_in_vopl>;
1549			};
1550
1551			vopl_out_hdmi: endpoint@2 {
1552				reg = <2>;
1553				remote-endpoint = <&hdmi_in_vopl>;
1554			};
1555
1556			vopl_out_mipi1: endpoint@3 {
1557				reg = <3>;
1558				remote-endpoint = <&mipi1_in_vopl>;
1559			};
1560
1561			vopl_out_dp: endpoint@4 {
1562				reg = <4>;
1563				remote-endpoint = <&dp_in_vopl>;
1564			};
1565		};
1566	};
1567
1568	vopl_mmu: iommu@ff8f3f00 {
1569		compatible = "rockchip,iommu";
1570		reg = <0x0 0xff8f3f00 0x0 0x100>;
1571		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1572		interrupt-names = "vopl_mmu";
1573		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1574		clock-names = "aclk", "iface";
1575		power-domains = <&power RK3399_PD_VOPL>;
1576		#iommu-cells = <0>;
1577		status = "disabled";
1578	};
1579
1580	vopb: vop@ff900000 {
1581		u-boot,dm-pre-reloc;
1582		compatible = "rockchip,rk3399-vop-big";
1583		reg = <0x0 0xff900000 0x0 0x3efc>;
1584		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1585		assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1586		assigned-clock-rates = <400000000>, <100000000>;
1587		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1588		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1589		iommus = <&vopb_mmu>;
1590		power-domains = <&power RK3399_PD_VOPB>;
1591		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1592		reset-names = "axi", "ahb", "dclk";
1593		status = "disabled";
1594
1595		vopb_out: port {
1596			#address-cells = <1>;
1597			#size-cells = <0>;
1598
1599			vopb_out_edp: endpoint@0 {
1600				reg = <0>;
1601				remote-endpoint = <&edp_in_vopb>;
1602			};
1603
1604			vopb_out_mipi: endpoint@1 {
1605				reg = <1>;
1606				remote-endpoint = <&mipi_in_vopb>;
1607			};
1608
1609			vopb_out_hdmi: endpoint@2 {
1610				reg = <2>;
1611				remote-endpoint = <&hdmi_in_vopb>;
1612			};
1613
1614			vopb_out_mipi1: endpoint@3 {
1615				reg = <3>;
1616				remote-endpoint = <&mipi1_in_vopb>;
1617			};
1618
1619			vopb_out_dp: endpoint@4 {
1620				reg = <4>;
1621				remote-endpoint = <&dp_in_vopb>;
1622			};
1623		};
1624	};
1625
1626	vopb_mmu: iommu@ff903f00 {
1627		compatible = "rockchip,iommu";
1628		reg = <0x0 0xff903f00 0x0 0x100>;
1629		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1630		interrupt-names = "vopb_mmu";
1631		clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1632		clock-names = "aclk", "iface";
1633		power-domains = <&power RK3399_PD_VOPB>;
1634		#iommu-cells = <0>;
1635		status = "disabled";
1636	};
1637
1638	isp0_mmu: iommu@ff914000 {
1639		compatible = "rockchip,iommu";
1640		reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1641		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1642		interrupt-names = "isp0_mmu";
1643		clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1644		clock-names = "aclk", "iface";
1645		#iommu-cells = <0>;
1646		rockchip,disable-mmu-reset;
1647		status = "disabled";
1648	};
1649
1650	isp1_mmu: iommu@ff924000 {
1651		compatible = "rockchip,iommu";
1652		reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1653		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1654		interrupt-names = "isp1_mmu";
1655		clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1656		clock-names = "aclk", "iface";
1657		#iommu-cells = <0>;
1658		rockchip,disable-mmu-reset;
1659		status = "disabled";
1660	};
1661
1662	hdmi_sound: hdmi-sound {
1663		compatible = "simple-audio-card";
1664		simple-audio-card,format = "i2s";
1665		simple-audio-card,mclk-fs = <256>;
1666		simple-audio-card,name = "hdmi-sound";
1667		status = "disabled";
1668
1669		simple-audio-card,cpu {
1670			sound-dai = <&i2s2>;
1671		};
1672		simple-audio-card,codec {
1673			sound-dai = <&hdmi>;
1674		};
1675	};
1676
1677	hdmi: hdmi@ff940000 {
1678		compatible = "rockchip,rk3399-dw-hdmi";
1679		reg = <0x0 0xff940000 0x0 0x20000>;
1680		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1681		clocks = <&cru PCLK_HDMI_CTRL>,
1682			 <&cru SCLK_HDMI_SFR>,
1683			 <&cru PLL_VPLL>,
1684			 <&cru PCLK_VIO_GRF>,
1685			 <&cru SCLK_HDMI_CEC>;
1686		clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1687		power-domains = <&power RK3399_PD_HDCP>;
1688		reg-io-width = <4>;
1689		rockchip,grf = <&grf>;
1690		#sound-dai-cells = <0>;
1691		status = "disabled";
1692
1693		ports {
1694			hdmi_in: port {
1695				#address-cells = <1>;
1696				#size-cells = <0>;
1697
1698				hdmi_in_vopb: endpoint@0 {
1699					reg = <0>;
1700					remote-endpoint = <&vopb_out_hdmi>;
1701				};
1702				hdmi_in_vopl: endpoint@1 {
1703					reg = <1>;
1704					remote-endpoint = <&vopl_out_hdmi>;
1705				};
1706			};
1707		};
1708	};
1709
1710	mipi_dsi: mipi@ff960000 {
1711		compatible = "rockchip,rk3399_mipi_dsi";
1712		reg = <0x0 0xff960000 0x0 0x8000>;
1713		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1714		clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1715		         <&cru SCLK_DPHY_TX0_CFG>;
1716		clock-names = "ref", "pclk", "phy_cfg";
1717		rockchip,grf = <&grf>;
1718		#address-cells = <1>;
1719		#size-cells = <0>;
1720		status = "disabled";
1721		ports {
1722			reg = <1>;
1723			mipi_in: port {
1724				#address-cells = <1>;
1725				#size-cells = <0>;
1726				mipi_in_vopb: endpoint@0 {
1727					reg = <0>;
1728					remote-endpoint = <&vopb_out_mipi>;
1729				};
1730				mipi_in_vopl: endpoint@1 {
1731					reg = <1>;
1732					remote-endpoint = <&vopl_out_mipi>;
1733				};
1734			};
1735		};
1736	};
1737
1738	mipi_dsi1: mipi@ff968000 {
1739		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1740		reg = <0x0 0xff968000 0x0 0x8000>;
1741		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1742		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1743			 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1744		clock-names = "ref", "pclk", "phy_cfg", "grf";
1745		power-domains = <&power RK3399_PD_VIO>;
1746		resets = <&cru SRST_P_MIPI_DSI1>;
1747		reset-names = "apb";
1748		rockchip,grf = <&grf>;
1749		status = "disabled";
1750
1751		ports {
1752			#address-cells = <1>;
1753			#size-cells = <0>;
1754
1755			mipi1_in: port@0 {
1756				reg = <0>;
1757				#address-cells = <1>;
1758				#size-cells = <0>;
1759
1760				mipi1_in_vopb: endpoint@0 {
1761					reg = <0>;
1762					remote-endpoint = <&vopb_out_mipi1>;
1763				};
1764
1765				mipi1_in_vopl: endpoint@1 {
1766					reg = <1>;
1767					remote-endpoint = <&vopl_out_mipi1>;
1768				};
1769			};
1770		};
1771	};
1772
1773	edp: edp@ff970000 {
1774		compatible = "rockchip,rk3399-edp";
1775		reg = <0x0 0xff970000 0x0 0x8000>;
1776		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1777		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1778		clock-names = "dp", "pclk", "grf";
1779		pinctrl-names = "default";
1780		pinctrl-0 = <&edp_hpd>;
1781		power-domains = <&power RK3399_PD_EDP>;
1782		resets = <&cru SRST_P_EDP_CTRL>;
1783		reset-names = "dp";
1784		rockchip,grf = <&grf>;
1785		status = "disabled";
1786
1787		ports {
1788			#address-cells = <1>;
1789			#size-cells = <0>;
1790			edp_in: port@0 {
1791				reg = <0>;
1792				#address-cells = <1>;
1793				#size-cells = <0>;
1794
1795				edp_in_vopb: endpoint@0 {
1796					reg = <0>;
1797					remote-endpoint = <&vopb_out_edp>;
1798				};
1799
1800				edp_in_vopl: endpoint@1 {
1801					reg = <1>;
1802					remote-endpoint = <&vopl_out_edp>;
1803				};
1804			};
1805		};
1806	};
1807
1808	gpu: gpu@ff9a0000 {
1809		compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1810		reg = <0x0 0xff9a0000 0x0 0x10000>;
1811		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1812			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1813			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1814		interrupt-names = "gpu", "job", "mmu";
1815		clocks = <&cru ACLK_GPU>;
1816		power-domains = <&power RK3399_PD_GPU>;
1817		status = "disabled";
1818	};
1819
1820	pinctrl: pinctrl {
1821		u-boot,dm-pre-reloc;
1822		compatible = "rockchip,rk3399-pinctrl";
1823		rockchip,grf = <&grf>;
1824		rockchip,pmu = <&pmugrf>;
1825		#address-cells = <2>;
1826		#size-cells = <2>;
1827		ranges;
1828
1829		gpio0: gpio0@ff720000 {
1830			compatible = "rockchip,gpio-bank";
1831			reg = <0x0 0xff720000 0x0 0x100>;
1832			clocks = <&pmucru PCLK_GPIO0_PMU>;
1833			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1834
1835			gpio-controller;
1836			#gpio-cells = <0x2>;
1837
1838			interrupt-controller;
1839			#interrupt-cells = <0x2>;
1840		};
1841
1842		gpio1: gpio1@ff730000 {
1843			compatible = "rockchip,gpio-bank";
1844			reg = <0x0 0xff730000 0x0 0x100>;
1845			clocks = <&pmucru PCLK_GPIO1_PMU>;
1846			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1847
1848			gpio-controller;
1849			#gpio-cells = <0x2>;
1850
1851			interrupt-controller;
1852			#interrupt-cells = <0x2>;
1853		};
1854
1855		gpio2: gpio2@ff780000 {
1856			compatible = "rockchip,gpio-bank";
1857			reg = <0x0 0xff780000 0x0 0x100>;
1858			clocks = <&cru PCLK_GPIO2>;
1859			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1860
1861			gpio-controller;
1862			#gpio-cells = <0x2>;
1863
1864			interrupt-controller;
1865			#interrupt-cells = <0x2>;
1866		};
1867
1868		gpio3: gpio3@ff788000 {
1869			compatible = "rockchip,gpio-bank";
1870			reg = <0x0 0xff788000 0x0 0x100>;
1871			clocks = <&cru PCLK_GPIO3>;
1872			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1873
1874			gpio-controller;
1875			#gpio-cells = <0x2>;
1876
1877			interrupt-controller;
1878			#interrupt-cells = <0x2>;
1879		};
1880
1881		gpio4: gpio4@ff790000 {
1882			compatible = "rockchip,gpio-bank";
1883			reg = <0x0 0xff790000 0x0 0x100>;
1884			clocks = <&cru PCLK_GPIO4>;
1885			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1886
1887			gpio-controller;
1888			#gpio-cells = <0x2>;
1889
1890			interrupt-controller;
1891			#interrupt-cells = <0x2>;
1892		};
1893
1894		pcfg_pull_up: pcfg-pull-up {
1895			bias-pull-up;
1896		};
1897
1898		pcfg_pull_down: pcfg-pull-down {
1899			bias-pull-down;
1900		};
1901
1902		pcfg_pull_none: pcfg-pull-none {
1903			bias-disable;
1904		};
1905
1906		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1907			bias-disable;
1908			drive-strength = <12>;
1909		};
1910
1911		pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1912			bias-disable;
1913			drive-strength = <13>;
1914		};
1915
1916		pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1917			bias-disable;
1918			drive-strength = <18>;
1919		};
1920
1921		pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1922			bias-disable;
1923			drive-strength = <20>;
1924		};
1925
1926		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1927			bias-pull-up;
1928			drive-strength = <2>;
1929		};
1930
1931		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1932			bias-pull-up;
1933			drive-strength = <8>;
1934		};
1935
1936		pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1937			bias-pull-up;
1938			drive-strength = <18>;
1939		};
1940
1941		pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1942			bias-pull-up;
1943			drive-strength = <20>;
1944		};
1945
1946		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1947			bias-pull-down;
1948			drive-strength = <4>;
1949		};
1950
1951		pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1952			bias-pull-down;
1953			drive-strength = <8>;
1954		};
1955
1956		pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1957			bias-pull-down;
1958			drive-strength = <12>;
1959		};
1960
1961		pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1962			bias-pull-down;
1963			drive-strength = <18>;
1964		};
1965
1966		pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1967			bias-pull-down;
1968			drive-strength = <20>;
1969		};
1970
1971		pcfg_output_high: pcfg-output-high {
1972			output-high;
1973		};
1974
1975		pcfg_output_low: pcfg-output-low {
1976			output-low;
1977		};
1978
1979		clock {
1980			clk_32k: clk-32k {
1981				rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
1982			};
1983		};
1984
1985		edp {
1986			edp_hpd: edp-hpd {
1987				rockchip,pins =
1988					<4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1989			};
1990		};
1991
1992		gmac {
1993			rgmii_pins: rgmii-pins {
1994				rockchip,pins =
1995					/* mac_txclk */
1996					<3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1997					/* mac_rxclk */
1998					<3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
1999					/* mac_mdio */
2000					<3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
2001					/* mac_txen */
2002					<3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2003					/* mac_clk */
2004					<3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
2005					/* mac_rxdv */
2006					<3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
2007					/* mac_mdc */
2008					<3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
2009					/* mac_rxd1 */
2010					<3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
2011					/* mac_rxd0 */
2012					<3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2013					/* mac_txd1 */
2014					<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2015					/* mac_txd0 */
2016					<3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2017					/* mac_rxd3 */
2018					<3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
2019					/* mac_rxd2 */
2020					<3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
2021					/* mac_txd3 */
2022					<3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2023					/* mac_txd2 */
2024					<3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2025			};
2026
2027			rmii_pins: rmii-pins {
2028				rockchip,pins =
2029					/* mac_mdio */
2030					<3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
2031					/* mac_txen */
2032					<3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2033					/* mac_clk */
2034					<3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
2035					/* mac_rxer */
2036					<3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
2037					/* mac_rxdv */
2038					<3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
2039					/* mac_mdc */
2040					<3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
2041					/* mac_rxd1 */
2042					<3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
2043					/* mac_rxd0 */
2044					<3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2045					/* mac_txd1 */
2046					<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2047					/* mac_txd0 */
2048					<3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2049			};
2050		};
2051
2052		i2c0 {
2053			i2c0_xfer: i2c0-xfer {
2054				rockchip,pins =
2055					<1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
2056					<1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
2057			};
2058		};
2059
2060		i2c1 {
2061			i2c1_xfer: i2c1-xfer {
2062				rockchip,pins =
2063					<4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
2064					<4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
2065			};
2066		};
2067
2068		i2c2 {
2069			i2c2_xfer: i2c2-xfer {
2070				rockchip,pins =
2071					<2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2072					<2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2073			};
2074		};
2075
2076		i2c3 {
2077			i2c3_xfer: i2c3-xfer {
2078				rockchip,pins =
2079					<4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
2080					<4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
2081			};
2082		};
2083
2084		i2c4 {
2085			i2c4_xfer: i2c4-xfer {
2086				rockchip,pins =
2087					<1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
2088					<1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
2089			};
2090		};
2091
2092		i2c5 {
2093			i2c5_xfer: i2c5-xfer {
2094				rockchip,pins =
2095					<3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
2096					<3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
2097			};
2098		};
2099
2100		i2c6 {
2101			i2c6_xfer: i2c6-xfer {
2102				rockchip,pins =
2103					<2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
2104					<2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2105			};
2106		};
2107
2108		i2c7 {
2109			i2c7_xfer: i2c7-xfer {
2110				rockchip,pins =
2111					<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
2112					<2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
2113			};
2114		};
2115
2116		i2c8 {
2117			i2c8_xfer: i2c8-xfer {
2118				rockchip,pins =
2119					<1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
2120					<1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2121			};
2122		};
2123
2124		i2s0 {
2125			i2s0_8ch_bus: i2s0-8ch-bus {
2126				rockchip,pins =
2127					<3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
2128					<3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
2129					<3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
2130					<3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
2131					<3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
2132					<3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
2133					<3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
2134					<3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
2135					<4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
2136			};
2137		};
2138
2139		i2s1 {
2140			i2s1_2ch_bus: i2s1-2ch-bus {
2141				rockchip,pins =
2142					<4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
2143					<4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
2144					<4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
2145					<4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2146					<4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
2147			};
2148		};
2149
2150		sdio0 {
2151			sdio0_bus1: sdio0-bus1 {
2152				rockchip,pins =
2153					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2154			};
2155
2156			sdio0_bus4: sdio0-bus4 {
2157				rockchip,pins =
2158					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2159					<2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2160					<2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2161					<2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2162			};
2163
2164			sdio0_cmd: sdio0-cmd {
2165				rockchip,pins =
2166					<2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2167			};
2168
2169			sdio0_clk: sdio0-clk {
2170				rockchip,pins =
2171					<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2172			};
2173
2174			sdio0_cd: sdio0-cd {
2175				rockchip,pins =
2176					<2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2177			};
2178
2179			sdio0_pwr: sdio0-pwr {
2180				rockchip,pins =
2181					<2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2182			};
2183
2184			sdio0_bkpwr: sdio0-bkpwr {
2185				rockchip,pins =
2186					<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2187			};
2188
2189			sdio0_wp: sdio0-wp {
2190				rockchip,pins =
2191					<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2192			};
2193
2194			sdio0_int: sdio0-int {
2195				rockchip,pins =
2196					<0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2197			};
2198		};
2199
2200		sdmmc {
2201			sdmmc_bus1: sdmmc-bus1 {
2202				rockchip,pins =
2203					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2204			};
2205
2206			sdmmc_bus4: sdmmc-bus4 {
2207				rockchip,pins =
2208					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2209					<4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2210					<4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2211					<4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2212			};
2213
2214			sdmmc_clk: sdmmc-clk {
2215				rockchip,pins =
2216					<4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2217			};
2218
2219			sdmmc_cmd: sdmmc-cmd {
2220				rockchip,pins =
2221					<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2222			};
2223
2224			sdmmc_cd: sdmmc-cd {
2225				rockchip,pins =
2226					<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2227			};
2228
2229			sdmmc_wp: sdmmc-wp {
2230				rockchip,pins =
2231					<0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2232			};
2233		};
2234
2235		sleep {
2236			ap_pwroff: ap-pwroff {
2237				rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
2238			};
2239
2240			ddrio_pwroff: ddrio-pwroff {
2241				rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
2242			};
2243		};
2244
2245		spdif {
2246			spdif_bus: spdif-bus {
2247				rockchip,pins =
2248					<4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
2249			};
2250
2251			spdif_bus_1: spdif-bus-1 {
2252				rockchip,pins =
2253					<3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2254			};
2255		};
2256
2257		spi0 {
2258			spi0_clk: spi0-clk {
2259				rockchip,pins =
2260					<3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
2261			};
2262			spi0_cs0: spi0-cs0 {
2263				rockchip,pins =
2264					<3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
2265			};
2266			spi0_cs1: spi0-cs1 {
2267				rockchip,pins =
2268					<3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
2269			};
2270			spi0_tx: spi0-tx {
2271				rockchip,pins =
2272					<3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
2273			};
2274			spi0_rx: spi0-rx {
2275				rockchip,pins =
2276					<3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
2277			};
2278		};
2279
2280		spi1 {
2281			spi1_clk: spi1-clk {
2282				rockchip,pins =
2283					<1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
2284			};
2285			spi1_cs0: spi1-cs0 {
2286				rockchip,pins =
2287					<1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
2288			};
2289			spi1_rx: spi1-rx {
2290				rockchip,pins =
2291					<1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
2292			};
2293			spi1_tx: spi1-tx {
2294				rockchip,pins =
2295					<1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
2296			};
2297		};
2298
2299		spi2 {
2300			spi2_clk: spi2-clk {
2301				rockchip,pins =
2302					<2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2303			};
2304			spi2_cs0: spi2-cs0 {
2305				rockchip,pins =
2306					<2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
2307			};
2308			spi2_rx: spi2-rx {
2309				rockchip,pins =
2310					<2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
2311			};
2312			spi2_tx: spi2-tx {
2313				rockchip,pins =
2314					<2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
2315			};
2316		};
2317
2318		spi3 {
2319			spi3_clk: spi3-clk {
2320				rockchip,pins =
2321					<1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
2322			};
2323			spi3_cs0: spi3-cs0 {
2324				rockchip,pins =
2325					<1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
2326			};
2327			spi3_rx: spi3-rx {
2328				rockchip,pins =
2329					<1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
2330			};
2331			spi3_tx: spi3-tx {
2332				rockchip,pins =
2333					<1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
2334			};
2335		};
2336
2337		spi4 {
2338			spi4_clk: spi4-clk {
2339				rockchip,pins =
2340					<3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
2341			};
2342			spi4_cs0: spi4-cs0 {
2343				rockchip,pins =
2344					<3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
2345			};
2346			spi4_rx: spi4-rx {
2347				rockchip,pins =
2348					<3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
2349			};
2350			spi4_tx: spi4-tx {
2351				rockchip,pins =
2352					<3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
2353			};
2354		};
2355
2356		spi5 {
2357			spi5_clk: spi5-clk {
2358				rockchip,pins =
2359					<2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
2360			};
2361			spi5_cs0: spi5-cs0 {
2362				rockchip,pins =
2363					<2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
2364			};
2365			spi5_rx: spi5-rx {
2366				rockchip,pins =
2367					<2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
2368			};
2369			spi5_tx: spi5-tx {
2370				rockchip,pins =
2371					<2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
2372			};
2373		};
2374
2375		tsadc {
2376			otp_gpio: otp-gpio {
2377				rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2378			};
2379
2380			otp_out: otp-out {
2381				rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2382			};
2383		};
2384
2385		uart0 {
2386			uart0_xfer: uart0-xfer {
2387				rockchip,pins =
2388					<2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
2389					<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
2390			};
2391
2392			uart0_cts: uart0-cts {
2393				rockchip,pins =
2394					<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2395			};
2396
2397			uart0_rts: uart0-rts {
2398				rockchip,pins =
2399					<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2400			};
2401		};
2402
2403		uart1 {
2404			uart1_xfer: uart1-xfer {
2405				rockchip,pins =
2406					<3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
2407					<3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
2408			};
2409		};
2410
2411		uart2a {
2412			uart2a_xfer: uart2a-xfer {
2413				rockchip,pins =
2414					<4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
2415					<4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2416			};
2417		};
2418
2419		uart2b {
2420			uart2b_xfer: uart2b-xfer {
2421				rockchip,pins =
2422					<4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
2423					<4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
2424			};
2425		};
2426
2427		uart2c {
2428			uart2c_xfer: uart2c-xfer {
2429				rockchip,pins =
2430					<4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
2431					<4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2432			};
2433		};
2434
2435		uart3 {
2436			uart3_xfer: uart3-xfer {
2437				rockchip,pins =
2438					<3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
2439					<3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
2440			};
2441
2442			uart3_cts: uart3-cts {
2443				rockchip,pins =
2444					<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2445			};
2446
2447			uart3_rts: uart3-rts {
2448				rockchip,pins =
2449					<3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
2450			};
2451		};
2452
2453		uart4 {
2454			uart4_xfer: uart4-xfer {
2455				rockchip,pins =
2456					<1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
2457					<1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
2458			};
2459		};
2460
2461		uarthdcp {
2462			uarthdcp_xfer: uarthdcp-xfer {
2463				rockchip,pins =
2464					<4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
2465					<4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
2466			};
2467		};
2468
2469		pwm0 {
2470			pwm0_pin: pwm0-pin {
2471				rockchip,pins =
2472					<4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2473			};
2474
2475			vop0_pwm_pin: vop0-pwm-pin {
2476				rockchip,pins =
2477					<4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2478			};
2479		};
2480
2481		pwm1 {
2482			pwm1_pin: pwm1-pin {
2483				rockchip,pins =
2484					<4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2485			};
2486
2487			vop1_pwm_pin: vop1-pwm-pin {
2488				rockchip,pins =
2489					<4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2490			};
2491		};
2492
2493		pwm2 {
2494			pwm2_pin: pwm2-pin {
2495				rockchip,pins =
2496					<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2497			};
2498		};
2499
2500		pwm3a {
2501			pwm3a_pin: pwm3a-pin {
2502				rockchip,pins =
2503					<0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2504			};
2505		};
2506
2507		pwm3b {
2508			pwm3b_pin: pwm3b-pin {
2509				rockchip,pins =
2510					<1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2511			};
2512		};
2513
2514		hdmi {
2515			hdmi_i2c_xfer: hdmi-i2c-xfer {
2516				rockchip,pins =
2517					<4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2518					<4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2519			};
2520
2521			hdmi_cec: hdmi-cec {
2522				rockchip,pins =
2523					<4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2524			};
2525		};
2526
2527		pcie {
2528			pcie_clkreqn: pci-clkreqn {
2529				rockchip,pins =
2530					<2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
2531			};
2532
2533			pcie_clkreqnb: pci-clkreqnb {
2534				rockchip,pins =
2535					<4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
2536			};
2537
2538			pcie_clkreqn_cpm: pci-clkreqn-cpm {
2539				rockchip,pins =
2540					<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2541			};
2542
2543			pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2544				rockchip,pins =
2545					<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2546			};
2547		};
2548
2549	};
2550};
2551