1 #ifndef QEMU_PCI_DEVICE_H
2 #define QEMU_PCI_DEVICE_H
3
4 #include "hw/pci/pci.h"
5 #include "hw/pci/pcie.h"
6 #include "hw/pci/pcie_doe.h"
7
8 #define TYPE_PCI_DEVICE "pci-device"
9 typedef struct PCIDeviceClass PCIDeviceClass;
10 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
11 PCI_DEVICE, TYPE_PCI_DEVICE)
12
13 /*
14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
15 * actually a "CXL Component, but we name it device to match the PCI naming.
16 */
17 #define INTERFACE_CXL_DEVICE "cxl-device"
18
19 /* Implemented by devices that can be plugged on PCI Express buses */
20 #define INTERFACE_PCIE_DEVICE "pci-express-device"
21
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
23 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
24
25 struct PCIDeviceClass {
26 DeviceClass parent_class;
27
28 void (*realize)(PCIDevice *dev, Error **errp);
29 PCIUnregisterFunc *exit;
30 PCIConfigReadFunc *config_read;
31 PCIConfigWriteFunc *config_write;
32
33 uint16_t vendor_id;
34 uint16_t device_id;
35 uint8_t revision;
36 uint16_t class_id;
37 uint16_t subsystem_vendor_id; /* only for header type = 0 */
38 uint16_t subsystem_id; /* only for header type = 0 */
39
40 const char *romfile; /* rom bar */
41 };
42
43 enum PCIReqIDType {
44 PCI_REQ_ID_INVALID = 0,
45 PCI_REQ_ID_BDF,
46 PCI_REQ_ID_SECONDARY_BUS,
47 PCI_REQ_ID_MAX,
48 };
49 typedef enum PCIReqIDType PCIReqIDType;
50
51 struct PCIReqIDCache {
52 PCIDevice *dev;
53 PCIReqIDType type;
54 };
55 typedef struct PCIReqIDCache PCIReqIDCache;
56
57 struct PCIDevice {
58 DeviceState qdev;
59 bool partially_hotplugged;
60 bool has_power;
61
62 /* PCI config space */
63 uint8_t *config;
64
65 /*
66 * Used to enable config checks on load. Note that writable bits are
67 * never checked even if set in cmask.
68 */
69 uint8_t *cmask;
70
71 /* Used to implement R/W bytes */
72 uint8_t *wmask;
73
74 /* Used to implement RW1C(Write 1 to Clear) bytes */
75 uint8_t *w1cmask;
76
77 /* Used to allocate config space for capabilities. */
78 uint8_t *used;
79
80 /* the following fields are read only */
81 int32_t devfn;
82 /*
83 * Cached device to fetch requester ID from, to avoid the PCI tree
84 * walking every time we invoke PCI request (e.g., MSI). For
85 * conventional PCI root complex, this field is meaningless.
86 */
87 PCIReqIDCache requester_id_cache;
88 char name[64];
89 PCIIORegion io_regions[PCI_NUM_REGIONS];
90 AddressSpace bus_master_as;
91 MemoryRegion bus_master_container_region;
92 MemoryRegion bus_master_enable_region;
93
94 /* do not access the following fields */
95 PCIConfigReadFunc *config_read;
96 PCIConfigWriteFunc *config_write;
97
98 /* Legacy PCI VGA regions */
99 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
100 bool has_vga;
101
102 /* Current IRQ levels. Used internally by the generic PCI code. */
103 uint8_t irq_state;
104
105 /* Capability bits */
106 uint32_t cap_present;
107
108 /* Offset of MSI-X capability in config space */
109 uint8_t msix_cap;
110
111 /* MSI-X entries */
112 int msix_entries_nr;
113
114 /* Space to store MSIX table & pending bit array */
115 uint8_t *msix_table;
116 uint8_t *msix_pba;
117
118 /* May be used by INTx or MSI during interrupt notification */
119 void *irq_opaque;
120
121 MSITriggerFunc *msi_trigger;
122 MSIPrepareMessageFunc *msi_prepare_message;
123 MSIxPrepareMessageFunc *msix_prepare_message;
124
125 /* MemoryRegion container for msix exclusive BAR setup */
126 MemoryRegion msix_exclusive_bar;
127 /* Memory Regions for MSIX table and pending bit entries. */
128 MemoryRegion msix_table_mmio;
129 MemoryRegion msix_pba_mmio;
130 /* Reference-count for entries actually in use by driver. */
131 unsigned *msix_entry_used;
132 /* MSIX function mask set or MSIX disabled */
133 bool msix_function_masked;
134 /* Version id needed for VMState */
135 int32_t version_id;
136
137 /* Offset of MSI capability in config space */
138 uint8_t msi_cap;
139
140 /* PCI Express */
141 PCIExpressDevice exp;
142
143 /* SHPC */
144 SHPCDevice *shpc;
145
146 /* Location of option rom */
147 char *romfile;
148 uint32_t romsize;
149 bool has_rom;
150 MemoryRegion rom;
151 uint32_t rom_bar;
152
153 /* INTx routing notifier */
154 PCIINTxRoutingNotifier intx_routing_notifier;
155
156 /* MSI-X notifiers */
157 MSIVectorUseNotifier msix_vector_use_notifier;
158 MSIVectorReleaseNotifier msix_vector_release_notifier;
159 MSIVectorPollNotifier msix_vector_poll_notifier;
160
161 /* SPDM */
162 uint16_t spdm_port;
163
164 /* DOE */
165 DOECap doe_spdm;
166
167 /* ID of standby device in net_failover pair */
168 char *failover_pair_id;
169 uint32_t acpi_index;
170 };
171
pci_intx(PCIDevice * pci_dev)172 static inline int pci_intx(PCIDevice *pci_dev)
173 {
174 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
175 }
176
pci_is_cxl(const PCIDevice * d)177 static inline int pci_is_cxl(const PCIDevice *d)
178 {
179 return d->cap_present & QEMU_PCIE_CAP_CXL;
180 }
181
pci_is_express(const PCIDevice * d)182 static inline int pci_is_express(const PCIDevice *d)
183 {
184 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
185 }
186
pci_is_express_downstream_port(const PCIDevice * d)187 static inline int pci_is_express_downstream_port(const PCIDevice *d)
188 {
189 uint8_t type;
190
191 if (!pci_is_express(d) || !d->exp.exp_cap) {
192 return 0;
193 }
194
195 type = pcie_cap_get_type(d);
196
197 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
198 }
199
pci_is_vf(const PCIDevice * d)200 static inline int pci_is_vf(const PCIDevice *d)
201 {
202 return d->exp.sriov_vf.pf != NULL;
203 }
204
pci_config_size(const PCIDevice * d)205 static inline uint32_t pci_config_size(const PCIDevice *d)
206 {
207 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
208 }
209
pci_get_bdf(PCIDevice * dev)210 static inline uint16_t pci_get_bdf(PCIDevice *dev)
211 {
212 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
213 }
214
215 uint16_t pci_requester_id(PCIDevice *dev);
216
217 /* DMA access functions */
pci_get_address_space(PCIDevice * dev)218 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
219 {
220 return &dev->bus_master_as;
221 }
222
223 /**
224 * pci_dma_rw: Read from or write to an address space from PCI device.
225 *
226 * Return a MemTxResult indicating whether the operation succeeded
227 * or failed (eg unassigned memory, device rejected the transaction,
228 * IOMMU fault).
229 *
230 * @dev: #PCIDevice doing the memory access
231 * @addr: address within the #PCIDevice address space
232 * @buf: buffer with the data transferred
233 * @len: the number of bytes to read or write
234 * @dir: indicates the transfer direction
235 */
pci_dma_rw(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len,DMADirection dir,MemTxAttrs attrs)236 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
237 void *buf, dma_addr_t len,
238 DMADirection dir, MemTxAttrs attrs)
239 {
240 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
241 dir, attrs);
242 }
243
244 /**
245 * pci_dma_read: Read from an address space from PCI device.
246 *
247 * Return a MemTxResult indicating whether the operation succeeded
248 * or failed (eg unassigned memory, device rejected the transaction,
249 * IOMMU fault). Called within RCU critical section.
250 *
251 * @dev: #PCIDevice doing the memory access
252 * @addr: address within the #PCIDevice address space
253 * @buf: buffer with the data transferred
254 * @len: length of the data transferred
255 */
pci_dma_read(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len)256 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
257 void *buf, dma_addr_t len)
258 {
259 return pci_dma_rw(dev, addr, buf, len,
260 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
261 }
262
263 /**
264 * pci_dma_write: Write to address space from PCI device.
265 *
266 * Return a MemTxResult indicating whether the operation succeeded
267 * or failed (eg unassigned memory, device rejected the transaction,
268 * IOMMU fault).
269 *
270 * @dev: #PCIDevice doing the memory access
271 * @addr: address within the #PCIDevice address space
272 * @buf: buffer with the data transferred
273 * @len: the number of bytes to write
274 */
pci_dma_write(PCIDevice * dev,dma_addr_t addr,const void * buf,dma_addr_t len)275 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
276 const void *buf, dma_addr_t len)
277 {
278 return pci_dma_rw(dev, addr, (void *) buf, len,
279 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
280 }
281
282 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
283 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
284 dma_addr_t addr, \
285 uint##_bits##_t *val, \
286 MemTxAttrs attrs) \
287 { \
288 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
289 } \
290 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
291 dma_addr_t addr, \
292 uint##_bits##_t val, \
293 MemTxAttrs attrs) \
294 { \
295 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
296 }
297
298 PCI_DMA_DEFINE_LDST(ub, b, 8);
299 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
300 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
301 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
302 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
303 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
304 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
305
306 #undef PCI_DMA_DEFINE_LDST
307
308 /**
309 * pci_dma_map: Map device PCI address space range into host virtual address
310 * @dev: #PCIDevice to be accessed
311 * @addr: address within that device's address space
312 * @plen: pointer to length of buffer; updated on return to indicate
313 * if only a subset of the requested range has been mapped
314 * @dir: indicates the transfer direction
315 *
316 * Return: A host pointer, or %NULL if the resources needed to
317 * perform the mapping are exhausted (in that case *@plen
318 * is set to zero).
319 */
pci_dma_map(PCIDevice * dev,dma_addr_t addr,dma_addr_t * plen,DMADirection dir)320 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
321 dma_addr_t *plen, DMADirection dir)
322 {
323 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
324 MEMTXATTRS_UNSPECIFIED);
325 }
326
pci_dma_unmap(PCIDevice * dev,void * buffer,dma_addr_t len,DMADirection dir,dma_addr_t access_len)327 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
328 DMADirection dir, dma_addr_t access_len)
329 {
330 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
331 }
332
pci_dma_sglist_init(QEMUSGList * qsg,PCIDevice * dev,int alloc_hint)333 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
334 int alloc_hint)
335 {
336 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
337 }
338
339 extern const VMStateDescription vmstate_pci_device;
340
341 #define VMSTATE_PCI_DEVICE(_field, _state) { \
342 .name = (stringify(_field)), \
343 .size = sizeof(PCIDevice), \
344 .vmsd = &vmstate_pci_device, \
345 .flags = VMS_STRUCT, \
346 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
347 }
348
349 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
350 .name = (stringify(_field)), \
351 .size = sizeof(PCIDevice), \
352 .vmsd = &vmstate_pci_device, \
353 .flags = VMS_STRUCT | VMS_POINTER, \
354 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
355 }
356
357 #endif
358