1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "kvm/tdx.h" 48 #include "hw/xen/xen.h" 49 #include "qobject/qlist.h" 50 #include "qemu/error-report.h" 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "acpi-build.h" 53 #include "hw/mem/nvdimm.h" 54 #include "hw/cxl/cxl_host.h" 55 #include "hw/usb.h" 56 #include "hw/i386/intel_iommu.h" 57 #include "hw/net/ne2000-isa.h" 58 #include "hw/virtio/virtio-iommu.h" 59 #include "hw/virtio/virtio-md-pci.h" 60 #include "hw/i386/kvm/xen_overlay.h" 61 #include "hw/i386/kvm/xen_evtchn.h" 62 #include "hw/i386/kvm/xen_gnttab.h" 63 #include "hw/i386/kvm/xen_xenstore.h" 64 #include "hw/mem/memory-device.h" 65 #include "e820_memory_layout.h" 66 #include "trace.h" 67 #include "sev.h" 68 #include CONFIG_DEVICES 69 70 #ifdef CONFIG_XEN_EMU 71 #include "hw/xen/xen-legacy-backend.h" 72 #include "hw/xen/xen-bus.h" 73 #endif 74 75 /* 76 * Helper for setting model-id for CPU models that changed model-id 77 * depending on QEMU versions up to QEMU 2.4. 78 */ 79 #define PC_CPU_MODEL_IDS(v) \ 80 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 82 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 83 84 GlobalProperty pc_compat_10_1[] = { 85 { "mch", "extended-tseg-mbytes", "16" }, 86 }; 87 const size_t pc_compat_10_1_len = G_N_ELEMENTS(pc_compat_10_1); 88 89 GlobalProperty pc_compat_10_0[] = { 90 { TYPE_X86_CPU, "x-consistent-cache", "false" }, 91 { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, 92 { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, 93 { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" }, 94 }; 95 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 96 97 GlobalProperty pc_compat_9_2[] = {}; 98 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 99 100 GlobalProperty pc_compat_9_1[] = { 101 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 102 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 103 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 104 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 105 }; 106 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 107 108 GlobalProperty pc_compat_9_0[] = { 109 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 110 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 111 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 112 { "sev-guest", "legacy-vm-type", "on" }, 113 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 114 }; 115 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 116 117 GlobalProperty pc_compat_8_2[] = {}; 118 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 119 120 GlobalProperty pc_compat_8_1[] = {}; 121 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 122 123 GlobalProperty pc_compat_8_0[] = { 124 { "virtio-mem", "unplugged-inaccessible", "auto" }, 125 }; 126 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 127 128 GlobalProperty pc_compat_7_2[] = { 129 { "ICH9-LPC", "noreboot", "true" }, 130 }; 131 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 132 133 GlobalProperty pc_compat_7_1[] = {}; 134 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 135 136 GlobalProperty pc_compat_7_0[] = {}; 137 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 138 139 GlobalProperty pc_compat_6_2[] = { 140 { "virtio-mem", "unplugged-inaccessible", "off" }, 141 }; 142 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 143 144 GlobalProperty pc_compat_6_1[] = { 145 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 146 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 147 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 148 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 149 }; 150 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 151 152 GlobalProperty pc_compat_6_0[] = { 153 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 154 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 155 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 156 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 157 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 158 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 159 }; 160 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 161 162 GlobalProperty pc_compat_5_2[] = { 163 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 164 }; 165 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 166 167 GlobalProperty pc_compat_5_1[] = { 168 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 169 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 170 }; 171 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 172 173 GlobalProperty pc_compat_5_0[] = { 174 }; 175 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 176 177 GlobalProperty pc_compat_4_2[] = { 178 { "mch", "smbase-smram", "off" }, 179 }; 180 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 181 182 GlobalProperty pc_compat_4_1[] = {}; 183 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 184 185 GlobalProperty pc_compat_4_0[] = {}; 186 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 187 188 GlobalProperty pc_compat_3_1[] = { 189 { "intel-iommu", "dma-drain", "off" }, 190 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 191 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 192 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 193 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 194 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 195 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 196 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 197 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 198 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 199 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 200 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 201 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 202 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 203 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 204 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 205 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 206 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 207 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 208 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 209 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 210 }; 211 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 212 213 GlobalProperty pc_compat_3_0[] = { 214 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 215 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 216 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 217 }; 218 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 219 220 GlobalProperty pc_compat_2_12[] = { 221 { TYPE_X86_CPU, "legacy-cache", "on" }, 222 { TYPE_X86_CPU, "topoext", "off" }, 223 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 224 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 225 }; 226 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 227 228 GlobalProperty pc_compat_2_11[] = { 229 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 230 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 231 }; 232 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 233 234 GlobalProperty pc_compat_2_10[] = { 235 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 236 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 237 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 238 }; 239 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 240 241 GlobalProperty pc_compat_2_9[] = { 242 { "mch", "extended-tseg-mbytes", "0" }, 243 }; 244 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 245 246 GlobalProperty pc_compat_2_8[] = { 247 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 248 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 249 { "ICH9-LPC", "x-smi-broadcast", "off" }, 250 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 251 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 252 }; 253 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 254 255 GlobalProperty pc_compat_2_7[] = { 256 { TYPE_X86_CPU, "l3-cache", "off" }, 257 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 258 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 259 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 260 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 261 { "isa-pcspk", "migrate", "off" }, 262 }; 263 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 264 265 GlobalProperty pc_compat_2_6[] = { 266 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 267 { "vmxnet3", "romfile", "" }, 268 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 269 { "apic-common", "legacy-instance-id", "on", } 270 }; 271 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 272 273 /* 274 * @PC_FW_DATA: 275 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 276 * and other BIOS datastructures. 277 * 278 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 279 * reported to be used at the moment, 32K should be enough for a while. 280 */ 281 #define PC_FW_DATA (0x20000 + 0x8000) 282 283 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 284 { 285 GSIState *s; 286 287 s = g_new0(GSIState, 1); 288 if (kvm_ioapic_in_kernel()) { 289 kvm_pc_setup_irq_routing(pci_enabled); 290 } 291 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 292 293 return s; 294 } 295 296 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 297 unsigned size) 298 { 299 } 300 301 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 302 { 303 return 0xffffffffffffffffULL; 304 } 305 306 /* MS-DOS compatibility mode FPU exception support */ 307 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 308 unsigned size) 309 { 310 if (tcg_enabled()) { 311 cpu_set_ignne(); 312 } 313 } 314 315 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 316 { 317 return 0xffffffffffffffffULL; 318 } 319 320 /* PC cmos mappings */ 321 322 #define REG_EQUIPMENT_BYTE 0x14 323 324 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 325 int16_t cylinders, int8_t heads, int8_t sectors) 326 { 327 mc146818rtc_set_cmos_data(s, type_ofs, 47); 328 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 329 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 330 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 331 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 332 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 333 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 334 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 335 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 336 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 337 } 338 339 /* convert boot_device letter to something recognizable by the bios */ 340 static int boot_device2nibble(char boot_device) 341 { 342 switch(boot_device) { 343 case 'a': 344 case 'b': 345 return 0x01; /* floppy boot */ 346 case 'c': 347 return 0x02; /* hard drive boot */ 348 case 'd': 349 return 0x03; /* CD-ROM boot */ 350 case 'n': 351 return 0x04; /* Network boot */ 352 } 353 return 0; 354 } 355 356 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 357 const char *boot_device, Error **errp) 358 { 359 #define PC_MAX_BOOT_DEVICES 3 360 int nbds, bds[3] = { 0, }; 361 int i; 362 363 nbds = strlen(boot_device); 364 if (nbds > PC_MAX_BOOT_DEVICES) { 365 error_setg(errp, "Too many boot devices for PC"); 366 return; 367 } 368 for (i = 0; i < nbds; i++) { 369 bds[i] = boot_device2nibble(boot_device[i]); 370 if (bds[i] == 0) { 371 error_setg(errp, "Invalid boot device for PC: '%c'", 372 boot_device[i]); 373 return; 374 } 375 } 376 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 377 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 378 } 379 380 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 381 { 382 PCMachineState *pcms = opaque; 383 X86MachineState *x86ms = X86_MACHINE(pcms); 384 385 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 386 } 387 388 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 389 { 390 int val, nb; 391 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 392 FLOPPY_DRIVE_TYPE_NONE }; 393 394 #ifdef CONFIG_FDC_ISA 395 /* floppy type */ 396 if (floppy) { 397 for (int i = 0; i < 2; i++) { 398 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 399 } 400 } 401 #endif 402 403 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 404 cmos_get_fd_drive_type(fd_type[1]); 405 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 406 407 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 408 nb = 0; 409 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 410 nb++; 411 } 412 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 413 nb++; 414 } 415 switch (nb) { 416 case 0: 417 break; 418 case 1: 419 val |= 0x01; /* 1 drive, ready for boot */ 420 break; 421 case 2: 422 val |= 0x41; /* 2 drives, ready for boot */ 423 break; 424 } 425 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 426 } 427 428 typedef struct check_fdc_state { 429 ISADevice *floppy; 430 bool multiple; 431 } CheckFdcState; 432 433 static int check_fdc(Object *obj, void *opaque) 434 { 435 CheckFdcState *state = opaque; 436 Object *fdc; 437 uint32_t iobase; 438 Error *local_err = NULL; 439 440 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 441 if (!fdc) { 442 return 0; 443 } 444 445 iobase = object_property_get_uint(obj, "iobase", &local_err); 446 if (local_err || iobase != 0x3f0) { 447 error_free(local_err); 448 return 0; 449 } 450 451 if (state->floppy) { 452 state->multiple = true; 453 } else { 454 state->floppy = ISA_DEVICE(obj); 455 } 456 return 0; 457 } 458 459 static const char * const fdc_container_path[] = { 460 "unattached", "peripheral", "peripheral-anon" 461 }; 462 463 /* 464 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 465 * and ACPI objects. 466 */ 467 static ISADevice *pc_find_fdc0(void) 468 { 469 int i; 470 Object *container; 471 CheckFdcState state = { 0 }; 472 473 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 474 container = machine_get_container(fdc_container_path[i]); 475 object_child_foreach(container, check_fdc, &state); 476 } 477 478 if (state.multiple) { 479 warn_report("multiple floppy disk controllers with " 480 "iobase=0x3f0 have been found"); 481 error_printf("the one being picked for CMOS setup might not reflect " 482 "your intent"); 483 } 484 485 return state.floppy; 486 } 487 488 static void pc_cmos_init_late(PCMachineState *pcms) 489 { 490 X86MachineState *x86ms = X86_MACHINE(pcms); 491 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 492 int16_t cylinders; 493 int8_t heads, sectors; 494 int val; 495 int i, trans; 496 497 val = 0; 498 if (pcms->idebus[0] && 499 ide_get_geometry(pcms->idebus[0], 0, 500 &cylinders, &heads, §ors) >= 0) { 501 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 502 val |= 0xf0; 503 } 504 if (pcms->idebus[0] && 505 ide_get_geometry(pcms->idebus[0], 1, 506 &cylinders, &heads, §ors) >= 0) { 507 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 508 val |= 0x0f; 509 } 510 mc146818rtc_set_cmos_data(s, 0x12, val); 511 512 val = 0; 513 for (i = 0; i < 4; i++) { 514 /* NOTE: ide_get_geometry() returns the physical 515 geometry. It is always such that: 1 <= sects <= 63, 1 516 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 517 geometry can be different if a translation is done. */ 518 BusState *idebus = pcms->idebus[i / 2]; 519 if (idebus && 520 ide_get_geometry(idebus, i % 2, 521 &cylinders, &heads, §ors) >= 0) { 522 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 523 assert((trans & ~3) == 0); 524 val |= trans << (i * 2); 525 } 526 } 527 mc146818rtc_set_cmos_data(s, 0x39, val); 528 529 pc_cmos_init_floppy(s, pc_find_fdc0()); 530 531 /* various important CMOS locations needed by PC/Bochs bios */ 532 533 /* memory size */ 534 /* base memory (first MiB) */ 535 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 536 mc146818rtc_set_cmos_data(s, 0x15, val); 537 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 538 /* extended memory (next 64MiB) */ 539 if (x86ms->below_4g_mem_size > 1 * MiB) { 540 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 541 } else { 542 val = 0; 543 } 544 if (val > 65535) 545 val = 65535; 546 mc146818rtc_set_cmos_data(s, 0x17, val); 547 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 548 mc146818rtc_set_cmos_data(s, 0x30, val); 549 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 550 /* memory between 16MiB and 4GiB */ 551 if (x86ms->below_4g_mem_size > 16 * MiB) { 552 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 553 } else { 554 val = 0; 555 } 556 if (val > 65535) 557 val = 65535; 558 mc146818rtc_set_cmos_data(s, 0x34, val); 559 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 560 /* memory above 4GiB */ 561 val = x86ms->above_4g_mem_size / 65536; 562 mc146818rtc_set_cmos_data(s, 0x5b, val); 563 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 564 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 565 566 val = 0; 567 val |= 0x02; /* FPU is there */ 568 val |= 0x04; /* PS/2 mouse installed */ 569 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 570 } 571 572 static void handle_a20_line_change(void *opaque, int irq, int level) 573 { 574 X86CPU *cpu = opaque; 575 576 /* XXX: send to all CPUs ? */ 577 /* XXX: add logic to handle multiple A20 line sources */ 578 x86_cpu_set_a20(cpu, level); 579 } 580 581 #define NE2000_NB_MAX 6 582 583 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 584 0x280, 0x380 }; 585 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 586 587 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 588 { 589 static int nb_ne2k = 0; 590 591 if (nb_ne2k == NE2000_NB_MAX) { 592 error_setg(errp, 593 "maximum number of ISA NE2000 devices exceeded"); 594 return false; 595 } 596 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 597 ne2000_irq[nb_ne2k], nd); 598 nb_ne2k++; 599 return true; 600 } 601 602 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 603 { 604 X86CPU *cpu = opaque; 605 606 if (level) { 607 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 608 } 609 } 610 611 static 612 void pc_machine_done(Notifier *notifier, void *data) 613 { 614 PCMachineState *pcms = container_of(notifier, 615 PCMachineState, machine_done); 616 X86MachineState *x86ms = X86_MACHINE(pcms); 617 618 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 619 &error_fatal); 620 621 if (pcms->cxl_devices_state.is_enabled) { 622 cxl_fmws_link_targets(&error_fatal); 623 } 624 625 /* set the number of CPUs */ 626 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 627 628 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 629 &error_abort); 630 631 acpi_setup(); 632 if (x86ms->fw_cfg) { 633 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 634 fw_cfg_add_e820(x86ms->fw_cfg); 635 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 636 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 637 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 638 } 639 640 pc_cmos_init_late(pcms); 641 } 642 643 /* setup pci memory address space mapping into system address space */ 644 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 645 MemoryRegion *pci_address_space) 646 { 647 /* Set to lower priority than RAM */ 648 memory_region_add_subregion_overlap(system_memory, 0x0, 649 pci_address_space, -1); 650 } 651 652 void xen_load_linux(PCMachineState *pcms) 653 { 654 int i; 655 FWCfgState *fw_cfg; 656 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 657 X86MachineState *x86ms = X86_MACHINE(pcms); 658 659 assert(MACHINE(pcms)->kernel_filename != NULL); 660 661 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 662 &address_space_memory); 663 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 664 rom_set_fw(fw_cfg); 665 666 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 667 for (i = 0; i < nb_option_roms; i++) { 668 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 669 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 670 !strcmp(option_rom[i].name, "pvh.bin") || 671 !strcmp(option_rom[i].name, "multiboot.bin") || 672 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 673 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 674 } 675 x86ms->fw_cfg = fw_cfg; 676 } 677 678 #define PC_ROM_MIN_VGA 0xc0000 679 #define PC_ROM_MIN_OPTION 0xc8000 680 #define PC_ROM_MAX 0xe0000 681 #define PC_ROM_ALIGN 0x800 682 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 683 684 static hwaddr pc_above_4g_end(PCMachineState *pcms) 685 { 686 X86MachineState *x86ms = X86_MACHINE(pcms); 687 688 if (pcms->sgx_epc.size != 0) { 689 return sgx_epc_above_4g_end(&pcms->sgx_epc); 690 } 691 692 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 693 } 694 695 static void pc_get_device_memory_range(PCMachineState *pcms, 696 hwaddr *base, 697 ram_addr_t *device_mem_size) 698 { 699 MachineState *machine = MACHINE(pcms); 700 ram_addr_t size; 701 hwaddr addr; 702 703 size = machine->maxram_size - machine->ram_size; 704 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 705 706 /* size device region assuming 1G page max alignment per slot */ 707 size += (1 * GiB) * machine->ram_slots; 708 709 *base = addr; 710 *device_mem_size = size; 711 } 712 713 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 714 { 715 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 716 MachineState *ms = MACHINE(pcms); 717 hwaddr cxl_base; 718 ram_addr_t size; 719 720 if (pcmc->has_reserved_memory && 721 (ms->ram_size < ms->maxram_size)) { 722 pc_get_device_memory_range(pcms, &cxl_base, &size); 723 cxl_base += size; 724 } else { 725 cxl_base = pc_above_4g_end(pcms); 726 } 727 728 return cxl_base; 729 } 730 731 static int cxl_get_fmw_end(Object *obj, void *opaque) 732 { 733 struct CXLFixedWindow *fw; 734 uint64_t *start = opaque; 735 736 if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { 737 return 0; 738 } 739 fw = CXL_FMW(obj); 740 741 *start += fw->size; 742 743 return 0; 744 } 745 746 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 747 { 748 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 749 750 /* Ordering doesn't matter so no need to build a sorted list */ 751 object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end, 752 &start); 753 return start; 754 } 755 756 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 757 { 758 X86CPU *cpu = X86_CPU(first_cpu); 759 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 760 MachineState *ms = MACHINE(pcms); 761 762 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 763 /* 64-bit systems */ 764 return pc_pci_hole64_start() + pci_hole64_size - 1; 765 } 766 767 /* 32-bit systems */ 768 if (pcmc->broken_32bit_mem_addr_check) { 769 /* old value for compatibility reasons */ 770 return ((hwaddr)1 << cpu->phys_bits) - 1; 771 } 772 773 /* 774 * 32-bit systems don't have hole64 but they might have a region for 775 * memory devices. Even if additional hotplugged memory devices might 776 * not be usable by most guest OSes, we need to still consider them for 777 * calculating the highest possible GPA so that we can properly report 778 * if someone configures them on a CPU that cannot possibly address them. 779 */ 780 if (pcmc->has_reserved_memory && 781 (ms->ram_size < ms->maxram_size)) { 782 hwaddr devmem_start; 783 ram_addr_t devmem_size; 784 785 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 786 devmem_start += devmem_size; 787 return devmem_start - 1; 788 } 789 790 /* configuration without any memory hotplug */ 791 return pc_above_4g_end(pcms) - 1; 792 } 793 794 /* 795 * AMD systems with an IOMMU have an additional hole close to the 796 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 797 * on kernel version, VFIO may or may not let you DMA map those ranges. 798 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 799 * with certain memory sizes. It's also wrong to use those IOVA ranges 800 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 801 * The ranges reserved for Hyper-Transport are: 802 * 803 * FD_0000_0000h - FF_FFFF_FFFFh 804 * 805 * The ranges represent the following: 806 * 807 * Base Address Top Address Use 808 * 809 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 810 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 811 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 812 * FD_F910_0000h FD_F91F_FFFFh System Management 813 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 814 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 815 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 816 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 817 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 818 * FE_2000_0000h FF_FFFF_FFFFh Reserved 819 * 820 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 821 * Table 3: Special Address Controls (GPA) for more information. 822 */ 823 #define AMD_HT_START 0xfd00000000UL 824 #define AMD_HT_END 0xffffffffffUL 825 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 826 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 827 828 void pc_memory_init(PCMachineState *pcms, 829 MemoryRegion *system_memory, 830 MemoryRegion *rom_memory, 831 uint64_t pci_hole64_size) 832 { 833 int linux_boot, i; 834 MemoryRegion *option_rom_mr; 835 MemoryRegion *ram_below_4g, *ram_above_4g; 836 FWCfgState *fw_cfg; 837 MachineState *machine = MACHINE(pcms); 838 MachineClass *mc = MACHINE_GET_CLASS(machine); 839 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 840 X86MachineState *x86ms = X86_MACHINE(pcms); 841 hwaddr maxphysaddr, maxusedaddr; 842 hwaddr cxl_base, cxl_resv_end = 0; 843 X86CPU *cpu = X86_CPU(first_cpu); 844 uint64_t res_mem_end; 845 846 assert(machine->ram_size == x86ms->below_4g_mem_size + 847 x86ms->above_4g_mem_size); 848 849 linux_boot = (machine->kernel_filename != NULL); 850 851 /* 852 * The HyperTransport range close to the 1T boundary is unique to AMD 853 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 854 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 855 * older machine types (<= 7.0) for compatibility purposes. 856 */ 857 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 858 /* Bail out if max possible address does not cross HT range */ 859 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 860 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 861 } 862 863 /* 864 * Advertise the HT region if address space covers the reserved 865 * region or if we relocate. 866 */ 867 if (cpu->phys_bits >= 40) { 868 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 869 } 870 } 871 872 /* 873 * phys-bits is required to be appropriately configured 874 * to make sure max used GPA is reachable. 875 */ 876 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 877 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 878 if (maxphysaddr < maxusedaddr) { 879 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 880 " phys-bits too low (%u)", 881 maxphysaddr, maxusedaddr, cpu->phys_bits); 882 exit(EXIT_FAILURE); 883 } 884 885 /* 886 * Split single memory region and use aliases to address portions of it, 887 * done for backwards compatibility with older qemus. 888 */ 889 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 890 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 891 0, x86ms->below_4g_mem_size); 892 memory_region_add_subregion(system_memory, 0, ram_below_4g); 893 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 894 if (x86ms->above_4g_mem_size > 0) { 895 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 896 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 897 machine->ram, 898 x86ms->below_4g_mem_size, 899 x86ms->above_4g_mem_size); 900 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 901 ram_above_4g); 902 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 903 E820_RAM); 904 } 905 906 if (pcms->sgx_epc.size != 0) { 907 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 908 } 909 910 if (!pcmc->has_reserved_memory && 911 (machine->ram_slots || 912 (machine->maxram_size > machine->ram_size))) { 913 914 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 915 mc->name); 916 exit(EXIT_FAILURE); 917 } 918 919 /* initialize device memory address space */ 920 if (pcmc->has_reserved_memory && 921 (machine->ram_size < machine->maxram_size)) { 922 ram_addr_t device_mem_size; 923 hwaddr device_mem_base; 924 925 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 926 error_report("unsupported amount of memory slots: %"PRIu64, 927 machine->ram_slots); 928 exit(EXIT_FAILURE); 929 } 930 931 if (QEMU_ALIGN_UP(machine->maxram_size, 932 TARGET_PAGE_SIZE) != machine->maxram_size) { 933 error_report("maximum memory size must by aligned to multiple of " 934 "%d bytes", TARGET_PAGE_SIZE); 935 exit(EXIT_FAILURE); 936 } 937 938 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 939 940 if (device_mem_base + device_mem_size < device_mem_size) { 941 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 942 machine->maxram_size); 943 exit(EXIT_FAILURE); 944 } 945 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 946 } 947 948 if (pcms->cxl_devices_state.is_enabled) { 949 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 950 hwaddr cxl_size = MiB; 951 952 cxl_base = pc_get_cxl_range_start(pcms); 953 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 954 memory_region_add_subregion(system_memory, cxl_base, mr); 955 cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 956 cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr); 957 cxl_fmws_update_mmio(); 958 } 959 960 /* Initialize PC system firmware */ 961 pc_system_firmware_init(pcms, rom_memory); 962 963 if (!is_tdx_vm()) { 964 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 965 if (machine_require_guest_memfd(machine)) { 966 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 967 PC_ROM_SIZE, &error_fatal); 968 } else { 969 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 970 &error_fatal); 971 if (pcmc->pci_enabled) { 972 memory_region_set_readonly(option_rom_mr, true); 973 } 974 } 975 memory_region_add_subregion_overlap(rom_memory, 976 PC_ROM_MIN_VGA, 977 option_rom_mr, 978 1); 979 } 980 981 fw_cfg = fw_cfg_arch_create(machine, 982 x86ms->boot_cpus, x86ms->apic_id_limit); 983 984 rom_set_fw(fw_cfg); 985 986 if (pcms->cxl_devices_state.is_enabled) { 987 res_mem_end = cxl_resv_end; 988 } else if (machine->device_memory) { 989 res_mem_end = machine->device_memory->base 990 + memory_region_size(&machine->device_memory->mr); 991 } else { 992 res_mem_end = 0; 993 } 994 995 if (res_mem_end) { 996 uint64_t *val = g_malloc(sizeof(*val)); 997 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 998 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 999 } 1000 1001 if (linux_boot) { 1002 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1003 } 1004 1005 for (i = 0; i < nb_option_roms; i++) { 1006 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1007 } 1008 x86ms->fw_cfg = fw_cfg; 1009 1010 /* Init default IOAPIC address space */ 1011 x86ms->ioapic_as = &address_space_memory; 1012 1013 /* Init ACPI memory hotplug IO base address */ 1014 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1015 } 1016 1017 /* 1018 * The 64bit pci hole starts after "above 4G RAM" and 1019 * potentially the space reserved for memory hotplug. 1020 */ 1021 uint64_t pc_pci_hole64_start(void) 1022 { 1023 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1024 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1025 MachineState *ms = MACHINE(pcms); 1026 uint64_t hole64_start = 0; 1027 ram_addr_t size = 0; 1028 1029 if (pcms->cxl_devices_state.is_enabled) { 1030 hole64_start = pc_get_cxl_range_end(pcms); 1031 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1032 pc_get_device_memory_range(pcms, &hole64_start, &size); 1033 hole64_start += size; 1034 } else { 1035 hole64_start = pc_above_4g_end(pcms); 1036 } 1037 1038 return ROUND_UP(hole64_start, 1 * GiB); 1039 } 1040 1041 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1042 { 1043 DeviceState *dev = NULL; 1044 1045 if (pci_bus) { 1046 PCIDevice *pcidev = pci_vga_init(pci_bus); 1047 dev = pcidev ? &pcidev->qdev : NULL; 1048 } else if (isa_bus) { 1049 ISADevice *isadev = isa_vga_init(isa_bus); 1050 dev = isadev ? DEVICE(isadev) : NULL; 1051 } 1052 1053 return dev; 1054 } 1055 1056 static const MemoryRegionOps ioport80_io_ops = { 1057 .write = ioport80_write, 1058 .read = ioport80_read, 1059 .endianness = DEVICE_LITTLE_ENDIAN, 1060 .impl = { 1061 .min_access_size = 1, 1062 .max_access_size = 1, 1063 }, 1064 }; 1065 1066 static const MemoryRegionOps ioportF0_io_ops = { 1067 .write = ioportF0_write, 1068 .read = ioportF0_read, 1069 .endianness = DEVICE_LITTLE_ENDIAN, 1070 .impl = { 1071 .min_access_size = 1, 1072 .max_access_size = 1, 1073 }, 1074 }; 1075 1076 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1077 bool create_i8042, bool no_vmport, Error **errp) 1078 { 1079 int i; 1080 DriveInfo *fd[MAX_FD]; 1081 qemu_irq *a20_line; 1082 ISADevice *i8042, *port92, *vmmouse; 1083 1084 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1085 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1086 1087 for (i = 0; i < MAX_FD; i++) { 1088 fd[i] = drive_get(IF_FLOPPY, 0, i); 1089 create_fdctrl |= !!fd[i]; 1090 } 1091 if (create_fdctrl) { 1092 #ifdef CONFIG_FDC_ISA 1093 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1094 if (fdc) { 1095 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1096 isa_fdc_init_drives(fdc, fd); 1097 } 1098 #endif 1099 } 1100 1101 if (!create_i8042) { 1102 if (!no_vmport) { 1103 error_setg(errp, 1104 "vmport requires the i8042 controller to be enabled"); 1105 } 1106 return; 1107 } 1108 1109 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1110 if (!no_vmport) { 1111 isa_create_simple(isa_bus, TYPE_VMPORT); 1112 vmmouse = isa_try_new("vmmouse"); 1113 } else { 1114 vmmouse = NULL; 1115 } 1116 if (vmmouse) { 1117 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1118 &error_abort); 1119 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1120 } 1121 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1122 1123 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1124 qdev_connect_gpio_out_named(DEVICE(i8042), 1125 I8042_A20_LINE, 0, a20_line[0]); 1126 qdev_connect_gpio_out_named(DEVICE(port92), 1127 PORT92_A20_LINE, 0, a20_line[1]); 1128 g_free(a20_line); 1129 } 1130 1131 void pc_basic_device_init(struct PCMachineState *pcms, 1132 ISABus *isa_bus, qemu_irq *gsi, 1133 ISADevice *rtc_state, 1134 bool create_fdctrl, 1135 uint32_t hpet_irqs) 1136 { 1137 int i; 1138 DeviceState *hpet = NULL; 1139 int pit_isa_irq = 0; 1140 qemu_irq pit_alt_irq = NULL; 1141 ISADevice *pit = NULL; 1142 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1143 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1144 X86MachineState *x86ms = X86_MACHINE(pcms); 1145 1146 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1147 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1148 1149 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1150 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1151 1152 /* 1153 * Check if an HPET shall be created. 1154 */ 1155 if (pcms->hpet_enabled) { 1156 qemu_irq rtc_irq; 1157 1158 hpet = qdev_try_new(TYPE_HPET); 1159 if (!hpet) { 1160 error_report("couldn't create HPET device"); 1161 exit(1); 1162 } 1163 /* 1164 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1165 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1166 * the property, use whatever mask they specified. 1167 */ 1168 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1169 HPET_INTCAP, NULL); 1170 if (!compat) { 1171 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1172 } 1173 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1174 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1175 1176 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1177 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1178 } 1179 pit_isa_irq = -1; 1180 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1181 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1182 1183 /* overwrite connection created by south bridge */ 1184 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1185 } 1186 1187 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1188 "date"); 1189 1190 #ifdef CONFIG_XEN_EMU 1191 if (xen_mode == XEN_EMULATE) { 1192 xen_overlay_create(); 1193 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1194 xen_gnttab_create(); 1195 xen_xenstore_create(); 1196 if (pcms->pcibus) { 1197 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1198 } 1199 xen_bus_init(); 1200 } 1201 #endif 1202 1203 qemu_register_boot_set(pc_boot_set, pcms); 1204 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1205 MACHINE(pcms)->boot_config.order, &error_fatal); 1206 1207 if (!xen_enabled() && 1208 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1209 if (kvm_pit_in_kernel()) { 1210 pit = kvm_pit_init(isa_bus, 0x40); 1211 } else { 1212 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1213 } 1214 if (hpet) { 1215 /* connect PIT to output control line of the HPET */ 1216 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1217 } 1218 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1219 OBJECT(pit), &error_fatal); 1220 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1221 } 1222 1223 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1224 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1225 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1226 } 1227 1228 /* Super I/O */ 1229 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1230 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1231 1232 pcms->machine_done.notify = pc_machine_done; 1233 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1234 } 1235 1236 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1237 { 1238 MachineClass *mc = MACHINE_CLASS(pcmc); 1239 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1240 NICInfo *nd; 1241 1242 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1243 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1244 } 1245 1246 /* Anything remaining should be a PCI NIC */ 1247 if (pci_bus) { 1248 pci_init_nic_devices(pci_bus, mc->default_nic); 1249 } 1250 } 1251 1252 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1253 { 1254 qemu_irq *i8259; 1255 1256 if (kvm_pic_in_kernel()) { 1257 i8259 = kvm_i8259_init(isa_bus); 1258 } else if (xen_enabled()) { 1259 i8259 = xen_interrupt_controller_init(); 1260 } else { 1261 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1262 } 1263 1264 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1265 i8259_irqs[i] = i8259[i]; 1266 } 1267 1268 g_free(i8259); 1269 } 1270 1271 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1272 Error **errp) 1273 { 1274 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1275 const MachineState *ms = MACHINE(hotplug_dev); 1276 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1277 Error *local_err = NULL; 1278 1279 /* 1280 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1281 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1282 * addition to cover this case. 1283 */ 1284 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1285 error_setg(errp, 1286 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1287 return; 1288 } 1289 1290 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1291 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1292 return; 1293 } 1294 1295 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1296 if (local_err) { 1297 error_propagate(errp, local_err); 1298 return; 1299 } 1300 1301 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1302 } 1303 1304 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1305 DeviceState *dev, Error **errp) 1306 { 1307 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1308 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1309 MachineState *ms = MACHINE(hotplug_dev); 1310 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1311 1312 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1313 1314 if (is_nvdimm) { 1315 nvdimm_plug(ms->nvdimms_state); 1316 } 1317 1318 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1319 } 1320 1321 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1322 DeviceState *dev, Error **errp) 1323 { 1324 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1325 1326 /* 1327 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1328 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1329 * addition to cover this case. 1330 */ 1331 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1332 error_setg(errp, 1333 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1334 return; 1335 } 1336 1337 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1338 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1339 return; 1340 } 1341 1342 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1343 errp); 1344 } 1345 1346 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1347 DeviceState *dev, Error **errp) 1348 { 1349 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1350 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1351 Error *local_err = NULL; 1352 1353 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1354 if (local_err) { 1355 goto out; 1356 } 1357 1358 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1359 qdev_unrealize(dev); 1360 out: 1361 error_propagate(errp, local_err); 1362 } 1363 1364 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1365 DeviceState *dev, Error **errp) 1366 { 1367 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1368 g_assert(!dev->hotplugged); 1369 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1370 } 1371 1372 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1373 DeviceState *dev, Error **errp) 1374 { 1375 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1376 } 1377 1378 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1379 DeviceState *dev, Error **errp) 1380 { 1381 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1382 pc_memory_pre_plug(hotplug_dev, dev, errp); 1383 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1384 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1386 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1388 /* Declare the APIC range as the reserved MSI region */ 1389 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1390 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1391 QList *reserved_regions = qlist_new(); 1392 1393 qlist_append_str(reserved_regions, resv_prop_str); 1394 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1395 1396 g_free(resv_prop_str); 1397 } 1398 1399 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1400 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1401 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1402 1403 if (pcms->iommu) { 1404 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1405 "for x86 yet."); 1406 return; 1407 } 1408 pcms->iommu = dev; 1409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1410 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1411 } 1412 } 1413 1414 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1415 DeviceState *dev, Error **errp) 1416 { 1417 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1418 pc_memory_plug(hotplug_dev, dev, errp); 1419 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1420 x86_cpu_plug(hotplug_dev, dev, errp); 1421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1422 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1424 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1425 } 1426 } 1427 1428 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1429 DeviceState *dev, Error **errp) 1430 { 1431 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1432 pc_memory_unplug_request(hotplug_dev, dev, errp); 1433 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1434 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1435 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1436 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1437 errp); 1438 } else { 1439 error_setg(errp, "acpi: device unplug request for not supported device" 1440 " type: %s", object_get_typename(OBJECT(dev))); 1441 } 1442 } 1443 1444 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1445 DeviceState *dev, Error **errp) 1446 { 1447 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1448 pc_memory_unplug(hotplug_dev, dev, errp); 1449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1450 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1452 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1453 } else { 1454 error_setg(errp, "acpi: device unplug for not supported device" 1455 " type: %s", object_get_typename(OBJECT(dev))); 1456 } 1457 } 1458 1459 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1460 DeviceState *dev) 1461 { 1462 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1463 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1464 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1465 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1466 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1467 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1468 return HOTPLUG_HANDLER(machine); 1469 } 1470 1471 return NULL; 1472 } 1473 1474 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1475 void *opaque, Error **errp) 1476 { 1477 PCMachineState *pcms = PC_MACHINE(obj); 1478 OnOffAuto vmport = pcms->vmport; 1479 1480 visit_type_OnOffAuto(v, name, &vmport, errp); 1481 } 1482 1483 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1484 void *opaque, Error **errp) 1485 { 1486 PCMachineState *pcms = PC_MACHINE(obj); 1487 1488 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1489 } 1490 1491 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1492 { 1493 PCMachineState *pcms = PC_MACHINE(obj); 1494 1495 return pcms->fd_bootchk; 1496 } 1497 1498 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1499 { 1500 PCMachineState *pcms = PC_MACHINE(obj); 1501 1502 pcms->fd_bootchk = value; 1503 } 1504 1505 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 return pcms->smbus_enabled; 1510 } 1511 1512 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 pcms->smbus_enabled = value; 1517 } 1518 1519 static bool pc_machine_get_sata(Object *obj, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 return pcms->sata_enabled; 1524 } 1525 1526 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 pcms->sata_enabled = value; 1531 } 1532 1533 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1534 { 1535 PCMachineState *pcms = PC_MACHINE(obj); 1536 1537 return pcms->hpet_enabled; 1538 } 1539 1540 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 pcms->hpet_enabled = value; 1545 } 1546 1547 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 1551 return pcms->i8042_enabled; 1552 } 1553 1554 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 1558 pcms->i8042_enabled = value; 1559 } 1560 1561 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 1565 return pcms->default_bus_bypass_iommu; 1566 } 1567 1568 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1569 Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 1573 pcms->default_bus_bypass_iommu = value; 1574 } 1575 1576 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1577 void *opaque, Error **errp) 1578 { 1579 PCMachineState *pcms = PC_MACHINE(obj); 1580 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1581 1582 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1583 } 1584 1585 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1586 void *opaque, Error **errp) 1587 { 1588 PCMachineState *pcms = PC_MACHINE(obj); 1589 1590 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1591 } 1592 1593 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1594 const char *name, void *opaque, 1595 Error **errp) 1596 { 1597 PCMachineState *pcms = PC_MACHINE(obj); 1598 uint64_t value = pcms->max_ram_below_4g; 1599 1600 visit_type_size(v, name, &value, errp); 1601 } 1602 1603 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1604 const char *name, void *opaque, 1605 Error **errp) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 uint64_t value; 1609 1610 if (!visit_type_size(v, name, &value, errp)) { 1611 return; 1612 } 1613 if (value > 4 * GiB) { 1614 error_setg(errp, 1615 "Machine option 'max-ram-below-4g=%"PRIu64 1616 "' expects size less than or equal to 4G", value); 1617 return; 1618 } 1619 1620 if (value < 1 * MiB) { 1621 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1622 "BIOS may not work with less than 1MiB", value); 1623 } 1624 1625 pcms->max_ram_below_4g = value; 1626 } 1627 1628 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1629 const char *name, void *opaque, 1630 Error **errp) 1631 { 1632 PCMachineState *pcms = PC_MACHINE(obj); 1633 uint64_t value = pcms->max_fw_size; 1634 1635 visit_type_size(v, name, &value, errp); 1636 } 1637 1638 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1639 const char *name, void *opaque, 1640 Error **errp) 1641 { 1642 PCMachineState *pcms = PC_MACHINE(obj); 1643 uint64_t value; 1644 1645 if (!visit_type_size(v, name, &value, errp)) { 1646 return; 1647 } 1648 1649 /* 1650 * We don't have a theoretically justifiable exact lower bound on the base 1651 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1652 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1653 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1654 * 16MiB in size. 1655 */ 1656 if (value > 16 * MiB) { 1657 error_setg(errp, 1658 "User specified max allowed firmware size %" PRIu64 " is " 1659 "greater than 16MiB. If combined firmware size exceeds " 1660 "16MiB the system may not boot, or experience intermittent" 1661 "stability issues.", 1662 value); 1663 return; 1664 } 1665 1666 pcms->max_fw_size = value; 1667 } 1668 1669 1670 static void pc_machine_initfn(Object *obj) 1671 { 1672 PCMachineState *pcms = PC_MACHINE(obj); 1673 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1674 1675 #ifdef CONFIG_VMPORT 1676 pcms->vmport = ON_OFF_AUTO_AUTO; 1677 #else 1678 pcms->vmport = ON_OFF_AUTO_OFF; 1679 #endif /* CONFIG_VMPORT */ 1680 pcms->max_ram_below_4g = 0; /* use default */ 1681 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1682 pcms->south_bridge = pcmc->default_south_bridge; 1683 1684 /* acpi build is enabled by default if machine supports it */ 1685 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1686 pcms->smbus_enabled = true; 1687 pcms->sata_enabled = true; 1688 pcms->i8042_enabled = true; 1689 pcms->max_fw_size = 8 * MiB; 1690 #if defined(CONFIG_HPET) 1691 pcms->hpet_enabled = true; 1692 #endif 1693 pcms->fd_bootchk = true; 1694 pcms->default_bus_bypass_iommu = false; 1695 1696 pc_system_flash_create(pcms); 1697 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1698 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1699 OBJECT(pcms->pcspk), "audiodev"); 1700 if (pcmc->pci_enabled) { 1701 cxl_machine_init(obj, &pcms->cxl_devices_state); 1702 } 1703 } 1704 1705 static void pc_machine_reset(MachineState *machine, ResetType type) 1706 { 1707 CPUState *cs; 1708 X86CPU *cpu; 1709 1710 qemu_devices_reset(type); 1711 1712 /* Reset APIC after devices have been reset to cancel 1713 * any changes that qemu_devices_reset() might have done. 1714 */ 1715 CPU_FOREACH(cs) { 1716 cpu = X86_CPU(cs); 1717 1718 x86_cpu_after_reset(cpu); 1719 } 1720 } 1721 1722 static void pc_machine_wakeup(MachineState *machine) 1723 { 1724 cpu_synchronize_all_states(); 1725 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1726 cpu_synchronize_all_post_reset(); 1727 } 1728 1729 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1730 { 1731 MachineClass *mc = MACHINE_CLASS(oc); 1732 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1733 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1734 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1735 1736 pcmc->pci_enabled = true; 1737 pcmc->has_acpi_build = true; 1738 pcmc->smbios_defaults = true; 1739 pcmc->gigabyte_align = true; 1740 pcmc->has_reserved_memory = true; 1741 pcmc->enforce_amd_1tb_hole = true; 1742 pcmc->isa_bios_alias = true; 1743 pcmc->pvh_enabled = true; 1744 pcmc->kvmclock_create_always = true; 1745 x86mc->apic_xrupt_override = true; 1746 assert(!mc->get_hotplug_handler); 1747 mc->get_hotplug_handler = pc_get_hotplug_handler; 1748 mc->auto_enable_numa_with_memhp = true; 1749 mc->auto_enable_numa_with_memdev = true; 1750 mc->has_hotpluggable_cpus = true; 1751 mc->default_boot_order = "cad"; 1752 mc->block_default_type = IF_IDE; 1753 mc->max_cpus = 255; 1754 mc->reset = pc_machine_reset; 1755 mc->wakeup = pc_machine_wakeup; 1756 hc->pre_plug = pc_machine_device_pre_plug_cb; 1757 hc->plug = pc_machine_device_plug_cb; 1758 hc->unplug_request = pc_machine_device_unplug_request_cb; 1759 hc->unplug = pc_machine_device_unplug_cb; 1760 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1761 mc->nvdimm_supported = true; 1762 mc->smp_props.dies_supported = true; 1763 mc->smp_props.modules_supported = true; 1764 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1765 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1766 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1767 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1768 mc->default_ram_id = "pc.ram"; 1769 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1770 1771 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1772 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1773 NULL, NULL); 1774 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1775 "Maximum ram below the 4G boundary (32bit boundary)"); 1776 1777 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1778 pc_machine_get_vmport, pc_machine_set_vmport, 1779 NULL, NULL); 1780 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1781 "Enable vmport (pc & q35)"); 1782 1783 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1784 pc_machine_get_smbus, pc_machine_set_smbus); 1785 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1786 "Enable/disable system management bus"); 1787 1788 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1789 pc_machine_get_sata, pc_machine_set_sata); 1790 object_class_property_set_description(oc, PC_MACHINE_SATA, 1791 "Enable/disable Serial ATA bus"); 1792 1793 object_class_property_add_bool(oc, "hpet", 1794 pc_machine_get_hpet, pc_machine_set_hpet); 1795 object_class_property_set_description(oc, "hpet", 1796 "Enable/disable high precision event timer emulation"); 1797 1798 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1799 pc_machine_get_i8042, pc_machine_set_i8042); 1800 object_class_property_set_description(oc, PC_MACHINE_I8042, 1801 "Enable/disable Intel 8042 PS/2 controller emulation"); 1802 1803 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1804 pc_machine_get_default_bus_bypass_iommu, 1805 pc_machine_set_default_bus_bypass_iommu); 1806 1807 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1808 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1809 NULL, NULL); 1810 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1811 "Maximum combined firmware size"); 1812 1813 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1814 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1815 NULL, NULL); 1816 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1817 "SMBIOS Entry Point type [32, 64]"); 1818 1819 object_class_property_add_bool(oc, "fd-bootchk", 1820 pc_machine_get_fd_bootchk, 1821 pc_machine_set_fd_bootchk); 1822 1823 #if defined(CONFIG_IGVM) 1824 object_class_property_add_link(oc, "igvm-cfg", 1825 TYPE_IGVM_CFG, 1826 offsetof(X86MachineState, igvm), 1827 object_property_allow_set_link, 1828 OBJ_PROP_LINK_STRONG); 1829 object_class_property_set_description(oc, "igvm-cfg", 1830 "Set IGVM configuration"); 1831 #endif 1832 1833 1834 } 1835 1836 static const TypeInfo pc_machine_info = { 1837 .name = TYPE_PC_MACHINE, 1838 .parent = TYPE_X86_MACHINE, 1839 .abstract = true, 1840 .instance_size = sizeof(PCMachineState), 1841 .instance_init = pc_machine_initfn, 1842 .class_size = sizeof(PCMachineClass), 1843 .class_init = pc_machine_class_init, 1844 .interfaces = (const InterfaceInfo[]) { 1845 { TYPE_HOTPLUG_HANDLER }, 1846 { } 1847 }, 1848 }; 1849 1850 static void pc_machine_register_types(void) 1851 { 1852 type_register_static(&pc_machine_info); 1853 } 1854 1855 type_init(pc_machine_register_types) 1856