1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/power/rk3588-power.h> 10 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/ata/ahci.h> 13 14 / { 15 compatible = "rockchip,rk3588"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu_l0>; 29 }; 30 core1 { 31 cpu = <&cpu_l1>; 32 }; 33 core2 { 34 cpu = <&cpu_l2>; 35 }; 36 core3 { 37 cpu = <&cpu_l3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu_b0>; 43 }; 44 core1 { 45 cpu = <&cpu_b1>; 46 }; 47 }; 48 cluster2 { 49 core0 { 50 cpu = <&cpu_b2>; 51 }; 52 core1 { 53 cpu = <&cpu_b3>; 54 }; 55 }; 56 }; 57 58 cpu_l0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x0>; 62 enable-method = "psci"; 63 capacity-dmips-mhz = <530>; 64 clocks = <&scmi_clk SCMI_CLK_CPUL>; 65 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 66 assigned-clock-rates = <816000000>; 67 cpu-idle-states = <&CPU_SLEEP>; 68 i-cache-size = <32768>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <128>; 71 d-cache-size = <32768>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&l2_cache_l0>; 75 dynamic-power-coefficient = <228>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu_l1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a55"; 82 reg = <0x100>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <530>; 85 clocks = <&scmi_clk SCMI_CLK_CPUL>; 86 cpu-idle-states = <&CPU_SLEEP>; 87 i-cache-size = <32768>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <128>; 90 d-cache-size = <32768>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&l2_cache_l1>; 94 dynamic-power-coefficient = <228>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu_l2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x200>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <530>; 104 clocks = <&scmi_clk SCMI_CLK_CPUL>; 105 cpu-idle-states = <&CPU_SLEEP>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <128>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_cache_l2>; 113 dynamic-power-coefficient = <228>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu_l3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 reg = <0x300>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <530>; 123 clocks = <&scmi_clk SCMI_CLK_CPUL>; 124 cpu-idle-states = <&CPU_SLEEP>; 125 i-cache-size = <32768>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <128>; 128 d-cache-size = <32768>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&l2_cache_l3>; 132 dynamic-power-coefficient = <228>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu_b0: cpu@400 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a76"; 139 reg = <0x400>; 140 enable-method = "psci"; 141 capacity-dmips-mhz = <1024>; 142 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 143 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 144 assigned-clock-rates = <816000000>; 145 cpu-idle-states = <&CPU_SLEEP>; 146 i-cache-size = <65536>; 147 i-cache-line-size = <64>; 148 i-cache-sets = <256>; 149 d-cache-size = <65536>; 150 d-cache-line-size = <64>; 151 d-cache-sets = <256>; 152 next-level-cache = <&l2_cache_b0>; 153 dynamic-power-coefficient = <416>; 154 #cooling-cells = <2>; 155 }; 156 157 cpu_b1: cpu@500 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a76"; 160 reg = <0x500>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 164 cpu-idle-states = <&CPU_SLEEP>; 165 i-cache-size = <65536>; 166 i-cache-line-size = <64>; 167 i-cache-sets = <256>; 168 d-cache-size = <65536>; 169 d-cache-line-size = <64>; 170 d-cache-sets = <256>; 171 next-level-cache = <&l2_cache_b1>; 172 dynamic-power-coefficient = <416>; 173 #cooling-cells = <2>; 174 }; 175 176 cpu_b2: cpu@600 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a76"; 179 reg = <0x600>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1024>; 182 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 183 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 184 assigned-clock-rates = <816000000>; 185 cpu-idle-states = <&CPU_SLEEP>; 186 i-cache-size = <65536>; 187 i-cache-line-size = <64>; 188 i-cache-sets = <256>; 189 d-cache-size = <65536>; 190 d-cache-line-size = <64>; 191 d-cache-sets = <256>; 192 next-level-cache = <&l2_cache_b2>; 193 dynamic-power-coefficient = <416>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu_b3: cpu@700 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a76"; 200 reg = <0x700>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 204 cpu-idle-states = <&CPU_SLEEP>; 205 i-cache-size = <65536>; 206 i-cache-line-size = <64>; 207 i-cache-sets = <256>; 208 d-cache-size = <65536>; 209 d-cache-line-size = <64>; 210 d-cache-sets = <256>; 211 next-level-cache = <&l2_cache_b3>; 212 dynamic-power-coefficient = <416>; 213 #cooling-cells = <2>; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 CPU_SLEEP: cpu-sleep { 219 compatible = "arm,idle-state"; 220 local-timer-stop; 221 arm,psci-suspend-param = <0x0010000>; 222 entry-latency-us = <100>; 223 exit-latency-us = <120>; 224 min-residency-us = <1000>; 225 }; 226 }; 227 228 l2_cache_l0: l2-cache-l0 { 229 compatible = "cache"; 230 cache-size = <131072>; 231 cache-line-size = <64>; 232 cache-sets = <512>; 233 cache-level = <2>; 234 cache-unified; 235 next-level-cache = <&l3_cache>; 236 }; 237 238 l2_cache_l1: l2-cache-l1 { 239 compatible = "cache"; 240 cache-size = <131072>; 241 cache-line-size = <64>; 242 cache-sets = <512>; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_cache>; 246 }; 247 248 l2_cache_l2: l2-cache-l2 { 249 compatible = "cache"; 250 cache-size = <131072>; 251 cache-line-size = <64>; 252 cache-sets = <512>; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_cache>; 256 }; 257 258 l2_cache_l3: l2-cache-l3 { 259 compatible = "cache"; 260 cache-size = <131072>; 261 cache-line-size = <64>; 262 cache-sets = <512>; 263 cache-level = <2>; 264 cache-unified; 265 next-level-cache = <&l3_cache>; 266 }; 267 268 l2_cache_b0: l2-cache-b0 { 269 compatible = "cache"; 270 cache-size = <524288>; 271 cache-line-size = <64>; 272 cache-sets = <1024>; 273 cache-level = <2>; 274 cache-unified; 275 next-level-cache = <&l3_cache>; 276 }; 277 278 l2_cache_b1: l2-cache-b1 { 279 compatible = "cache"; 280 cache-size = <524288>; 281 cache-line-size = <64>; 282 cache-sets = <1024>; 283 cache-level = <2>; 284 cache-unified; 285 next-level-cache = <&l3_cache>; 286 }; 287 288 l2_cache_b2: l2-cache-b2 { 289 compatible = "cache"; 290 cache-size = <524288>; 291 cache-line-size = <64>; 292 cache-sets = <1024>; 293 cache-level = <2>; 294 cache-unified; 295 next-level-cache = <&l3_cache>; 296 }; 297 298 l2_cache_b3: l2-cache-b3 { 299 compatible = "cache"; 300 cache-size = <524288>; 301 cache-line-size = <64>; 302 cache-sets = <1024>; 303 cache-level = <2>; 304 cache-unified; 305 next-level-cache = <&l3_cache>; 306 }; 307 308 l3_cache: l3-cache { 309 compatible = "cache"; 310 cache-size = <3145728>; 311 cache-line-size = <64>; 312 cache-sets = <4096>; 313 cache-level = <3>; 314 cache-unified; 315 }; 316 }; 317 318 firmware { 319 optee: optee { 320 compatible = "linaro,optee-tz"; 321 method = "smc"; 322 }; 323 324 scmi: scmi { 325 compatible = "arm,scmi-smc"; 326 arm,smc-id = <0x82000010>; 327 shmem = <&scmi_shmem>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 scmi_clk: protocol@14 { 332 reg = <0x14>; 333 #clock-cells = <1>; 334 }; 335 336 scmi_reset: protocol@16 { 337 reg = <0x16>; 338 #reset-cells = <1>; 339 }; 340 }; 341 }; 342 343 pmu-a55 { 344 compatible = "arm,cortex-a55-pmu"; 345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 346 }; 347 348 pmu-a76 { 349 compatible = "arm,cortex-a76-pmu"; 350 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 351 }; 352 353 psci { 354 compatible = "arm,psci-1.0"; 355 method = "smc"; 356 }; 357 358 spll: clock-0 { 359 compatible = "fixed-clock"; 360 clock-frequency = <702000000>; 361 clock-output-names = "spll"; 362 #clock-cells = <0>; 363 }; 364 365 timer { 366 compatible = "arm,armv8-timer"; 367 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 368 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 369 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 370 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 371 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 372 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 373 }; 374 375 xin24m: clock-1 { 376 compatible = "fixed-clock"; 377 clock-frequency = <24000000>; 378 clock-output-names = "xin24m"; 379 #clock-cells = <0>; 380 }; 381 382 xin32k: clock-2 { 383 compatible = "fixed-clock"; 384 clock-frequency = <32768>; 385 clock-output-names = "xin32k"; 386 #clock-cells = <0>; 387 }; 388 389 pmu_sram: sram@10f000 { 390 compatible = "mmio-sram"; 391 reg = <0x0 0x0010f000 0x0 0x100>; 392 ranges = <0 0x0 0x0010f000 0x100>; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 396 scmi_shmem: sram@0 { 397 compatible = "arm,scmi-shmem"; 398 reg = <0x0 0x100>; 399 }; 400 }; 401 402 usb_host0_ehci: usb@fc800000 { 403 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 404 reg = <0x0 0xfc800000 0x0 0x40000>; 405 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 407 phys = <&u2phy2_host>; 408 phy-names = "usb"; 409 power-domains = <&power RK3588_PD_USB>; 410 status = "disabled"; 411 }; 412 413 usb_host0_ohci: usb@fc840000 { 414 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 415 reg = <0x0 0xfc840000 0x0 0x40000>; 416 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 418 phys = <&u2phy2_host>; 419 phy-names = "usb"; 420 power-domains = <&power RK3588_PD_USB>; 421 status = "disabled"; 422 }; 423 424 usb_host1_ehci: usb@fc880000 { 425 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 426 reg = <0x0 0xfc880000 0x0 0x40000>; 427 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 429 phys = <&u2phy3_host>; 430 phy-names = "usb"; 431 power-domains = <&power RK3588_PD_USB>; 432 status = "disabled"; 433 }; 434 435 usb_host1_ohci: usb@fc8c0000 { 436 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 437 reg = <0x0 0xfc8c0000 0x0 0x40000>; 438 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 440 phys = <&u2phy3_host>; 441 phy-names = "usb"; 442 power-domains = <&power RK3588_PD_USB>; 443 status = "disabled"; 444 }; 445 446 sys_grf: syscon@fd58c000 { 447 compatible = "rockchip,rk3588-sys-grf", "syscon"; 448 reg = <0x0 0xfd58c000 0x0 0x1000>; 449 }; 450 451 php_grf: syscon@fd5b0000 { 452 compatible = "rockchip,rk3588-php-grf", "syscon"; 453 reg = <0x0 0xfd5b0000 0x0 0x1000>; 454 }; 455 456 pipe_phy0_grf: syscon@fd5bc000 { 457 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 458 reg = <0x0 0xfd5bc000 0x0 0x100>; 459 }; 460 461 pipe_phy2_grf: syscon@fd5c4000 { 462 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 463 reg = <0x0 0xfd5c4000 0x0 0x100>; 464 }; 465 466 usb2phy2_grf: syscon@fd5d8000 { 467 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 468 reg = <0x0 0xfd5d8000 0x0 0x4000>; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 472 u2phy2: usb2-phy@8000 { 473 compatible = "rockchip,rk3588-usb2phy"; 474 reg = <0x8000 0x10>; 475 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 476 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 477 reset-names = "phy", "apb"; 478 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 479 clock-names = "phyclk"; 480 clock-output-names = "usb480m_phy2"; 481 #clock-cells = <0>; 482 status = "disabled"; 483 484 u2phy2_host: host-port { 485 #phy-cells = <0>; 486 status = "disabled"; 487 }; 488 }; 489 }; 490 491 usb2phy3_grf: syscon@fd5dc000 { 492 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 493 reg = <0x0 0xfd5dc000 0x0 0x4000>; 494 #address-cells = <1>; 495 #size-cells = <1>; 496 497 u2phy3: usb2-phy@c000 { 498 compatible = "rockchip,rk3588-usb2phy"; 499 reg = <0xc000 0x10>; 500 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 501 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 502 reset-names = "phy", "apb"; 503 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 504 clock-names = "phyclk"; 505 clock-output-names = "usb480m_phy3"; 506 #clock-cells = <0>; 507 status = "disabled"; 508 509 u2phy3_host: host-port { 510 #phy-cells = <0>; 511 status = "disabled"; 512 }; 513 }; 514 }; 515 516 ioc: syscon@fd5f0000 { 517 compatible = "rockchip,rk3588-ioc", "syscon"; 518 reg = <0x0 0xfd5f0000 0x0 0x10000>; 519 }; 520 521 system_sram1: sram@fd600000 { 522 compatible = "mmio-sram"; 523 reg = <0x0 0xfd600000 0x0 0x100000>; 524 ranges = <0x0 0x0 0xfd600000 0x100000>; 525 #address-cells = <1>; 526 #size-cells = <1>; 527 }; 528 529 cru: clock-controller@fd7c0000 { 530 compatible = "rockchip,rk3588-cru"; 531 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 532 assigned-clocks = 533 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 534 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 535 <&cru ACLK_CENTER_ROOT>, 536 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 537 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 538 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 539 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 540 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 541 <&cru CLK_GPU>; 542 assigned-clock-rates = 543 <1100000000>, <786432000>, 544 <850000000>, <1188000000>, 545 <702000000>, 546 <400000000>, <500000000>, 547 <800000000>, <100000000>, 548 <400000000>, <100000000>, 549 <200000000>, <500000000>, 550 <375000000>, <150000000>, 551 <200000000>; 552 rockchip,grf = <&php_grf>; 553 #clock-cells = <1>; 554 #reset-cells = <1>; 555 }; 556 557 i2c0: i2c@fd880000 { 558 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 559 reg = <0x0 0xfd880000 0x0 0x1000>; 560 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 561 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 562 clock-names = "i2c", "pclk"; 563 pinctrl-0 = <&i2c0m0_xfer>; 564 pinctrl-names = "default"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 status = "disabled"; 568 }; 569 570 uart0: serial@fd890000 { 571 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 572 reg = <0x0 0xfd890000 0x0 0x100>; 573 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 574 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 575 clock-names = "baudclk", "apb_pclk"; 576 dmas = <&dmac0 6>, <&dmac0 7>; 577 dma-names = "tx", "rx"; 578 pinctrl-0 = <&uart0m1_xfer>; 579 pinctrl-names = "default"; 580 reg-shift = <2>; 581 reg-io-width = <4>; 582 status = "disabled"; 583 }; 584 585 pwm0: pwm@fd8b0000 { 586 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 587 reg = <0x0 0xfd8b0000 0x0 0x10>; 588 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 589 clock-names = "pwm", "pclk"; 590 pinctrl-0 = <&pwm0m0_pins>; 591 pinctrl-names = "default"; 592 #pwm-cells = <3>; 593 status = "disabled"; 594 }; 595 596 pwm1: pwm@fd8b0010 { 597 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 598 reg = <0x0 0xfd8b0010 0x0 0x10>; 599 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 600 clock-names = "pwm", "pclk"; 601 pinctrl-0 = <&pwm1m0_pins>; 602 pinctrl-names = "default"; 603 #pwm-cells = <3>; 604 status = "disabled"; 605 }; 606 607 pwm2: pwm@fd8b0020 { 608 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 609 reg = <0x0 0xfd8b0020 0x0 0x10>; 610 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 611 clock-names = "pwm", "pclk"; 612 pinctrl-0 = <&pwm2m0_pins>; 613 pinctrl-names = "default"; 614 #pwm-cells = <3>; 615 status = "disabled"; 616 }; 617 618 pwm3: pwm@fd8b0030 { 619 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 620 reg = <0x0 0xfd8b0030 0x0 0x10>; 621 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 622 clock-names = "pwm", "pclk"; 623 pinctrl-0 = <&pwm3m0_pins>; 624 pinctrl-names = "default"; 625 #pwm-cells = <3>; 626 status = "disabled"; 627 }; 628 629 pmu: power-management@fd8d8000 { 630 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 631 reg = <0x0 0xfd8d8000 0x0 0x400>; 632 633 power: power-controller { 634 compatible = "rockchip,rk3588-power-controller"; 635 #address-cells = <1>; 636 #power-domain-cells = <1>; 637 #size-cells = <0>; 638 status = "okay"; 639 640 /* These power domains are grouped by VD_NPU */ 641 power-domain@RK3588_PD_NPU { 642 reg = <RK3588_PD_NPU>; 643 #power-domain-cells = <0>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 power-domain@RK3588_PD_NPUTOP { 648 reg = <RK3588_PD_NPUTOP>; 649 clocks = <&cru HCLK_NPU_ROOT>, 650 <&cru PCLK_NPU_ROOT>, 651 <&cru CLK_NPU_DSU0>, 652 <&cru HCLK_NPU_CM0_ROOT>; 653 pm_qos = <&qos_npu0_mwr>, 654 <&qos_npu0_mro>, 655 <&qos_mcu_npu>; 656 #power-domain-cells = <0>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 power-domain@RK3588_PD_NPU1 { 661 reg = <RK3588_PD_NPU1>; 662 clocks = <&cru HCLK_NPU_ROOT>, 663 <&cru PCLK_NPU_ROOT>, 664 <&cru CLK_NPU_DSU0>; 665 pm_qos = <&qos_npu1>; 666 #power-domain-cells = <0>; 667 }; 668 power-domain@RK3588_PD_NPU2 { 669 reg = <RK3588_PD_NPU2>; 670 clocks = <&cru HCLK_NPU_ROOT>, 671 <&cru PCLK_NPU_ROOT>, 672 <&cru CLK_NPU_DSU0>; 673 pm_qos = <&qos_npu2>; 674 #power-domain-cells = <0>; 675 }; 676 }; 677 }; 678 /* These power domains are grouped by VD_GPU */ 679 power-domain@RK3588_PD_GPU { 680 reg = <RK3588_PD_GPU>; 681 clocks = <&cru CLK_GPU>, 682 <&cru CLK_GPU_COREGROUP>, 683 <&cru CLK_GPU_STACKS>; 684 pm_qos = <&qos_gpu_m0>, 685 <&qos_gpu_m1>, 686 <&qos_gpu_m2>, 687 <&qos_gpu_m3>; 688 #power-domain-cells = <0>; 689 }; 690 /* These power domains are grouped by VD_VCODEC */ 691 power-domain@RK3588_PD_VCODEC { 692 reg = <RK3588_PD_VCODEC>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 #power-domain-cells = <0>; 696 697 power-domain@RK3588_PD_RKVDEC0 { 698 reg = <RK3588_PD_RKVDEC0>; 699 clocks = <&cru HCLK_RKVDEC0>, 700 <&cru HCLK_VDPU_ROOT>, 701 <&cru ACLK_VDPU_ROOT>, 702 <&cru ACLK_RKVDEC0>, 703 <&cru ACLK_RKVDEC_CCU>; 704 pm_qos = <&qos_rkvdec0>; 705 #power-domain-cells = <0>; 706 }; 707 power-domain@RK3588_PD_RKVDEC1 { 708 reg = <RK3588_PD_RKVDEC1>; 709 clocks = <&cru HCLK_RKVDEC1>, 710 <&cru HCLK_VDPU_ROOT>, 711 <&cru ACLK_VDPU_ROOT>, 712 <&cru ACLK_RKVDEC1>; 713 pm_qos = <&qos_rkvdec1>; 714 #power-domain-cells = <0>; 715 }; 716 power-domain@RK3588_PD_VENC0 { 717 reg = <RK3588_PD_VENC0>; 718 clocks = <&cru HCLK_RKVENC0>, 719 <&cru ACLK_RKVENC0>; 720 pm_qos = <&qos_rkvenc0_m0ro>, 721 <&qos_rkvenc0_m1ro>, 722 <&qos_rkvenc0_m2wo>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 #power-domain-cells = <0>; 726 727 power-domain@RK3588_PD_VENC1 { 728 reg = <RK3588_PD_VENC1>; 729 clocks = <&cru HCLK_RKVENC1>, 730 <&cru HCLK_RKVENC0>, 731 <&cru ACLK_RKVENC0>, 732 <&cru ACLK_RKVENC1>; 733 pm_qos = <&qos_rkvenc1_m0ro>, 734 <&qos_rkvenc1_m1ro>, 735 <&qos_rkvenc1_m2wo>; 736 #power-domain-cells = <0>; 737 }; 738 }; 739 }; 740 /* These power domains are grouped by VD_LOGIC */ 741 power-domain@RK3588_PD_VDPU { 742 reg = <RK3588_PD_VDPU>; 743 clocks = <&cru HCLK_VDPU_ROOT>, 744 <&cru ACLK_VDPU_LOW_ROOT>, 745 <&cru ACLK_VDPU_ROOT>, 746 <&cru ACLK_JPEG_DECODER_ROOT>, 747 <&cru ACLK_IEP2P0>, 748 <&cru HCLK_IEP2P0>, 749 <&cru ACLK_JPEG_ENCODER0>, 750 <&cru HCLK_JPEG_ENCODER0>, 751 <&cru ACLK_JPEG_ENCODER1>, 752 <&cru HCLK_JPEG_ENCODER1>, 753 <&cru ACLK_JPEG_ENCODER2>, 754 <&cru HCLK_JPEG_ENCODER2>, 755 <&cru ACLK_JPEG_ENCODER3>, 756 <&cru HCLK_JPEG_ENCODER3>, 757 <&cru ACLK_JPEG_DECODER>, 758 <&cru HCLK_JPEG_DECODER>, 759 <&cru ACLK_RGA2>, 760 <&cru HCLK_RGA2>; 761 pm_qos = <&qos_iep>, 762 <&qos_jpeg_dec>, 763 <&qos_jpeg_enc0>, 764 <&qos_jpeg_enc1>, 765 <&qos_jpeg_enc2>, 766 <&qos_jpeg_enc3>, 767 <&qos_rga2_mro>, 768 <&qos_rga2_mwo>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 #power-domain-cells = <0>; 772 773 774 power-domain@RK3588_PD_AV1 { 775 reg = <RK3588_PD_AV1>; 776 clocks = <&cru PCLK_AV1>, 777 <&cru ACLK_AV1>, 778 <&cru HCLK_VDPU_ROOT>; 779 pm_qos = <&qos_av1>; 780 #power-domain-cells = <0>; 781 }; 782 power-domain@RK3588_PD_RKVDEC0 { 783 reg = <RK3588_PD_RKVDEC0>; 784 clocks = <&cru HCLK_RKVDEC0>, 785 <&cru HCLK_VDPU_ROOT>, 786 <&cru ACLK_VDPU_ROOT>, 787 <&cru ACLK_RKVDEC0>; 788 pm_qos = <&qos_rkvdec0>; 789 #power-domain-cells = <0>; 790 }; 791 power-domain@RK3588_PD_RKVDEC1 { 792 reg = <RK3588_PD_RKVDEC1>; 793 clocks = <&cru HCLK_RKVDEC1>, 794 <&cru HCLK_VDPU_ROOT>, 795 <&cru ACLK_VDPU_ROOT>; 796 pm_qos = <&qos_rkvdec1>; 797 #power-domain-cells = <0>; 798 }; 799 power-domain@RK3588_PD_RGA30 { 800 reg = <RK3588_PD_RGA30>; 801 clocks = <&cru ACLK_RGA3_0>, 802 <&cru HCLK_RGA3_0>; 803 pm_qos = <&qos_rga3_0>; 804 #power-domain-cells = <0>; 805 }; 806 }; 807 power-domain@RK3588_PD_VOP { 808 reg = <RK3588_PD_VOP>; 809 clocks = <&cru PCLK_VOP_ROOT>, 810 <&cru HCLK_VOP_ROOT>, 811 <&cru ACLK_VOP>; 812 pm_qos = <&qos_vop_m0>, 813 <&qos_vop_m1>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #power-domain-cells = <0>; 817 818 power-domain@RK3588_PD_VO0 { 819 reg = <RK3588_PD_VO0>; 820 clocks = <&cru PCLK_VO0_ROOT>, 821 <&cru PCLK_VO0_S_ROOT>, 822 <&cru HCLK_VO0_S_ROOT>, 823 <&cru ACLK_VO0_ROOT>, 824 <&cru HCLK_HDCP0>, 825 <&cru ACLK_HDCP0>, 826 <&cru HCLK_VOP_ROOT>; 827 pm_qos = <&qos_hdcp0>; 828 #power-domain-cells = <0>; 829 }; 830 }; 831 power-domain@RK3588_PD_VO1 { 832 reg = <RK3588_PD_VO1>; 833 clocks = <&cru PCLK_VO1_ROOT>, 834 <&cru PCLK_VO1_S_ROOT>, 835 <&cru HCLK_VO1_S_ROOT>, 836 <&cru HCLK_HDCP1>, 837 <&cru ACLK_HDCP1>, 838 <&cru ACLK_HDMIRX_ROOT>, 839 <&cru HCLK_VO1USB_TOP_ROOT>; 840 pm_qos = <&qos_hdcp1>, 841 <&qos_hdmirx>; 842 #power-domain-cells = <0>; 843 }; 844 power-domain@RK3588_PD_VI { 845 reg = <RK3588_PD_VI>; 846 clocks = <&cru HCLK_VI_ROOT>, 847 <&cru PCLK_VI_ROOT>, 848 <&cru HCLK_ISP0>, 849 <&cru ACLK_ISP0>, 850 <&cru HCLK_VICAP>, 851 <&cru ACLK_VICAP>; 852 pm_qos = <&qos_isp0_mro>, 853 <&qos_isp0_mwo>, 854 <&qos_vicap_m0>, 855 <&qos_vicap_m1>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 #power-domain-cells = <0>; 859 860 power-domain@RK3588_PD_ISP1 { 861 reg = <RK3588_PD_ISP1>; 862 clocks = <&cru HCLK_ISP1>, 863 <&cru ACLK_ISP1>, 864 <&cru HCLK_VI_ROOT>, 865 <&cru PCLK_VI_ROOT>; 866 pm_qos = <&qos_isp1_mwo>, 867 <&qos_isp1_mro>; 868 #power-domain-cells = <0>; 869 }; 870 power-domain@RK3588_PD_FEC { 871 reg = <RK3588_PD_FEC>; 872 clocks = <&cru HCLK_FISHEYE0>, 873 <&cru ACLK_FISHEYE0>, 874 <&cru HCLK_FISHEYE1>, 875 <&cru ACLK_FISHEYE1>, 876 <&cru PCLK_VI_ROOT>; 877 pm_qos = <&qos_fisheye0>, 878 <&qos_fisheye1>; 879 #power-domain-cells = <0>; 880 }; 881 }; 882 power-domain@RK3588_PD_RGA31 { 883 reg = <RK3588_PD_RGA31>; 884 clocks = <&cru HCLK_RGA3_1>, 885 <&cru ACLK_RGA3_1>; 886 pm_qos = <&qos_rga3_1>; 887 #power-domain-cells = <0>; 888 }; 889 power-domain@RK3588_PD_USB { 890 reg = <RK3588_PD_USB>; 891 clocks = <&cru PCLK_PHP_ROOT>, 892 <&cru ACLK_USB_ROOT>, 893 <&cru ACLK_USB>, 894 <&cru HCLK_USB_ROOT>, 895 <&cru HCLK_HOST0>, 896 <&cru HCLK_HOST_ARB0>, 897 <&cru HCLK_HOST1>, 898 <&cru HCLK_HOST_ARB1>; 899 pm_qos = <&qos_usb3_0>, 900 <&qos_usb3_1>, 901 <&qos_usb2host_0>, 902 <&qos_usb2host_1>; 903 #power-domain-cells = <0>; 904 }; 905 power-domain@RK3588_PD_GMAC { 906 reg = <RK3588_PD_GMAC>; 907 clocks = <&cru PCLK_PHP_ROOT>, 908 <&cru ACLK_PCIE_ROOT>, 909 <&cru ACLK_PHP_ROOT>; 910 #power-domain-cells = <0>; 911 }; 912 power-domain@RK3588_PD_PCIE { 913 reg = <RK3588_PD_PCIE>; 914 clocks = <&cru PCLK_PHP_ROOT>, 915 <&cru ACLK_PCIE_ROOT>, 916 <&cru ACLK_PHP_ROOT>; 917 #power-domain-cells = <0>; 918 }; 919 power-domain@RK3588_PD_SDIO { 920 reg = <RK3588_PD_SDIO>; 921 clocks = <&cru HCLK_SDIO>, 922 <&cru HCLK_NVM_ROOT>; 923 pm_qos = <&qos_sdio>; 924 #power-domain-cells = <0>; 925 }; 926 power-domain@RK3588_PD_AUDIO { 927 reg = <RK3588_PD_AUDIO>; 928 clocks = <&cru HCLK_AUDIO_ROOT>, 929 <&cru PCLK_AUDIO_ROOT>; 930 #power-domain-cells = <0>; 931 }; 932 power-domain@RK3588_PD_SDMMC { 933 reg = <RK3588_PD_SDMMC>; 934 pm_qos = <&qos_sdmmc>; 935 #power-domain-cells = <0>; 936 }; 937 }; 938 }; 939 940 i2s4_8ch: i2s@fddc0000 { 941 compatible = "rockchip,rk3588-i2s-tdm"; 942 reg = <0x0 0xfddc0000 0x0 0x1000>; 943 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 944 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 945 clock-names = "mclk_tx", "mclk_rx", "hclk"; 946 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 947 assigned-clock-parents = <&cru PLL_AUPLL>; 948 dmas = <&dmac2 0>; 949 dma-names = "tx"; 950 power-domains = <&power RK3588_PD_VO0>; 951 resets = <&cru SRST_M_I2S4_8CH_TX>; 952 reset-names = "tx-m"; 953 #sound-dai-cells = <0>; 954 status = "disabled"; 955 }; 956 957 i2s5_8ch: i2s@fddf0000 { 958 compatible = "rockchip,rk3588-i2s-tdm"; 959 reg = <0x0 0xfddf0000 0x0 0x1000>; 960 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 961 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 962 clock-names = "mclk_tx", "mclk_rx", "hclk"; 963 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 964 assigned-clock-parents = <&cru PLL_AUPLL>; 965 dmas = <&dmac2 2>; 966 dma-names = "tx"; 967 power-domains = <&power RK3588_PD_VO1>; 968 resets = <&cru SRST_M_I2S5_8CH_TX>; 969 reset-names = "tx-m"; 970 #sound-dai-cells = <0>; 971 status = "disabled"; 972 }; 973 974 i2s9_8ch: i2s@fddfc000 { 975 compatible = "rockchip,rk3588-i2s-tdm"; 976 reg = <0x0 0xfddfc000 0x0 0x1000>; 977 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 978 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 979 clock-names = "mclk_tx", "mclk_rx", "hclk"; 980 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 981 assigned-clock-parents = <&cru PLL_AUPLL>; 982 dmas = <&dmac2 23>; 983 dma-names = "rx"; 984 power-domains = <&power RK3588_PD_VO1>; 985 resets = <&cru SRST_M_I2S9_8CH_RX>; 986 reset-names = "rx-m"; 987 #sound-dai-cells = <0>; 988 status = "disabled"; 989 }; 990 991 qos_gpu_m0: qos@fdf35000 { 992 compatible = "rockchip,rk3588-qos", "syscon"; 993 reg = <0x0 0xfdf35000 0x0 0x20>; 994 }; 995 996 qos_gpu_m1: qos@fdf35200 { 997 compatible = "rockchip,rk3588-qos", "syscon"; 998 reg = <0x0 0xfdf35200 0x0 0x20>; 999 }; 1000 1001 qos_gpu_m2: qos@fdf35400 { 1002 compatible = "rockchip,rk3588-qos", "syscon"; 1003 reg = <0x0 0xfdf35400 0x0 0x20>; 1004 }; 1005 1006 qos_gpu_m3: qos@fdf35600 { 1007 compatible = "rockchip,rk3588-qos", "syscon"; 1008 reg = <0x0 0xfdf35600 0x0 0x20>; 1009 }; 1010 1011 qos_rga3_1: qos@fdf36000 { 1012 compatible = "rockchip,rk3588-qos", "syscon"; 1013 reg = <0x0 0xfdf36000 0x0 0x20>; 1014 }; 1015 1016 qos_sdio: qos@fdf39000 { 1017 compatible = "rockchip,rk3588-qos", "syscon"; 1018 reg = <0x0 0xfdf39000 0x0 0x20>; 1019 }; 1020 1021 qos_sdmmc: qos@fdf3d800 { 1022 compatible = "rockchip,rk3588-qos", "syscon"; 1023 reg = <0x0 0xfdf3d800 0x0 0x20>; 1024 }; 1025 1026 qos_usb3_1: qos@fdf3e000 { 1027 compatible = "rockchip,rk3588-qos", "syscon"; 1028 reg = <0x0 0xfdf3e000 0x0 0x20>; 1029 }; 1030 1031 qos_usb3_0: qos@fdf3e200 { 1032 compatible = "rockchip,rk3588-qos", "syscon"; 1033 reg = <0x0 0xfdf3e200 0x0 0x20>; 1034 }; 1035 1036 qos_usb2host_0: qos@fdf3e400 { 1037 compatible = "rockchip,rk3588-qos", "syscon"; 1038 reg = <0x0 0xfdf3e400 0x0 0x20>; 1039 }; 1040 1041 qos_usb2host_1: qos@fdf3e600 { 1042 compatible = "rockchip,rk3588-qos", "syscon"; 1043 reg = <0x0 0xfdf3e600 0x0 0x20>; 1044 }; 1045 1046 qos_fisheye0: qos@fdf40000 { 1047 compatible = "rockchip,rk3588-qos", "syscon"; 1048 reg = <0x0 0xfdf40000 0x0 0x20>; 1049 }; 1050 1051 qos_fisheye1: qos@fdf40200 { 1052 compatible = "rockchip,rk3588-qos", "syscon"; 1053 reg = <0x0 0xfdf40200 0x0 0x20>; 1054 }; 1055 1056 qos_isp0_mro: qos@fdf40400 { 1057 compatible = "rockchip,rk3588-qos", "syscon"; 1058 reg = <0x0 0xfdf40400 0x0 0x20>; 1059 }; 1060 1061 qos_isp0_mwo: qos@fdf40500 { 1062 compatible = "rockchip,rk3588-qos", "syscon"; 1063 reg = <0x0 0xfdf40500 0x0 0x20>; 1064 }; 1065 1066 qos_vicap_m0: qos@fdf40600 { 1067 compatible = "rockchip,rk3588-qos", "syscon"; 1068 reg = <0x0 0xfdf40600 0x0 0x20>; 1069 }; 1070 1071 qos_vicap_m1: qos@fdf40800 { 1072 compatible = "rockchip,rk3588-qos", "syscon"; 1073 reg = <0x0 0xfdf40800 0x0 0x20>; 1074 }; 1075 1076 qos_isp1_mwo: qos@fdf41000 { 1077 compatible = "rockchip,rk3588-qos", "syscon"; 1078 reg = <0x0 0xfdf41000 0x0 0x20>; 1079 }; 1080 1081 qos_isp1_mro: qos@fdf41100 { 1082 compatible = "rockchip,rk3588-qos", "syscon"; 1083 reg = <0x0 0xfdf41100 0x0 0x20>; 1084 }; 1085 1086 qos_rkvenc0_m0ro: qos@fdf60000 { 1087 compatible = "rockchip,rk3588-qos", "syscon"; 1088 reg = <0x0 0xfdf60000 0x0 0x20>; 1089 }; 1090 1091 qos_rkvenc0_m1ro: qos@fdf60200 { 1092 compatible = "rockchip,rk3588-qos", "syscon"; 1093 reg = <0x0 0xfdf60200 0x0 0x20>; 1094 }; 1095 1096 qos_rkvenc0_m2wo: qos@fdf60400 { 1097 compatible = "rockchip,rk3588-qos", "syscon"; 1098 reg = <0x0 0xfdf60400 0x0 0x20>; 1099 }; 1100 1101 qos_rkvenc1_m0ro: qos@fdf61000 { 1102 compatible = "rockchip,rk3588-qos", "syscon"; 1103 reg = <0x0 0xfdf61000 0x0 0x20>; 1104 }; 1105 1106 qos_rkvenc1_m1ro: qos@fdf61200 { 1107 compatible = "rockchip,rk3588-qos", "syscon"; 1108 reg = <0x0 0xfdf61200 0x0 0x20>; 1109 }; 1110 1111 qos_rkvenc1_m2wo: qos@fdf61400 { 1112 compatible = "rockchip,rk3588-qos", "syscon"; 1113 reg = <0x0 0xfdf61400 0x0 0x20>; 1114 }; 1115 1116 qos_rkvdec0: qos@fdf62000 { 1117 compatible = "rockchip,rk3588-qos", "syscon"; 1118 reg = <0x0 0xfdf62000 0x0 0x20>; 1119 }; 1120 1121 qos_rkvdec1: qos@fdf63000 { 1122 compatible = "rockchip,rk3588-qos", "syscon"; 1123 reg = <0x0 0xfdf63000 0x0 0x20>; 1124 }; 1125 1126 qos_av1: qos@fdf64000 { 1127 compatible = "rockchip,rk3588-qos", "syscon"; 1128 reg = <0x0 0xfdf64000 0x0 0x20>; 1129 }; 1130 1131 qos_iep: qos@fdf66000 { 1132 compatible = "rockchip,rk3588-qos", "syscon"; 1133 reg = <0x0 0xfdf66000 0x0 0x20>; 1134 }; 1135 1136 qos_jpeg_dec: qos@fdf66200 { 1137 compatible = "rockchip,rk3588-qos", "syscon"; 1138 reg = <0x0 0xfdf66200 0x0 0x20>; 1139 }; 1140 1141 qos_jpeg_enc0: qos@fdf66400 { 1142 compatible = "rockchip,rk3588-qos", "syscon"; 1143 reg = <0x0 0xfdf66400 0x0 0x20>; 1144 }; 1145 1146 qos_jpeg_enc1: qos@fdf66600 { 1147 compatible = "rockchip,rk3588-qos", "syscon"; 1148 reg = <0x0 0xfdf66600 0x0 0x20>; 1149 }; 1150 1151 qos_jpeg_enc2: qos@fdf66800 { 1152 compatible = "rockchip,rk3588-qos", "syscon"; 1153 reg = <0x0 0xfdf66800 0x0 0x20>; 1154 }; 1155 1156 qos_jpeg_enc3: qos@fdf66a00 { 1157 compatible = "rockchip,rk3588-qos", "syscon"; 1158 reg = <0x0 0xfdf66a00 0x0 0x20>; 1159 }; 1160 1161 qos_rga2_mro: qos@fdf66c00 { 1162 compatible = "rockchip,rk3588-qos", "syscon"; 1163 reg = <0x0 0xfdf66c00 0x0 0x20>; 1164 }; 1165 1166 qos_rga2_mwo: qos@fdf66e00 { 1167 compatible = "rockchip,rk3588-qos", "syscon"; 1168 reg = <0x0 0xfdf66e00 0x0 0x20>; 1169 }; 1170 1171 qos_rga3_0: qos@fdf67000 { 1172 compatible = "rockchip,rk3588-qos", "syscon"; 1173 reg = <0x0 0xfdf67000 0x0 0x20>; 1174 }; 1175 1176 qos_vdpu: qos@fdf67200 { 1177 compatible = "rockchip,rk3588-qos", "syscon"; 1178 reg = <0x0 0xfdf67200 0x0 0x20>; 1179 }; 1180 1181 qos_npu1: qos@fdf70000 { 1182 compatible = "rockchip,rk3588-qos", "syscon"; 1183 reg = <0x0 0xfdf70000 0x0 0x20>; 1184 }; 1185 1186 qos_npu2: qos@fdf71000 { 1187 compatible = "rockchip,rk3588-qos", "syscon"; 1188 reg = <0x0 0xfdf71000 0x0 0x20>; 1189 }; 1190 1191 qos_npu0_mwr: qos@fdf72000 { 1192 compatible = "rockchip,rk3588-qos", "syscon"; 1193 reg = <0x0 0xfdf72000 0x0 0x20>; 1194 }; 1195 1196 qos_npu0_mro: qos@fdf72200 { 1197 compatible = "rockchip,rk3588-qos", "syscon"; 1198 reg = <0x0 0xfdf72200 0x0 0x20>; 1199 }; 1200 1201 qos_mcu_npu: qos@fdf72400 { 1202 compatible = "rockchip,rk3588-qos", "syscon"; 1203 reg = <0x0 0xfdf72400 0x0 0x20>; 1204 }; 1205 1206 qos_hdcp0: qos@fdf80000 { 1207 compatible = "rockchip,rk3588-qos", "syscon"; 1208 reg = <0x0 0xfdf80000 0x0 0x20>; 1209 }; 1210 1211 qos_hdcp1: qos@fdf81000 { 1212 compatible = "rockchip,rk3588-qos", "syscon"; 1213 reg = <0x0 0xfdf81000 0x0 0x20>; 1214 }; 1215 1216 qos_hdmirx: qos@fdf81200 { 1217 compatible = "rockchip,rk3588-qos", "syscon"; 1218 reg = <0x0 0xfdf81200 0x0 0x20>; 1219 }; 1220 1221 qos_vop_m0: qos@fdf82000 { 1222 compatible = "rockchip,rk3588-qos", "syscon"; 1223 reg = <0x0 0xfdf82000 0x0 0x20>; 1224 }; 1225 1226 qos_vop_m1: qos@fdf82200 { 1227 compatible = "rockchip,rk3588-qos", "syscon"; 1228 reg = <0x0 0xfdf82200 0x0 0x20>; 1229 }; 1230 1231 pcie2x1l1: pcie@fe180000 { 1232 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1233 bus-range = <0x30 0x3f>; 1234 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1235 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1236 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1237 clock-names = "aclk_mst", "aclk_slv", 1238 "aclk_dbi", "pclk", 1239 "aux", "pipe"; 1240 device_type = "pci"; 1241 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1242 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1244 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1245 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1246 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1247 #interrupt-cells = <1>; 1248 interrupt-map-mask = <0 0 0 7>; 1249 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1250 <0 0 0 2 &pcie2x1l1_intc 1>, 1251 <0 0 0 3 &pcie2x1l1_intc 2>, 1252 <0 0 0 4 &pcie2x1l1_intc 3>; 1253 linux,pci-domain = <3>; 1254 max-link-speed = <2>; 1255 msi-map = <0x3000 &its0 0x3000 0x1000>; 1256 num-lanes = <1>; 1257 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1258 phy-names = "pcie-phy"; 1259 power-domains = <&power RK3588_PD_PCIE>; 1260 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1261 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1262 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1263 reg = <0xa 0x40c00000 0x0 0x00400000>, 1264 <0x0 0xfe180000 0x0 0x00010000>, 1265 <0x0 0xf3000000 0x0 0x00100000>; 1266 reg-names = "dbi", "apb", "config"; 1267 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1268 reset-names = "pwr", "pipe"; 1269 #address-cells = <3>; 1270 #size-cells = <2>; 1271 status = "disabled"; 1272 1273 pcie2x1l1_intc: legacy-interrupt-controller { 1274 interrupt-controller; 1275 #address-cells = <0>; 1276 #interrupt-cells = <1>; 1277 interrupt-parent = <&gic>; 1278 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1279 }; 1280 }; 1281 1282 pcie2x1l2: pcie@fe190000 { 1283 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1284 bus-range = <0x40 0x4f>; 1285 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1286 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1287 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1288 clock-names = "aclk_mst", "aclk_slv", 1289 "aclk_dbi", "pclk", 1290 "aux", "pipe"; 1291 device_type = "pci"; 1292 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1293 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1294 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1295 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1297 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1298 #interrupt-cells = <1>; 1299 interrupt-map-mask = <0 0 0 7>; 1300 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1301 <0 0 0 2 &pcie2x1l2_intc 1>, 1302 <0 0 0 3 &pcie2x1l2_intc 2>, 1303 <0 0 0 4 &pcie2x1l2_intc 3>; 1304 linux,pci-domain = <4>; 1305 max-link-speed = <2>; 1306 msi-map = <0x4000 &its0 0x4000 0x1000>; 1307 num-lanes = <1>; 1308 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1309 phy-names = "pcie-phy"; 1310 power-domains = <&power RK3588_PD_PCIE>; 1311 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1312 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1313 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1314 reg = <0xa 0x41000000 0x0 0x00400000>, 1315 <0x0 0xfe190000 0x0 0x00010000>, 1316 <0x0 0xf4000000 0x0 0x00100000>; 1317 reg-names = "dbi", "apb", "config"; 1318 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1319 reset-names = "pwr", "pipe"; 1320 #address-cells = <3>; 1321 #size-cells = <2>; 1322 status = "disabled"; 1323 1324 pcie2x1l2_intc: legacy-interrupt-controller { 1325 interrupt-controller; 1326 #address-cells = <0>; 1327 #interrupt-cells = <1>; 1328 interrupt-parent = <&gic>; 1329 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1330 }; 1331 }; 1332 1333 gmac1: ethernet@fe1c0000 { 1334 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1335 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1336 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1337 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1338 interrupt-names = "macirq", "eth_wake_irq"; 1339 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1340 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1341 <&cru CLK_GMAC1_PTP_REF>; 1342 clock-names = "stmmaceth", "clk_mac_ref", 1343 "pclk_mac", "aclk_mac", 1344 "ptp_ref"; 1345 power-domains = <&power RK3588_PD_GMAC>; 1346 resets = <&cru SRST_A_GMAC1>; 1347 reset-names = "stmmaceth"; 1348 rockchip,grf = <&sys_grf>; 1349 rockchip,php-grf = <&php_grf>; 1350 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1351 snps,mixed-burst; 1352 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1353 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1354 snps,tso; 1355 status = "disabled"; 1356 1357 mdio1: mdio { 1358 compatible = "snps,dwmac-mdio"; 1359 #address-cells = <0x1>; 1360 #size-cells = <0x0>; 1361 }; 1362 1363 gmac1_stmmac_axi_setup: stmmac-axi-config { 1364 snps,blen = <0 0 0 0 16 8 4>; 1365 snps,wr_osr_lmt = <4>; 1366 snps,rd_osr_lmt = <8>; 1367 }; 1368 1369 gmac1_mtl_rx_setup: rx-queues-config { 1370 snps,rx-queues-to-use = <2>; 1371 queue0 {}; 1372 queue1 {}; 1373 }; 1374 1375 gmac1_mtl_tx_setup: tx-queues-config { 1376 snps,tx-queues-to-use = <2>; 1377 queue0 {}; 1378 queue1 {}; 1379 }; 1380 }; 1381 1382 sata0: sata@fe210000 { 1383 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1384 reg = <0 0xfe210000 0 0x1000>; 1385 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1386 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1387 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1388 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1389 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1390 ports-implemented = <0x1>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 status = "disabled"; 1394 1395 sata-port@0 { 1396 reg = <0>; 1397 hba-port-cap = <HBA_PORT_FBSCP>; 1398 phys = <&combphy0_ps PHY_TYPE_SATA>; 1399 phy-names = "sata-phy"; 1400 snps,rx-ts-max = <32>; 1401 snps,tx-ts-max = <32>; 1402 }; 1403 }; 1404 1405 sata2: sata@fe230000 { 1406 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1407 reg = <0 0xfe230000 0 0x1000>; 1408 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1409 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1410 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1411 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1412 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1413 ports-implemented = <0x1>; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 status = "disabled"; 1417 1418 sata-port@0 { 1419 reg = <0>; 1420 hba-port-cap = <HBA_PORT_FBSCP>; 1421 phys = <&combphy2_psu PHY_TYPE_SATA>; 1422 phy-names = "sata-phy"; 1423 snps,rx-ts-max = <32>; 1424 snps,tx-ts-max = <32>; 1425 }; 1426 }; 1427 1428 sdmmc: mmc@fe2c0000 { 1429 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1430 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1431 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1432 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1433 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1434 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1435 fifo-depth = <0x100>; 1436 max-frequency = <200000000>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1439 power-domains = <&power RK3588_PD_SDMMC>; 1440 status = "disabled"; 1441 }; 1442 1443 sdio: mmc@fe2d0000 { 1444 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1445 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1446 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1447 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1448 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1449 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1450 fifo-depth = <0x100>; 1451 max-frequency = <200000000>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&sdiom1_pins>; 1454 power-domains = <&power RK3588_PD_SDIO>; 1455 status = "disabled"; 1456 }; 1457 1458 sdhci: mmc@fe2e0000 { 1459 compatible = "rockchip,rk3588-dwcmshc"; 1460 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1461 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1462 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1463 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1464 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1465 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1466 <&cru TMCLK_EMMC>; 1467 clock-names = "core", "bus", "axi", "block", "timer"; 1468 max-frequency = <200000000>; 1469 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1470 <&emmc_cmd>, <&emmc_data_strobe>; 1471 pinctrl-names = "default"; 1472 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1473 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1474 <&cru SRST_T_EMMC>; 1475 reset-names = "core", "bus", "axi", "block", "timer"; 1476 status = "disabled"; 1477 }; 1478 1479 i2s0_8ch: i2s@fe470000 { 1480 compatible = "rockchip,rk3588-i2s-tdm"; 1481 reg = <0x0 0xfe470000 0x0 0x1000>; 1482 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1483 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1484 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1485 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1486 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1487 dmas = <&dmac0 0>, <&dmac0 1>; 1488 dma-names = "tx", "rx"; 1489 power-domains = <&power RK3588_PD_AUDIO>; 1490 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1491 reset-names = "tx-m", "rx-m"; 1492 rockchip,trcm-sync-tx-only; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&i2s0_lrck 1495 &i2s0_sclk 1496 &i2s0_sdi0 1497 &i2s0_sdi1 1498 &i2s0_sdi2 1499 &i2s0_sdi3 1500 &i2s0_sdo0 1501 &i2s0_sdo1 1502 &i2s0_sdo2 1503 &i2s0_sdo3>; 1504 #sound-dai-cells = <0>; 1505 status = "disabled"; 1506 }; 1507 1508 i2s1_8ch: i2s@fe480000 { 1509 compatible = "rockchip,rk3588-i2s-tdm"; 1510 reg = <0x0 0xfe480000 0x0 0x1000>; 1511 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1512 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1513 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1514 dmas = <&dmac0 2>, <&dmac0 3>; 1515 dma-names = "tx", "rx"; 1516 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1517 reset-names = "tx-m", "rx-m"; 1518 rockchip,trcm-sync-tx-only; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&i2s1m0_lrck 1521 &i2s1m0_sclk 1522 &i2s1m0_sdi0 1523 &i2s1m0_sdi1 1524 &i2s1m0_sdi2 1525 &i2s1m0_sdi3 1526 &i2s1m0_sdo0 1527 &i2s1m0_sdo1 1528 &i2s1m0_sdo2 1529 &i2s1m0_sdo3>; 1530 #sound-dai-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 i2s2_2ch: i2s@fe490000 { 1535 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1536 reg = <0x0 0xfe490000 0x0 0x1000>; 1537 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1538 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1539 clock-names = "i2s_clk", "i2s_hclk"; 1540 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1541 assigned-clock-parents = <&cru PLL_AUPLL>; 1542 dmas = <&dmac1 0>, <&dmac1 1>; 1543 dma-names = "tx", "rx"; 1544 power-domains = <&power RK3588_PD_AUDIO>; 1545 pinctrl-names = "default"; 1546 pinctrl-0 = <&i2s2m1_lrck 1547 &i2s2m1_sclk 1548 &i2s2m1_sdi 1549 &i2s2m1_sdo>; 1550 #sound-dai-cells = <0>; 1551 status = "disabled"; 1552 }; 1553 1554 i2s3_2ch: i2s@fe4a0000 { 1555 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1556 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1557 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1558 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1559 clock-names = "i2s_clk", "i2s_hclk"; 1560 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1561 assigned-clock-parents = <&cru PLL_AUPLL>; 1562 dmas = <&dmac1 2>, <&dmac1 3>; 1563 dma-names = "tx", "rx"; 1564 power-domains = <&power RK3588_PD_AUDIO>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&i2s3_lrck 1567 &i2s3_sclk 1568 &i2s3_sdi 1569 &i2s3_sdo>; 1570 #sound-dai-cells = <0>; 1571 status = "disabled"; 1572 }; 1573 1574 gic: interrupt-controller@fe600000 { 1575 compatible = "arm,gic-v3"; 1576 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1577 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1578 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1579 interrupt-controller; 1580 mbi-alias = <0x0 0xfe610000>; 1581 mbi-ranges = <424 56>; 1582 msi-controller; 1583 ranges; 1584 #address-cells = <2>; 1585 #interrupt-cells = <4>; 1586 #size-cells = <2>; 1587 1588 its0: msi-controller@fe640000 { 1589 compatible = "arm,gic-v3-its"; 1590 reg = <0x0 0xfe640000 0x0 0x20000>; 1591 msi-controller; 1592 #msi-cells = <1>; 1593 }; 1594 1595 its1: msi-controller@fe660000 { 1596 compatible = "arm,gic-v3-its"; 1597 reg = <0x0 0xfe660000 0x0 0x20000>; 1598 msi-controller; 1599 #msi-cells = <1>; 1600 }; 1601 1602 ppi-partitions { 1603 ppi_partition0: interrupt-partition-0 { 1604 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1605 }; 1606 1607 ppi_partition1: interrupt-partition-1 { 1608 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1609 }; 1610 }; 1611 }; 1612 1613 dmac0: dma-controller@fea10000 { 1614 compatible = "arm,pl330", "arm,primecell"; 1615 reg = <0x0 0xfea10000 0x0 0x4000>; 1616 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1617 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1618 arm,pl330-periph-burst; 1619 clocks = <&cru ACLK_DMAC0>; 1620 clock-names = "apb_pclk"; 1621 #dma-cells = <1>; 1622 }; 1623 1624 dmac1: dma-controller@fea30000 { 1625 compatible = "arm,pl330", "arm,primecell"; 1626 reg = <0x0 0xfea30000 0x0 0x4000>; 1627 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1628 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1629 arm,pl330-periph-burst; 1630 clocks = <&cru ACLK_DMAC1>; 1631 clock-names = "apb_pclk"; 1632 #dma-cells = <1>; 1633 }; 1634 1635 i2c1: i2c@fea90000 { 1636 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1637 reg = <0x0 0xfea90000 0x0 0x1000>; 1638 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1639 clock-names = "i2c", "pclk"; 1640 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1641 pinctrl-0 = <&i2c1m0_xfer>; 1642 pinctrl-names = "default"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c2: i2c@feaa0000 { 1649 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1650 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1651 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1652 clock-names = "i2c", "pclk"; 1653 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1654 pinctrl-0 = <&i2c2m0_xfer>; 1655 pinctrl-names = "default"; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 i2c3: i2c@feab0000 { 1662 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1663 reg = <0x0 0xfeab0000 0x0 0x1000>; 1664 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1665 clock-names = "i2c", "pclk"; 1666 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1667 pinctrl-0 = <&i2c3m0_xfer>; 1668 pinctrl-names = "default"; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 status = "disabled"; 1672 }; 1673 1674 i2c4: i2c@feac0000 { 1675 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1676 reg = <0x0 0xfeac0000 0x0 0x1000>; 1677 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1678 clock-names = "i2c", "pclk"; 1679 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1680 pinctrl-0 = <&i2c4m0_xfer>; 1681 pinctrl-names = "default"; 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 status = "disabled"; 1685 }; 1686 1687 i2c5: i2c@fead0000 { 1688 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1689 reg = <0x0 0xfead0000 0x0 0x1000>; 1690 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1691 clock-names = "i2c", "pclk"; 1692 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1693 pinctrl-0 = <&i2c5m0_xfer>; 1694 pinctrl-names = "default"; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 status = "disabled"; 1698 }; 1699 1700 timer0: timer@feae0000 { 1701 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1702 reg = <0x0 0xfeae0000 0x0 0x20>; 1703 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 1704 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1705 clock-names = "pclk", "timer"; 1706 }; 1707 1708 wdt: watchdog@feaf0000 { 1709 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1710 reg = <0x0 0xfeaf0000 0x0 0x100>; 1711 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1712 clock-names = "tclk", "pclk"; 1713 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1714 }; 1715 1716 spi0: spi@feb00000 { 1717 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1718 reg = <0x0 0xfeb00000 0x0 0x1000>; 1719 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1720 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1721 clock-names = "spiclk", "apb_pclk"; 1722 dmas = <&dmac0 14>, <&dmac0 15>; 1723 dma-names = "tx", "rx"; 1724 num-cs = <2>; 1725 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1726 pinctrl-names = "default"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 spi1: spi@feb10000 { 1733 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1734 reg = <0x0 0xfeb10000 0x0 0x1000>; 1735 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1736 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1737 clock-names = "spiclk", "apb_pclk"; 1738 dmas = <&dmac0 16>, <&dmac0 17>; 1739 dma-names = "tx", "rx"; 1740 num-cs = <2>; 1741 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1742 pinctrl-names = "default"; 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 status = "disabled"; 1746 }; 1747 1748 spi2: spi@feb20000 { 1749 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1750 reg = <0x0 0xfeb20000 0x0 0x1000>; 1751 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1752 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1753 clock-names = "spiclk", "apb_pclk"; 1754 dmas = <&dmac1 15>, <&dmac1 16>; 1755 dma-names = "tx", "rx"; 1756 num-cs = <2>; 1757 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1758 pinctrl-names = "default"; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 1764 spi3: spi@feb30000 { 1765 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1766 reg = <0x0 0xfeb30000 0x0 0x1000>; 1767 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1768 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1769 clock-names = "spiclk", "apb_pclk"; 1770 dmas = <&dmac1 17>, <&dmac1 18>; 1771 dma-names = "tx", "rx"; 1772 num-cs = <2>; 1773 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1774 pinctrl-names = "default"; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 status = "disabled"; 1778 }; 1779 1780 uart1: serial@feb40000 { 1781 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1782 reg = <0x0 0xfeb40000 0x0 0x100>; 1783 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1784 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1785 clock-names = "baudclk", "apb_pclk"; 1786 dmas = <&dmac0 8>, <&dmac0 9>; 1787 dma-names = "tx", "rx"; 1788 pinctrl-0 = <&uart1m1_xfer>; 1789 pinctrl-names = "default"; 1790 reg-io-width = <4>; 1791 reg-shift = <2>; 1792 status = "disabled"; 1793 }; 1794 1795 uart2: serial@feb50000 { 1796 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1797 reg = <0x0 0xfeb50000 0x0 0x100>; 1798 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1799 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1800 clock-names = "baudclk", "apb_pclk"; 1801 dmas = <&dmac0 10>, <&dmac0 11>; 1802 dma-names = "tx", "rx"; 1803 pinctrl-0 = <&uart2m1_xfer>; 1804 pinctrl-names = "default"; 1805 reg-io-width = <4>; 1806 reg-shift = <2>; 1807 status = "disabled"; 1808 }; 1809 1810 uart3: serial@feb60000 { 1811 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1812 reg = <0x0 0xfeb60000 0x0 0x100>; 1813 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1814 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1815 clock-names = "baudclk", "apb_pclk"; 1816 dmas = <&dmac0 12>, <&dmac0 13>; 1817 dma-names = "tx", "rx"; 1818 pinctrl-0 = <&uart3m1_xfer>; 1819 pinctrl-names = "default"; 1820 reg-io-width = <4>; 1821 reg-shift = <2>; 1822 status = "disabled"; 1823 }; 1824 1825 uart4: serial@feb70000 { 1826 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1827 reg = <0x0 0xfeb70000 0x0 0x100>; 1828 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1829 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1830 clock-names = "baudclk", "apb_pclk"; 1831 dmas = <&dmac1 9>, <&dmac1 10>; 1832 dma-names = "tx", "rx"; 1833 pinctrl-0 = <&uart4m1_xfer>; 1834 pinctrl-names = "default"; 1835 reg-io-width = <4>; 1836 reg-shift = <2>; 1837 status = "disabled"; 1838 }; 1839 1840 uart5: serial@feb80000 { 1841 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1842 reg = <0x0 0xfeb80000 0x0 0x100>; 1843 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 1844 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1845 clock-names = "baudclk", "apb_pclk"; 1846 dmas = <&dmac1 11>, <&dmac1 12>; 1847 dma-names = "tx", "rx"; 1848 pinctrl-0 = <&uart5m1_xfer>; 1849 pinctrl-names = "default"; 1850 reg-io-width = <4>; 1851 reg-shift = <2>; 1852 status = "disabled"; 1853 }; 1854 1855 uart6: serial@feb90000 { 1856 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1857 reg = <0x0 0xfeb90000 0x0 0x100>; 1858 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 1859 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1860 clock-names = "baudclk", "apb_pclk"; 1861 dmas = <&dmac1 13>, <&dmac1 14>; 1862 dma-names = "tx", "rx"; 1863 pinctrl-0 = <&uart6m1_xfer>; 1864 pinctrl-names = "default"; 1865 reg-io-width = <4>; 1866 reg-shift = <2>; 1867 status = "disabled"; 1868 }; 1869 1870 uart7: serial@feba0000 { 1871 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1872 reg = <0x0 0xfeba0000 0x0 0x100>; 1873 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 1874 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1875 clock-names = "baudclk", "apb_pclk"; 1876 dmas = <&dmac2 7>, <&dmac2 8>; 1877 dma-names = "tx", "rx"; 1878 pinctrl-0 = <&uart7m1_xfer>; 1879 pinctrl-names = "default"; 1880 reg-io-width = <4>; 1881 reg-shift = <2>; 1882 status = "disabled"; 1883 }; 1884 1885 uart8: serial@febb0000 { 1886 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1887 reg = <0x0 0xfebb0000 0x0 0x100>; 1888 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 1889 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1890 clock-names = "baudclk", "apb_pclk"; 1891 dmas = <&dmac2 9>, <&dmac2 10>; 1892 dma-names = "tx", "rx"; 1893 pinctrl-0 = <&uart8m1_xfer>; 1894 pinctrl-names = "default"; 1895 reg-io-width = <4>; 1896 reg-shift = <2>; 1897 status = "disabled"; 1898 }; 1899 1900 uart9: serial@febc0000 { 1901 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1902 reg = <0x0 0xfebc0000 0x0 0x100>; 1903 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 1904 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1905 clock-names = "baudclk", "apb_pclk"; 1906 dmas = <&dmac2 11>, <&dmac2 12>; 1907 dma-names = "tx", "rx"; 1908 pinctrl-0 = <&uart9m1_xfer>; 1909 pinctrl-names = "default"; 1910 reg-io-width = <4>; 1911 reg-shift = <2>; 1912 status = "disabled"; 1913 }; 1914 1915 pwm4: pwm@febd0000 { 1916 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1917 reg = <0x0 0xfebd0000 0x0 0x10>; 1918 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1919 clock-names = "pwm", "pclk"; 1920 pinctrl-0 = <&pwm4m0_pins>; 1921 pinctrl-names = "default"; 1922 #pwm-cells = <3>; 1923 status = "disabled"; 1924 }; 1925 1926 pwm5: pwm@febd0010 { 1927 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1928 reg = <0x0 0xfebd0010 0x0 0x10>; 1929 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1930 clock-names = "pwm", "pclk"; 1931 pinctrl-0 = <&pwm5m0_pins>; 1932 pinctrl-names = "default"; 1933 #pwm-cells = <3>; 1934 status = "disabled"; 1935 }; 1936 1937 pwm6: pwm@febd0020 { 1938 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1939 reg = <0x0 0xfebd0020 0x0 0x10>; 1940 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1941 clock-names = "pwm", "pclk"; 1942 pinctrl-0 = <&pwm6m0_pins>; 1943 pinctrl-names = "default"; 1944 #pwm-cells = <3>; 1945 status = "disabled"; 1946 }; 1947 1948 pwm7: pwm@febd0030 { 1949 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1950 reg = <0x0 0xfebd0030 0x0 0x10>; 1951 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1952 clock-names = "pwm", "pclk"; 1953 pinctrl-0 = <&pwm7m0_pins>; 1954 pinctrl-names = "default"; 1955 #pwm-cells = <3>; 1956 status = "disabled"; 1957 }; 1958 1959 pwm8: pwm@febe0000 { 1960 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1961 reg = <0x0 0xfebe0000 0x0 0x10>; 1962 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1963 clock-names = "pwm", "pclk"; 1964 pinctrl-0 = <&pwm8m0_pins>; 1965 pinctrl-names = "default"; 1966 #pwm-cells = <3>; 1967 status = "disabled"; 1968 }; 1969 1970 pwm9: pwm@febe0010 { 1971 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1972 reg = <0x0 0xfebe0010 0x0 0x10>; 1973 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1974 clock-names = "pwm", "pclk"; 1975 pinctrl-0 = <&pwm9m0_pins>; 1976 pinctrl-names = "default"; 1977 #pwm-cells = <3>; 1978 status = "disabled"; 1979 }; 1980 1981 pwm10: pwm@febe0020 { 1982 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1983 reg = <0x0 0xfebe0020 0x0 0x10>; 1984 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1985 clock-names = "pwm", "pclk"; 1986 pinctrl-0 = <&pwm10m0_pins>; 1987 pinctrl-names = "default"; 1988 #pwm-cells = <3>; 1989 status = "disabled"; 1990 }; 1991 1992 pwm11: pwm@febe0030 { 1993 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1994 reg = <0x0 0xfebe0030 0x0 0x10>; 1995 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1996 clock-names = "pwm", "pclk"; 1997 pinctrl-0 = <&pwm11m0_pins>; 1998 pinctrl-names = "default"; 1999 #pwm-cells = <3>; 2000 status = "disabled"; 2001 }; 2002 2003 pwm12: pwm@febf0000 { 2004 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2005 reg = <0x0 0xfebf0000 0x0 0x10>; 2006 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2007 clock-names = "pwm", "pclk"; 2008 pinctrl-0 = <&pwm12m0_pins>; 2009 pinctrl-names = "default"; 2010 #pwm-cells = <3>; 2011 status = "disabled"; 2012 }; 2013 2014 pwm13: pwm@febf0010 { 2015 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2016 reg = <0x0 0xfebf0010 0x0 0x10>; 2017 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2018 clock-names = "pwm", "pclk"; 2019 pinctrl-0 = <&pwm13m0_pins>; 2020 pinctrl-names = "default"; 2021 #pwm-cells = <3>; 2022 status = "disabled"; 2023 }; 2024 2025 pwm14: pwm@febf0020 { 2026 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2027 reg = <0x0 0xfebf0020 0x0 0x10>; 2028 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2029 clock-names = "pwm", "pclk"; 2030 pinctrl-0 = <&pwm14m0_pins>; 2031 pinctrl-names = "default"; 2032 #pwm-cells = <3>; 2033 status = "disabled"; 2034 }; 2035 2036 pwm15: pwm@febf0030 { 2037 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2038 reg = <0x0 0xfebf0030 0x0 0x10>; 2039 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2040 clock-names = "pwm", "pclk"; 2041 pinctrl-0 = <&pwm15m0_pins>; 2042 pinctrl-names = "default"; 2043 #pwm-cells = <3>; 2044 status = "disabled"; 2045 }; 2046 2047 tsadc: tsadc@fec00000 { 2048 compatible = "rockchip,rk3588-tsadc"; 2049 reg = <0x0 0xfec00000 0x0 0x400>; 2050 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2051 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2052 clock-names = "tsadc", "apb_pclk"; 2053 assigned-clocks = <&cru CLK_TSADC>; 2054 assigned-clock-rates = <2000000>; 2055 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2056 reset-names = "tsadc-apb", "tsadc"; 2057 rockchip,hw-tshut-temp = <120000>; 2058 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2059 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2060 pinctrl-0 = <&tsadc_gpio_func>; 2061 pinctrl-1 = <&tsadc_shut>; 2062 pinctrl-names = "gpio", "otpout"; 2063 #thermal-sensor-cells = <1>; 2064 status = "disabled"; 2065 }; 2066 2067 saradc: adc@fec10000 { 2068 compatible = "rockchip,rk3588-saradc"; 2069 reg = <0x0 0xfec10000 0x0 0x10000>; 2070 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2071 #io-channel-cells = <1>; 2072 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2073 clock-names = "saradc", "apb_pclk"; 2074 resets = <&cru SRST_P_SARADC>; 2075 reset-names = "saradc-apb"; 2076 status = "disabled"; 2077 }; 2078 2079 i2c6: i2c@fec80000 { 2080 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2081 reg = <0x0 0xfec80000 0x0 0x1000>; 2082 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2083 clock-names = "i2c", "pclk"; 2084 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2085 pinctrl-0 = <&i2c6m0_xfer>; 2086 pinctrl-names = "default"; 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 status = "disabled"; 2090 }; 2091 2092 i2c7: i2c@fec90000 { 2093 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2094 reg = <0x0 0xfec90000 0x0 0x1000>; 2095 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2096 clock-names = "i2c", "pclk"; 2097 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2098 pinctrl-0 = <&i2c7m0_xfer>; 2099 pinctrl-names = "default"; 2100 #address-cells = <1>; 2101 #size-cells = <0>; 2102 status = "disabled"; 2103 }; 2104 2105 i2c8: i2c@feca0000 { 2106 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2107 reg = <0x0 0xfeca0000 0x0 0x1000>; 2108 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2109 clock-names = "i2c", "pclk"; 2110 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2111 pinctrl-0 = <&i2c8m0_xfer>; 2112 pinctrl-names = "default"; 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 status = "disabled"; 2116 }; 2117 2118 spi4: spi@fecb0000 { 2119 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2120 reg = <0x0 0xfecb0000 0x0 0x1000>; 2121 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2122 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2123 clock-names = "spiclk", "apb_pclk"; 2124 dmas = <&dmac2 13>, <&dmac2 14>; 2125 dma-names = "tx", "rx"; 2126 num-cs = <2>; 2127 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2128 pinctrl-names = "default"; 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 status = "disabled"; 2132 }; 2133 2134 otp: efuse@fecc0000 { 2135 compatible = "rockchip,rk3588-otp"; 2136 reg = <0x0 0xfecc0000 0x0 0x400>; 2137 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2138 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2139 clock-names = "otp", "apb_pclk", "phy", "arb"; 2140 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2141 <&cru SRST_OTPC_ARB>; 2142 reset-names = "otp", "apb", "arb"; 2143 #address-cells = <1>; 2144 #size-cells = <1>; 2145 2146 cpu_code: cpu-code@2 { 2147 reg = <0x02 0x2>; 2148 }; 2149 2150 otp_id: id@7 { 2151 reg = <0x07 0x10>; 2152 }; 2153 2154 cpub0_leakage: cpu-leakage@17 { 2155 reg = <0x17 0x1>; 2156 }; 2157 2158 cpub1_leakage: cpu-leakage@18 { 2159 reg = <0x18 0x1>; 2160 }; 2161 2162 cpul_leakage: cpu-leakage@19 { 2163 reg = <0x19 0x1>; 2164 }; 2165 2166 log_leakage: log-leakage@1a { 2167 reg = <0x1a 0x1>; 2168 }; 2169 2170 gpu_leakage: gpu-leakage@1b { 2171 reg = <0x1b 0x1>; 2172 }; 2173 2174 otp_cpu_version: cpu-version@1c { 2175 reg = <0x1c 0x1>; 2176 bits = <3 3>; 2177 }; 2178 2179 npu_leakage: npu-leakage@28 { 2180 reg = <0x28 0x1>; 2181 }; 2182 2183 codec_leakage: codec-leakage@29 { 2184 reg = <0x29 0x1>; 2185 }; 2186 }; 2187 2188 dmac2: dma-controller@fed10000 { 2189 compatible = "arm,pl330", "arm,primecell"; 2190 reg = <0x0 0xfed10000 0x0 0x4000>; 2191 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2192 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2193 arm,pl330-periph-burst; 2194 clocks = <&cru ACLK_DMAC2>; 2195 clock-names = "apb_pclk"; 2196 #dma-cells = <1>; 2197 }; 2198 2199 combphy0_ps: phy@fee00000 { 2200 compatible = "rockchip,rk3588-naneng-combphy"; 2201 reg = <0x0 0xfee00000 0x0 0x100>; 2202 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2203 <&cru PCLK_PHP_ROOT>; 2204 clock-names = "ref", "apb", "pipe"; 2205 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2206 assigned-clock-rates = <100000000>; 2207 #phy-cells = <1>; 2208 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2209 reset-names = "phy", "apb"; 2210 rockchip,pipe-grf = <&php_grf>; 2211 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2212 status = "disabled"; 2213 }; 2214 2215 combphy2_psu: phy@fee20000 { 2216 compatible = "rockchip,rk3588-naneng-combphy"; 2217 reg = <0x0 0xfee20000 0x0 0x100>; 2218 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2219 <&cru PCLK_PHP_ROOT>; 2220 clock-names = "ref", "apb", "pipe"; 2221 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2222 assigned-clock-rates = <100000000>; 2223 #phy-cells = <1>; 2224 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2225 reset-names = "phy", "apb"; 2226 rockchip,pipe-grf = <&php_grf>; 2227 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2228 status = "disabled"; 2229 }; 2230 2231 system_sram2: sram@ff001000 { 2232 compatible = "mmio-sram"; 2233 reg = <0x0 0xff001000 0x0 0xef000>; 2234 ranges = <0x0 0x0 0xff001000 0xef000>; 2235 #address-cells = <1>; 2236 #size-cells = <1>; 2237 }; 2238 2239 pinctrl: pinctrl { 2240 compatible = "rockchip,rk3588-pinctrl"; 2241 ranges; 2242 rockchip,grf = <&ioc>; 2243 #address-cells = <2>; 2244 #size-cells = <2>; 2245 2246 gpio0: gpio@fd8a0000 { 2247 compatible = "rockchip,gpio-bank"; 2248 reg = <0x0 0xfd8a0000 0x0 0x100>; 2249 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2250 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2251 gpio-controller; 2252 gpio-ranges = <&pinctrl 0 0 32>; 2253 interrupt-controller; 2254 #gpio-cells = <2>; 2255 #interrupt-cells = <2>; 2256 }; 2257 2258 gpio1: gpio@fec20000 { 2259 compatible = "rockchip,gpio-bank"; 2260 reg = <0x0 0xfec20000 0x0 0x100>; 2261 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2262 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2263 gpio-controller; 2264 gpio-ranges = <&pinctrl 0 32 32>; 2265 interrupt-controller; 2266 #gpio-cells = <2>; 2267 #interrupt-cells = <2>; 2268 }; 2269 2270 gpio2: gpio@fec30000 { 2271 compatible = "rockchip,gpio-bank"; 2272 reg = <0x0 0xfec30000 0x0 0x100>; 2273 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2274 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2275 gpio-controller; 2276 gpio-ranges = <&pinctrl 0 64 32>; 2277 interrupt-controller; 2278 #gpio-cells = <2>; 2279 #interrupt-cells = <2>; 2280 }; 2281 2282 gpio3: gpio@fec40000 { 2283 compatible = "rockchip,gpio-bank"; 2284 reg = <0x0 0xfec40000 0x0 0x100>; 2285 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2286 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2287 gpio-controller; 2288 gpio-ranges = <&pinctrl 0 96 32>; 2289 interrupt-controller; 2290 #gpio-cells = <2>; 2291 #interrupt-cells = <2>; 2292 }; 2293 2294 gpio4: gpio@fec50000 { 2295 compatible = "rockchip,gpio-bank"; 2296 reg = <0x0 0xfec50000 0x0 0x100>; 2297 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2298 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2299 gpio-controller; 2300 gpio-ranges = <&pinctrl 0 128 32>; 2301 interrupt-controller; 2302 #gpio-cells = <2>; 2303 #interrupt-cells = <2>; 2304 }; 2305 }; 2306 }; 2307 2308 #include "rk3588s-pinctrl.dtsi" 2309