xref: /openbmc/linux/drivers/pwm/pwm-xilinx.c (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
4   *
5   * Limitations:
6   * - When changing both duty cycle and period, we may end up with one cycle
7   *   with the old duty cycle and the new period. This is because the counters
8   *   may only be reloaded by first stopping them, or by letting them be
9   *   automatically reloaded at the end of a cycle. If this automatic reload
10   *   happens after we set TLR0 but before we set TLR1 then we will have a
11   *   bad cycle. This could probably be fixed by reading TCR0 just before
12   *   reprogramming, but I think it would add complexity for little gain.
13   * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
14   *   possible by stopping the counters at an appropriate point in the cycle,
15   *   but this is not (yet) implemented.
16   * - Only produces "normal" output.
17   * - Always produces low output if disabled.
18   */
19  
20  #include <clocksource/timer-xilinx.h>
21  #include <linux/clk.h>
22  #include <linux/clk-provider.h>
23  #include <linux/device.h>
24  #include <linux/module.h>
25  #include <linux/of.h>
26  #include <linux/platform_device.h>
27  #include <linux/pwm.h>
28  #include <linux/regmap.h>
29  
30  /*
31   * The following functions are "common" to drivers for this device, and may be
32   * exported at a future date.
33   */
xilinx_timer_tlr_cycles(struct xilinx_timer_priv * priv,u32 tcsr,u64 cycles)34  u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
35  			    u64 cycles)
36  {
37  	WARN_ON(cycles < 2 || cycles - 2 > priv->max);
38  
39  	if (tcsr & TCSR_UDT)
40  		return cycles - 2;
41  	return priv->max - cycles + 2;
42  }
43  
xilinx_timer_get_period(struct xilinx_timer_priv * priv,u32 tlr,u32 tcsr)44  unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
45  				     u32 tlr, u32 tcsr)
46  {
47  	u64 cycles;
48  
49  	if (tcsr & TCSR_UDT)
50  		cycles = tlr + 2;
51  	else
52  		cycles = (u64)priv->max - tlr + 2;
53  
54  	/* cycles has a max of 2^32 + 2, so we can't overflow */
55  	return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC,
56  				  clk_get_rate(priv->clk));
57  }
58  
59  /*
60   * The idea here is to capture whether the PWM is actually running (e.g.
61   * because we or the bootloader set it up) and we need to be careful to ensure
62   * we don't cause a glitch. According to the data sheet, to enable the PWM we
63   * need to
64   *
65   * - Set both timers to generate mode (MDT=1)
66   * - Set both timers to PWM mode (PWMA=1)
67   * - Enable the generate out signals (GENT=1)
68   *
69   * In addition,
70   *
71   * - The timer must be running (ENT=1)
72   * - The timer must auto-reload TLR into TCR (ARHT=1)
73   * - We must not be in the process of loading TLR into TCR (LOAD=0)
74   * - Cascade mode must be disabled (CASC=0)
75   *
76   * If any of these differ from usual, then the PWM is either disabled, or is
77   * running in a mode that this driver does not support.
78   */
79  #define TCSR_PWM_SET (TCSR_GENT | TCSR_ARHT | TCSR_ENT | TCSR_PWMA)
80  #define TCSR_PWM_CLEAR (TCSR_MDT | TCSR_LOAD)
81  #define TCSR_PWM_MASK (TCSR_PWM_SET | TCSR_PWM_CLEAR)
82  
83  struct xilinx_pwm_device {
84  	struct pwm_chip chip;
85  	struct xilinx_timer_priv priv;
86  };
87  
88  static inline struct xilinx_timer_priv
xilinx_pwm_chip_to_priv(struct pwm_chip * chip)89  *xilinx_pwm_chip_to_priv(struct pwm_chip *chip)
90  {
91  	return &container_of(chip, struct xilinx_pwm_device, chip)->priv;
92  }
93  
xilinx_timer_pwm_enabled(u32 tcsr0,u32 tcsr1)94  static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1)
95  {
96  	return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET &&
97  		(TCSR_PWM_MASK & tcsr1) == TCSR_PWM_SET;
98  }
99  
xilinx_pwm_apply(struct pwm_chip * chip,struct pwm_device * unused,const struct pwm_state * state)100  static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
101  			    const struct pwm_state *state)
102  {
103  	struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
104  	u32 tlr0, tlr1, tcsr0, tcsr1;
105  	u64 period_cycles, duty_cycles;
106  	unsigned long rate;
107  
108  	if (state->polarity != PWM_POLARITY_NORMAL)
109  		return -EINVAL;
110  
111  	/*
112  	 * To be representable by TLR, cycles must be between 2 and
113  	 * priv->max + 2. To enforce this we can reduce the cycles, but we may
114  	 * not increase them. Caveat emptor: while this does result in more
115  	 * predictable rounding, it may also result in a completely different
116  	 * duty cycle (% high time) than what was requested.
117  	 */
118  	rate = clk_get_rate(priv->clk);
119  	/* Avoid overflow */
120  	period_cycles = min_t(u64, state->period, U32_MAX * NSEC_PER_SEC);
121  	period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC);
122  	period_cycles = min_t(u64, period_cycles, priv->max + 2);
123  	if (period_cycles < 2)
124  		return -ERANGE;
125  
126  	/* Same thing for duty cycles */
127  	duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC);
128  	duty_cycles = mul_u64_u32_div(duty_cycles, rate, NSEC_PER_SEC);
129  	duty_cycles = min_t(u64, duty_cycles, priv->max + 2);
130  
131  	/*
132  	 * If we specify 100% duty cycle, we will get 0% instead, so decrease
133  	 * the duty cycle count by one.
134  	 */
135  	if (duty_cycles >= period_cycles)
136  		duty_cycles = period_cycles - 1;
137  
138  	/* Round down to 0% duty cycle for unrepresentable duty cycles */
139  	if (duty_cycles < 2)
140  		duty_cycles = period_cycles;
141  
142  	regmap_read(priv->map, TCSR0, &tcsr0);
143  	regmap_read(priv->map, TCSR1, &tcsr1);
144  	tlr0 = xilinx_timer_tlr_cycles(priv, tcsr0, period_cycles);
145  	tlr1 = xilinx_timer_tlr_cycles(priv, tcsr1, duty_cycles);
146  	regmap_write(priv->map, TLR0, tlr0);
147  	regmap_write(priv->map, TLR1, tlr1);
148  
149  	if (state->enabled) {
150  		/*
151  		 * If the PWM is already running, then the counters will be
152  		 * reloaded at the end of the current cycle.
153  		 */
154  		if (!xilinx_timer_pwm_enabled(tcsr0, tcsr1)) {
155  			/* Load TLR into TCR */
156  			regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD);
157  			regmap_write(priv->map, TCSR1, tcsr1 | TCSR_LOAD);
158  			/* Enable timers all at once with ENALL */
159  			tcsr0 = (TCSR_PWM_SET & ~TCSR_ENT) | (tcsr0 & TCSR_UDT);
160  			tcsr1 = TCSR_PWM_SET | TCSR_ENALL | (tcsr1 & TCSR_UDT);
161  			regmap_write(priv->map, TCSR0, tcsr0);
162  			regmap_write(priv->map, TCSR1, tcsr1);
163  		}
164  	} else {
165  		regmap_write(priv->map, TCSR0, 0);
166  		regmap_write(priv->map, TCSR1, 0);
167  	}
168  
169  	return 0;
170  }
171  
xilinx_pwm_get_state(struct pwm_chip * chip,struct pwm_device * unused,struct pwm_state * state)172  static int xilinx_pwm_get_state(struct pwm_chip *chip,
173  				struct pwm_device *unused,
174  				struct pwm_state *state)
175  {
176  	struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
177  	u32 tlr0, tlr1, tcsr0, tcsr1;
178  
179  	regmap_read(priv->map, TLR0, &tlr0);
180  	regmap_read(priv->map, TLR1, &tlr1);
181  	regmap_read(priv->map, TCSR0, &tcsr0);
182  	regmap_read(priv->map, TCSR1, &tcsr1);
183  	state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);
184  	state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);
185  	state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);
186  	state->polarity = PWM_POLARITY_NORMAL;
187  
188  	/*
189  	 * 100% duty cycle results in constant low output. This may be (very)
190  	 * wrong if rate > 1 GHz, so fix this if you have such hardware :)
191  	 */
192  	if (state->period == state->duty_cycle)
193  		state->duty_cycle = 0;
194  
195  	return 0;
196  }
197  
198  static const struct pwm_ops xilinx_pwm_ops = {
199  	.apply = xilinx_pwm_apply,
200  	.get_state = xilinx_pwm_get_state,
201  	.owner = THIS_MODULE,
202  };
203  
204  static const struct regmap_config xilinx_pwm_regmap_config = {
205  	.reg_bits = 32,
206  	.reg_stride = 4,
207  	.val_bits = 32,
208  	.val_format_endian = REGMAP_ENDIAN_LITTLE,
209  	.max_register = TCR1,
210  };
211  
xilinx_pwm_probe(struct platform_device * pdev)212  static int xilinx_pwm_probe(struct platform_device *pdev)
213  {
214  	int ret;
215  	struct device *dev = &pdev->dev;
216  	struct device_node *np = dev->of_node;
217  	struct xilinx_timer_priv *priv;
218  	struct xilinx_pwm_device *xilinx_pwm;
219  	u32 pwm_cells, one_timer, width;
220  	void __iomem *regs;
221  
222  	/* If there are no PWM cells, this binding is for a timer */
223  	ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells);
224  	if (ret == -EINVAL)
225  		return -ENODEV;
226  	if (ret)
227  		return dev_err_probe(dev, ret, "could not read #pwm-cells\n");
228  
229  	xilinx_pwm = devm_kzalloc(dev, sizeof(*xilinx_pwm), GFP_KERNEL);
230  	if (!xilinx_pwm)
231  		return -ENOMEM;
232  	platform_set_drvdata(pdev, xilinx_pwm);
233  	priv = &xilinx_pwm->priv;
234  
235  	regs = devm_platform_ioremap_resource(pdev, 0);
236  	if (IS_ERR(regs))
237  		return PTR_ERR(regs);
238  
239  	priv->map = devm_regmap_init_mmio(dev, regs,
240  					  &xilinx_pwm_regmap_config);
241  	if (IS_ERR(priv->map))
242  		return dev_err_probe(dev, PTR_ERR(priv->map),
243  				     "Could not create regmap\n");
244  
245  	ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer);
246  	if (ret)
247  		return dev_err_probe(dev, ret,
248  				     "Could not read xlnx,one-timer-only\n");
249  
250  	if (one_timer)
251  		return dev_err_probe(dev, -EINVAL,
252  				     "Two timers required for PWM mode\n");
253  
254  	ret = of_property_read_u32(np, "xlnx,count-width", &width);
255  	if (ret == -EINVAL)
256  		width = 32;
257  	else if (ret)
258  		return dev_err_probe(dev, ret,
259  				     "Could not read xlnx,count-width\n");
260  
261  	if (width != 8 && width != 16 && width != 32)
262  		return dev_err_probe(dev, -EINVAL,
263  				     "Invalid counter width %d\n", width);
264  	priv->max = BIT_ULL(width) - 1;
265  
266  	/*
267  	 * The polarity of the Generate Out signals must be active high for PWM
268  	 * mode to work. We could determine this from the device tree, but
269  	 * alas, such properties are not allowed to be used.
270  	 */
271  
272  	priv->clk = devm_clk_get(dev, "s_axi_aclk");
273  	if (IS_ERR(priv->clk))
274  		return dev_err_probe(dev, PTR_ERR(priv->clk),
275  				     "Could not get clock\n");
276  
277  	ret = clk_prepare_enable(priv->clk);
278  	if (ret)
279  		return dev_err_probe(dev, ret, "Clock enable failed\n");
280  	clk_rate_exclusive_get(priv->clk);
281  
282  	xilinx_pwm->chip.dev = dev;
283  	xilinx_pwm->chip.ops = &xilinx_pwm_ops;
284  	xilinx_pwm->chip.npwm = 1;
285  	ret = pwmchip_add(&xilinx_pwm->chip);
286  	if (ret) {
287  		clk_rate_exclusive_put(priv->clk);
288  		clk_disable_unprepare(priv->clk);
289  		return dev_err_probe(dev, ret, "Could not register PWM chip\n");
290  	}
291  
292  	return 0;
293  }
294  
xilinx_pwm_remove(struct platform_device * pdev)295  static void xilinx_pwm_remove(struct platform_device *pdev)
296  {
297  	struct xilinx_pwm_device *xilinx_pwm = platform_get_drvdata(pdev);
298  
299  	pwmchip_remove(&xilinx_pwm->chip);
300  	clk_rate_exclusive_put(xilinx_pwm->priv.clk);
301  	clk_disable_unprepare(xilinx_pwm->priv.clk);
302  }
303  
304  static const struct of_device_id xilinx_pwm_of_match[] = {
305  	{ .compatible = "xlnx,xps-timer-1.00.a", },
306  	{},
307  };
308  MODULE_DEVICE_TABLE(of, xilinx_pwm_of_match);
309  
310  static struct platform_driver xilinx_pwm_driver = {
311  	.probe = xilinx_pwm_probe,
312  	.remove_new = xilinx_pwm_remove,
313  	.driver = {
314  		.name = "xilinx-pwm",
315  		.of_match_table = of_match_ptr(xilinx_pwm_of_match),
316  	},
317  };
318  module_platform_driver(xilinx_pwm_driver);
319  
320  MODULE_ALIAS("platform:xilinx-pwm");
321  MODULE_DESCRIPTION("PWM driver for Xilinx LogiCORE IP AXI Timer");
322  MODULE_LICENSE("GPL");
323