1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/console.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/sys_soc.h>
30
31 #include "8250.h"
32
33 #define DEFAULT_CLK_SPEED 48000000
34 #define OMAP_UART_REGSHIFT 2
35
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
39 /*
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
42 */
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
44 #define UART_HAS_EFR2 BIT(4)
45 #define UART_HAS_RHR_IT_DIS BIT(5)
46 #define UART_RX_TIMEOUT_QUIRK BIT(6)
47 #define UART_HAS_NATIVE_RS485 BIT(7)
48
49 #define OMAP_UART_FCR_RX_TRIG 6
50 #define OMAP_UART_FCR_TX_TRIG 4
51
52 /* SCR register bitmasks */
53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
59
60 /* MVR register bitmasks */
61 #define OMAP_UART_MVR_SCHEME_SHIFT 30
62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
65 #define OMAP_UART_MVR_MAJ_MASK 0x700
66 #define OMAP_UART_MVR_MAJ_SHIFT 8
67 #define OMAP_UART_MVR_MIN_MASK 0x3f
68
69 /* SYSC register bitmasks */
70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
71
72 /* SYSS register bitmasks */
73 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
74
75 #define UART_TI752_TLR_TX 0
76 #define UART_TI752_TLR_RX 4
77
78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
79 #define TRIGGER_FCR_MASK(x) (x & 3)
80
81 /* Enable XON/XOFF flow control on output */
82 #define OMAP_UART_SW_TX 0x08
83 /* Enable XON/XOFF flow control on input */
84 #define OMAP_UART_SW_RX 0x02
85
86 #define OMAP_UART_WER_MOD_WKUP 0x7f
87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
88
89 #define TX_TRIGGER 1
90 #define RX_TRIGGER 48
91
92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
94
95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
96
97 #define OMAP_UART_REV_46 0x0406
98 #define OMAP_UART_REV_52 0x0502
99 #define OMAP_UART_REV_63 0x0603
100
101 /* Interrupt Enable Register 2 */
102 #define UART_OMAP_IER2 0x1B
103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
104
105 /* Mode Definition Register 3 */
106 #define UART_OMAP_MDR3 0x20
107 #define UART_OMAP_MDR3_DIR_POL BIT(3)
108 #define UART_OMAP_MDR3_DIR_EN BIT(4)
109
110 /* Enhanced features register 2 */
111 #define UART_OMAP_EFR2 0x23
112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
113
114 /* RX FIFO occupancy indicator */
115 #define UART_OMAP_RX_LVL 0x19
116
117 struct omap8250_priv {
118 void __iomem *membase;
119 int line;
120 u8 habit;
121 u8 mdr1;
122 u8 mdr3;
123 u8 efr;
124 u8 scr;
125 u8 wer;
126 u8 xon;
127 u8 xoff;
128 u8 delayed_restore;
129 u16 quot;
130
131 u8 tx_trigger;
132 u8 rx_trigger;
133 bool is_suspending;
134 int wakeirq;
135 int wakeups_enabled;
136 u32 latency;
137 u32 calc_latency;
138 struct pm_qos_request pm_qos_request;
139 struct work_struct qos_work;
140 struct uart_8250_dma omap8250_dma;
141 spinlock_t rx_dma_lock;
142 bool rx_dma_broken;
143 bool throttled;
144 };
145
146 struct omap8250_dma_params {
147 u32 rx_size;
148 u8 rx_trigger;
149 u8 tx_trigger;
150 };
151
152 struct omap8250_platdata {
153 struct omap8250_dma_params *dma_params;
154 u8 habit;
155 };
156
157 #ifdef CONFIG_SERIAL_8250_DMA
158 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
159 #else
omap_8250_rx_dma_flush(struct uart_8250_port * p)160 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
161 #endif
162
uart_read(struct omap8250_priv * priv,u32 reg)163 static u32 uart_read(struct omap8250_priv *priv, u32 reg)
164 {
165 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
166 }
167
168 /* Timeout low and High */
169 #define UART_OMAP_TO_L 0x26
170 #define UART_OMAP_TO_H 0x27
171
172 /*
173 * Called on runtime PM resume path from omap8250_restore_regs(), and
174 * omap8250_set_mctrl().
175 */
__omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)176 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
177 {
178 struct uart_8250_port *up = up_to_u8250p(port);
179 struct omap8250_priv *priv = up->port.private_data;
180 u8 lcr;
181
182 serial8250_do_set_mctrl(port, mctrl);
183
184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
185 /*
186 * Turn off autoRTS if RTS is lowered and restore autoRTS
187 * setting if RTS is raised
188 */
189 lcr = serial_in(up, UART_LCR);
190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
191 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
192 priv->efr |= UART_EFR_RTS;
193 else
194 priv->efr &= ~UART_EFR_RTS;
195 serial_out(up, UART_EFR, priv->efr);
196 serial_out(up, UART_LCR, lcr);
197 }
198 }
199
omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)200 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
201 {
202 int err;
203
204 err = pm_runtime_resume_and_get(port->dev);
205 if (err)
206 return;
207
208 __omap8250_set_mctrl(port, mctrl);
209
210 pm_runtime_mark_last_busy(port->dev);
211 pm_runtime_put_autosuspend(port->dev);
212 }
213
214 /*
215 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
216 * The access to uart register after MDR1 Access
217 * causes UART to corrupt data.
218 *
219 * Need a delay =
220 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
221 * give 10 times as much
222 */
omap_8250_mdr1_errataset(struct uart_8250_port * up,struct omap8250_priv * priv)223 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
224 struct omap8250_priv *priv)
225 {
226 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
227 udelay(2);
228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
229 UART_FCR_CLEAR_RCVR);
230 }
231
omap_8250_get_divisor(struct uart_port * port,unsigned int baud,struct omap8250_priv * priv)232 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
233 struct omap8250_priv *priv)
234 {
235 unsigned int uartclk = port->uartclk;
236 unsigned int div_13, div_16;
237 unsigned int abs_d13, abs_d16;
238
239 /*
240 * Old custom speed handling.
241 */
242 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
243 priv->quot = port->custom_divisor & UART_DIV_MAX;
244 /*
245 * I assume that nobody is using this. But hey, if somebody
246 * would like to specify the divisor _and_ the mode then the
247 * driver is ready and waiting for it.
248 */
249 if (port->custom_divisor & (1 << 16))
250 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
251 else
252 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
253 return;
254 }
255 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
256 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
257
258 if (!div_13)
259 div_13 = 1;
260 if (!div_16)
261 div_16 = 1;
262
263 abs_d13 = abs(baud - uartclk / 13 / div_13);
264 abs_d16 = abs(baud - uartclk / 16 / div_16);
265
266 if (abs_d13 >= abs_d16) {
267 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
268 priv->quot = div_16;
269 } else {
270 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
271 priv->quot = div_13;
272 }
273 }
274
omap8250_update_scr(struct uart_8250_port * up,struct omap8250_priv * priv)275 static void omap8250_update_scr(struct uart_8250_port *up,
276 struct omap8250_priv *priv)
277 {
278 u8 old_scr;
279
280 old_scr = serial_in(up, UART_OMAP_SCR);
281 if (old_scr == priv->scr)
282 return;
283
284 /*
285 * The manual recommends not to enable the DMA mode selector in the SCR
286 * (instead of the FCR) register _and_ selecting the DMA mode as one
287 * register write because this may lead to malfunction.
288 */
289 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
290 serial_out(up, UART_OMAP_SCR,
291 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
292 serial_out(up, UART_OMAP_SCR, priv->scr);
293 }
294
omap8250_update_mdr1(struct uart_8250_port * up,struct omap8250_priv * priv)295 static void omap8250_update_mdr1(struct uart_8250_port *up,
296 struct omap8250_priv *priv)
297 {
298 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
299 omap_8250_mdr1_errataset(up, priv);
300 else
301 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
302 }
303
omap8250_restore_regs(struct uart_8250_port * up)304 static void omap8250_restore_regs(struct uart_8250_port *up)
305 {
306 struct omap8250_priv *priv = up->port.private_data;
307 struct uart_8250_dma *dma = up->dma;
308 u8 mcr = serial8250_in_MCR(up);
309
310 /* Port locked to synchronize UART_IER access against the console. */
311 lockdep_assert_held_once(&up->port.lock);
312
313 if (dma && dma->tx_running) {
314 /*
315 * TCSANOW requests the change to occur immediately however if
316 * we have a TX-DMA operation in progress then it has been
317 * observed that it might stall and never complete. Therefore we
318 * delay DMA completes to prevent this hang from happen.
319 */
320 priv->delayed_restore = 1;
321 return;
322 }
323
324 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
325 serial_out(up, UART_EFR, UART_EFR_ECB);
326
327 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
328 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
329 serial_out(up, UART_FCR, up->fcr);
330
331 omap8250_update_scr(up, priv);
332
333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
334
335 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
336 OMAP_UART_TCR_HALT(52));
337 serial_out(up, UART_TI752_TLR,
338 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
339 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
340
341 serial_out(up, UART_LCR, 0);
342
343 /* drop TCR + TLR access, we setup XON/XOFF later */
344 serial8250_out_MCR(up, mcr);
345
346 serial_out(up, UART_IER, up->ier);
347
348 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
349 serial_dl_write(up, priv->quot);
350
351 serial_out(up, UART_EFR, priv->efr);
352
353 /* Configure flow control */
354 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
355 serial_out(up, UART_XON1, priv->xon);
356 serial_out(up, UART_XOFF1, priv->xoff);
357
358 serial_out(up, UART_LCR, up->lcr);
359
360 omap8250_update_mdr1(up, priv);
361
362 __omap8250_set_mctrl(&up->port, up->port.mctrl);
363
364 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
365
366 if (up->port.rs485.flags & SER_RS485_ENABLED &&
367 up->port.rs485_config == serial8250_em485_config)
368 serial8250_em485_stop_tx(up);
369 }
370
371 /*
372 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
373 * some differences in how we want to handle flow control.
374 */
omap_8250_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)375 static void omap_8250_set_termios(struct uart_port *port,
376 struct ktermios *termios,
377 const struct ktermios *old)
378 {
379 struct uart_8250_port *up = up_to_u8250p(port);
380 struct omap8250_priv *priv = up->port.private_data;
381 unsigned char cval = 0;
382 unsigned int baud;
383
384 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
385
386 if (termios->c_cflag & CSTOPB)
387 cval |= UART_LCR_STOP;
388 if (termios->c_cflag & PARENB)
389 cval |= UART_LCR_PARITY;
390 if (!(termios->c_cflag & PARODD))
391 cval |= UART_LCR_EPAR;
392 if (termios->c_cflag & CMSPAR)
393 cval |= UART_LCR_SPAR;
394
395 /*
396 * Ask the core to calculate the divisor for us.
397 */
398 baud = uart_get_baud_rate(port, termios, old,
399 port->uartclk / 16 / UART_DIV_MAX,
400 port->uartclk / 13);
401 omap_8250_get_divisor(port, baud, priv);
402
403 /*
404 * Ok, we're now changing the port state. Do it with
405 * interrupts disabled.
406 */
407 pm_runtime_get_sync(port->dev);
408 spin_lock_irq(&port->lock);
409
410 /*
411 * Update the per-port timeout.
412 */
413 uart_update_timeout(port, termios->c_cflag, baud);
414
415 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
416 if (termios->c_iflag & INPCK)
417 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
418 if (termios->c_iflag & (IGNBRK | PARMRK))
419 up->port.read_status_mask |= UART_LSR_BI;
420
421 /*
422 * Characters to ignore
423 */
424 up->port.ignore_status_mask = 0;
425 if (termios->c_iflag & IGNPAR)
426 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
427 if (termios->c_iflag & IGNBRK) {
428 up->port.ignore_status_mask |= UART_LSR_BI;
429 /*
430 * If we're ignoring parity and break indicators,
431 * ignore overruns too (for real raw support).
432 */
433 if (termios->c_iflag & IGNPAR)
434 up->port.ignore_status_mask |= UART_LSR_OE;
435 }
436
437 /*
438 * ignore all characters if CREAD is not set
439 */
440 if ((termios->c_cflag & CREAD) == 0)
441 up->port.ignore_status_mask |= UART_LSR_DR;
442
443 /*
444 * Modem status interrupts
445 */
446 up->ier &= ~UART_IER_MSI;
447 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
448 up->ier |= UART_IER_MSI;
449
450 up->lcr = cval;
451 /* Up to here it was mostly serial8250_do_set_termios() */
452
453 /*
454 * We enable TRIG_GRANU for RX and TX and additionally we set
455 * SCR_TX_EMPTY bit. The result is the following:
456 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
457 * - less than RX_TRIGGER number of bytes will also cause an interrupt
458 * once the UART decides that there no new bytes arriving.
459 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
460 * empty - the trigger level is ignored here.
461 *
462 * Once DMA is enabled:
463 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
464 * bytes in the TX FIFO. On each assert the DMA engine will move
465 * TX_TRIGGER bytes into the FIFO.
466 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
467 * the FIFO and move RX_TRIGGER bytes.
468 * This is because threshold and trigger values are the same.
469 */
470 up->fcr = UART_FCR_ENABLE_FIFO;
471 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
472 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
473
474 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
475 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
476
477 if (up->dma)
478 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
479 OMAP_UART_SCR_DMAMODE_CTL;
480
481 priv->xon = termios->c_cc[VSTART];
482 priv->xoff = termios->c_cc[VSTOP];
483
484 priv->efr = 0;
485 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
486
487 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
488 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
489 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
490 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
491 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
492 priv->efr |= UART_EFR_CTS;
493 } else if (up->port.flags & UPF_SOFT_FLOW) {
494 /*
495 * OMAP rx s/w flow control is borked; the transmitter remains
496 * stuck off even if rx flow control is subsequently disabled
497 */
498
499 /*
500 * IXOFF Flag:
501 * Enable XON/XOFF flow control on output.
502 * Transmit XON1, XOFF1
503 */
504 if (termios->c_iflag & IXOFF) {
505 up->port.status |= UPSTAT_AUTOXOFF;
506 priv->efr |= OMAP_UART_SW_TX;
507 }
508 }
509 omap8250_restore_regs(up);
510
511 spin_unlock_irq(&up->port.lock);
512 pm_runtime_mark_last_busy(port->dev);
513 pm_runtime_put_autosuspend(port->dev);
514
515 /* calculate wakeup latency constraint */
516 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
517 priv->latency = priv->calc_latency;
518
519 schedule_work(&priv->qos_work);
520
521 /* Don't rewrite B0 */
522 if (tty_termios_baud_rate(termios))
523 tty_termios_encode_baud_rate(termios, baud, baud);
524 }
525
526 /* same as 8250 except that we may have extra flow bits set in EFR */
omap_8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)527 static void omap_8250_pm(struct uart_port *port, unsigned int state,
528 unsigned int oldstate)
529 {
530 struct uart_8250_port *up = up_to_u8250p(port);
531 u8 efr;
532
533 pm_runtime_get_sync(port->dev);
534
535 /* Synchronize UART_IER access against the console. */
536 spin_lock_irq(&port->lock);
537
538 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
539 efr = serial_in(up, UART_EFR);
540 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
541 serial_out(up, UART_LCR, 0);
542
543 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
544 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
545 serial_out(up, UART_EFR, efr);
546 serial_out(up, UART_LCR, 0);
547
548 spin_unlock_irq(&port->lock);
549
550 pm_runtime_mark_last_busy(port->dev);
551 pm_runtime_put_autosuspend(port->dev);
552 }
553
omap_serial_fill_features_erratas(struct uart_8250_port * up,struct omap8250_priv * priv)554 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
555 struct omap8250_priv *priv)
556 {
557 static const struct soc_device_attribute k3_soc_devices[] = {
558 { .family = "AM65X", },
559 { .family = "J721E", .revision = "SR1.0" },
560 { /* sentinel */ }
561 };
562 u32 mvr, scheme;
563 u16 revision, major, minor;
564
565 mvr = uart_read(priv, UART_OMAP_MVER);
566
567 /* Check revision register scheme */
568 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
569
570 switch (scheme) {
571 case 0: /* Legacy Scheme: OMAP2/3 */
572 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
573 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
574 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
575 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
576 break;
577 case 1:
578 /* New Scheme: OMAP4+ */
579 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
580 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
581 OMAP_UART_MVR_MAJ_SHIFT;
582 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
583 break;
584 default:
585 dev_warn(up->port.dev,
586 "Unknown revision, defaulting to highest\n");
587 /* highest possible revision */
588 major = 0xff;
589 minor = 0xff;
590 }
591 /* normalize revision for the driver */
592 revision = UART_BUILD_REVISION(major, minor);
593
594 switch (revision) {
595 case OMAP_UART_REV_46:
596 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
597 break;
598 case OMAP_UART_REV_52:
599 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
600 OMAP_UART_WER_HAS_TX_WAKEUP;
601 break;
602 case OMAP_UART_REV_63:
603 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
604 OMAP_UART_WER_HAS_TX_WAKEUP;
605 break;
606 default:
607 break;
608 }
609
610 /*
611 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
612 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
613 * to enable errata workaround.
614 */
615 if (soc_device_match(k3_soc_devices))
616 priv->habit &= ~UART_HAS_RHR_IT_DIS;
617 }
618
omap8250_uart_qos_work(struct work_struct * work)619 static void omap8250_uart_qos_work(struct work_struct *work)
620 {
621 struct omap8250_priv *priv;
622
623 priv = container_of(work, struct omap8250_priv, qos_work);
624 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
625 }
626
627 #ifdef CONFIG_SERIAL_8250_DMA
628 static int omap_8250_dma_handle_irq(struct uart_port *port);
629 #endif
630
omap8250_irq(int irq,void * dev_id)631 static irqreturn_t omap8250_irq(int irq, void *dev_id)
632 {
633 struct omap8250_priv *priv = dev_id;
634 struct uart_8250_port *up = serial8250_get_port(priv->line);
635 struct uart_port *port = &up->port;
636 unsigned int iir, lsr;
637 int ret;
638
639 #ifdef CONFIG_SERIAL_8250_DMA
640 if (up->dma) {
641 ret = omap_8250_dma_handle_irq(port);
642 return IRQ_RETVAL(ret);
643 }
644 #endif
645
646 serial8250_rpm_get(up);
647 lsr = serial_port_in(port, UART_LSR);
648 iir = serial_port_in(port, UART_IIR);
649 ret = serial8250_handle_irq(port, iir);
650
651 /*
652 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
653 * FIFO has been drained or erroneously.
654 * So apply solution of Errata i2310 as mentioned in
655 * https://www.ti.com/lit/pdf/sprz536
656 */
657 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
658 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
659 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
660 unsigned char efr2, timeout_h, timeout_l;
661
662 efr2 = serial_in(up, UART_OMAP_EFR2);
663 timeout_h = serial_in(up, UART_OMAP_TO_H);
664 timeout_l = serial_in(up, UART_OMAP_TO_L);
665 serial_out(up, UART_OMAP_TO_H, 0xFF);
666 serial_out(up, UART_OMAP_TO_L, 0xFF);
667 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
668 serial_in(up, UART_IIR);
669 serial_out(up, UART_OMAP_EFR2, efr2);
670 serial_out(up, UART_OMAP_TO_H, timeout_h);
671 serial_out(up, UART_OMAP_TO_L, timeout_l);
672 }
673
674 /* Stop processing interrupts on input overrun */
675 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
676 unsigned long delay;
677
678 /* Synchronize UART_IER access against the console. */
679 spin_lock(&port->lock);
680 up->ier = port->serial_in(port, UART_IER);
681 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
682 port->ops->stop_rx(port);
683 } else {
684 /* Keep restarting the timer until
685 * the input overrun subsides.
686 */
687 cancel_delayed_work(&up->overrun_backoff);
688 }
689 spin_unlock(&port->lock);
690
691 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
692 schedule_delayed_work(&up->overrun_backoff, delay);
693 }
694
695 serial8250_rpm_put(up);
696
697 return IRQ_RETVAL(ret);
698 }
699
omap_8250_startup(struct uart_port * port)700 static int omap_8250_startup(struct uart_port *port)
701 {
702 struct uart_8250_port *up = up_to_u8250p(port);
703 struct omap8250_priv *priv = port->private_data;
704 struct uart_8250_dma *dma = &priv->omap8250_dma;
705 int ret;
706
707 if (priv->wakeirq) {
708 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
709 if (ret)
710 return ret;
711 }
712
713 pm_runtime_get_sync(port->dev);
714
715 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
716
717 serial_out(up, UART_LCR, UART_LCR_WLEN8);
718
719 up->lsr_saved_flags = 0;
720 up->msr_saved_flags = 0;
721
722 /* Disable DMA for console UART */
723 if (dma->fn && !uart_console(port)) {
724 up->dma = &priv->omap8250_dma;
725 ret = serial8250_request_dma(up);
726 if (ret) {
727 dev_warn_ratelimited(port->dev,
728 "failed to request DMA\n");
729 up->dma = NULL;
730 }
731 } else {
732 up->dma = NULL;
733 }
734
735 /* Synchronize UART_IER access against the console. */
736 spin_lock_irq(&port->lock);
737 up->ier = UART_IER_RLSI | UART_IER_RDI;
738 serial_out(up, UART_IER, up->ier);
739 spin_unlock_irq(&port->lock);
740
741 #ifdef CONFIG_PM
742 up->capabilities |= UART_CAP_RPM;
743 #endif
744
745 /* Enable module level wake up */
746 priv->wer = OMAP_UART_WER_MOD_WKUP;
747 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
748 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
749 serial_out(up, UART_OMAP_WER, priv->wer);
750
751 if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
752 spin_lock_irq(&port->lock);
753 up->dma->rx_dma(up);
754 spin_unlock_irq(&port->lock);
755 }
756
757 enable_irq(up->port.irq);
758
759 pm_runtime_mark_last_busy(port->dev);
760 pm_runtime_put_autosuspend(port->dev);
761 return 0;
762 }
763
omap_8250_shutdown(struct uart_port * port)764 static void omap_8250_shutdown(struct uart_port *port)
765 {
766 struct uart_8250_port *up = up_to_u8250p(port);
767 struct omap8250_priv *priv = port->private_data;
768
769 flush_work(&priv->qos_work);
770 if (up->dma)
771 omap_8250_rx_dma_flush(up);
772
773 pm_runtime_get_sync(port->dev);
774
775 serial_out(up, UART_OMAP_WER, 0);
776 if (priv->habit & UART_HAS_EFR2)
777 serial_out(up, UART_OMAP_EFR2, 0x0);
778
779 /* Synchronize UART_IER access against the console. */
780 spin_lock_irq(&port->lock);
781 up->ier = 0;
782 serial_out(up, UART_IER, 0);
783 spin_unlock_irq(&port->lock);
784 disable_irq_nosync(up->port.irq);
785 dev_pm_clear_wake_irq(port->dev);
786
787 serial8250_release_dma(up);
788 up->dma = NULL;
789
790 /*
791 * Disable break condition and FIFOs
792 */
793 if (up->lcr & UART_LCR_SBC)
794 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
795 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
796
797 pm_runtime_mark_last_busy(port->dev);
798 pm_runtime_put_autosuspend(port->dev);
799 }
800
omap_8250_throttle(struct uart_port * port)801 static void omap_8250_throttle(struct uart_port *port)
802 {
803 struct omap8250_priv *priv = port->private_data;
804 unsigned long flags;
805
806 pm_runtime_get_sync(port->dev);
807
808 spin_lock_irqsave(&port->lock, flags);
809 port->ops->stop_rx(port);
810 priv->throttled = true;
811 spin_unlock_irqrestore(&port->lock, flags);
812
813 pm_runtime_mark_last_busy(port->dev);
814 pm_runtime_put_autosuspend(port->dev);
815 }
816
omap_8250_unthrottle(struct uart_port * port)817 static void omap_8250_unthrottle(struct uart_port *port)
818 {
819 struct omap8250_priv *priv = port->private_data;
820 struct uart_8250_port *up = up_to_u8250p(port);
821 unsigned long flags;
822
823 pm_runtime_get_sync(port->dev);
824
825 /* Synchronize UART_IER access against the console. */
826 spin_lock_irqsave(&port->lock, flags);
827 priv->throttled = false;
828 if (up->dma)
829 up->dma->rx_dma(up);
830 up->ier |= UART_IER_RLSI | UART_IER_RDI;
831 port->read_status_mask |= UART_LSR_DR;
832 serial_out(up, UART_IER, up->ier);
833 spin_unlock_irqrestore(&port->lock, flags);
834
835 pm_runtime_mark_last_busy(port->dev);
836 pm_runtime_put_autosuspend(port->dev);
837 }
838
omap8250_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)839 static int omap8250_rs485_config(struct uart_port *port,
840 struct ktermios *termios,
841 struct serial_rs485 *rs485)
842 {
843 struct omap8250_priv *priv = port->private_data;
844 struct uart_8250_port *up = up_to_u8250p(port);
845 u32 fixed_delay_rts_before_send = 0;
846 u32 fixed_delay_rts_after_send = 0;
847 unsigned int baud;
848
849 /*
850 * There is a fixed delay of 3 bit clock cycles after the TX shift
851 * register is going empty to allow time for the stop bit to transition
852 * through the transceiver before direction is changed to receive.
853 *
854 * Additionally there appears to be a 1 bit clock delay between writing
855 * to the THR register and transmission of the start bit, per page 8783
856 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
857 */
858 if (priv->quot) {
859 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
860 baud = port->uartclk / (16 * priv->quot);
861 else
862 baud = port->uartclk / (13 * priv->quot);
863
864 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud;
865 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
866 }
867
868 /*
869 * Fall back to RS485 software emulation if the UART is missing
870 * hardware support, if the device tree specifies an mctrl_gpio
871 * (indicates that RTS is unavailable due to a pinmux conflict)
872 * or if the requested delays exceed the fixed hardware delays.
873 */
874 if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
875 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
876 rs485->delay_rts_after_send > fixed_delay_rts_after_send ||
877 rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
878 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
879 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
880
881 port->rs485_config = serial8250_em485_config;
882 return serial8250_em485_config(port, termios, rs485);
883 }
884
885 rs485->delay_rts_after_send = fixed_delay_rts_after_send;
886 rs485->delay_rts_before_send = fixed_delay_rts_before_send;
887
888 if (rs485->flags & SER_RS485_ENABLED)
889 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
890 else
891 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
892
893 /*
894 * Retain same polarity semantics as RS485 software emulation,
895 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send.
896 */
897 if (rs485->flags & SER_RS485_RTS_ON_SEND)
898 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
899 else
900 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
901
902 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
903
904 return 0;
905 }
906
907 #ifdef CONFIG_SERIAL_8250_DMA
908 static int omap_8250_rx_dma(struct uart_8250_port *p);
909
910 /* Must be called while priv->rx_dma_lock is held */
__dma_rx_do_complete(struct uart_8250_port * p)911 static void __dma_rx_do_complete(struct uart_8250_port *p)
912 {
913 struct uart_8250_dma *dma = p->dma;
914 struct tty_port *tty_port = &p->port.state->port;
915 struct omap8250_priv *priv = p->port.private_data;
916 struct dma_chan *rxchan = dma->rxchan;
917 dma_cookie_t cookie;
918 struct dma_tx_state state;
919 int count;
920 int ret;
921 u32 reg;
922
923 if (!dma->rx_running)
924 goto out;
925
926 cookie = dma->rx_cookie;
927 dma->rx_running = 0;
928
929 /* Re-enable RX FIFO interrupt now that transfer is complete */
930 if (priv->habit & UART_HAS_RHR_IT_DIS) {
931 reg = serial_in(p, UART_OMAP_IER2);
932 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
933 serial_out(p, UART_OMAP_IER2, reg);
934 }
935
936 dmaengine_tx_status(rxchan, cookie, &state);
937
938 count = dma->rx_size - state.residue + state.in_flight_bytes;
939 if (count < dma->rx_size) {
940 dmaengine_terminate_async(rxchan);
941
942 /*
943 * Poll for teardown to complete which guarantees in
944 * flight data is drained.
945 */
946 if (state.in_flight_bytes) {
947 int poll_count = 25;
948
949 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
950 poll_count--)
951 cpu_relax();
952
953 if (poll_count == -1)
954 dev_err(p->port.dev, "teardown incomplete\n");
955 }
956 }
957 if (!count)
958 goto out;
959 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
960
961 p->port.icount.rx += ret;
962 p->port.icount.buf_overrun += count - ret;
963 out:
964
965 tty_flip_buffer_push(tty_port);
966 }
967
__dma_rx_complete(void * param)968 static void __dma_rx_complete(void *param)
969 {
970 struct uart_8250_port *p = param;
971 struct omap8250_priv *priv = p->port.private_data;
972 struct uart_8250_dma *dma = p->dma;
973 struct dma_tx_state state;
974 unsigned long flags;
975
976 /* Synchronize UART_IER access against the console. */
977 spin_lock_irqsave(&p->port.lock, flags);
978
979 /*
980 * If the tx status is not DMA_COMPLETE, then this is a delayed
981 * completion callback. A previous RX timeout flush would have
982 * already pushed the data, so exit.
983 */
984 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
985 DMA_COMPLETE) {
986 spin_unlock_irqrestore(&p->port.lock, flags);
987 return;
988 }
989 __dma_rx_do_complete(p);
990 if (!priv->throttled) {
991 p->ier |= UART_IER_RLSI | UART_IER_RDI;
992 serial_out(p, UART_IER, p->ier);
993 if (!(priv->habit & UART_HAS_EFR2))
994 omap_8250_rx_dma(p);
995 }
996
997 spin_unlock_irqrestore(&p->port.lock, flags);
998 }
999
omap_8250_rx_dma_flush(struct uart_8250_port * p)1000 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
1001 {
1002 struct omap8250_priv *priv = p->port.private_data;
1003 struct uart_8250_dma *dma = p->dma;
1004 struct dma_tx_state state;
1005 unsigned long flags;
1006 int ret;
1007
1008 spin_lock_irqsave(&priv->rx_dma_lock, flags);
1009
1010 if (!dma->rx_running) {
1011 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1012 return;
1013 }
1014
1015 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
1016 if (ret == DMA_IN_PROGRESS) {
1017 ret = dmaengine_pause(dma->rxchan);
1018 if (WARN_ON_ONCE(ret))
1019 priv->rx_dma_broken = true;
1020 }
1021 __dma_rx_do_complete(p);
1022 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1023 }
1024
omap_8250_rx_dma(struct uart_8250_port * p)1025 static int omap_8250_rx_dma(struct uart_8250_port *p)
1026 {
1027 struct omap8250_priv *priv = p->port.private_data;
1028 struct uart_8250_dma *dma = p->dma;
1029 int err = 0;
1030 struct dma_async_tx_descriptor *desc;
1031 unsigned long flags;
1032 u32 reg;
1033
1034 /* Port locked to synchronize UART_IER access against the console. */
1035 lockdep_assert_held_once(&p->port.lock);
1036
1037 if (priv->rx_dma_broken)
1038 return -EINVAL;
1039
1040 spin_lock_irqsave(&priv->rx_dma_lock, flags);
1041
1042 if (dma->rx_running) {
1043 enum dma_status state;
1044
1045 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
1046 if (state == DMA_COMPLETE) {
1047 /*
1048 * Disable RX interrupts to allow RX DMA completion
1049 * callback to run.
1050 */
1051 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1052 serial_out(p, UART_IER, p->ier);
1053 }
1054 goto out;
1055 }
1056
1057 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
1058 dma->rx_size, DMA_DEV_TO_MEM,
1059 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1060 if (!desc) {
1061 err = -EBUSY;
1062 goto out;
1063 }
1064
1065 dma->rx_running = 1;
1066 desc->callback = __dma_rx_complete;
1067 desc->callback_param = p;
1068
1069 dma->rx_cookie = dmaengine_submit(desc);
1070
1071 /*
1072 * Disable RX FIFO interrupt while RX DMA is enabled, else
1073 * spurious interrupt may be raised when data is in the RX FIFO
1074 * but is yet to be drained by DMA.
1075 */
1076 if (priv->habit & UART_HAS_RHR_IT_DIS) {
1077 reg = serial_in(p, UART_OMAP_IER2);
1078 reg |= UART_OMAP_IER2_RHR_IT_DIS;
1079 serial_out(p, UART_OMAP_IER2, reg);
1080 }
1081
1082 dma_async_issue_pending(dma->rxchan);
1083 out:
1084 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1085 return err;
1086 }
1087
1088 static int omap_8250_tx_dma(struct uart_8250_port *p);
1089
omap_8250_dma_tx_complete(void * param)1090 static void omap_8250_dma_tx_complete(void *param)
1091 {
1092 struct uart_8250_port *p = param;
1093 struct uart_8250_dma *dma = p->dma;
1094 struct circ_buf *xmit = &p->port.state->xmit;
1095 unsigned long flags;
1096 bool en_thri = false;
1097 struct omap8250_priv *priv = p->port.private_data;
1098
1099 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1100 UART_XMIT_SIZE, DMA_TO_DEVICE);
1101
1102 spin_lock_irqsave(&p->port.lock, flags);
1103
1104 dma->tx_running = 0;
1105
1106 uart_xmit_advance(&p->port, dma->tx_size);
1107
1108 if (priv->delayed_restore) {
1109 priv->delayed_restore = 0;
1110 omap8250_restore_regs(p);
1111 }
1112
1113 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1114 uart_write_wakeup(&p->port);
1115
1116 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1117 int ret;
1118
1119 ret = omap_8250_tx_dma(p);
1120 if (ret)
1121 en_thri = true;
1122 } else if (p->capabilities & UART_CAP_RPM) {
1123 en_thri = true;
1124 }
1125
1126 if (en_thri) {
1127 dma->tx_err = 1;
1128 serial8250_set_THRI(p);
1129 }
1130
1131 spin_unlock_irqrestore(&p->port.lock, flags);
1132 }
1133
omap_8250_tx_dma(struct uart_8250_port * p)1134 static int omap_8250_tx_dma(struct uart_8250_port *p)
1135 {
1136 struct uart_8250_dma *dma = p->dma;
1137 struct omap8250_priv *priv = p->port.private_data;
1138 struct circ_buf *xmit = &p->port.state->xmit;
1139 struct dma_async_tx_descriptor *desc;
1140 unsigned int skip_byte = 0;
1141 int ret;
1142
1143 if (dma->tx_running)
1144 return 0;
1145 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1146
1147 /*
1148 * Even if no data, we need to return an error for the two cases
1149 * below so serial8250_tx_chars() is invoked and properly clears
1150 * THRI and/or runtime suspend.
1151 */
1152 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1153 ret = -EBUSY;
1154 goto err;
1155 }
1156 serial8250_clear_THRI(p);
1157 return 0;
1158 }
1159
1160 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1161 if (priv->habit & OMAP_DMA_TX_KICK) {
1162 u8 tx_lvl;
1163
1164 /*
1165 * We need to put the first byte into the FIFO in order to start
1166 * the DMA transfer. For transfers smaller than four bytes we
1167 * don't bother doing DMA at all. It seem not matter if there
1168 * are still bytes in the FIFO from the last transfer (in case
1169 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1170 * leaving the FIFO seem not to trigger the DMA transfer. It is
1171 * really the byte that we put into the FIFO.
1172 * If the FIFO is already full then we most likely got here from
1173 * omap_8250_dma_tx_complete(). And this means the DMA engine
1174 * just completed its work. We don't have to wait the complete
1175 * 86us at 115200,8n1 but around 60us (not to mention lower
1176 * baudrates). So in that case we take the interrupt and try
1177 * again with an empty FIFO.
1178 */
1179 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1180 if (tx_lvl == p->tx_loadsz) {
1181 ret = -EBUSY;
1182 goto err;
1183 }
1184 if (dma->tx_size < 4) {
1185 ret = -EINVAL;
1186 goto err;
1187 }
1188 skip_byte = 1;
1189 }
1190
1191 desc = dmaengine_prep_slave_single(dma->txchan,
1192 dma->tx_addr + xmit->tail + skip_byte,
1193 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1194 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1195 if (!desc) {
1196 ret = -EBUSY;
1197 goto err;
1198 }
1199
1200 dma->tx_running = 1;
1201
1202 desc->callback = omap_8250_dma_tx_complete;
1203 desc->callback_param = p;
1204
1205 dma->tx_cookie = dmaengine_submit(desc);
1206
1207 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1208 UART_XMIT_SIZE, DMA_TO_DEVICE);
1209
1210 dma_async_issue_pending(dma->txchan);
1211 if (dma->tx_err)
1212 dma->tx_err = 0;
1213
1214 serial8250_clear_THRI(p);
1215 if (skip_byte)
1216 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1217 return 0;
1218 err:
1219 dma->tx_err = 1;
1220 return ret;
1221 }
1222
handle_rx_dma(struct uart_8250_port * up,unsigned int iir)1223 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1224 {
1225 switch (iir & 0x3f) {
1226 case UART_IIR_RLSI:
1227 case UART_IIR_RX_TIMEOUT:
1228 case UART_IIR_RDI:
1229 omap_8250_rx_dma_flush(up);
1230 return true;
1231 }
1232 return omap_8250_rx_dma(up);
1233 }
1234
omap_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,u16 status)1235 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1236 {
1237 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1238 (iir & UART_IIR_RDI)) {
1239 if (handle_rx_dma(up, iir)) {
1240 status = serial8250_rx_chars(up, status);
1241 omap_8250_rx_dma(up);
1242 }
1243 }
1244
1245 return status;
1246 }
1247
am654_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,u16 status)1248 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1249 u16 status)
1250 {
1251 /* Port locked to synchronize UART_IER access against the console. */
1252 lockdep_assert_held_once(&up->port.lock);
1253
1254 /*
1255 * Queue a new transfer if FIFO has data.
1256 */
1257 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1258 (up->ier & UART_IER_RDI)) {
1259 omap_8250_rx_dma(up);
1260 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1261 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1262 /*
1263 * Disable RX timeout, read IIR to clear
1264 * current timeout condition, clear EFR2 to
1265 * periodic timeouts, re-enable interrupts.
1266 */
1267 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1268 serial_out(up, UART_IER, up->ier);
1269 omap_8250_rx_dma_flush(up);
1270 serial_in(up, UART_IIR);
1271 serial_out(up, UART_OMAP_EFR2, 0x0);
1272 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1273 serial_out(up, UART_IER, up->ier);
1274 }
1275 }
1276
1277 /*
1278 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1279 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1280 * use the default routine in the non-DMA case and this one for with DMA.
1281 */
omap_8250_dma_handle_irq(struct uart_port * port)1282 static int omap_8250_dma_handle_irq(struct uart_port *port)
1283 {
1284 struct uart_8250_port *up = up_to_u8250p(port);
1285 struct omap8250_priv *priv = up->port.private_data;
1286 u16 status;
1287 u8 iir;
1288
1289 serial8250_rpm_get(up);
1290
1291 iir = serial_port_in(port, UART_IIR);
1292 if (iir & UART_IIR_NO_INT) {
1293 serial8250_rpm_put(up);
1294 return IRQ_HANDLED;
1295 }
1296
1297 spin_lock(&port->lock);
1298
1299 status = serial_port_in(port, UART_LSR);
1300
1301 if ((iir & 0x3f) != UART_IIR_THRI) {
1302 if (priv->habit & UART_HAS_EFR2)
1303 am654_8250_handle_rx_dma(up, iir, status);
1304 else
1305 status = omap_8250_handle_rx_dma(up, iir, status);
1306 }
1307
1308 serial8250_modem_status(up);
1309 if (status & UART_LSR_THRE && up->dma->tx_err) {
1310 if (uart_tx_stopped(&up->port) ||
1311 uart_circ_empty(&up->port.state->xmit)) {
1312 up->dma->tx_err = 0;
1313 serial8250_tx_chars(up);
1314 } else {
1315 /*
1316 * try again due to an earlier failer which
1317 * might have been resolved by now.
1318 */
1319 if (omap_8250_tx_dma(up))
1320 serial8250_tx_chars(up);
1321 }
1322 }
1323
1324 uart_unlock_and_check_sysrq(port);
1325
1326 serial8250_rpm_put(up);
1327 return 1;
1328 }
1329
the_no_dma_filter_fn(struct dma_chan * chan,void * param)1330 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1331 {
1332 return false;
1333 }
1334
1335 #else
1336
omap_8250_rx_dma(struct uart_8250_port * p)1337 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1338 {
1339 return -EINVAL;
1340 }
1341 #endif
1342
omap8250_no_handle_irq(struct uart_port * port)1343 static int omap8250_no_handle_irq(struct uart_port *port)
1344 {
1345 /* IRQ has not been requested but handling irq? */
1346 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1347 return 0;
1348 }
1349
1350 static struct omap8250_dma_params am654_dma = {
1351 .rx_size = SZ_2K,
1352 .rx_trigger = 1,
1353 .tx_trigger = TX_TRIGGER,
1354 };
1355
1356 static struct omap8250_dma_params am33xx_dma = {
1357 .rx_size = RX_TRIGGER,
1358 .rx_trigger = RX_TRIGGER,
1359 .tx_trigger = TX_TRIGGER,
1360 };
1361
1362 static struct omap8250_platdata am654_platdata = {
1363 .dma_params = &am654_dma,
1364 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1365 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485,
1366 };
1367
1368 static struct omap8250_platdata am33xx_platdata = {
1369 .dma_params = &am33xx_dma,
1370 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1371 };
1372
1373 static struct omap8250_platdata omap4_platdata = {
1374 .dma_params = &am33xx_dma,
1375 .habit = UART_ERRATA_CLOCK_DISABLE,
1376 };
1377
1378 static const struct of_device_id omap8250_dt_ids[] = {
1379 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1380 { .compatible = "ti,omap2-uart" },
1381 { .compatible = "ti,omap3-uart" },
1382 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1383 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1384 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1385 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1386 {},
1387 };
1388 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1389
omap8250_probe(struct platform_device * pdev)1390 static int omap8250_probe(struct platform_device *pdev)
1391 {
1392 struct device_node *np = pdev->dev.of_node;
1393 struct omap8250_priv *priv;
1394 const struct omap8250_platdata *pdata;
1395 struct uart_8250_port up;
1396 struct resource *regs;
1397 void __iomem *membase;
1398 int irq, ret;
1399
1400 irq = platform_get_irq(pdev, 0);
1401 if (irq < 0)
1402 return irq;
1403
1404 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405 if (!regs) {
1406 dev_err(&pdev->dev, "missing registers\n");
1407 return -EINVAL;
1408 }
1409
1410 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1411 if (!priv)
1412 return -ENOMEM;
1413
1414 membase = devm_ioremap(&pdev->dev, regs->start,
1415 resource_size(regs));
1416 if (!membase)
1417 return -ENODEV;
1418
1419 memset(&up, 0, sizeof(up));
1420 up.port.dev = &pdev->dev;
1421 up.port.mapbase = regs->start;
1422 up.port.membase = membase;
1423 up.port.irq = irq;
1424 /*
1425 * It claims to be 16C750 compatible however it is a little different.
1426 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1427 * have) is enabled via EFR instead of MCR. The type is set here 8250
1428 * just to get things going. UNKNOWN does not work for a few reasons and
1429 * we don't need our own type since we don't use 8250's set_termios()
1430 * or pm callback.
1431 */
1432 up.port.type = PORT_8250;
1433 up.port.iotype = UPIO_MEM;
1434 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1435 UPF_HARD_FLOW;
1436 up.port.private_data = priv;
1437
1438 up.port.regshift = OMAP_UART_REGSHIFT;
1439 up.port.fifosize = 64;
1440 up.tx_loadsz = 64;
1441 up.capabilities = UART_CAP_FIFO;
1442 #ifdef CONFIG_PM
1443 /*
1444 * Runtime PM is mostly transparent. However to do it right we need to a
1445 * TX empty interrupt before we can put the device to auto idle. So if
1446 * PM is not enabled we don't add that flag and can spare that one extra
1447 * interrupt in the TX path.
1448 */
1449 up.capabilities |= UART_CAP_RPM;
1450 #endif
1451 up.port.set_termios = omap_8250_set_termios;
1452 up.port.set_mctrl = omap8250_set_mctrl;
1453 up.port.pm = omap_8250_pm;
1454 up.port.startup = omap_8250_startup;
1455 up.port.shutdown = omap_8250_shutdown;
1456 up.port.throttle = omap_8250_throttle;
1457 up.port.unthrottle = omap_8250_unthrottle;
1458 up.port.rs485_config = omap8250_rs485_config;
1459 /* same rs485_supported for software emulation and native RS485 */
1460 up.port.rs485_supported = serial8250_em485_supported;
1461 up.rs485_start_tx = serial8250_em485_start_tx;
1462 up.rs485_stop_tx = serial8250_em485_stop_tx;
1463 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1464
1465 ret = of_alias_get_id(np, "serial");
1466 if (ret < 0) {
1467 dev_err(&pdev->dev, "failed to get alias\n");
1468 return ret;
1469 }
1470 up.port.line = ret;
1471
1472 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1473 struct clk *clk;
1474
1475 clk = devm_clk_get(&pdev->dev, NULL);
1476 if (IS_ERR(clk)) {
1477 if (PTR_ERR(clk) == -EPROBE_DEFER)
1478 return -EPROBE_DEFER;
1479 } else {
1480 up.port.uartclk = clk_get_rate(clk);
1481 }
1482 }
1483
1484 if (of_property_read_u32(np, "overrun-throttle-ms",
1485 &up.overrun_backoff_time_ms) != 0)
1486 up.overrun_backoff_time_ms = 0;
1487
1488 pdata = of_device_get_match_data(&pdev->dev);
1489 if (pdata)
1490 priv->habit |= pdata->habit;
1491
1492 if (!up.port.uartclk) {
1493 up.port.uartclk = DEFAULT_CLK_SPEED;
1494 dev_warn(&pdev->dev,
1495 "No clock speed specified: using default: %d\n",
1496 DEFAULT_CLK_SPEED);
1497 }
1498
1499 priv->membase = membase;
1500 priv->line = -ENODEV;
1501 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1502 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1503 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1504 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1505
1506 spin_lock_init(&priv->rx_dma_lock);
1507
1508 platform_set_drvdata(pdev, priv);
1509
1510 device_init_wakeup(&pdev->dev, true);
1511 pm_runtime_enable(&pdev->dev);
1512 pm_runtime_use_autosuspend(&pdev->dev);
1513
1514 /*
1515 * Disable runtime PM until autosuspend delay unless specifically
1516 * enabled by the user via sysfs. This is the historic way to
1517 * prevent an unsafe default policy with lossy characters on wake-up.
1518 * For serdev devices this is not needed, the policy can be managed by
1519 * the serdev driver.
1520 */
1521 if (!of_get_available_child_count(pdev->dev.of_node))
1522 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1523
1524 pm_runtime_irq_safe(&pdev->dev);
1525
1526 pm_runtime_get_sync(&pdev->dev);
1527
1528 omap_serial_fill_features_erratas(&up, priv);
1529 up.port.handle_irq = omap8250_no_handle_irq;
1530 priv->rx_trigger = RX_TRIGGER;
1531 priv->tx_trigger = TX_TRIGGER;
1532 #ifdef CONFIG_SERIAL_8250_DMA
1533 /*
1534 * Oh DMA support. If there are no DMA properties in the DT then
1535 * we will fall back to a generic DMA channel which does not
1536 * really work here. To ensure that we do not get a generic DMA
1537 * channel assigned, we have the the_no_dma_filter_fn() here.
1538 * To avoid "failed to request DMA" messages we check for DMA
1539 * properties in DT.
1540 */
1541 ret = of_property_count_strings(np, "dma-names");
1542 if (ret == 2) {
1543 struct omap8250_dma_params *dma_params = NULL;
1544 struct uart_8250_dma *dma = &priv->omap8250_dma;
1545
1546 dma->fn = the_no_dma_filter_fn;
1547 dma->tx_dma = omap_8250_tx_dma;
1548 dma->rx_dma = omap_8250_rx_dma;
1549 if (pdata)
1550 dma_params = pdata->dma_params;
1551
1552 if (dma_params) {
1553 dma->rx_size = dma_params->rx_size;
1554 dma->rxconf.src_maxburst = dma_params->rx_trigger;
1555 dma->txconf.dst_maxburst = dma_params->tx_trigger;
1556 priv->rx_trigger = dma_params->rx_trigger;
1557 priv->tx_trigger = dma_params->tx_trigger;
1558 } else {
1559 dma->rx_size = RX_TRIGGER;
1560 dma->rxconf.src_maxburst = RX_TRIGGER;
1561 dma->txconf.dst_maxburst = TX_TRIGGER;
1562 }
1563 }
1564 #endif
1565
1566 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1567 ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0,
1568 dev_name(&pdev->dev), priv);
1569 if (ret < 0)
1570 return ret;
1571
1572 priv->wakeirq = irq_of_parse_and_map(np, 1);
1573
1574 ret = serial8250_register_8250_port(&up);
1575 if (ret < 0) {
1576 dev_err(&pdev->dev, "unable to register 8250 port\n");
1577 goto err;
1578 }
1579 priv->line = ret;
1580 pm_runtime_mark_last_busy(&pdev->dev);
1581 pm_runtime_put_autosuspend(&pdev->dev);
1582 return 0;
1583 err:
1584 pm_runtime_dont_use_autosuspend(&pdev->dev);
1585 pm_runtime_put_sync(&pdev->dev);
1586 flush_work(&priv->qos_work);
1587 pm_runtime_disable(&pdev->dev);
1588 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1589 return ret;
1590 }
1591
omap8250_remove(struct platform_device * pdev)1592 static int omap8250_remove(struct platform_device *pdev)
1593 {
1594 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1595 struct uart_8250_port *up;
1596 int err;
1597
1598 err = pm_runtime_resume_and_get(&pdev->dev);
1599 if (err)
1600 dev_err(&pdev->dev, "Failed to resume hardware\n");
1601
1602 up = serial8250_get_port(priv->line);
1603 omap_8250_shutdown(&up->port);
1604 serial8250_unregister_port(priv->line);
1605 priv->line = -ENODEV;
1606 pm_runtime_dont_use_autosuspend(&pdev->dev);
1607 pm_runtime_put_sync(&pdev->dev);
1608 flush_work(&priv->qos_work);
1609 pm_runtime_disable(&pdev->dev);
1610 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1611 device_init_wakeup(&pdev->dev, false);
1612 return 0;
1613 }
1614
omap8250_prepare(struct device * dev)1615 static int omap8250_prepare(struct device *dev)
1616 {
1617 struct omap8250_priv *priv = dev_get_drvdata(dev);
1618
1619 if (!priv)
1620 return 0;
1621 priv->is_suspending = true;
1622 return 0;
1623 }
1624
omap8250_complete(struct device * dev)1625 static void omap8250_complete(struct device *dev)
1626 {
1627 struct omap8250_priv *priv = dev_get_drvdata(dev);
1628
1629 if (!priv)
1630 return;
1631 priv->is_suspending = false;
1632 }
1633
omap8250_suspend(struct device * dev)1634 static int omap8250_suspend(struct device *dev)
1635 {
1636 struct omap8250_priv *priv = dev_get_drvdata(dev);
1637 struct uart_8250_port *up = serial8250_get_port(priv->line);
1638 int err = 0;
1639
1640 serial8250_suspend_port(priv->line);
1641
1642 err = pm_runtime_resume_and_get(dev);
1643 if (err)
1644 return err;
1645 if (!device_may_wakeup(dev))
1646 priv->wer = 0;
1647 serial_out(up, UART_OMAP_WER, priv->wer);
1648 if (uart_console(&up->port) && console_suspend_enabled)
1649 err = pm_runtime_force_suspend(dev);
1650 flush_work(&priv->qos_work);
1651
1652 return err;
1653 }
1654
omap8250_resume(struct device * dev)1655 static int omap8250_resume(struct device *dev)
1656 {
1657 struct omap8250_priv *priv = dev_get_drvdata(dev);
1658 struct uart_8250_port *up = serial8250_get_port(priv->line);
1659 int err;
1660
1661 if (uart_console(&up->port) && console_suspend_enabled) {
1662 err = pm_runtime_force_resume(dev);
1663 if (err)
1664 return err;
1665 }
1666
1667 serial8250_resume_port(priv->line);
1668 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
1669 pm_runtime_mark_last_busy(dev);
1670 pm_runtime_put_autosuspend(dev);
1671
1672 return 0;
1673 }
1674
omap8250_lost_context(struct uart_8250_port * up)1675 static int omap8250_lost_context(struct uart_8250_port *up)
1676 {
1677 u32 val;
1678
1679 val = serial_in(up, UART_OMAP_SCR);
1680 /*
1681 * If we lose context, then SCR is set to its reset value of zero.
1682 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1683 * among other bits, to never set the register back to zero again.
1684 */
1685 if (!val)
1686 return 1;
1687 return 0;
1688 }
1689
uart_write(struct omap8250_priv * priv,u32 reg,u32 val)1690 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
1691 {
1692 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
1693 }
1694
1695 /* TODO: in future, this should happen via API in drivers/reset/ */
omap8250_soft_reset(struct device * dev)1696 static int omap8250_soft_reset(struct device *dev)
1697 {
1698 struct omap8250_priv *priv = dev_get_drvdata(dev);
1699 int timeout = 100;
1700 int sysc;
1701 int syss;
1702
1703 /*
1704 * At least on omap4, unused uarts may not idle after reset without
1705 * a basic scr dma configuration even with no dma in use. The
1706 * module clkctrl status bits will be 1 instead of 3 blocking idle
1707 * for the whole clockdomain. The softreset below will clear scr,
1708 * and we restore it on resume so this is safe to do on all SoCs
1709 * needing omap8250_soft_reset() quirk. Do it in two writes as
1710 * recommended in the comment for omap8250_update_scr().
1711 */
1712 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1713 uart_write(priv, UART_OMAP_SCR,
1714 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1715
1716 sysc = uart_read(priv, UART_OMAP_SYSC);
1717
1718 /* softreset the UART */
1719 sysc |= OMAP_UART_SYSC_SOFTRESET;
1720 uart_write(priv, UART_OMAP_SYSC, sysc);
1721
1722 /* By experiments, 1us enough for reset complete on AM335x */
1723 do {
1724 udelay(1);
1725 syss = uart_read(priv, UART_OMAP_SYSS);
1726 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1727
1728 if (!timeout) {
1729 dev_err(dev, "timed out waiting for reset done\n");
1730 return -ETIMEDOUT;
1731 }
1732
1733 return 0;
1734 }
1735
omap8250_runtime_suspend(struct device * dev)1736 static int omap8250_runtime_suspend(struct device *dev)
1737 {
1738 struct omap8250_priv *priv = dev_get_drvdata(dev);
1739 struct uart_8250_port *up = NULL;
1740
1741 if (priv->line >= 0)
1742 up = serial8250_get_port(priv->line);
1743
1744 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1745 int ret;
1746
1747 ret = omap8250_soft_reset(dev);
1748 if (ret)
1749 return ret;
1750
1751 if (up) {
1752 /* Restore to UART mode after reset (for wakeup) */
1753 omap8250_update_mdr1(up, priv);
1754 /* Restore wakeup enable register */
1755 serial_out(up, UART_OMAP_WER, priv->wer);
1756 }
1757 }
1758
1759 if (up && up->dma && up->dma->rxchan)
1760 omap_8250_rx_dma_flush(up);
1761
1762 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1763 schedule_work(&priv->qos_work);
1764
1765 return 0;
1766 }
1767
omap8250_runtime_resume(struct device * dev)1768 static int omap8250_runtime_resume(struct device *dev)
1769 {
1770 struct omap8250_priv *priv = dev_get_drvdata(dev);
1771 struct uart_8250_port *up = NULL;
1772
1773 if (priv->line >= 0)
1774 up = serial8250_get_port(priv->line);
1775
1776 if (up && omap8250_lost_context(up)) {
1777 spin_lock_irq(&up->port.lock);
1778 omap8250_restore_regs(up);
1779 spin_unlock_irq(&up->port.lock);
1780 }
1781
1782 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
1783 spin_lock_irq(&up->port.lock);
1784 omap_8250_rx_dma(up);
1785 spin_unlock_irq(&up->port.lock);
1786 }
1787
1788 priv->latency = priv->calc_latency;
1789 schedule_work(&priv->qos_work);
1790 return 0;
1791 }
1792
1793 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
omap8250_console_fixup(void)1794 static int __init omap8250_console_fixup(void)
1795 {
1796 char *omap_str;
1797 char *options;
1798 u8 idx;
1799
1800 if (strstr(boot_command_line, "console=ttyS"))
1801 /* user set a ttyS based name for the console */
1802 return 0;
1803
1804 omap_str = strstr(boot_command_line, "console=ttyO");
1805 if (!omap_str)
1806 /* user did not set ttyO based console, so we don't care */
1807 return 0;
1808
1809 omap_str += 12;
1810 if ('0' <= *omap_str && *omap_str <= '9')
1811 idx = *omap_str - '0';
1812 else
1813 return 0;
1814
1815 omap_str++;
1816 if (omap_str[0] == ',') {
1817 omap_str++;
1818 options = omap_str;
1819 } else {
1820 options = NULL;
1821 }
1822
1823 add_preferred_console("ttyS", idx, options);
1824 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1825 idx, idx);
1826 pr_err("This ensures that you still see kernel messages. Please\n");
1827 pr_err("update your kernel commandline.\n");
1828 return 0;
1829 }
1830 console_initcall(omap8250_console_fixup);
1831 #endif
1832
1833 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1834 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1835 RUNTIME_PM_OPS(omap8250_runtime_suspend,
1836 omap8250_runtime_resume, NULL)
1837 .prepare = pm_sleep_ptr(omap8250_prepare),
1838 .complete = pm_sleep_ptr(omap8250_complete),
1839 };
1840
1841 static struct platform_driver omap8250_platform_driver = {
1842 .driver = {
1843 .name = "omap8250",
1844 .pm = pm_ptr(&omap8250_dev_pm_ops),
1845 .of_match_table = omap8250_dt_ids,
1846 },
1847 .probe = omap8250_probe,
1848 .remove = omap8250_remove,
1849 };
1850 module_platform_driver(omap8250_platform_driver);
1851
1852 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1853 MODULE_DESCRIPTION("OMAP 8250 Driver");
1854 MODULE_LICENSE("GPL v2");
1855