1 /* 2 * Initio A100 device driver for Linux. 3 * 4 * Copyright (c) 1994-1998 Initio Corporation 5 * Copyright (c) 2003-2004 Christoph Hellwig 6 * All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Revision History: 37 * 07/02/98 hl - v.91n Initial drivers. 38 * 09/14/98 hl - v1.01 Support new Kernel. 39 * 09/22/98 hl - v1.01a Support reset. 40 * 09/24/98 hl - v1.01b Fixed reset. 41 * 10/05/98 hl - v1.02 split the source code and release. 42 * 12/19/98 bv - v1.02a Use spinlocks for 2.1.95 and up 43 * 01/31/99 bv - v1.02b Use mdelay instead of waitForPause 44 * 08/08/99 bv - v1.02c Use waitForPause again. 45 * 06/25/02 Doug Ledford <dledford@redhat.com> - v1.02d 46 * - Remove limit on number of controllers 47 * - Port to DMA mapping API 48 * - Clean up interrupt handler registration 49 * - Fix memory leaks 50 * - Fix allocation of scsi host structs and private data 51 * 11/18/03 Christoph Hellwig <hch@lst.de> 52 * - Port to new probing API 53 * - Fix some more leaks in init failure cases 54 * 9/28/04 Christoph Hellwig <hch@lst.de> 55 * - merge the two source files 56 * - remove internal queueing code 57 * 14/06/07 Alan Cox <alan@lxorguk.ukuu.org.uk> 58 * - Grand cleanup and Linuxisation 59 */ 60 61 #include <linux/module.h> 62 #include <linux/errno.h> 63 #include <linux/delay.h> 64 #include <linux/interrupt.h> 65 #include <linux/pci.h> 66 #include <linux/init.h> 67 #include <linux/blkdev.h> 68 #include <linux/spinlock.h> 69 #include <linux/kernel.h> 70 #include <linux/string.h> 71 #include <linux/ioport.h> 72 #include <linux/dma-mapping.h> 73 74 #include <asm/io.h> 75 #include <asm/irq.h> 76 77 #include <scsi/scsi.h> 78 #include <scsi/scsi_cmnd.h> 79 #include <scsi/scsi_device.h> 80 #include <scsi/scsi_host.h> 81 82 #include "a100u2w.h" 83 84 85 static struct orc_scb *__orc_alloc_scb(struct orc_host * host); 86 static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb); 87 88 static struct orc_nvram nvram, *nvramp = &nvram; 89 90 static u8 default_nvram[64] = 91 { 92 /*----------header -------------*/ 93 0x01, /* 0x00: Sub System Vendor ID 0 */ 94 0x11, /* 0x01: Sub System Vendor ID 1 */ 95 0x60, /* 0x02: Sub System ID 0 */ 96 0x10, /* 0x03: Sub System ID 1 */ 97 0x00, /* 0x04: SubClass */ 98 0x01, /* 0x05: Vendor ID 0 */ 99 0x11, /* 0x06: Vendor ID 1 */ 100 0x60, /* 0x07: Device ID 0 */ 101 0x10, /* 0x08: Device ID 1 */ 102 0x00, /* 0x09: Reserved */ 103 0x00, /* 0x0A: Reserved */ 104 0x01, /* 0x0B: Revision of Data Structure */ 105 /* -- Host Adapter Structure --- */ 106 0x01, /* 0x0C: Number Of SCSI Channel */ 107 0x01, /* 0x0D: BIOS Configuration 1 */ 108 0x00, /* 0x0E: BIOS Configuration 2 */ 109 0x00, /* 0x0F: BIOS Configuration 3 */ 110 /* --- SCSI Channel 0 Configuration --- */ 111 0x07, /* 0x10: H/A ID */ 112 0x83, /* 0x11: Channel Configuration */ 113 0x20, /* 0x12: MAX TAG per target */ 114 0x0A, /* 0x13: SCSI Reset Recovering time */ 115 0x00, /* 0x14: Channel Configuration4 */ 116 0x00, /* 0x15: Channel Configuration5 */ 117 /* SCSI Channel 0 Target Configuration */ 118 /* 0x16-0x25 */ 119 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 120 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 121 /* --- SCSI Channel 1 Configuration --- */ 122 0x07, /* 0x26: H/A ID */ 123 0x83, /* 0x27: Channel Configuration */ 124 0x20, /* 0x28: MAX TAG per target */ 125 0x0A, /* 0x29: SCSI Reset Recovering time */ 126 0x00, /* 0x2A: Channel Configuration4 */ 127 0x00, /* 0x2B: Channel Configuration5 */ 128 /* SCSI Channel 1 Target Configuration */ 129 /* 0x2C-0x3B */ 130 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 131 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 132 0x00, /* 0x3C: Reserved */ 133 0x00, /* 0x3D: Reserved */ 134 0x00, /* 0x3E: Reserved */ 135 0x00 /* 0x3F: Checksum */ 136 }; 137 138 wait_chip_ready(struct orc_host * host)139 static u8 wait_chip_ready(struct orc_host * host) 140 { 141 int i; 142 143 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 144 if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ 145 return 1; 146 msleep(100); 147 } 148 return 0; 149 } 150 wait_firmware_ready(struct orc_host * host)151 static u8 wait_firmware_ready(struct orc_host * host) 152 { 153 int i; 154 155 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 156 if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */ 157 return 1; 158 msleep(100); /* wait 100ms before try again */ 159 } 160 return 0; 161 } 162 163 /***************************************************************************/ wait_scsi_reset_done(struct orc_host * host)164 static u8 wait_scsi_reset_done(struct orc_host * host) 165 { 166 int i; 167 168 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 169 if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ 170 return 1; 171 mdelay(100); /* wait 100ms before try again */ 172 } 173 return 0; 174 } 175 176 /***************************************************************************/ wait_HDO_off(struct orc_host * host)177 static u8 wait_HDO_off(struct orc_host * host) 178 { 179 int i; 180 181 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 182 if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */ 183 return 1; 184 mdelay(100); /* wait 100ms before try again */ 185 } 186 return 0; 187 } 188 189 /***************************************************************************/ wait_hdi_set(struct orc_host * host,u8 * data)190 static u8 wait_hdi_set(struct orc_host * host, u8 * data) 191 { 192 int i; 193 194 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ 195 if ((*data = inb(host->base + ORC_HSTUS)) & HDI) 196 return 1; /* Wait HDI set */ 197 mdelay(100); /* wait 100ms before try again */ 198 } 199 return 0; 200 } 201 202 /***************************************************************************/ orc_read_fwrev(struct orc_host * host)203 static unsigned short orc_read_fwrev(struct orc_host * host) 204 { 205 u16 version; 206 u8 data; 207 208 outb(ORC_CMD_VERSION, host->base + ORC_HDATA); 209 outb(HDO, host->base + ORC_HCTRL); 210 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 211 return 0; 212 213 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 214 return 0; 215 version = inb(host->base + ORC_HDATA); 216 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 217 218 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 219 return 0; 220 version |= inb(host->base + ORC_HDATA) << 8; 221 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 222 223 return version; 224 } 225 226 /***************************************************************************/ orc_nv_write(struct orc_host * host,unsigned char address,unsigned char value)227 static u8 orc_nv_write(struct orc_host * host, unsigned char address, unsigned char value) 228 { 229 outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA); /* Write command */ 230 outb(HDO, host->base + ORC_HCTRL); 231 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 232 return 0; 233 234 outb(address, host->base + ORC_HDATA); /* Write address */ 235 outb(HDO, host->base + ORC_HCTRL); 236 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 237 return 0; 238 239 outb(value, host->base + ORC_HDATA); /* Write value */ 240 outb(HDO, host->base + ORC_HCTRL); 241 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 242 return 0; 243 244 return 1; 245 } 246 247 /***************************************************************************/ orc_nv_read(struct orc_host * host,u8 address,u8 * ptr)248 static u8 orc_nv_read(struct orc_host * host, u8 address, u8 *ptr) 249 { 250 unsigned char data; 251 252 outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA); /* Write command */ 253 outb(HDO, host->base + ORC_HCTRL); 254 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 255 return 0; 256 257 outb(address, host->base + ORC_HDATA); /* Write address */ 258 outb(HDO, host->base + ORC_HCTRL); 259 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 260 return 0; 261 262 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 263 return 0; 264 *ptr = inb(host->base + ORC_HDATA); 265 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 266 267 return 1; 268 269 } 270 271 /** 272 * orc_exec_scb - Queue an SCB with the HA 273 * @host: host adapter the SCB belongs to 274 * @scb: SCB to queue for execution 275 */ 276 orc_exec_scb(struct orc_host * host,struct orc_scb * scb)277 static void orc_exec_scb(struct orc_host * host, struct orc_scb * scb) 278 { 279 scb->status = ORCSCB_POST; 280 outb(scb->scbidx, host->base + ORC_PQUEUE); 281 } 282 283 284 /** 285 * se2_rd_all - read SCSI parameters from EEPROM 286 * @host: Host whose EEPROM is being loaded 287 * 288 * Read SCSI H/A configuration parameters from serial EEPROM 289 */ 290 se2_rd_all(struct orc_host * host)291 static int se2_rd_all(struct orc_host * host) 292 { 293 int i; 294 u8 *np, chksum = 0; 295 296 np = (u8 *) nvramp; 297 for (i = 0; i < 64; i++, np++) { /* <01> */ 298 if (orc_nv_read(host, (u8) i, np) == 0) 299 return -1; 300 } 301 302 /*------ Is ckecksum ok ? ------*/ 303 np = (u8 *) nvramp; 304 for (i = 0; i < 63; i++) 305 chksum += *np++; 306 307 if (nvramp->CheckSum != (u8) chksum) 308 return -1; 309 return 1; 310 } 311 312 /** 313 * se2_update_all - update the EEPROM 314 * @host: Host whose EEPROM is being updated 315 * 316 * Update changed bytes in the EEPROM image. 317 */ 318 se2_update_all(struct orc_host * host)319 static void se2_update_all(struct orc_host * host) 320 { /* setup default pattern */ 321 int i; 322 u8 *np, *np1, chksum = 0; 323 324 /* Calculate checksum first */ 325 np = (u8 *) default_nvram; 326 for (i = 0; i < 63; i++) 327 chksum += *np++; 328 *np = chksum; 329 330 np = (u8 *) default_nvram; 331 np1 = (u8 *) nvramp; 332 for (i = 0; i < 64; i++, np++, np1++) { 333 if (*np != *np1) 334 orc_nv_write(host, (u8) i, *np); 335 } 336 } 337 338 /** 339 * read_eeprom - load EEPROM 340 * @host: Host EEPROM to read 341 * 342 * Read the EEPROM for a given host. If it is invalid or fails 343 * the restore the defaults and use them. 344 */ 345 read_eeprom(struct orc_host * host)346 static void read_eeprom(struct orc_host * host) 347 { 348 if (se2_rd_all(host) != 1) { 349 se2_update_all(host); /* setup default pattern */ 350 se2_rd_all(host); /* load again */ 351 } 352 } 353 354 355 /** 356 * orc_load_firmware - initialise firmware 357 * @host: Host to set up 358 * 359 * Load the firmware from the EEPROM into controller SRAM. This 360 * is basically a 4K block copy and then a 4K block read to check 361 * correctness. The rest is convulted by the indirect interfaces 362 * in the hardware 363 */ 364 orc_load_firmware(struct orc_host * host)365 static u8 orc_load_firmware(struct orc_host * host) 366 { 367 u32 data32; 368 u16 bios_addr; 369 u16 i; 370 u8 *data32_ptr, data; 371 372 373 /* Set up the EEPROM for access */ 374 375 data = inb(host->base + ORC_GCFG); 376 outb(data | EEPRG, host->base + ORC_GCFG); /* Enable EEPROM programming */ 377 outb(0x00, host->base + ORC_EBIOSADR2); 378 outw(0x0000, host->base + ORC_EBIOSADR0); 379 if (inb(host->base + ORC_EBIOSDATA) != 0x55) { 380 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 381 return 0; 382 } 383 outw(0x0001, host->base + ORC_EBIOSADR0); 384 if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { 385 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 386 return 0; 387 } 388 389 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ 390 data32_ptr = (u8 *) & data32; 391 data32 = cpu_to_le32(0); /* Initial FW address to 0 */ 392 outw(0x0010, host->base + ORC_EBIOSADR0); 393 *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 394 outw(0x0011, host->base + ORC_EBIOSADR0); 395 *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 396 outw(0x0012, host->base + ORC_EBIOSADR0); 397 *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 398 outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); 399 outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR); /* Write FW address */ 400 401 /* Copy the code from the BIOS to the SRAM */ 402 403 udelay(500); /* Required on Sun Ultra 5 ... 350 -> failures */ 404 bios_addr = (u16) le32_to_cpu(data32); /* FW code locate at BIOS address + ? */ 405 for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */ 406 i < 0x1000; /* Firmware code size = 4K */ 407 i++, bios_addr++) { 408 outw(bios_addr, host->base + ORC_EBIOSADR0); 409 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 410 if ((i % 4) == 3) { 411 outl(le32_to_cpu(data32), host->base + ORC_RISCRAM); /* Write every 4 bytes */ 412 data32_ptr = (u8 *) & data32; 413 } 414 } 415 416 /* Go back and check they match */ 417 418 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ 419 bios_addr -= 0x1000; /* Reset the BIOS address */ 420 for (i = 0, data32_ptr = (u8 *) & data32; /* Check the code */ 421 i < 0x1000; /* Firmware code size = 4K */ 422 i++, bios_addr++) { 423 outw(bios_addr, host->base + ORC_EBIOSADR0); 424 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ 425 if ((i % 4) == 3) { 426 if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) { 427 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ 428 outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ 429 return 0; 430 } 431 data32_ptr = (u8 *) & data32; 432 } 433 } 434 435 /* Success */ 436 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ 437 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ 438 return 1; 439 } 440 441 /***************************************************************************/ setup_SCBs(struct orc_host * host)442 static void setup_SCBs(struct orc_host * host) 443 { 444 struct orc_scb *scb; 445 int i; 446 struct orc_extended_scb *escb; 447 dma_addr_t escb_phys; 448 449 /* Setup SCB base and SCB Size registers */ 450 outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE); /* Total number of SCBs */ 451 /* SCB base address 0 */ 452 outl(host->scb_phys, host->base + ORC_SCBBASE0); 453 /* SCB base address 1 */ 454 outl(host->scb_phys, host->base + ORC_SCBBASE1); 455 456 /* setup scatter list address with one buffer */ 457 scb = host->scb_virt; 458 escb = host->escb_virt; 459 460 for (i = 0; i < ORC_MAXQUEUE; i++) { 461 escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i)); 462 scb->sg_addr = cpu_to_le32((u32) escb_phys); 463 scb->sense_addr = cpu_to_le32((u32) escb_phys); 464 scb->escb = escb; 465 scb->scbidx = i; 466 scb++; 467 escb++; 468 } 469 } 470 471 /** 472 * init_alloc_map - initialise allocation map 473 * @host: host map to configure 474 * 475 * Initialise the allocation maps for this device. If the device 476 * is not quiescent the caller must hold the allocation lock 477 */ 478 init_alloc_map(struct orc_host * host)479 static void init_alloc_map(struct orc_host * host) 480 { 481 u8 i, j; 482 483 for (i = 0; i < MAX_CHANNELS; i++) { 484 for (j = 0; j < 8; j++) { 485 host->allocation_map[i][j] = 0xffffffff; 486 } 487 } 488 } 489 490 /** 491 * init_orchid - initialise the host adapter 492 * @host:host adapter to initialise 493 * 494 * Initialise the controller and if necessary load the firmware. 495 * 496 * Returns -1 if the initialisation fails. 497 */ 498 init_orchid(struct orc_host * host)499 static int init_orchid(struct orc_host * host) 500 { 501 u8 *ptr; 502 u16 revision; 503 u8 i; 504 505 init_alloc_map(host); 506 outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */ 507 508 if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */ 509 revision = orc_read_fwrev(host); 510 if (revision == 0xFFFF) { 511 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ 512 if (wait_chip_ready(host) == 0) 513 return -1; 514 orc_load_firmware(host); /* Download FW */ 515 setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 516 outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */ 517 if (wait_firmware_ready(host) == 0) 518 return -1; 519 /* Wait for firmware ready */ 520 } else { 521 setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 522 } 523 } else { /* Orchid is not Ready */ 524 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ 525 if (wait_chip_ready(host) == 0) 526 return -1; 527 orc_load_firmware(host); /* Download FW */ 528 setup_SCBs(host); /* Setup SCB base and SCB Size registers */ 529 outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */ 530 531 /* clear HOSTSTOP */ 532 if (wait_firmware_ready(host) == 0) /* Wait for firmware ready */ 533 return -1; 534 } 535 536 /* Load an EEProm copy into RAM */ 537 /* Assumes single threaded at this point */ 538 read_eeprom(host); 539 540 if (nvramp->revision != 1) 541 return -1; 542 543 host->scsi_id = nvramp->scsi_id; 544 host->BIOScfg = nvramp->BIOSConfig1; 545 host->max_targets = MAX_TARGETS; 546 ptr = (u8 *) & (nvramp->Target00Config); 547 for (i = 0; i < 16; ptr++, i++) { 548 host->target_flag[i] = *ptr; 549 host->max_tags[i] = ORC_MAXTAGS; 550 } 551 552 if (nvramp->SCSI0Config & NCC_BUSRESET) 553 host->flags |= HCF_SCSI_RESET; 554 outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */ 555 return 0; 556 } 557 558 /** 559 * orc_reset_scsi_bus - perform bus reset 560 * @host: host being reset 561 * 562 * Perform a full bus reset on the adapter. 563 */ 564 orc_reset_scsi_bus(struct orc_host * host)565 static int orc_reset_scsi_bus(struct orc_host * host) 566 { /* I need Host Control Block Information */ 567 unsigned long flags; 568 569 spin_lock_irqsave(&host->allocation_lock, flags); 570 571 init_alloc_map(host); 572 /* reset scsi bus */ 573 outb(SCSIRST, host->base + ORC_HCTRL); 574 /* FIXME: We can spend up to a second with the lock held and 575 interrupts off here */ 576 if (wait_scsi_reset_done(host) == 0) { 577 spin_unlock_irqrestore(&host->allocation_lock, flags); 578 return FAILED; 579 } else { 580 spin_unlock_irqrestore(&host->allocation_lock, flags); 581 return SUCCESS; 582 } 583 } 584 585 /** 586 * orc_device_reset - device reset handler 587 * @host: host to reset 588 * @cmd: command causing the reset 589 * @target: target device 590 * 591 * Reset registers, reset a hanging bus and kill active and disconnected 592 * commands for target w/o soft reset 593 */ 594 orc_device_reset(struct orc_host * host,struct scsi_cmnd * cmd,unsigned int target)595 static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsigned int target) 596 { /* I need Host Control Block Information */ 597 struct orc_scb *scb; 598 struct orc_extended_scb *escb; 599 struct orc_scb *host_scb; 600 u8 i; 601 unsigned long flags; 602 603 spin_lock_irqsave(&(host->allocation_lock), flags); 604 scb = (struct orc_scb *) NULL; 605 escb = (struct orc_extended_scb *) NULL; 606 607 /* setup scatter list address with one buffer */ 608 host_scb = host->scb_virt; 609 610 /* FIXME: is this safe if we then fail to issue the reset or race 611 a completion ? */ 612 init_alloc_map(host); 613 614 /* Find the scb corresponding to the command */ 615 for (i = 0; i < ORC_MAXQUEUE; i++) { 616 escb = host_scb->escb; 617 if (host_scb->status && escb->srb == cmd) 618 break; 619 host_scb++; 620 } 621 622 if (i == ORC_MAXQUEUE) { 623 printk(KERN_ERR "Unable to Reset - No SCB Found\n"); 624 spin_unlock_irqrestore(&(host->allocation_lock), flags); 625 return FAILED; 626 } 627 628 /* Allocate a new SCB for the reset command to the firmware */ 629 if ((scb = __orc_alloc_scb(host)) == NULL) { 630 /* Can't happen.. */ 631 spin_unlock_irqrestore(&(host->allocation_lock), flags); 632 return FAILED; 633 } 634 635 /* Reset device is handled by the firmware, we fill in an SCB and 636 fire it at the controller, it does the rest */ 637 scb->opcode = ORC_BUSDEVRST; 638 scb->target = target; 639 scb->hastat = 0; 640 scb->tastat = 0; 641 scb->status = 0x0; 642 scb->link = 0xFF; 643 scb->reserved0 = 0; 644 scb->reserved1 = 0; 645 scb->xferlen = cpu_to_le32(0); 646 scb->sg_len = cpu_to_le32(0); 647 648 escb->srb = NULL; 649 escb->srb = cmd; 650 orc_exec_scb(host, scb); /* Start execute SCB */ 651 spin_unlock_irqrestore(&host->allocation_lock, flags); 652 return SUCCESS; 653 } 654 655 /** 656 * __orc_alloc_scb - allocate an SCB 657 * @host: host to allocate from 658 * 659 * Allocate an SCB and return a pointer to the SCB object. NULL 660 * is returned if no SCB is free. The caller must already hold 661 * the allocator lock at this point. 662 */ 663 664 __orc_alloc_scb(struct orc_host * host)665 static struct orc_scb *__orc_alloc_scb(struct orc_host * host) 666 { 667 u8 channel; 668 unsigned long idx; 669 u8 index; 670 u8 i; 671 672 channel = host->index; 673 for (i = 0; i < 8; i++) { 674 for (index = 0; index < 32; index++) { 675 if ((host->allocation_map[channel][i] >> index) & 0x01) { 676 host->allocation_map[channel][i] &= ~(1 << index); 677 idx = index + 32 * i; 678 /* 679 * Translate the index to a structure instance 680 */ 681 return host->scb_virt + idx; 682 } 683 } 684 } 685 return NULL; 686 } 687 688 /** 689 * orc_alloc_scb - allocate an SCB 690 * @host: host to allocate from 691 * 692 * Allocate an SCB and return a pointer to the SCB object. NULL 693 * is returned if no SCB is free. 694 */ 695 orc_alloc_scb(struct orc_host * host)696 static struct orc_scb *orc_alloc_scb(struct orc_host * host) 697 { 698 struct orc_scb *scb; 699 unsigned long flags; 700 701 spin_lock_irqsave(&host->allocation_lock, flags); 702 scb = __orc_alloc_scb(host); 703 spin_unlock_irqrestore(&host->allocation_lock, flags); 704 return scb; 705 } 706 707 /** 708 * orc_release_scb - release an SCB 709 * @host: host owning the SCB 710 * @scb: SCB that is now free 711 * 712 * Called to return a completed SCB to the allocation pool. Before 713 * calling the SCB must be out of use on both the host and the HA. 714 */ 715 orc_release_scb(struct orc_host * host,struct orc_scb * scb)716 static void orc_release_scb(struct orc_host *host, struct orc_scb *scb) 717 { 718 unsigned long flags; 719 u8 index, i, channel; 720 721 spin_lock_irqsave(&(host->allocation_lock), flags); 722 channel = host->index; /* Channel */ 723 index = scb->scbidx; 724 i = index / 32; 725 index %= 32; 726 host->allocation_map[channel][i] |= (1 << index); 727 spin_unlock_irqrestore(&(host->allocation_lock), flags); 728 } 729 730 /* 731 * orchid_abort_scb - abort a command 732 * 733 * Abort a queued command that has been passed to the firmware layer 734 * if possible. This is all handled by the firmware. We aks the firmware 735 * and it either aborts the command or fails 736 */ 737 orchid_abort_scb(struct orc_host * host,struct orc_scb * scb)738 static int orchid_abort_scb(struct orc_host * host, struct orc_scb * scb) 739 { 740 unsigned char data, status; 741 742 outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA); /* Write command */ 743 outb(HDO, host->base + ORC_HCTRL); 744 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 745 return 0; 746 747 outb(scb->scbidx, host->base + ORC_HDATA); /* Write address */ 748 outb(HDO, host->base + ORC_HCTRL); 749 if (wait_HDO_off(host) == 0) /* Wait HDO off */ 750 return 0; 751 752 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ 753 return 0; 754 status = inb(host->base + ORC_HDATA); 755 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ 756 757 if (status == 1) /* 0 - Successfully */ 758 return 0; /* 1 - Fail */ 759 return 1; 760 } 761 inia100_abort_cmd(struct orc_host * host,struct scsi_cmnd * cmd)762 static int inia100_abort_cmd(struct orc_host * host, struct scsi_cmnd *cmd) 763 { 764 struct orc_extended_scb *escb; 765 struct orc_scb *scb; 766 u8 i; 767 unsigned long flags; 768 769 spin_lock_irqsave(&(host->allocation_lock), flags); 770 771 scb = host->scb_virt; 772 773 /* Walk the queue until we find the SCB that belongs to the command 774 block. This isn't a performance critical path so a walk in the park 775 here does no harm */ 776 777 for (i = 0; i < ORC_MAXQUEUE; i++, scb++) { 778 escb = scb->escb; 779 if (scb->status && escb->srb == cmd) { 780 if (scb->tag_msg == 0) { 781 goto out; 782 } else { 783 /* Issue an ABORT to the firmware */ 784 if (orchid_abort_scb(host, scb)) { 785 escb->srb = NULL; 786 spin_unlock_irqrestore(&host->allocation_lock, flags); 787 return SUCCESS; 788 } else 789 goto out; 790 } 791 } 792 } 793 out: 794 spin_unlock_irqrestore(&host->allocation_lock, flags); 795 return FAILED; 796 } 797 798 /** 799 * orc_interrupt - IRQ processing 800 * @host: Host causing the interrupt 801 * 802 * This function is called from the IRQ handler and protected 803 * by the host lock. While the controller reports that there are 804 * scb's for processing we pull them off the controller, turn the 805 * index into a host address pointer to the scb and call the scb 806 * handler. 807 * 808 * Returns IRQ_HANDLED if any SCBs were processed, IRQ_NONE otherwise 809 */ 810 orc_interrupt(struct orc_host * host)811 static irqreturn_t orc_interrupt(struct orc_host * host) 812 { 813 u8 scb_index; 814 struct orc_scb *scb; 815 816 /* Check if we have an SCB queued for servicing */ 817 if (inb(host->base + ORC_RQUEUECNT) == 0) 818 return IRQ_NONE; 819 820 do { 821 /* Get the SCB index of the SCB to service */ 822 scb_index = inb(host->base + ORC_RQUEUE); 823 824 /* Translate it back to a host pointer */ 825 scb = (struct orc_scb *) ((unsigned long) host->scb_virt + (unsigned long) (sizeof(struct orc_scb) * scb_index)); 826 scb->status = 0x0; 827 /* Process the SCB */ 828 inia100_scb_handler(host, scb); 829 } while (inb(host->base + ORC_RQUEUECNT)); 830 return IRQ_HANDLED; 831 } /* End of I1060Interrupt() */ 832 833 /** 834 * inia100_build_scb - build SCB 835 * @host: host owing the control block 836 * @scb: control block to use 837 * @cmd: Mid layer command 838 * 839 * Build a host adapter control block from the SCSI mid layer command 840 */ 841 inia100_build_scb(struct orc_host * host,struct orc_scb * scb,struct scsi_cmnd * cmd)842 static int inia100_build_scb(struct orc_host * host, struct orc_scb * scb, struct scsi_cmnd * cmd) 843 { /* Create corresponding SCB */ 844 struct scatterlist *sg; 845 struct orc_sgent *sgent; /* Pointer to SG list */ 846 int i, count_sg; 847 struct orc_extended_scb *escb; 848 849 /* Links between the escb, scb and Linux scsi midlayer cmd */ 850 escb = scb->escb; 851 escb->srb = cmd; 852 sgent = NULL; 853 854 /* Set up the SCB to do a SCSI command block */ 855 scb->opcode = ORC_EXECSCSI; 856 scb->flags = SCF_NO_DCHK; /* Clear done bit */ 857 scb->target = cmd->device->id; 858 scb->lun = cmd->device->lun; 859 scb->reserved0 = 0; 860 scb->reserved1 = 0; 861 scb->sg_len = cpu_to_le32(0); 862 863 scb->xferlen = cpu_to_le32((u32) scsi_bufflen(cmd)); 864 sgent = (struct orc_sgent *) & escb->sglist[0]; 865 866 count_sg = scsi_dma_map(cmd); 867 if (count_sg < 0) 868 return count_sg; 869 BUG_ON(count_sg > TOTAL_SG_ENTRY); 870 871 /* Build the scatter gather lists */ 872 if (count_sg) { 873 scb->sg_len = cpu_to_le32((u32) (count_sg * 8)); 874 scsi_for_each_sg(cmd, sg, count_sg, i) { 875 sgent->base = cpu_to_le32((u32) sg_dma_address(sg)); 876 sgent->length = cpu_to_le32((u32) sg_dma_len(sg)); 877 sgent++; 878 } 879 } else { 880 scb->sg_len = cpu_to_le32(0); 881 sgent->base = cpu_to_le32(0); 882 sgent->length = cpu_to_le32(0); 883 } 884 scb->sg_addr = (u32) scb->sense_addr; /* sense_addr is already little endian */ 885 scb->hastat = 0; 886 scb->tastat = 0; 887 scb->link = 0xFF; 888 scb->sense_len = SENSE_SIZE; 889 scb->cdb_len = cmd->cmd_len; 890 if (scb->cdb_len >= IMAX_CDB) { 891 printk("max cdb length= %x\n", cmd->cmd_len); 892 scb->cdb_len = IMAX_CDB; 893 } 894 scb->ident = (u8)(cmd->device->lun & 0xff) | DISC_ALLOW; 895 if (cmd->device->tagged_supported) { /* Tag Support */ 896 scb->tag_msg = SIMPLE_QUEUE_TAG; /* Do simple tag only */ 897 } else { 898 scb->tag_msg = 0; /* No tag support */ 899 } 900 memcpy(scb->cdb, cmd->cmnd, scb->cdb_len); 901 return 0; 902 } 903 904 /** 905 * inia100_queue_lck - queue command with host 906 * @cmd: Command block 907 * 908 * Called by the mid layer to queue a command. Process the command 909 * block, build the host specific scb structures and if there is room 910 * queue the command down to the controller 911 */ inia100_queue_lck(struct scsi_cmnd * cmd)912 static int inia100_queue_lck(struct scsi_cmnd *cmd) 913 { 914 struct orc_scb *scb; 915 struct orc_host *host; /* Point to Host adapter control block */ 916 917 host = (struct orc_host *) cmd->device->host->hostdata; 918 /* Get free SCSI control block */ 919 if ((scb = orc_alloc_scb(host)) == NULL) 920 return SCSI_MLQUEUE_HOST_BUSY; 921 922 if (inia100_build_scb(host, scb, cmd)) { 923 orc_release_scb(host, scb); 924 return SCSI_MLQUEUE_HOST_BUSY; 925 } 926 orc_exec_scb(host, scb); /* Start execute SCB */ 927 return 0; 928 } 929 DEF_SCSI_QCMD(inia100_queue)930 static DEF_SCSI_QCMD(inia100_queue) 931 932 /***************************************************************************** 933 Function name : inia100_abort 934 Description : Abort a queued command. 935 (commands that are on the bus can't be aborted easily) 936 Input : host - Pointer to host adapter structure 937 Output : None. 938 Return : pSRB - Pointer to SCSI request block. 939 *****************************************************************************/ 940 static int inia100_abort(struct scsi_cmnd * cmd) 941 { 942 struct orc_host *host; 943 944 host = (struct orc_host *) cmd->device->host->hostdata; 945 return inia100_abort_cmd(host, cmd); 946 } 947 948 /***************************************************************************** 949 Function name : inia100_reset 950 Description : Reset registers, reset a hanging bus and 951 kill active and disconnected commands for target w/o soft reset 952 Input : host - Pointer to host adapter structure 953 Output : None. 954 Return : pSRB - Pointer to SCSI request block. 955 *****************************************************************************/ inia100_bus_reset(struct scsi_cmnd * cmd)956 static int inia100_bus_reset(struct scsi_cmnd * cmd) 957 { /* I need Host Control Block Information */ 958 struct orc_host *host; 959 host = (struct orc_host *) cmd->device->host->hostdata; 960 return orc_reset_scsi_bus(host); 961 } 962 963 /***************************************************************************** 964 Function name : inia100_device_reset 965 Description : Reset the device 966 Input : host - Pointer to host adapter structure 967 Output : None. 968 Return : pSRB - Pointer to SCSI request block. 969 *****************************************************************************/ inia100_device_reset(struct scsi_cmnd * cmd)970 static int inia100_device_reset(struct scsi_cmnd * cmd) 971 { /* I need Host Control Block Information */ 972 struct orc_host *host; 973 host = (struct orc_host *) cmd->device->host->hostdata; 974 return orc_device_reset(host, cmd, scmd_id(cmd)); 975 976 } 977 978 /** 979 * inia100_scb_handler - interrupt callback 980 * @host: Host causing the interrupt 981 * @scb: SCB the controller returned as needing processing 982 * 983 * Perform completion processing on a control block. Do the conversions 984 * from host to SCSI midlayer error coding, save any sense data and 985 * the complete with the midlayer and recycle the scb. 986 */ 987 inia100_scb_handler(struct orc_host * host,struct orc_scb * scb)988 static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb) 989 { 990 struct scsi_cmnd *cmd; /* Pointer to SCSI request block */ 991 struct orc_extended_scb *escb; 992 993 escb = scb->escb; 994 if ((cmd = (struct scsi_cmnd *) escb->srb) == NULL) { 995 printk(KERN_ERR "inia100_scb_handler: SRB pointer is empty\n"); 996 orc_release_scb(host, scb); /* Release SCB for current channel */ 997 return; 998 } 999 escb->srb = NULL; 1000 1001 switch (scb->hastat) { 1002 case 0x0: 1003 case 0xa: /* Linked command complete without error and linked normally */ 1004 case 0xb: /* Linked command complete without error interrupt generated */ 1005 scb->hastat = 0; 1006 break; 1007 1008 case 0x11: /* Selection time out-The initiator selection or target 1009 reselection was not complete within the SCSI Time out period */ 1010 scb->hastat = DID_TIME_OUT; 1011 break; 1012 1013 case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus 1014 phase sequence was requested by the target. The host adapter 1015 will generate a SCSI Reset Condition, notifying the host with 1016 a SCRD interrupt */ 1017 scb->hastat = DID_RESET; 1018 break; 1019 1020 case 0x1a: /* SCB Aborted. 07/21/98 */ 1021 scb->hastat = DID_ABORT; 1022 break; 1023 1024 case 0x12: /* Data overrun/underrun-The target attempted to transfer more data 1025 than was allocated by the Data Length field or the sum of the 1026 Scatter / Gather Data Length fields. */ 1027 case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */ 1028 case 0x16: /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */ 1029 1030 default: 1031 printk(KERN_DEBUG "inia100: %x %x\n", scb->hastat, scb->tastat); 1032 scb->hastat = DID_ERROR; /* Couldn't find any better */ 1033 break; 1034 } 1035 1036 if (scb->tastat == 2) { /* Check condition */ 1037 memcpy((unsigned char *) &cmd->sense_buffer[0], 1038 (unsigned char *) &escb->sglist[0], SENSE_SIZE); 1039 } 1040 cmd->result = scb->tastat | (scb->hastat << 16); 1041 scsi_dma_unmap(cmd); 1042 scsi_done(cmd); /* Notify system DONE */ 1043 orc_release_scb(host, scb); /* Release SCB for current channel */ 1044 } 1045 1046 /** 1047 * inia100_intr - interrupt handler 1048 * @irqno: Interrupt value 1049 * @devid: Host adapter 1050 * 1051 * Entry point for IRQ handling. All the real work is performed 1052 * by orc_interrupt. 1053 */ inia100_intr(int irqno,void * devid)1054 static irqreturn_t inia100_intr(int irqno, void *devid) 1055 { 1056 struct Scsi_Host *shost = (struct Scsi_Host *)devid; 1057 struct orc_host *host = (struct orc_host *)shost->hostdata; 1058 unsigned long flags; 1059 irqreturn_t res; 1060 1061 spin_lock_irqsave(shost->host_lock, flags); 1062 res = orc_interrupt(host); 1063 spin_unlock_irqrestore(shost->host_lock, flags); 1064 1065 return res; 1066 } 1067 1068 static const struct scsi_host_template inia100_template = { 1069 .proc_name = "inia100", 1070 .name = inia100_REVID, 1071 .queuecommand = inia100_queue, 1072 .eh_abort_handler = inia100_abort, 1073 .eh_bus_reset_handler = inia100_bus_reset, 1074 .eh_device_reset_handler = inia100_device_reset, 1075 .can_queue = 1, 1076 .this_id = 1, 1077 .sg_tablesize = SG_ALL, 1078 }; 1079 inia100_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1080 static int inia100_probe_one(struct pci_dev *pdev, 1081 const struct pci_device_id *id) 1082 { 1083 struct Scsi_Host *shost; 1084 struct orc_host *host; 1085 unsigned long port, bios; 1086 int error = -ENODEV; 1087 u32 sz; 1088 1089 if (pci_enable_device(pdev)) 1090 goto out; 1091 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1092 printk(KERN_WARNING "Unable to set 32bit DMA " 1093 "on inia100 adapter, ignoring.\n"); 1094 goto out_disable_device; 1095 } 1096 1097 pci_set_master(pdev); 1098 1099 port = pci_resource_start(pdev, 0); 1100 if (!request_region(port, 256, "inia100")) { 1101 printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port); 1102 goto out_disable_device; 1103 } 1104 1105 /* <02> read from base address + 0x50 offset to get the bios value. */ 1106 bios = inw(port + 0x50); 1107 1108 1109 shost = scsi_host_alloc(&inia100_template, sizeof(struct orc_host)); 1110 if (!shost) 1111 goto out_release_region; 1112 1113 host = (struct orc_host *)shost->hostdata; 1114 host->pdev = pdev; 1115 host->base = port; 1116 host->BIOScfg = bios; 1117 spin_lock_init(&host->allocation_lock); 1118 1119 /* Get total memory needed for SCB */ 1120 sz = ORC_MAXQUEUE * sizeof(struct orc_scb); 1121 host->scb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->scb_phys, 1122 GFP_KERNEL); 1123 if (!host->scb_virt) { 1124 printk("inia100: SCB memory allocation error\n"); 1125 goto out_host_put; 1126 } 1127 1128 /* Get total memory needed for ESCB */ 1129 sz = ORC_MAXQUEUE * sizeof(struct orc_extended_scb); 1130 host->escb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->escb_phys, 1131 GFP_KERNEL); 1132 if (!host->escb_virt) { 1133 printk("inia100: ESCB memory allocation error\n"); 1134 goto out_free_scb_array; 1135 } 1136 1137 if (init_orchid(host)) { /* Initialize orchid chip */ 1138 printk("inia100: initial orchid fail!!\n"); 1139 goto out_free_escb_array; 1140 } 1141 1142 shost->io_port = host->base; 1143 shost->n_io_port = 0xff; 1144 shost->can_queue = ORC_MAXQUEUE; 1145 shost->unique_id = shost->io_port; 1146 shost->max_id = host->max_targets; 1147 shost->max_lun = 16; 1148 shost->irq = pdev->irq; 1149 shost->this_id = host->scsi_id; /* Assign HCS index */ 1150 shost->sg_tablesize = TOTAL_SG_ENTRY; 1151 1152 /* Initial orc chip */ 1153 error = request_irq(pdev->irq, inia100_intr, IRQF_SHARED, 1154 "inia100", shost); 1155 if (error < 0) { 1156 printk(KERN_WARNING "inia100: unable to get irq %d\n", 1157 pdev->irq); 1158 goto out_free_escb_array; 1159 } 1160 1161 pci_set_drvdata(pdev, shost); 1162 1163 error = scsi_add_host(shost, &pdev->dev); 1164 if (error) 1165 goto out_free_irq; 1166 1167 scsi_scan_host(shost); 1168 return 0; 1169 1170 out_free_irq: 1171 free_irq(shost->irq, shost); 1172 out_free_escb_array: 1173 dma_free_coherent(&pdev->dev, 1174 ORC_MAXQUEUE * sizeof(struct orc_extended_scb), 1175 host->escb_virt, host->escb_phys); 1176 out_free_scb_array: 1177 dma_free_coherent(&pdev->dev, 1178 ORC_MAXQUEUE * sizeof(struct orc_scb), 1179 host->scb_virt, host->scb_phys); 1180 out_host_put: 1181 scsi_host_put(shost); 1182 out_release_region: 1183 release_region(port, 256); 1184 out_disable_device: 1185 pci_disable_device(pdev); 1186 out: 1187 return error; 1188 } 1189 inia100_remove_one(struct pci_dev * pdev)1190 static void inia100_remove_one(struct pci_dev *pdev) 1191 { 1192 struct Scsi_Host *shost = pci_get_drvdata(pdev); 1193 struct orc_host *host = (struct orc_host *)shost->hostdata; 1194 1195 scsi_remove_host(shost); 1196 1197 free_irq(shost->irq, shost); 1198 dma_free_coherent(&pdev->dev, 1199 ORC_MAXQUEUE * sizeof(struct orc_extended_scb), 1200 host->escb_virt, host->escb_phys); 1201 dma_free_coherent(&pdev->dev, 1202 ORC_MAXQUEUE * sizeof(struct orc_scb), 1203 host->scb_virt, host->scb_phys); 1204 release_region(shost->io_port, 256); 1205 1206 scsi_host_put(shost); 1207 } 1208 1209 static struct pci_device_id inia100_pci_tbl[] = { 1210 {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1211 {0,} 1212 }; 1213 MODULE_DEVICE_TABLE(pci, inia100_pci_tbl); 1214 1215 static struct pci_driver inia100_pci_driver = { 1216 .name = "inia100", 1217 .id_table = inia100_pci_tbl, 1218 .probe = inia100_probe_one, 1219 .remove = inia100_remove_one, 1220 }; 1221 1222 module_pci_driver(inia100_pci_driver); 1223 1224 MODULE_DESCRIPTION("Initio A100U2W SCSI driver"); 1225 MODULE_AUTHOR("Initio Corporation"); 1226 MODULE_LICENSE("Dual BSD/GPL"); 1227