1 /*
2 * ARM GIC support
3 *
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7 * Written by Peter Maydell
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #ifndef HW_ARM_GICV3_COMMON_H
25 #define HW_ARM_GICV3_COMMON_H
26
27 #include "hw/sysbus.h"
28 #include "hw/intc/arm_gic_common.h"
29 #include "qom/object.h"
30
31 /*
32 * Maximum number of possible interrupts, determined by the GIC architecture.
33 * Note that this does not include LPIs. When implemented, these should be
34 * dealt with separately.
35 */
36 #define GICV3_MAXIRQ 1020
37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
38
39 #define GICV3_LPI_INTID_START 8192
40
41 /*
42 * The redistributor in GICv3 has two 64KB frames per CPU; in
43 * GICv4 it has four 64KB frames per CPU.
44 */
45 #define GICV3_REDIST_SIZE 0x20000
46 #define GICV4_REDIST_SIZE 0x40000
47
48 /* Number of SGI target-list bits */
49 #define GICV3_TARGETLIST_BITS 16
50
51 /* Maximum number of list registers (architectural limit) */
52 #define GICV3_LR_MAX 16
53
54 /* For some distributor fields we want to model the array of 32-bit
55 * register values which hold various bitmaps corresponding to enabled,
56 * pending, etc bits. These macros and functions facilitate that; the
57 * APIs are generally modelled on the generic bitmap.h functions
58 * (which are unsuitable here because they use 'unsigned long' as the
59 * underlying storage type, which is very awkward when you need to
60 * access the data as 32-bit values.)
61 * Each bitmap contains a bit for each interrupt. Although there is
62 * space for the PPIs and SGIs, those bits (the first 32) are never
63 * used as that state lives in the redistributor. The unused bits are
64 * provided purely so that interrupt X's state is always in bit X; this
65 * avoids bugs where we forget to subtract GIC_INTERNAL from an
66 * interrupt number.
67 */
68 #define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
69
70 #define GIC_DECLARE_BITMAP(name) \
71 uint32_t name[GICV3_BMP_SIZE]
72
73 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
74 #define GIC_BIT_WORD(nr) ((nr) / 32)
75
gic_bmp_set_bit(int nr,uint32_t * addr)76 static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
77 {
78 uint32_t mask = GIC_BIT_MASK(nr);
79 uint32_t *p = addr + GIC_BIT_WORD(nr);
80
81 *p |= mask;
82 }
83
gic_bmp_clear_bit(int nr,uint32_t * addr)84 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
85 {
86 uint32_t mask = GIC_BIT_MASK(nr);
87 uint32_t *p = addr + GIC_BIT_WORD(nr);
88
89 *p &= ~mask;
90 }
91
gic_bmp_test_bit(int nr,const uint32_t * addr)92 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
93 {
94 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
95 }
96
gic_bmp_replace_bit(int nr,uint32_t * addr,int val)97 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
98 {
99 uint32_t mask = GIC_BIT_MASK(nr);
100 uint32_t *p = addr + GIC_BIT_WORD(nr);
101
102 *p &= ~mask;
103 *p |= (val & 1U) << (nr % 32);
104 }
105
106 /* Return a pointer to the 32-bit word containing the specified bit. */
gic_bmp_ptr32(uint32_t * addr,int nr)107 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
108 {
109 return addr + GIC_BIT_WORD(nr);
110 }
111
112 typedef struct GICv3State GICv3State;
113 typedef struct GICv3CPUState GICv3CPUState;
114
115 /* Some CPU interface registers come in three flavours:
116 * Group0, Group1 (Secure) and Group1 (NonSecure)
117 * (where the latter two are exposed as a single banked system register).
118 * In the state struct they are implemented as a 3-element array which
119 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
120 * If the CPU doesn't support EL3 then the G1 element is unused.
121 *
122 * These constants are also used to communicate the group to use for
123 * an interrupt or SGI when it is passed between the cpu interface and
124 * the redistributor or distributor. For those purposes the receiving end
125 * must be prepared to cope with a Group 1 Secure interrupt even if it does
126 * not have security support enabled, because security can be disabled
127 * independently in the CPU and in the GIC. In that case the receiver should
128 * treat an incoming Group 1 Secure interrupt as if it were Group 0.
129 * (This architectural requirement is why the _G1 element is the unused one
130 * in a no-EL3 CPU: we would otherwise have to translate back and forth
131 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
132 */
133 #define GICV3_G0 0
134 #define GICV3_G1 1
135 #define GICV3_G1NS 2
136
137 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
138 * group-related, so those indices are just 0 for S and 1 for NS.
139 * (If the CPU or the GIC, respectively, don't support the Security
140 * extensions then the S element is unused.)
141 */
142 #define GICV3_S 0
143 #define GICV3_NS 1
144
145 typedef struct {
146 int irq;
147 uint8_t prio;
148 int grp;
149 bool nmi;
150 } PendingIrq;
151
152 struct GICv3CPUState {
153 GICv3State *gic;
154 CPUState *cpu;
155 qemu_irq parent_irq;
156 qemu_irq parent_fiq;
157 qemu_irq parent_virq;
158 qemu_irq parent_vfiq;
159 qemu_irq parent_nmi;
160 qemu_irq parent_vnmi;
161
162 /* Redistributor */
163 uint32_t level; /* Current IRQ level */
164 /* RD_base page registers */
165 uint32_t gicr_ctlr;
166 uint64_t gicr_typer;
167 uint32_t gicr_statusr[2];
168 uint32_t gicr_waker;
169 uint64_t gicr_propbaser;
170 uint64_t gicr_pendbaser;
171 /* SGI_base page registers */
172 uint32_t gicr_igroupr0;
173 uint32_t gicr_ienabler0;
174 uint32_t gicr_ipendr0;
175 uint32_t gicr_iactiver0;
176 uint32_t gicr_inmir0;
177 uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
178 uint32_t gicr_igrpmodr0;
179 uint32_t gicr_nsacr;
180 uint8_t gicr_ipriorityr[GIC_INTERNAL];
181 /* VLPI_base page registers */
182 uint64_t gicr_vpropbaser;
183 uint64_t gicr_vpendbaser;
184
185 /* CPU interface */
186 uint64_t icc_sre_el1;
187 uint64_t icc_ctlr_el1[2];
188 uint64_t icc_pmr_el1;
189 uint64_t icc_bpr[3];
190 uint64_t icc_apr[3][4];
191 uint64_t icc_igrpen[3];
192 uint64_t icc_ctlr_el3;
193
194 /* Virtualization control interface */
195 uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
196 uint64_t ich_hcr_el2;
197 uint64_t ich_lr_el2[GICV3_LR_MAX];
198 uint64_t ich_vmcr_el2;
199
200 /* Properties of the CPU interface. These are initialized from
201 * the settings in the CPU proper.
202 * If the number of implemented list registers is 0 then the
203 * virtualization support is not implemented.
204 */
205 int num_list_regs;
206 int vpribits; /* number of virtual priority bits */
207 int vprebits; /* number of virtual preemption bits */
208 int pribits; /* number of physical priority bits */
209 int prebits; /* number of physical preemption bits */
210
211 /* Current highest priority pending interrupt for this CPU.
212 * This is cached information that can be recalculated from the
213 * real state above; it doesn't need to be migrated.
214 */
215 PendingIrq hppi;
216
217 /*
218 * Cached information recalculated from LPI tables
219 * in guest memory
220 */
221 PendingIrq hpplpi;
222
223 /* Cached information recalculated from vLPI tables in guest memory */
224 PendingIrq hppvlpi;
225
226 /* This is temporary working state, to avoid a malloc in gicv3_update() */
227 bool seenbetter;
228
229 /*
230 * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The
231 * CPU interface may support NMIs even when the GIC proper (what the
232 * spec calls the IRI; the redistributors and distributor) does not.
233 */
234 bool nmi_support;
235 };
236
237 /*
238 * The redistributor pages might be split into more than one region
239 * on some machine types if there are many CPUs.
240 */
241 typedef struct GICv3RedistRegion {
242 GICv3State *gic;
243 MemoryRegion iomem;
244 uint32_t cpuidx; /* index of first CPU this region covers */
245 } GICv3RedistRegion;
246
247 struct GICv3State {
248 /*< private >*/
249 SysBusDevice parent_obj;
250 /*< public >*/
251
252 MemoryRegion iomem_dist; /* Distributor */
253 GICv3RedistRegion *redist_regions; /* Redistributor Regions */
254 uint32_t *redist_region_count; /* redistributor count within each region */
255 uint32_t nb_redist_regions; /* number of redist regions */
256
257 uint32_t num_cpu;
258 uint32_t num_irq;
259 uint32_t revision;
260 bool lpi_enable;
261 bool nmi_support;
262 bool security_extn;
263 bool force_8bit_prio;
264 bool irq_reset_nonsecure;
265 bool gicd_no_migration_shift_bug;
266
267 int dev_fd; /* kvm device fd if backed by kvm vgic support */
268 Error *migration_blocker;
269
270 MemoryRegion *dma;
271 AddressSpace dma_as;
272
273 /* Distributor */
274
275 /* for a GIC with the security extensions the NS banked version of this
276 * register is just an alias of bit 1 of the S banked version.
277 */
278 uint32_t gicd_ctlr;
279 uint32_t gicd_statusr[2];
280 GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */
281 GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */
282 GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */
283 GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */
284 GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */
285 GIC_DECLARE_BITMAP(level); /* Current level */
286 GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
287 GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */
288 uint8_t gicd_ipriority[GICV3_MAXIRQ];
289 uint64_t gicd_irouter[GICV3_MAXIRQ];
290 /* Cached information: pointer to the cpu i/f for the CPUs specified
291 * in the IROUTER registers
292 */
293 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
294 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
295
296 GICv3CPUState *cpu;
297 /* List of all ITSes connected to this GIC */
298 GPtrArray *itslist;
299 };
300
301 #define GICV3_BITMAP_ACCESSORS(BMP) \
302 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
303 { \
304 gic_bmp_set_bit(irq, s->BMP); \
305 } \
306 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
307 { \
308 return gic_bmp_test_bit(irq, s->BMP); \
309 } \
310 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
311 { \
312 gic_bmp_clear_bit(irq, s->BMP); \
313 } \
314 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
315 int irq, int value) \
316 { \
317 gic_bmp_replace_bit(irq, s->BMP, value); \
318 }
319
320 GICV3_BITMAP_ACCESSORS(group)
321 GICV3_BITMAP_ACCESSORS(grpmod)
322 GICV3_BITMAP_ACCESSORS(enabled)
323 GICV3_BITMAP_ACCESSORS(pending)
324 GICV3_BITMAP_ACCESSORS(active)
325 GICV3_BITMAP_ACCESSORS(level)
326 GICV3_BITMAP_ACCESSORS(edge_trigger)
327 GICV3_BITMAP_ACCESSORS(nmi)
328
329 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
330 typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
331 DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
332 ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
333
334 struct ARMGICv3CommonClass {
335 /*< private >*/
336 SysBusDeviceClass parent_class;
337 /*< public >*/
338
339 void (*pre_save)(GICv3State *s);
340 void (*post_load)(GICv3State *s);
341 };
342
343 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
344 const MemoryRegionOps *ops);
345
346 /**
347 * gicv3_class_name
348 *
349 * Return name of GICv3 class to use depending on whether KVM acceleration is
350 * in use. May throw an error if the chosen implementation is not available.
351 *
352 * Returns: class name to use
353 */
354 const char *gicv3_class_name(void);
355
356 #endif
357