1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <div64.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 /* General purpose timers registers */
17 struct mxc_gpt {
18 unsigned int control;
19 unsigned int prescaler;
20 unsigned int status;
21 unsigned int nouse[6];
22 unsigned int counter;
23 };
24
25 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
26
27 /* General purpose timers bitfields */
28 #define GPTCR_SWR (1 << 15) /* Software reset */
29 #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
30 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
31 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
32 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
33 #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
34 #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
35 #define GPTCR_TEN 1 /* Timer enable */
36
37 #define GPTPR_PRESCALER24M_SHIFT 12
38 #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
39
gpt_has_clk_source_osc(void)40 static inline int gpt_has_clk_source_osc(void)
41 {
42 #if defined(CONFIG_MX6)
43 if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
44 is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
45 is_mx6ull() || is_mx6sll())
46 return 1;
47
48 return 0;
49 #else
50 return 0;
51 #endif
52 }
53
gpt_get_clk(void)54 static inline ulong gpt_get_clk(void)
55 {
56 #ifdef CONFIG_MXC_GPT_HCLK
57 if (gpt_has_clk_source_osc())
58 return MXC_HCLK >> 3;
59 else
60 return mxc_get_clock(MXC_IPG_PERCLK);
61 #else
62 return MXC_CLK32;
63 #endif
64 }
65
timer_init(void)66 int timer_init(void)
67 {
68 int i;
69
70 /* setup GP Timer 1 */
71 __raw_writel(GPTCR_SWR, &cur_gpt->control);
72
73 /* We have no udelay by now */
74 __raw_writel(0, &cur_gpt->control);
75
76 i = __raw_readl(&cur_gpt->control);
77 i &= ~GPTCR_CLKSOURCE_MASK;
78
79 #ifdef CONFIG_MXC_GPT_HCLK
80 if (gpt_has_clk_source_osc()) {
81 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
82
83 /*
84 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
85 * Enable bit and prescaler
86 */
87 if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
88 is_mx6sll()) {
89 i |= GPTCR_24MEN;
90
91 /* Produce 3Mhz clock */
92 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
93 &cur_gpt->prescaler);
94 }
95 } else {
96 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
97 }
98 #else
99 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
100 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
101 #endif
102 __raw_writel(i, &cur_gpt->control);
103
104 return 0;
105 }
106
timer_read_counter(void)107 unsigned long timer_read_counter(void)
108 {
109 return __raw_readl(&cur_gpt->counter); /* current tick value */
110 }
111
112 /*
113 * This function is derived from PowerPC code (timebase clock frequency).
114 * On ARM it returns the number of timer ticks per second.
115 */
get_tbclk(void)116 ulong get_tbclk(void)
117 {
118 return gpt_get_clk();
119 }
120
121 /*
122 * This function is intended for SHORT delays only.
123 * It will overflow at around 10 seconds @ 400MHz,
124 * or 20 seconds @ 200MHz.
125 */
usec2ticks(unsigned long _usec)126 unsigned long usec2ticks(unsigned long _usec)
127 {
128 unsigned long long usec = _usec;
129
130 usec *= get_tbclk();
131 usec += 999999;
132 do_div(usec, 1000000);
133
134 return usec;
135 }
136