1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "cpu.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "elf.h" 37 #include "exec/memory.h" 38 #include "hw/char/serial-mm.h" 39 #include "net/net.h" 40 #include "hw/sysbus.h" 41 #include "hw/block/flash.h" 42 #include "chardev/char.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/reset.h" 45 #include "sysemu/runstate.h" 46 #include "qemu/error-report.h" 47 #include "qemu/option.h" 48 #include "bootparam.h" 49 #include "xtensa_memory.h" 50 #include "hw/xtensa/mx_pic.h" 51 #include "migration/vmstate.h" 52 53 typedef struct XtfpgaFlashDesc { 54 hwaddr base; 55 size_t size; 56 size_t boot_base; 57 size_t sector_size; 58 } XtfpgaFlashDesc; 59 60 typedef struct XtfpgaBoardDesc { 61 const XtfpgaFlashDesc *flash; 62 size_t sram_size; 63 const hwaddr *io; 64 } XtfpgaBoardDesc; 65 66 typedef struct XtfpgaFpgaState { 67 MemoryRegion iomem; 68 uint32_t freq; 69 uint32_t leds; 70 uint32_t switches; 71 } XtfpgaFpgaState; 72 xtfpga_fpga_reset(void * opaque)73 static void xtfpga_fpga_reset(void *opaque) 74 { 75 XtfpgaFpgaState *s = opaque; 76 77 s->leds = 0; 78 s->switches = 0; 79 } 80 xtfpga_fpga_read(void * opaque,hwaddr addr,unsigned size)81 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 XtfpgaFpgaState *s = opaque; 85 86 switch (addr) { 87 case 0x0: /*build date code*/ 88 return 0x09272011; 89 90 case 0x4: /*processor clock frequency, Hz*/ 91 return s->freq; 92 93 case 0x8: /*LEDs (off = 0, on = 1)*/ 94 return s->leds; 95 96 case 0xc: /*DIP switches (off = 0, on = 1)*/ 97 return s->switches; 98 } 99 return 0; 100 } 101 xtfpga_fpga_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)102 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 103 uint64_t val, unsigned size) 104 { 105 XtfpgaFpgaState *s = opaque; 106 107 switch (addr) { 108 case 0x8: /*LEDs (off = 0, on = 1)*/ 109 s->leds = val; 110 break; 111 112 case 0x10: /*board reset*/ 113 if (val == 0xdead) { 114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 115 } 116 break; 117 } 118 } 119 120 static const MemoryRegionOps xtfpga_fpga_ops = { 121 .read = xtfpga_fpga_read, 122 .write = xtfpga_fpga_write, 123 .endianness = DEVICE_NATIVE_ENDIAN, 124 }; 125 xtfpga_fpga_init(MemoryRegion * address_space,hwaddr base,uint32_t freq)126 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 127 hwaddr base, uint32_t freq) 128 { 129 XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); 130 131 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 132 "xtfpga.fpga", 0x10000); 133 memory_region_add_subregion(address_space, base, &s->iomem); 134 s->freq = freq; 135 xtfpga_fpga_reset(s); 136 qemu_register_reset(xtfpga_fpga_reset, s); 137 return s; 138 } 139 xtfpga_net_init(MemoryRegion * address_space,hwaddr base,hwaddr descriptors,hwaddr buffers,qemu_irq irq)140 static void xtfpga_net_init(MemoryRegion *address_space, 141 hwaddr base, 142 hwaddr descriptors, 143 hwaddr buffers, 144 qemu_irq irq) 145 { 146 DeviceState *dev; 147 SysBusDevice *s; 148 MemoryRegion *ram; 149 150 dev = qemu_create_nic_device("open_eth", true, NULL); 151 if (!dev) { 152 return; 153 } 154 155 s = SYS_BUS_DEVICE(dev); 156 sysbus_realize_and_unref(s, &error_fatal); 157 sysbus_connect_irq(s, 0, irq); 158 memory_region_add_subregion(address_space, base, 159 sysbus_mmio_get_region(s, 0)); 160 memory_region_add_subregion(address_space, descriptors, 161 sysbus_mmio_get_region(s, 1)); 162 163 ram = g_malloc(sizeof(*ram)); 164 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 165 &error_fatal); 166 vmstate_register_ram_global(ram); 167 memory_region_add_subregion(address_space, buffers, ram); 168 } 169 xtfpga_flash_init(MemoryRegion * address_space,const XtfpgaBoardDesc * board,DriveInfo * dinfo,int be)170 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 171 const XtfpgaBoardDesc *board, 172 DriveInfo *dinfo, int be) 173 { 174 SysBusDevice *s; 175 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 176 177 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 178 qdev_prop_set_uint32(dev, "num-blocks", 179 board->flash->size / board->flash->sector_size); 180 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 181 qdev_prop_set_uint8(dev, "width", 2); 182 qdev_prop_set_bit(dev, "big-endian", be); 183 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 184 s = SYS_BUS_DEVICE(dev); 185 sysbus_realize_and_unref(s, &error_fatal); 186 memory_region_add_subregion(address_space, board->flash->base, 187 sysbus_mmio_get_region(s, 0)); 188 return PFLASH_CFI01(dev); 189 } 190 translate_phys_addr(void * opaque,uint64_t addr)191 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 192 { 193 XtensaCPU *cpu = opaque; 194 195 return cpu_get_phys_page_debug(CPU(cpu), addr); 196 } 197 xtfpga_reset(void * opaque)198 static void xtfpga_reset(void *opaque) 199 { 200 XtensaCPU *cpu = opaque; 201 202 cpu_reset(CPU(cpu)); 203 } 204 xtfpga_io_read(void * opaque,hwaddr addr,unsigned size)205 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 206 unsigned size) 207 { 208 return 0; 209 } 210 xtfpga_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)211 static void xtfpga_io_write(void *opaque, hwaddr addr, 212 uint64_t val, unsigned size) 213 { 214 } 215 216 static const MemoryRegionOps xtfpga_io_ops = { 217 .read = xtfpga_io_read, 218 .write = xtfpga_io_write, 219 .endianness = DEVICE_NATIVE_ENDIAN, 220 }; 221 xtfpga_init(const XtfpgaBoardDesc * board,MachineState * machine)222 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 223 { 224 MemoryRegion *system_memory = get_system_memory(); 225 XtensaCPU *cpu = NULL; 226 CPUXtensaState *env = NULL; 227 MemoryRegion *system_io; 228 XtensaMxPic *mx_pic = NULL; 229 qemu_irq *extints; 230 DriveInfo *dinfo; 231 PFlashCFI01 *flash = NULL; 232 const char *kernel_filename = machine->kernel_filename; 233 const char *kernel_cmdline = machine->kernel_cmdline; 234 const char *dtb_filename = machine->dtb; 235 const char *initrd_filename = machine->initrd_filename; 236 const unsigned system_io_size = 224 * MiB; 237 uint32_t freq = 10000000; 238 int n; 239 unsigned int smp_cpus = machine->smp.cpus; 240 241 if (smp_cpus > 1) { 242 mx_pic = xtensa_mx_pic_init(31); 243 qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 244 } 245 for (n = 0; n < smp_cpus; n++) { 246 CPUXtensaState *cenv = NULL; 247 248 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 249 cenv = &cpu->env; 250 if (!env) { 251 env = cenv; 252 freq = env->config->clock_freq_khz * 1000; 253 } 254 255 if (mx_pic) { 256 MemoryRegion *mx_eri; 257 258 mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 259 xtensa_get_extints(cenv), 260 xtensa_get_runstall(cenv)); 261 memory_region_add_subregion(xtensa_get_er_region(cenv), 262 0, mx_eri); 263 } 264 cenv->sregs[PRID] = n; 265 xtensa_select_static_vectors(cenv, n != 0); 266 qemu_register_reset(xtfpga_reset, cpu); 267 /* Need MMU initialized prior to ELF loading, 268 * so that ELF gets loaded into virtual addresses 269 */ 270 cpu_reset(CPU(cpu)); 271 } 272 if (smp_cpus > 1) { 273 extints = xtensa_mx_pic_get_extints(mx_pic); 274 } else { 275 extints = xtensa_get_extints(env); 276 } 277 278 if (env) { 279 XtensaMemory sysram = env->config->sysram; 280 281 sysram.location[0].size = machine->ram_size; 282 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 283 system_memory); 284 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 285 system_memory); 286 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 287 system_memory); 288 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 289 system_memory); 290 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 291 system_memory); 292 } 293 294 system_io = g_malloc(sizeof(*system_io)); 295 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 296 system_io_size); 297 memory_region_add_subregion(system_memory, board->io[0], system_io); 298 if (board->io[1]) { 299 MemoryRegion *io = g_malloc(sizeof(*io)); 300 301 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 302 system_io, 0, system_io_size); 303 memory_region_add_subregion(system_memory, board->io[1], io); 304 } 305 xtfpga_fpga_init(system_io, 0x0d020000, freq); 306 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]); 307 308 serial_mm_init(system_io, 0x0d050020, 2, extints[0], 309 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 310 311 dinfo = drive_get(IF_PFLASH, 0, 0); 312 if (dinfo) { 313 flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); 314 } 315 316 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 317 if (kernel_filename) { 318 uint32_t entry_point = env->pc; 319 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 320 uint32_t tagptr = env->config->sysrom.location[0].addr + 321 board->sram_size; 322 uint32_t cur_tagptr; 323 BpMemInfo memory_location = { 324 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 325 .start = tswap32(env->config->sysram.location[0].addr), 326 .end = tswap32(env->config->sysram.location[0].addr + 327 machine->ram_size), 328 }; 329 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 330 machine->ram_size : 0x08000000; 331 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 332 333 lowmem_end += env->config->sysram.location[0].addr; 334 cur_lowmem += env->config->sysram.location[0].addr; 335 336 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 337 system_memory); 338 339 if (kernel_cmdline) { 340 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 341 } 342 if (dtb_filename) { 343 bp_size += get_tag_size(sizeof(uint32_t)); 344 } 345 if (initrd_filename) { 346 bp_size += get_tag_size(sizeof(BpMemInfo)); 347 } 348 349 /* Put kernel bootparameters to the end of that SRAM */ 350 tagptr = (tagptr - bp_size) & ~0xff; 351 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 352 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 353 sizeof(memory_location), &memory_location); 354 355 if (kernel_cmdline) { 356 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 357 strlen(kernel_cmdline) + 1, kernel_cmdline); 358 } 359 if (dtb_filename) { 360 int fdt_size; 361 void *fdt = load_device_tree(dtb_filename, &fdt_size); 362 uint32_t dtb_addr = tswap32(cur_lowmem); 363 364 if (!fdt) { 365 error_report("could not load DTB '%s'", dtb_filename); 366 exit(EXIT_FAILURE); 367 } 368 369 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 370 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 371 sizeof(dtb_addr), &dtb_addr); 372 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 373 g_free(fdt); 374 } 375 if (initrd_filename) { 376 BpMemInfo initrd_location = { 0 }; 377 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 378 lowmem_end - cur_lowmem); 379 380 if (initrd_size < 0) { 381 initrd_size = load_image_targphys(initrd_filename, 382 cur_lowmem, 383 lowmem_end - cur_lowmem); 384 } 385 if (initrd_size < 0) { 386 error_report("could not load initrd '%s'", initrd_filename); 387 exit(EXIT_FAILURE); 388 } 389 initrd_location.start = tswap32(cur_lowmem); 390 initrd_location.end = tswap32(cur_lowmem + initrd_size); 391 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 392 sizeof(initrd_location), &initrd_location); 393 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 394 } 395 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 396 env->regs[2] = tagptr; 397 398 uint64_t elf_entry; 399 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 400 &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN, 401 EM_XTENSA, 0, 0); 402 if (success > 0) { 403 entry_point = elf_entry; 404 } else { 405 hwaddr ep; 406 int is_linux; 407 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 408 translate_phys_addr, cpu); 409 if (success > 0 && is_linux) { 410 entry_point = ep; 411 } else { 412 error_report("could not load kernel '%s'", 413 kernel_filename); 414 exit(EXIT_FAILURE); 415 } 416 } 417 if (entry_point != env->pc) { 418 uint8_t boot_be[] = { 419 0x60, 0x00, 0x08, /* j 1f */ 420 0x00, /* .literal_position */ 421 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 422 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 423 /* 1: */ 424 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 425 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 426 0x0a, 0x00, 0x00, /* jx a0 */ 427 }; 428 uint8_t boot_le[] = { 429 0x06, 0x02, 0x00, /* j 1f */ 430 0x00, /* .literal_position */ 431 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 432 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 433 /* 1: */ 434 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 435 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 436 0xa0, 0x00, 0x00, /* jx a0 */ 437 }; 438 const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) 439 : sizeof(boot_le); 440 uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; 441 uint32_t entry_pc = tswap32(entry_point); 442 uint32_t entry_a2 = tswap32(tagptr); 443 444 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 445 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 446 cpu_physical_memory_write(env->pc, boot, boot_sz); 447 } 448 } else { 449 if (flash) { 450 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 451 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 452 uint32_t size = env->config->sysrom.location[0].size; 453 454 if (board->flash->size - board->flash->boot_base < size) { 455 size = board->flash->size - board->flash->boot_base; 456 } 457 458 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 459 flash_mr, board->flash->boot_base, size); 460 memory_region_add_subregion(system_memory, 461 env->config->sysrom.location[0].addr, 462 flash_io); 463 } else { 464 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 465 system_memory); 466 } 467 } 468 } 469 470 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 471 472 static const hwaddr xtfpga_mmu_io[2] = { 473 0xf0000000, 474 }; 475 476 static const hwaddr xtfpga_nommu_io[2] = { 477 0x90000000, 478 0x70000000, 479 }; 480 481 static const XtfpgaFlashDesc lx60_flash = { 482 .base = 0x08000000, 483 .size = 0x00400000, 484 .sector_size = 0x10000, 485 }; 486 xtfpga_lx60_init(MachineState * machine)487 static void xtfpga_lx60_init(MachineState *machine) 488 { 489 static const XtfpgaBoardDesc lx60_board = { 490 .flash = &lx60_flash, 491 .sram_size = 0x20000, 492 .io = xtfpga_mmu_io, 493 }; 494 xtfpga_init(&lx60_board, machine); 495 } 496 xtfpga_lx60_nommu_init(MachineState * machine)497 static void xtfpga_lx60_nommu_init(MachineState *machine) 498 { 499 static const XtfpgaBoardDesc lx60_board = { 500 .flash = &lx60_flash, 501 .sram_size = 0x20000, 502 .io = xtfpga_nommu_io, 503 }; 504 xtfpga_init(&lx60_board, machine); 505 } 506 507 static const XtfpgaFlashDesc lx200_flash = { 508 .base = 0x08000000, 509 .size = 0x01000000, 510 .sector_size = 0x20000, 511 }; 512 xtfpga_lx200_init(MachineState * machine)513 static void xtfpga_lx200_init(MachineState *machine) 514 { 515 static const XtfpgaBoardDesc lx200_board = { 516 .flash = &lx200_flash, 517 .sram_size = 0x2000000, 518 .io = xtfpga_mmu_io, 519 }; 520 xtfpga_init(&lx200_board, machine); 521 } 522 xtfpga_lx200_nommu_init(MachineState * machine)523 static void xtfpga_lx200_nommu_init(MachineState *machine) 524 { 525 static const XtfpgaBoardDesc lx200_board = { 526 .flash = &lx200_flash, 527 .sram_size = 0x2000000, 528 .io = xtfpga_nommu_io, 529 }; 530 xtfpga_init(&lx200_board, machine); 531 } 532 533 static const XtfpgaFlashDesc ml605_flash = { 534 .base = 0x08000000, 535 .size = 0x01000000, 536 .sector_size = 0x20000, 537 }; 538 xtfpga_ml605_init(MachineState * machine)539 static void xtfpga_ml605_init(MachineState *machine) 540 { 541 static const XtfpgaBoardDesc ml605_board = { 542 .flash = &ml605_flash, 543 .sram_size = 0x2000000, 544 .io = xtfpga_mmu_io, 545 }; 546 xtfpga_init(&ml605_board, machine); 547 } 548 xtfpga_ml605_nommu_init(MachineState * machine)549 static void xtfpga_ml605_nommu_init(MachineState *machine) 550 { 551 static const XtfpgaBoardDesc ml605_board = { 552 .flash = &ml605_flash, 553 .sram_size = 0x2000000, 554 .io = xtfpga_nommu_io, 555 }; 556 xtfpga_init(&ml605_board, machine); 557 } 558 559 static const XtfpgaFlashDesc kc705_flash = { 560 .base = 0x00000000, 561 .size = 0x08000000, 562 .boot_base = 0x06000000, 563 .sector_size = 0x20000, 564 }; 565 xtfpga_kc705_init(MachineState * machine)566 static void xtfpga_kc705_init(MachineState *machine) 567 { 568 static const XtfpgaBoardDesc kc705_board = { 569 .flash = &kc705_flash, 570 .sram_size = 0x2000000, 571 .io = xtfpga_mmu_io, 572 }; 573 xtfpga_init(&kc705_board, machine); 574 } 575 xtfpga_kc705_nommu_init(MachineState * machine)576 static void xtfpga_kc705_nommu_init(MachineState *machine) 577 { 578 static const XtfpgaBoardDesc kc705_board = { 579 .flash = &kc705_flash, 580 .sram_size = 0x2000000, 581 .io = xtfpga_nommu_io, 582 }; 583 xtfpga_init(&kc705_board, machine); 584 } 585 xtfpga_lx60_class_init(ObjectClass * oc,void * data)586 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 587 { 588 MachineClass *mc = MACHINE_CLASS(oc); 589 590 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 591 mc->init = xtfpga_lx60_init; 592 mc->max_cpus = 32; 593 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 594 mc->default_ram_size = 64 * MiB; 595 } 596 597 static const TypeInfo xtfpga_lx60_type = { 598 .name = MACHINE_TYPE_NAME("lx60"), 599 .parent = TYPE_MACHINE, 600 .class_init = xtfpga_lx60_class_init, 601 }; 602 xtfpga_lx60_nommu_class_init(ObjectClass * oc,void * data)603 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 604 { 605 MachineClass *mc = MACHINE_CLASS(oc); 606 607 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 608 mc->init = xtfpga_lx60_nommu_init; 609 mc->max_cpus = 32; 610 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 611 mc->default_ram_size = 64 * MiB; 612 } 613 614 static const TypeInfo xtfpga_lx60_nommu_type = { 615 .name = MACHINE_TYPE_NAME("lx60-nommu"), 616 .parent = TYPE_MACHINE, 617 .class_init = xtfpga_lx60_nommu_class_init, 618 }; 619 xtfpga_lx200_class_init(ObjectClass * oc,void * data)620 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 621 { 622 MachineClass *mc = MACHINE_CLASS(oc); 623 624 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 625 mc->init = xtfpga_lx200_init; 626 mc->max_cpus = 32; 627 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 628 mc->default_ram_size = 96 * MiB; 629 } 630 631 static const TypeInfo xtfpga_lx200_type = { 632 .name = MACHINE_TYPE_NAME("lx200"), 633 .parent = TYPE_MACHINE, 634 .class_init = xtfpga_lx200_class_init, 635 }; 636 xtfpga_lx200_nommu_class_init(ObjectClass * oc,void * data)637 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 638 { 639 MachineClass *mc = MACHINE_CLASS(oc); 640 641 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 642 mc->init = xtfpga_lx200_nommu_init; 643 mc->max_cpus = 32; 644 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 645 mc->default_ram_size = 96 * MiB; 646 } 647 648 static const TypeInfo xtfpga_lx200_nommu_type = { 649 .name = MACHINE_TYPE_NAME("lx200-nommu"), 650 .parent = TYPE_MACHINE, 651 .class_init = xtfpga_lx200_nommu_class_init, 652 }; 653 xtfpga_ml605_class_init(ObjectClass * oc,void * data)654 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 655 { 656 MachineClass *mc = MACHINE_CLASS(oc); 657 658 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 659 mc->init = xtfpga_ml605_init; 660 mc->max_cpus = 32; 661 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 662 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 663 } 664 665 static const TypeInfo xtfpga_ml605_type = { 666 .name = MACHINE_TYPE_NAME("ml605"), 667 .parent = TYPE_MACHINE, 668 .class_init = xtfpga_ml605_class_init, 669 }; 670 xtfpga_ml605_nommu_class_init(ObjectClass * oc,void * data)671 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 672 { 673 MachineClass *mc = MACHINE_CLASS(oc); 674 675 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 676 mc->init = xtfpga_ml605_nommu_init; 677 mc->max_cpus = 32; 678 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 679 mc->default_ram_size = 256 * MiB; 680 } 681 682 static const TypeInfo xtfpga_ml605_nommu_type = { 683 .name = MACHINE_TYPE_NAME("ml605-nommu"), 684 .parent = TYPE_MACHINE, 685 .class_init = xtfpga_ml605_nommu_class_init, 686 }; 687 xtfpga_kc705_class_init(ObjectClass * oc,void * data)688 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 689 { 690 MachineClass *mc = MACHINE_CLASS(oc); 691 692 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 693 mc->init = xtfpga_kc705_init; 694 mc->max_cpus = 32; 695 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 696 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 697 } 698 699 static const TypeInfo xtfpga_kc705_type = { 700 .name = MACHINE_TYPE_NAME("kc705"), 701 .parent = TYPE_MACHINE, 702 .class_init = xtfpga_kc705_class_init, 703 }; 704 xtfpga_kc705_nommu_class_init(ObjectClass * oc,void * data)705 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 706 { 707 MachineClass *mc = MACHINE_CLASS(oc); 708 709 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 710 mc->init = xtfpga_kc705_nommu_init; 711 mc->max_cpus = 32; 712 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 713 mc->default_ram_size = 256 * MiB; 714 } 715 716 static const TypeInfo xtfpga_kc705_nommu_type = { 717 .name = MACHINE_TYPE_NAME("kc705-nommu"), 718 .parent = TYPE_MACHINE, 719 .class_init = xtfpga_kc705_nommu_class_init, 720 }; 721 xtfpga_machines_init(void)722 static void xtfpga_machines_init(void) 723 { 724 type_register_static(&xtfpga_lx60_type); 725 type_register_static(&xtfpga_lx200_type); 726 type_register_static(&xtfpga_ml605_type); 727 type_register_static(&xtfpga_kc705_type); 728 type_register_static(&xtfpga_lx60_nommu_type); 729 type_register_static(&xtfpga_lx200_nommu_type); 730 type_register_static(&xtfpga_ml605_nommu_type); 731 type_register_static(&xtfpga_kc705_nommu_type); 732 } 733 734 type_init(xtfpga_machines_init) 735