1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4  *
5  * Copyright (C) 2014 Marvell
6  *
7  * Marcin Wojtas <mw@semihalf.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/phy.h>
28 #include <linux/phylink.h>
29 #include <linux/phy/phy.h>
30 #include <linux/ptp_classify.h>
31 #include <linux/clk.h>
32 #include <linux/hrtimer.h>
33 #include <linux/ktime.h>
34 #include <linux/regmap.h>
35 #include <uapi/linux/ppp_defs.h>
36 #include <net/ip.h>
37 #include <net/ipv6.h>
38 #include <net/page_pool/helpers.h>
39 #include <net/tso.h>
40 #include <linux/bpf_trace.h>
41 
42 #include "mvpp2.h"
43 #include "mvpp2_prs.h"
44 #include "mvpp2_cls.h"
45 
46 enum mvpp2_bm_pool_log_num {
47 	MVPP2_BM_SHORT,
48 	MVPP2_BM_LONG,
49 	MVPP2_BM_JUMBO,
50 	MVPP2_BM_POOLS_NUM
51 };
52 
53 static struct {
54 	int pkt_size;
55 	int buf_num;
56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
57 
58 /* The prototype is added here to be used in start_dev when using ACPI. This
59  * will be removed once phylink is used for all modes (dt+ACPI).
60  */
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
62 
63 /* Queue modes */
64 #define MVPP2_QDIST_SINGLE_MODE	0
65 #define MVPP2_QDIST_MULTI_MODE	1
66 
67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
68 
69 module_param(queue_mode, int, 0444);
70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
71 
72 /* Utility/helper methods */
73 
mvpp2_write(struct mvpp2 * priv,u32 offset,u32 data)74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
75 {
76 	writel(data, priv->swth_base[0] + offset);
77 }
78 
mvpp2_read(struct mvpp2 * priv,u32 offset)79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
80 {
81 	return readl(priv->swth_base[0] + offset);
82 }
83 
mvpp2_read_relaxed(struct mvpp2 * priv,u32 offset)84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
85 {
86 	return readl_relaxed(priv->swth_base[0] + offset);
87 }
88 
mvpp2_cpu_to_thread(struct mvpp2 * priv,int cpu)89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
90 {
91 	return cpu % priv->nthreads;
92 }
93 
mvpp2_cm3_write(struct mvpp2 * priv,u32 offset,u32 data)94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
95 {
96 	writel(data, priv->cm3_base + offset);
97 }
98 
mvpp2_cm3_read(struct mvpp2 * priv,u32 offset)99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
100 {
101 	return readl(priv->cm3_base + offset);
102 }
103 
104 static struct page_pool *
mvpp2_create_page_pool(struct device * dev,int num,int len,enum dma_data_direction dma_dir)105 mvpp2_create_page_pool(struct device *dev, int num, int len,
106 		       enum dma_data_direction dma_dir)
107 {
108 	struct page_pool_params pp_params = {
109 		/* internal DMA mapping in page_pool */
110 		.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
111 		.pool_size = num,
112 		.nid = NUMA_NO_NODE,
113 		.dev = dev,
114 		.dma_dir = dma_dir,
115 		.offset = MVPP2_SKB_HEADROOM,
116 		.max_len = len,
117 	};
118 
119 	return page_pool_create(&pp_params);
120 }
121 
122 /* These accessors should be used to access:
123  *
124  * - per-thread registers, where each thread has its own copy of the
125  *   register.
126  *
127  *   MVPP2_BM_VIRT_ALLOC_REG
128  *   MVPP2_BM_ADDR_HIGH_ALLOC
129  *   MVPP22_BM_ADDR_HIGH_RLS_REG
130  *   MVPP2_BM_VIRT_RLS_REG
131  *   MVPP2_ISR_RX_TX_CAUSE_REG
132  *   MVPP2_ISR_RX_TX_MASK_REG
133  *   MVPP2_TXQ_NUM_REG
134  *   MVPP2_AGGR_TXQ_UPDATE_REG
135  *   MVPP2_TXQ_RSVD_REQ_REG
136  *   MVPP2_TXQ_RSVD_RSLT_REG
137  *   MVPP2_TXQ_SENT_REG
138  *   MVPP2_RXQ_NUM_REG
139  *
140  * - global registers that must be accessed through a specific thread
141  *   window, because they are related to an access to a per-thread
142  *   register
143  *
144  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
145  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
146  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
147  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
148  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
149  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
150  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
151  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
152  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
153  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
154  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
155  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
156  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
157  */
mvpp2_thread_write(struct mvpp2 * priv,unsigned int thread,u32 offset,u32 data)158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
159 			       u32 offset, u32 data)
160 {
161 	writel(data, priv->swth_base[thread] + offset);
162 }
163 
mvpp2_thread_read(struct mvpp2 * priv,unsigned int thread,u32 offset)164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
165 			     u32 offset)
166 {
167 	return readl(priv->swth_base[thread] + offset);
168 }
169 
mvpp2_thread_write_relaxed(struct mvpp2 * priv,unsigned int thread,u32 offset,u32 data)170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
171 				       u32 offset, u32 data)
172 {
173 	writel_relaxed(data, priv->swth_base[thread] + offset);
174 }
175 
mvpp2_thread_read_relaxed(struct mvpp2 * priv,unsigned int thread,u32 offset)176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
177 				     u32 offset)
178 {
179 	return readl_relaxed(priv->swth_base[thread] + offset);
180 }
181 
mvpp2_txdesc_dma_addr_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
183 					    struct mvpp2_tx_desc *tx_desc)
184 {
185 	if (port->priv->hw_version == MVPP21)
186 		return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
187 	else
188 		return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
189 		       MVPP2_DESC_DMA_MASK;
190 }
191 
mvpp2_txdesc_dma_addr_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,dma_addr_t dma_addr)192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
193 				      struct mvpp2_tx_desc *tx_desc,
194 				      dma_addr_t dma_addr)
195 {
196 	dma_addr_t addr, offset;
197 
198 	addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
199 	offset = dma_addr & MVPP2_TX_DESC_ALIGN;
200 
201 	if (port->priv->hw_version == MVPP21) {
202 		tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
203 		tx_desc->pp21.packet_offset = offset;
204 	} else {
205 		__le64 val = cpu_to_le64(addr);
206 
207 		tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
208 		tx_desc->pp22.buf_dma_addr_ptp |= val;
209 		tx_desc->pp22.packet_offset = offset;
210 	}
211 }
212 
mvpp2_txdesc_size_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
214 				    struct mvpp2_tx_desc *tx_desc)
215 {
216 	if (port->priv->hw_version == MVPP21)
217 		return le16_to_cpu(tx_desc->pp21.data_size);
218 	else
219 		return le16_to_cpu(tx_desc->pp22.data_size);
220 }
221 
mvpp2_txdesc_size_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,size_t size)222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
223 				  struct mvpp2_tx_desc *tx_desc,
224 				  size_t size)
225 {
226 	if (port->priv->hw_version == MVPP21)
227 		tx_desc->pp21.data_size = cpu_to_le16(size);
228 	else
229 		tx_desc->pp22.data_size = cpu_to_le16(size);
230 }
231 
mvpp2_txdesc_txq_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,unsigned int txq)232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
233 				 struct mvpp2_tx_desc *tx_desc,
234 				 unsigned int txq)
235 {
236 	if (port->priv->hw_version == MVPP21)
237 		tx_desc->pp21.phys_txq = txq;
238 	else
239 		tx_desc->pp22.phys_txq = txq;
240 }
241 
mvpp2_txdesc_cmd_set(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,unsigned int command)242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
243 				 struct mvpp2_tx_desc *tx_desc,
244 				 unsigned int command)
245 {
246 	if (port->priv->hw_version == MVPP21)
247 		tx_desc->pp21.command = cpu_to_le32(command);
248 	else
249 		tx_desc->pp22.command = cpu_to_le32(command);
250 }
251 
mvpp2_txdesc_offset_get(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc)252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
253 					    struct mvpp2_tx_desc *tx_desc)
254 {
255 	if (port->priv->hw_version == MVPP21)
256 		return tx_desc->pp21.packet_offset;
257 	else
258 		return tx_desc->pp22.packet_offset;
259 }
260 
mvpp2_rxdesc_dma_addr_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
262 					    struct mvpp2_rx_desc *rx_desc)
263 {
264 	if (port->priv->hw_version == MVPP21)
265 		return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
266 	else
267 		return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
268 		       MVPP2_DESC_DMA_MASK;
269 }
270 
mvpp2_rxdesc_cookie_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
272 					     struct mvpp2_rx_desc *rx_desc)
273 {
274 	if (port->priv->hw_version == MVPP21)
275 		return le32_to_cpu(rx_desc->pp21.buf_cookie);
276 	else
277 		return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
278 		       MVPP2_DESC_DMA_MASK;
279 }
280 
mvpp2_rxdesc_size_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
282 				    struct mvpp2_rx_desc *rx_desc)
283 {
284 	if (port->priv->hw_version == MVPP21)
285 		return le16_to_cpu(rx_desc->pp21.data_size);
286 	else
287 		return le16_to_cpu(rx_desc->pp22.data_size);
288 }
289 
mvpp2_rxdesc_status_get(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
291 				   struct mvpp2_rx_desc *rx_desc)
292 {
293 	if (port->priv->hw_version == MVPP21)
294 		return le32_to_cpu(rx_desc->pp21.status);
295 	else
296 		return le32_to_cpu(rx_desc->pp22.status);
297 }
298 
mvpp2_txq_inc_get(struct mvpp2_txq_pcpu * txq_pcpu)299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
300 {
301 	txq_pcpu->txq_get_index++;
302 	if (txq_pcpu->txq_get_index == txq_pcpu->size)
303 		txq_pcpu->txq_get_index = 0;
304 }
305 
mvpp2_txq_inc_put(struct mvpp2_port * port,struct mvpp2_txq_pcpu * txq_pcpu,void * data,struct mvpp2_tx_desc * tx_desc,enum mvpp2_tx_buf_type buf_type)306 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
307 			      struct mvpp2_txq_pcpu *txq_pcpu,
308 			      void *data,
309 			      struct mvpp2_tx_desc *tx_desc,
310 			      enum mvpp2_tx_buf_type buf_type)
311 {
312 	struct mvpp2_txq_pcpu_buf *tx_buf =
313 		txq_pcpu->buffs + txq_pcpu->txq_put_index;
314 	tx_buf->type = buf_type;
315 	if (buf_type == MVPP2_TYPE_SKB)
316 		tx_buf->skb = data;
317 	else
318 		tx_buf->xdpf = data;
319 	tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
320 	tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
321 		mvpp2_txdesc_offset_get(port, tx_desc);
322 	txq_pcpu->txq_put_index++;
323 	if (txq_pcpu->txq_put_index == txq_pcpu->size)
324 		txq_pcpu->txq_put_index = 0;
325 }
326 
327 /* Get number of maximum RXQ */
mvpp2_get_nrxqs(struct mvpp2 * priv)328 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
329 {
330 	unsigned int nrxqs;
331 
332 	if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
333 		return 1;
334 
335 	/* According to the PPv2.2 datasheet and our experiments on
336 	 * PPv2.1, RX queues have an allocation granularity of 4 (when
337 	 * more than a single one on PPv2.2).
338 	 * Round up to nearest multiple of 4.
339 	 */
340 	nrxqs = (num_possible_cpus() + 3) & ~0x3;
341 	if (nrxqs > MVPP2_PORT_MAX_RXQ)
342 		nrxqs = MVPP2_PORT_MAX_RXQ;
343 
344 	return nrxqs;
345 }
346 
347 /* Get number of physical egress port */
mvpp2_egress_port(struct mvpp2_port * port)348 static inline int mvpp2_egress_port(struct mvpp2_port *port)
349 {
350 	return MVPP2_MAX_TCONT + port->id;
351 }
352 
353 /* Get number of physical TXQ */
mvpp2_txq_phys(int port,int txq)354 static inline int mvpp2_txq_phys(int port, int txq)
355 {
356 	return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
357 }
358 
359 /* Returns a struct page if page_pool is set, otherwise a buffer */
mvpp2_frag_alloc(const struct mvpp2_bm_pool * pool,struct page_pool * page_pool)360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
361 			      struct page_pool *page_pool)
362 {
363 	if (page_pool)
364 		return page_pool_dev_alloc_pages(page_pool);
365 
366 	if (likely(pool->frag_size <= PAGE_SIZE))
367 		return netdev_alloc_frag(pool->frag_size);
368 
369 	return kmalloc(pool->frag_size, GFP_ATOMIC);
370 }
371 
mvpp2_frag_free(const struct mvpp2_bm_pool * pool,struct page_pool * page_pool,void * data)372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
373 			    struct page_pool *page_pool, void *data)
374 {
375 	if (page_pool)
376 		page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
377 	else if (likely(pool->frag_size <= PAGE_SIZE))
378 		skb_free_frag(data);
379 	else
380 		kfree(data);
381 }
382 
383 /* Buffer Manager configuration routines */
384 
385 /* Create pool */
mvpp2_bm_pool_create(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int size)386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
387 				struct mvpp2_bm_pool *bm_pool, int size)
388 {
389 	u32 val;
390 
391 	/* Number of buffer pointers must be a multiple of 16, as per
392 	 * hardware constraints
393 	 */
394 	if (!IS_ALIGNED(size, 16))
395 		return -EINVAL;
396 
397 	/* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
398 	 * bytes per buffer pointer
399 	 */
400 	if (priv->hw_version == MVPP21)
401 		bm_pool->size_bytes = 2 * sizeof(u32) * size;
402 	else
403 		bm_pool->size_bytes = 2 * sizeof(u64) * size;
404 
405 	bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
406 						&bm_pool->dma_addr,
407 						GFP_KERNEL);
408 	if (!bm_pool->virt_addr)
409 		return -ENOMEM;
410 
411 	if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
412 			MVPP2_BM_POOL_PTR_ALIGN)) {
413 		dma_free_coherent(dev, bm_pool->size_bytes,
414 				  bm_pool->virt_addr, bm_pool->dma_addr);
415 		dev_err(dev, "BM pool %d is not %d bytes aligned\n",
416 			bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
417 		return -ENOMEM;
418 	}
419 
420 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
421 		    lower_32_bits(bm_pool->dma_addr));
422 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
423 
424 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
425 	val |= MVPP2_BM_START_MASK;
426 
427 	val &= ~MVPP2_BM_LOW_THRESH_MASK;
428 	val &= ~MVPP2_BM_HIGH_THRESH_MASK;
429 
430 	/* Set 8 Pools BPPI threshold for MVPP23 */
431 	if (priv->hw_version == MVPP23) {
432 		val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
433 		val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
434 	} else {
435 		val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
436 		val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
437 	}
438 
439 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
440 
441 	bm_pool->size = size;
442 	bm_pool->pkt_size = 0;
443 	bm_pool->buf_num = 0;
444 
445 	return 0;
446 }
447 
448 /* Set pool buffer size */
mvpp2_bm_pool_bufsize_set(struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int buf_size)449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
450 				      struct mvpp2_bm_pool *bm_pool,
451 				      int buf_size)
452 {
453 	u32 val;
454 
455 	bm_pool->buf_size = buf_size;
456 
457 	val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
458 	mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
459 }
460 
mvpp2_bm_bufs_get_addrs(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,dma_addr_t * dma_addr,phys_addr_t * phys_addr)461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
462 				    struct mvpp2_bm_pool *bm_pool,
463 				    dma_addr_t *dma_addr,
464 				    phys_addr_t *phys_addr)
465 {
466 	unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
467 
468 	*dma_addr = mvpp2_thread_read(priv, thread,
469 				      MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
470 	*phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
471 
472 	if (priv->hw_version >= MVPP22) {
473 		u32 val;
474 		u32 dma_addr_highbits, phys_addr_highbits;
475 
476 		val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
477 		dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
478 		phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
479 			MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
480 
481 		if (sizeof(dma_addr_t) == 8)
482 			*dma_addr |= (u64)dma_addr_highbits << 32;
483 
484 		if (sizeof(phys_addr_t) == 8)
485 			*phys_addr |= (u64)phys_addr_highbits << 32;
486 	}
487 
488 	put_cpu();
489 }
490 
491 /* Free all buffers from the pool */
mvpp2_bm_bufs_free(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool,int buf_num)492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
493 			       struct mvpp2_bm_pool *bm_pool, int buf_num)
494 {
495 	struct page_pool *pp = NULL;
496 	int i;
497 
498 	if (buf_num > bm_pool->buf_num) {
499 		WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
500 		     bm_pool->id, buf_num);
501 		buf_num = bm_pool->buf_num;
502 	}
503 
504 	if (priv->percpu_pools)
505 		pp = priv->page_pool[bm_pool->id];
506 
507 	for (i = 0; i < buf_num; i++) {
508 		dma_addr_t buf_dma_addr;
509 		phys_addr_t buf_phys_addr;
510 		void *data;
511 
512 		mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
513 					&buf_dma_addr, &buf_phys_addr);
514 
515 		if (!pp)
516 			dma_unmap_single(dev, buf_dma_addr,
517 					 bm_pool->buf_size, DMA_FROM_DEVICE);
518 
519 		data = (void *)phys_to_virt(buf_phys_addr);
520 		if (!data)
521 			break;
522 
523 		mvpp2_frag_free(bm_pool, pp, data);
524 	}
525 
526 	/* Update BM driver with number of buffers removed from pool */
527 	bm_pool->buf_num -= i;
528 }
529 
530 /* Check number of buffers in BM pool */
mvpp2_check_hw_buf_num(struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool)531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
532 {
533 	int buf_num = 0;
534 
535 	buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
536 				    MVPP22_BM_POOL_PTRS_NUM_MASK;
537 	buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
538 				    MVPP2_BM_BPPI_PTR_NUM_MASK;
539 
540 	/* HW has one buffer ready which is not reflected in the counters */
541 	if (buf_num)
542 		buf_num += 1;
543 
544 	return buf_num;
545 }
546 
547 /* Cleanup pool */
mvpp2_bm_pool_destroy(struct device * dev,struct mvpp2 * priv,struct mvpp2_bm_pool * bm_pool)548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
549 				 struct mvpp2_bm_pool *bm_pool)
550 {
551 	int buf_num;
552 	u32 val;
553 
554 	buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
555 	mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
556 
557 	/* Check buffer counters after free */
558 	buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
559 	if (buf_num) {
560 		WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
561 		     bm_pool->id, bm_pool->buf_num);
562 		return 0;
563 	}
564 
565 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
566 	val |= MVPP2_BM_STOP_MASK;
567 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
568 
569 	if (priv->percpu_pools) {
570 		page_pool_destroy(priv->page_pool[bm_pool->id]);
571 		priv->page_pool[bm_pool->id] = NULL;
572 	}
573 
574 	dma_free_coherent(dev, bm_pool->size_bytes,
575 			  bm_pool->virt_addr,
576 			  bm_pool->dma_addr);
577 	return 0;
578 }
579 
mvpp2_bm_pools_init(struct device * dev,struct mvpp2 * priv)580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
581 {
582 	int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
583 	struct mvpp2_bm_pool *bm_pool;
584 
585 	if (priv->percpu_pools)
586 		poolnum = mvpp2_get_nrxqs(priv) * 2;
587 
588 	/* Create all pools with maximum size */
589 	size = MVPP2_BM_POOL_SIZE_MAX;
590 	for (i = 0; i < poolnum; i++) {
591 		bm_pool = &priv->bm_pools[i];
592 		bm_pool->id = i;
593 		err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
594 		if (err)
595 			goto err_unroll_pools;
596 		mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
597 	}
598 	return 0;
599 
600 err_unroll_pools:
601 	dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
602 	for (i = i - 1; i >= 0; i--)
603 		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
604 	return err;
605 }
606 
607 /* Routine enable PPv23 8 pool mode */
mvpp23_bm_set_8pool_mode(struct mvpp2 * priv)608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
609 {
610 	int val;
611 
612 	val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
613 	val |= MVPP23_BM_8POOL_MODE;
614 	mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
615 }
616 
617 /* Cleanup pool before actual initialization in the OS */
mvpp2_bm_pool_cleanup(struct mvpp2 * priv,int pool_id)618 static void mvpp2_bm_pool_cleanup(struct mvpp2 *priv, int pool_id)
619 {
620 	unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
621 	u32 val;
622 	int i;
623 
624 	/* Drain the BM from all possible residues left by firmware */
625 	for (i = 0; i < MVPP2_BM_POOL_SIZE_MAX; i++)
626 		mvpp2_thread_read(priv, thread, MVPP2_BM_PHY_ALLOC_REG(pool_id));
627 
628 	put_cpu();
629 
630 	/* Stop the BM pool */
631 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id));
632 	val |= MVPP2_BM_STOP_MASK;
633 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val);
634 }
635 
mvpp2_bm_init(struct device * dev,struct mvpp2 * priv)636 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
637 {
638 	enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
639 	int i, err, poolnum = MVPP2_BM_POOLS_NUM;
640 	struct mvpp2_port *port;
641 
642 	if (priv->percpu_pools)
643 		poolnum = mvpp2_get_nrxqs(priv) * 2;
644 
645 	/* Clean up the pool state in case it contains stale state */
646 	for (i = 0; i < poolnum; i++)
647 		mvpp2_bm_pool_cleanup(priv, i);
648 
649 	if (priv->percpu_pools) {
650 		for (i = 0; i < priv->port_count; i++) {
651 			port = priv->port_list[i];
652 			if (port->xdp_prog) {
653 				dma_dir = DMA_BIDIRECTIONAL;
654 				break;
655 			}
656 		}
657 
658 		for (i = 0; i < poolnum; i++) {
659 			/* the pool in use */
660 			int pn = i / (poolnum / 2);
661 
662 			priv->page_pool[i] =
663 				mvpp2_create_page_pool(dev,
664 						       mvpp2_pools[pn].buf_num,
665 						       mvpp2_pools[pn].pkt_size,
666 						       dma_dir);
667 			if (IS_ERR(priv->page_pool[i])) {
668 				int j;
669 
670 				for (j = 0; j < i; j++) {
671 					page_pool_destroy(priv->page_pool[j]);
672 					priv->page_pool[j] = NULL;
673 				}
674 				return PTR_ERR(priv->page_pool[i]);
675 			}
676 		}
677 	}
678 
679 	dev_info(dev, "using %d %s buffers\n", poolnum,
680 		 priv->percpu_pools ? "per-cpu" : "shared");
681 
682 	for (i = 0; i < poolnum; i++) {
683 		/* Mask BM all interrupts */
684 		mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
685 		/* Clear BM cause register */
686 		mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
687 	}
688 
689 	/* Allocate and initialize BM pools */
690 	priv->bm_pools = devm_kcalloc(dev, poolnum,
691 				      sizeof(*priv->bm_pools), GFP_KERNEL);
692 	if (!priv->bm_pools)
693 		return -ENOMEM;
694 
695 	if (priv->hw_version == MVPP23)
696 		mvpp23_bm_set_8pool_mode(priv);
697 
698 	err = mvpp2_bm_pools_init(dev, priv);
699 	if (err < 0)
700 		return err;
701 	return 0;
702 }
703 
mvpp2_setup_bm_pool(void)704 static void mvpp2_setup_bm_pool(void)
705 {
706 	/* Short pool */
707 	mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
708 	mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
709 
710 	/* Long pool */
711 	mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
712 	mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
713 
714 	/* Jumbo pool */
715 	mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
716 	mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
717 }
718 
719 /* Attach long pool to rxq */
mvpp2_rxq_long_pool_set(struct mvpp2_port * port,int lrxq,int long_pool)720 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
721 				    int lrxq, int long_pool)
722 {
723 	u32 val, mask;
724 	int prxq;
725 
726 	/* Get queue physical ID */
727 	prxq = port->rxqs[lrxq]->id;
728 
729 	if (port->priv->hw_version == MVPP21)
730 		mask = MVPP21_RXQ_POOL_LONG_MASK;
731 	else
732 		mask = MVPP22_RXQ_POOL_LONG_MASK;
733 
734 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
735 	val &= ~mask;
736 	val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
737 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
738 }
739 
740 /* Attach short pool to rxq */
mvpp2_rxq_short_pool_set(struct mvpp2_port * port,int lrxq,int short_pool)741 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
742 				     int lrxq, int short_pool)
743 {
744 	u32 val, mask;
745 	int prxq;
746 
747 	/* Get queue physical ID */
748 	prxq = port->rxqs[lrxq]->id;
749 
750 	if (port->priv->hw_version == MVPP21)
751 		mask = MVPP21_RXQ_POOL_SHORT_MASK;
752 	else
753 		mask = MVPP22_RXQ_POOL_SHORT_MASK;
754 
755 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
756 	val &= ~mask;
757 	val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
758 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
759 }
760 
mvpp2_buf_alloc(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,struct page_pool * page_pool,dma_addr_t * buf_dma_addr,phys_addr_t * buf_phys_addr,gfp_t gfp_mask)761 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
762 			     struct mvpp2_bm_pool *bm_pool,
763 			     struct page_pool *page_pool,
764 			     dma_addr_t *buf_dma_addr,
765 			     phys_addr_t *buf_phys_addr,
766 			     gfp_t gfp_mask)
767 {
768 	dma_addr_t dma_addr;
769 	struct page *page;
770 	void *data;
771 
772 	data = mvpp2_frag_alloc(bm_pool, page_pool);
773 	if (!data)
774 		return NULL;
775 
776 	if (page_pool) {
777 		page = (struct page *)data;
778 		dma_addr = page_pool_get_dma_addr(page);
779 		data = page_to_virt(page);
780 	} else {
781 		dma_addr = dma_map_single(port->dev->dev.parent, data,
782 					  MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
783 					  DMA_FROM_DEVICE);
784 		if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
785 			mvpp2_frag_free(bm_pool, NULL, data);
786 			return NULL;
787 		}
788 	}
789 	*buf_dma_addr = dma_addr;
790 	*buf_phys_addr = virt_to_phys(data);
791 
792 	return data;
793 }
794 
795 /* Routine enable flow control for RXQs condition */
mvpp2_rxq_enable_fc(struct mvpp2_port * port)796 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
797 {
798 	int val, cm3_state, host_id, q;
799 	int fq = port->first_rxq;
800 	unsigned long flags;
801 
802 	spin_lock_irqsave(&port->priv->mss_spinlock, flags);
803 
804 	/* Remove Flow control enable bit to prevent race between FW and Kernel
805 	 * If Flow control was enabled, it would be re-enabled.
806 	 */
807 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
808 	cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
809 	val &= ~FLOW_CONTROL_ENABLE_BIT;
810 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
811 
812 	/* Set same Flow control for all RXQs */
813 	for (q = 0; q < port->nrxqs; q++) {
814 		/* Set stop and start Flow control RXQ thresholds */
815 		val = MSS_THRESHOLD_START;
816 		val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
817 		mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
818 
819 		val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
820 		/* Set RXQ port ID */
821 		val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
822 		val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
823 		val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
824 			+ MSS_RXQ_ASS_HOSTID_OFFS));
825 
826 		/* Calculate RXQ host ID:
827 		 * In Single queue mode: Host ID equal to Host ID used for
828 		 *			 shared RX interrupt
829 		 * In Multi queue mode: Host ID equal to number of
830 		 *			RXQ ID / number of CoS queues
831 		 * In Single resource mode: Host ID always equal to 0
832 		 */
833 		if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
834 			host_id = port->nqvecs;
835 		else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
836 			host_id = q;
837 		else
838 			host_id = 0;
839 
840 		/* Set RXQ host ID */
841 		val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
842 			+ MSS_RXQ_ASS_HOSTID_OFFS));
843 
844 		mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
845 	}
846 
847 	/* Notify Firmware that Flow control config space ready for update */
848 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
849 	val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
850 	val |= cm3_state;
851 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
852 
853 	spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
854 }
855 
856 /* Routine disable flow control for RXQs condition */
mvpp2_rxq_disable_fc(struct mvpp2_port * port)857 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
858 {
859 	int val, cm3_state, q;
860 	unsigned long flags;
861 	int fq = port->first_rxq;
862 
863 	spin_lock_irqsave(&port->priv->mss_spinlock, flags);
864 
865 	/* Remove Flow control enable bit to prevent race between FW and Kernel
866 	 * If Flow control was enabled, it would be re-enabled.
867 	 */
868 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
869 	cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
870 	val &= ~FLOW_CONTROL_ENABLE_BIT;
871 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
872 
873 	/* Disable Flow control for all RXQs */
874 	for (q = 0; q < port->nrxqs; q++) {
875 		/* Set threshold 0 to disable Flow control */
876 		val = 0;
877 		val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
878 		mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
879 
880 		val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
881 
882 		val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
883 
884 		val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
885 			+ MSS_RXQ_ASS_HOSTID_OFFS));
886 
887 		mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
888 	}
889 
890 	/* Notify Firmware that Flow control config space ready for update */
891 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
892 	val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
893 	val |= cm3_state;
894 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
895 
896 	spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
897 }
898 
899 /* Routine disable/enable flow control for BM pool condition */
mvpp2_bm_pool_update_fc(struct mvpp2_port * port,struct mvpp2_bm_pool * pool,bool en)900 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
901 				    struct mvpp2_bm_pool *pool,
902 				    bool en)
903 {
904 	int val, cm3_state;
905 	unsigned long flags;
906 
907 	spin_lock_irqsave(&port->priv->mss_spinlock, flags);
908 
909 	/* Remove Flow control enable bit to prevent race between FW and Kernel
910 	 * If Flow control were enabled, it would be re-enabled.
911 	 */
912 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
913 	cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
914 	val &= ~FLOW_CONTROL_ENABLE_BIT;
915 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
916 
917 	/* Check if BM pool should be enabled/disable */
918 	if (en) {
919 		/* Set BM pool start and stop thresholds per port */
920 		val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
921 		val |= MSS_BUF_POOL_PORT_OFFS(port->id);
922 		val &= ~MSS_BUF_POOL_START_MASK;
923 		val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
924 		val &= ~MSS_BUF_POOL_STOP_MASK;
925 		val |= MSS_THRESHOLD_STOP;
926 		mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
927 	} else {
928 		/* Remove BM pool from the port */
929 		val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
930 		val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
931 
932 		/* Zero BM pool start and stop thresholds to disable pool
933 		 * flow control if pool empty (not used by any port)
934 		 */
935 		if (!pool->buf_num) {
936 			val &= ~MSS_BUF_POOL_START_MASK;
937 			val &= ~MSS_BUF_POOL_STOP_MASK;
938 		}
939 
940 		mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
941 	}
942 
943 	/* Notify Firmware that Flow control config space ready for update */
944 	val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
945 	val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
946 	val |= cm3_state;
947 	mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
948 
949 	spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
950 }
951 
952 /* disable/enable flow control for BM pool on all ports */
mvpp2_bm_pool_update_priv_fc(struct mvpp2 * priv,bool en)953 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
954 {
955 	struct mvpp2_port *port;
956 	int i, j;
957 
958 	for (i = 0; i < priv->port_count; i++) {
959 		port = priv->port_list[i];
960 		if (port->priv->percpu_pools) {
961 			for (j = 0; j < port->nrxqs; j++)
962 				mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[j],
963 							port->tx_fc & en);
964 		} else {
965 			mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
966 			mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en);
967 		}
968 	}
969 }
970 
mvpp2_enable_global_fc(struct mvpp2 * priv)971 static int mvpp2_enable_global_fc(struct mvpp2 *priv)
972 {
973 	int val, timeout = 0;
974 
975 	/* Enable global flow control. In this stage global
976 	 * flow control enabled, but still disabled per port.
977 	 */
978 	val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
979 	val |= FLOW_CONTROL_ENABLE_BIT;
980 	mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
981 
982 	/* Check if Firmware running and disable FC if not*/
983 	val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
984 	mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
985 
986 	while (timeout < MSS_FC_MAX_TIMEOUT) {
987 		val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
988 
989 		if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
990 			return 0;
991 		usleep_range(10, 20);
992 		timeout++;
993 	}
994 
995 	priv->global_tx_fc = false;
996 	return -EOPNOTSUPP;
997 }
998 
999 /* Release buffer to BM */
mvpp2_bm_pool_put(struct mvpp2_port * port,int pool,dma_addr_t buf_dma_addr,phys_addr_t buf_phys_addr)1000 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
1001 				     dma_addr_t buf_dma_addr,
1002 				     phys_addr_t buf_phys_addr)
1003 {
1004 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1005 	unsigned long flags = 0;
1006 
1007 	if (test_bit(thread, &port->priv->lock_map))
1008 		spin_lock_irqsave(&port->bm_lock[thread], flags);
1009 
1010 	if (port->priv->hw_version >= MVPP22) {
1011 		u32 val = 0;
1012 
1013 		if (sizeof(dma_addr_t) == 8)
1014 			val |= upper_32_bits(buf_dma_addr) &
1015 				MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
1016 
1017 		if (sizeof(phys_addr_t) == 8)
1018 			val |= (upper_32_bits(buf_phys_addr)
1019 				<< MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
1020 				MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
1021 
1022 		mvpp2_thread_write_relaxed(port->priv, thread,
1023 					   MVPP22_BM_ADDR_HIGH_RLS_REG, val);
1024 	}
1025 
1026 	/* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
1027 	 * returned in the "cookie" field of the RX
1028 	 * descriptor. Instead of storing the virtual address, we
1029 	 * store the physical address
1030 	 */
1031 	mvpp2_thread_write_relaxed(port->priv, thread,
1032 				   MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1033 	mvpp2_thread_write_relaxed(port->priv, thread,
1034 				   MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
1035 
1036 	if (test_bit(thread, &port->priv->lock_map))
1037 		spin_unlock_irqrestore(&port->bm_lock[thread], flags);
1038 
1039 	put_cpu();
1040 }
1041 
1042 /* Allocate buffers for the pool */
mvpp2_bm_bufs_add(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,int buf_num)1043 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
1044 			     struct mvpp2_bm_pool *bm_pool, int buf_num)
1045 {
1046 	int i, buf_size, total_size;
1047 	dma_addr_t dma_addr;
1048 	phys_addr_t phys_addr;
1049 	struct page_pool *pp = NULL;
1050 	void *buf;
1051 
1052 	if (port->priv->percpu_pools &&
1053 	    bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1054 		netdev_err(port->dev,
1055 			   "attempted to use jumbo frames with per-cpu pools");
1056 		return 0;
1057 	}
1058 
1059 	buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
1060 	total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
1061 
1062 	if (buf_num < 0 ||
1063 	    (buf_num + bm_pool->buf_num > bm_pool->size)) {
1064 		netdev_err(port->dev,
1065 			   "cannot allocate %d buffers for pool %d\n",
1066 			   buf_num, bm_pool->id);
1067 		return 0;
1068 	}
1069 
1070 	if (port->priv->percpu_pools)
1071 		pp = port->priv->page_pool[bm_pool->id];
1072 	for (i = 0; i < buf_num; i++) {
1073 		buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
1074 				      &phys_addr, GFP_KERNEL);
1075 		if (!buf)
1076 			break;
1077 
1078 		mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
1079 				  phys_addr);
1080 	}
1081 
1082 	/* Update BM driver with number of buffers added to pool */
1083 	bm_pool->buf_num += i;
1084 
1085 	netdev_dbg(port->dev,
1086 		   "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
1087 		   bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
1088 
1089 	netdev_dbg(port->dev,
1090 		   "pool %d: %d of %d buffers added\n",
1091 		   bm_pool->id, i, buf_num);
1092 	return i;
1093 }
1094 
1095 /* Notify the driver that BM pool is being used as specific type and return the
1096  * pool pointer on success
1097  */
1098 static struct mvpp2_bm_pool *
mvpp2_bm_pool_use(struct mvpp2_port * port,unsigned pool,int pkt_size)1099 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
1100 {
1101 	struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1102 	int num;
1103 
1104 	if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
1105 	    (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
1106 		netdev_err(port->dev, "Invalid pool %d\n", pool);
1107 		return NULL;
1108 	}
1109 
1110 	/* Allocate buffers in case BM pool is used as long pool, but packet
1111 	 * size doesn't match MTU or BM pool hasn't being used yet
1112 	 */
1113 	if (new_pool->pkt_size == 0) {
1114 		int pkts_num;
1115 
1116 		/* Set default buffer number or free all the buffers in case
1117 		 * the pool is not empty
1118 		 */
1119 		pkts_num = new_pool->buf_num;
1120 		if (pkts_num == 0) {
1121 			if (port->priv->percpu_pools) {
1122 				if (pool < port->nrxqs)
1123 					pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
1124 				else
1125 					pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
1126 			} else {
1127 				pkts_num = mvpp2_pools[pool].buf_num;
1128 			}
1129 		} else {
1130 			mvpp2_bm_bufs_free(port->dev->dev.parent,
1131 					   port->priv, new_pool, pkts_num);
1132 		}
1133 
1134 		new_pool->pkt_size = pkt_size;
1135 		new_pool->frag_size =
1136 			SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1137 			MVPP2_SKB_SHINFO_SIZE;
1138 
1139 		/* Allocate buffers for this pool */
1140 		num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1141 		if (num != pkts_num) {
1142 			WARN(1, "pool %d: %d of %d allocated\n",
1143 			     new_pool->id, num, pkts_num);
1144 			return NULL;
1145 		}
1146 	}
1147 
1148 	mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1149 				  MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1150 
1151 	return new_pool;
1152 }
1153 
1154 static struct mvpp2_bm_pool *
mvpp2_bm_pool_use_percpu(struct mvpp2_port * port,int type,unsigned int pool,int pkt_size)1155 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
1156 			 unsigned int pool, int pkt_size)
1157 {
1158 	struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1159 	int num;
1160 
1161 	if (pool > port->nrxqs * 2) {
1162 		netdev_err(port->dev, "Invalid pool %d\n", pool);
1163 		return NULL;
1164 	}
1165 
1166 	/* Allocate buffers in case BM pool is used as long pool, but packet
1167 	 * size doesn't match MTU or BM pool hasn't being used yet
1168 	 */
1169 	if (new_pool->pkt_size == 0) {
1170 		int pkts_num;
1171 
1172 		/* Set default buffer number or free all the buffers in case
1173 		 * the pool is not empty
1174 		 */
1175 		pkts_num = new_pool->buf_num;
1176 		if (pkts_num == 0)
1177 			pkts_num = mvpp2_pools[type].buf_num;
1178 		else
1179 			mvpp2_bm_bufs_free(port->dev->dev.parent,
1180 					   port->priv, new_pool, pkts_num);
1181 
1182 		new_pool->pkt_size = pkt_size;
1183 		new_pool->frag_size =
1184 			SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1185 			MVPP2_SKB_SHINFO_SIZE;
1186 
1187 		/* Allocate buffers for this pool */
1188 		num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1189 		if (num != pkts_num) {
1190 			WARN(1, "pool %d: %d of %d allocated\n",
1191 			     new_pool->id, num, pkts_num);
1192 			return NULL;
1193 		}
1194 	}
1195 
1196 	mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1197 				  MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1198 
1199 	return new_pool;
1200 }
1201 
1202 /* Initialize pools for swf, shared buffers variant */
mvpp2_swf_bm_pool_init_shared(struct mvpp2_port * port)1203 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
1204 {
1205 	enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
1206 	int rxq;
1207 
1208 	/* If port pkt_size is higher than 1518B:
1209 	 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1210 	 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1211 	 */
1212 	if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1213 		long_log_pool = MVPP2_BM_JUMBO;
1214 		short_log_pool = MVPP2_BM_LONG;
1215 	} else {
1216 		long_log_pool = MVPP2_BM_LONG;
1217 		short_log_pool = MVPP2_BM_SHORT;
1218 	}
1219 
1220 	if (!port->pool_long) {
1221 		port->pool_long =
1222 			mvpp2_bm_pool_use(port, long_log_pool,
1223 					  mvpp2_pools[long_log_pool].pkt_size);
1224 		if (!port->pool_long)
1225 			return -ENOMEM;
1226 
1227 		port->pool_long->port_map |= BIT(port->id);
1228 
1229 		for (rxq = 0; rxq < port->nrxqs; rxq++)
1230 			mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
1231 	}
1232 
1233 	if (!port->pool_short) {
1234 		port->pool_short =
1235 			mvpp2_bm_pool_use(port, short_log_pool,
1236 					  mvpp2_pools[short_log_pool].pkt_size);
1237 		if (!port->pool_short)
1238 			return -ENOMEM;
1239 
1240 		port->pool_short->port_map |= BIT(port->id);
1241 
1242 		for (rxq = 0; rxq < port->nrxqs; rxq++)
1243 			mvpp2_rxq_short_pool_set(port, rxq,
1244 						 port->pool_short->id);
1245 	}
1246 
1247 	return 0;
1248 }
1249 
1250 /* Initialize pools for swf, percpu buffers variant */
mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port * port)1251 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
1252 {
1253 	struct mvpp2_bm_pool *bm_pool;
1254 	int i;
1255 
1256 	for (i = 0; i < port->nrxqs; i++) {
1257 		bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
1258 						   mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
1259 		if (!bm_pool)
1260 			return -ENOMEM;
1261 
1262 		bm_pool->port_map |= BIT(port->id);
1263 		mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1264 	}
1265 
1266 	for (i = 0; i < port->nrxqs; i++) {
1267 		bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1268 						   mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1269 		if (!bm_pool)
1270 			return -ENOMEM;
1271 
1272 		bm_pool->port_map |= BIT(port->id);
1273 		mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1274 	}
1275 
1276 	port->pool_long = NULL;
1277 	port->pool_short = NULL;
1278 
1279 	return 0;
1280 }
1281 
mvpp2_swf_bm_pool_init(struct mvpp2_port * port)1282 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1283 {
1284 	if (port->priv->percpu_pools)
1285 		return mvpp2_swf_bm_pool_init_percpu(port);
1286 	else
1287 		return mvpp2_swf_bm_pool_init_shared(port);
1288 }
1289 
mvpp2_set_hw_csum(struct mvpp2_port * port,enum mvpp2_bm_pool_log_num new_long_pool)1290 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1291 			      enum mvpp2_bm_pool_log_num new_long_pool)
1292 {
1293 	const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1294 
1295 	/* Update L4 checksum when jumbo enable/disable on port.
1296 	 * Only port 0 supports hardware checksum offload due to
1297 	 * the Tx FIFO size limitation.
1298 	 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1299 	 * has 7 bits, so the maximum L3 offset is 128.
1300 	 */
1301 	if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1302 		port->dev->features &= ~csums;
1303 		port->dev->hw_features &= ~csums;
1304 	} else {
1305 		port->dev->features |= csums;
1306 		port->dev->hw_features |= csums;
1307 	}
1308 }
1309 
mvpp2_bm_update_mtu(struct net_device * dev,int mtu)1310 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1311 {
1312 	struct mvpp2_port *port = netdev_priv(dev);
1313 	enum mvpp2_bm_pool_log_num new_long_pool;
1314 	int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1315 
1316 	if (port->priv->percpu_pools)
1317 		goto out_set;
1318 
1319 	/* If port MTU is higher than 1518B:
1320 	 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1321 	 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1322 	 */
1323 	if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1324 		new_long_pool = MVPP2_BM_JUMBO;
1325 	else
1326 		new_long_pool = MVPP2_BM_LONG;
1327 
1328 	if (new_long_pool != port->pool_long->id) {
1329 		if (port->tx_fc) {
1330 			if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1331 				mvpp2_bm_pool_update_fc(port,
1332 							port->pool_short,
1333 							false);
1334 			else
1335 				mvpp2_bm_pool_update_fc(port, port->pool_long,
1336 							false);
1337 		}
1338 
1339 		/* Remove port from old short & long pool */
1340 		port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1341 						    port->pool_long->pkt_size);
1342 		port->pool_long->port_map &= ~BIT(port->id);
1343 		port->pool_long = NULL;
1344 
1345 		port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1346 						     port->pool_short->pkt_size);
1347 		port->pool_short->port_map &= ~BIT(port->id);
1348 		port->pool_short = NULL;
1349 
1350 		port->pkt_size =  pkt_size;
1351 
1352 		/* Add port to new short & long pool */
1353 		mvpp2_swf_bm_pool_init(port);
1354 
1355 		mvpp2_set_hw_csum(port, new_long_pool);
1356 
1357 		if (port->tx_fc) {
1358 			if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1359 				mvpp2_bm_pool_update_fc(port, port->pool_long,
1360 							true);
1361 			else
1362 				mvpp2_bm_pool_update_fc(port, port->pool_short,
1363 							true);
1364 		}
1365 
1366 		/* Update L4 checksum when jumbo enable/disable on port */
1367 		if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1368 			dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1369 			dev->hw_features &= ~(NETIF_F_IP_CSUM |
1370 					      NETIF_F_IPV6_CSUM);
1371 		} else {
1372 			dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1373 			dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1374 		}
1375 	}
1376 
1377 out_set:
1378 	dev->mtu = mtu;
1379 	dev->wanted_features = dev->features;
1380 
1381 	netdev_update_features(dev);
1382 	return 0;
1383 }
1384 
mvpp2_interrupts_enable(struct mvpp2_port * port)1385 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1386 {
1387 	int i, sw_thread_mask = 0;
1388 
1389 	for (i = 0; i < port->nqvecs; i++)
1390 		sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1391 
1392 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1393 		    MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1394 }
1395 
mvpp2_interrupts_disable(struct mvpp2_port * port)1396 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1397 {
1398 	int i, sw_thread_mask = 0;
1399 
1400 	for (i = 0; i < port->nqvecs; i++)
1401 		sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1402 
1403 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1404 		    MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1405 }
1406 
mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector * qvec)1407 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1408 {
1409 	struct mvpp2_port *port = qvec->port;
1410 
1411 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1412 		    MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1413 }
1414 
mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector * qvec)1415 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1416 {
1417 	struct mvpp2_port *port = qvec->port;
1418 
1419 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1420 		    MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1421 }
1422 
1423 /* Mask the current thread's Rx/Tx interrupts
1424  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1425  * using smp_processor_id() is OK.
1426  */
mvpp2_interrupts_mask(void * arg)1427 static void mvpp2_interrupts_mask(void *arg)
1428 {
1429 	struct mvpp2_port *port = arg;
1430 	int cpu = smp_processor_id();
1431 	u32 thread;
1432 
1433 	/* If the thread isn't used, don't do anything */
1434 	if (cpu > port->priv->nthreads)
1435 		return;
1436 
1437 	thread = mvpp2_cpu_to_thread(port->priv, cpu);
1438 
1439 	mvpp2_thread_write(port->priv, thread,
1440 			   MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1441 	mvpp2_thread_write(port->priv, thread,
1442 			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
1443 }
1444 
1445 /* Unmask the current thread's Rx/Tx interrupts.
1446  * Called by on_each_cpu(), guaranteed to run with migration disabled,
1447  * using smp_processor_id() is OK.
1448  */
mvpp2_interrupts_unmask(void * arg)1449 static void mvpp2_interrupts_unmask(void *arg)
1450 {
1451 	struct mvpp2_port *port = arg;
1452 	int cpu = smp_processor_id();
1453 	u32 val, thread;
1454 
1455 	/* If the thread isn't used, don't do anything */
1456 	if (cpu >= port->priv->nthreads)
1457 		return;
1458 
1459 	thread = mvpp2_cpu_to_thread(port->priv, cpu);
1460 
1461 	val = MVPP2_CAUSE_MISC_SUM_MASK |
1462 		MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1463 	if (port->has_tx_irqs)
1464 		val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1465 
1466 	mvpp2_thread_write(port->priv, thread,
1467 			   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1468 	mvpp2_thread_write(port->priv, thread,
1469 			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1470 			   MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1471 }
1472 
1473 static void
mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port * port,bool mask)1474 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1475 {
1476 	u32 val;
1477 	int i;
1478 
1479 	if (port->priv->hw_version == MVPP21)
1480 		return;
1481 
1482 	if (mask)
1483 		val = 0;
1484 	else
1485 		val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1486 
1487 	for (i = 0; i < port->nqvecs; i++) {
1488 		struct mvpp2_queue_vector *v = port->qvecs + i;
1489 
1490 		if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1491 			continue;
1492 
1493 		mvpp2_thread_write(port->priv, v->sw_thread_id,
1494 				   MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1495 		mvpp2_thread_write(port->priv, v->sw_thread_id,
1496 				   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1497 				   MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1498 	}
1499 }
1500 
1501 /* Only GOP port 0 has an XLG MAC */
mvpp2_port_supports_xlg(struct mvpp2_port * port)1502 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1503 {
1504 	return port->gop_id == 0;
1505 }
1506 
mvpp2_port_supports_rgmii(struct mvpp2_port * port)1507 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1508 {
1509 	return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
1510 }
1511 
1512 /* Port configuration routines */
mvpp2_is_xlg(phy_interface_t interface)1513 static bool mvpp2_is_xlg(phy_interface_t interface)
1514 {
1515 	return interface == PHY_INTERFACE_MODE_10GBASER ||
1516 	       interface == PHY_INTERFACE_MODE_5GBASER ||
1517 	       interface == PHY_INTERFACE_MODE_XAUI;
1518 }
1519 
mvpp2_modify(void __iomem * ptr,u32 mask,u32 set)1520 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1521 {
1522 	u32 old, val;
1523 
1524 	old = val = readl(ptr);
1525 	val &= ~mask;
1526 	val |= set;
1527 	if (old != val)
1528 		writel(val, ptr);
1529 }
1530 
mvpp22_gop_init_rgmii(struct mvpp2_port * port)1531 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1532 {
1533 	struct mvpp2 *priv = port->priv;
1534 	u32 val;
1535 
1536 	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1537 	val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1538 	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1539 
1540 	regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1541 	if (port->gop_id == 2)
1542 		val |= GENCONF_CTRL0_PORT2_RGMII;
1543 	else if (port->gop_id == 3)
1544 		val |= GENCONF_CTRL0_PORT3_RGMII_MII;
1545 	regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1546 }
1547 
mvpp22_gop_init_sgmii(struct mvpp2_port * port)1548 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1549 {
1550 	struct mvpp2 *priv = port->priv;
1551 	u32 val;
1552 
1553 	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1554 	val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1555 	       GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1556 	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1557 
1558 	if (port->gop_id > 1) {
1559 		regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1560 		if (port->gop_id == 2)
1561 			val &= ~GENCONF_CTRL0_PORT2_RGMII;
1562 		else if (port->gop_id == 3)
1563 			val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
1564 		regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1565 	}
1566 }
1567 
mvpp22_gop_init_10gkr(struct mvpp2_port * port)1568 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1569 {
1570 	struct mvpp2 *priv = port->priv;
1571 	void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1572 	void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1573 	u32 val;
1574 
1575 	val = readl(xpcs + MVPP22_XPCS_CFG0);
1576 	val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1577 		 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1578 	val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1579 	writel(val, xpcs + MVPP22_XPCS_CFG0);
1580 
1581 	val = readl(mpcs + MVPP22_MPCS_CTRL);
1582 	val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1583 	writel(val, mpcs + MVPP22_MPCS_CTRL);
1584 
1585 	val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1586 	val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1587 	val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1588 	writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1589 }
1590 
mvpp22_gop_fca_enable_periodic(struct mvpp2_port * port,bool en)1591 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
1592 {
1593 	struct mvpp2 *priv = port->priv;
1594 	void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1595 	u32 val;
1596 
1597 	val = readl(fca + MVPP22_FCA_CONTROL_REG);
1598 	val &= ~MVPP22_FCA_ENABLE_PERIODIC;
1599 	if (en)
1600 		val |= MVPP22_FCA_ENABLE_PERIODIC;
1601 	writel(val, fca + MVPP22_FCA_CONTROL_REG);
1602 }
1603 
mvpp22_gop_fca_set_timer(struct mvpp2_port * port,u32 timer)1604 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
1605 {
1606 	struct mvpp2 *priv = port->priv;
1607 	void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1608 	u32 lsb, msb;
1609 
1610 	lsb = timer & MVPP22_FCA_REG_MASK;
1611 	msb = timer >> MVPP22_FCA_REG_SIZE;
1612 
1613 	writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
1614 	writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
1615 }
1616 
1617 /* Set Flow Control timer x100 faster than pause quanta to ensure that link
1618  * partner won't send traffic if port is in XOFF mode.
1619  */
mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port * port)1620 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
1621 {
1622 	u32 timer;
1623 
1624 	timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
1625 		* FC_QUANTA;
1626 
1627 	mvpp22_gop_fca_enable_periodic(port, false);
1628 
1629 	mvpp22_gop_fca_set_timer(port, timer);
1630 
1631 	mvpp22_gop_fca_enable_periodic(port, true);
1632 }
1633 
mvpp22_gop_init(struct mvpp2_port * port,phy_interface_t interface)1634 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface)
1635 {
1636 	struct mvpp2 *priv = port->priv;
1637 	u32 val;
1638 
1639 	if (!priv->sysctrl_base)
1640 		return 0;
1641 
1642 	switch (interface) {
1643 	case PHY_INTERFACE_MODE_RGMII:
1644 	case PHY_INTERFACE_MODE_RGMII_ID:
1645 	case PHY_INTERFACE_MODE_RGMII_RXID:
1646 	case PHY_INTERFACE_MODE_RGMII_TXID:
1647 		if (!mvpp2_port_supports_rgmii(port))
1648 			goto invalid_conf;
1649 		mvpp22_gop_init_rgmii(port);
1650 		break;
1651 	case PHY_INTERFACE_MODE_SGMII:
1652 	case PHY_INTERFACE_MODE_1000BASEX:
1653 	case PHY_INTERFACE_MODE_2500BASEX:
1654 		mvpp22_gop_init_sgmii(port);
1655 		break;
1656 	case PHY_INTERFACE_MODE_5GBASER:
1657 	case PHY_INTERFACE_MODE_10GBASER:
1658 		if (!mvpp2_port_supports_xlg(port))
1659 			goto invalid_conf;
1660 		mvpp22_gop_init_10gkr(port);
1661 		break;
1662 	default:
1663 		goto unsupported_conf;
1664 	}
1665 
1666 	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1667 	val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1668 	       GENCONF_PORT_CTRL1_EN(port->gop_id);
1669 	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1670 
1671 	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1672 	val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1673 	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1674 
1675 	regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1676 	val |= GENCONF_SOFT_RESET1_GOP;
1677 	regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1678 
1679 	mvpp22_gop_fca_set_periodic_timer(port);
1680 
1681 unsupported_conf:
1682 	return 0;
1683 
1684 invalid_conf:
1685 	netdev_err(port->dev, "Invalid port configuration\n");
1686 	return -EINVAL;
1687 }
1688 
mvpp22_gop_unmask_irq(struct mvpp2_port * port)1689 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1690 {
1691 	u32 val;
1692 
1693 	if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1694 	    phy_interface_mode_is_8023z(port->phy_interface) ||
1695 	    port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1696 		/* Enable the GMAC link status irq for this port */
1697 		val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1698 		val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1699 		writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1700 	}
1701 
1702 	if (mvpp2_port_supports_xlg(port)) {
1703 		/* Enable the XLG/GIG irqs for this port */
1704 		val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1705 		if (mvpp2_is_xlg(port->phy_interface))
1706 			val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1707 		else
1708 			val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1709 		writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1710 	}
1711 }
1712 
mvpp22_gop_mask_irq(struct mvpp2_port * port)1713 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1714 {
1715 	u32 val;
1716 
1717 	if (mvpp2_port_supports_xlg(port)) {
1718 		val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1719 		val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1720 			 MVPP22_XLG_EXT_INT_MASK_GIG);
1721 		writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1722 	}
1723 
1724 	if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1725 	    phy_interface_mode_is_8023z(port->phy_interface) ||
1726 	    port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1727 		val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1728 		val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1729 		writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1730 	}
1731 }
1732 
mvpp22_gop_setup_irq(struct mvpp2_port * port)1733 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1734 {
1735 	u32 val;
1736 
1737 	mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1738 		     MVPP22_GMAC_INT_SUM_MASK_PTP,
1739 		     MVPP22_GMAC_INT_SUM_MASK_PTP);
1740 
1741 	if (port->phylink ||
1742 	    phy_interface_mode_is_rgmii(port->phy_interface) ||
1743 	    phy_interface_mode_is_8023z(port->phy_interface) ||
1744 	    port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1745 		val = readl(port->base + MVPP22_GMAC_INT_MASK);
1746 		val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1747 		writel(val, port->base + MVPP22_GMAC_INT_MASK);
1748 	}
1749 
1750 	if (mvpp2_port_supports_xlg(port)) {
1751 		val = readl(port->base + MVPP22_XLG_INT_MASK);
1752 		val |= MVPP22_XLG_INT_MASK_LINK;
1753 		writel(val, port->base + MVPP22_XLG_INT_MASK);
1754 
1755 		mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1756 			     MVPP22_XLG_EXT_INT_MASK_PTP,
1757 			     MVPP22_XLG_EXT_INT_MASK_PTP);
1758 	}
1759 
1760 	mvpp22_gop_unmask_irq(port);
1761 }
1762 
1763 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1764  *
1765  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1766  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1767  * differ.
1768  *
1769  * The COMPHY configures the serdes lanes regardless of the actual use of the
1770  * lanes by the physical layer. This is why configurations like
1771  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1772  */
mvpp22_comphy_init(struct mvpp2_port * port,phy_interface_t interface)1773 static int mvpp22_comphy_init(struct mvpp2_port *port,
1774 			      phy_interface_t interface)
1775 {
1776 	int ret;
1777 
1778 	if (!port->comphy)
1779 		return 0;
1780 
1781 	ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface);
1782 	if (ret)
1783 		return ret;
1784 
1785 	return phy_power_on(port->comphy);
1786 }
1787 
mvpp2_port_enable(struct mvpp2_port * port)1788 static void mvpp2_port_enable(struct mvpp2_port *port)
1789 {
1790 	u32 val;
1791 
1792 	if (mvpp2_port_supports_xlg(port) &&
1793 	    mvpp2_is_xlg(port->phy_interface)) {
1794 		val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1795 		val |= MVPP22_XLG_CTRL0_PORT_EN;
1796 		val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1797 		writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1798 	} else {
1799 		val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1800 		val |= MVPP2_GMAC_PORT_EN_MASK;
1801 		val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1802 		writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1803 	}
1804 }
1805 
mvpp2_port_disable(struct mvpp2_port * port)1806 static void mvpp2_port_disable(struct mvpp2_port *port)
1807 {
1808 	u32 val;
1809 
1810 	if (mvpp2_port_supports_xlg(port) &&
1811 	    mvpp2_is_xlg(port->phy_interface)) {
1812 		val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1813 		val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1814 		writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1815 	}
1816 
1817 	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1818 	val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1819 	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1820 }
1821 
1822 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
mvpp2_port_periodic_xon_disable(struct mvpp2_port * port)1823 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1824 {
1825 	u32 val;
1826 
1827 	val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1828 		    ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1829 	writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1830 }
1831 
1832 /* Configure loopback port */
mvpp2_port_loopback_set(struct mvpp2_port * port,const struct phylink_link_state * state)1833 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1834 				    const struct phylink_link_state *state)
1835 {
1836 	u32 val;
1837 
1838 	val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1839 
1840 	if (state->speed == 1000)
1841 		val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1842 	else
1843 		val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1844 
1845 	if (phy_interface_mode_is_8023z(state->interface) ||
1846 	    state->interface == PHY_INTERFACE_MODE_SGMII)
1847 		val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1848 	else
1849 		val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1850 
1851 	writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1852 }
1853 
1854 enum {
1855 	ETHTOOL_XDP_REDIRECT,
1856 	ETHTOOL_XDP_PASS,
1857 	ETHTOOL_XDP_DROP,
1858 	ETHTOOL_XDP_TX,
1859 	ETHTOOL_XDP_TX_ERR,
1860 	ETHTOOL_XDP_XMIT,
1861 	ETHTOOL_XDP_XMIT_ERR,
1862 };
1863 
1864 struct mvpp2_ethtool_counter {
1865 	unsigned int offset;
1866 	const char string[ETH_GSTRING_LEN];
1867 	bool reg_is_64b;
1868 };
1869 
mvpp2_read_count(struct mvpp2_port * port,const struct mvpp2_ethtool_counter * counter)1870 static u64 mvpp2_read_count(struct mvpp2_port *port,
1871 			    const struct mvpp2_ethtool_counter *counter)
1872 {
1873 	u64 val;
1874 
1875 	val = readl(port->stats_base + counter->offset);
1876 	if (counter->reg_is_64b)
1877 		val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1878 
1879 	return val;
1880 }
1881 
1882 /* Some counters are accessed indirectly by first writing an index to
1883  * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1884  * register we access, it can be a hit counter for some classification tables,
1885  * a counter specific to a rxq, a txq or a buffer pool.
1886  */
mvpp2_read_index(struct mvpp2 * priv,u32 index,u32 reg)1887 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1888 {
1889 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1890 	return mvpp2_read(priv, reg);
1891 }
1892 
1893 /* Due to the fact that software statistics and hardware statistics are, by
1894  * design, incremented at different moments in the chain of packet processing,
1895  * it is very likely that incoming packets could have been dropped after being
1896  * counted by hardware but before reaching software statistics (most probably
1897  * multicast packets), and in the opposite way, during transmission, FCS bytes
1898  * are added in between as well as TSO skb will be split and header bytes added.
1899  * Hence, statistics gathered from userspace with ifconfig (software) and
1900  * ethtool (hardware) cannot be compared.
1901  */
1902 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1903 	{ MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1904 	{ MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1905 	{ MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1906 	{ MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1907 	{ MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1908 	{ MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1909 	{ MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1910 	{ MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1911 	{ MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1912 	{ MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1913 	{ MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1914 	{ MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1915 	{ MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1916 	{ MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1917 	{ MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1918 	{ MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1919 	{ MVPP2_MIB_FC_SENT, "fc_sent" },
1920 	{ MVPP2_MIB_FC_RCVD, "fc_received" },
1921 	{ MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1922 	{ MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1923 	{ MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1924 	{ MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1925 	{ MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1926 	{ MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1927 	{ MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1928 	{ MVPP2_MIB_COLLISION, "collision" },
1929 	{ MVPP2_MIB_LATE_COLLISION, "late_collision" },
1930 };
1931 
1932 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1933 	{ MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1934 	{ MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1935 };
1936 
1937 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1938 	{ MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1939 	{ MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1940 	{ MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1941 	{ MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1942 	{ MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1943 	{ MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1944 	{ MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1945 	{ MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1946 	{ MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1947 };
1948 
1949 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1950 	{ MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1951 	{ MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1952 	{ MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1953 	{ MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1954 };
1955 
1956 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1957 	{ ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1958 	{ ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1959 	{ ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1960 	{ ETHTOOL_XDP_TX, "rx_xdp_tx", },
1961 	{ ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1962 	{ ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1963 	{ ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1964 };
1965 
1966 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs)	(ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1967 						 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1968 						 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1969 						 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1970 						 ARRAY_SIZE(mvpp2_ethtool_xdp))
1971 
mvpp2_ethtool_get_strings(struct net_device * netdev,u32 sset,u8 * data)1972 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1973 				      u8 *data)
1974 {
1975 	struct mvpp2_port *port = netdev_priv(netdev);
1976 	int i, q;
1977 
1978 	if (sset != ETH_SS_STATS)
1979 		return;
1980 
1981 	for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1982 		strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1983 			ETH_GSTRING_LEN);
1984 		data += ETH_GSTRING_LEN;
1985 	}
1986 
1987 	for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1988 		strscpy(data, mvpp2_ethtool_port_regs[i].string,
1989 			ETH_GSTRING_LEN);
1990 		data += ETH_GSTRING_LEN;
1991 	}
1992 
1993 	for (q = 0; q < port->ntxqs; q++) {
1994 		for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1995 			snprintf(data, ETH_GSTRING_LEN,
1996 				 mvpp2_ethtool_txq_regs[i].string, q);
1997 			data += ETH_GSTRING_LEN;
1998 		}
1999 	}
2000 
2001 	for (q = 0; q < port->nrxqs; q++) {
2002 		for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
2003 			snprintf(data, ETH_GSTRING_LEN,
2004 				 mvpp2_ethtool_rxq_regs[i].string,
2005 				 q);
2006 			data += ETH_GSTRING_LEN;
2007 		}
2008 	}
2009 
2010 	for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
2011 		strscpy(data, mvpp2_ethtool_xdp[i].string,
2012 			ETH_GSTRING_LEN);
2013 		data += ETH_GSTRING_LEN;
2014 	}
2015 }
2016 
2017 static void
mvpp2_get_xdp_stats(struct mvpp2_port * port,struct mvpp2_pcpu_stats * xdp_stats)2018 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
2019 {
2020 	unsigned int start;
2021 	unsigned int cpu;
2022 
2023 	/* Gather XDP Statistics */
2024 	for_each_possible_cpu(cpu) {
2025 		struct mvpp2_pcpu_stats *cpu_stats;
2026 		u64	xdp_redirect;
2027 		u64	xdp_pass;
2028 		u64	xdp_drop;
2029 		u64	xdp_xmit;
2030 		u64	xdp_xmit_err;
2031 		u64	xdp_tx;
2032 		u64	xdp_tx_err;
2033 
2034 		cpu_stats = per_cpu_ptr(port->stats, cpu);
2035 		do {
2036 			start = u64_stats_fetch_begin(&cpu_stats->syncp);
2037 			xdp_redirect = cpu_stats->xdp_redirect;
2038 			xdp_pass   = cpu_stats->xdp_pass;
2039 			xdp_drop = cpu_stats->xdp_drop;
2040 			xdp_xmit   = cpu_stats->xdp_xmit;
2041 			xdp_xmit_err   = cpu_stats->xdp_xmit_err;
2042 			xdp_tx   = cpu_stats->xdp_tx;
2043 			xdp_tx_err   = cpu_stats->xdp_tx_err;
2044 		} while (u64_stats_fetch_retry(&cpu_stats->syncp, start));
2045 
2046 		xdp_stats->xdp_redirect += xdp_redirect;
2047 		xdp_stats->xdp_pass   += xdp_pass;
2048 		xdp_stats->xdp_drop += xdp_drop;
2049 		xdp_stats->xdp_xmit   += xdp_xmit;
2050 		xdp_stats->xdp_xmit_err   += xdp_xmit_err;
2051 		xdp_stats->xdp_tx   += xdp_tx;
2052 		xdp_stats->xdp_tx_err   += xdp_tx_err;
2053 	}
2054 }
2055 
mvpp2_read_stats(struct mvpp2_port * port)2056 static void mvpp2_read_stats(struct mvpp2_port *port)
2057 {
2058 	struct mvpp2_pcpu_stats xdp_stats = {};
2059 	const struct mvpp2_ethtool_counter *s;
2060 	u64 *pstats;
2061 	int i, q;
2062 
2063 	pstats = port->ethtool_stats;
2064 
2065 	for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
2066 		*pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
2067 
2068 	for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
2069 		*pstats++ += mvpp2_read(port->priv,
2070 					mvpp2_ethtool_port_regs[i].offset +
2071 					4 * port->id);
2072 
2073 	for (q = 0; q < port->ntxqs; q++)
2074 		for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
2075 			*pstats++ += mvpp2_read_index(port->priv,
2076 						      MVPP22_CTRS_TX_CTR(port->id, q),
2077 						      mvpp2_ethtool_txq_regs[i].offset);
2078 
2079 	/* Rxqs are numbered from 0 from the user standpoint, but not from the
2080 	 * driver's. We need to add the  port->first_rxq offset.
2081 	 */
2082 	for (q = 0; q < port->nrxqs; q++)
2083 		for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
2084 			*pstats++ += mvpp2_read_index(port->priv,
2085 						      port->first_rxq + q,
2086 						      mvpp2_ethtool_rxq_regs[i].offset);
2087 
2088 	/* Gather XDP Statistics */
2089 	mvpp2_get_xdp_stats(port, &xdp_stats);
2090 
2091 	for (i = 0, s = mvpp2_ethtool_xdp;
2092 		 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
2093 	     s++, i++) {
2094 		switch (s->offset) {
2095 		case ETHTOOL_XDP_REDIRECT:
2096 			*pstats++ = xdp_stats.xdp_redirect;
2097 			break;
2098 		case ETHTOOL_XDP_PASS:
2099 			*pstats++ = xdp_stats.xdp_pass;
2100 			break;
2101 		case ETHTOOL_XDP_DROP:
2102 			*pstats++ = xdp_stats.xdp_drop;
2103 			break;
2104 		case ETHTOOL_XDP_TX:
2105 			*pstats++ = xdp_stats.xdp_tx;
2106 			break;
2107 		case ETHTOOL_XDP_TX_ERR:
2108 			*pstats++ = xdp_stats.xdp_tx_err;
2109 			break;
2110 		case ETHTOOL_XDP_XMIT:
2111 			*pstats++ = xdp_stats.xdp_xmit;
2112 			break;
2113 		case ETHTOOL_XDP_XMIT_ERR:
2114 			*pstats++ = xdp_stats.xdp_xmit_err;
2115 			break;
2116 		}
2117 	}
2118 }
2119 
mvpp2_gather_hw_statistics(struct work_struct * work)2120 static void mvpp2_gather_hw_statistics(struct work_struct *work)
2121 {
2122 	struct delayed_work *del_work = to_delayed_work(work);
2123 	struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
2124 					       stats_work);
2125 
2126 	mutex_lock(&port->gather_stats_lock);
2127 
2128 	mvpp2_read_stats(port);
2129 
2130 	/* No need to read again the counters right after this function if it
2131 	 * was called asynchronously by the user (ie. use of ethtool).
2132 	 */
2133 	cancel_delayed_work(&port->stats_work);
2134 	queue_delayed_work(port->priv->stats_queue, &port->stats_work,
2135 			   MVPP2_MIB_COUNTERS_STATS_DELAY);
2136 
2137 	mutex_unlock(&port->gather_stats_lock);
2138 }
2139 
mvpp2_ethtool_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2140 static void mvpp2_ethtool_get_stats(struct net_device *dev,
2141 				    struct ethtool_stats *stats, u64 *data)
2142 {
2143 	struct mvpp2_port *port = netdev_priv(dev);
2144 
2145 	/* Update statistics for the given port, then take the lock to avoid
2146 	 * concurrent accesses on the ethtool_stats structure during its copy.
2147 	 */
2148 	mvpp2_gather_hw_statistics(&port->stats_work.work);
2149 
2150 	mutex_lock(&port->gather_stats_lock);
2151 	memcpy(data, port->ethtool_stats,
2152 	       sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
2153 	mutex_unlock(&port->gather_stats_lock);
2154 }
2155 
mvpp2_ethtool_get_sset_count(struct net_device * dev,int sset)2156 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
2157 {
2158 	struct mvpp2_port *port = netdev_priv(dev);
2159 
2160 	if (sset == ETH_SS_STATS)
2161 		return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
2162 
2163 	return -EOPNOTSUPP;
2164 }
2165 
mvpp2_mac_reset_assert(struct mvpp2_port * port)2166 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
2167 {
2168 	u32 val;
2169 
2170 	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
2171 	      MVPP2_GMAC_PORT_RESET_MASK;
2172 	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2173 
2174 	if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
2175 		val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
2176 		      ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
2177 		writel(val, port->base + MVPP22_XLG_CTRL0_REG);
2178 	}
2179 }
2180 
mvpp22_pcs_reset_assert(struct mvpp2_port * port)2181 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
2182 {
2183 	struct mvpp2 *priv = port->priv;
2184 	void __iomem *mpcs, *xpcs;
2185 	u32 val;
2186 
2187 	if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2188 		return;
2189 
2190 	mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2191 	xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2192 
2193 	val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2194 	val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
2195 	val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
2196 	writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2197 
2198 	val = readl(xpcs + MVPP22_XPCS_CFG0);
2199 	writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2200 }
2201 
mvpp22_pcs_reset_deassert(struct mvpp2_port * port,phy_interface_t interface)2202 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port,
2203 				      phy_interface_t interface)
2204 {
2205 	struct mvpp2 *priv = port->priv;
2206 	void __iomem *mpcs, *xpcs;
2207 	u32 val;
2208 
2209 	if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2210 		return;
2211 
2212 	mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2213 	xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2214 
2215 	switch (interface) {
2216 	case PHY_INTERFACE_MODE_5GBASER:
2217 	case PHY_INTERFACE_MODE_10GBASER:
2218 		val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2219 		val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
2220 		       MAC_CLK_RESET_SD_TX;
2221 		val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
2222 		writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2223 		break;
2224 	case PHY_INTERFACE_MODE_XAUI:
2225 	case PHY_INTERFACE_MODE_RXAUI:
2226 		val = readl(xpcs + MVPP22_XPCS_CFG0);
2227 		writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2228 		break;
2229 	default:
2230 		break;
2231 	}
2232 }
2233 
2234 /* Change maximum receive size of the port */
mvpp2_gmac_max_rx_size_set(struct mvpp2_port * port)2235 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2236 {
2237 	u32 val;
2238 
2239 	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2240 	val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2241 	val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2242 		    MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2243 	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2244 }
2245 
2246 /* Change maximum receive size of the port */
mvpp2_xlg_max_rx_size_set(struct mvpp2_port * port)2247 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
2248 {
2249 	u32 val;
2250 
2251 	val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
2252 	val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
2253 	val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2254 	       MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
2255 	writel(val, port->base + MVPP22_XLG_CTRL1_REG);
2256 }
2257 
2258 /* Set defaults to the MVPP2 port */
mvpp2_defaults_set(struct mvpp2_port * port)2259 static void mvpp2_defaults_set(struct mvpp2_port *port)
2260 {
2261 	int tx_port_num, val, queue, lrxq;
2262 
2263 	if (port->priv->hw_version == MVPP21) {
2264 		/* Update TX FIFO MIN Threshold */
2265 		val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2266 		val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2267 		/* Min. TX threshold must be less than minimal packet length */
2268 		val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2269 		writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2270 	}
2271 
2272 	/* Disable Legacy WRR, Disable EJP, Release from reset */
2273 	tx_port_num = mvpp2_egress_port(port);
2274 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2275 		    tx_port_num);
2276 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2277 
2278 	/* Set TXQ scheduling to Round-Robin */
2279 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
2280 
2281 	/* Close bandwidth for all queues */
2282 	for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
2283 		mvpp2_write(port->priv,
2284 			    MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
2285 
2286 	/* Set refill period to 1 usec, refill tokens
2287 	 * and bucket size to maximum
2288 	 */
2289 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
2290 		    port->priv->tclk / USEC_PER_SEC);
2291 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2292 	val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2293 	val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2294 	val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2295 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2296 	val = MVPP2_TXP_TOKEN_SIZE_MAX;
2297 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2298 
2299 	/* Set MaximumLowLatencyPacketSize value to 256 */
2300 	mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2301 		    MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2302 		    MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2303 
2304 	/* Enable Rx cache snoop */
2305 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2306 		queue = port->rxqs[lrxq]->id;
2307 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2308 		val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2309 			   MVPP2_SNOOP_BUF_HDR_MASK;
2310 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2311 	}
2312 
2313 	/* At default, mask all interrupts to all present cpus */
2314 	mvpp2_interrupts_disable(port);
2315 }
2316 
2317 /* Enable/disable receiving packets */
mvpp2_ingress_enable(struct mvpp2_port * port)2318 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2319 {
2320 	u32 val;
2321 	int lrxq, queue;
2322 
2323 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2324 		queue = port->rxqs[lrxq]->id;
2325 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2326 		val &= ~MVPP2_RXQ_DISABLE_MASK;
2327 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2328 	}
2329 }
2330 
mvpp2_ingress_disable(struct mvpp2_port * port)2331 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2332 {
2333 	u32 val;
2334 	int lrxq, queue;
2335 
2336 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2337 		queue = port->rxqs[lrxq]->id;
2338 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2339 		val |= MVPP2_RXQ_DISABLE_MASK;
2340 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2341 	}
2342 }
2343 
2344 /* Enable transmit via physical egress queue
2345  * - HW starts take descriptors from DRAM
2346  */
mvpp2_egress_enable(struct mvpp2_port * port)2347 static void mvpp2_egress_enable(struct mvpp2_port *port)
2348 {
2349 	u32 qmap;
2350 	int queue;
2351 	int tx_port_num = mvpp2_egress_port(port);
2352 
2353 	/* Enable all initialized TXs. */
2354 	qmap = 0;
2355 	for (queue = 0; queue < port->ntxqs; queue++) {
2356 		struct mvpp2_tx_queue *txq = port->txqs[queue];
2357 
2358 		if (txq->descs)
2359 			qmap |= (1 << queue);
2360 	}
2361 
2362 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2363 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2364 }
2365 
2366 /* Disable transmit via physical egress queue
2367  * - HW doesn't take descriptors from DRAM
2368  */
mvpp2_egress_disable(struct mvpp2_port * port)2369 static void mvpp2_egress_disable(struct mvpp2_port *port)
2370 {
2371 	u32 reg_data;
2372 	int delay;
2373 	int tx_port_num = mvpp2_egress_port(port);
2374 
2375 	/* Issue stop command for active channels only */
2376 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2377 	reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2378 		    MVPP2_TXP_SCHED_ENQ_MASK;
2379 	if (reg_data != 0)
2380 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2381 			    (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2382 
2383 	/* Wait for all Tx activity to terminate. */
2384 	delay = 0;
2385 	do {
2386 		if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2387 			netdev_warn(port->dev,
2388 				    "Tx stop timed out, status=0x%08x\n",
2389 				    reg_data);
2390 			break;
2391 		}
2392 		mdelay(1);
2393 		delay++;
2394 
2395 		/* Check port TX Command register that all
2396 		 * Tx queues are stopped
2397 		 */
2398 		reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2399 	} while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2400 }
2401 
2402 /* Rx descriptors helper methods */
2403 
2404 /* Get number of Rx descriptors occupied by received packets */
2405 static inline int
mvpp2_rxq_received(struct mvpp2_port * port,int rxq_id)2406 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2407 {
2408 	u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2409 
2410 	return val & MVPP2_RXQ_OCCUPIED_MASK;
2411 }
2412 
2413 /* Update Rx queue status with the number of occupied and available
2414  * Rx descriptor slots.
2415  */
2416 static inline void
mvpp2_rxq_status_update(struct mvpp2_port * port,int rxq_id,int used_count,int free_count)2417 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2418 			int used_count, int free_count)
2419 {
2420 	/* Decrement the number of used descriptors and increment count
2421 	 * increment the number of free descriptors.
2422 	 */
2423 	u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2424 
2425 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2426 }
2427 
2428 /* Get pointer to next RX descriptor to be processed by SW */
2429 static inline struct mvpp2_rx_desc *
mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue * rxq)2430 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2431 {
2432 	int rx_desc = rxq->next_desc_to_proc;
2433 
2434 	rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2435 	prefetch(rxq->descs + rxq->next_desc_to_proc);
2436 	return rxq->descs + rx_desc;
2437 }
2438 
2439 /* Set rx queue offset */
mvpp2_rxq_offset_set(struct mvpp2_port * port,int prxq,int offset)2440 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2441 				 int prxq, int offset)
2442 {
2443 	u32 val;
2444 
2445 	/* Convert offset from bytes to units of 32 bytes */
2446 	offset = offset >> 5;
2447 
2448 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2449 	val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2450 
2451 	/* Offset is in */
2452 	val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2453 		    MVPP2_RXQ_PACKET_OFFSET_MASK);
2454 
2455 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2456 }
2457 
2458 /* Tx descriptors helper methods */
2459 
2460 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2461 static struct mvpp2_tx_desc *
mvpp2_txq_next_desc_get(struct mvpp2_tx_queue * txq)2462 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2463 {
2464 	int tx_desc = txq->next_desc_to_proc;
2465 
2466 	txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2467 	return txq->descs + tx_desc;
2468 }
2469 
2470 /* Update HW with number of aggregated Tx descriptors to be sent
2471  *
2472  * Called only from mvpp2_tx(), so migration is disabled, using
2473  * smp_processor_id() is OK.
2474  */
mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port * port,int pending)2475 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2476 {
2477 	/* aggregated access - relevant TXQ number is written in TX desc */
2478 	mvpp2_thread_write(port->priv,
2479 			   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2480 			   MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2481 }
2482 
2483 /* Check if there are enough free descriptors in aggregated txq.
2484  * If not, update the number of occupied descriptors and repeat the check.
2485  *
2486  * Called only from mvpp2_tx(), so migration is disabled, using
2487  * smp_processor_id() is OK.
2488  */
mvpp2_aggr_desc_num_check(struct mvpp2_port * port,struct mvpp2_tx_queue * aggr_txq,int num)2489 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2490 				     struct mvpp2_tx_queue *aggr_txq, int num)
2491 {
2492 	if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2493 		/* Update number of occupied aggregated Tx descriptors */
2494 		unsigned int thread =
2495 			mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2496 		u32 val = mvpp2_read_relaxed(port->priv,
2497 					     MVPP2_AGGR_TXQ_STATUS_REG(thread));
2498 
2499 		aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2500 
2501 		if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2502 			return -ENOMEM;
2503 	}
2504 	return 0;
2505 }
2506 
2507 /* Reserved Tx descriptors allocation request
2508  *
2509  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2510  * only by mvpp2_tx(), so migration is disabled, using
2511  * smp_processor_id() is OK.
2512  */
mvpp2_txq_alloc_reserved_desc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,int num)2513 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2514 					 struct mvpp2_tx_queue *txq, int num)
2515 {
2516 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2517 	struct mvpp2 *priv = port->priv;
2518 	u32 val;
2519 
2520 	val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2521 	mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2522 
2523 	val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2524 
2525 	return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2526 }
2527 
2528 /* Check if there are enough reserved descriptors for transmission.
2529  * If not, request chunk of reserved descriptors and check again.
2530  */
mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu,int num)2531 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2532 					    struct mvpp2_tx_queue *txq,
2533 					    struct mvpp2_txq_pcpu *txq_pcpu,
2534 					    int num)
2535 {
2536 	int req, desc_count;
2537 	unsigned int thread;
2538 
2539 	if (txq_pcpu->reserved_num >= num)
2540 		return 0;
2541 
2542 	/* Not enough descriptors reserved! Update the reserved descriptor
2543 	 * count and check again.
2544 	 */
2545 
2546 	desc_count = 0;
2547 	/* Compute total of used descriptors */
2548 	for (thread = 0; thread < port->priv->nthreads; thread++) {
2549 		struct mvpp2_txq_pcpu *txq_pcpu_aux;
2550 
2551 		txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2552 		desc_count += txq_pcpu_aux->count;
2553 		desc_count += txq_pcpu_aux->reserved_num;
2554 	}
2555 
2556 	req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2557 	desc_count += req;
2558 
2559 	if (desc_count >
2560 	   (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2561 		return -ENOMEM;
2562 
2563 	txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2564 
2565 	/* OK, the descriptor could have been updated: check again. */
2566 	if (txq_pcpu->reserved_num < num)
2567 		return -ENOMEM;
2568 	return 0;
2569 }
2570 
2571 /* Release the last allocated Tx descriptor. Useful to handle DMA
2572  * mapping failures in the Tx path.
2573  */
mvpp2_txq_desc_put(struct mvpp2_tx_queue * txq)2574 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2575 {
2576 	if (txq->next_desc_to_proc == 0)
2577 		txq->next_desc_to_proc = txq->last_desc - 1;
2578 	else
2579 		txq->next_desc_to_proc--;
2580 }
2581 
2582 /* Set Tx descriptors fields relevant for CSUM calculation */
mvpp2_txq_desc_csum(int l3_offs,__be16 l3_proto,int ip_hdr_len,int l4_proto)2583 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2584 			       int ip_hdr_len, int l4_proto)
2585 {
2586 	u32 command;
2587 
2588 	/* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2589 	 * G_L4_chk, L4_type required only for checksum calculation
2590 	 */
2591 	command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2592 	command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2593 	command |= MVPP2_TXD_IP_CSUM_DISABLE;
2594 
2595 	if (l3_proto == htons(ETH_P_IP)) {
2596 		command &= ~MVPP2_TXD_IP_CSUM_DISABLE;	/* enable IPv4 csum */
2597 		command &= ~MVPP2_TXD_L3_IP6;		/* enable IPv4 */
2598 	} else {
2599 		command |= MVPP2_TXD_L3_IP6;		/* enable IPv6 */
2600 	}
2601 
2602 	if (l4_proto == IPPROTO_TCP) {
2603 		command &= ~MVPP2_TXD_L4_UDP;		/* enable TCP */
2604 		command &= ~MVPP2_TXD_L4_CSUM_FRAG;	/* generate L4 csum */
2605 	} else if (l4_proto == IPPROTO_UDP) {
2606 		command |= MVPP2_TXD_L4_UDP;		/* enable UDP */
2607 		command &= ~MVPP2_TXD_L4_CSUM_FRAG;	/* generate L4 csum */
2608 	} else {
2609 		command |= MVPP2_TXD_L4_CSUM_NOT;
2610 	}
2611 
2612 	return command;
2613 }
2614 
2615 /* Get number of sent descriptors and decrement counter.
2616  * The number of sent descriptors is returned.
2617  * Per-thread access
2618  *
2619  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2620  * (migration disabled) and from the TX completion tasklet (migration
2621  * disabled) so using smp_processor_id() is OK.
2622  */
mvpp2_txq_sent_desc_proc(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)2623 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2624 					   struct mvpp2_tx_queue *txq)
2625 {
2626 	u32 val;
2627 
2628 	/* Reading status reg resets transmitted descriptor counter */
2629 	val = mvpp2_thread_read_relaxed(port->priv,
2630 					mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2631 					MVPP2_TXQ_SENT_REG(txq->id));
2632 
2633 	return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2634 		MVPP2_TRANSMITTED_COUNT_OFFSET;
2635 }
2636 
2637 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2638  * disabled, therefore using smp_processor_id() is OK.
2639  */
mvpp2_txq_sent_counter_clear(void * arg)2640 static void mvpp2_txq_sent_counter_clear(void *arg)
2641 {
2642 	struct mvpp2_port *port = arg;
2643 	int queue;
2644 
2645 	/* If the thread isn't used, don't do anything */
2646 	if (smp_processor_id() >= port->priv->nthreads)
2647 		return;
2648 
2649 	for (queue = 0; queue < port->ntxqs; queue++) {
2650 		int id = port->txqs[queue]->id;
2651 
2652 		mvpp2_thread_read(port->priv,
2653 				  mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2654 				  MVPP2_TXQ_SENT_REG(id));
2655 	}
2656 }
2657 
2658 /* Set max sizes for Tx queues */
mvpp2_txp_max_tx_size_set(struct mvpp2_port * port)2659 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2660 {
2661 	u32	val, size, mtu;
2662 	int	txq, tx_port_num;
2663 
2664 	mtu = port->pkt_size * 8;
2665 	if (mtu > MVPP2_TXP_MTU_MAX)
2666 		mtu = MVPP2_TXP_MTU_MAX;
2667 
2668 	/* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2669 	mtu = 3 * mtu;
2670 
2671 	/* Indirect access to registers */
2672 	tx_port_num = mvpp2_egress_port(port);
2673 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2674 
2675 	/* Set MTU */
2676 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2677 	val &= ~MVPP2_TXP_MTU_MAX;
2678 	val |= mtu;
2679 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2680 
2681 	/* TXP token size and all TXQs token size must be larger that MTU */
2682 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2683 	size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2684 	if (size < mtu) {
2685 		size = mtu;
2686 		val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2687 		val |= size;
2688 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2689 	}
2690 
2691 	for (txq = 0; txq < port->ntxqs; txq++) {
2692 		val = mvpp2_read(port->priv,
2693 				 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2694 		size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2695 
2696 		if (size < mtu) {
2697 			size = mtu;
2698 			val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2699 			val |= size;
2700 			mvpp2_write(port->priv,
2701 				    MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2702 				    val);
2703 		}
2704 	}
2705 }
2706 
2707 /* Set the number of non-occupied descriptors threshold */
mvpp2_set_rxq_free_tresh(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2708 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
2709 				     struct mvpp2_rx_queue *rxq)
2710 {
2711 	u32 val;
2712 
2713 	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2714 
2715 	val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
2716 	val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
2717 	val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
2718 	mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
2719 }
2720 
2721 /* Set the number of packets that will be received before Rx interrupt
2722  * will be generated by HW.
2723  */
mvpp2_rx_pkts_coal_set(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2724 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2725 				   struct mvpp2_rx_queue *rxq)
2726 {
2727 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2728 
2729 	if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2730 		rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2731 
2732 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2733 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2734 			   rxq->pkts_coal);
2735 
2736 	put_cpu();
2737 }
2738 
2739 /* For some reason in the LSP this is done on each CPU. Why ? */
mvpp2_tx_pkts_coal_set(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)2740 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2741 				   struct mvpp2_tx_queue *txq)
2742 {
2743 	unsigned int thread;
2744 	u32 val;
2745 
2746 	if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2747 		txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2748 
2749 	val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2750 	/* PKT-coalescing registers are per-queue + per-thread */
2751 	for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2752 		mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2753 		mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2754 	}
2755 }
2756 
mvpp2_usec_to_cycles(u32 usec,unsigned long clk_hz)2757 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2758 {
2759 	u64 tmp = (u64)clk_hz * usec;
2760 
2761 	do_div(tmp, USEC_PER_SEC);
2762 
2763 	return tmp > U32_MAX ? U32_MAX : tmp;
2764 }
2765 
mvpp2_cycles_to_usec(u32 cycles,unsigned long clk_hz)2766 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2767 {
2768 	u64 tmp = (u64)cycles * USEC_PER_SEC;
2769 
2770 	do_div(tmp, clk_hz);
2771 
2772 	return tmp > U32_MAX ? U32_MAX : tmp;
2773 }
2774 
2775 /* Set the time delay in usec before Rx interrupt */
mvpp2_rx_time_coal_set(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2776 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2777 				   struct mvpp2_rx_queue *rxq)
2778 {
2779 	unsigned long freq = port->priv->tclk;
2780 	u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2781 
2782 	if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2783 		rxq->time_coal =
2784 			mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2785 
2786 		/* re-evaluate to get actual register value */
2787 		val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2788 	}
2789 
2790 	mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2791 }
2792 
mvpp2_tx_time_coal_set(struct mvpp2_port * port)2793 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2794 {
2795 	unsigned long freq = port->priv->tclk;
2796 	u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2797 
2798 	if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2799 		port->tx_time_coal =
2800 			mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2801 
2802 		/* re-evaluate to get actual register value */
2803 		val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2804 	}
2805 
2806 	mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2807 }
2808 
2809 /* Free Tx queue skbuffs */
mvpp2_txq_bufs_free(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu,int num)2810 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2811 				struct mvpp2_tx_queue *txq,
2812 				struct mvpp2_txq_pcpu *txq_pcpu, int num)
2813 {
2814 	struct xdp_frame_bulk bq;
2815 	int i;
2816 
2817 	xdp_frame_bulk_init(&bq);
2818 
2819 	rcu_read_lock(); /* need for xdp_return_frame_bulk */
2820 
2821 	for (i = 0; i < num; i++) {
2822 		struct mvpp2_txq_pcpu_buf *tx_buf =
2823 			txq_pcpu->buffs + txq_pcpu->txq_get_index;
2824 
2825 		if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2826 		    tx_buf->type != MVPP2_TYPE_XDP_TX)
2827 			dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2828 					 tx_buf->size, DMA_TO_DEVICE);
2829 		if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2830 			dev_kfree_skb_any(tx_buf->skb);
2831 		else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2832 			 tx_buf->type == MVPP2_TYPE_XDP_NDO)
2833 			xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2834 
2835 		mvpp2_txq_inc_get(txq_pcpu);
2836 	}
2837 	xdp_flush_frame_bulk(&bq);
2838 
2839 	rcu_read_unlock();
2840 }
2841 
mvpp2_get_rx_queue(struct mvpp2_port * port,u32 cause)2842 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2843 							u32 cause)
2844 {
2845 	int queue = fls(cause) - 1;
2846 
2847 	return port->rxqs[queue];
2848 }
2849 
mvpp2_get_tx_queue(struct mvpp2_port * port,u32 cause)2850 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2851 							u32 cause)
2852 {
2853 	int queue = fls(cause) - 1;
2854 
2855 	return port->txqs[queue];
2856 }
2857 
2858 /* Handle end of transmission */
mvpp2_txq_done(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_txq_pcpu * txq_pcpu)2859 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2860 			   struct mvpp2_txq_pcpu *txq_pcpu)
2861 {
2862 	struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2863 	int tx_done;
2864 
2865 	if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2866 		netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2867 
2868 	tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2869 	if (!tx_done)
2870 		return;
2871 	mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2872 
2873 	txq_pcpu->count -= tx_done;
2874 
2875 	if (netif_tx_queue_stopped(nq))
2876 		if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2877 			netif_tx_wake_queue(nq);
2878 }
2879 
mvpp2_tx_done(struct mvpp2_port * port,u32 cause,unsigned int thread)2880 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2881 				  unsigned int thread)
2882 {
2883 	struct mvpp2_tx_queue *txq;
2884 	struct mvpp2_txq_pcpu *txq_pcpu;
2885 	unsigned int tx_todo = 0;
2886 
2887 	while (cause) {
2888 		txq = mvpp2_get_tx_queue(port, cause);
2889 		if (!txq)
2890 			break;
2891 
2892 		txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2893 
2894 		if (txq_pcpu->count) {
2895 			mvpp2_txq_done(port, txq, txq_pcpu);
2896 			tx_todo += txq_pcpu->count;
2897 		}
2898 
2899 		cause &= ~(1 << txq->log_id);
2900 	}
2901 	return tx_todo;
2902 }
2903 
2904 /* Rx/Tx queue initialization/cleanup methods */
2905 
2906 /* Allocate and initialize descriptors for aggr TXQ */
mvpp2_aggr_txq_init(struct platform_device * pdev,struct mvpp2_tx_queue * aggr_txq,unsigned int thread,struct mvpp2 * priv)2907 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2908 			       struct mvpp2_tx_queue *aggr_txq,
2909 			       unsigned int thread, struct mvpp2 *priv)
2910 {
2911 	u32 txq_dma;
2912 
2913 	/* Allocate memory for TX descriptors */
2914 	aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2915 					     MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2916 					     &aggr_txq->descs_dma, GFP_KERNEL);
2917 	if (!aggr_txq->descs)
2918 		return -ENOMEM;
2919 
2920 	aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2921 
2922 	/* Aggr TXQ no reset WA */
2923 	aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2924 						 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2925 
2926 	/* Set Tx descriptors queue starting address indirect
2927 	 * access
2928 	 */
2929 	if (priv->hw_version == MVPP21)
2930 		txq_dma = aggr_txq->descs_dma;
2931 	else
2932 		txq_dma = aggr_txq->descs_dma >>
2933 			MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2934 
2935 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2936 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2937 		    MVPP2_AGGR_TXQ_SIZE);
2938 
2939 	return 0;
2940 }
2941 
2942 /* Create a specified Rx queue */
mvpp2_rxq_init(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)2943 static int mvpp2_rxq_init(struct mvpp2_port *port,
2944 			  struct mvpp2_rx_queue *rxq)
2945 {
2946 	struct mvpp2 *priv = port->priv;
2947 	unsigned int thread;
2948 	u32 rxq_dma;
2949 	int err;
2950 
2951 	rxq->size = port->rx_ring_size;
2952 
2953 	/* Allocate memory for RX descriptors */
2954 	rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2955 					rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2956 					&rxq->descs_dma, GFP_KERNEL);
2957 	if (!rxq->descs)
2958 		return -ENOMEM;
2959 
2960 	rxq->last_desc = rxq->size - 1;
2961 
2962 	/* Zero occupied and non-occupied counters - direct access */
2963 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2964 
2965 	/* Set Rx descriptors queue starting address - indirect access */
2966 	thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2967 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2968 	if (port->priv->hw_version == MVPP21)
2969 		rxq_dma = rxq->descs_dma;
2970 	else
2971 		rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2972 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2973 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2974 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2975 	put_cpu();
2976 
2977 	/* Set Offset */
2978 	mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2979 
2980 	/* Set coalescing pkts and time */
2981 	mvpp2_rx_pkts_coal_set(port, rxq);
2982 	mvpp2_rx_time_coal_set(port, rxq);
2983 
2984 	/* Set the number of non occupied descriptors threshold */
2985 	mvpp2_set_rxq_free_tresh(port, rxq);
2986 
2987 	/* Add number of descriptors ready for receiving packets */
2988 	mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2989 
2990 	if (priv->percpu_pools) {
2991 		err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0);
2992 		if (err < 0)
2993 			goto err_free_dma;
2994 
2995 		err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0);
2996 		if (err < 0)
2997 			goto err_unregister_rxq_short;
2998 
2999 		/* Every RXQ has a pool for short and another for long packets */
3000 		err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
3001 						 MEM_TYPE_PAGE_POOL,
3002 						 priv->page_pool[rxq->logic_rxq]);
3003 		if (err < 0)
3004 			goto err_unregister_rxq_long;
3005 
3006 		err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
3007 						 MEM_TYPE_PAGE_POOL,
3008 						 priv->page_pool[rxq->logic_rxq +
3009 								 port->nrxqs]);
3010 		if (err < 0)
3011 			goto err_unregister_mem_rxq_short;
3012 	}
3013 
3014 	return 0;
3015 
3016 err_unregister_mem_rxq_short:
3017 	xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
3018 err_unregister_rxq_long:
3019 	xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3020 err_unregister_rxq_short:
3021 	xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3022 err_free_dma:
3023 	dma_free_coherent(port->dev->dev.parent,
3024 			  rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3025 			  rxq->descs, rxq->descs_dma);
3026 	return err;
3027 }
3028 
3029 /* Push packets received by the RXQ to BM pool */
mvpp2_rxq_drop_pkts(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)3030 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3031 				struct mvpp2_rx_queue *rxq)
3032 {
3033 	int rx_received, i;
3034 
3035 	rx_received = mvpp2_rxq_received(port, rxq->id);
3036 	if (!rx_received)
3037 		return;
3038 
3039 	for (i = 0; i < rx_received; i++) {
3040 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3041 		u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3042 		int pool;
3043 
3044 		pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3045 			MVPP2_RXD_BM_POOL_ID_OFFS;
3046 
3047 		mvpp2_bm_pool_put(port, pool,
3048 				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3049 				  mvpp2_rxdesc_cookie_get(port, rx_desc));
3050 	}
3051 	mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3052 }
3053 
3054 /* Cleanup Rx queue */
mvpp2_rxq_deinit(struct mvpp2_port * port,struct mvpp2_rx_queue * rxq)3055 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3056 			     struct mvpp2_rx_queue *rxq)
3057 {
3058 	unsigned int thread;
3059 
3060 	if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
3061 		xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3062 
3063 	if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
3064 		xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3065 
3066 	mvpp2_rxq_drop_pkts(port, rxq);
3067 
3068 	if (rxq->descs)
3069 		dma_free_coherent(port->dev->dev.parent,
3070 				  rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3071 				  rxq->descs,
3072 				  rxq->descs_dma);
3073 
3074 	rxq->descs             = NULL;
3075 	rxq->last_desc         = 0;
3076 	rxq->next_desc_to_proc = 0;
3077 	rxq->descs_dma         = 0;
3078 
3079 	/* Clear Rx descriptors queue starting address and size;
3080 	 * free descriptor number
3081 	 */
3082 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3083 	thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3084 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
3085 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
3086 	mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
3087 	put_cpu();
3088 }
3089 
3090 /* Create and initialize a Tx queue */
mvpp2_txq_init(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3091 static int mvpp2_txq_init(struct mvpp2_port *port,
3092 			  struct mvpp2_tx_queue *txq)
3093 {
3094 	u32 val;
3095 	unsigned int thread;
3096 	int desc, desc_per_txq, tx_port_num;
3097 	struct mvpp2_txq_pcpu *txq_pcpu;
3098 
3099 	txq->size = port->tx_ring_size;
3100 
3101 	/* Allocate memory for Tx descriptors */
3102 	txq->descs = dma_alloc_coherent(port->dev->dev.parent,
3103 				txq->size * MVPP2_DESC_ALIGNED_SIZE,
3104 				&txq->descs_dma, GFP_KERNEL);
3105 	if (!txq->descs)
3106 		return -ENOMEM;
3107 
3108 	txq->last_desc = txq->size - 1;
3109 
3110 	/* Set Tx descriptors queue starting address - indirect access */
3111 	thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3112 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3113 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
3114 			   txq->descs_dma);
3115 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
3116 			   txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
3117 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
3118 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
3119 			   txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3120 	val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3121 	val &= ~MVPP2_TXQ_PENDING_MASK;
3122 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3123 
3124 	/* Calculate base address in prefetch buffer. We reserve 16 descriptors
3125 	 * for each existing TXQ.
3126 	 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3127 	 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3128 	 */
3129 	desc_per_txq = 16;
3130 	desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3131 	       (txq->log_id * desc_per_txq);
3132 
3133 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
3134 			   MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3135 			   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3136 	put_cpu();
3137 
3138 	/* WRR / EJP configuration - indirect access */
3139 	tx_port_num = mvpp2_egress_port(port);
3140 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3141 
3142 	val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3143 	val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3144 	val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3145 	val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3146 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3147 
3148 	val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3149 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3150 		    val);
3151 
3152 	for (thread = 0; thread < port->priv->nthreads; thread++) {
3153 		txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3154 		txq_pcpu->size = txq->size;
3155 		txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
3156 						sizeof(*txq_pcpu->buffs),
3157 						GFP_KERNEL);
3158 		if (!txq_pcpu->buffs)
3159 			return -ENOMEM;
3160 
3161 		txq_pcpu->count = 0;
3162 		txq_pcpu->reserved_num = 0;
3163 		txq_pcpu->txq_put_index = 0;
3164 		txq_pcpu->txq_get_index = 0;
3165 		txq_pcpu->tso_headers = NULL;
3166 
3167 		txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
3168 		txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
3169 
3170 		txq_pcpu->tso_headers =
3171 			dma_alloc_coherent(port->dev->dev.parent,
3172 					   txq_pcpu->size * TSO_HEADER_SIZE,
3173 					   &txq_pcpu->tso_headers_dma,
3174 					   GFP_KERNEL);
3175 		if (!txq_pcpu->tso_headers)
3176 			return -ENOMEM;
3177 	}
3178 
3179 	return 0;
3180 }
3181 
3182 /* Free allocated TXQ resources */
mvpp2_txq_deinit(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3183 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3184 			     struct mvpp2_tx_queue *txq)
3185 {
3186 	struct mvpp2_txq_pcpu *txq_pcpu;
3187 	unsigned int thread;
3188 
3189 	for (thread = 0; thread < port->priv->nthreads; thread++) {
3190 		txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3191 		kfree(txq_pcpu->buffs);
3192 
3193 		if (txq_pcpu->tso_headers)
3194 			dma_free_coherent(port->dev->dev.parent,
3195 					  txq_pcpu->size * TSO_HEADER_SIZE,
3196 					  txq_pcpu->tso_headers,
3197 					  txq_pcpu->tso_headers_dma);
3198 
3199 		txq_pcpu->tso_headers = NULL;
3200 	}
3201 
3202 	if (txq->descs)
3203 		dma_free_coherent(port->dev->dev.parent,
3204 				  txq->size * MVPP2_DESC_ALIGNED_SIZE,
3205 				  txq->descs, txq->descs_dma);
3206 
3207 	txq->descs             = NULL;
3208 	txq->last_desc         = 0;
3209 	txq->next_desc_to_proc = 0;
3210 	txq->descs_dma         = 0;
3211 
3212 	/* Set minimum bandwidth for disabled TXQs */
3213 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3214 
3215 	/* Set Tx descriptors queue starting address and size */
3216 	thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3217 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3218 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
3219 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
3220 	put_cpu();
3221 }
3222 
3223 /* Cleanup Tx ports */
mvpp2_txq_clean(struct mvpp2_port * port,struct mvpp2_tx_queue * txq)3224 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3225 {
3226 	struct mvpp2_txq_pcpu *txq_pcpu;
3227 	int delay, pending;
3228 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3229 	u32 val;
3230 
3231 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3232 	val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3233 	val |= MVPP2_TXQ_DRAIN_EN_MASK;
3234 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3235 
3236 	/* The napi queue has been stopped so wait for all packets
3237 	 * to be transmitted.
3238 	 */
3239 	delay = 0;
3240 	do {
3241 		if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3242 			netdev_warn(port->dev,
3243 				    "port %d: cleaning queue %d timed out\n",
3244 				    port->id, txq->log_id);
3245 			break;
3246 		}
3247 		mdelay(1);
3248 		delay++;
3249 
3250 		pending = mvpp2_thread_read(port->priv, thread,
3251 					    MVPP2_TXQ_PENDING_REG);
3252 		pending &= MVPP2_TXQ_PENDING_MASK;
3253 	} while (pending);
3254 
3255 	val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3256 	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3257 	put_cpu();
3258 
3259 	for (thread = 0; thread < port->priv->nthreads; thread++) {
3260 		txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3261 
3262 		/* Release all packets */
3263 		mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3264 
3265 		/* Reset queue */
3266 		txq_pcpu->count = 0;
3267 		txq_pcpu->txq_put_index = 0;
3268 		txq_pcpu->txq_get_index = 0;
3269 	}
3270 }
3271 
3272 /* Cleanup all Tx queues */
mvpp2_cleanup_txqs(struct mvpp2_port * port)3273 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3274 {
3275 	struct mvpp2_tx_queue *txq;
3276 	int queue;
3277 	u32 val;
3278 
3279 	val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3280 
3281 	/* Reset Tx ports and delete Tx queues */
3282 	val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3283 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3284 
3285 	for (queue = 0; queue < port->ntxqs; queue++) {
3286 		txq = port->txqs[queue];
3287 		mvpp2_txq_clean(port, txq);
3288 		mvpp2_txq_deinit(port, txq);
3289 	}
3290 
3291 	on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3292 
3293 	val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3294 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3295 }
3296 
3297 /* Cleanup all Rx queues */
mvpp2_cleanup_rxqs(struct mvpp2_port * port)3298 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3299 {
3300 	int queue;
3301 
3302 	for (queue = 0; queue < port->nrxqs; queue++)
3303 		mvpp2_rxq_deinit(port, port->rxqs[queue]);
3304 
3305 	if (port->tx_fc)
3306 		mvpp2_rxq_disable_fc(port);
3307 }
3308 
3309 /* Init all Rx queues for port */
mvpp2_setup_rxqs(struct mvpp2_port * port)3310 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3311 {
3312 	int queue, err;
3313 
3314 	for (queue = 0; queue < port->nrxqs; queue++) {
3315 		err = mvpp2_rxq_init(port, port->rxqs[queue]);
3316 		if (err)
3317 			goto err_cleanup;
3318 	}
3319 
3320 	if (port->tx_fc)
3321 		mvpp2_rxq_enable_fc(port);
3322 
3323 	return 0;
3324 
3325 err_cleanup:
3326 	mvpp2_cleanup_rxqs(port);
3327 	return err;
3328 }
3329 
3330 /* Init all tx queues for port */
mvpp2_setup_txqs(struct mvpp2_port * port)3331 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3332 {
3333 	struct mvpp2_tx_queue *txq;
3334 	int queue, err;
3335 
3336 	for (queue = 0; queue < port->ntxqs; queue++) {
3337 		txq = port->txqs[queue];
3338 		err = mvpp2_txq_init(port, txq);
3339 		if (err)
3340 			goto err_cleanup;
3341 
3342 		/* Assign this queue to a CPU */
3343 		if (queue < num_possible_cpus())
3344 			netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
3345 	}
3346 
3347 	if (port->has_tx_irqs) {
3348 		mvpp2_tx_time_coal_set(port);
3349 		for (queue = 0; queue < port->ntxqs; queue++) {
3350 			txq = port->txqs[queue];
3351 			mvpp2_tx_pkts_coal_set(port, txq);
3352 		}
3353 	}
3354 
3355 	on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3356 	return 0;
3357 
3358 err_cleanup:
3359 	mvpp2_cleanup_txqs(port);
3360 	return err;
3361 }
3362 
3363 /* The callback for per-port interrupt */
mvpp2_isr(int irq,void * dev_id)3364 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
3365 {
3366 	struct mvpp2_queue_vector *qv = dev_id;
3367 
3368 	mvpp2_qvec_interrupt_disable(qv);
3369 
3370 	napi_schedule(&qv->napi);
3371 
3372 	return IRQ_HANDLED;
3373 }
3374 
mvpp2_isr_handle_ptp_queue(struct mvpp2_port * port,int nq)3375 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
3376 {
3377 	struct skb_shared_hwtstamps shhwtstamps;
3378 	struct mvpp2_hwtstamp_queue *queue;
3379 	struct sk_buff *skb;
3380 	void __iomem *ptp_q;
3381 	unsigned int id;
3382 	u32 r0, r1, r2;
3383 
3384 	ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3385 	if (nq)
3386 		ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3387 
3388 	queue = &port->tx_hwtstamp_queue[nq];
3389 
3390 	while (1) {
3391 		r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3392 		if (!r0)
3393 			break;
3394 
3395 		r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3396 		r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3397 
3398 		id = (r0 >> 1) & 31;
3399 
3400 		skb = queue->skb[id];
3401 		queue->skb[id] = NULL;
3402 		if (skb) {
3403 			u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3404 
3405 			mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3406 			skb_tstamp_tx(skb, &shhwtstamps);
3407 			dev_kfree_skb_any(skb);
3408 		}
3409 	}
3410 }
3411 
mvpp2_isr_handle_ptp(struct mvpp2_port * port)3412 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3413 {
3414 	void __iomem *ptp;
3415 	u32 val;
3416 
3417 	ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3418 	val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3419 	if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3420 		mvpp2_isr_handle_ptp_queue(port, 0);
3421 	if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3422 		mvpp2_isr_handle_ptp_queue(port, 1);
3423 }
3424 
mvpp2_isr_handle_link(struct mvpp2_port * port,bool link)3425 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3426 {
3427 	struct net_device *dev = port->dev;
3428 
3429 	if (port->phylink) {
3430 		phylink_mac_change(port->phylink, link);
3431 		return;
3432 	}
3433 
3434 	if (!netif_running(dev))
3435 		return;
3436 
3437 	if (link) {
3438 		mvpp2_interrupts_enable(port);
3439 
3440 		mvpp2_egress_enable(port);
3441 		mvpp2_ingress_enable(port);
3442 		netif_carrier_on(dev);
3443 		netif_tx_wake_all_queues(dev);
3444 	} else {
3445 		netif_tx_stop_all_queues(dev);
3446 		netif_carrier_off(dev);
3447 		mvpp2_ingress_disable(port);
3448 		mvpp2_egress_disable(port);
3449 
3450 		mvpp2_interrupts_disable(port);
3451 	}
3452 }
3453 
mvpp2_isr_handle_xlg(struct mvpp2_port * port)3454 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3455 {
3456 	bool link;
3457 	u32 val;
3458 
3459 	val = readl(port->base + MVPP22_XLG_INT_STAT);
3460 	if (val & MVPP22_XLG_INT_STAT_LINK) {
3461 		val = readl(port->base + MVPP22_XLG_STATUS);
3462 		link = (val & MVPP22_XLG_STATUS_LINK_UP);
3463 		mvpp2_isr_handle_link(port, link);
3464 	}
3465 }
3466 
mvpp2_isr_handle_gmac_internal(struct mvpp2_port * port)3467 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3468 {
3469 	bool link;
3470 	u32 val;
3471 
3472 	if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3473 	    phy_interface_mode_is_8023z(port->phy_interface) ||
3474 	    port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3475 		val = readl(port->base + MVPP22_GMAC_INT_STAT);
3476 		if (val & MVPP22_GMAC_INT_STAT_LINK) {
3477 			val = readl(port->base + MVPP2_GMAC_STATUS0);
3478 			link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3479 			mvpp2_isr_handle_link(port, link);
3480 		}
3481 	}
3482 }
3483 
3484 /* Per-port interrupt for link status changes */
mvpp2_port_isr(int irq,void * dev_id)3485 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3486 {
3487 	struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3488 	u32 val;
3489 
3490 	mvpp22_gop_mask_irq(port);
3491 
3492 	if (mvpp2_port_supports_xlg(port) &&
3493 	    mvpp2_is_xlg(port->phy_interface)) {
3494 		/* Check the external status register */
3495 		val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3496 		if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3497 			mvpp2_isr_handle_xlg(port);
3498 		if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3499 			mvpp2_isr_handle_ptp(port);
3500 	} else {
3501 		/* If it's not the XLG, we must be using the GMAC.
3502 		 * Check the summary status.
3503 		 */
3504 		val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3505 		if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3506 			mvpp2_isr_handle_gmac_internal(port);
3507 		if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3508 			mvpp2_isr_handle_ptp(port);
3509 	}
3510 
3511 	mvpp22_gop_unmask_irq(port);
3512 	return IRQ_HANDLED;
3513 }
3514 
mvpp2_hr_timer_cb(struct hrtimer * timer)3515 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3516 {
3517 	struct net_device *dev;
3518 	struct mvpp2_port *port;
3519 	struct mvpp2_port_pcpu *port_pcpu;
3520 	unsigned int tx_todo, cause;
3521 
3522 	port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3523 	dev = port_pcpu->dev;
3524 
3525 	if (!netif_running(dev))
3526 		return HRTIMER_NORESTART;
3527 
3528 	port_pcpu->timer_scheduled = false;
3529 	port = netdev_priv(dev);
3530 
3531 	/* Process all the Tx queues */
3532 	cause = (1 << port->ntxqs) - 1;
3533 	tx_todo = mvpp2_tx_done(port, cause,
3534 				mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3535 
3536 	/* Set the timer in case not all the packets were processed */
3537 	if (tx_todo && !port_pcpu->timer_scheduled) {
3538 		port_pcpu->timer_scheduled = true;
3539 		hrtimer_forward_now(&port_pcpu->tx_done_timer,
3540 				    MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3541 
3542 		return HRTIMER_RESTART;
3543 	}
3544 	return HRTIMER_NORESTART;
3545 }
3546 
3547 /* Main RX/TX processing routines */
3548 
3549 /* Display more error info */
mvpp2_rx_error(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc)3550 static void mvpp2_rx_error(struct mvpp2_port *port,
3551 			   struct mvpp2_rx_desc *rx_desc)
3552 {
3553 	u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3554 	size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3555 	char *err_str = NULL;
3556 
3557 	switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3558 	case MVPP2_RXD_ERR_CRC:
3559 		err_str = "crc";
3560 		break;
3561 	case MVPP2_RXD_ERR_OVERRUN:
3562 		err_str = "overrun";
3563 		break;
3564 	case MVPP2_RXD_ERR_RESOURCE:
3565 		err_str = "resource";
3566 		break;
3567 	}
3568 	if (err_str && net_ratelimit())
3569 		netdev_err(port->dev,
3570 			   "bad rx status %08x (%s error), size=%zu\n",
3571 			   status, err_str, sz);
3572 }
3573 
3574 /* Handle RX checksum offload */
mvpp2_rx_csum(struct mvpp2_port * port,u32 status)3575 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status)
3576 {
3577 	if (((status & MVPP2_RXD_L3_IP4) &&
3578 	     !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3579 	    (status & MVPP2_RXD_L3_IP6))
3580 		if (((status & MVPP2_RXD_L4_UDP) ||
3581 		     (status & MVPP2_RXD_L4_TCP)) &&
3582 		     (status & MVPP2_RXD_L4_CSUM_OK))
3583 			return CHECKSUM_UNNECESSARY;
3584 
3585 	return CHECKSUM_NONE;
3586 }
3587 
3588 /* Allocate a new skb and add it to BM pool */
mvpp2_rx_refill(struct mvpp2_port * port,struct mvpp2_bm_pool * bm_pool,struct page_pool * page_pool,int pool)3589 static int mvpp2_rx_refill(struct mvpp2_port *port,
3590 			   struct mvpp2_bm_pool *bm_pool,
3591 			   struct page_pool *page_pool, int pool)
3592 {
3593 	dma_addr_t dma_addr;
3594 	phys_addr_t phys_addr;
3595 	void *buf;
3596 
3597 	buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3598 			      &dma_addr, &phys_addr, GFP_ATOMIC);
3599 	if (!buf)
3600 		return -ENOMEM;
3601 
3602 	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3603 
3604 	return 0;
3605 }
3606 
3607 /* Handle tx checksum */
mvpp2_skb_tx_csum(struct mvpp2_port * port,struct sk_buff * skb)3608 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3609 {
3610 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
3611 		int ip_hdr_len = 0;
3612 		u8 l4_proto;
3613 		__be16 l3_proto = vlan_get_protocol(skb);
3614 
3615 		if (l3_proto == htons(ETH_P_IP)) {
3616 			struct iphdr *ip4h = ip_hdr(skb);
3617 
3618 			/* Calculate IPv4 checksum and L4 checksum */
3619 			ip_hdr_len = ip4h->ihl;
3620 			l4_proto = ip4h->protocol;
3621 		} else if (l3_proto == htons(ETH_P_IPV6)) {
3622 			struct ipv6hdr *ip6h = ipv6_hdr(skb);
3623 
3624 			/* Read l4_protocol from one of IPv6 extra headers */
3625 			if (skb_network_header_len(skb) > 0)
3626 				ip_hdr_len = (skb_network_header_len(skb) >> 2);
3627 			l4_proto = ip6h->nexthdr;
3628 		} else {
3629 			return MVPP2_TXD_L4_CSUM_NOT;
3630 		}
3631 
3632 		return mvpp2_txq_desc_csum(skb_network_offset(skb),
3633 					   l3_proto, ip_hdr_len, l4_proto);
3634 	}
3635 
3636 	return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3637 }
3638 
mvpp2_xdp_finish_tx(struct mvpp2_port * port,u16 txq_id,int nxmit,int nxmit_byte)3639 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3640 {
3641 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3642 	struct mvpp2_tx_queue *aggr_txq;
3643 	struct mvpp2_txq_pcpu *txq_pcpu;
3644 	struct mvpp2_tx_queue *txq;
3645 	struct netdev_queue *nq;
3646 
3647 	txq = port->txqs[txq_id];
3648 	txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3649 	nq = netdev_get_tx_queue(port->dev, txq_id);
3650 	aggr_txq = &port->priv->aggr_txqs[thread];
3651 
3652 	txq_pcpu->reserved_num -= nxmit;
3653 	txq_pcpu->count += nxmit;
3654 	aggr_txq->count += nxmit;
3655 
3656 	/* Enable transmit */
3657 	wmb();
3658 	mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3659 
3660 	if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3661 		netif_tx_stop_queue(nq);
3662 
3663 	/* Finalize TX processing */
3664 	if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3665 		mvpp2_txq_done(port, txq, txq_pcpu);
3666 }
3667 
3668 static int
mvpp2_xdp_submit_frame(struct mvpp2_port * port,u16 txq_id,struct xdp_frame * xdpf,bool dma_map)3669 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3670 		       struct xdp_frame *xdpf, bool dma_map)
3671 {
3672 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3673 	u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3674 		     MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3675 	enum mvpp2_tx_buf_type buf_type;
3676 	struct mvpp2_txq_pcpu *txq_pcpu;
3677 	struct mvpp2_tx_queue *aggr_txq;
3678 	struct mvpp2_tx_desc *tx_desc;
3679 	struct mvpp2_tx_queue *txq;
3680 	int ret = MVPP2_XDP_TX;
3681 	dma_addr_t dma_addr;
3682 
3683 	txq = port->txqs[txq_id];
3684 	txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3685 	aggr_txq = &port->priv->aggr_txqs[thread];
3686 
3687 	/* Check number of available descriptors */
3688 	if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3689 	    mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3690 		ret = MVPP2_XDP_DROPPED;
3691 		goto out;
3692 	}
3693 
3694 	/* Get a descriptor for the first part of the packet */
3695 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3696 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3697 	mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3698 
3699 	if (dma_map) {
3700 		/* XDP_REDIRECT or AF_XDP */
3701 		dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3702 					  xdpf->len, DMA_TO_DEVICE);
3703 
3704 		if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3705 			mvpp2_txq_desc_put(txq);
3706 			ret = MVPP2_XDP_DROPPED;
3707 			goto out;
3708 		}
3709 
3710 		buf_type = MVPP2_TYPE_XDP_NDO;
3711 	} else {
3712 		/* XDP_TX */
3713 		struct page *page = virt_to_page(xdpf->data);
3714 
3715 		dma_addr = page_pool_get_dma_addr(page) +
3716 			   sizeof(*xdpf) + xdpf->headroom;
3717 		dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3718 					   xdpf->len, DMA_BIDIRECTIONAL);
3719 
3720 		buf_type = MVPP2_TYPE_XDP_TX;
3721 	}
3722 
3723 	mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3724 
3725 	mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3726 	mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3727 
3728 out:
3729 	return ret;
3730 }
3731 
3732 static int
mvpp2_xdp_xmit_back(struct mvpp2_port * port,struct xdp_buff * xdp)3733 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3734 {
3735 	struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3736 	struct xdp_frame *xdpf;
3737 	u16 txq_id;
3738 	int ret;
3739 
3740 	xdpf = xdp_convert_buff_to_frame(xdp);
3741 	if (unlikely(!xdpf))
3742 		return MVPP2_XDP_DROPPED;
3743 
3744 	/* The first of the TX queues are used for XPS,
3745 	 * the second half for XDP_TX
3746 	 */
3747 	txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3748 
3749 	ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3750 	if (ret == MVPP2_XDP_TX) {
3751 		u64_stats_update_begin(&stats->syncp);
3752 		stats->tx_bytes += xdpf->len;
3753 		stats->tx_packets++;
3754 		stats->xdp_tx++;
3755 		u64_stats_update_end(&stats->syncp);
3756 
3757 		mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3758 	} else {
3759 		u64_stats_update_begin(&stats->syncp);
3760 		stats->xdp_tx_err++;
3761 		u64_stats_update_end(&stats->syncp);
3762 	}
3763 
3764 	return ret;
3765 }
3766 
3767 static int
mvpp2_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)3768 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3769 	       struct xdp_frame **frames, u32 flags)
3770 {
3771 	struct mvpp2_port *port = netdev_priv(dev);
3772 	int i, nxmit_byte = 0, nxmit = 0;
3773 	struct mvpp2_pcpu_stats *stats;
3774 	u16 txq_id;
3775 	u32 ret;
3776 
3777 	if (unlikely(test_bit(0, &port->state)))
3778 		return -ENETDOWN;
3779 
3780 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3781 		return -EINVAL;
3782 
3783 	/* The first of the TX queues are used for XPS,
3784 	 * the second half for XDP_TX
3785 	 */
3786 	txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3787 
3788 	for (i = 0; i < num_frame; i++) {
3789 		ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3790 		if (ret != MVPP2_XDP_TX)
3791 			break;
3792 
3793 		nxmit_byte += frames[i]->len;
3794 		nxmit++;
3795 	}
3796 
3797 	if (likely(nxmit > 0))
3798 		mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3799 
3800 	stats = this_cpu_ptr(port->stats);
3801 	u64_stats_update_begin(&stats->syncp);
3802 	stats->tx_bytes += nxmit_byte;
3803 	stats->tx_packets += nxmit;
3804 	stats->xdp_xmit += nxmit;
3805 	stats->xdp_xmit_err += num_frame - nxmit;
3806 	u64_stats_update_end(&stats->syncp);
3807 
3808 	return nxmit;
3809 }
3810 
3811 static int
mvpp2_run_xdp(struct mvpp2_port * port,struct bpf_prog * prog,struct xdp_buff * xdp,struct page_pool * pp,struct mvpp2_pcpu_stats * stats)3812 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog,
3813 	      struct xdp_buff *xdp, struct page_pool *pp,
3814 	      struct mvpp2_pcpu_stats *stats)
3815 {
3816 	unsigned int len, sync, err;
3817 	struct page *page;
3818 	u32 ret, act;
3819 
3820 	len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3821 	act = bpf_prog_run_xdp(prog, xdp);
3822 
3823 	/* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3824 	sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3825 	sync = max(sync, len);
3826 
3827 	switch (act) {
3828 	case XDP_PASS:
3829 		stats->xdp_pass++;
3830 		ret = MVPP2_XDP_PASS;
3831 		break;
3832 	case XDP_REDIRECT:
3833 		err = xdp_do_redirect(port->dev, xdp, prog);
3834 		if (unlikely(err)) {
3835 			ret = MVPP2_XDP_DROPPED;
3836 			page = virt_to_head_page(xdp->data);
3837 			page_pool_put_page(pp, page, sync, true);
3838 		} else {
3839 			ret = MVPP2_XDP_REDIR;
3840 			stats->xdp_redirect++;
3841 		}
3842 		break;
3843 	case XDP_TX:
3844 		ret = mvpp2_xdp_xmit_back(port, xdp);
3845 		if (ret != MVPP2_XDP_TX) {
3846 			page = virt_to_head_page(xdp->data);
3847 			page_pool_put_page(pp, page, sync, true);
3848 		}
3849 		break;
3850 	default:
3851 		bpf_warn_invalid_xdp_action(port->dev, prog, act);
3852 		fallthrough;
3853 	case XDP_ABORTED:
3854 		trace_xdp_exception(port->dev, prog, act);
3855 		fallthrough;
3856 	case XDP_DROP:
3857 		page = virt_to_head_page(xdp->data);
3858 		page_pool_put_page(pp, page, sync, true);
3859 		ret = MVPP2_XDP_DROPPED;
3860 		stats->xdp_drop++;
3861 		break;
3862 	}
3863 
3864 	return ret;
3865 }
3866 
mvpp2_buff_hdr_pool_put(struct mvpp2_port * port,struct mvpp2_rx_desc * rx_desc,int pool,u32 rx_status)3867 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc,
3868 				    int pool, u32 rx_status)
3869 {
3870 	phys_addr_t phys_addr, phys_addr_next;
3871 	dma_addr_t dma_addr, dma_addr_next;
3872 	struct mvpp2_buff_hdr *buff_hdr;
3873 
3874 	phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3875 	dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3876 
3877 	do {
3878 		buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr);
3879 
3880 		phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr);
3881 		dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr);
3882 
3883 		if (port->priv->hw_version >= MVPP22) {
3884 			phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32);
3885 			dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32);
3886 		}
3887 
3888 		mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3889 
3890 		phys_addr = phys_addr_next;
3891 		dma_addr = dma_addr_next;
3892 
3893 	} while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info)));
3894 }
3895 
3896 /* Main rx processing */
mvpp2_rx(struct mvpp2_port * port,struct napi_struct * napi,int rx_todo,struct mvpp2_rx_queue * rxq)3897 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3898 		    int rx_todo, struct mvpp2_rx_queue *rxq)
3899 {
3900 	struct net_device *dev = port->dev;
3901 	struct mvpp2_pcpu_stats ps = {};
3902 	enum dma_data_direction dma_dir;
3903 	struct bpf_prog *xdp_prog;
3904 	struct xdp_buff xdp;
3905 	int rx_received;
3906 	int rx_done = 0;
3907 	u32 xdp_ret = 0;
3908 
3909 	xdp_prog = READ_ONCE(port->xdp_prog);
3910 
3911 	/* Get number of received packets and clamp the to-do */
3912 	rx_received = mvpp2_rxq_received(port, rxq->id);
3913 	if (rx_todo > rx_received)
3914 		rx_todo = rx_received;
3915 
3916 	while (rx_done < rx_todo) {
3917 		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3918 		struct mvpp2_bm_pool *bm_pool;
3919 		struct page_pool *pp = NULL;
3920 		struct sk_buff *skb;
3921 		unsigned int frag_size;
3922 		dma_addr_t dma_addr;
3923 		phys_addr_t phys_addr;
3924 		u32 rx_status, timestamp;
3925 		int pool, rx_bytes, err, ret;
3926 		struct page *page;
3927 		void *data;
3928 
3929 		phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3930 		data = (void *)phys_to_virt(phys_addr);
3931 		page = virt_to_page(data);
3932 		prefetch(page);
3933 
3934 		rx_done++;
3935 		rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3936 		rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3937 		rx_bytes -= MVPP2_MH_SIZE;
3938 		dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3939 
3940 		pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3941 			MVPP2_RXD_BM_POOL_ID_OFFS;
3942 		bm_pool = &port->priv->bm_pools[pool];
3943 
3944 		if (port->priv->percpu_pools) {
3945 			pp = port->priv->page_pool[pool];
3946 			dma_dir = page_pool_get_dma_dir(pp);
3947 		} else {
3948 			dma_dir = DMA_FROM_DEVICE;
3949 		}
3950 
3951 		dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3952 					rx_bytes + MVPP2_MH_SIZE,
3953 					dma_dir);
3954 
3955 		/* Buffer header not supported */
3956 		if (rx_status & MVPP2_RXD_BUF_HDR)
3957 			goto err_drop_frame;
3958 
3959 		/* In case of an error, release the requested buffer pointer
3960 		 * to the Buffer Manager. This request process is controlled
3961 		 * by the hardware, and the information about the buffer is
3962 		 * comprised by the RX descriptor.
3963 		 */
3964 		if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3965 			goto err_drop_frame;
3966 
3967 		/* Prefetch header */
3968 		prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3969 
3970 		if (bm_pool->frag_size > PAGE_SIZE)
3971 			frag_size = 0;
3972 		else
3973 			frag_size = bm_pool->frag_size;
3974 
3975 		if (xdp_prog) {
3976 			struct xdp_rxq_info *xdp_rxq;
3977 
3978 			if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3979 				xdp_rxq = &rxq->xdp_rxq_short;
3980 			else
3981 				xdp_rxq = &rxq->xdp_rxq_long;
3982 
3983 			xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq);
3984 			xdp_prepare_buff(&xdp, data,
3985 					 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM,
3986 					 rx_bytes, false);
3987 
3988 			ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps);
3989 
3990 			if (ret) {
3991 				xdp_ret |= ret;
3992 				err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3993 				if (err) {
3994 					netdev_err(port->dev, "failed to refill BM pools\n");
3995 					goto err_drop_frame;
3996 				}
3997 
3998 				ps.rx_packets++;
3999 				ps.rx_bytes += rx_bytes;
4000 				continue;
4001 			}
4002 		}
4003 
4004 		if (frag_size)
4005 			skb = build_skb(data, frag_size);
4006 		else
4007 			skb = slab_build_skb(data);
4008 		if (!skb) {
4009 			netdev_warn(port->dev, "skb build failed\n");
4010 			goto err_drop_frame;
4011 		}
4012 
4013 		/* If we have RX hardware timestamping enabled, grab the
4014 		 * timestamp from the queue and convert.
4015 		 */
4016 		if (mvpp22_rx_hwtstamping(port)) {
4017 			timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
4018 			mvpp22_tai_tstamp(port->priv->tai, timestamp,
4019 					 skb_hwtstamps(skb));
4020 		}
4021 
4022 		err = mvpp2_rx_refill(port, bm_pool, pp, pool);
4023 		if (err) {
4024 			netdev_err(port->dev, "failed to refill BM pools\n");
4025 			dev_kfree_skb_any(skb);
4026 			goto err_drop_frame;
4027 		}
4028 
4029 		if (pp)
4030 			skb_mark_for_recycle(skb);
4031 		else
4032 			dma_unmap_single_attrs(dev->dev.parent, dma_addr,
4033 					       bm_pool->buf_size, DMA_FROM_DEVICE,
4034 					       DMA_ATTR_SKIP_CPU_SYNC);
4035 
4036 		ps.rx_packets++;
4037 		ps.rx_bytes += rx_bytes;
4038 
4039 		skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
4040 		skb_put(skb, rx_bytes);
4041 		skb->ip_summed = mvpp2_rx_csum(port, rx_status);
4042 		skb->protocol = eth_type_trans(skb, dev);
4043 
4044 		napi_gro_receive(napi, skb);
4045 		continue;
4046 
4047 err_drop_frame:
4048 		dev->stats.rx_errors++;
4049 		mvpp2_rx_error(port, rx_desc);
4050 		/* Return the buffer to the pool */
4051 		if (rx_status & MVPP2_RXD_BUF_HDR)
4052 			mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status);
4053 		else
4054 			mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
4055 	}
4056 
4057 	if (xdp_ret & MVPP2_XDP_REDIR)
4058 		xdp_do_flush_map();
4059 
4060 	if (ps.rx_packets) {
4061 		struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
4062 
4063 		u64_stats_update_begin(&stats->syncp);
4064 		stats->rx_packets += ps.rx_packets;
4065 		stats->rx_bytes   += ps.rx_bytes;
4066 		/* xdp */
4067 		stats->xdp_redirect += ps.xdp_redirect;
4068 		stats->xdp_pass += ps.xdp_pass;
4069 		stats->xdp_drop += ps.xdp_drop;
4070 		u64_stats_update_end(&stats->syncp);
4071 	}
4072 
4073 	/* Update Rx queue management counters */
4074 	wmb();
4075 	mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
4076 
4077 	return rx_todo;
4078 }
4079 
4080 static inline void
tx_desc_unmap_put(struct mvpp2_port * port,struct mvpp2_tx_queue * txq,struct mvpp2_tx_desc * desc)4081 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4082 		  struct mvpp2_tx_desc *desc)
4083 {
4084 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4085 	struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4086 
4087 	dma_addr_t buf_dma_addr =
4088 		mvpp2_txdesc_dma_addr_get(port, desc);
4089 	size_t buf_sz =
4090 		mvpp2_txdesc_size_get(port, desc);
4091 	if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
4092 		dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
4093 				 buf_sz, DMA_TO_DEVICE);
4094 	mvpp2_txq_desc_put(txq);
4095 }
4096 
mvpp2_txdesc_clear_ptp(struct mvpp2_port * port,struct mvpp2_tx_desc * desc)4097 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
4098 				   struct mvpp2_tx_desc *desc)
4099 {
4100 	/* We only need to clear the low bits */
4101 	if (port->priv->hw_version >= MVPP22)
4102 		desc->pp22.ptp_descriptor &=
4103 			cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4104 }
4105 
mvpp2_tx_hw_tstamp(struct mvpp2_port * port,struct mvpp2_tx_desc * tx_desc,struct sk_buff * skb)4106 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
4107 			       struct mvpp2_tx_desc *tx_desc,
4108 			       struct sk_buff *skb)
4109 {
4110 	struct mvpp2_hwtstamp_queue *queue;
4111 	unsigned int mtype, type, i;
4112 	struct ptp_header *hdr;
4113 	u64 ptpdesc;
4114 
4115 	if (port->priv->hw_version == MVPP21 ||
4116 	    port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
4117 		return false;
4118 
4119 	type = ptp_classify_raw(skb);
4120 	if (!type)
4121 		return false;
4122 
4123 	hdr = ptp_parse_header(skb, type);
4124 	if (!hdr)
4125 		return false;
4126 
4127 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4128 
4129 	ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
4130 		  MVPP22_PTP_ACTION_CAPTURE;
4131 	queue = &port->tx_hwtstamp_queue[0];
4132 
4133 	switch (type & PTP_CLASS_VMASK) {
4134 	case PTP_CLASS_V1:
4135 		ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
4136 		break;
4137 
4138 	case PTP_CLASS_V2:
4139 		ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
4140 		mtype = hdr->tsmt & 15;
4141 		/* Direct PTP Sync messages to queue 1 */
4142 		if (mtype == 0) {
4143 			ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
4144 			queue = &port->tx_hwtstamp_queue[1];
4145 		}
4146 		break;
4147 	}
4148 
4149 	/* Take a reference on the skb and insert into our queue */
4150 	i = queue->next;
4151 	queue->next = (i + 1) & 31;
4152 	if (queue->skb[i])
4153 		dev_kfree_skb_any(queue->skb[i]);
4154 	queue->skb[i] = skb_get(skb);
4155 
4156 	ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
4157 
4158 	/*
4159 	 * 3:0		- PTPAction
4160 	 * 6:4		- PTPPacketFormat
4161 	 * 7		- PTP_CF_WraparoundCheckEn
4162 	 * 9:8		- IngressTimestampSeconds[1:0]
4163 	 * 10		- Reserved
4164 	 * 11		- MACTimestampingEn
4165 	 * 17:12	- PTP_TimestampQueueEntryID[5:0]
4166 	 * 18		- PTPTimestampQueueSelect
4167 	 * 19		- UDPChecksumUpdateEn
4168 	 * 27:20	- TimestampOffset
4169 	 *			PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
4170 	 *			NTPTs, Y.1731 - L3 to timestamp entry
4171 	 * 35:28	- UDP Checksum Offset
4172 	 *
4173 	 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
4174 	 */
4175 	tx_desc->pp22.ptp_descriptor &=
4176 		cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4177 	tx_desc->pp22.ptp_descriptor |=
4178 		cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
4179 	tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4180 	tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4181 
4182 	return true;
4183 }
4184 
4185 /* Handle tx fragmentation processing */
mvpp2_tx_frag_process(struct mvpp2_port * port,struct sk_buff * skb,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_tx_queue * txq)4186 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
4187 				 struct mvpp2_tx_queue *aggr_txq,
4188 				 struct mvpp2_tx_queue *txq)
4189 {
4190 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4191 	struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4192 	struct mvpp2_tx_desc *tx_desc;
4193 	int i;
4194 	dma_addr_t buf_dma_addr;
4195 
4196 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4197 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4198 		void *addr = skb_frag_address(frag);
4199 
4200 		tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4201 		mvpp2_txdesc_clear_ptp(port, tx_desc);
4202 		mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4203 		mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4204 
4205 		buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
4206 					      skb_frag_size(frag),
4207 					      DMA_TO_DEVICE);
4208 		if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
4209 			mvpp2_txq_desc_put(txq);
4210 			goto cleanup;
4211 		}
4212 
4213 		mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4214 
4215 		if (i == (skb_shinfo(skb)->nr_frags - 1)) {
4216 			/* Last descriptor */
4217 			mvpp2_txdesc_cmd_set(port, tx_desc,
4218 					     MVPP2_TXD_L_DESC);
4219 			mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4220 		} else {
4221 			/* Descriptor in the middle: Not First, Not Last */
4222 			mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4223 			mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4224 		}
4225 	}
4226 
4227 	return 0;
4228 cleanup:
4229 	/* Release all descriptors that were used to map fragments of
4230 	 * this packet, as well as the corresponding DMA mappings
4231 	 */
4232 	for (i = i - 1; i >= 0; i--) {
4233 		tx_desc = txq->descs + i;
4234 		tx_desc_unmap_put(port, txq, tx_desc);
4235 	}
4236 
4237 	return -ENOMEM;
4238 }
4239 
mvpp2_tso_put_hdr(struct sk_buff * skb,struct net_device * dev,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu,int hdr_sz)4240 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
4241 				     struct net_device *dev,
4242 				     struct mvpp2_tx_queue *txq,
4243 				     struct mvpp2_tx_queue *aggr_txq,
4244 				     struct mvpp2_txq_pcpu *txq_pcpu,
4245 				     int hdr_sz)
4246 {
4247 	struct mvpp2_port *port = netdev_priv(dev);
4248 	struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4249 	dma_addr_t addr;
4250 
4251 	mvpp2_txdesc_clear_ptp(port, tx_desc);
4252 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4253 	mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4254 
4255 	addr = txq_pcpu->tso_headers_dma +
4256 	       txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4257 	mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4258 
4259 	mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4260 					    MVPP2_TXD_F_DESC |
4261 					    MVPP2_TXD_PADDING_DISABLE);
4262 	mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4263 }
4264 
mvpp2_tso_put_data(struct sk_buff * skb,struct net_device * dev,struct tso_t * tso,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu,int sz,bool left,bool last)4265 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
4266 				     struct net_device *dev, struct tso_t *tso,
4267 				     struct mvpp2_tx_queue *txq,
4268 				     struct mvpp2_tx_queue *aggr_txq,
4269 				     struct mvpp2_txq_pcpu *txq_pcpu,
4270 				     int sz, bool left, bool last)
4271 {
4272 	struct mvpp2_port *port = netdev_priv(dev);
4273 	struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4274 	dma_addr_t buf_dma_addr;
4275 
4276 	mvpp2_txdesc_clear_ptp(port, tx_desc);
4277 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4278 	mvpp2_txdesc_size_set(port, tx_desc, sz);
4279 
4280 	buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
4281 				      DMA_TO_DEVICE);
4282 	if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4283 		mvpp2_txq_desc_put(txq);
4284 		return -ENOMEM;
4285 	}
4286 
4287 	mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4288 
4289 	if (!left) {
4290 		mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4291 		if (last) {
4292 			mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4293 			return 0;
4294 		}
4295 	} else {
4296 		mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4297 	}
4298 
4299 	mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4300 	return 0;
4301 }
4302 
mvpp2_tx_tso(struct sk_buff * skb,struct net_device * dev,struct mvpp2_tx_queue * txq,struct mvpp2_tx_queue * aggr_txq,struct mvpp2_txq_pcpu * txq_pcpu)4303 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
4304 			struct mvpp2_tx_queue *txq,
4305 			struct mvpp2_tx_queue *aggr_txq,
4306 			struct mvpp2_txq_pcpu *txq_pcpu)
4307 {
4308 	struct mvpp2_port *port = netdev_priv(dev);
4309 	int hdr_sz, i, len, descs = 0;
4310 	struct tso_t tso;
4311 
4312 	/* Check number of available descriptors */
4313 	if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
4314 	    mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
4315 					     tso_count_descs(skb)))
4316 		return 0;
4317 
4318 	hdr_sz = tso_start(skb, &tso);
4319 
4320 	len = skb->len - hdr_sz;
4321 	while (len > 0) {
4322 		int left = min_t(int, skb_shinfo(skb)->gso_size, len);
4323 		char *hdr = txq_pcpu->tso_headers +
4324 			    txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4325 
4326 		len -= left;
4327 		descs++;
4328 
4329 		tso_build_hdr(skb, hdr, &tso, left, len == 0);
4330 		mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
4331 
4332 		while (left > 0) {
4333 			int sz = min_t(int, tso.size, left);
4334 			left -= sz;
4335 			descs++;
4336 
4337 			if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
4338 					       txq_pcpu, sz, left, len == 0))
4339 				goto release;
4340 			tso_build_data(skb, &tso, sz);
4341 		}
4342 	}
4343 
4344 	return descs;
4345 
4346 release:
4347 	for (i = descs - 1; i >= 0; i--) {
4348 		struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4349 		tx_desc_unmap_put(port, txq, tx_desc);
4350 	}
4351 	return 0;
4352 }
4353 
4354 /* Main tx processing */
mvpp2_tx(struct sk_buff * skb,struct net_device * dev)4355 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
4356 {
4357 	struct mvpp2_port *port = netdev_priv(dev);
4358 	struct mvpp2_tx_queue *txq, *aggr_txq;
4359 	struct mvpp2_txq_pcpu *txq_pcpu;
4360 	struct mvpp2_tx_desc *tx_desc;
4361 	dma_addr_t buf_dma_addr;
4362 	unsigned long flags = 0;
4363 	unsigned int thread;
4364 	int frags = 0;
4365 	u16 txq_id;
4366 	u32 tx_cmd;
4367 
4368 	thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4369 
4370 	txq_id = skb_get_queue_mapping(skb);
4371 	txq = port->txqs[txq_id];
4372 	txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4373 	aggr_txq = &port->priv->aggr_txqs[thread];
4374 
4375 	if (test_bit(thread, &port->priv->lock_map))
4376 		spin_lock_irqsave(&port->tx_lock[thread], flags);
4377 
4378 	if (skb_is_gso(skb)) {
4379 		frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
4380 		goto out;
4381 	}
4382 	frags = skb_shinfo(skb)->nr_frags + 1;
4383 
4384 	/* Check number of available descriptors */
4385 	if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
4386 	    mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
4387 		frags = 0;
4388 		goto out;
4389 	}
4390 
4391 	/* Get a descriptor for the first part of the packet */
4392 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4393 	if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
4394 	    !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4395 		mvpp2_txdesc_clear_ptp(port, tx_desc);
4396 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4397 	mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4398 
4399 	buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
4400 				      skb_headlen(skb), DMA_TO_DEVICE);
4401 	if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4402 		mvpp2_txq_desc_put(txq);
4403 		frags = 0;
4404 		goto out;
4405 	}
4406 
4407 	mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4408 
4409 	tx_cmd = mvpp2_skb_tx_csum(port, skb);
4410 
4411 	if (frags == 1) {
4412 		/* First and Last descriptor */
4413 		tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4414 		mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4415 		mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4416 	} else {
4417 		/* First but not Last */
4418 		tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4419 		mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4420 		mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4421 
4422 		/* Continue with other skb fragments */
4423 		if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4424 			tx_desc_unmap_put(port, txq, tx_desc);
4425 			frags = 0;
4426 		}
4427 	}
4428 
4429 out:
4430 	if (frags > 0) {
4431 		struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4432 		struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4433 
4434 		txq_pcpu->reserved_num -= frags;
4435 		txq_pcpu->count += frags;
4436 		aggr_txq->count += frags;
4437 
4438 		/* Enable transmit */
4439 		wmb();
4440 		mvpp2_aggr_txq_pend_desc_add(port, frags);
4441 
4442 		if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4443 			netif_tx_stop_queue(nq);
4444 
4445 		u64_stats_update_begin(&stats->syncp);
4446 		stats->tx_packets++;
4447 		stats->tx_bytes += skb->len;
4448 		u64_stats_update_end(&stats->syncp);
4449 	} else {
4450 		dev->stats.tx_dropped++;
4451 		dev_kfree_skb_any(skb);
4452 	}
4453 
4454 	/* Finalize TX processing */
4455 	if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4456 		mvpp2_txq_done(port, txq, txq_pcpu);
4457 
4458 	/* Set the timer in case not all frags were processed */
4459 	if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4460 	    txq_pcpu->count > 0) {
4461 		struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4462 
4463 		if (!port_pcpu->timer_scheduled) {
4464 			port_pcpu->timer_scheduled = true;
4465 			hrtimer_start(&port_pcpu->tx_done_timer,
4466 				      MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4467 				      HRTIMER_MODE_REL_PINNED_SOFT);
4468 		}
4469 	}
4470 
4471 	if (test_bit(thread, &port->priv->lock_map))
4472 		spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4473 
4474 	return NETDEV_TX_OK;
4475 }
4476 
mvpp2_cause_error(struct net_device * dev,int cause)4477 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4478 {
4479 	if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4480 		netdev_err(dev, "FCS error\n");
4481 	if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4482 		netdev_err(dev, "rx fifo overrun error\n");
4483 	if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4484 		netdev_err(dev, "tx fifo underrun error\n");
4485 }
4486 
mvpp2_poll(struct napi_struct * napi,int budget)4487 static int mvpp2_poll(struct napi_struct *napi, int budget)
4488 {
4489 	u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4490 	int rx_done = 0;
4491 	struct mvpp2_port *port = netdev_priv(napi->dev);
4492 	struct mvpp2_queue_vector *qv;
4493 	unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4494 
4495 	qv = container_of(napi, struct mvpp2_queue_vector, napi);
4496 
4497 	/* Rx/Tx cause register
4498 	 *
4499 	 * Bits 0-15: each bit indicates received packets on the Rx queue
4500 	 * (bit 0 is for Rx queue 0).
4501 	 *
4502 	 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4503 	 * (bit 16 is for Tx queue 0).
4504 	 *
4505 	 * Each CPU has its own Rx/Tx cause register
4506 	 */
4507 	cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4508 						MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4509 
4510 	cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4511 	if (cause_misc) {
4512 		mvpp2_cause_error(port->dev, cause_misc);
4513 
4514 		/* Clear the cause register */
4515 		mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4516 		mvpp2_thread_write(port->priv, thread,
4517 				   MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4518 				   cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4519 	}
4520 
4521 	if (port->has_tx_irqs) {
4522 		cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4523 		if (cause_tx) {
4524 			cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4525 			mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4526 		}
4527 	}
4528 
4529 	/* Process RX packets */
4530 	cause_rx = cause_rx_tx &
4531 		   MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4532 	cause_rx <<= qv->first_rxq;
4533 	cause_rx |= qv->pending_cause_rx;
4534 	while (cause_rx && budget > 0) {
4535 		int count;
4536 		struct mvpp2_rx_queue *rxq;
4537 
4538 		rxq = mvpp2_get_rx_queue(port, cause_rx);
4539 		if (!rxq)
4540 			break;
4541 
4542 		count = mvpp2_rx(port, napi, budget, rxq);
4543 		rx_done += count;
4544 		budget -= count;
4545 		if (budget > 0) {
4546 			/* Clear the bit associated to this Rx queue
4547 			 * so that next iteration will continue from
4548 			 * the next Rx queue.
4549 			 */
4550 			cause_rx &= ~(1 << rxq->logic_rxq);
4551 		}
4552 	}
4553 
4554 	if (budget > 0) {
4555 		cause_rx = 0;
4556 		napi_complete_done(napi, rx_done);
4557 
4558 		mvpp2_qvec_interrupt_enable(qv);
4559 	}
4560 	qv->pending_cause_rx = cause_rx;
4561 	return rx_done;
4562 }
4563 
mvpp22_mode_reconfigure(struct mvpp2_port * port,phy_interface_t interface)4564 static void mvpp22_mode_reconfigure(struct mvpp2_port *port,
4565 				    phy_interface_t interface)
4566 {
4567 	u32 ctrl3;
4568 
4569 	/* Set the GMAC & XLG MAC in reset */
4570 	mvpp2_mac_reset_assert(port);
4571 
4572 	/* Set the MPCS and XPCS in reset */
4573 	mvpp22_pcs_reset_assert(port);
4574 
4575 	/* comphy reconfiguration */
4576 	mvpp22_comphy_init(port, interface);
4577 
4578 	/* gop reconfiguration */
4579 	mvpp22_gop_init(port, interface);
4580 
4581 	mvpp22_pcs_reset_deassert(port, interface);
4582 
4583 	if (mvpp2_port_supports_xlg(port)) {
4584 		ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4585 		ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4586 
4587 		if (mvpp2_is_xlg(interface))
4588 			ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4589 		else
4590 			ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4591 
4592 		writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4593 	}
4594 
4595 	if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface))
4596 		mvpp2_xlg_max_rx_size_set(port);
4597 	else
4598 		mvpp2_gmac_max_rx_size_set(port);
4599 }
4600 
4601 /* Set hw internals when starting port */
mvpp2_start_dev(struct mvpp2_port * port)4602 static void mvpp2_start_dev(struct mvpp2_port *port)
4603 {
4604 	int i;
4605 
4606 	mvpp2_txp_max_tx_size_set(port);
4607 
4608 	for (i = 0; i < port->nqvecs; i++)
4609 		napi_enable(&port->qvecs[i].napi);
4610 
4611 	/* Enable interrupts on all threads */
4612 	mvpp2_interrupts_enable(port);
4613 
4614 	if (port->priv->hw_version >= MVPP22)
4615 		mvpp22_mode_reconfigure(port, port->phy_interface);
4616 
4617 	if (port->phylink) {
4618 		phylink_start(port->phylink);
4619 	} else {
4620 		mvpp2_acpi_start(port);
4621 	}
4622 
4623 	netif_tx_start_all_queues(port->dev);
4624 
4625 	clear_bit(0, &port->state);
4626 }
4627 
4628 /* Set hw internals when stopping port */
mvpp2_stop_dev(struct mvpp2_port * port)4629 static void mvpp2_stop_dev(struct mvpp2_port *port)
4630 {
4631 	int i;
4632 
4633 	set_bit(0, &port->state);
4634 
4635 	/* Disable interrupts on all threads */
4636 	mvpp2_interrupts_disable(port);
4637 
4638 	for (i = 0; i < port->nqvecs; i++)
4639 		napi_disable(&port->qvecs[i].napi);
4640 
4641 	if (port->phylink)
4642 		phylink_stop(port->phylink);
4643 	phy_power_off(port->comphy);
4644 }
4645 
mvpp2_check_ringparam_valid(struct net_device * dev,struct ethtool_ringparam * ring)4646 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4647 				       struct ethtool_ringparam *ring)
4648 {
4649 	u16 new_rx_pending = ring->rx_pending;
4650 	u16 new_tx_pending = ring->tx_pending;
4651 
4652 	if (ring->rx_pending == 0 || ring->tx_pending == 0)
4653 		return -EINVAL;
4654 
4655 	if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4656 		new_rx_pending = MVPP2_MAX_RXD_MAX;
4657 	else if (ring->rx_pending < MSS_THRESHOLD_START)
4658 		new_rx_pending = MSS_THRESHOLD_START;
4659 	else if (!IS_ALIGNED(ring->rx_pending, 16))
4660 		new_rx_pending = ALIGN(ring->rx_pending, 16);
4661 
4662 	if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4663 		new_tx_pending = MVPP2_MAX_TXD_MAX;
4664 	else if (!IS_ALIGNED(ring->tx_pending, 32))
4665 		new_tx_pending = ALIGN(ring->tx_pending, 32);
4666 
4667 	/* The Tx ring size cannot be smaller than the minimum number of
4668 	 * descriptors needed for TSO.
4669 	 */
4670 	if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4671 		new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4672 
4673 	if (ring->rx_pending != new_rx_pending) {
4674 		netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4675 			    ring->rx_pending, new_rx_pending);
4676 		ring->rx_pending = new_rx_pending;
4677 	}
4678 
4679 	if (ring->tx_pending != new_tx_pending) {
4680 		netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4681 			    ring->tx_pending, new_tx_pending);
4682 		ring->tx_pending = new_tx_pending;
4683 	}
4684 
4685 	return 0;
4686 }
4687 
mvpp21_get_mac_address(struct mvpp2_port * port,unsigned char * addr)4688 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4689 {
4690 	u32 mac_addr_l, mac_addr_m, mac_addr_h;
4691 
4692 	mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4693 	mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4694 	mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4695 	addr[0] = (mac_addr_h >> 24) & 0xFF;
4696 	addr[1] = (mac_addr_h >> 16) & 0xFF;
4697 	addr[2] = (mac_addr_h >> 8) & 0xFF;
4698 	addr[3] = mac_addr_h & 0xFF;
4699 	addr[4] = mac_addr_m & 0xFF;
4700 	addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4701 }
4702 
mvpp2_irqs_init(struct mvpp2_port * port)4703 static int mvpp2_irqs_init(struct mvpp2_port *port)
4704 {
4705 	int err, i;
4706 
4707 	for (i = 0; i < port->nqvecs; i++) {
4708 		struct mvpp2_queue_vector *qv = port->qvecs + i;
4709 
4710 		if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4711 			qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4712 			if (!qv->mask) {
4713 				err = -ENOMEM;
4714 				goto err;
4715 			}
4716 
4717 			irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4718 		}
4719 
4720 		err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4721 		if (err)
4722 			goto err;
4723 
4724 		if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4725 			unsigned int cpu;
4726 
4727 			for_each_present_cpu(cpu) {
4728 				if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4729 				    qv->sw_thread_id)
4730 					cpumask_set_cpu(cpu, qv->mask);
4731 			}
4732 
4733 			irq_set_affinity_hint(qv->irq, qv->mask);
4734 		}
4735 	}
4736 
4737 	return 0;
4738 err:
4739 	for (i = 0; i < port->nqvecs; i++) {
4740 		struct mvpp2_queue_vector *qv = port->qvecs + i;
4741 
4742 		irq_set_affinity_hint(qv->irq, NULL);
4743 		kfree(qv->mask);
4744 		qv->mask = NULL;
4745 		free_irq(qv->irq, qv);
4746 	}
4747 
4748 	return err;
4749 }
4750 
mvpp2_irqs_deinit(struct mvpp2_port * port)4751 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4752 {
4753 	int i;
4754 
4755 	for (i = 0; i < port->nqvecs; i++) {
4756 		struct mvpp2_queue_vector *qv = port->qvecs + i;
4757 
4758 		irq_set_affinity_hint(qv->irq, NULL);
4759 		kfree(qv->mask);
4760 		qv->mask = NULL;
4761 		irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4762 		free_irq(qv->irq, qv);
4763 	}
4764 }
4765 
mvpp22_rss_is_supported(struct mvpp2_port * port)4766 static bool mvpp22_rss_is_supported(struct mvpp2_port *port)
4767 {
4768 	return (queue_mode == MVPP2_QDIST_MULTI_MODE) &&
4769 		!(port->flags & MVPP2_F_LOOPBACK);
4770 }
4771 
mvpp2_open(struct net_device * dev)4772 static int mvpp2_open(struct net_device *dev)
4773 {
4774 	struct mvpp2_port *port = netdev_priv(dev);
4775 	struct mvpp2 *priv = port->priv;
4776 	unsigned char mac_bcast[ETH_ALEN] = {
4777 			0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4778 	bool valid = false;
4779 	int err;
4780 
4781 	err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4782 	if (err) {
4783 		netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4784 		return err;
4785 	}
4786 	err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4787 	if (err) {
4788 		netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4789 		return err;
4790 	}
4791 	err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4792 	if (err) {
4793 		netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4794 		return err;
4795 	}
4796 	err = mvpp2_prs_def_flow(port);
4797 	if (err) {
4798 		netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4799 		return err;
4800 	}
4801 
4802 	/* Allocate the Rx/Tx queues */
4803 	err = mvpp2_setup_rxqs(port);
4804 	if (err) {
4805 		netdev_err(port->dev, "cannot allocate Rx queues\n");
4806 		return err;
4807 	}
4808 
4809 	err = mvpp2_setup_txqs(port);
4810 	if (err) {
4811 		netdev_err(port->dev, "cannot allocate Tx queues\n");
4812 		goto err_cleanup_rxqs;
4813 	}
4814 
4815 	err = mvpp2_irqs_init(port);
4816 	if (err) {
4817 		netdev_err(port->dev, "cannot init IRQs\n");
4818 		goto err_cleanup_txqs;
4819 	}
4820 
4821 	if (port->phylink) {
4822 		err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0);
4823 		if (err) {
4824 			netdev_err(port->dev, "could not attach PHY (%d)\n",
4825 				   err);
4826 			goto err_free_irq;
4827 		}
4828 
4829 		valid = true;
4830 	}
4831 
4832 	if (priv->hw_version >= MVPP22 && port->port_irq) {
4833 		err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4834 				  dev->name, port);
4835 		if (err) {
4836 			netdev_err(port->dev,
4837 				   "cannot request port link/ptp IRQ %d\n",
4838 				   port->port_irq);
4839 			goto err_free_irq;
4840 		}
4841 
4842 		mvpp22_gop_setup_irq(port);
4843 
4844 		/* In default link is down */
4845 		netif_carrier_off(port->dev);
4846 
4847 		valid = true;
4848 	} else {
4849 		port->port_irq = 0;
4850 	}
4851 
4852 	if (!valid) {
4853 		netdev_err(port->dev,
4854 			   "invalid configuration: no dt or link IRQ");
4855 		err = -ENOENT;
4856 		goto err_free_irq;
4857 	}
4858 
4859 	/* Unmask interrupts on all CPUs */
4860 	on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4861 	mvpp2_shared_interrupt_mask_unmask(port, false);
4862 
4863 	mvpp2_start_dev(port);
4864 
4865 	/* Start hardware statistics gathering */
4866 	queue_delayed_work(priv->stats_queue, &port->stats_work,
4867 			   MVPP2_MIB_COUNTERS_STATS_DELAY);
4868 
4869 	return 0;
4870 
4871 err_free_irq:
4872 	mvpp2_irqs_deinit(port);
4873 err_cleanup_txqs:
4874 	mvpp2_cleanup_txqs(port);
4875 err_cleanup_rxqs:
4876 	mvpp2_cleanup_rxqs(port);
4877 	return err;
4878 }
4879 
mvpp2_stop(struct net_device * dev)4880 static int mvpp2_stop(struct net_device *dev)
4881 {
4882 	struct mvpp2_port *port = netdev_priv(dev);
4883 	struct mvpp2_port_pcpu *port_pcpu;
4884 	unsigned int thread;
4885 
4886 	mvpp2_stop_dev(port);
4887 
4888 	/* Mask interrupts on all threads */
4889 	on_each_cpu(mvpp2_interrupts_mask, port, 1);
4890 	mvpp2_shared_interrupt_mask_unmask(port, true);
4891 
4892 	if (port->phylink)
4893 		phylink_disconnect_phy(port->phylink);
4894 	if (port->port_irq)
4895 		free_irq(port->port_irq, port);
4896 
4897 	mvpp2_irqs_deinit(port);
4898 	if (!port->has_tx_irqs) {
4899 		for (thread = 0; thread < port->priv->nthreads; thread++) {
4900 			port_pcpu = per_cpu_ptr(port->pcpu, thread);
4901 
4902 			hrtimer_cancel(&port_pcpu->tx_done_timer);
4903 			port_pcpu->timer_scheduled = false;
4904 		}
4905 	}
4906 	mvpp2_cleanup_rxqs(port);
4907 	mvpp2_cleanup_txqs(port);
4908 
4909 	cancel_delayed_work_sync(&port->stats_work);
4910 
4911 	mvpp2_mac_reset_assert(port);
4912 	mvpp22_pcs_reset_assert(port);
4913 
4914 	return 0;
4915 }
4916 
mvpp2_prs_mac_da_accept_list(struct mvpp2_port * port,struct netdev_hw_addr_list * list)4917 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4918 					struct netdev_hw_addr_list *list)
4919 {
4920 	struct netdev_hw_addr *ha;
4921 	int ret;
4922 
4923 	netdev_hw_addr_list_for_each(ha, list) {
4924 		ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4925 		if (ret)
4926 			return ret;
4927 	}
4928 
4929 	return 0;
4930 }
4931 
mvpp2_set_rx_promisc(struct mvpp2_port * port,bool enable)4932 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4933 {
4934 	if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4935 		mvpp2_prs_vid_enable_filtering(port);
4936 	else
4937 		mvpp2_prs_vid_disable_filtering(port);
4938 
4939 	mvpp2_prs_mac_promisc_set(port->priv, port->id,
4940 				  MVPP2_PRS_L2_UNI_CAST, enable);
4941 
4942 	mvpp2_prs_mac_promisc_set(port->priv, port->id,
4943 				  MVPP2_PRS_L2_MULTI_CAST, enable);
4944 }
4945 
mvpp2_set_rx_mode(struct net_device * dev)4946 static void mvpp2_set_rx_mode(struct net_device *dev)
4947 {
4948 	struct mvpp2_port *port = netdev_priv(dev);
4949 
4950 	/* Clear the whole UC and MC list */
4951 	mvpp2_prs_mac_del_all(port);
4952 
4953 	if (dev->flags & IFF_PROMISC) {
4954 		mvpp2_set_rx_promisc(port, true);
4955 		return;
4956 	}
4957 
4958 	mvpp2_set_rx_promisc(port, false);
4959 
4960 	if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4961 	    mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4962 		mvpp2_prs_mac_promisc_set(port->priv, port->id,
4963 					  MVPP2_PRS_L2_UNI_CAST, true);
4964 
4965 	if (dev->flags & IFF_ALLMULTI) {
4966 		mvpp2_prs_mac_promisc_set(port->priv, port->id,
4967 					  MVPP2_PRS_L2_MULTI_CAST, true);
4968 		return;
4969 	}
4970 
4971 	if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4972 	    mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4973 		mvpp2_prs_mac_promisc_set(port->priv, port->id,
4974 					  MVPP2_PRS_L2_MULTI_CAST, true);
4975 }
4976 
mvpp2_set_mac_address(struct net_device * dev,void * p)4977 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4978 {
4979 	const struct sockaddr *addr = p;
4980 	int err;
4981 
4982 	if (!is_valid_ether_addr(addr->sa_data))
4983 		return -EADDRNOTAVAIL;
4984 
4985 	err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4986 	if (err) {
4987 		/* Reconfigure parser accept the original MAC address */
4988 		mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4989 		netdev_err(dev, "failed to change MAC address\n");
4990 	}
4991 	return err;
4992 }
4993 
4994 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4995  * then bring up again all ports.
4996  */
mvpp2_bm_switch_buffers(struct mvpp2 * priv,bool percpu)4997 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4998 {
4999 	bool change_percpu = (percpu != priv->percpu_pools);
5000 	int numbufs = MVPP2_BM_POOLS_NUM, i;
5001 	struct mvpp2_port *port = NULL;
5002 	bool status[MVPP2_MAX_PORTS];
5003 
5004 	for (i = 0; i < priv->port_count; i++) {
5005 		port = priv->port_list[i];
5006 		status[i] = netif_running(port->dev);
5007 		if (status[i])
5008 			mvpp2_stop(port->dev);
5009 	}
5010 
5011 	/* nrxqs is the same for all ports */
5012 	if (priv->percpu_pools)
5013 		numbufs = port->nrxqs * 2;
5014 
5015 	if (change_percpu)
5016 		mvpp2_bm_pool_update_priv_fc(priv, false);
5017 
5018 	for (i = 0; i < numbufs; i++)
5019 		mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
5020 
5021 	devm_kfree(port->dev->dev.parent, priv->bm_pools);
5022 	priv->percpu_pools = percpu;
5023 	mvpp2_bm_init(port->dev->dev.parent, priv);
5024 
5025 	for (i = 0; i < priv->port_count; i++) {
5026 		port = priv->port_list[i];
5027 		if (percpu && port->ntxqs >= num_possible_cpus() * 2)
5028 			xdp_set_features_flag(port->dev,
5029 					      NETDEV_XDP_ACT_BASIC |
5030 					      NETDEV_XDP_ACT_REDIRECT |
5031 					      NETDEV_XDP_ACT_NDO_XMIT);
5032 		else
5033 			xdp_clear_features_flag(port->dev);
5034 
5035 		mvpp2_swf_bm_pool_init(port);
5036 		if (status[i])
5037 			mvpp2_open(port->dev);
5038 	}
5039 
5040 	if (change_percpu)
5041 		mvpp2_bm_pool_update_priv_fc(priv, true);
5042 
5043 	return 0;
5044 }
5045 
mvpp2_change_mtu(struct net_device * dev,int mtu)5046 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5047 {
5048 	struct mvpp2_port *port = netdev_priv(dev);
5049 	bool running = netif_running(dev);
5050 	struct mvpp2 *priv = port->priv;
5051 	int err;
5052 
5053 	if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5054 		netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5055 			    ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5056 		mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5057 	}
5058 
5059 	if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) {
5060 		netdev_err(dev, "Illegal MTU value %d (> %d) for XDP mode\n",
5061 			   mtu, (int)MVPP2_MAX_RX_BUF_SIZE);
5062 		return -EINVAL;
5063 	}
5064 
5065 	if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
5066 		if (priv->percpu_pools) {
5067 			netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
5068 			mvpp2_bm_switch_buffers(priv, false);
5069 		}
5070 	} else {
5071 		bool jumbo = false;
5072 		int i;
5073 
5074 		for (i = 0; i < priv->port_count; i++)
5075 			if (priv->port_list[i] != port &&
5076 			    MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
5077 			    MVPP2_BM_LONG_PKT_SIZE) {
5078 				jumbo = true;
5079 				break;
5080 			}
5081 
5082 		/* No port is using jumbo frames */
5083 		if (!jumbo) {
5084 			dev_info(port->dev->dev.parent,
5085 				 "all ports have a low MTU, switching to per-cpu buffers");
5086 			mvpp2_bm_switch_buffers(priv, true);
5087 		}
5088 	}
5089 
5090 	if (running)
5091 		mvpp2_stop_dev(port);
5092 
5093 	err = mvpp2_bm_update_mtu(dev, mtu);
5094 	if (err) {
5095 		netdev_err(dev, "failed to change MTU\n");
5096 		/* Reconfigure BM to the original MTU */
5097 		mvpp2_bm_update_mtu(dev, dev->mtu);
5098 	} else {
5099 		port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
5100 	}
5101 
5102 	if (running) {
5103 		mvpp2_start_dev(port);
5104 		mvpp2_egress_enable(port);
5105 		mvpp2_ingress_enable(port);
5106 	}
5107 
5108 	return err;
5109 }
5110 
mvpp2_check_pagepool_dma(struct mvpp2_port * port)5111 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
5112 {
5113 	enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
5114 	struct mvpp2 *priv = port->priv;
5115 	int err = -1, i;
5116 
5117 	if (!priv->percpu_pools)
5118 		return err;
5119 
5120 	if (!priv->page_pool[0])
5121 		return -ENOMEM;
5122 
5123 	for (i = 0; i < priv->port_count; i++) {
5124 		port = priv->port_list[i];
5125 		if (port->xdp_prog) {
5126 			dma_dir = DMA_BIDIRECTIONAL;
5127 			break;
5128 		}
5129 	}
5130 
5131 	/* All pools are equal in terms of DMA direction */
5132 	if (priv->page_pool[0]->p.dma_dir != dma_dir)
5133 		err = mvpp2_bm_switch_buffers(priv, true);
5134 
5135 	return err;
5136 }
5137 
5138 static void
mvpp2_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)5139 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5140 {
5141 	struct mvpp2_port *port = netdev_priv(dev);
5142 	unsigned int start;
5143 	unsigned int cpu;
5144 
5145 	for_each_possible_cpu(cpu) {
5146 		struct mvpp2_pcpu_stats *cpu_stats;
5147 		u64 rx_packets;
5148 		u64 rx_bytes;
5149 		u64 tx_packets;
5150 		u64 tx_bytes;
5151 
5152 		cpu_stats = per_cpu_ptr(port->stats, cpu);
5153 		do {
5154 			start = u64_stats_fetch_begin(&cpu_stats->syncp);
5155 			rx_packets = cpu_stats->rx_packets;
5156 			rx_bytes   = cpu_stats->rx_bytes;
5157 			tx_packets = cpu_stats->tx_packets;
5158 			tx_bytes   = cpu_stats->tx_bytes;
5159 		} while (u64_stats_fetch_retry(&cpu_stats->syncp, start));
5160 
5161 		stats->rx_packets += rx_packets;
5162 		stats->rx_bytes   += rx_bytes;
5163 		stats->tx_packets += tx_packets;
5164 		stats->tx_bytes   += tx_bytes;
5165 	}
5166 
5167 	stats->rx_errors	= dev->stats.rx_errors;
5168 	stats->rx_dropped	= dev->stats.rx_dropped;
5169 	stats->tx_dropped	= dev->stats.tx_dropped;
5170 }
5171 
mvpp2_set_ts_config(struct mvpp2_port * port,struct ifreq * ifr)5172 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5173 {
5174 	struct hwtstamp_config config;
5175 	void __iomem *ptp;
5176 	u32 gcr, int_mask;
5177 
5178 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5179 		return -EFAULT;
5180 
5181 	if (config.tx_type != HWTSTAMP_TX_OFF &&
5182 	    config.tx_type != HWTSTAMP_TX_ON)
5183 		return -ERANGE;
5184 
5185 	ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
5186 
5187 	int_mask = gcr = 0;
5188 	if (config.tx_type != HWTSTAMP_TX_OFF) {
5189 		gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
5190 		int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
5191 			    MVPP22_PTP_INT_MASK_QUEUE0;
5192 	}
5193 
5194 	/* It seems we must also release the TX reset when enabling the TSU */
5195 	if (config.rx_filter != HWTSTAMP_FILTER_NONE)
5196 		gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
5197 		       MVPP22_PTP_GCR_TX_RESET;
5198 
5199 	if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
5200 		mvpp22_tai_start(port->priv->tai);
5201 
5202 	if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
5203 		config.rx_filter = HWTSTAMP_FILTER_ALL;
5204 		mvpp2_modify(ptp + MVPP22_PTP_GCR,
5205 			     MVPP22_PTP_GCR_RX_RESET |
5206 			     MVPP22_PTP_GCR_TX_RESET |
5207 			     MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5208 		port->rx_hwtstamp = true;
5209 	} else {
5210 		port->rx_hwtstamp = false;
5211 		mvpp2_modify(ptp + MVPP22_PTP_GCR,
5212 			     MVPP22_PTP_GCR_RX_RESET |
5213 			     MVPP22_PTP_GCR_TX_RESET |
5214 			     MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5215 	}
5216 
5217 	mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
5218 		     MVPP22_PTP_INT_MASK_QUEUE1 |
5219 		     MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
5220 
5221 	if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
5222 		mvpp22_tai_stop(port->priv->tai);
5223 
5224 	port->tx_hwtstamp_type = config.tx_type;
5225 
5226 	if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5227 		return -EFAULT;
5228 
5229 	return 0;
5230 }
5231 
mvpp2_get_ts_config(struct mvpp2_port * port,struct ifreq * ifr)5232 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5233 {
5234 	struct hwtstamp_config config;
5235 
5236 	memset(&config, 0, sizeof(config));
5237 
5238 	config.tx_type = port->tx_hwtstamp_type;
5239 	config.rx_filter = port->rx_hwtstamp ?
5240 		HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
5241 
5242 	if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5243 		return -EFAULT;
5244 
5245 	return 0;
5246 }
5247 
mvpp2_ethtool_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)5248 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
5249 				     struct ethtool_ts_info *info)
5250 {
5251 	struct mvpp2_port *port = netdev_priv(dev);
5252 
5253 	if (!port->hwtstamp)
5254 		return -EOPNOTSUPP;
5255 
5256 	info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
5257 	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5258 				SOF_TIMESTAMPING_RX_SOFTWARE |
5259 				SOF_TIMESTAMPING_SOFTWARE |
5260 				SOF_TIMESTAMPING_TX_HARDWARE |
5261 				SOF_TIMESTAMPING_RX_HARDWARE |
5262 				SOF_TIMESTAMPING_RAW_HARDWARE;
5263 	info->tx_types = BIT(HWTSTAMP_TX_OFF) |
5264 			 BIT(HWTSTAMP_TX_ON);
5265 	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
5266 			   BIT(HWTSTAMP_FILTER_ALL);
5267 
5268 	return 0;
5269 }
5270 
mvpp2_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)5271 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5272 {
5273 	struct mvpp2_port *port = netdev_priv(dev);
5274 
5275 	switch (cmd) {
5276 	case SIOCSHWTSTAMP:
5277 		if (port->hwtstamp)
5278 			return mvpp2_set_ts_config(port, ifr);
5279 		break;
5280 
5281 	case SIOCGHWTSTAMP:
5282 		if (port->hwtstamp)
5283 			return mvpp2_get_ts_config(port, ifr);
5284 		break;
5285 	}
5286 
5287 	if (!port->phylink)
5288 		return -ENOTSUPP;
5289 
5290 	return phylink_mii_ioctl(port->phylink, ifr, cmd);
5291 }
5292 
mvpp2_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)5293 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
5294 {
5295 	struct mvpp2_port *port = netdev_priv(dev);
5296 	int ret;
5297 
5298 	ret = mvpp2_prs_vid_entry_add(port, vid);
5299 	if (ret)
5300 		netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
5301 			   MVPP2_PRS_VLAN_FILT_MAX - 1);
5302 	return ret;
5303 }
5304 
mvpp2_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)5305 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
5306 {
5307 	struct mvpp2_port *port = netdev_priv(dev);
5308 
5309 	mvpp2_prs_vid_entry_remove(port, vid);
5310 	return 0;
5311 }
5312 
mvpp2_set_features(struct net_device * dev,netdev_features_t features)5313 static int mvpp2_set_features(struct net_device *dev,
5314 			      netdev_features_t features)
5315 {
5316 	netdev_features_t changed = dev->features ^ features;
5317 	struct mvpp2_port *port = netdev_priv(dev);
5318 
5319 	if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
5320 		if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
5321 			mvpp2_prs_vid_enable_filtering(port);
5322 		} else {
5323 			/* Invalidate all registered VID filters for this
5324 			 * port
5325 			 */
5326 			mvpp2_prs_vid_remove_all(port);
5327 
5328 			mvpp2_prs_vid_disable_filtering(port);
5329 		}
5330 	}
5331 
5332 	if (changed & NETIF_F_RXHASH) {
5333 		if (features & NETIF_F_RXHASH)
5334 			mvpp22_port_rss_enable(port);
5335 		else
5336 			mvpp22_port_rss_disable(port);
5337 	}
5338 
5339 	return 0;
5340 }
5341 
mvpp2_xdp_setup(struct mvpp2_port * port,struct netdev_bpf * bpf)5342 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
5343 {
5344 	struct bpf_prog *prog = bpf->prog, *old_prog;
5345 	bool running = netif_running(port->dev);
5346 	bool reset = !prog != !port->xdp_prog;
5347 
5348 	if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) {
5349 		NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP");
5350 		return -EOPNOTSUPP;
5351 	}
5352 
5353 	if (!port->priv->percpu_pools) {
5354 		NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
5355 		return -EOPNOTSUPP;
5356 	}
5357 
5358 	if (port->ntxqs < num_possible_cpus() * 2) {
5359 		NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
5360 		return -EOPNOTSUPP;
5361 	}
5362 
5363 	/* device is up and bpf is added/removed, must setup the RX queues */
5364 	if (running && reset)
5365 		mvpp2_stop(port->dev);
5366 
5367 	old_prog = xchg(&port->xdp_prog, prog);
5368 	if (old_prog)
5369 		bpf_prog_put(old_prog);
5370 
5371 	/* bpf is just replaced, RXQ and MTU are already setup */
5372 	if (!reset)
5373 		return 0;
5374 
5375 	/* device was up, restore the link */
5376 	if (running)
5377 		mvpp2_open(port->dev);
5378 
5379 	/* Check Page Pool DMA Direction */
5380 	mvpp2_check_pagepool_dma(port);
5381 
5382 	return 0;
5383 }
5384 
mvpp2_xdp(struct net_device * dev,struct netdev_bpf * xdp)5385 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5386 {
5387 	struct mvpp2_port *port = netdev_priv(dev);
5388 
5389 	switch (xdp->command) {
5390 	case XDP_SETUP_PROG:
5391 		return mvpp2_xdp_setup(port, xdp);
5392 	default:
5393 		return -EINVAL;
5394 	}
5395 }
5396 
5397 /* Ethtool methods */
5398 
mvpp2_ethtool_nway_reset(struct net_device * dev)5399 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
5400 {
5401 	struct mvpp2_port *port = netdev_priv(dev);
5402 
5403 	if (!port->phylink)
5404 		return -ENOTSUPP;
5405 
5406 	return phylink_ethtool_nway_reset(port->phylink);
5407 }
5408 
5409 /* Set interrupt coalescing for ethtools */
5410 static int
mvpp2_ethtool_set_coalesce(struct net_device * dev,struct ethtool_coalesce * c,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)5411 mvpp2_ethtool_set_coalesce(struct net_device *dev,
5412 			   struct ethtool_coalesce *c,
5413 			   struct kernel_ethtool_coalesce *kernel_coal,
5414 			   struct netlink_ext_ack *extack)
5415 {
5416 	struct mvpp2_port *port = netdev_priv(dev);
5417 	int queue;
5418 
5419 	for (queue = 0; queue < port->nrxqs; queue++) {
5420 		struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5421 
5422 		rxq->time_coal = c->rx_coalesce_usecs;
5423 		rxq->pkts_coal = c->rx_max_coalesced_frames;
5424 		mvpp2_rx_pkts_coal_set(port, rxq);
5425 		mvpp2_rx_time_coal_set(port, rxq);
5426 	}
5427 
5428 	if (port->has_tx_irqs) {
5429 		port->tx_time_coal = c->tx_coalesce_usecs;
5430 		mvpp2_tx_time_coal_set(port);
5431 	}
5432 
5433 	for (queue = 0; queue < port->ntxqs; queue++) {
5434 		struct mvpp2_tx_queue *txq = port->txqs[queue];
5435 
5436 		txq->done_pkts_coal = c->tx_max_coalesced_frames;
5437 
5438 		if (port->has_tx_irqs)
5439 			mvpp2_tx_pkts_coal_set(port, txq);
5440 	}
5441 
5442 	return 0;
5443 }
5444 
5445 /* get coalescing for ethtools */
5446 static int
mvpp2_ethtool_get_coalesce(struct net_device * dev,struct ethtool_coalesce * c,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)5447 mvpp2_ethtool_get_coalesce(struct net_device *dev,
5448 			   struct ethtool_coalesce *c,
5449 			   struct kernel_ethtool_coalesce *kernel_coal,
5450 			   struct netlink_ext_ack *extack)
5451 {
5452 	struct mvpp2_port *port = netdev_priv(dev);
5453 
5454 	c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
5455 	c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5456 	c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5457 	c->tx_coalesce_usecs       = port->tx_time_coal;
5458 	return 0;
5459 }
5460 
mvpp2_ethtool_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)5461 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5462 				      struct ethtool_drvinfo *drvinfo)
5463 {
5464 	strscpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5465 		sizeof(drvinfo->driver));
5466 	strscpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5467 		sizeof(drvinfo->version));
5468 	strscpy(drvinfo->bus_info, dev_name(&dev->dev),
5469 		sizeof(drvinfo->bus_info));
5470 }
5471 
5472 static void
mvpp2_ethtool_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)5473 mvpp2_ethtool_get_ringparam(struct net_device *dev,
5474 			    struct ethtool_ringparam *ring,
5475 			    struct kernel_ethtool_ringparam *kernel_ring,
5476 			    struct netlink_ext_ack *extack)
5477 {
5478 	struct mvpp2_port *port = netdev_priv(dev);
5479 
5480 	ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5481 	ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5482 	ring->rx_pending = port->rx_ring_size;
5483 	ring->tx_pending = port->tx_ring_size;
5484 }
5485 
5486 static int
mvpp2_ethtool_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)5487 mvpp2_ethtool_set_ringparam(struct net_device *dev,
5488 			    struct ethtool_ringparam *ring,
5489 			    struct kernel_ethtool_ringparam *kernel_ring,
5490 			    struct netlink_ext_ack *extack)
5491 {
5492 	struct mvpp2_port *port = netdev_priv(dev);
5493 	u16 prev_rx_ring_size = port->rx_ring_size;
5494 	u16 prev_tx_ring_size = port->tx_ring_size;
5495 	int err;
5496 
5497 	err = mvpp2_check_ringparam_valid(dev, ring);
5498 	if (err)
5499 		return err;
5500 
5501 	if (!netif_running(dev)) {
5502 		port->rx_ring_size = ring->rx_pending;
5503 		port->tx_ring_size = ring->tx_pending;
5504 		return 0;
5505 	}
5506 
5507 	/* The interface is running, so we have to force a
5508 	 * reallocation of the queues
5509 	 */
5510 	mvpp2_stop_dev(port);
5511 	mvpp2_cleanup_rxqs(port);
5512 	mvpp2_cleanup_txqs(port);
5513 
5514 	port->rx_ring_size = ring->rx_pending;
5515 	port->tx_ring_size = ring->tx_pending;
5516 
5517 	err = mvpp2_setup_rxqs(port);
5518 	if (err) {
5519 		/* Reallocate Rx queues with the original ring size */
5520 		port->rx_ring_size = prev_rx_ring_size;
5521 		ring->rx_pending = prev_rx_ring_size;
5522 		err = mvpp2_setup_rxqs(port);
5523 		if (err)
5524 			goto err_out;
5525 	}
5526 	err = mvpp2_setup_txqs(port);
5527 	if (err) {
5528 		/* Reallocate Tx queues with the original ring size */
5529 		port->tx_ring_size = prev_tx_ring_size;
5530 		ring->tx_pending = prev_tx_ring_size;
5531 		err = mvpp2_setup_txqs(port);
5532 		if (err)
5533 			goto err_clean_rxqs;
5534 	}
5535 
5536 	mvpp2_start_dev(port);
5537 	mvpp2_egress_enable(port);
5538 	mvpp2_ingress_enable(port);
5539 
5540 	return 0;
5541 
5542 err_clean_rxqs:
5543 	mvpp2_cleanup_rxqs(port);
5544 err_out:
5545 	netdev_err(dev, "failed to change ring parameters");
5546 	return err;
5547 }
5548 
mvpp2_ethtool_get_pause_param(struct net_device * dev,struct ethtool_pauseparam * pause)5549 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5550 					  struct ethtool_pauseparam *pause)
5551 {
5552 	struct mvpp2_port *port = netdev_priv(dev);
5553 
5554 	if (!port->phylink)
5555 		return;
5556 
5557 	phylink_ethtool_get_pauseparam(port->phylink, pause);
5558 }
5559 
mvpp2_ethtool_set_pause_param(struct net_device * dev,struct ethtool_pauseparam * pause)5560 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5561 					 struct ethtool_pauseparam *pause)
5562 {
5563 	struct mvpp2_port *port = netdev_priv(dev);
5564 
5565 	if (!port->phylink)
5566 		return -ENOTSUPP;
5567 
5568 	return phylink_ethtool_set_pauseparam(port->phylink, pause);
5569 }
5570 
mvpp2_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)5571 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5572 					    struct ethtool_link_ksettings *cmd)
5573 {
5574 	struct mvpp2_port *port = netdev_priv(dev);
5575 
5576 	if (!port->phylink)
5577 		return -ENOTSUPP;
5578 
5579 	return phylink_ethtool_ksettings_get(port->phylink, cmd);
5580 }
5581 
mvpp2_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)5582 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5583 					    const struct ethtool_link_ksettings *cmd)
5584 {
5585 	struct mvpp2_port *port = netdev_priv(dev);
5586 
5587 	if (!port->phylink)
5588 		return -ENOTSUPP;
5589 
5590 	return phylink_ethtool_ksettings_set(port->phylink, cmd);
5591 }
5592 
mvpp2_ethtool_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rules)5593 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5594 				   struct ethtool_rxnfc *info, u32 *rules)
5595 {
5596 	struct mvpp2_port *port = netdev_priv(dev);
5597 	int ret = 0, i, loc = 0;
5598 
5599 	if (!mvpp22_rss_is_supported(port))
5600 		return -EOPNOTSUPP;
5601 
5602 	switch (info->cmd) {
5603 	case ETHTOOL_GRXFH:
5604 		ret = mvpp2_ethtool_rxfh_get(port, info);
5605 		break;
5606 	case ETHTOOL_GRXRINGS:
5607 		info->data = port->nrxqs;
5608 		break;
5609 	case ETHTOOL_GRXCLSRLCNT:
5610 		info->rule_cnt = port->n_rfs_rules;
5611 		break;
5612 	case ETHTOOL_GRXCLSRULE:
5613 		ret = mvpp2_ethtool_cls_rule_get(port, info);
5614 		break;
5615 	case ETHTOOL_GRXCLSRLALL:
5616 		for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5617 			if (loc == info->rule_cnt) {
5618 				ret = -EMSGSIZE;
5619 				break;
5620 			}
5621 
5622 			if (port->rfs_rules[i])
5623 				rules[loc++] = i;
5624 		}
5625 		break;
5626 	default:
5627 		return -ENOTSUPP;
5628 	}
5629 
5630 	return ret;
5631 }
5632 
mvpp2_ethtool_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info)5633 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5634 				   struct ethtool_rxnfc *info)
5635 {
5636 	struct mvpp2_port *port = netdev_priv(dev);
5637 	int ret = 0;
5638 
5639 	if (!mvpp22_rss_is_supported(port))
5640 		return -EOPNOTSUPP;
5641 
5642 	switch (info->cmd) {
5643 	case ETHTOOL_SRXFH:
5644 		ret = mvpp2_ethtool_rxfh_set(port, info);
5645 		break;
5646 	case ETHTOOL_SRXCLSRLINS:
5647 		ret = mvpp2_ethtool_cls_rule_ins(port, info);
5648 		break;
5649 	case ETHTOOL_SRXCLSRLDEL:
5650 		ret = mvpp2_ethtool_cls_rule_del(port, info);
5651 		break;
5652 	default:
5653 		return -EOPNOTSUPP;
5654 	}
5655 	return ret;
5656 }
5657 
mvpp2_ethtool_get_rxfh_indir_size(struct net_device * dev)5658 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5659 {
5660 	struct mvpp2_port *port = netdev_priv(dev);
5661 
5662 	return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;
5663 }
5664 
mvpp2_ethtool_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)5665 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5666 				  u8 *hfunc)
5667 {
5668 	struct mvpp2_port *port = netdev_priv(dev);
5669 	int ret = 0;
5670 
5671 	if (!mvpp22_rss_is_supported(port))
5672 		return -EOPNOTSUPP;
5673 
5674 	if (indir)
5675 		ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5676 
5677 	if (hfunc)
5678 		*hfunc = ETH_RSS_HASH_CRC32;
5679 
5680 	return ret;
5681 }
5682 
mvpp2_ethtool_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)5683 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5684 				  const u8 *key, const u8 hfunc)
5685 {
5686 	struct mvpp2_port *port = netdev_priv(dev);
5687 	int ret = 0;
5688 
5689 	if (!mvpp22_rss_is_supported(port))
5690 		return -EOPNOTSUPP;
5691 
5692 	if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5693 		return -EOPNOTSUPP;
5694 
5695 	if (key)
5696 		return -EOPNOTSUPP;
5697 
5698 	if (indir)
5699 		ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5700 
5701 	return ret;
5702 }
5703 
mvpp2_ethtool_get_rxfh_context(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc,u32 rss_context)5704 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5705 					  u8 *key, u8 *hfunc, u32 rss_context)
5706 {
5707 	struct mvpp2_port *port = netdev_priv(dev);
5708 	int ret = 0;
5709 
5710 	if (!mvpp22_rss_is_supported(port))
5711 		return -EOPNOTSUPP;
5712 	if (rss_context >= MVPP22_N_RSS_TABLES)
5713 		return -EINVAL;
5714 
5715 	if (hfunc)
5716 		*hfunc = ETH_RSS_HASH_CRC32;
5717 
5718 	if (indir)
5719 		ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5720 
5721 	return ret;
5722 }
5723 
mvpp2_ethtool_set_rxfh_context(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc,u32 * rss_context,bool delete)5724 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5725 					  const u32 *indir, const u8 *key,
5726 					  const u8 hfunc, u32 *rss_context,
5727 					  bool delete)
5728 {
5729 	struct mvpp2_port *port = netdev_priv(dev);
5730 	int ret;
5731 
5732 	if (!mvpp22_rss_is_supported(port))
5733 		return -EOPNOTSUPP;
5734 
5735 	if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5736 		return -EOPNOTSUPP;
5737 
5738 	if (key)
5739 		return -EOPNOTSUPP;
5740 
5741 	if (delete)
5742 		return mvpp22_port_rss_ctx_delete(port, *rss_context);
5743 
5744 	if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5745 		ret = mvpp22_port_rss_ctx_create(port, rss_context);
5746 		if (ret)
5747 			return ret;
5748 	}
5749 
5750 	return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5751 }
5752 /* Device ops */
5753 
5754 static const struct net_device_ops mvpp2_netdev_ops = {
5755 	.ndo_open		= mvpp2_open,
5756 	.ndo_stop		= mvpp2_stop,
5757 	.ndo_start_xmit		= mvpp2_tx,
5758 	.ndo_set_rx_mode	= mvpp2_set_rx_mode,
5759 	.ndo_set_mac_address	= mvpp2_set_mac_address,
5760 	.ndo_change_mtu		= mvpp2_change_mtu,
5761 	.ndo_get_stats64	= mvpp2_get_stats64,
5762 	.ndo_eth_ioctl		= mvpp2_ioctl,
5763 	.ndo_vlan_rx_add_vid	= mvpp2_vlan_rx_add_vid,
5764 	.ndo_vlan_rx_kill_vid	= mvpp2_vlan_rx_kill_vid,
5765 	.ndo_set_features	= mvpp2_set_features,
5766 	.ndo_bpf		= mvpp2_xdp,
5767 	.ndo_xdp_xmit		= mvpp2_xdp_xmit,
5768 };
5769 
5770 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5771 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5772 				     ETHTOOL_COALESCE_MAX_FRAMES,
5773 	.nway_reset		= mvpp2_ethtool_nway_reset,
5774 	.get_link		= ethtool_op_get_link,
5775 	.get_ts_info		= mvpp2_ethtool_get_ts_info,
5776 	.set_coalesce		= mvpp2_ethtool_set_coalesce,
5777 	.get_coalesce		= mvpp2_ethtool_get_coalesce,
5778 	.get_drvinfo		= mvpp2_ethtool_get_drvinfo,
5779 	.get_ringparam		= mvpp2_ethtool_get_ringparam,
5780 	.set_ringparam		= mvpp2_ethtool_set_ringparam,
5781 	.get_strings		= mvpp2_ethtool_get_strings,
5782 	.get_ethtool_stats	= mvpp2_ethtool_get_stats,
5783 	.get_sset_count		= mvpp2_ethtool_get_sset_count,
5784 	.get_pauseparam		= mvpp2_ethtool_get_pause_param,
5785 	.set_pauseparam		= mvpp2_ethtool_set_pause_param,
5786 	.get_link_ksettings	= mvpp2_ethtool_get_link_ksettings,
5787 	.set_link_ksettings	= mvpp2_ethtool_set_link_ksettings,
5788 	.get_rxnfc		= mvpp2_ethtool_get_rxnfc,
5789 	.set_rxnfc		= mvpp2_ethtool_set_rxnfc,
5790 	.get_rxfh_indir_size	= mvpp2_ethtool_get_rxfh_indir_size,
5791 	.get_rxfh		= mvpp2_ethtool_get_rxfh,
5792 	.set_rxfh		= mvpp2_ethtool_set_rxfh,
5793 	.get_rxfh_context	= mvpp2_ethtool_get_rxfh_context,
5794 	.set_rxfh_context	= mvpp2_ethtool_set_rxfh_context,
5795 };
5796 
5797 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5798  * had a single IRQ defined per-port.
5799  */
mvpp2_simple_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5800 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5801 					   struct device_node *port_node)
5802 {
5803 	struct mvpp2_queue_vector *v = &port->qvecs[0];
5804 
5805 	v->first_rxq = 0;
5806 	v->nrxqs = port->nrxqs;
5807 	v->type = MVPP2_QUEUE_VECTOR_SHARED;
5808 	v->sw_thread_id = 0;
5809 	v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5810 	v->port = port;
5811 	v->irq = irq_of_parse_and_map(port_node, 0);
5812 	if (v->irq <= 0)
5813 		return -EINVAL;
5814 	netif_napi_add(port->dev, &v->napi, mvpp2_poll);
5815 
5816 	port->nqvecs = 1;
5817 
5818 	return 0;
5819 }
5820 
mvpp2_multi_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5821 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5822 					  struct device_node *port_node)
5823 {
5824 	struct mvpp2 *priv = port->priv;
5825 	struct mvpp2_queue_vector *v;
5826 	int i, ret;
5827 
5828 	switch (queue_mode) {
5829 	case MVPP2_QDIST_SINGLE_MODE:
5830 		port->nqvecs = priv->nthreads + 1;
5831 		break;
5832 	case MVPP2_QDIST_MULTI_MODE:
5833 		port->nqvecs = priv->nthreads;
5834 		break;
5835 	}
5836 
5837 	for (i = 0; i < port->nqvecs; i++) {
5838 		char irqname[16];
5839 
5840 		v = port->qvecs + i;
5841 
5842 		v->port = port;
5843 		v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5844 		v->sw_thread_id = i;
5845 		v->sw_thread_mask = BIT(i);
5846 
5847 		if (port->flags & MVPP2_F_DT_COMPAT)
5848 			snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5849 		else
5850 			snprintf(irqname, sizeof(irqname), "hif%d", i);
5851 
5852 		if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5853 			v->first_rxq = i;
5854 			v->nrxqs = 1;
5855 		} else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5856 			   i == (port->nqvecs - 1)) {
5857 			v->first_rxq = 0;
5858 			v->nrxqs = port->nrxqs;
5859 			v->type = MVPP2_QUEUE_VECTOR_SHARED;
5860 
5861 			if (port->flags & MVPP2_F_DT_COMPAT)
5862 				strncpy(irqname, "rx-shared", sizeof(irqname));
5863 		}
5864 
5865 		if (port_node)
5866 			v->irq = of_irq_get_byname(port_node, irqname);
5867 		else
5868 			v->irq = fwnode_irq_get(port->fwnode, i);
5869 		if (v->irq <= 0) {
5870 			ret = -EINVAL;
5871 			goto err;
5872 		}
5873 
5874 		netif_napi_add(port->dev, &v->napi, mvpp2_poll);
5875 	}
5876 
5877 	return 0;
5878 
5879 err:
5880 	for (i = 0; i < port->nqvecs; i++)
5881 		irq_dispose_mapping(port->qvecs[i].irq);
5882 	return ret;
5883 }
5884 
mvpp2_queue_vectors_init(struct mvpp2_port * port,struct device_node * port_node)5885 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5886 				    struct device_node *port_node)
5887 {
5888 	if (port->has_tx_irqs)
5889 		return mvpp2_multi_queue_vectors_init(port, port_node);
5890 	else
5891 		return mvpp2_simple_queue_vectors_init(port, port_node);
5892 }
5893 
mvpp2_queue_vectors_deinit(struct mvpp2_port * port)5894 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5895 {
5896 	int i;
5897 
5898 	for (i = 0; i < port->nqvecs; i++)
5899 		irq_dispose_mapping(port->qvecs[i].irq);
5900 }
5901 
5902 /* Configure Rx queue group interrupt for this port */
mvpp2_rx_irqs_setup(struct mvpp2_port * port)5903 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5904 {
5905 	struct mvpp2 *priv = port->priv;
5906 	u32 val;
5907 	int i;
5908 
5909 	if (priv->hw_version == MVPP21) {
5910 		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5911 			    port->nrxqs);
5912 		return;
5913 	}
5914 
5915 	/* Handle the more complicated PPv2.2 and PPv2.3 case */
5916 	for (i = 0; i < port->nqvecs; i++) {
5917 		struct mvpp2_queue_vector *qv = port->qvecs + i;
5918 
5919 		if (!qv->nrxqs)
5920 			continue;
5921 
5922 		val = qv->sw_thread_id;
5923 		val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5924 		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5925 
5926 		val = qv->first_rxq;
5927 		val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5928 		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5929 	}
5930 }
5931 
5932 /* Initialize port HW */
mvpp2_port_init(struct mvpp2_port * port)5933 static int mvpp2_port_init(struct mvpp2_port *port)
5934 {
5935 	struct device *dev = port->dev->dev.parent;
5936 	struct mvpp2 *priv = port->priv;
5937 	struct mvpp2_txq_pcpu *txq_pcpu;
5938 	unsigned int thread;
5939 	int queue, err, val;
5940 
5941 	/* Checks for hardware constraints */
5942 	if (port->first_rxq + port->nrxqs >
5943 	    MVPP2_MAX_PORTS * priv->max_port_rxqs)
5944 		return -EINVAL;
5945 
5946 	if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5947 		return -EINVAL;
5948 
5949 	/* Disable port */
5950 	mvpp2_egress_disable(port);
5951 	mvpp2_port_disable(port);
5952 
5953 	if (mvpp2_is_xlg(port->phy_interface)) {
5954 		val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5955 		val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5956 		val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5957 		writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5958 	} else {
5959 		val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5960 		val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5961 		val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5962 		writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5963 	}
5964 
5965 	port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5966 
5967 	port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5968 				  GFP_KERNEL);
5969 	if (!port->txqs)
5970 		return -ENOMEM;
5971 
5972 	/* Associate physical Tx queues to this port and initialize.
5973 	 * The mapping is predefined.
5974 	 */
5975 	for (queue = 0; queue < port->ntxqs; queue++) {
5976 		int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5977 		struct mvpp2_tx_queue *txq;
5978 
5979 		txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5980 		if (!txq) {
5981 			err = -ENOMEM;
5982 			goto err_free_percpu;
5983 		}
5984 
5985 		txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5986 		if (!txq->pcpu) {
5987 			err = -ENOMEM;
5988 			goto err_free_percpu;
5989 		}
5990 
5991 		txq->id = queue_phy_id;
5992 		txq->log_id = queue;
5993 		txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5994 		for (thread = 0; thread < priv->nthreads; thread++) {
5995 			txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5996 			txq_pcpu->thread = thread;
5997 		}
5998 
5999 		port->txqs[queue] = txq;
6000 	}
6001 
6002 	port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
6003 				  GFP_KERNEL);
6004 	if (!port->rxqs) {
6005 		err = -ENOMEM;
6006 		goto err_free_percpu;
6007 	}
6008 
6009 	/* Allocate and initialize Rx queue for this port */
6010 	for (queue = 0; queue < port->nrxqs; queue++) {
6011 		struct mvpp2_rx_queue *rxq;
6012 
6013 		/* Map physical Rx queue to port's logical Rx queue */
6014 		rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
6015 		if (!rxq) {
6016 			err = -ENOMEM;
6017 			goto err_free_percpu;
6018 		}
6019 		/* Map this Rx queue to a physical queue */
6020 		rxq->id = port->first_rxq + queue;
6021 		rxq->port = port->id;
6022 		rxq->logic_rxq = queue;
6023 
6024 		port->rxqs[queue] = rxq;
6025 	}
6026 
6027 	mvpp2_rx_irqs_setup(port);
6028 
6029 	/* Create Rx descriptor rings */
6030 	for (queue = 0; queue < port->nrxqs; queue++) {
6031 		struct mvpp2_rx_queue *rxq = port->rxqs[queue];
6032 
6033 		rxq->size = port->rx_ring_size;
6034 		rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
6035 		rxq->time_coal = MVPP2_RX_COAL_USEC;
6036 	}
6037 
6038 	mvpp2_ingress_disable(port);
6039 
6040 	/* Port default configuration */
6041 	mvpp2_defaults_set(port);
6042 
6043 	/* Port's classifier configuration */
6044 	mvpp2_cls_oversize_rxq_set(port);
6045 	mvpp2_cls_port_config(port);
6046 
6047 	if (mvpp22_rss_is_supported(port))
6048 		mvpp22_port_rss_init(port);
6049 
6050 	/* Provide an initial Rx packet size */
6051 	port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6052 
6053 	/* Initialize pools for swf */
6054 	err = mvpp2_swf_bm_pool_init(port);
6055 	if (err)
6056 		goto err_free_percpu;
6057 
6058 	/* Clear all port stats */
6059 	mvpp2_read_stats(port);
6060 	memset(port->ethtool_stats, 0,
6061 	       MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6062 
6063 	return 0;
6064 
6065 err_free_percpu:
6066 	for (queue = 0; queue < port->ntxqs; queue++) {
6067 		if (!port->txqs[queue])
6068 			continue;
6069 		free_percpu(port->txqs[queue]->pcpu);
6070 	}
6071 	return err;
6072 }
6073 
mvpp22_port_has_legacy_tx_irqs(struct device_node * port_node,unsigned long * flags)6074 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
6075 					   unsigned long *flags)
6076 {
6077 	char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
6078 			  "tx-cpu3" };
6079 	int i;
6080 
6081 	for (i = 0; i < 5; i++)
6082 		if (of_property_match_string(port_node, "interrupt-names",
6083 					     irqs[i]) < 0)
6084 			return false;
6085 
6086 	*flags |= MVPP2_F_DT_COMPAT;
6087 	return true;
6088 }
6089 
6090 /* Checks if the port dt description has the required Tx interrupts:
6091  * - PPv2.1: there are no such interrupts.
6092  * - PPv2.2 and PPv2.3:
6093  *   - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6094  *   - The new ones have: "hifX" with X in [0..8]
6095  *
6096  * All those variants are supported to keep the backward compatibility.
6097  */
mvpp2_port_has_irqs(struct mvpp2 * priv,struct device_node * port_node,unsigned long * flags)6098 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
6099 				struct device_node *port_node,
6100 				unsigned long *flags)
6101 {
6102 	char name[5];
6103 	int i;
6104 
6105 	/* ACPI */
6106 	if (!port_node)
6107 		return true;
6108 
6109 	if (priv->hw_version == MVPP21)
6110 		return false;
6111 
6112 	if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
6113 		return true;
6114 
6115 	for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6116 		snprintf(name, 5, "hif%d", i);
6117 		if (of_property_match_string(port_node, "interrupt-names",
6118 					     name) < 0)
6119 			return false;
6120 	}
6121 
6122 	return true;
6123 }
6124 
mvpp2_port_copy_mac_addr(struct net_device * dev,struct mvpp2 * priv,struct fwnode_handle * fwnode,char ** mac_from)6125 static int mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
6126 				    struct fwnode_handle *fwnode,
6127 				    char **mac_from)
6128 {
6129 	struct mvpp2_port *port = netdev_priv(dev);
6130 	char hw_mac_addr[ETH_ALEN] = {0};
6131 	char fw_mac_addr[ETH_ALEN];
6132 	int ret;
6133 
6134 	if (!fwnode_get_mac_address(fwnode, fw_mac_addr)) {
6135 		*mac_from = "firmware node";
6136 		eth_hw_addr_set(dev, fw_mac_addr);
6137 		return 0;
6138 	}
6139 
6140 	if (priv->hw_version == MVPP21) {
6141 		mvpp21_get_mac_address(port, hw_mac_addr);
6142 		if (is_valid_ether_addr(hw_mac_addr)) {
6143 			*mac_from = "hardware";
6144 			eth_hw_addr_set(dev, hw_mac_addr);
6145 			return 0;
6146 		}
6147 	}
6148 
6149 	/* Only valid on OF enabled platforms */
6150 	ret = of_get_mac_address_nvmem(to_of_node(fwnode), fw_mac_addr);
6151 	if (ret == -EPROBE_DEFER)
6152 		return ret;
6153 	if (!ret) {
6154 		*mac_from = "nvmem cell";
6155 		eth_hw_addr_set(dev, fw_mac_addr);
6156 		return 0;
6157 	}
6158 
6159 	*mac_from = "random";
6160 	eth_hw_addr_random(dev);
6161 
6162 	return 0;
6163 }
6164 
mvpp2_phylink_to_port(struct phylink_config * config)6165 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
6166 {
6167 	return container_of(config, struct mvpp2_port, phylink_config);
6168 }
6169 
mvpp2_pcs_xlg_to_port(struct phylink_pcs * pcs)6170 static struct mvpp2_port *mvpp2_pcs_xlg_to_port(struct phylink_pcs *pcs)
6171 {
6172 	return container_of(pcs, struct mvpp2_port, pcs_xlg);
6173 }
6174 
mvpp2_pcs_gmac_to_port(struct phylink_pcs * pcs)6175 static struct mvpp2_port *mvpp2_pcs_gmac_to_port(struct phylink_pcs *pcs)
6176 {
6177 	return container_of(pcs, struct mvpp2_port, pcs_gmac);
6178 }
6179 
mvpp2_xlg_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)6180 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
6181 				    struct phylink_link_state *state)
6182 {
6183 	struct mvpp2_port *port = mvpp2_pcs_xlg_to_port(pcs);
6184 	u32 val;
6185 
6186 	if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER)
6187 		state->speed = SPEED_5000;
6188 	else
6189 		state->speed = SPEED_10000;
6190 	state->duplex = 1;
6191 	state->an_complete = 1;
6192 
6193 	val = readl(port->base + MVPP22_XLG_STATUS);
6194 	state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
6195 
6196 	state->pause = 0;
6197 	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6198 	if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
6199 		state->pause |= MLO_PAUSE_TX;
6200 	if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
6201 		state->pause |= MLO_PAUSE_RX;
6202 }
6203 
mvpp2_xlg_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)6204 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
6205 				phy_interface_t interface,
6206 				const unsigned long *advertising,
6207 				bool permit_pause_to_mac)
6208 {
6209 	return 0;
6210 }
6211 
6212 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
6213 	.pcs_get_state = mvpp2_xlg_pcs_get_state,
6214 	.pcs_config = mvpp2_xlg_pcs_config,
6215 };
6216 
mvpp2_gmac_pcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)6217 static int mvpp2_gmac_pcs_validate(struct phylink_pcs *pcs,
6218 				   unsigned long *supported,
6219 				   const struct phylink_link_state *state)
6220 {
6221 	/* When in 802.3z mode, we must have AN enabled:
6222 	 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
6223 	 * When <PortType> = 1 (1000BASE-X) this field must be set to 1.
6224 	 */
6225 	if (phy_interface_mode_is_8023z(state->interface) &&
6226 	    !phylink_test(state->advertising, Autoneg))
6227 		return -EINVAL;
6228 
6229 	return 0;
6230 }
6231 
mvpp2_gmac_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)6232 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
6233 				     struct phylink_link_state *state)
6234 {
6235 	struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6236 	u32 val;
6237 
6238 	val = readl(port->base + MVPP2_GMAC_STATUS0);
6239 
6240 	state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
6241 	state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
6242 	state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
6243 
6244 	switch (port->phy_interface) {
6245 	case PHY_INTERFACE_MODE_1000BASEX:
6246 		state->speed = SPEED_1000;
6247 		break;
6248 	case PHY_INTERFACE_MODE_2500BASEX:
6249 		state->speed = SPEED_2500;
6250 		break;
6251 	default:
6252 		if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
6253 			state->speed = SPEED_1000;
6254 		else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
6255 			state->speed = SPEED_100;
6256 		else
6257 			state->speed = SPEED_10;
6258 	}
6259 
6260 	state->pause = 0;
6261 	if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
6262 		state->pause |= MLO_PAUSE_RX;
6263 	if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
6264 		state->pause |= MLO_PAUSE_TX;
6265 }
6266 
mvpp2_gmac_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)6267 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
6268 				 phy_interface_t interface,
6269 				 const unsigned long *advertising,
6270 				 bool permit_pause_to_mac)
6271 {
6272 	struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6273 	u32 mask, val, an, old_an, changed;
6274 
6275 	mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
6276 	       MVPP2_GMAC_IN_BAND_AUTONEG |
6277 	       MVPP2_GMAC_AN_SPEED_EN |
6278 	       MVPP2_GMAC_FLOW_CTRL_AUTONEG |
6279 	       MVPP2_GMAC_AN_DUPLEX_EN;
6280 
6281 	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
6282 		mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
6283 			MVPP2_GMAC_CONFIG_GMII_SPEED |
6284 			MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6285 		val = MVPP2_GMAC_IN_BAND_AUTONEG;
6286 
6287 		if (interface == PHY_INTERFACE_MODE_SGMII) {
6288 			/* SGMII mode receives the speed and duplex from PHY */
6289 			val |= MVPP2_GMAC_AN_SPEED_EN |
6290 			       MVPP2_GMAC_AN_DUPLEX_EN;
6291 		} else {
6292 			/* 802.3z mode has fixed speed and duplex */
6293 			val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
6294 			       MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6295 
6296 			/* The FLOW_CTRL_AUTONEG bit selects either the hardware
6297 			 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
6298 			 * manually controls the GMAC pause modes.
6299 			 */
6300 			if (permit_pause_to_mac)
6301 				val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
6302 
6303 			/* Configure advertisement bits */
6304 			mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
6305 			if (phylink_test(advertising, Pause))
6306 				val |= MVPP2_GMAC_FC_ADV_EN;
6307 			if (phylink_test(advertising, Asym_Pause))
6308 				val |= MVPP2_GMAC_FC_ADV_ASM_EN;
6309 		}
6310 	} else {
6311 		val = 0;
6312 	}
6313 
6314 	old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6315 	an = (an & ~mask) | val;
6316 	changed = an ^ old_an;
6317 	if (changed)
6318 		writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6319 
6320 	/* We are only interested in the advertisement bits changing */
6321 	return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
6322 }
6323 
mvpp2_gmac_pcs_an_restart(struct phylink_pcs * pcs)6324 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
6325 {
6326 	struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs);
6327 	u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6328 
6329 	writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
6330 	       port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6331 	writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
6332 	       port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6333 }
6334 
6335 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
6336 	.pcs_validate = mvpp2_gmac_pcs_validate,
6337 	.pcs_get_state = mvpp2_gmac_pcs_get_state,
6338 	.pcs_config = mvpp2_gmac_pcs_config,
6339 	.pcs_an_restart = mvpp2_gmac_pcs_an_restart,
6340 };
6341 
mvpp2_xlg_config(struct mvpp2_port * port,unsigned int mode,const struct phylink_link_state * state)6342 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
6343 			     const struct phylink_link_state *state)
6344 {
6345 	u32 val;
6346 
6347 	mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6348 		     MVPP22_XLG_CTRL0_MAC_RESET_DIS,
6349 		     MVPP22_XLG_CTRL0_MAC_RESET_DIS);
6350 	mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
6351 		     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
6352 		     MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
6353 		     MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
6354 		     MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
6355 
6356 	/* Wait for reset to deassert */
6357 	do {
6358 		val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6359 	} while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
6360 }
6361 
mvpp2_gmac_config(struct mvpp2_port * port,unsigned int mode,const struct phylink_link_state * state)6362 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
6363 			      const struct phylink_link_state *state)
6364 {
6365 	u32 old_ctrl0, ctrl0;
6366 	u32 old_ctrl2, ctrl2;
6367 	u32 old_ctrl4, ctrl4;
6368 
6369 	old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
6370 	old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
6371 	old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
6372 
6373 	ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
6374 	ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
6375 
6376 	/* Configure port type */
6377 	if (phy_interface_mode_is_8023z(state->interface)) {
6378 		ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
6379 		ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6380 		ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6381 			 MVPP22_CTRL4_DP_CLK_SEL |
6382 			 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6383 	} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6384 		ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
6385 		ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6386 		ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6387 			 MVPP22_CTRL4_DP_CLK_SEL |
6388 			 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6389 	} else if (phy_interface_mode_is_rgmii(state->interface)) {
6390 		ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
6391 		ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
6392 			 MVPP22_CTRL4_SYNC_BYPASS_DIS |
6393 			 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6394 	}
6395 
6396 	/* Configure negotiation style */
6397 	if (!phylink_autoneg_inband(mode)) {
6398 		/* Phy or fixed speed - no in-band AN, nothing to do, leave the
6399 		 * configured speed, duplex and flow control as-is.
6400 		 */
6401 	} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6402 		/* SGMII in-band mode receives the speed and duplex from
6403 		 * the PHY. Flow control information is not received. */
6404 	} else if (phy_interface_mode_is_8023z(state->interface)) {
6405 		/* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6406 		 * they negotiate duplex: they are always operating with a fixed
6407 		 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6408 		 * speed and full duplex here.
6409 		 */
6410 		ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6411 	}
6412 
6413 	if (old_ctrl0 != ctrl0)
6414 		writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6415 	if (old_ctrl2 != ctrl2)
6416 		writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6417 	if (old_ctrl4 != ctrl4)
6418 		writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6419 }
6420 
mvpp2_select_pcs(struct phylink_config * config,phy_interface_t interface)6421 static struct phylink_pcs *mvpp2_select_pcs(struct phylink_config *config,
6422 					    phy_interface_t interface)
6423 {
6424 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6425 
6426 	/* Select the appropriate PCS operations depending on the
6427 	 * configured interface mode. We will only switch to a mode
6428 	 * that the validate() checks have already passed.
6429 	 */
6430 	if (mvpp2_is_xlg(interface))
6431 		return &port->pcs_xlg;
6432 	else
6433 		return &port->pcs_gmac;
6434 }
6435 
mvpp2_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6436 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6437 			     phy_interface_t interface)
6438 {
6439 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6440 
6441 	/* Check for invalid configuration */
6442 	if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6443 		netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6444 		return -EINVAL;
6445 	}
6446 
6447 	if (port->phy_interface != interface ||
6448 	    phylink_autoneg_inband(mode)) {
6449 		/* Force the link down when changing the interface or if in
6450 		 * in-band mode to ensure we do not change the configuration
6451 		 * while the hardware is indicating link is up. We force both
6452 		 * XLG and GMAC down to ensure that they're both in a known
6453 		 * state.
6454 		 */
6455 		mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6456 			     MVPP2_GMAC_FORCE_LINK_PASS |
6457 			     MVPP2_GMAC_FORCE_LINK_DOWN,
6458 			     MVPP2_GMAC_FORCE_LINK_DOWN);
6459 
6460 		if (mvpp2_port_supports_xlg(port))
6461 			mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6462 				     MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6463 				     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6464 				     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6465 	}
6466 
6467 	/* Make sure the port is disabled when reconfiguring the mode */
6468 	mvpp2_port_disable(port);
6469 
6470 	if (port->phy_interface != interface) {
6471 		/* Place GMAC into reset */
6472 		mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6473 			     MVPP2_GMAC_PORT_RESET_MASK,
6474 			     MVPP2_GMAC_PORT_RESET_MASK);
6475 
6476 		if (port->priv->hw_version >= MVPP22) {
6477 			mvpp22_gop_mask_irq(port);
6478 
6479 			phy_power_off(port->comphy);
6480 
6481 			/* Reconfigure the serdes lanes */
6482 			mvpp22_mode_reconfigure(port, interface);
6483 		}
6484 	}
6485 
6486 	return 0;
6487 }
6488 
mvpp2_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)6489 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6490 			     const struct phylink_link_state *state)
6491 {
6492 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6493 
6494 	/* mac (re)configuration */
6495 	if (mvpp2_is_xlg(state->interface))
6496 		mvpp2_xlg_config(port, mode, state);
6497 	else if (phy_interface_mode_is_rgmii(state->interface) ||
6498 		 phy_interface_mode_is_8023z(state->interface) ||
6499 		 state->interface == PHY_INTERFACE_MODE_SGMII)
6500 		mvpp2_gmac_config(port, mode, state);
6501 
6502 	if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6503 		mvpp2_port_loopback_set(port, state);
6504 }
6505 
mvpp2_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6506 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6507 			    phy_interface_t interface)
6508 {
6509 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6510 
6511 	if (port->priv->hw_version >= MVPP22 &&
6512 	    port->phy_interface != interface) {
6513 		port->phy_interface = interface;
6514 
6515 		/* Unmask interrupts */
6516 		mvpp22_gop_unmask_irq(port);
6517 	}
6518 
6519 	if (!mvpp2_is_xlg(interface)) {
6520 		/* Release GMAC reset and wait */
6521 		mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6522 			     MVPP2_GMAC_PORT_RESET_MASK, 0);
6523 
6524 		while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6525 		       MVPP2_GMAC_PORT_RESET_MASK)
6526 			continue;
6527 	}
6528 
6529 	mvpp2_port_enable(port);
6530 
6531 	/* Allow the link to come up if in in-band mode, otherwise the
6532 	 * link is forced via mac_link_down()/mac_link_up()
6533 	 */
6534 	if (phylink_autoneg_inband(mode)) {
6535 		if (mvpp2_is_xlg(interface))
6536 			mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6537 				     MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6538 				     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6539 		else
6540 			mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6541 				     MVPP2_GMAC_FORCE_LINK_PASS |
6542 				     MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6543 	}
6544 
6545 	return 0;
6546 }
6547 
mvpp2_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)6548 static void mvpp2_mac_link_up(struct phylink_config *config,
6549 			      struct phy_device *phy,
6550 			      unsigned int mode, phy_interface_t interface,
6551 			      int speed, int duplex,
6552 			      bool tx_pause, bool rx_pause)
6553 {
6554 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6555 	u32 val;
6556 	int i;
6557 
6558 	if (mvpp2_is_xlg(interface)) {
6559 		if (!phylink_autoneg_inband(mode)) {
6560 			val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6561 			if (tx_pause)
6562 				val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6563 			if (rx_pause)
6564 				val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6565 
6566 			mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6567 				     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6568 				     MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6569 				     MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6570 				     MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6571 		}
6572 	} else {
6573 		if (!phylink_autoneg_inband(mode)) {
6574 			val = MVPP2_GMAC_FORCE_LINK_PASS;
6575 
6576 			if (speed == SPEED_1000 || speed == SPEED_2500)
6577 				val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6578 			else if (speed == SPEED_100)
6579 				val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6580 
6581 			if (duplex == DUPLEX_FULL)
6582 				val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6583 
6584 			mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6585 				     MVPP2_GMAC_FORCE_LINK_DOWN |
6586 				     MVPP2_GMAC_FORCE_LINK_PASS |
6587 				     MVPP2_GMAC_CONFIG_MII_SPEED |
6588 				     MVPP2_GMAC_CONFIG_GMII_SPEED |
6589 				     MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6590 		}
6591 
6592 		/* We can always update the flow control enable bits;
6593 		 * these will only be effective if flow control AN
6594 		 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6595 		 */
6596 		val = 0;
6597 		if (tx_pause)
6598 			val |= MVPP22_CTRL4_TX_FC_EN;
6599 		if (rx_pause)
6600 			val |= MVPP22_CTRL4_RX_FC_EN;
6601 
6602 		mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6603 			     MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6604 			     val);
6605 	}
6606 
6607 	if (port->priv->global_tx_fc) {
6608 		port->tx_fc = tx_pause;
6609 		if (tx_pause)
6610 			mvpp2_rxq_enable_fc(port);
6611 		else
6612 			mvpp2_rxq_disable_fc(port);
6613 		if (port->priv->percpu_pools) {
6614 			for (i = 0; i < port->nrxqs; i++)
6615 				mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
6616 		} else {
6617 			mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
6618 			mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
6619 		}
6620 		if (port->priv->hw_version == MVPP23)
6621 			mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
6622 	}
6623 
6624 	mvpp2_port_enable(port);
6625 
6626 	mvpp2_egress_enable(port);
6627 	mvpp2_ingress_enable(port);
6628 	netif_tx_wake_all_queues(port->dev);
6629 }
6630 
mvpp2_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)6631 static void mvpp2_mac_link_down(struct phylink_config *config,
6632 				unsigned int mode, phy_interface_t interface)
6633 {
6634 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6635 	u32 val;
6636 
6637 	if (!phylink_autoneg_inband(mode)) {
6638 		if (mvpp2_is_xlg(interface)) {
6639 			val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6640 			val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6641 			val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6642 			writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6643 		} else {
6644 			val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6645 			val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6646 			val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6647 			writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6648 		}
6649 	}
6650 
6651 	netif_tx_stop_all_queues(port->dev);
6652 	mvpp2_egress_disable(port);
6653 	mvpp2_ingress_disable(port);
6654 
6655 	mvpp2_port_disable(port);
6656 }
6657 
6658 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6659 	.mac_select_pcs = mvpp2_select_pcs,
6660 	.mac_prepare = mvpp2_mac_prepare,
6661 	.mac_config = mvpp2_mac_config,
6662 	.mac_finish = mvpp2_mac_finish,
6663 	.mac_link_up = mvpp2_mac_link_up,
6664 	.mac_link_down = mvpp2_mac_link_down,
6665 };
6666 
6667 /* Work-around for ACPI */
mvpp2_acpi_start(struct mvpp2_port * port)6668 static void mvpp2_acpi_start(struct mvpp2_port *port)
6669 {
6670 	/* Phylink isn't used as of now for ACPI, so the MAC has to be
6671 	 * configured manually when the interface is started. This will
6672 	 * be removed as soon as the phylink ACPI support lands in.
6673 	 */
6674 	struct phylink_link_state state = {
6675 		.interface = port->phy_interface,
6676 	};
6677 	struct phylink_pcs *pcs;
6678 
6679 	pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface);
6680 
6681 	mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6682 			  port->phy_interface);
6683 	mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6684 	pcs->ops->pcs_config(pcs, PHYLINK_PCS_NEG_INBAND_ENABLED,
6685 			     port->phy_interface, state.advertising,
6686 			     false);
6687 	mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6688 			 port->phy_interface);
6689 	mvpp2_mac_link_up(&port->phylink_config, NULL,
6690 			  MLO_AN_INBAND, port->phy_interface,
6691 			  SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6692 }
6693 
6694 /* In order to ensure backward compatibility for ACPI, check if the port
6695  * firmware node comprises the necessary description allowing to use phylink.
6696  */
mvpp2_use_acpi_compat_mode(struct fwnode_handle * port_fwnode)6697 static bool mvpp2_use_acpi_compat_mode(struct fwnode_handle *port_fwnode)
6698 {
6699 	if (!is_acpi_node(port_fwnode))
6700 		return false;
6701 
6702 	return (!fwnode_property_present(port_fwnode, "phy-handle") &&
6703 		!fwnode_property_present(port_fwnode, "managed") &&
6704 		!fwnode_get_named_child_node(port_fwnode, "fixed-link"));
6705 }
6706 
6707 /* Ports initialization */
mvpp2_port_probe(struct platform_device * pdev,struct fwnode_handle * port_fwnode,struct mvpp2 * priv)6708 static int mvpp2_port_probe(struct platform_device *pdev,
6709 			    struct fwnode_handle *port_fwnode,
6710 			    struct mvpp2 *priv)
6711 {
6712 	struct phy *comphy = NULL;
6713 	struct mvpp2_port *port;
6714 	struct mvpp2_port_pcpu *port_pcpu;
6715 	struct device_node *port_node = to_of_node(port_fwnode);
6716 	netdev_features_t features;
6717 	struct net_device *dev;
6718 	struct phylink *phylink;
6719 	char *mac_from = "";
6720 	unsigned int ntxqs, nrxqs, thread;
6721 	unsigned long flags = 0;
6722 	bool has_tx_irqs;
6723 	u32 id;
6724 	int phy_mode;
6725 	int err, i;
6726 
6727 	has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6728 	if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6729 		dev_err(&pdev->dev,
6730 			"not enough IRQs to support multi queue mode\n");
6731 		return -EINVAL;
6732 	}
6733 
6734 	ntxqs = MVPP2_MAX_TXQ;
6735 	nrxqs = mvpp2_get_nrxqs(priv);
6736 
6737 	dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6738 	if (!dev)
6739 		return -ENOMEM;
6740 
6741 	phy_mode = fwnode_get_phy_mode(port_fwnode);
6742 	if (phy_mode < 0) {
6743 		dev_err(&pdev->dev, "incorrect phy mode\n");
6744 		err = phy_mode;
6745 		goto err_free_netdev;
6746 	}
6747 
6748 	/*
6749 	 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6750 	 * Existing usage of 10GBASE-KR is not correct; no backplane
6751 	 * negotiation is done, and this driver does not actually support
6752 	 * 10GBASE-KR.
6753 	 */
6754 	if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6755 		phy_mode = PHY_INTERFACE_MODE_10GBASER;
6756 
6757 	if (port_node) {
6758 		comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6759 		if (IS_ERR(comphy)) {
6760 			if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6761 				err = -EPROBE_DEFER;
6762 				goto err_free_netdev;
6763 			}
6764 			comphy = NULL;
6765 		}
6766 	}
6767 
6768 	if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6769 		err = -EINVAL;
6770 		dev_err(&pdev->dev, "missing port-id value\n");
6771 		goto err_free_netdev;
6772 	}
6773 
6774 	dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6775 	dev->watchdog_timeo = 5 * HZ;
6776 	dev->netdev_ops = &mvpp2_netdev_ops;
6777 	dev->ethtool_ops = &mvpp2_eth_tool_ops;
6778 
6779 	port = netdev_priv(dev);
6780 	port->dev = dev;
6781 	port->fwnode = port_fwnode;
6782 	port->ntxqs = ntxqs;
6783 	port->nrxqs = nrxqs;
6784 	port->priv = priv;
6785 	port->has_tx_irqs = has_tx_irqs;
6786 	port->flags = flags;
6787 
6788 	err = mvpp2_queue_vectors_init(port, port_node);
6789 	if (err)
6790 		goto err_free_netdev;
6791 
6792 	if (port_node)
6793 		port->port_irq = of_irq_get_byname(port_node, "link");
6794 	else
6795 		port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6796 	if (port->port_irq == -EPROBE_DEFER) {
6797 		err = -EPROBE_DEFER;
6798 		goto err_deinit_qvecs;
6799 	}
6800 	if (port->port_irq <= 0)
6801 		/* the link irq is optional */
6802 		port->port_irq = 0;
6803 
6804 	if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6805 		port->flags |= MVPP2_F_LOOPBACK;
6806 
6807 	port->id = id;
6808 	if (priv->hw_version == MVPP21)
6809 		port->first_rxq = port->id * port->nrxqs;
6810 	else
6811 		port->first_rxq = port->id * priv->max_port_rxqs;
6812 
6813 	port->of_node = port_node;
6814 	port->phy_interface = phy_mode;
6815 	port->comphy = comphy;
6816 
6817 	if (priv->hw_version == MVPP21) {
6818 		port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6819 		if (IS_ERR(port->base)) {
6820 			err = PTR_ERR(port->base);
6821 			goto err_free_irq;
6822 		}
6823 
6824 		port->stats_base = port->priv->lms_base +
6825 				   MVPP21_MIB_COUNTERS_OFFSET +
6826 				   port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6827 	} else {
6828 		if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6829 					     &port->gop_id)) {
6830 			err = -EINVAL;
6831 			dev_err(&pdev->dev, "missing gop-port-id value\n");
6832 			goto err_deinit_qvecs;
6833 		}
6834 
6835 		port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6836 		port->stats_base = port->priv->iface_base +
6837 				   MVPP22_MIB_COUNTERS_OFFSET +
6838 				   port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6839 
6840 		/* We may want a property to describe whether we should use
6841 		 * MAC hardware timestamping.
6842 		 */
6843 		if (priv->tai)
6844 			port->hwtstamp = true;
6845 	}
6846 
6847 	/* Alloc per-cpu and ethtool stats */
6848 	port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6849 	if (!port->stats) {
6850 		err = -ENOMEM;
6851 		goto err_free_irq;
6852 	}
6853 
6854 	port->ethtool_stats = devm_kcalloc(&pdev->dev,
6855 					   MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6856 					   sizeof(u64), GFP_KERNEL);
6857 	if (!port->ethtool_stats) {
6858 		err = -ENOMEM;
6859 		goto err_free_stats;
6860 	}
6861 
6862 	mutex_init(&port->gather_stats_lock);
6863 	INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6864 
6865 	err = mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6866 	if (err < 0)
6867 		goto err_free_stats;
6868 
6869 	port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6870 	port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6871 	SET_NETDEV_DEV(dev, &pdev->dev);
6872 
6873 	err = mvpp2_port_init(port);
6874 	if (err < 0) {
6875 		dev_err(&pdev->dev, "failed to init port %d\n", id);
6876 		goto err_free_stats;
6877 	}
6878 
6879 	mvpp2_port_periodic_xon_disable(port);
6880 
6881 	mvpp2_mac_reset_assert(port);
6882 	mvpp22_pcs_reset_assert(port);
6883 
6884 	port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6885 	if (!port->pcpu) {
6886 		err = -ENOMEM;
6887 		goto err_free_txq_pcpu;
6888 	}
6889 
6890 	if (!port->has_tx_irqs) {
6891 		for (thread = 0; thread < priv->nthreads; thread++) {
6892 			port_pcpu = per_cpu_ptr(port->pcpu, thread);
6893 
6894 			hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6895 				     HRTIMER_MODE_REL_PINNED_SOFT);
6896 			port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6897 			port_pcpu->timer_scheduled = false;
6898 			port_pcpu->dev = dev;
6899 		}
6900 	}
6901 
6902 	features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6903 		   NETIF_F_TSO;
6904 	dev->features = features | NETIF_F_RXCSUM;
6905 	dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6906 			    NETIF_F_HW_VLAN_CTAG_FILTER;
6907 
6908 	if (mvpp22_rss_is_supported(port)) {
6909 		dev->hw_features |= NETIF_F_RXHASH;
6910 		dev->features |= NETIF_F_NTUPLE;
6911 	}
6912 
6913 	if (!port->priv->percpu_pools)
6914 		mvpp2_set_hw_csum(port, port->pool_long->id);
6915 	else if (port->ntxqs >= num_possible_cpus() * 2)
6916 		dev->xdp_features = NETDEV_XDP_ACT_BASIC |
6917 				    NETDEV_XDP_ACT_REDIRECT |
6918 				    NETDEV_XDP_ACT_NDO_XMIT;
6919 
6920 	dev->vlan_features |= features;
6921 	netif_set_tso_max_segs(dev, MVPP2_MAX_TSO_SEGS);
6922 
6923 	dev->priv_flags |= IFF_UNICAST_FLT;
6924 
6925 	/* MTU range: 68 - 9704 */
6926 	dev->min_mtu = ETH_MIN_MTU;
6927 	/* 9704 == 9728 - 20 and rounding to 8 */
6928 	dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6929 	dev->dev.of_node = port_node;
6930 
6931 	port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops;
6932 	port->pcs_gmac.neg_mode = true;
6933 	port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops;
6934 	port->pcs_xlg.neg_mode = true;
6935 
6936 	if (!mvpp2_use_acpi_compat_mode(port_fwnode)) {
6937 		port->phylink_config.dev = &dev->dev;
6938 		port->phylink_config.type = PHYLINK_NETDEV;
6939 		port->phylink_config.mac_capabilities =
6940 			MAC_2500FD | MAC_1000FD | MAC_100 | MAC_10;
6941 
6942 		if (port->priv->global_tx_fc)
6943 			port->phylink_config.mac_capabilities |=
6944 				MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
6945 
6946 		if (mvpp2_port_supports_xlg(port)) {
6947 			/* If a COMPHY is present, we can support any of
6948 			 * the serdes modes and switch between them.
6949 			 */
6950 			if (comphy) {
6951 				__set_bit(PHY_INTERFACE_MODE_5GBASER,
6952 					  port->phylink_config.supported_interfaces);
6953 				__set_bit(PHY_INTERFACE_MODE_10GBASER,
6954 					  port->phylink_config.supported_interfaces);
6955 				__set_bit(PHY_INTERFACE_MODE_XAUI,
6956 					  port->phylink_config.supported_interfaces);
6957 			} else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) {
6958 				__set_bit(PHY_INTERFACE_MODE_5GBASER,
6959 					  port->phylink_config.supported_interfaces);
6960 			} else if (phy_mode == PHY_INTERFACE_MODE_10GBASER) {
6961 				__set_bit(PHY_INTERFACE_MODE_10GBASER,
6962 					  port->phylink_config.supported_interfaces);
6963 			} else if (phy_mode == PHY_INTERFACE_MODE_XAUI) {
6964 				__set_bit(PHY_INTERFACE_MODE_XAUI,
6965 					  port->phylink_config.supported_interfaces);
6966 			}
6967 
6968 			if (comphy)
6969 				port->phylink_config.mac_capabilities |=
6970 					MAC_10000FD | MAC_5000FD;
6971 			else if (phy_mode == PHY_INTERFACE_MODE_5GBASER)
6972 				port->phylink_config.mac_capabilities |=
6973 					MAC_5000FD;
6974 			else
6975 				port->phylink_config.mac_capabilities |=
6976 					MAC_10000FD;
6977 		}
6978 
6979 		if (mvpp2_port_supports_rgmii(port))
6980 			phy_interface_set_rgmii(port->phylink_config.supported_interfaces);
6981 
6982 		if (comphy) {
6983 			/* If a COMPHY is present, we can support any of the
6984 			 * serdes modes and switch between them.
6985 			 */
6986 			__set_bit(PHY_INTERFACE_MODE_SGMII,
6987 				  port->phylink_config.supported_interfaces);
6988 			__set_bit(PHY_INTERFACE_MODE_1000BASEX,
6989 				  port->phylink_config.supported_interfaces);
6990 			__set_bit(PHY_INTERFACE_MODE_2500BASEX,
6991 				  port->phylink_config.supported_interfaces);
6992 		} else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
6993 			/* No COMPHY, with only 2500BASE-X mode supported */
6994 			__set_bit(PHY_INTERFACE_MODE_2500BASEX,
6995 				  port->phylink_config.supported_interfaces);
6996 		} else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
6997 			   phy_mode == PHY_INTERFACE_MODE_SGMII) {
6998 			/* No COMPHY, we can switch between 1000BASE-X and SGMII
6999 			 */
7000 			__set_bit(PHY_INTERFACE_MODE_1000BASEX,
7001 				  port->phylink_config.supported_interfaces);
7002 			__set_bit(PHY_INTERFACE_MODE_SGMII,
7003 				  port->phylink_config.supported_interfaces);
7004 		}
7005 
7006 		phylink = phylink_create(&port->phylink_config, port_fwnode,
7007 					 phy_mode, &mvpp2_phylink_ops);
7008 		if (IS_ERR(phylink)) {
7009 			err = PTR_ERR(phylink);
7010 			goto err_free_port_pcpu;
7011 		}
7012 		port->phylink = phylink;
7013 	} else {
7014 		dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id);
7015 		port->phylink = NULL;
7016 	}
7017 
7018 	/* Cycle the comphy to power it down, saving 270mW per port -
7019 	 * don't worry about an error powering it up. When the comphy
7020 	 * driver does this, we can remove this code.
7021 	 */
7022 	if (port->comphy) {
7023 		err = mvpp22_comphy_init(port, port->phy_interface);
7024 		if (err == 0)
7025 			phy_power_off(port->comphy);
7026 	}
7027 
7028 	err = register_netdev(dev);
7029 	if (err < 0) {
7030 		dev_err(&pdev->dev, "failed to register netdev\n");
7031 		goto err_phylink;
7032 	}
7033 	netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
7034 
7035 	priv->port_list[priv->port_count++] = port;
7036 
7037 	return 0;
7038 
7039 err_phylink:
7040 	if (port->phylink)
7041 		phylink_destroy(port->phylink);
7042 err_free_port_pcpu:
7043 	free_percpu(port->pcpu);
7044 err_free_txq_pcpu:
7045 	for (i = 0; i < port->ntxqs; i++)
7046 		free_percpu(port->txqs[i]->pcpu);
7047 err_free_stats:
7048 	free_percpu(port->stats);
7049 err_free_irq:
7050 	if (port->port_irq)
7051 		irq_dispose_mapping(port->port_irq);
7052 err_deinit_qvecs:
7053 	mvpp2_queue_vectors_deinit(port);
7054 err_free_netdev:
7055 	free_netdev(dev);
7056 	return err;
7057 }
7058 
7059 /* Ports removal routine */
mvpp2_port_remove(struct mvpp2_port * port)7060 static void mvpp2_port_remove(struct mvpp2_port *port)
7061 {
7062 	int i;
7063 
7064 	unregister_netdev(port->dev);
7065 	if (port->phylink)
7066 		phylink_destroy(port->phylink);
7067 	free_percpu(port->pcpu);
7068 	free_percpu(port->stats);
7069 	for (i = 0; i < port->ntxqs; i++)
7070 		free_percpu(port->txqs[i]->pcpu);
7071 	mvpp2_queue_vectors_deinit(port);
7072 	if (port->port_irq)
7073 		irq_dispose_mapping(port->port_irq);
7074 	free_netdev(port->dev);
7075 }
7076 
7077 /* Initialize decoding windows */
mvpp2_conf_mbus_windows(const struct mbus_dram_target_info * dram,struct mvpp2 * priv)7078 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
7079 				    struct mvpp2 *priv)
7080 {
7081 	u32 win_enable;
7082 	int i;
7083 
7084 	for (i = 0; i < 6; i++) {
7085 		mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
7086 		mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
7087 
7088 		if (i < 4)
7089 			mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
7090 	}
7091 
7092 	win_enable = 0;
7093 
7094 	for (i = 0; i < dram->num_cs; i++) {
7095 		const struct mbus_dram_window *cs = dram->cs + i;
7096 
7097 		mvpp2_write(priv, MVPP2_WIN_BASE(i),
7098 			    (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
7099 			    dram->mbus_dram_target_id);
7100 
7101 		mvpp2_write(priv, MVPP2_WIN_SIZE(i),
7102 			    (cs->size - 1) & 0xffff0000);
7103 
7104 		win_enable |= (1 << i);
7105 	}
7106 
7107 	mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
7108 }
7109 
7110 /* Initialize Rx FIFO's */
mvpp2_rx_fifo_init(struct mvpp2 * priv)7111 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
7112 {
7113 	int port;
7114 
7115 	for (port = 0; port < MVPP2_MAX_PORTS; port++) {
7116 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
7117 			    MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7118 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
7119 			    MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
7120 	}
7121 
7122 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7123 		    MVPP2_RX_FIFO_PORT_MIN_PKT);
7124 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7125 }
7126 
mvpp22_rx_fifo_set_hw(struct mvpp2 * priv,int port,int data_size)7127 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
7128 {
7129 	int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
7130 
7131 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
7132 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
7133 }
7134 
7135 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
7136  * 4kB fixed space must be assigned for the loopback port.
7137  * Redistribute remaining avialable 44kB space among all active ports.
7138  * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7139  * SGMII link.
7140  */
mvpp22_rx_fifo_init(struct mvpp2 * priv)7141 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
7142 {
7143 	int remaining_ports_count;
7144 	unsigned long port_map;
7145 	int size_remainder;
7146 	int port, size;
7147 
7148 	/* The loopback requires fixed 4kB of the FIFO space assignment. */
7149 	mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7150 			      MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7151 	port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7152 
7153 	/* Set RX FIFO size to 0 for inactive ports. */
7154 	for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7155 		mvpp22_rx_fifo_set_hw(priv, port, 0);
7156 
7157 	/* Assign remaining RX FIFO space among all active ports. */
7158 	size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
7159 	remaining_ports_count = hweight_long(port_map);
7160 
7161 	for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7162 		if (remaining_ports_count == 1)
7163 			size = size_remainder;
7164 		else if (port == 0)
7165 			size = max(size_remainder / remaining_ports_count,
7166 				   MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
7167 		else if (port == 1)
7168 			size = max(size_remainder / remaining_ports_count,
7169 				   MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
7170 		else
7171 			size = size_remainder / remaining_ports_count;
7172 
7173 		size_remainder -= size;
7174 		remaining_ports_count--;
7175 
7176 		mvpp22_rx_fifo_set_hw(priv, port, size);
7177 	}
7178 
7179 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7180 		    MVPP2_RX_FIFO_PORT_MIN_PKT);
7181 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7182 }
7183 
7184 /* Configure Rx FIFO Flow control thresholds */
mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 * priv)7185 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
7186 {
7187 	int port, val;
7188 
7189 	/* Port 0: maximum speed -10Gb/s port
7190 	 *	   required by spec RX FIFO threshold 9KB
7191 	 * Port 1: maximum speed -5Gb/s port
7192 	 *	   required by spec RX FIFO threshold 4KB
7193 	 * Port 2: maximum speed -1Gb/s port
7194 	 *	   required by spec RX FIFO threshold 2KB
7195 	 */
7196 
7197 	/* Without loopback port */
7198 	for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
7199 		if (port == 0) {
7200 			val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7201 				<< MVPP2_RX_FC_TRSH_OFFS;
7202 			val &= MVPP2_RX_FC_TRSH_MASK;
7203 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7204 		} else if (port == 1) {
7205 			val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7206 				<< MVPP2_RX_FC_TRSH_OFFS;
7207 			val &= MVPP2_RX_FC_TRSH_MASK;
7208 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7209 		} else {
7210 			val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7211 				<< MVPP2_RX_FC_TRSH_OFFS;
7212 			val &= MVPP2_RX_FC_TRSH_MASK;
7213 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7214 		}
7215 	}
7216 }
7217 
7218 /* Configure Rx FIFO Flow control thresholds */
mvpp23_rx_fifo_fc_en(struct mvpp2 * priv,int port,bool en)7219 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
7220 {
7221 	int val;
7222 
7223 	val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
7224 
7225 	if (en)
7226 		val |= MVPP2_RX_FC_EN;
7227 	else
7228 		val &= ~MVPP2_RX_FC_EN;
7229 
7230 	mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7231 }
7232 
mvpp22_tx_fifo_set_hw(struct mvpp2 * priv,int port,int size)7233 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
7234 {
7235 	int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
7236 
7237 	mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
7238 	mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
7239 }
7240 
7241 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
7242  * 1kB fixed space must be assigned for the loopback port.
7243  * Redistribute remaining avialable 18kB space among all active ports.
7244  * The 10G interface should use 10kB (which is maximum possible size
7245  * per single port).
7246  */
mvpp22_tx_fifo_init(struct mvpp2 * priv)7247 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
7248 {
7249 	int remaining_ports_count;
7250 	unsigned long port_map;
7251 	int size_remainder;
7252 	int port, size;
7253 
7254 	/* The loopback requires fixed 1kB of the FIFO space assignment. */
7255 	mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7256 			      MVPP22_TX_FIFO_DATA_SIZE_1KB);
7257 	port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7258 
7259 	/* Set TX FIFO size to 0 for inactive ports. */
7260 	for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7261 		mvpp22_tx_fifo_set_hw(priv, port, 0);
7262 
7263 	/* Assign remaining TX FIFO space among all active ports. */
7264 	size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB;
7265 	remaining_ports_count = hweight_long(port_map);
7266 
7267 	for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7268 		if (remaining_ports_count == 1)
7269 			size = min(size_remainder,
7270 				   MVPP22_TX_FIFO_DATA_SIZE_10KB);
7271 		else if (port == 0)
7272 			size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
7273 		else
7274 			size = size_remainder / remaining_ports_count;
7275 
7276 		size_remainder -= size;
7277 		remaining_ports_count--;
7278 
7279 		mvpp22_tx_fifo_set_hw(priv, port, size);
7280 	}
7281 }
7282 
mvpp2_axi_init(struct mvpp2 * priv)7283 static void mvpp2_axi_init(struct mvpp2 *priv)
7284 {
7285 	u32 val, rdval, wrval;
7286 
7287 	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
7288 
7289 	/* AXI Bridge Configuration */
7290 
7291 	rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
7292 		<< MVPP22_AXI_ATTR_CACHE_OFFS;
7293 	rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7294 		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
7295 
7296 	wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
7297 		<< MVPP22_AXI_ATTR_CACHE_OFFS;
7298 	wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7299 		<< MVPP22_AXI_ATTR_DOMAIN_OFFS;
7300 
7301 	/* BM */
7302 	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
7303 	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
7304 
7305 	/* Descriptors */
7306 	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
7307 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
7308 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
7309 	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
7310 
7311 	/* Buffer Data */
7312 	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
7313 	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
7314 
7315 	val = MVPP22_AXI_CODE_CACHE_NON_CACHE
7316 		<< MVPP22_AXI_CODE_CACHE_OFFS;
7317 	val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
7318 		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
7319 	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
7320 	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
7321 
7322 	val = MVPP22_AXI_CODE_CACHE_RD_CACHE
7323 		<< MVPP22_AXI_CODE_CACHE_OFFS;
7324 	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7325 		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
7326 
7327 	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
7328 
7329 	val = MVPP22_AXI_CODE_CACHE_WR_CACHE
7330 		<< MVPP22_AXI_CODE_CACHE_OFFS;
7331 	val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7332 		<< MVPP22_AXI_CODE_DOMAIN_OFFS;
7333 
7334 	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
7335 }
7336 
7337 /* Initialize network controller common part HW */
mvpp2_init(struct platform_device * pdev,struct mvpp2 * priv)7338 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
7339 {
7340 	const struct mbus_dram_target_info *dram_target_info;
7341 	int err, i;
7342 	u32 val;
7343 
7344 	/* MBUS windows configuration */
7345 	dram_target_info = mv_mbus_dram_info();
7346 	if (dram_target_info)
7347 		mvpp2_conf_mbus_windows(dram_target_info, priv);
7348 
7349 	if (priv->hw_version >= MVPP22)
7350 		mvpp2_axi_init(priv);
7351 
7352 	/* Disable HW PHY polling */
7353 	if (priv->hw_version == MVPP21) {
7354 		val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7355 		val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
7356 		writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7357 	} else {
7358 		val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7359 		val &= ~MVPP22_SMI_POLLING_EN;
7360 		writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7361 	}
7362 
7363 	/* Allocate and initialize aggregated TXQs */
7364 	priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
7365 				       sizeof(*priv->aggr_txqs),
7366 				       GFP_KERNEL);
7367 	if (!priv->aggr_txqs)
7368 		return -ENOMEM;
7369 
7370 	for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7371 		priv->aggr_txqs[i].id = i;
7372 		priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
7373 		err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
7374 		if (err < 0)
7375 			return err;
7376 	}
7377 
7378 	/* Fifo Init */
7379 	if (priv->hw_version == MVPP21) {
7380 		mvpp2_rx_fifo_init(priv);
7381 	} else {
7382 		mvpp22_rx_fifo_init(priv);
7383 		mvpp22_tx_fifo_init(priv);
7384 		if (priv->hw_version == MVPP23)
7385 			mvpp23_rx_fifo_fc_set_tresh(priv);
7386 	}
7387 
7388 	if (priv->hw_version == MVPP21)
7389 		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
7390 		       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
7391 
7392 	/* Allow cache snoop when transmiting packets */
7393 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
7394 
7395 	/* Buffer Manager initialization */
7396 	err = mvpp2_bm_init(&pdev->dev, priv);
7397 	if (err < 0)
7398 		return err;
7399 
7400 	/* Parser default initialization */
7401 	err = mvpp2_prs_default_init(pdev, priv);
7402 	if (err < 0)
7403 		return err;
7404 
7405 	/* Classifier default initialization */
7406 	mvpp2_cls_init(priv);
7407 
7408 	return 0;
7409 }
7410 
mvpp2_get_sram(struct platform_device * pdev,struct mvpp2 * priv)7411 static int mvpp2_get_sram(struct platform_device *pdev,
7412 			  struct mvpp2 *priv)
7413 {
7414 	struct resource *res;
7415 	void __iomem *base;
7416 
7417 	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7418 	if (!res) {
7419 		if (has_acpi_companion(&pdev->dev))
7420 			dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
7421 		else
7422 			dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
7423 		return 0;
7424 	}
7425 
7426 	base = devm_ioremap_resource(&pdev->dev, res);
7427 	if (IS_ERR(base))
7428 		return PTR_ERR(base);
7429 
7430 	priv->cm3_base = base;
7431 	return 0;
7432 }
7433 
mvpp2_probe(struct platform_device * pdev)7434 static int mvpp2_probe(struct platform_device *pdev)
7435 {
7436 	struct fwnode_handle *fwnode = pdev->dev.fwnode;
7437 	struct fwnode_handle *port_fwnode;
7438 	struct mvpp2 *priv;
7439 	struct resource *res;
7440 	void __iomem *base;
7441 	int i, shared;
7442 	int err;
7443 
7444 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
7445 	if (!priv)
7446 		return -ENOMEM;
7447 
7448 	priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
7449 
7450 	/* multi queue mode isn't supported on PPV2.1, fallback to single
7451 	 * mode
7452 	 */
7453 	if (priv->hw_version == MVPP21)
7454 		queue_mode = MVPP2_QDIST_SINGLE_MODE;
7455 
7456 	base = devm_platform_ioremap_resource(pdev, 0);
7457 	if (IS_ERR(base))
7458 		return PTR_ERR(base);
7459 
7460 	if (priv->hw_version == MVPP21) {
7461 		priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
7462 		if (IS_ERR(priv->lms_base))
7463 			return PTR_ERR(priv->lms_base);
7464 	} else {
7465 		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7466 		if (!res) {
7467 			dev_err(&pdev->dev, "Invalid resource\n");
7468 			return -EINVAL;
7469 		}
7470 		if (has_acpi_companion(&pdev->dev)) {
7471 			/* In case the MDIO memory region is declared in
7472 			 * the ACPI, it can already appear as 'in-use'
7473 			 * in the OS. Because it is overlapped by second
7474 			 * region of the network controller, make
7475 			 * sure it is released, before requesting it again.
7476 			 * The care is taken by mvpp2 driver to avoid
7477 			 * concurrent access to this memory region.
7478 			 */
7479 			release_resource(res);
7480 		}
7481 		priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
7482 		if (IS_ERR(priv->iface_base))
7483 			return PTR_ERR(priv->iface_base);
7484 
7485 		/* Map CM3 SRAM */
7486 		err = mvpp2_get_sram(pdev, priv);
7487 		if (err)
7488 			dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
7489 
7490 		/* Enable global Flow Control only if handler to SRAM not NULL */
7491 		if (priv->cm3_base)
7492 			priv->global_tx_fc = true;
7493 	}
7494 
7495 	if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
7496 		priv->sysctrl_base =
7497 			syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
7498 							"marvell,system-controller");
7499 		if (IS_ERR(priv->sysctrl_base))
7500 			/* The system controller regmap is optional for dt
7501 			 * compatibility reasons. When not provided, the
7502 			 * configuration of the GoP relies on the
7503 			 * firmware/bootloader.
7504 			 */
7505 			priv->sysctrl_base = NULL;
7506 	}
7507 
7508 	if (priv->hw_version >= MVPP22 &&
7509 	    mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
7510 		priv->percpu_pools = 1;
7511 
7512 	mvpp2_setup_bm_pool();
7513 
7514 
7515 	priv->nthreads = min_t(unsigned int, num_present_cpus(),
7516 			       MVPP2_MAX_THREADS);
7517 
7518 	shared = num_present_cpus() - priv->nthreads;
7519 	if (shared > 0)
7520 		bitmap_set(&priv->lock_map, 0,
7521 			    min_t(int, shared, MVPP2_MAX_THREADS));
7522 
7523 	for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7524 		u32 addr_space_sz;
7525 
7526 		addr_space_sz = (priv->hw_version == MVPP21 ?
7527 				 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
7528 		priv->swth_base[i] = base + i * addr_space_sz;
7529 	}
7530 
7531 	if (priv->hw_version == MVPP21)
7532 		priv->max_port_rxqs = 8;
7533 	else
7534 		priv->max_port_rxqs = 32;
7535 
7536 	if (dev_of_node(&pdev->dev)) {
7537 		priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
7538 		if (IS_ERR(priv->pp_clk))
7539 			return PTR_ERR(priv->pp_clk);
7540 		err = clk_prepare_enable(priv->pp_clk);
7541 		if (err < 0)
7542 			return err;
7543 
7544 		priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
7545 		if (IS_ERR(priv->gop_clk)) {
7546 			err = PTR_ERR(priv->gop_clk);
7547 			goto err_pp_clk;
7548 		}
7549 		err = clk_prepare_enable(priv->gop_clk);
7550 		if (err < 0)
7551 			goto err_pp_clk;
7552 
7553 		if (priv->hw_version >= MVPP22) {
7554 			priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
7555 			if (IS_ERR(priv->mg_clk)) {
7556 				err = PTR_ERR(priv->mg_clk);
7557 				goto err_gop_clk;
7558 			}
7559 
7560 			err = clk_prepare_enable(priv->mg_clk);
7561 			if (err < 0)
7562 				goto err_gop_clk;
7563 
7564 			priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk");
7565 			if (IS_ERR(priv->mg_core_clk)) {
7566 				err = PTR_ERR(priv->mg_core_clk);
7567 				goto err_mg_clk;
7568 			}
7569 
7570 			err = clk_prepare_enable(priv->mg_core_clk);
7571 			if (err < 0)
7572 				goto err_mg_clk;
7573 		}
7574 
7575 		priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk");
7576 		if (IS_ERR(priv->axi_clk)) {
7577 			err = PTR_ERR(priv->axi_clk);
7578 			goto err_mg_core_clk;
7579 		}
7580 
7581 		err = clk_prepare_enable(priv->axi_clk);
7582 		if (err < 0)
7583 			goto err_mg_core_clk;
7584 
7585 		/* Get system's tclk rate */
7586 		priv->tclk = clk_get_rate(priv->pp_clk);
7587 	} else {
7588 		err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk);
7589 		if (err) {
7590 			dev_err(&pdev->dev, "missing clock-frequency value\n");
7591 			return err;
7592 		}
7593 	}
7594 
7595 	if (priv->hw_version >= MVPP22) {
7596 		err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7597 		if (err)
7598 			goto err_axi_clk;
7599 		/* Sadly, the BM pools all share the same register to
7600 		 * store the high 32 bits of their address. So they
7601 		 * must all have the same high 32 bits, which forces
7602 		 * us to restrict coherent memory to DMA_BIT_MASK(32).
7603 		 */
7604 		err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7605 		if (err)
7606 			goto err_axi_clk;
7607 	}
7608 
7609 	/* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7610 	fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7611 		if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7612 			priv->port_map |= BIT(i);
7613 	}
7614 
7615 	if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
7616 		priv->hw_version = MVPP23;
7617 
7618 	/* Init mss lock */
7619 	spin_lock_init(&priv->mss_spinlock);
7620 
7621 	/* Initialize network controller */
7622 	err = mvpp2_init(pdev, priv);
7623 	if (err < 0) {
7624 		dev_err(&pdev->dev, "failed to initialize controller\n");
7625 		goto err_axi_clk;
7626 	}
7627 
7628 	err = mvpp22_tai_probe(&pdev->dev, priv);
7629 	if (err < 0)
7630 		goto err_axi_clk;
7631 
7632 	/* Initialize ports */
7633 	fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7634 		err = mvpp2_port_probe(pdev, port_fwnode, priv);
7635 		if (err < 0)
7636 			goto err_port_probe;
7637 	}
7638 
7639 	if (priv->port_count == 0) {
7640 		dev_err(&pdev->dev, "no ports enabled\n");
7641 		err = -ENODEV;
7642 		goto err_axi_clk;
7643 	}
7644 
7645 	/* Statistics must be gathered regularly because some of them (like
7646 	 * packets counters) are 32-bit registers and could overflow quite
7647 	 * quickly. For instance, a 10Gb link used at full bandwidth with the
7648 	 * smallest packets (64B) will overflow a 32-bit counter in less than
7649 	 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7650 	 */
7651 	snprintf(priv->queue_name, sizeof(priv->queue_name),
7652 		 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7653 		 priv->port_count > 1 ? "+" : "");
7654 	priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7655 	if (!priv->stats_queue) {
7656 		err = -ENOMEM;
7657 		goto err_port_probe;
7658 	}
7659 
7660 	if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
7661 		err = mvpp2_enable_global_fc(priv);
7662 		if (err)
7663 			dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
7664 	}
7665 
7666 	mvpp2_dbgfs_init(priv, pdev->name);
7667 
7668 	platform_set_drvdata(pdev, priv);
7669 	return 0;
7670 
7671 err_port_probe:
7672 	fwnode_handle_put(port_fwnode);
7673 
7674 	i = 0;
7675 	fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7676 		if (priv->port_list[i])
7677 			mvpp2_port_remove(priv->port_list[i]);
7678 		i++;
7679 	}
7680 err_axi_clk:
7681 	clk_disable_unprepare(priv->axi_clk);
7682 err_mg_core_clk:
7683 	clk_disable_unprepare(priv->mg_core_clk);
7684 err_mg_clk:
7685 	clk_disable_unprepare(priv->mg_clk);
7686 err_gop_clk:
7687 	clk_disable_unprepare(priv->gop_clk);
7688 err_pp_clk:
7689 	clk_disable_unprepare(priv->pp_clk);
7690 	return err;
7691 }
7692 
mvpp2_remove(struct platform_device * pdev)7693 static int mvpp2_remove(struct platform_device *pdev)
7694 {
7695 	struct mvpp2 *priv = platform_get_drvdata(pdev);
7696 	struct fwnode_handle *fwnode = pdev->dev.fwnode;
7697 	int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7698 	struct fwnode_handle *port_fwnode;
7699 
7700 	mvpp2_dbgfs_cleanup(priv);
7701 
7702 	fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7703 		if (priv->port_list[i]) {
7704 			mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7705 			mvpp2_port_remove(priv->port_list[i]);
7706 		}
7707 		i++;
7708 	}
7709 
7710 	destroy_workqueue(priv->stats_queue);
7711 
7712 	if (priv->percpu_pools)
7713 		poolnum = mvpp2_get_nrxqs(priv) * 2;
7714 
7715 	for (i = 0; i < poolnum; i++) {
7716 		struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7717 
7718 		mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7719 	}
7720 
7721 	for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7722 		struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7723 
7724 		dma_free_coherent(&pdev->dev,
7725 				  MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7726 				  aggr_txq->descs,
7727 				  aggr_txq->descs_dma);
7728 	}
7729 
7730 	if (is_acpi_node(port_fwnode))
7731 		return 0;
7732 
7733 	clk_disable_unprepare(priv->axi_clk);
7734 	clk_disable_unprepare(priv->mg_core_clk);
7735 	clk_disable_unprepare(priv->mg_clk);
7736 	clk_disable_unprepare(priv->pp_clk);
7737 	clk_disable_unprepare(priv->gop_clk);
7738 
7739 	return 0;
7740 }
7741 
7742 static const struct of_device_id mvpp2_match[] = {
7743 	{
7744 		.compatible = "marvell,armada-375-pp2",
7745 		.data = (void *)MVPP21,
7746 	},
7747 	{
7748 		.compatible = "marvell,armada-7k-pp22",
7749 		.data = (void *)MVPP22,
7750 	},
7751 	{ }
7752 };
7753 MODULE_DEVICE_TABLE(of, mvpp2_match);
7754 
7755 #ifdef CONFIG_ACPI
7756 static const struct acpi_device_id mvpp2_acpi_match[] = {
7757 	{ "MRVL0110", MVPP22 },
7758 	{ },
7759 };
7760 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7761 #endif
7762 
7763 static struct platform_driver mvpp2_driver = {
7764 	.probe = mvpp2_probe,
7765 	.remove = mvpp2_remove,
7766 	.driver = {
7767 		.name = MVPP2_DRIVER_NAME,
7768 		.of_match_table = mvpp2_match,
7769 		.acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7770 	},
7771 };
7772 
mvpp2_driver_init(void)7773 static int __init mvpp2_driver_init(void)
7774 {
7775 	return platform_driver_register(&mvpp2_driver);
7776 }
7777 module_init(mvpp2_driver_init);
7778 
mvpp2_driver_exit(void)7779 static void __exit mvpp2_driver_exit(void)
7780 {
7781 	platform_driver_unregister(&mvpp2_driver);
7782 	mvpp2_dbgfs_exit();
7783 }
7784 module_exit(mvpp2_driver_exit);
7785 
7786 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7787 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7788 MODULE_LICENSE("GPL v2");
7789