1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/ethtool_netlink.h>
34
35 #include "en.h"
36 #include "en/port.h"
37 #include "en/params.h"
38 #include "en/ptp.h"
39 #include "lib/clock.h"
40 #include "en/fs_ethtool.h"
41
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)42 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
43 struct ethtool_drvinfo *drvinfo)
44 {
45 struct mlx5_core_dev *mdev = priv->mdev;
46 int count;
47
48 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
49 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
50 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),
51 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id);
52 if (count >= sizeof(drvinfo->fw_version))
53 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
54 "%d.%d.%04d", fw_rev_maj(mdev),
55 fw_rev_min(mdev), fw_rev_sub(mdev));
56
57 strscpy(drvinfo->bus_info, dev_name(mdev->device),
58 sizeof(drvinfo->bus_info));
59 }
60
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)61 static void mlx5e_get_drvinfo(struct net_device *dev,
62 struct ethtool_drvinfo *drvinfo)
63 {
64 struct mlx5e_priv *priv = netdev_priv(dev);
65
66 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
67 }
68
69 struct ptys2ethtool_config {
70 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
71 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
72 };
73
74 static
75 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
76 static
77 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
78
79 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
80 ({ \
81 struct ptys2ethtool_config *cfg; \
82 const unsigned int modes[] = { __VA_ARGS__ }; \
83 unsigned int i, bit, idx; \
84 cfg = &ptys2##table##_ethtool_table[reg_]; \
85 bitmap_zero(cfg->supported, \
86 __ETHTOOL_LINK_MODE_MASK_NBITS); \
87 bitmap_zero(cfg->advertised, \
88 __ETHTOOL_LINK_MODE_MASK_NBITS); \
89 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
90 bit = modes[i] % 64; \
91 idx = modes[i] / 64; \
92 __set_bit(bit, &cfg->supported[idx]); \
93 __set_bit(bit, &cfg->advertised[idx]); \
94 } \
95 })
96
mlx5e_build_ptys2ethtool_map(void)97 void mlx5e_build_ptys2ethtool_map(void)
98 {
99 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
100 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
102 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
104 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
106 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
108 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
110 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
112 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
114 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
116 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
118 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
120 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
122 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
124 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
126 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
128 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
130 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
132 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
134 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
136 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
138 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
140 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
142 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
144 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
146 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
148 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
150 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
152 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
154 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
156 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
158 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
159 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
160 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
161 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
162 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
164 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
165 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
166 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
167 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
168 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
169 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
170 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
171 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
172 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
173 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
174 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
175 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
176 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
177 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
179 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
181 ext,
182 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
183 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
184 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
186 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
187 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
188 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
189 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
190 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
195 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
196 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
197 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
198 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
199 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
200 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
201 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
202 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
203 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
204 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
205 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
206 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
207 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
208 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
209 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
210 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
211 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
212 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
213 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
214 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
215 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
216 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
217 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
218 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
219 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
220 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
221 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
222 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
223 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
224 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
225 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
226 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
227 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
228 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
229 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
230 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
231 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
232 }
233
mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev * mdev,struct ptys2ethtool_config ** arr,u32 * size)234 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
235 struct ptys2ethtool_config **arr,
236 u32 *size)
237 {
238 bool ext = mlx5_ptys_ext_supported(mdev);
239
240 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
241 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
242 ARRAY_SIZE(ptys2legacy_ethtool_table);
243 }
244
245 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
246
247 struct pflag_desc {
248 char name[ETH_GSTRING_LEN];
249 mlx5e_pflag_handler handler;
250 };
251
252 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
253
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)254 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
255 {
256 switch (sset) {
257 case ETH_SS_STATS:
258 return mlx5e_stats_total_num(priv);
259 case ETH_SS_PRIV_FLAGS:
260 return MLX5E_NUM_PFLAGS;
261 case ETH_SS_TEST:
262 return mlx5e_self_test_num(priv);
263 default:
264 return -EOPNOTSUPP;
265 }
266 }
267
mlx5e_get_sset_count(struct net_device * dev,int sset)268 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
269 {
270 struct mlx5e_priv *priv = netdev_priv(dev);
271
272 return mlx5e_ethtool_get_sset_count(priv, sset);
273 }
274
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)275 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
276 {
277 int i;
278
279 switch (stringset) {
280 case ETH_SS_PRIV_FLAGS:
281 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
282 strcpy(data + i * ETH_GSTRING_LEN,
283 mlx5e_priv_flags[i].name);
284 break;
285
286 case ETH_SS_TEST:
287 mlx5e_self_test_fill_strings(priv, data);
288 break;
289
290 case ETH_SS_STATS:
291 mlx5e_stats_fill_strings(priv, data);
292 break;
293 }
294 }
295
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)296 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
297 {
298 struct mlx5e_priv *priv = netdev_priv(dev);
299
300 mlx5e_ethtool_get_strings(priv, stringset, data);
301 }
302
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)303 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
304 struct ethtool_stats *stats, u64 *data)
305 {
306 int idx = 0;
307
308 mutex_lock(&priv->state_lock);
309 mlx5e_stats_update(priv);
310 mutex_unlock(&priv->state_lock);
311
312 mlx5e_stats_fill(priv, data, idx);
313 }
314
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)315 static void mlx5e_get_ethtool_stats(struct net_device *dev,
316 struct ethtool_stats *stats,
317 u64 *data)
318 {
319 struct mlx5e_priv *priv = netdev_priv(dev);
320
321 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
322 }
323
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param)324 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
325 struct ethtool_ringparam *param,
326 struct kernel_ethtool_ringparam *kernel_param)
327 {
328 /* Limitation for regular RQ. XSK RQ may clamp the queue length in
329 * mlx5e_mpwqe_get_log_rq_size.
330 */
331 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev,
332 PAGE_SHIFT,
333 MLX5E_MPWRQ_UMR_MODE_ALIGNED);
334
335 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE,
336 max_log_mpwrq_pkts);
337 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
338 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
339 param->tx_pending = 1 << priv->channels.params.log_sq_size;
340
341 kernel_param->tcp_data_split =
342 (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) ?
343 ETHTOOL_TCP_DATA_SPLIT_ENABLED :
344 ETHTOOL_TCP_DATA_SPLIT_DISABLED;
345 }
346
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)347 static void mlx5e_get_ringparam(struct net_device *dev,
348 struct ethtool_ringparam *param,
349 struct kernel_ethtool_ringparam *kernel_param,
350 struct netlink_ext_ack *extack)
351 {
352 struct mlx5e_priv *priv = netdev_priv(dev);
353
354 mlx5e_ethtool_get_ringparam(priv, param, kernel_param);
355 }
356
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)357 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
358 struct ethtool_ringparam *param)
359 {
360 struct mlx5e_params new_params;
361 u8 log_rq_size;
362 u8 log_sq_size;
363 int err = 0;
364
365 if (param->rx_jumbo_pending) {
366 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
367 __func__);
368 return -EINVAL;
369 }
370 if (param->rx_mini_pending) {
371 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
372 __func__);
373 return -EINVAL;
374 }
375
376 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
377 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
378 __func__, param->rx_pending,
379 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
380 return -EINVAL;
381 }
382
383 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
384 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
385 __func__, param->tx_pending,
386 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
387 return -EINVAL;
388 }
389
390 log_rq_size = order_base_2(param->rx_pending);
391 log_sq_size = order_base_2(param->tx_pending);
392
393 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
394 log_sq_size == priv->channels.params.log_sq_size)
395 return 0;
396
397 mutex_lock(&priv->state_lock);
398
399 new_params = priv->channels.params;
400 new_params.log_rq_mtu_frames = log_rq_size;
401 new_params.log_sq_size = log_sq_size;
402
403 err = mlx5e_validate_params(priv->mdev, &new_params);
404 if (err)
405 goto unlock;
406
407 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
408
409 unlock:
410 mutex_unlock(&priv->state_lock);
411
412 return err;
413 }
414
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param,struct kernel_ethtool_ringparam * kernel_param,struct netlink_ext_ack * extack)415 static int mlx5e_set_ringparam(struct net_device *dev,
416 struct ethtool_ringparam *param,
417 struct kernel_ethtool_ringparam *kernel_param,
418 struct netlink_ext_ack *extack)
419 {
420 struct mlx5e_priv *priv = netdev_priv(dev);
421
422 return mlx5e_ethtool_set_ringparam(priv, param);
423 }
424
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)425 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
426 struct ethtool_channels *ch)
427 {
428 mutex_lock(&priv->state_lock);
429 ch->max_combined = priv->max_nch;
430 ch->combined_count = priv->channels.params.num_channels;
431 mutex_unlock(&priv->state_lock);
432 }
433
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)434 static void mlx5e_get_channels(struct net_device *dev,
435 struct ethtool_channels *ch)
436 {
437 struct mlx5e_priv *priv = netdev_priv(dev);
438
439 mlx5e_ethtool_get_channels(priv, ch);
440 }
441
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)442 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
443 struct ethtool_channels *ch)
444 {
445 struct mlx5e_params *cur_params = &priv->channels.params;
446 unsigned int count = ch->combined_count;
447 struct mlx5e_params new_params;
448 bool arfs_enabled;
449 int rss_cnt;
450 bool opened;
451 int err = 0;
452
453 if (!count) {
454 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
455 __func__);
456 return -EINVAL;
457 }
458
459 if (cur_params->num_channels == count)
460 return 0;
461
462 mutex_lock(&priv->state_lock);
463
464 /* Don't allow changing the number of channels if HTB offload is active,
465 * because the numeration of the QoS SQs will change, while per-queue
466 * qdiscs are attached.
467 */
468 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
469 err = -EINVAL;
470 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n",
471 __func__);
472 goto out;
473 }
474
475 /* Don't allow changing the number of channels if non-default RSS contexts exist,
476 * the kernel doesn't protect against set_channels operations that break them.
477 */
478 rss_cnt = mlx5e_rx_res_rss_cnt(priv->rx_res) - 1;
479 if (rss_cnt) {
480 err = -EINVAL;
481 netdev_err(priv->netdev, "%s: Non-default RSS contexts exist (%d), cannot change the number of channels\n",
482 __func__, rss_cnt);
483 goto out;
484 }
485
486 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active,
487 * because it defines a partition over the channels queues.
488 */
489 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
490 err = -EINVAL;
491 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n",
492 __func__);
493 goto out;
494 }
495
496 new_params = *cur_params;
497 new_params.num_channels = count;
498
499 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
500
501 arfs_enabled = opened && (priv->netdev->features & NETIF_F_NTUPLE);
502 if (arfs_enabled)
503 mlx5e_arfs_disable(priv->fs);
504
505 /* Switch to new channels, set new parameters and close old ones */
506 err = mlx5e_safe_switch_params(priv, &new_params,
507 mlx5e_num_channels_changed_ctx, NULL, true);
508
509 if (arfs_enabled) {
510 int err2 = mlx5e_arfs_enable(priv->fs);
511
512 if (err2)
513 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
514 __func__, err2);
515 }
516
517 out:
518 mutex_unlock(&priv->state_lock);
519
520 return err;
521 }
522
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)523 static int mlx5e_set_channels(struct net_device *dev,
524 struct ethtool_channels *ch)
525 {
526 struct mlx5e_priv *priv = netdev_priv(dev);
527
528 return mlx5e_ethtool_set_channels(priv, ch);
529 }
530
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal)531 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
532 struct ethtool_coalesce *coal,
533 struct kernel_ethtool_coalesce *kernel_coal)
534 {
535 struct dim_cq_moder *rx_moder, *tx_moder;
536
537 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
538 return -EOPNOTSUPP;
539
540 rx_moder = &priv->channels.params.rx_cq_moderation;
541 coal->rx_coalesce_usecs = rx_moder->usec;
542 coal->rx_max_coalesced_frames = rx_moder->pkts;
543 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
544
545 tx_moder = &priv->channels.params.tx_cq_moderation;
546 coal->tx_coalesce_usecs = tx_moder->usec;
547 coal->tx_max_coalesced_frames = tx_moder->pkts;
548 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
549
550 kernel_coal->use_cqe_mode_rx =
551 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_BASED_MODER);
552 kernel_coal->use_cqe_mode_tx =
553 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_CQE_BASED_MODER);
554
555 return 0;
556 }
557
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)558 static int mlx5e_get_coalesce(struct net_device *netdev,
559 struct ethtool_coalesce *coal,
560 struct kernel_ethtool_coalesce *kernel_coal,
561 struct netlink_ext_ack *extack)
562 {
563 struct mlx5e_priv *priv = netdev_priv(netdev);
564
565 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal);
566 }
567
568 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
569 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
570
571 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)572 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
573 {
574 struct mlx5_core_dev *mdev = priv->mdev;
575 int tc;
576 int i;
577
578 for (i = 0; i < priv->channels.num; ++i) {
579 struct mlx5e_channel *c = priv->channels.c[i];
580
581 for (tc = 0; tc < c->num_tc; tc++) {
582 mlx5_core_modify_cq_moderation(mdev,
583 &c->sq[tc].cq.mcq,
584 coal->tx_coalesce_usecs,
585 coal->tx_max_coalesced_frames);
586 }
587 }
588 }
589
590 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)591 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
592 {
593 struct mlx5_core_dev *mdev = priv->mdev;
594 int i;
595
596 for (i = 0; i < priv->channels.num; ++i) {
597 struct mlx5e_channel *c = priv->channels.c[i];
598
599 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
600 coal->rx_coalesce_usecs,
601 coal->rx_max_coalesced_frames);
602 }
603 }
604
605 /* convert a boolean value of cq_mode to mlx5 period mode
606 * true : MLX5_CQ_PERIOD_MODE_START_FROM_CQE
607 * false : MLX5_CQ_PERIOD_MODE_START_FROM_EQE
608 */
cqe_mode_to_period_mode(bool val)609 static int cqe_mode_to_period_mode(bool val)
610 {
611 return val ? MLX5_CQ_PERIOD_MODE_START_FROM_CQE : MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
612 }
613
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)614 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
615 struct ethtool_coalesce *coal,
616 struct kernel_ethtool_coalesce *kernel_coal,
617 struct netlink_ext_ack *extack)
618 {
619 struct dim_cq_moder *rx_moder, *tx_moder;
620 struct mlx5_core_dev *mdev = priv->mdev;
621 struct mlx5e_params new_params;
622 bool reset_rx, reset_tx;
623 bool reset = true;
624 u8 cq_period_mode;
625 int err = 0;
626
627 if (!MLX5_CAP_GEN(mdev, cq_moderation))
628 return -EOPNOTSUPP;
629
630 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
631 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
632 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
633 __func__, MLX5E_MAX_COAL_TIME);
634 return -ERANGE;
635 }
636
637 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
638 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
639 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
640 __func__, MLX5E_MAX_COAL_FRAMES);
641 return -ERANGE;
642 }
643
644 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
645 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) {
646 NL_SET_ERR_MSG_MOD(extack, "cqe_mode_rx/tx is not supported on this device");
647 return -EOPNOTSUPP;
648 }
649
650 mutex_lock(&priv->state_lock);
651 new_params = priv->channels.params;
652
653 rx_moder = &new_params.rx_cq_moderation;
654 rx_moder->usec = coal->rx_coalesce_usecs;
655 rx_moder->pkts = coal->rx_max_coalesced_frames;
656 new_params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
657
658 tx_moder = &new_params.tx_cq_moderation;
659 tx_moder->usec = coal->tx_coalesce_usecs;
660 tx_moder->pkts = coal->tx_max_coalesced_frames;
661 new_params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
662
663 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
664 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
665
666 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_rx);
667 if (cq_period_mode != rx_moder->cq_period_mode) {
668 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode);
669 reset_rx = true;
670 }
671
672 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_tx);
673 if (cq_period_mode != tx_moder->cq_period_mode) {
674 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode);
675 reset_tx = true;
676 }
677
678 if (reset_rx) {
679 u8 mode = MLX5E_GET_PFLAG(&new_params,
680 MLX5E_PFLAG_RX_CQE_BASED_MODER);
681
682 mlx5e_reset_rx_moderation(&new_params, mode);
683 }
684 if (reset_tx) {
685 u8 mode = MLX5E_GET_PFLAG(&new_params,
686 MLX5E_PFLAG_TX_CQE_BASED_MODER);
687
688 mlx5e_reset_tx_moderation(&new_params, mode);
689 }
690
691 /* If DIM state hasn't changed, it's possible to modify interrupt
692 * moderation parameters on the fly, even if the channels are open.
693 */
694 if (!reset_rx && !reset_tx && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
695 if (!coal->use_adaptive_rx_coalesce)
696 mlx5e_set_priv_channels_rx_coalesce(priv, coal);
697 if (!coal->use_adaptive_tx_coalesce)
698 mlx5e_set_priv_channels_tx_coalesce(priv, coal);
699 reset = false;
700 }
701
702 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
703
704 mutex_unlock(&priv->state_lock);
705 return err;
706 }
707
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)708 static int mlx5e_set_coalesce(struct net_device *netdev,
709 struct ethtool_coalesce *coal,
710 struct kernel_ethtool_coalesce *kernel_coal,
711 struct netlink_ext_ack *extack)
712 {
713 struct mlx5e_priv *priv = netdev_priv(netdev);
714
715 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack);
716 }
717
ptys2ethtool_supported_link(struct mlx5_core_dev * mdev,unsigned long * supported_modes,u32 eth_proto_cap)718 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
719 unsigned long *supported_modes,
720 u32 eth_proto_cap)
721 {
722 unsigned long proto_cap = eth_proto_cap;
723 struct ptys2ethtool_config *table;
724 u32 max_size;
725 int proto;
726
727 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
728 for_each_set_bit(proto, &proto_cap, max_size)
729 bitmap_or(supported_modes, supported_modes,
730 table[proto].supported,
731 __ETHTOOL_LINK_MODE_MASK_NBITS);
732 }
733
ptys2ethtool_adver_link(unsigned long * advertising_modes,u32 eth_proto_cap,bool ext)734 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
735 u32 eth_proto_cap, bool ext)
736 {
737 unsigned long proto_cap = eth_proto_cap;
738 struct ptys2ethtool_config *table;
739 u32 max_size;
740 int proto;
741
742 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
743 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
744 ARRAY_SIZE(ptys2legacy_ethtool_table);
745
746 for_each_set_bit(proto, &proto_cap, max_size)
747 bitmap_or(advertising_modes, advertising_modes,
748 table[proto].advertised,
749 __ETHTOOL_LINK_MODE_MASK_NBITS);
750 }
751
752 static const u32 pplm_fec_2_ethtool[] = {
753 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
754 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
755 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
756 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
757 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
758 };
759
pplm2ethtool_fec(u_long fec_mode,unsigned long size)760 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
761 {
762 int mode = 0;
763
764 if (!fec_mode)
765 return ETHTOOL_FEC_AUTO;
766
767 mode = find_first_bit(&fec_mode, size);
768
769 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
770 return pplm_fec_2_ethtool[mode];
771
772 return 0;
773 }
774
775 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
776 do { \
777 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
778 __set_bit(ethtool_fec, \
779 link_ksettings->link_modes.supported);\
780 } while (0)
781
782 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
783 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
784 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
785 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
786 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
787 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
788 };
789
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)790 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
791 struct ethtool_link_ksettings *link_ksettings)
792 {
793 unsigned long active_fec_long;
794 u32 active_fec;
795 u32 bitn;
796 int err;
797
798 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
799 if (err)
800 return (err == -EOPNOTSUPP) ? 0 : err;
801
802 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
803 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
804 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
805 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
806 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
807 ETHTOOL_LINK_MODE_FEC_RS_BIT);
808 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
809 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
810
811 active_fec_long = active_fec;
812 /* active fec is a bit set, find out which bit is set and
813 * advertise the corresponding ethtool bit
814 */
815 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
816 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
817 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
818 link_ksettings->link_modes.advertising);
819
820 return 0;
821 }
822
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)823 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
824 struct ethtool_link_ksettings *link_ksettings,
825 u32 eth_proto_cap, u8 connector_type)
826 {
827 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
828 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
829 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
830 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
831 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
832 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
833 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
834 ethtool_link_ksettings_add_link_mode(link_ksettings,
835 supported,
836 FIBRE);
837 ethtool_link_ksettings_add_link_mode(link_ksettings,
838 advertising,
839 FIBRE);
840 }
841
842 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
843 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
844 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
845 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
846 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
847 ethtool_link_ksettings_add_link_mode(link_ksettings,
848 supported,
849 Backplane);
850 ethtool_link_ksettings_add_link_mode(link_ksettings,
851 advertising,
852 Backplane);
853 }
854 return;
855 }
856
857 switch (connector_type) {
858 case MLX5E_PORT_TP:
859 ethtool_link_ksettings_add_link_mode(link_ksettings,
860 supported, TP);
861 ethtool_link_ksettings_add_link_mode(link_ksettings,
862 advertising, TP);
863 break;
864 case MLX5E_PORT_AUI:
865 ethtool_link_ksettings_add_link_mode(link_ksettings,
866 supported, AUI);
867 ethtool_link_ksettings_add_link_mode(link_ksettings,
868 advertising, AUI);
869 break;
870 case MLX5E_PORT_BNC:
871 ethtool_link_ksettings_add_link_mode(link_ksettings,
872 supported, BNC);
873 ethtool_link_ksettings_add_link_mode(link_ksettings,
874 advertising, BNC);
875 break;
876 case MLX5E_PORT_MII:
877 ethtool_link_ksettings_add_link_mode(link_ksettings,
878 supported, MII);
879 ethtool_link_ksettings_add_link_mode(link_ksettings,
880 advertising, MII);
881 break;
882 case MLX5E_PORT_FIBRE:
883 ethtool_link_ksettings_add_link_mode(link_ksettings,
884 supported, FIBRE);
885 ethtool_link_ksettings_add_link_mode(link_ksettings,
886 advertising, FIBRE);
887 break;
888 case MLX5E_PORT_DA:
889 ethtool_link_ksettings_add_link_mode(link_ksettings,
890 supported, Backplane);
891 ethtool_link_ksettings_add_link_mode(link_ksettings,
892 advertising, Backplane);
893 break;
894 case MLX5E_PORT_NONE:
895 case MLX5E_PORT_OTHER:
896 default:
897 break;
898 }
899 }
900
get_speed_duplex(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)901 static void get_speed_duplex(struct net_device *netdev,
902 u32 eth_proto_oper, bool force_legacy,
903 u16 data_rate_oper,
904 struct ethtool_link_ksettings *link_ksettings)
905 {
906 struct mlx5e_priv *priv = netdev_priv(netdev);
907 u32 speed = SPEED_UNKNOWN;
908 u8 duplex = DUPLEX_UNKNOWN;
909
910 if (!netif_carrier_ok(netdev))
911 goto out;
912
913 speed = mlx5_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
914 if (!speed) {
915 if (data_rate_oper)
916 speed = 100 * data_rate_oper;
917 else
918 speed = SPEED_UNKNOWN;
919 goto out;
920 }
921
922 duplex = DUPLEX_FULL;
923
924 out:
925 link_ksettings->base.speed = speed;
926 link_ksettings->base.duplex = duplex;
927 }
928
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)929 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
930 struct ethtool_link_ksettings *link_ksettings)
931 {
932 unsigned long *supported = link_ksettings->link_modes.supported;
933 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
934
935 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
936 }
937
get_advertising(u32 eth_proto_cap,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)938 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
939 struct ethtool_link_ksettings *link_ksettings,
940 bool ext)
941 {
942 unsigned long *advertising = link_ksettings->link_modes.advertising;
943 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
944
945 if (rx_pause)
946 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
947 if (tx_pause ^ rx_pause)
948 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
949 }
950
951 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
952 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
953 [MLX5E_PORT_NONE] = PORT_NONE,
954 [MLX5E_PORT_TP] = PORT_TP,
955 [MLX5E_PORT_AUI] = PORT_AUI,
956 [MLX5E_PORT_BNC] = PORT_BNC,
957 [MLX5E_PORT_MII] = PORT_MII,
958 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
959 [MLX5E_PORT_DA] = PORT_DA,
960 [MLX5E_PORT_OTHER] = PORT_OTHER,
961 };
962
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)963 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
964 {
965 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
966 return ptys2connector_type[connector_type];
967
968 if (eth_proto &
969 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
970 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
971 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
972 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
973 return PORT_FIBRE;
974 }
975
976 if (eth_proto &
977 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
978 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
979 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
980 return PORT_DA;
981 }
982
983 if (eth_proto &
984 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
985 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
986 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
987 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
988 return PORT_NONE;
989 }
990
991 return PORT_OTHER;
992 }
993
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)994 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
995 struct ethtool_link_ksettings *link_ksettings)
996 {
997 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
998 bool ext = mlx5_ptys_ext_supported(mdev);
999
1000 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
1001 }
1002
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)1003 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1004 struct ethtool_link_ksettings *link_ksettings)
1005 {
1006 struct mlx5_core_dev *mdev = priv->mdev;
1007 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
1008 u32 eth_proto_admin;
1009 u8 an_disable_admin;
1010 u16 data_rate_oper;
1011 u32 eth_proto_oper;
1012 u32 eth_proto_cap;
1013 u8 connector_type;
1014 u32 rx_pause = 0;
1015 u32 tx_pause = 0;
1016 u32 eth_proto_lp;
1017 bool admin_ext;
1018 u8 an_status;
1019 bool ext;
1020 int err;
1021
1022 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
1023 if (err) {
1024 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
1025 __func__, err);
1026 goto err_query_regs;
1027 }
1028 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
1029 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1030 eth_proto_capability);
1031 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1032 eth_proto_admin);
1033 /* Fields: eth_proto_admin and ext_eth_proto_admin are
1034 * mutually exclusive. Hence try reading legacy advertising
1035 * when extended advertising is zero.
1036 * admin_ext indicates which proto_admin (ext vs. legacy)
1037 * should be read and interpreted
1038 */
1039 admin_ext = ext;
1040 if (ext && !eth_proto_admin) {
1041 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
1042 eth_proto_admin);
1043 admin_ext = false;
1044 }
1045
1046 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
1047 eth_proto_oper);
1048 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1049 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1050 an_status = MLX5_GET(ptys_reg, out, an_status);
1051 connector_type = MLX5_GET(ptys_reg, out, connector_type);
1052 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
1053
1054 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1055
1056 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1057 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1058
1059 get_supported(mdev, eth_proto_cap, link_ksettings);
1060 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
1061 admin_ext);
1062 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
1063 data_rate_oper, link_ksettings);
1064
1065 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1066 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
1067 connector_type : MLX5E_PORT_UNKNOWN;
1068 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
1069 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
1070 connector_type);
1071 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
1072
1073 if (an_status == MLX5_AN_COMPLETE)
1074 ethtool_link_ksettings_add_link_mode(link_ksettings,
1075 lp_advertising, Autoneg);
1076
1077 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1078 AUTONEG_ENABLE;
1079 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1080 Autoneg);
1081
1082 err = get_fec_supported_advertised(mdev, link_ksettings);
1083 if (err) {
1084 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1085 __func__, err);
1086 err = 0; /* don't fail caps query because of FEC error */
1087 }
1088
1089 if (!an_disable_admin)
1090 ethtool_link_ksettings_add_link_mode(link_ksettings,
1091 advertising, Autoneg);
1092
1093 err_query_regs:
1094 return err;
1095 }
1096
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1097 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1098 struct ethtool_link_ksettings *link_ksettings)
1099 {
1100 struct mlx5e_priv *priv = netdev_priv(netdev);
1101
1102 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1103 }
1104
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1105 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1106 const unsigned long link_modes, u8 autoneg)
1107 {
1108 /* Extended link-mode has no speed limitations. */
1109 if (ext)
1110 return 0;
1111
1112 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1113 autoneg != AUTONEG_ENABLE) {
1114 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1115 __func__);
1116 return -EINVAL;
1117 }
1118 return 0;
1119 }
1120
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1121 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1122 {
1123 u32 i, ptys_modes = 0;
1124
1125 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1126 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1127 continue;
1128 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1129 link_modes,
1130 __ETHTOOL_LINK_MODE_MASK_NBITS))
1131 ptys_modes |= MLX5E_PROT_MASK(i);
1132 }
1133
1134 return ptys_modes;
1135 }
1136
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1137 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1138 {
1139 u32 i, ptys_modes = 0;
1140 unsigned long modes[2];
1141
1142 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1143 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1144 ptys2ext_ethtool_table[i].advertised[1] == 0)
1145 continue;
1146 memset(modes, 0, sizeof(modes));
1147 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1148 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1149
1150 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1151 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1152 ptys_modes |= MLX5E_PROT_MASK(i);
1153 }
1154 return ptys_modes;
1155 }
1156
ext_link_mode_requested(const unsigned long * adver)1157 static bool ext_link_mode_requested(const unsigned long *adver)
1158 {
1159 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1160 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1161 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1162
1163 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1164 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1165 }
1166
ext_requested(u8 autoneg,const unsigned long * adver,bool ext_supported)1167 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1168 {
1169 bool ext_link_mode = ext_link_mode_requested(adver);
1170
1171 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1172 }
1173
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1174 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1175 const struct ethtool_link_ksettings *link_ksettings)
1176 {
1177 struct mlx5_core_dev *mdev = priv->mdev;
1178 struct mlx5_port_eth_proto eproto;
1179 const unsigned long *adver;
1180 bool an_changes = false;
1181 u8 an_disable_admin;
1182 bool ext_supported;
1183 u8 an_disable_cap;
1184 bool an_disable;
1185 u32 link_modes;
1186 u8 an_status;
1187 u8 autoneg;
1188 u32 speed;
1189 bool ext;
1190 int err;
1191
1192 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1193
1194 adver = link_ksettings->link_modes.advertising;
1195 autoneg = link_ksettings->base.autoneg;
1196 speed = link_ksettings->base.speed;
1197
1198 ext_supported = mlx5_ptys_ext_supported(mdev);
1199 ext = ext_requested(autoneg, adver, ext_supported);
1200 if (!ext_supported && ext)
1201 return -EOPNOTSUPP;
1202
1203 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1204 mlx5e_ethtool2ptys_adver_link;
1205 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1206 if (err) {
1207 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1208 __func__, err);
1209 goto out;
1210 }
1211 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1212 mlx5_port_speed2linkmodes(mdev, speed, !ext);
1213
1214 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1215 if (err)
1216 goto out;
1217
1218 link_modes = link_modes & eproto.cap;
1219 if (!link_modes) {
1220 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1221 __func__);
1222 err = -EINVAL;
1223 goto out;
1224 }
1225
1226 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1227 &an_disable_admin);
1228
1229 an_disable = autoneg == AUTONEG_DISABLE;
1230 an_changes = ((!an_disable && an_disable_admin) ||
1231 (an_disable && !an_disable_admin));
1232
1233 if (!an_changes && link_modes == eproto.admin)
1234 goto out;
1235
1236 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1237 if (err) {
1238 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err);
1239 goto out;
1240 }
1241
1242 mlx5_toggle_port_link(mdev);
1243
1244 out:
1245 return err;
1246 }
1247
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1248 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1249 const struct ethtool_link_ksettings *link_ksettings)
1250 {
1251 struct mlx5e_priv *priv = netdev_priv(netdev);
1252
1253 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1254 }
1255
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1256 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1257 {
1258 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key);
1259 }
1260
mlx5e_get_rxfh_key_size(struct net_device * netdev)1261 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1262 {
1263 struct mlx5e_priv *priv = netdev_priv(netdev);
1264
1265 return mlx5e_ethtool_get_rxfh_key_size(priv);
1266 }
1267
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1268 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1269 {
1270 return MLX5E_INDIR_RQT_SIZE;
1271 }
1272
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1273 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1274 {
1275 struct mlx5e_priv *priv = netdev_priv(netdev);
1276
1277 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1278 }
1279
mlx5e_get_rxfh_context(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc,u32 rss_context)1280 static int mlx5e_get_rxfh_context(struct net_device *dev, u32 *indir,
1281 u8 *key, u8 *hfunc, u32 rss_context)
1282 {
1283 struct mlx5e_priv *priv = netdev_priv(dev);
1284 int err;
1285
1286 mutex_lock(&priv->state_lock);
1287 err = mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rss_context, indir, key, hfunc);
1288 mutex_unlock(&priv->state_lock);
1289 return err;
1290 }
1291
mlx5e_set_rxfh_context(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc,u32 * rss_context,bool delete)1292 static int mlx5e_set_rxfh_context(struct net_device *dev, const u32 *indir,
1293 const u8 *key, const u8 hfunc,
1294 u32 *rss_context, bool delete)
1295 {
1296 struct mlx5e_priv *priv = netdev_priv(dev);
1297 int err;
1298
1299 mutex_lock(&priv->state_lock);
1300 if (delete) {
1301 err = mlx5e_rx_res_rss_destroy(priv->rx_res, *rss_context);
1302 goto unlock;
1303 }
1304
1305 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
1306 unsigned int count = priv->channels.params.num_channels;
1307
1308 err = mlx5e_rx_res_rss_init(priv->rx_res, rss_context, count);
1309 if (err)
1310 goto unlock;
1311 }
1312
1313 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, *rss_context, indir, key,
1314 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc);
1315
1316 unlock:
1317 mutex_unlock(&priv->state_lock);
1318 return err;
1319 }
1320
mlx5e_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)1321 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1322 u8 *hfunc)
1323 {
1324 return mlx5e_get_rxfh_context(netdev, indir, key, hfunc, 0);
1325 }
1326
mlx5e_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1327 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1328 const u8 *key, const u8 hfunc)
1329 {
1330 struct mlx5e_priv *priv = netdev_priv(dev);
1331 int err;
1332
1333 mutex_lock(&priv->state_lock);
1334 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, 0, indir, key,
1335 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc);
1336 mutex_unlock(&priv->state_lock);
1337 return err;
1338 }
1339
1340 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1341 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1342 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1343 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1344 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1345 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1346 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1347
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1348 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1349 u16 *pfc_prevention_tout)
1350 {
1351 struct mlx5e_priv *priv = netdev_priv(netdev);
1352 struct mlx5_core_dev *mdev = priv->mdev;
1353
1354 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1355 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1356 return -EOPNOTSUPP;
1357
1358 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1359 }
1360
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1361 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1362 u16 pfc_preven)
1363 {
1364 struct mlx5e_priv *priv = netdev_priv(netdev);
1365 struct mlx5_core_dev *mdev = priv->mdev;
1366 u16 critical_tout;
1367 u16 minor;
1368
1369 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1370 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1371 return -EOPNOTSUPP;
1372
1373 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1374 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1375 pfc_preven;
1376
1377 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1378 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1379 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1380 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1381 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1382 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1383 return -EINVAL;
1384 }
1385
1386 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1387 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1388 minor);
1389 }
1390
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1391 static int mlx5e_get_tunable(struct net_device *dev,
1392 const struct ethtool_tunable *tuna,
1393 void *data)
1394 {
1395 int err;
1396
1397 switch (tuna->id) {
1398 case ETHTOOL_PFC_PREVENTION_TOUT:
1399 err = mlx5e_get_pfc_prevention_tout(dev, data);
1400 break;
1401 default:
1402 err = -EINVAL;
1403 break;
1404 }
1405
1406 return err;
1407 }
1408
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1409 static int mlx5e_set_tunable(struct net_device *dev,
1410 const struct ethtool_tunable *tuna,
1411 const void *data)
1412 {
1413 struct mlx5e_priv *priv = netdev_priv(dev);
1414 int err;
1415
1416 mutex_lock(&priv->state_lock);
1417
1418 switch (tuna->id) {
1419 case ETHTOOL_PFC_PREVENTION_TOUT:
1420 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1421 break;
1422 default:
1423 err = -EINVAL;
1424 break;
1425 }
1426
1427 mutex_unlock(&priv->state_lock);
1428 return err;
1429 }
1430
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1431 static void mlx5e_get_pause_stats(struct net_device *netdev,
1432 struct ethtool_pause_stats *pause_stats)
1433 {
1434 struct mlx5e_priv *priv = netdev_priv(netdev);
1435
1436 mlx5e_stats_pause_get(priv, pause_stats);
1437 }
1438
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1439 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1440 struct ethtool_pauseparam *pauseparam)
1441 {
1442 struct mlx5_core_dev *mdev = priv->mdev;
1443 int err;
1444
1445 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1446 &pauseparam->tx_pause);
1447 if (err) {
1448 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1449 __func__, err);
1450 }
1451 }
1452
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1453 static void mlx5e_get_pauseparam(struct net_device *netdev,
1454 struct ethtool_pauseparam *pauseparam)
1455 {
1456 struct mlx5e_priv *priv = netdev_priv(netdev);
1457
1458 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1459 }
1460
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1461 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1462 struct ethtool_pauseparam *pauseparam)
1463 {
1464 struct mlx5_core_dev *mdev = priv->mdev;
1465 int err;
1466
1467 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1468 return -EOPNOTSUPP;
1469
1470 if (pauseparam->autoneg)
1471 return -EINVAL;
1472
1473 err = mlx5_set_port_pause(mdev,
1474 pauseparam->rx_pause ? 1 : 0,
1475 pauseparam->tx_pause ? 1 : 0);
1476 if (err) {
1477 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1478 __func__, err);
1479 }
1480
1481 return err;
1482 }
1483
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1484 static int mlx5e_set_pauseparam(struct net_device *netdev,
1485 struct ethtool_pauseparam *pauseparam)
1486 {
1487 struct mlx5e_priv *priv = netdev_priv(netdev);
1488
1489 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1490 }
1491
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct ethtool_ts_info * info)1492 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1493 struct ethtool_ts_info *info)
1494 {
1495 struct mlx5_core_dev *mdev = priv->mdev;
1496
1497 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1498
1499 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1500 info->phc_index == -1)
1501 return 0;
1502
1503 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1504 SOF_TIMESTAMPING_RX_HARDWARE |
1505 SOF_TIMESTAMPING_RAW_HARDWARE;
1506
1507 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1508 BIT(HWTSTAMP_TX_ON);
1509
1510 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1511 BIT(HWTSTAMP_FILTER_ALL);
1512
1513 return 0;
1514 }
1515
mlx5e_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1516 static int mlx5e_get_ts_info(struct net_device *dev,
1517 struct ethtool_ts_info *info)
1518 {
1519 struct mlx5e_priv *priv = netdev_priv(dev);
1520
1521 return mlx5e_ethtool_get_ts_info(priv, info);
1522 }
1523
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1524 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1525 {
1526 __u32 ret = 0;
1527
1528 if (MLX5_CAP_GEN(mdev, wol_g))
1529 ret |= WAKE_MAGIC;
1530
1531 if (MLX5_CAP_GEN(mdev, wol_s))
1532 ret |= WAKE_MAGICSECURE;
1533
1534 if (MLX5_CAP_GEN(mdev, wol_a))
1535 ret |= WAKE_ARP;
1536
1537 if (MLX5_CAP_GEN(mdev, wol_b))
1538 ret |= WAKE_BCAST;
1539
1540 if (MLX5_CAP_GEN(mdev, wol_m))
1541 ret |= WAKE_MCAST;
1542
1543 if (MLX5_CAP_GEN(mdev, wol_u))
1544 ret |= WAKE_UCAST;
1545
1546 if (MLX5_CAP_GEN(mdev, wol_p))
1547 ret |= WAKE_PHY;
1548
1549 return ret;
1550 }
1551
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1552 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1553 {
1554 __u32 ret = 0;
1555
1556 if (mode & MLX5_WOL_MAGIC)
1557 ret |= WAKE_MAGIC;
1558
1559 if (mode & MLX5_WOL_SECURED_MAGIC)
1560 ret |= WAKE_MAGICSECURE;
1561
1562 if (mode & MLX5_WOL_ARP)
1563 ret |= WAKE_ARP;
1564
1565 if (mode & MLX5_WOL_BROADCAST)
1566 ret |= WAKE_BCAST;
1567
1568 if (mode & MLX5_WOL_MULTICAST)
1569 ret |= WAKE_MCAST;
1570
1571 if (mode & MLX5_WOL_UNICAST)
1572 ret |= WAKE_UCAST;
1573
1574 if (mode & MLX5_WOL_PHY_ACTIVITY)
1575 ret |= WAKE_PHY;
1576
1577 return ret;
1578 }
1579
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1580 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1581 {
1582 u8 ret = 0;
1583
1584 if (mode & WAKE_MAGIC)
1585 ret |= MLX5_WOL_MAGIC;
1586
1587 if (mode & WAKE_MAGICSECURE)
1588 ret |= MLX5_WOL_SECURED_MAGIC;
1589
1590 if (mode & WAKE_ARP)
1591 ret |= MLX5_WOL_ARP;
1592
1593 if (mode & WAKE_BCAST)
1594 ret |= MLX5_WOL_BROADCAST;
1595
1596 if (mode & WAKE_MCAST)
1597 ret |= MLX5_WOL_MULTICAST;
1598
1599 if (mode & WAKE_UCAST)
1600 ret |= MLX5_WOL_UNICAST;
1601
1602 if (mode & WAKE_PHY)
1603 ret |= MLX5_WOL_PHY_ACTIVITY;
1604
1605 return ret;
1606 }
1607
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1608 static void mlx5e_get_wol(struct net_device *netdev,
1609 struct ethtool_wolinfo *wol)
1610 {
1611 struct mlx5e_priv *priv = netdev_priv(netdev);
1612 struct mlx5_core_dev *mdev = priv->mdev;
1613 u8 mlx5_wol_mode;
1614 int err;
1615
1616 memset(wol, 0, sizeof(*wol));
1617
1618 wol->supported = mlx5e_get_wol_supported(mdev);
1619 if (!wol->supported)
1620 return;
1621
1622 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1623 if (err)
1624 return;
1625
1626 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1627 }
1628
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1629 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1630 {
1631 struct mlx5e_priv *priv = netdev_priv(netdev);
1632 struct mlx5_core_dev *mdev = priv->mdev;
1633 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1634 u32 mlx5_wol_mode;
1635
1636 if (!wol_supported)
1637 return -EOPNOTSUPP;
1638
1639 if (wol->wolopts & ~wol_supported)
1640 return -EINVAL;
1641
1642 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1643
1644 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1645 }
1646
mlx5e_get_fec_stats(struct net_device * netdev,struct ethtool_fec_stats * fec_stats)1647 static void mlx5e_get_fec_stats(struct net_device *netdev,
1648 struct ethtool_fec_stats *fec_stats)
1649 {
1650 struct mlx5e_priv *priv = netdev_priv(netdev);
1651
1652 mlx5e_stats_fec_get(priv, fec_stats);
1653 }
1654
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1655 static int mlx5e_get_fecparam(struct net_device *netdev,
1656 struct ethtool_fecparam *fecparam)
1657 {
1658 struct mlx5e_priv *priv = netdev_priv(netdev);
1659 struct mlx5_core_dev *mdev = priv->mdev;
1660 u16 fec_configured;
1661 u32 fec_active;
1662 int err;
1663
1664 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1665
1666 if (err)
1667 return err;
1668
1669 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1670 sizeof(unsigned long) * BITS_PER_BYTE);
1671
1672 if (!fecparam->active_fec)
1673 return -EOPNOTSUPP;
1674
1675 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1676 sizeof(unsigned long) * BITS_PER_BYTE);
1677
1678 return 0;
1679 }
1680
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1681 static int mlx5e_set_fecparam(struct net_device *netdev,
1682 struct ethtool_fecparam *fecparam)
1683 {
1684 struct mlx5e_priv *priv = netdev_priv(netdev);
1685 struct mlx5_core_dev *mdev = priv->mdev;
1686 unsigned long fec_bitmap;
1687 u16 fec_policy = 0;
1688 int mode;
1689 int err;
1690
1691 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1692 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1693 return -EOPNOTSUPP;
1694
1695 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1696 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1697 continue;
1698 fec_policy |= (1 << mode);
1699 break;
1700 }
1701
1702 err = mlx5e_set_fec_mode(mdev, fec_policy);
1703
1704 if (err)
1705 return err;
1706
1707 mlx5_toggle_port_link(mdev);
1708
1709 return 0;
1710 }
1711
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1712 static int mlx5e_set_phys_id(struct net_device *dev,
1713 enum ethtool_phys_id_state state)
1714 {
1715 struct mlx5e_priv *priv = netdev_priv(dev);
1716 struct mlx5_core_dev *mdev = priv->mdev;
1717 u16 beacon_duration;
1718
1719 if (!MLX5_CAP_GEN(mdev, beacon_led))
1720 return -EOPNOTSUPP;
1721
1722 switch (state) {
1723 case ETHTOOL_ID_ACTIVE:
1724 beacon_duration = MLX5_BEACON_DURATION_INF;
1725 break;
1726 case ETHTOOL_ID_INACTIVE:
1727 beacon_duration = MLX5_BEACON_DURATION_OFF;
1728 break;
1729 default:
1730 return -EOPNOTSUPP;
1731 }
1732
1733 return mlx5_set_port_beacon(mdev, beacon_duration);
1734 }
1735
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1736 static int mlx5e_get_module_info(struct net_device *netdev,
1737 struct ethtool_modinfo *modinfo)
1738 {
1739 struct mlx5e_priv *priv = netdev_priv(netdev);
1740 struct mlx5_core_dev *dev = priv->mdev;
1741 int size_read = 0;
1742 u8 data[4] = {0};
1743
1744 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1745 if (size_read < 2)
1746 return -EIO;
1747
1748 /* data[0] = identifier byte */
1749 switch (data[0]) {
1750 case MLX5_MODULE_ID_QSFP:
1751 modinfo->type = ETH_MODULE_SFF_8436;
1752 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1753 break;
1754 case MLX5_MODULE_ID_QSFP_PLUS:
1755 case MLX5_MODULE_ID_QSFP28:
1756 /* data[1] = revision id */
1757 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1758 modinfo->type = ETH_MODULE_SFF_8636;
1759 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1760 } else {
1761 modinfo->type = ETH_MODULE_SFF_8436;
1762 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1763 }
1764 break;
1765 case MLX5_MODULE_ID_SFP:
1766 modinfo->type = ETH_MODULE_SFF_8472;
1767 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1768 break;
1769 default:
1770 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1771 __func__, data[0]);
1772 return -EINVAL;
1773 }
1774
1775 return 0;
1776 }
1777
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1778 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1779 struct ethtool_eeprom *ee,
1780 u8 *data)
1781 {
1782 struct mlx5e_priv *priv = netdev_priv(netdev);
1783 struct mlx5_core_dev *mdev = priv->mdev;
1784 int offset = ee->offset;
1785 int size_read;
1786 int i = 0;
1787
1788 if (!ee->len)
1789 return -EINVAL;
1790
1791 memset(data, 0, ee->len);
1792
1793 while (i < ee->len) {
1794 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1795 data + i);
1796
1797 if (!size_read)
1798 /* Done reading */
1799 return 0;
1800
1801 if (size_read < 0) {
1802 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1803 __func__, size_read);
1804 return size_read;
1805 }
1806
1807 i += size_read;
1808 offset += size_read;
1809 }
1810
1811 return 0;
1812 }
1813
mlx5e_get_module_eeprom_by_page(struct net_device * netdev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)1814 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev,
1815 const struct ethtool_module_eeprom *page_data,
1816 struct netlink_ext_ack *extack)
1817 {
1818 struct mlx5e_priv *priv = netdev_priv(netdev);
1819 struct mlx5_module_eeprom_query_params query;
1820 struct mlx5_core_dev *mdev = priv->mdev;
1821 u8 *data = page_data->data;
1822 int size_read;
1823 int i = 0;
1824
1825 if (!page_data->length)
1826 return -EINVAL;
1827
1828 memset(data, 0, page_data->length);
1829
1830 query.offset = page_data->offset;
1831 query.i2c_address = page_data->i2c_address;
1832 query.bank = page_data->bank;
1833 query.page = page_data->page;
1834 while (i < page_data->length) {
1835 query.size = page_data->length - i;
1836 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i);
1837
1838 /* Done reading, return how many bytes was read */
1839 if (!size_read)
1840 return i;
1841
1842 if (size_read == -EINVAL)
1843 return -EINVAL;
1844 if (size_read < 0) {
1845 netdev_err(priv->netdev, "%s: mlx5_query_module_eeprom_by_page failed:0x%x\n",
1846 __func__, size_read);
1847 return i;
1848 }
1849
1850 i += size_read;
1851 query.offset += size_read;
1852 }
1853
1854 return i;
1855 }
1856
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)1857 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1858 struct ethtool_flash *flash)
1859 {
1860 struct mlx5_core_dev *mdev = priv->mdev;
1861 struct net_device *dev = priv->netdev;
1862 const struct firmware *fw;
1863 int err;
1864
1865 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1866 return -EOPNOTSUPP;
1867
1868 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1869 if (err)
1870 return err;
1871
1872 dev_hold(dev);
1873 rtnl_unlock();
1874
1875 err = mlx5_firmware_flash(mdev, fw, NULL);
1876 release_firmware(fw);
1877
1878 rtnl_lock();
1879 dev_put(dev);
1880 return err;
1881 }
1882
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)1883 static int mlx5e_flash_device(struct net_device *dev,
1884 struct ethtool_flash *flash)
1885 {
1886 struct mlx5e_priv *priv = netdev_priv(dev);
1887
1888 return mlx5e_ethtool_flash_device(priv, flash);
1889 }
1890
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)1891 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1892 bool is_rx_cq)
1893 {
1894 struct mlx5e_priv *priv = netdev_priv(netdev);
1895 u8 cq_period_mode, current_cq_period_mode;
1896 struct mlx5e_params new_params;
1897
1898 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1899 return -EOPNOTSUPP;
1900
1901 cq_period_mode = cqe_mode_to_period_mode(enable);
1902
1903 current_cq_period_mode = is_rx_cq ?
1904 priv->channels.params.rx_cq_moderation.cq_period_mode :
1905 priv->channels.params.tx_cq_moderation.cq_period_mode;
1906
1907 if (cq_period_mode == current_cq_period_mode)
1908 return 0;
1909
1910 new_params = priv->channels.params;
1911 if (is_rx_cq)
1912 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode);
1913 else
1914 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode);
1915
1916 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
1917 }
1918
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)1919 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1920 {
1921 return set_pflag_cqe_based_moder(netdev, enable, false);
1922 }
1923
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)1924 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1925 {
1926 return set_pflag_cqe_based_moder(netdev, enable, true);
1927 }
1928
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val,bool rx_filter)1929 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter)
1930 {
1931 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1932 struct mlx5e_params new_params;
1933 int err = 0;
1934
1935 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1936 return new_val ? -EOPNOTSUPP : 0;
1937
1938 if (curr_val == new_val)
1939 return 0;
1940
1941 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) {
1942 netdev_err(priv->netdev,
1943 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");
1944 return -EINVAL;
1945 }
1946
1947 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
1948 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n");
1949 return -EINVAL;
1950 }
1951
1952 new_params = priv->channels.params;
1953 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1954 if (rx_filter)
1955 new_params.ptp_rx = new_val;
1956
1957 if (new_params.ptp_rx == priv->channels.params.ptp_rx)
1958 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
1959 else
1960 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
1961 &new_params.ptp_rx, true);
1962 if (err)
1963 return err;
1964
1965 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n",
1966 MLX5E_GET_PFLAG(&priv->channels.params,
1967 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1968
1969 return 0;
1970 }
1971
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)1972 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1973 bool enable)
1974 {
1975 struct mlx5e_priv *priv = netdev_priv(netdev);
1976 struct mlx5_core_dev *mdev = priv->mdev;
1977 bool rx_filter;
1978 int err;
1979
1980 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1981 return -EOPNOTSUPP;
1982
1983 rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE;
1984 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter);
1985 if (err)
1986 return err;
1987
1988 priv->channels.params.rx_cqe_compress_def = enable;
1989
1990 return 0;
1991 }
1992
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)1993 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1994 {
1995 struct mlx5e_priv *priv = netdev_priv(netdev);
1996 struct mlx5_core_dev *mdev = priv->mdev;
1997 struct mlx5e_params new_params;
1998 int err;
1999
2000 if (enable) {
2001 /* Checking the regular RQ here; mlx5e_validate_xsk_param called
2002 * from mlx5e_open_xsk will check for each XSK queue, and
2003 * mlx5e_safe_switch_params will be reverted if any check fails.
2004 */
2005 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params);
2006
2007 if (err)
2008 return err;
2009 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
2010 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n");
2011 return -EINVAL;
2012 }
2013
2014 new_params = priv->channels.params;
2015
2016 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
2017 mlx5e_set_rq_type(mdev, &new_params);
2018
2019 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2020 if (err)
2021 return err;
2022
2023 /* update XDP supported features */
2024 mlx5e_set_xdp_feature(netdev);
2025
2026 return 0;
2027 }
2028
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)2029 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
2030 {
2031 struct mlx5e_priv *priv = netdev_priv(netdev);
2032 struct mlx5e_channels *channels = &priv->channels;
2033 struct mlx5e_channel *c;
2034 int i;
2035
2036 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
2037 priv->channels.params.xdp_prog)
2038 return 0;
2039
2040 for (i = 0; i < channels->num; i++) {
2041 c = channels->c[i];
2042 if (enable)
2043 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2044 else
2045 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
2046 }
2047
2048 return 0;
2049 }
2050
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)2051 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
2052 {
2053 struct mlx5e_priv *priv = netdev_priv(netdev);
2054 struct mlx5_core_dev *mdev = priv->mdev;
2055 struct mlx5e_params new_params;
2056
2057 if (enable && !mlx5e_tx_mpwqe_supported(mdev))
2058 return -EOPNOTSUPP;
2059
2060 new_params = priv->channels.params;
2061
2062 MLX5E_SET_PFLAG(&new_params, flag, enable);
2063
2064 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true);
2065 }
2066
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)2067 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
2068 {
2069 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
2070 }
2071
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)2072 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
2073 {
2074 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
2075 }
2076
set_pflag_tx_port_ts(struct net_device * netdev,bool enable)2077 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable)
2078 {
2079 struct mlx5e_priv *priv = netdev_priv(netdev);
2080 struct mlx5_core_dev *mdev = priv->mdev;
2081 struct mlx5e_params new_params;
2082 int err;
2083
2084 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) ||
2085 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter))
2086 return -EOPNOTSUPP;
2087
2088 /* Don't allow changing the PTP state if HTB offload is active, because
2089 * the numeration of the QoS SQs will change, while per-queue qdiscs are
2090 * attached.
2091 */
2092 if (mlx5e_selq_is_htb_enabled(&priv->selq)) {
2093 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n",
2094 __func__);
2095 return -EINVAL;
2096 }
2097
2098 new_params = priv->channels.params;
2099 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is
2100 * active, since it defines explicitly which TC accepts the packet.
2101 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific
2102 * HW TX-queue.
2103 */
2104 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
2105 netdev_err(priv->netdev,
2106 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n",
2107 __func__);
2108 return -EINVAL;
2109 }
2110 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable);
2111 /* No need to verify SQ stop room as
2112 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both
2113 * has the same log_sq_size.
2114 */
2115
2116 err = mlx5e_safe_switch_params(priv, &new_params,
2117 mlx5e_num_channels_changed_ctx, NULL, true);
2118 if (!err)
2119 priv->tx_ptp_opened = true;
2120
2121 return err;
2122 }
2123
2124 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
2125 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
2126 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
2127 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
2128 { "rx_striding_rq", set_pflag_rx_striding_rq },
2129 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
2130 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
2131 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
2132 { "tx_port_ts", set_pflag_tx_port_ts },
2133 };
2134
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)2135 static int mlx5e_handle_pflag(struct net_device *netdev,
2136 u32 wanted_flags,
2137 enum mlx5e_priv_flag flag)
2138 {
2139 struct mlx5e_priv *priv = netdev_priv(netdev);
2140 bool enable = !!(wanted_flags & BIT(flag));
2141 u32 changes = wanted_flags ^ priv->channels.params.pflags;
2142 int err;
2143
2144 if (!(changes & BIT(flag)))
2145 return 0;
2146
2147 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2148 if (err) {
2149 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2150 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2151 return err;
2152 }
2153
2154 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2155 return 0;
2156 }
2157
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2158 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2159 {
2160 struct mlx5e_priv *priv = netdev_priv(netdev);
2161 enum mlx5e_priv_flag pflag;
2162 int err;
2163
2164 mutex_lock(&priv->state_lock);
2165
2166 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2167 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2168 if (err)
2169 break;
2170 }
2171
2172 mutex_unlock(&priv->state_lock);
2173
2174 /* Need to fix some features.. */
2175 netdev_update_features(netdev);
2176
2177 return err;
2178 }
2179
mlx5e_get_priv_flags(struct net_device * netdev)2180 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2181 {
2182 struct mlx5e_priv *priv = netdev_priv(netdev);
2183
2184 return priv->channels.params.pflags;
2185 }
2186
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2187 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2188 u32 *rule_locs)
2189 {
2190 struct mlx5e_priv *priv = netdev_priv(dev);
2191
2192 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2193 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2194 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2195 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2196 */
2197 if (info->cmd == ETHTOOL_GRXRINGS) {
2198 info->data = priv->channels.params.num_channels;
2199 return 0;
2200 }
2201
2202 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs);
2203 }
2204
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2205 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2206 {
2207 struct mlx5e_priv *priv = netdev_priv(dev);
2208
2209 return mlx5e_ethtool_set_rxnfc(priv, cmd);
2210 }
2211
query_port_status_opcode(struct mlx5_core_dev * mdev,u32 * status_opcode)2212 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode)
2213 {
2214 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page;
2215 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {};
2216 u32 out[MLX5_ST_SZ_DW(pddr_reg)];
2217 int err;
2218
2219 MLX5_SET(pddr_reg, in, local_port, 1);
2220 MLX5_SET(pddr_reg, in, page_select,
2221 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE);
2222
2223 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data);
2224 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2225 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR);
2226 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
2227 sizeof(out), MLX5_REG_PDDR, 0, 0);
2228 if (err)
2229 return err;
2230
2231 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data);
2232 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page,
2233 status_opcode);
2234 return 0;
2235 }
2236
2237 struct mlx5e_ethtool_link_ext_state_opcode_mapping {
2238 u32 status_opcode;
2239 enum ethtool_link_ext_state link_ext_state;
2240 u8 link_ext_substate;
2241 };
2242
2243 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping
2244 mlx5e_link_ext_state_opcode_map[] = {
2245 /* States relating to the autonegotiation or issues therein */
2246 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2247 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
2248 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2249 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
2250 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2251 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
2252 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2253 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
2254 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2255 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
2256 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
2257 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
2258
2259 /* Failure during link training */
2260 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2261 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
2262 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2263 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
2264 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2265 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
2266 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
2267 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
2268 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
2269
2270 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */
2271 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2272 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
2273 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2274 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
2275 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2276 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
2277 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2278 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
2279 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
2280 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
2281
2282 /* Signal integrity issues */
2283 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
2284 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2285 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
2286 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
2287 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
2288
2289 /* No cable connected */
2290 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
2291
2292 /* Failure is related to cable, e.g., unsupported cable */
2293 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2294 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2295 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2296 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2297 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2298 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2299 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2300 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2301 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
2302 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
2303 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
2304
2305 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */
2306 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
2307
2308 /* Failure during calibration algorithm */
2309 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
2310
2311 /* The hardware is not able to provide the power required from cable or module */
2312 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
2313
2314 /* The module is overheated */
2315 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
2316 };
2317
2318 static void
mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)2319 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping
2320 link_ext_state_mapping,
2321 struct ethtool_link_ext_state_info *link_ext_state_info)
2322 {
2323 switch (link_ext_state_mapping.link_ext_state) {
2324 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
2325 link_ext_state_info->autoneg =
2326 link_ext_state_mapping.link_ext_substate;
2327 break;
2328 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
2329 link_ext_state_info->link_training =
2330 link_ext_state_mapping.link_ext_substate;
2331 break;
2332 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
2333 link_ext_state_info->link_logical_mismatch =
2334 link_ext_state_mapping.link_ext_substate;
2335 break;
2336 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
2337 link_ext_state_info->bad_signal_integrity =
2338 link_ext_state_mapping.link_ext_substate;
2339 break;
2340 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
2341 link_ext_state_info->cable_issue =
2342 link_ext_state_mapping.link_ext_substate;
2343 break;
2344 default:
2345 break;
2346 }
2347
2348 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
2349 }
2350
2351 static int
mlx5e_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)2352 mlx5e_get_link_ext_state(struct net_device *dev,
2353 struct ethtool_link_ext_state_info *link_ext_state_info)
2354 {
2355 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
2356 struct mlx5e_priv *priv = netdev_priv(dev);
2357 u32 status_opcode = 0;
2358 int i;
2359
2360 /* Exit without data if the interface state is OK, since no extended data is
2361 * available in such case
2362 */
2363 if (netif_carrier_ok(dev))
2364 return -ENODATA;
2365
2366 if (query_port_status_opcode(priv->mdev, &status_opcode) ||
2367 !status_opcode)
2368 return -ENODATA;
2369
2370 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) {
2371 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i];
2372 if (link_ext_state_mapping.status_opcode == status_opcode) {
2373 mlx5e_set_link_ext_state(link_ext_state_mapping,
2374 link_ext_state_info);
2375 return 0;
2376 }
2377 }
2378
2379 return -ENODATA;
2380 }
2381
mlx5e_get_eth_phy_stats(struct net_device * netdev,struct ethtool_eth_phy_stats * phy_stats)2382 static void mlx5e_get_eth_phy_stats(struct net_device *netdev,
2383 struct ethtool_eth_phy_stats *phy_stats)
2384 {
2385 struct mlx5e_priv *priv = netdev_priv(netdev);
2386
2387 mlx5e_stats_eth_phy_get(priv, phy_stats);
2388 }
2389
mlx5e_get_eth_mac_stats(struct net_device * netdev,struct ethtool_eth_mac_stats * mac_stats)2390 static void mlx5e_get_eth_mac_stats(struct net_device *netdev,
2391 struct ethtool_eth_mac_stats *mac_stats)
2392 {
2393 struct mlx5e_priv *priv = netdev_priv(netdev);
2394
2395 mlx5e_stats_eth_mac_get(priv, mac_stats);
2396 }
2397
mlx5e_get_eth_ctrl_stats(struct net_device * netdev,struct ethtool_eth_ctrl_stats * ctrl_stats)2398 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev,
2399 struct ethtool_eth_ctrl_stats *ctrl_stats)
2400 {
2401 struct mlx5e_priv *priv = netdev_priv(netdev);
2402
2403 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats);
2404 }
2405
mlx5e_get_rmon_stats(struct net_device * netdev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)2406 static void mlx5e_get_rmon_stats(struct net_device *netdev,
2407 struct ethtool_rmon_stats *rmon_stats,
2408 const struct ethtool_rmon_hist_range **ranges)
2409 {
2410 struct mlx5e_priv *priv = netdev_priv(netdev);
2411
2412 mlx5e_stats_rmon_get(priv, rmon_stats, ranges);
2413 }
2414
2415 const struct ethtool_ops mlx5e_ethtool_ops = {
2416 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2417 ETHTOOL_COALESCE_MAX_FRAMES |
2418 ETHTOOL_COALESCE_USE_ADAPTIVE |
2419 ETHTOOL_COALESCE_USE_CQE,
2420 .get_drvinfo = mlx5e_get_drvinfo,
2421 .get_link = ethtool_op_get_link,
2422 .get_link_ext_state = mlx5e_get_link_ext_state,
2423 .get_strings = mlx5e_get_strings,
2424 .get_sset_count = mlx5e_get_sset_count,
2425 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2426 .get_ringparam = mlx5e_get_ringparam,
2427 .set_ringparam = mlx5e_set_ringparam,
2428 .get_channels = mlx5e_get_channels,
2429 .set_channels = mlx5e_set_channels,
2430 .get_coalesce = mlx5e_get_coalesce,
2431 .set_coalesce = mlx5e_set_coalesce,
2432 .get_link_ksettings = mlx5e_get_link_ksettings,
2433 .set_link_ksettings = mlx5e_set_link_ksettings,
2434 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2435 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2436 .get_rxfh = mlx5e_get_rxfh,
2437 .set_rxfh = mlx5e_set_rxfh,
2438 .get_rxfh_context = mlx5e_get_rxfh_context,
2439 .set_rxfh_context = mlx5e_set_rxfh_context,
2440 .get_rxnfc = mlx5e_get_rxnfc,
2441 .set_rxnfc = mlx5e_set_rxnfc,
2442 .get_tunable = mlx5e_get_tunable,
2443 .set_tunable = mlx5e_set_tunable,
2444 .get_pause_stats = mlx5e_get_pause_stats,
2445 .get_pauseparam = mlx5e_get_pauseparam,
2446 .set_pauseparam = mlx5e_set_pauseparam,
2447 .get_ts_info = mlx5e_get_ts_info,
2448 .set_phys_id = mlx5e_set_phys_id,
2449 .get_wol = mlx5e_get_wol,
2450 .set_wol = mlx5e_set_wol,
2451 .get_module_info = mlx5e_get_module_info,
2452 .get_module_eeprom = mlx5e_get_module_eeprom,
2453 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page,
2454 .flash_device = mlx5e_flash_device,
2455 .get_priv_flags = mlx5e_get_priv_flags,
2456 .set_priv_flags = mlx5e_set_priv_flags,
2457 .self_test = mlx5e_self_test,
2458 .get_fec_stats = mlx5e_get_fec_stats,
2459 .get_fecparam = mlx5e_get_fecparam,
2460 .set_fecparam = mlx5e_set_fecparam,
2461 .get_eth_phy_stats = mlx5e_get_eth_phy_stats,
2462 .get_eth_mac_stats = mlx5e_get_eth_mac_stats,
2463 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats,
2464 .get_rmon_stats = mlx5e_get_rmon_stats,
2465 .get_link_ext_stats = mlx5e_get_link_ext_stats
2466 };
2467