1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/iopoll.h>
10 #include <linux/phy/phy.h>
11 #include <net/pkt_sched.h>
12 #include <soc/mscc/ocelot_hsio.h>
13 #include <soc/mscc/ocelot_vcap.h>
14 #include "ocelot.h"
15 #include "ocelot_vcap.h"
16
17 #define TABLE_UPDATE_SLEEP_US 10
18 #define TABLE_UPDATE_TIMEOUT_US 100000
19 #define MEM_INIT_SLEEP_US 1000
20 #define MEM_INIT_TIMEOUT_US 100000
21
22 #define OCELOT_RSV_VLAN_RANGE_START 4000
23
24 struct ocelot_mact_entry {
25 u8 mac[ETH_ALEN];
26 u16 vid;
27 enum macaccess_entry_type type;
28 };
29
30 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_read_macaccess(struct ocelot * ocelot)31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
32 {
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
34 }
35
36 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_wait_for_completion(struct ocelot * ocelot)37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
38 {
39 u32 val;
40
41 return readx_poll_timeout(ocelot_mact_read_macaccess,
42 ocelot, val,
43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
44 MACACCESS_CMD_IDLE,
45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
46 }
47
48 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_select(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)49 static void ocelot_mact_select(struct ocelot *ocelot,
50 const unsigned char mac[ETH_ALEN],
51 unsigned int vid)
52 {
53 u32 macl = 0, mach = 0;
54
55 /* Set the MAC address to handle and the vlan associated in a format
56 * understood by the hardware.
57 */
58 mach |= vid << 16;
59 mach |= mac[0] << 8;
60 mach |= mac[1] << 0;
61 macl |= mac[2] << 24;
62 macl |= mac[3] << 16;
63 macl |= mac[4] << 8;
64 macl |= mac[5] << 0;
65
66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
68
69 }
70
__ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
72 const unsigned char mac[ETH_ALEN],
73 unsigned int vid, enum macaccess_entry_type type)
74 {
75 u32 cmd = ANA_TABLES_MACACCESS_VALID |
76 ANA_TABLES_MACACCESS_DEST_IDX(port) |
77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
79 unsigned int mc_ports;
80 int err;
81
82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
83 if (type == ENTRYTYPE_MACv4)
84 mc_ports = (mac[1] << 8) | mac[2];
85 else if (type == ENTRYTYPE_MACv6)
86 mc_ports = (mac[0] << 8) | mac[1];
87 else
88 mc_ports = 0;
89
90 if (mc_ports & BIT(ocelot->num_phys_ports))
91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
92
93 ocelot_mact_select(ocelot, mac, vid);
94
95 /* Issue a write command */
96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
97
98 err = ocelot_mact_wait_for_completion(ocelot);
99
100 return err;
101 }
102
ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)103 int ocelot_mact_learn(struct ocelot *ocelot, int port,
104 const unsigned char mac[ETH_ALEN],
105 unsigned int vid, enum macaccess_entry_type type)
106 {
107 int ret;
108
109 mutex_lock(&ocelot->mact_lock);
110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
111 mutex_unlock(&ocelot->mact_lock);
112
113 return ret;
114 }
115 EXPORT_SYMBOL(ocelot_mact_learn);
116
ocelot_mact_forget(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)117 int ocelot_mact_forget(struct ocelot *ocelot,
118 const unsigned char mac[ETH_ALEN], unsigned int vid)
119 {
120 int err;
121
122 mutex_lock(&ocelot->mact_lock);
123
124 ocelot_mact_select(ocelot, mac, vid);
125
126 /* Issue a forget command */
127 ocelot_write(ocelot,
128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
129 ANA_TABLES_MACACCESS);
130
131 err = ocelot_mact_wait_for_completion(ocelot);
132
133 mutex_unlock(&ocelot->mact_lock);
134
135 return err;
136 }
137 EXPORT_SYMBOL(ocelot_mact_forget);
138
ocelot_mact_lookup(struct ocelot * ocelot,int * dst_idx,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type * type)139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
140 const unsigned char mac[ETH_ALEN],
141 unsigned int vid, enum macaccess_entry_type *type)
142 {
143 int val;
144
145 mutex_lock(&ocelot->mact_lock);
146
147 ocelot_mact_select(ocelot, mac, vid);
148
149 /* Issue a read command with MACACCESS_VALID=1. */
150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
152 ANA_TABLES_MACACCESS);
153
154 if (ocelot_mact_wait_for_completion(ocelot)) {
155 mutex_unlock(&ocelot->mact_lock);
156 return -ETIMEDOUT;
157 }
158
159 /* Read back the entry flags */
160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
161
162 mutex_unlock(&ocelot->mact_lock);
163
164 if (!(val & ANA_TABLES_MACACCESS_VALID))
165 return -ENOENT;
166
167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
169
170 return 0;
171 }
172 EXPORT_SYMBOL(ocelot_mact_lookup);
173
ocelot_mact_learn_streamdata(struct ocelot * ocelot,int dst_idx,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type,int sfid,int ssid)174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
175 const unsigned char mac[ETH_ALEN],
176 unsigned int vid,
177 enum macaccess_entry_type type,
178 int sfid, int ssid)
179 {
180 int ret;
181
182 mutex_lock(&ocelot->mact_lock);
183
184 ocelot_write(ocelot,
185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
186 ANA_TABLES_STREAMDATA_SFID(sfid) |
187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
188 ANA_TABLES_STREAMDATA_SSID(ssid),
189 ANA_TABLES_STREAMDATA);
190
191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
192
193 mutex_unlock(&ocelot->mact_lock);
194
195 return ret;
196 }
197 EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
198
ocelot_mact_init(struct ocelot * ocelot)199 static void ocelot_mact_init(struct ocelot *ocelot)
200 {
201 /* Configure the learning mode entries attributes:
202 * - Do not copy the frame to the CPU extraction queues.
203 * - Use the vlan and mac_cpoy for dmac lookup.
204 */
205 ocelot_rmw(ocelot, 0,
206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
207 | ANA_AGENCTRL_LEARN_FWD_KILL
208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
209 ANA_AGENCTRL);
210
211 /* Clear the MAC table. We are not concurrent with anyone, so
212 * holding &ocelot->mact_lock is pointless.
213 */
214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
215 }
216
ocelot_pll5_init(struct ocelot * ocelot)217 void ocelot_pll5_init(struct ocelot *ocelot)
218 {
219 /* Configure PLL5. This will need a proper CCF driver
220 * The values are coming from the VTSS API for Ocelot
221 */
222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
228 HSIO_PLL5G_CFG0_ENA_BIAS |
229 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
230 HSIO_PLL5G_CFG0_ENA_CP1 |
231 HSIO_PLL5G_CFG0_SELCPI(2) |
232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
233 HSIO_PLL5G_CFG0_SELBGV820(4) |
234 HSIO_PLL5G_CFG0_DIV4 |
235 HSIO_PLL5G_CFG0_ENA_CLKTREE |
236 HSIO_PLL5G_CFG0_ENA_LANE);
237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
241 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
244 }
245 EXPORT_SYMBOL(ocelot_pll5_init);
246
ocelot_vcap_enable(struct ocelot * ocelot,int port)247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
248 {
249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
251 ANA_PORT_VCAP_S2_CFG, port);
252
253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
254 ANA_PORT_VCAP_CFG, port);
255
256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
257 REW_PORT_CFG_ES0_EN,
258 REW_PORT_CFG, port);
259 }
260
ocelot_single_vlan_aware_bridge(struct ocelot * ocelot,struct netlink_ext_ack * extack)261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
262 struct netlink_ext_ack *extack)
263 {
264 struct net_device *bridge = NULL;
265 int port;
266
267 for (port = 0; port < ocelot->num_phys_ports; port++) {
268 struct ocelot_port *ocelot_port = ocelot->ports[port];
269
270 if (!ocelot_port || !ocelot_port->bridge ||
271 !br_vlan_enabled(ocelot_port->bridge))
272 continue;
273
274 if (!bridge) {
275 bridge = ocelot_port->bridge;
276 continue;
277 }
278
279 if (bridge == ocelot_port->bridge)
280 continue;
281
282 NL_SET_ERR_MSG_MOD(extack,
283 "Only one VLAN-aware bridge is supported");
284 return -EBUSY;
285 }
286
287 return 0;
288 }
289
ocelot_vlant_read_vlanaccess(struct ocelot * ocelot)290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
291 {
292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
293 }
294
ocelot_vlant_wait_for_completion(struct ocelot * ocelot)295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
296 {
297 u32 val;
298
299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
300 ocelot,
301 val,
302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
303 ANA_TABLES_VLANACCESS_CMD_IDLE,
304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
305 }
306
ocelot_vlant_set_mask(struct ocelot * ocelot,u16 vid,u32 mask)307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
308 {
309 /* Select the VID to configure */
310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
311 ANA_TABLES_VLANTIDX);
312 /* Set the vlan port members mask and issue a write command */
313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
314 ANA_TABLES_VLANACCESS_CMD_WRITE,
315 ANA_TABLES_VLANACCESS);
316
317 return ocelot_vlant_wait_for_completion(ocelot);
318 }
319
ocelot_port_num_untagged_vlans(struct ocelot * ocelot,int port)320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
321 {
322 struct ocelot_bridge_vlan *vlan;
323 int num_untagged = 0;
324
325 list_for_each_entry(vlan, &ocelot->vlans, list) {
326 if (!(vlan->portmask & BIT(port)))
327 continue;
328
329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
330 * because this is never active in hardware at the same time as
331 * the bridge VLANs, which only matter in VLAN-aware mode.
332 */
333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
334 continue;
335
336 if (vlan->untagged & BIT(port))
337 num_untagged++;
338 }
339
340 return num_untagged;
341 }
342
ocelot_port_num_tagged_vlans(struct ocelot * ocelot,int port)343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
344 {
345 struct ocelot_bridge_vlan *vlan;
346 int num_tagged = 0;
347
348 list_for_each_entry(vlan, &ocelot->vlans, list) {
349 if (!(vlan->portmask & BIT(port)))
350 continue;
351
352 if (!(vlan->untagged & BIT(port)))
353 num_tagged++;
354 }
355
356 return num_tagged;
357 }
358
359 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
360 * _one_ egress-untagged VLAN (_the_ native VLAN)
361 */
ocelot_port_uses_native_vlan(struct ocelot * ocelot,int port)362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
363 {
364 return ocelot_port_num_tagged_vlans(ocelot, port) &&
365 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
366 }
367
368 static struct ocelot_bridge_vlan *
ocelot_port_find_native_vlan(struct ocelot * ocelot,int port)369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
370 {
371 struct ocelot_bridge_vlan *vlan;
372
373 list_for_each_entry(vlan, &ocelot->vlans, list)
374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
375 return vlan;
376
377 return NULL;
378 }
379
380 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
382 * state of the port.
383 */
ocelot_port_manage_port_tag(struct ocelot * ocelot,int port)384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
385 {
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
387 enum ocelot_port_tag_config tag_cfg;
388 bool uses_native_vlan = false;
389
390 if (ocelot_port->vlan_aware) {
391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
392
393 if (uses_native_vlan)
394 tag_cfg = OCELOT_PORT_TAG_NATIVE;
395 else if (ocelot_port_num_untagged_vlans(ocelot, port))
396 tag_cfg = OCELOT_PORT_TAG_DISABLED;
397 else
398 tag_cfg = OCELOT_PORT_TAG_TRUNK;
399 } else {
400 tag_cfg = OCELOT_PORT_TAG_DISABLED;
401 }
402
403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
404 REW_TAG_CFG_TAG_CFG_M,
405 REW_TAG_CFG, port);
406
407 if (uses_native_vlan) {
408 struct ocelot_bridge_vlan *native_vlan;
409
410 /* Not having a native VLAN is impossible, because
411 * ocelot_port_num_untagged_vlans has returned 1.
412 * So there is no use in checking for NULL here.
413 */
414 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
415
416 ocelot_rmw_gix(ocelot,
417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
418 REW_PORT_VLAN_CFG_PORT_VID_M,
419 REW_PORT_VLAN_CFG, port);
420 }
421 }
422
ocelot_bridge_num_find(struct ocelot * ocelot,const struct net_device * bridge)423 int ocelot_bridge_num_find(struct ocelot *ocelot,
424 const struct net_device *bridge)
425 {
426 int port;
427
428 for (port = 0; port < ocelot->num_phys_ports; port++) {
429 struct ocelot_port *ocelot_port = ocelot->ports[port];
430
431 if (ocelot_port && ocelot_port->bridge == bridge)
432 return ocelot_port->bridge_num;
433 }
434
435 return -1;
436 }
437 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
438
ocelot_vlan_unaware_pvid(struct ocelot * ocelot,const struct net_device * bridge)439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
440 const struct net_device *bridge)
441 {
442 int bridge_num;
443
444 /* Standalone ports use VID 0 */
445 if (!bridge)
446 return 0;
447
448 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
449 if (WARN_ON(bridge_num < 0))
450 return 0;
451
452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
453 return VLAN_N_VID - bridge_num - 1;
454 }
455
456 /* Default vlan to clasify for untagged frames (may be zero) */
ocelot_port_set_pvid(struct ocelot * ocelot,int port,const struct ocelot_bridge_vlan * pvid_vlan)457 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
458 const struct ocelot_bridge_vlan *pvid_vlan)
459 {
460 struct ocelot_port *ocelot_port = ocelot->ports[port];
461 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
462 u32 val = 0;
463
464 ocelot_port->pvid_vlan = pvid_vlan;
465
466 if (ocelot_port->vlan_aware && pvid_vlan)
467 pvid = pvid_vlan->vid;
468
469 ocelot_rmw_gix(ocelot,
470 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
471 ANA_PORT_VLAN_CFG_VLAN_VID_M,
472 ANA_PORT_VLAN_CFG, port);
473
474 /* If there's no pvid, we should drop not only untagged traffic (which
475 * happens automatically), but also 802.1p traffic which gets
476 * classified to VLAN 0, but that is always in our RX filter, so it
477 * would get accepted were it not for this setting.
478 */
479 if (!pvid_vlan && ocelot_port->vlan_aware)
480 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
481 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
482
483 ocelot_rmw_gix(ocelot, val,
484 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
485 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
486 ANA_PORT_DROP_CFG, port);
487 }
488
ocelot_bridge_vlan_find(struct ocelot * ocelot,u16 vid)489 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
490 u16 vid)
491 {
492 struct ocelot_bridge_vlan *vlan;
493
494 list_for_each_entry(vlan, &ocelot->vlans, list)
495 if (vlan->vid == vid)
496 return vlan;
497
498 return NULL;
499 }
500
ocelot_vlan_member_add(struct ocelot * ocelot,int port,u16 vid,bool untagged)501 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
502 bool untagged)
503 {
504 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
505 unsigned long portmask;
506 int err;
507
508 if (vlan) {
509 portmask = vlan->portmask | BIT(port);
510
511 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
512 if (err)
513 return err;
514
515 vlan->portmask = portmask;
516 /* Bridge VLANs can be overwritten with a different
517 * egress-tagging setting, so make sure to override an untagged
518 * with a tagged VID if that's going on.
519 */
520 if (untagged)
521 vlan->untagged |= BIT(port);
522 else
523 vlan->untagged &= ~BIT(port);
524
525 return 0;
526 }
527
528 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
529 if (!vlan)
530 return -ENOMEM;
531
532 portmask = BIT(port);
533
534 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
535 if (err) {
536 kfree(vlan);
537 return err;
538 }
539
540 vlan->vid = vid;
541 vlan->portmask = portmask;
542 if (untagged)
543 vlan->untagged = BIT(port);
544 INIT_LIST_HEAD(&vlan->list);
545 list_add_tail(&vlan->list, &ocelot->vlans);
546
547 return 0;
548 }
549
ocelot_vlan_member_del(struct ocelot * ocelot,int port,u16 vid)550 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
551 {
552 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
553 unsigned long portmask;
554 int err;
555
556 if (!vlan)
557 return 0;
558
559 portmask = vlan->portmask & ~BIT(port);
560
561 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
562 if (err)
563 return err;
564
565 vlan->portmask = portmask;
566 if (vlan->portmask)
567 return 0;
568
569 list_del(&vlan->list);
570 kfree(vlan);
571
572 return 0;
573 }
574
ocelot_add_vlan_unaware_pvid(struct ocelot * ocelot,int port,const struct net_device * bridge)575 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
576 const struct net_device *bridge)
577 {
578 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
579
580 return ocelot_vlan_member_add(ocelot, port, vid, true);
581 }
582
ocelot_del_vlan_unaware_pvid(struct ocelot * ocelot,int port,const struct net_device * bridge)583 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
584 const struct net_device *bridge)
585 {
586 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
587
588 return ocelot_vlan_member_del(ocelot, port, vid);
589 }
590
ocelot_port_vlan_filtering(struct ocelot * ocelot,int port,bool vlan_aware,struct netlink_ext_ack * extack)591 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
592 bool vlan_aware, struct netlink_ext_ack *extack)
593 {
594 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
595 struct ocelot_port *ocelot_port = ocelot->ports[port];
596 struct ocelot_vcap_filter *filter;
597 int err = 0;
598 u32 val;
599
600 list_for_each_entry(filter, &block->rules, list) {
601 if (filter->ingress_port_mask & BIT(port) &&
602 filter->action.vid_replace_ena) {
603 NL_SET_ERR_MSG_MOD(extack,
604 "Cannot change VLAN state with vlan modify rules active");
605 return -EBUSY;
606 }
607 }
608
609 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
610 if (err)
611 return err;
612
613 if (vlan_aware)
614 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
615 ocelot_port->bridge);
616 else if (ocelot_port->bridge)
617 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
618 ocelot_port->bridge);
619 if (err)
620 return err;
621
622 ocelot_port->vlan_aware = vlan_aware;
623
624 if (vlan_aware)
625 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
626 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
627 else
628 val = 0;
629 ocelot_rmw_gix(ocelot, val,
630 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
631 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
632 ANA_PORT_VLAN_CFG, port);
633
634 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
635 ocelot_port_manage_port_tag(ocelot, port);
636
637 return 0;
638 }
639 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
640
ocelot_vlan_prepare(struct ocelot * ocelot,int port,u16 vid,bool pvid,bool untagged,struct netlink_ext_ack * extack)641 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
642 bool untagged, struct netlink_ext_ack *extack)
643 {
644 if (untagged) {
645 /* We are adding an egress-tagged VLAN */
646 if (ocelot_port_uses_native_vlan(ocelot, port)) {
647 NL_SET_ERR_MSG_MOD(extack,
648 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
649 return -EBUSY;
650 }
651 } else {
652 /* We are adding an egress-tagged VLAN */
653 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
654 NL_SET_ERR_MSG_MOD(extack,
655 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
656 return -EBUSY;
657 }
658 }
659
660 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
661 NL_SET_ERR_MSG_MOD(extack,
662 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
663 return -EBUSY;
664 }
665
666 return 0;
667 }
668 EXPORT_SYMBOL(ocelot_vlan_prepare);
669
ocelot_vlan_add(struct ocelot * ocelot,int port,u16 vid,bool pvid,bool untagged)670 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
671 bool untagged)
672 {
673 int err;
674
675 /* Ignore VID 0 added to our RX filter by the 8021q module, since
676 * that collides with OCELOT_STANDALONE_PVID and changes it from
677 * egress-untagged to egress-tagged.
678 */
679 if (!vid)
680 return 0;
681
682 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
683 if (err)
684 return err;
685
686 /* Default ingress vlan classification */
687 if (pvid)
688 ocelot_port_set_pvid(ocelot, port,
689 ocelot_bridge_vlan_find(ocelot, vid));
690
691 /* Untagged egress vlan clasification */
692 ocelot_port_manage_port_tag(ocelot, port);
693
694 return 0;
695 }
696 EXPORT_SYMBOL(ocelot_vlan_add);
697
ocelot_vlan_del(struct ocelot * ocelot,int port,u16 vid)698 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
699 {
700 struct ocelot_port *ocelot_port = ocelot->ports[port];
701 bool del_pvid = false;
702 int err;
703
704 if (!vid)
705 return 0;
706
707 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
708 del_pvid = true;
709
710 err = ocelot_vlan_member_del(ocelot, port, vid);
711 if (err)
712 return err;
713
714 /* Ingress */
715 if (del_pvid)
716 ocelot_port_set_pvid(ocelot, port, NULL);
717
718 /* Egress */
719 ocelot_port_manage_port_tag(ocelot, port);
720
721 return 0;
722 }
723 EXPORT_SYMBOL(ocelot_vlan_del);
724
ocelot_vlan_init(struct ocelot * ocelot)725 static void ocelot_vlan_init(struct ocelot *ocelot)
726 {
727 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
728 u16 port, vid;
729
730 /* Clear VLAN table, by default all ports are members of all VLANs */
731 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
732 ANA_TABLES_VLANACCESS);
733 ocelot_vlant_wait_for_completion(ocelot);
734
735 /* Configure the port VLAN memberships */
736 for (vid = 1; vid < VLAN_N_VID; vid++)
737 ocelot_vlant_set_mask(ocelot, vid, 0);
738
739 /* We need VID 0 to get traffic on standalone ports.
740 * It is added automatically if the 8021q module is loaded, but we
741 * can't rely on that since it might not be.
742 */
743 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
744
745 /* Set vlan ingress filter mask to all ports but the CPU port by
746 * default.
747 */
748 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
749
750 for (port = 0; port < ocelot->num_phys_ports; port++) {
751 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
752 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
753 }
754 }
755
ocelot_read_eq_avail(struct ocelot * ocelot,int port)756 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
757 {
758 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
759 }
760
ocelot_port_flush(struct ocelot * ocelot,int port)761 static int ocelot_port_flush(struct ocelot *ocelot, int port)
762 {
763 unsigned int pause_ena;
764 int err, val;
765
766 /* Disable dequeuing from the egress queues */
767 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
768 QSYS_PORT_MODE_DEQUEUE_DIS,
769 QSYS_PORT_MODE, port);
770
771 /* Disable flow control */
772 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
773 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
774
775 /* Disable priority flow control */
776 ocelot_fields_write(ocelot, port,
777 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
778
779 /* Wait at least the time it takes to receive a frame of maximum length
780 * at the port.
781 * Worst-case delays for 10 kilobyte jumbo frames are:
782 * 8 ms on a 10M port
783 * 800 μs on a 100M port
784 * 80 μs on a 1G port
785 * 32 μs on a 2.5G port
786 */
787 usleep_range(8000, 10000);
788
789 /* Disable half duplex backpressure. */
790 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
791 SYS_FRONT_PORT_MODE, port);
792
793 /* Flush the queues associated with the port. */
794 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
795 REW_PORT_CFG, port);
796
797 /* Enable dequeuing from the egress queues. */
798 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
799 port);
800
801 /* Wait until flushing is complete. */
802 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
803 100, 2000000, false, ocelot, port);
804
805 /* Clear flushing again. */
806 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
807
808 /* Re-enable flow control */
809 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
810
811 return err;
812 }
813
ocelot_port_configure_serdes(struct ocelot * ocelot,int port,struct device_node * portnp)814 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
815 struct device_node *portnp)
816 {
817 struct ocelot_port *ocelot_port = ocelot->ports[port];
818 struct device *dev = ocelot->dev;
819 int err;
820
821 /* Ensure clock signals and speed are set on all QSGMII links */
822 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII)
823 ocelot_port_rmwl(ocelot_port, 0,
824 DEV_CLOCK_CFG_MAC_TX_RST |
825 DEV_CLOCK_CFG_MAC_RX_RST,
826 DEV_CLOCK_CFG);
827
828 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
829 struct phy *serdes = of_phy_get(portnp, NULL);
830
831 if (IS_ERR(serdes)) {
832 err = PTR_ERR(serdes);
833 dev_err_probe(dev, err,
834 "missing SerDes phys for port %d\n",
835 port);
836 return err;
837 }
838
839 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET,
840 ocelot_port->phy_mode);
841 of_phy_put(serdes);
842 if (err) {
843 dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
844 port, ERR_PTR(err));
845 return err;
846 }
847 }
848
849 return 0;
850 }
851 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes);
852
ocelot_phylink_mac_config(struct ocelot * ocelot,int port,unsigned int link_an_mode,const struct phylink_link_state * state)853 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
854 unsigned int link_an_mode,
855 const struct phylink_link_state *state)
856 {
857 struct ocelot_port *ocelot_port = ocelot->ports[port];
858
859 /* Disable HDX fast control */
860 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
861 DEV_PORT_MISC);
862
863 /* SGMII only for now */
864 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
865 PCS1G_MODE_CFG);
866 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
867
868 /* Enable PCS */
869 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
870
871 /* No aneg on SGMII */
872 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
873
874 /* No loopback */
875 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
876 }
877 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config);
878
ocelot_phylink_mac_link_down(struct ocelot * ocelot,int port,unsigned int link_an_mode,phy_interface_t interface,unsigned long quirks)879 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
880 unsigned int link_an_mode,
881 phy_interface_t interface,
882 unsigned long quirks)
883 {
884 struct ocelot_port *ocelot_port = ocelot->ports[port];
885 int err;
886
887 ocelot_port->speed = SPEED_UNKNOWN;
888
889 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
890 DEV_MAC_ENA_CFG);
891
892 if (ocelot->ops->cut_through_fwd) {
893 mutex_lock(&ocelot->fwd_domain_lock);
894 ocelot->ops->cut_through_fwd(ocelot);
895 mutex_unlock(&ocelot->fwd_domain_lock);
896 }
897
898 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
899
900 err = ocelot_port_flush(ocelot, port);
901 if (err)
902 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
903 port, err);
904
905 /* Put the port in reset. */
906 if (interface != PHY_INTERFACE_MODE_QSGMII ||
907 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
908 ocelot_port_rmwl(ocelot_port,
909 DEV_CLOCK_CFG_MAC_TX_RST |
910 DEV_CLOCK_CFG_MAC_RX_RST,
911 DEV_CLOCK_CFG_MAC_TX_RST |
912 DEV_CLOCK_CFG_MAC_RX_RST,
913 DEV_CLOCK_CFG);
914 }
915 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
916
ocelot_phylink_mac_link_up(struct ocelot * ocelot,int port,struct phy_device * phydev,unsigned int link_an_mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause,unsigned long quirks)917 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
918 struct phy_device *phydev,
919 unsigned int link_an_mode,
920 phy_interface_t interface,
921 int speed, int duplex,
922 bool tx_pause, bool rx_pause,
923 unsigned long quirks)
924 {
925 struct ocelot_port *ocelot_port = ocelot->ports[port];
926 int mac_speed, mode = 0;
927 u32 mac_fc_cfg;
928
929 ocelot_port->speed = speed;
930
931 /* The MAC might be integrated in systems where the MAC speed is fixed
932 * and it's the PCS who is performing the rate adaptation, so we have
933 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
934 * (which is also its default value).
935 */
936 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
937 speed == SPEED_1000) {
938 mac_speed = OCELOT_SPEED_1000;
939 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
940 } else if (speed == SPEED_2500) {
941 mac_speed = OCELOT_SPEED_2500;
942 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
943 } else if (speed == SPEED_100) {
944 mac_speed = OCELOT_SPEED_100;
945 } else {
946 mac_speed = OCELOT_SPEED_10;
947 }
948
949 if (duplex == DUPLEX_FULL)
950 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
951
952 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
953
954 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
955 * PORT_RST bits in DEV_CLOCK_CFG.
956 */
957 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
958 DEV_CLOCK_CFG);
959
960 switch (speed) {
961 case SPEED_10:
962 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
963 break;
964 case SPEED_100:
965 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
966 break;
967 case SPEED_1000:
968 case SPEED_2500:
969 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
970 break;
971 default:
972 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
973 port, speed);
974 return;
975 }
976
977 if (rx_pause)
978 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
979
980 if (tx_pause)
981 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
982 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
983 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
984 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
985
986 /* Flow control. Link speed is only used here to evaluate the time
987 * specification in incoming pause frames.
988 */
989 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
990
991 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
992
993 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
994 if (port != ocelot->npi)
995 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
996 tx_pause);
997
998 /* Undo the effects of ocelot_phylink_mac_link_down:
999 * enable MAC module
1000 */
1001 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
1002 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
1003
1004 /* If the port supports cut-through forwarding, update the masks before
1005 * enabling forwarding on the port.
1006 */
1007 if (ocelot->ops->cut_through_fwd) {
1008 mutex_lock(&ocelot->fwd_domain_lock);
1009 /* Workaround for hardware bug - FP doesn't work
1010 * at all link speeds for all PHY modes. The function
1011 * below also calls ocelot->ops->cut_through_fwd(),
1012 * so we don't need to do it twice.
1013 */
1014 ocelot_port_update_active_preemptible_tcs(ocelot, port);
1015 mutex_unlock(&ocelot->fwd_domain_lock);
1016 }
1017
1018 /* Core: Enable port for frame transfer */
1019 ocelot_fields_write(ocelot, port,
1020 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1021 }
1022 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
1023
ocelot_rx_frame_word(struct ocelot * ocelot,u8 grp,bool ifh,u32 * rval)1024 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1025 u32 *rval)
1026 {
1027 u32 bytes_valid, val;
1028
1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1030 if (val == XTR_NOT_READY) {
1031 if (ifh)
1032 return -EIO;
1033
1034 do {
1035 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1036 } while (val == XTR_NOT_READY);
1037 }
1038
1039 switch (val) {
1040 case XTR_ABORT:
1041 return -EIO;
1042 case XTR_EOF_0:
1043 case XTR_EOF_1:
1044 case XTR_EOF_2:
1045 case XTR_EOF_3:
1046 case XTR_PRUNED:
1047 bytes_valid = XTR_VALID_BYTES(val);
1048 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1049 if (val == XTR_ESCAPE)
1050 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1051 else
1052 *rval = val;
1053
1054 return bytes_valid;
1055 case XTR_ESCAPE:
1056 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1057
1058 return 4;
1059 default:
1060 *rval = val;
1061
1062 return 4;
1063 }
1064 }
1065
ocelot_xtr_poll_xfh(struct ocelot * ocelot,int grp,u32 * xfh)1066 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1067 {
1068 int i, err = 0;
1069
1070 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1071 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1072 if (err != 4)
1073 return (err < 0) ? err : -EIO;
1074 }
1075
1076 return 0;
1077 }
1078
ocelot_ptp_rx_timestamp(struct ocelot * ocelot,struct sk_buff * skb,u64 timestamp)1079 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1080 u64 timestamp)
1081 {
1082 struct skb_shared_hwtstamps *shhwtstamps;
1083 u64 tod_in_ns, full_ts_in_ns;
1084 struct timespec64 ts;
1085
1086 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1087
1088 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1089 if ((tod_in_ns & 0xffffffff) < timestamp)
1090 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1091 timestamp;
1092 else
1093 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1094 timestamp;
1095
1096 shhwtstamps = skb_hwtstamps(skb);
1097 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1098 shhwtstamps->hwtstamp = full_ts_in_ns;
1099 }
1100 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1101
ocelot_lock_inj_grp(struct ocelot * ocelot,int grp)1102 void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp)
1103 __acquires(&ocelot->inj_lock)
1104 {
1105 spin_lock(&ocelot->inj_lock);
1106 }
1107 EXPORT_SYMBOL_GPL(ocelot_lock_inj_grp);
1108
ocelot_unlock_inj_grp(struct ocelot * ocelot,int grp)1109 void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp)
1110 __releases(&ocelot->inj_lock)
1111 {
1112 spin_unlock(&ocelot->inj_lock);
1113 }
1114 EXPORT_SYMBOL_GPL(ocelot_unlock_inj_grp);
1115
ocelot_lock_xtr_grp(struct ocelot * ocelot,int grp)1116 void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp)
1117 __acquires(&ocelot->inj_lock)
1118 {
1119 spin_lock(&ocelot->inj_lock);
1120 }
1121 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp);
1122
ocelot_unlock_xtr_grp(struct ocelot * ocelot,int grp)1123 void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp)
1124 __releases(&ocelot->inj_lock)
1125 {
1126 spin_unlock(&ocelot->inj_lock);
1127 }
1128 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp);
1129
ocelot_lock_xtr_grp_bh(struct ocelot * ocelot,int grp)1130 void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1131 __acquires(&ocelot->xtr_lock)
1132 {
1133 spin_lock_bh(&ocelot->xtr_lock);
1134 }
1135 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp_bh);
1136
ocelot_unlock_xtr_grp_bh(struct ocelot * ocelot,int grp)1137 void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1138 __releases(&ocelot->xtr_lock)
1139 {
1140 spin_unlock_bh(&ocelot->xtr_lock);
1141 }
1142 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp_bh);
1143
ocelot_xtr_poll_frame(struct ocelot * ocelot,int grp,struct sk_buff ** nskb)1144 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1145 {
1146 u64 timestamp, src_port, len;
1147 u32 xfh[OCELOT_TAG_LEN / 4];
1148 struct net_device *dev;
1149 struct sk_buff *skb;
1150 int sz, buf_len;
1151 u32 val, *buf;
1152 int err;
1153
1154 lockdep_assert_held(&ocelot->xtr_lock);
1155
1156 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1157 if (err)
1158 return err;
1159
1160 ocelot_xfh_get_src_port(xfh, &src_port);
1161 ocelot_xfh_get_len(xfh, &len);
1162 ocelot_xfh_get_rew_val(xfh, ×tamp);
1163
1164 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1165 return -EINVAL;
1166
1167 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1168 if (!dev)
1169 return -EINVAL;
1170
1171 skb = netdev_alloc_skb(dev, len);
1172 if (unlikely(!skb)) {
1173 netdev_err(dev, "Unable to allocate sk_buff\n");
1174 return -ENOMEM;
1175 }
1176
1177 buf_len = len - ETH_FCS_LEN;
1178 buf = (u32 *)skb_put(skb, buf_len);
1179
1180 len = 0;
1181 do {
1182 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1183 if (sz < 0) {
1184 err = sz;
1185 goto out_free_skb;
1186 }
1187 *buf++ = val;
1188 len += sz;
1189 } while (len < buf_len);
1190
1191 /* Read the FCS */
1192 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1193 if (sz < 0) {
1194 err = sz;
1195 goto out_free_skb;
1196 }
1197
1198 /* Update the statistics if part of the FCS was read before */
1199 len -= ETH_FCS_LEN - sz;
1200
1201 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1202 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1203 *buf = val;
1204 }
1205
1206 if (ocelot->ptp)
1207 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1208
1209 /* Everything we see on an interface that is in the HW bridge
1210 * has already been forwarded.
1211 */
1212 if (ocelot->ports[src_port]->bridge)
1213 skb->offload_fwd_mark = 1;
1214
1215 skb->protocol = eth_type_trans(skb, dev);
1216
1217 *nskb = skb;
1218
1219 return 0;
1220
1221 out_free_skb:
1222 kfree_skb(skb);
1223 return err;
1224 }
1225 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1226
ocelot_can_inject(struct ocelot * ocelot,int grp)1227 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1228 {
1229 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1230
1231 lockdep_assert_held(&ocelot->inj_lock);
1232
1233 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1234 return false;
1235 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1236 return false;
1237
1238 return true;
1239 }
1240 EXPORT_SYMBOL(ocelot_can_inject);
1241
1242 /**
1243 * ocelot_ifh_set_basic - Set basic information in Injection Frame Header
1244 * @ifh: Pointer to Injection Frame Header memory
1245 * @ocelot: Switch private data structure
1246 * @port: Egress port number
1247 * @rew_op: Egress rewriter operation for PTP
1248 * @skb: Pointer to socket buffer (packet)
1249 *
1250 * Populate the Injection Frame Header with basic information for this skb: the
1251 * analyzer bypass bit, destination port, VLAN info, egress rewriter info.
1252 */
ocelot_ifh_set_basic(void * ifh,struct ocelot * ocelot,int port,u32 rew_op,struct sk_buff * skb)1253 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port,
1254 u32 rew_op, struct sk_buff *skb)
1255 {
1256 struct ocelot_port *ocelot_port = ocelot->ports[port];
1257 struct net_device *dev = skb->dev;
1258 u64 vlan_tci, tag_type;
1259 int qos_class;
1260
1261 ocelot_xmit_get_vlan_info(skb, ocelot_port->bridge, &vlan_tci,
1262 &tag_type);
1263
1264 qos_class = netdev_get_num_tc(dev) ?
1265 netdev_get_prio_tc_map(dev, skb->priority) : skb->priority;
1266
1267 memset(ifh, 0, OCELOT_TAG_LEN);
1268 ocelot_ifh_set_bypass(ifh, 1);
1269 ocelot_ifh_set_src(ifh, BIT_ULL(ocelot->num_phys_ports));
1270 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1271 ocelot_ifh_set_qos_class(ifh, qos_class);
1272 ocelot_ifh_set_tag_type(ifh, tag_type);
1273 ocelot_ifh_set_vlan_tci(ifh, vlan_tci);
1274 if (rew_op)
1275 ocelot_ifh_set_rew_op(ifh, rew_op);
1276 }
1277 EXPORT_SYMBOL(ocelot_ifh_set_basic);
1278
ocelot_port_inject_frame(struct ocelot * ocelot,int port,int grp,u32 rew_op,struct sk_buff * skb)1279 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1280 u32 rew_op, struct sk_buff *skb)
1281 {
1282 u32 ifh[OCELOT_TAG_LEN / 4];
1283 unsigned int i, count, last;
1284
1285 lockdep_assert_held(&ocelot->inj_lock);
1286
1287 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1288 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1289
1290 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb);
1291
1292 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1293 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1294
1295 count = DIV_ROUND_UP(skb->len, 4);
1296 last = skb->len % 4;
1297 for (i = 0; i < count; i++)
1298 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1299
1300 /* Add padding */
1301 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1302 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1303 i++;
1304 }
1305
1306 /* Indicate EOF and valid bytes in last word */
1307 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1308 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1309 QS_INJ_CTRL_EOF,
1310 QS_INJ_CTRL, grp);
1311
1312 /* Add dummy CRC */
1313 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1314 skb_tx_timestamp(skb);
1315
1316 skb->dev->stats.tx_packets++;
1317 skb->dev->stats.tx_bytes += skb->len;
1318 }
1319 EXPORT_SYMBOL(ocelot_port_inject_frame);
1320
ocelot_drain_cpu_queue(struct ocelot * ocelot,int grp)1321 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1322 {
1323 lockdep_assert_held(&ocelot->xtr_lock);
1324
1325 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1326 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1327 }
1328 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1329
ocelot_fdb_add(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid,const struct net_device * bridge)1330 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1331 u16 vid, const struct net_device *bridge)
1332 {
1333 if (!vid)
1334 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1335
1336 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1337 }
1338 EXPORT_SYMBOL(ocelot_fdb_add);
1339
ocelot_fdb_del(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid,const struct net_device * bridge)1340 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1341 u16 vid, const struct net_device *bridge)
1342 {
1343 if (!vid)
1344 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1345
1346 return ocelot_mact_forget(ocelot, addr, vid);
1347 }
1348 EXPORT_SYMBOL(ocelot_fdb_del);
1349
1350 /* Caller must hold &ocelot->mact_lock */
ocelot_mact_read(struct ocelot * ocelot,int port,int row,int col,struct ocelot_mact_entry * entry)1351 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1352 struct ocelot_mact_entry *entry)
1353 {
1354 u32 val, dst, macl, mach;
1355 char mac[ETH_ALEN];
1356
1357 /* Set row and column to read from */
1358 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1359 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1360
1361 /* Issue a read command */
1362 ocelot_write(ocelot,
1363 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1364 ANA_TABLES_MACACCESS);
1365
1366 if (ocelot_mact_wait_for_completion(ocelot))
1367 return -ETIMEDOUT;
1368
1369 /* Read the entry flags */
1370 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1371 if (!(val & ANA_TABLES_MACACCESS_VALID))
1372 return -EINVAL;
1373
1374 /* If the entry read has another port configured as its destination,
1375 * do not report it.
1376 */
1377 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1378 if (dst != port)
1379 return -EINVAL;
1380
1381 /* Get the entry's MAC address and VLAN id */
1382 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1383 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1384
1385 mac[0] = (mach >> 8) & 0xff;
1386 mac[1] = (mach >> 0) & 0xff;
1387 mac[2] = (macl >> 24) & 0xff;
1388 mac[3] = (macl >> 16) & 0xff;
1389 mac[4] = (macl >> 8) & 0xff;
1390 mac[5] = (macl >> 0) & 0xff;
1391
1392 entry->vid = (mach >> 16) & 0xfff;
1393 ether_addr_copy(entry->mac, mac);
1394
1395 return 0;
1396 }
1397
ocelot_mact_flush(struct ocelot * ocelot,int port)1398 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1399 {
1400 int err;
1401
1402 mutex_lock(&ocelot->mact_lock);
1403
1404 /* Program ageing filter for a single port */
1405 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1406 ANA_ANAGEFIL);
1407
1408 /* Flushing dynamic FDB entries requires two successive age scans */
1409 ocelot_write(ocelot,
1410 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1411 ANA_TABLES_MACACCESS);
1412
1413 err = ocelot_mact_wait_for_completion(ocelot);
1414 if (err) {
1415 mutex_unlock(&ocelot->mact_lock);
1416 return err;
1417 }
1418
1419 /* And second... */
1420 ocelot_write(ocelot,
1421 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1422 ANA_TABLES_MACACCESS);
1423
1424 err = ocelot_mact_wait_for_completion(ocelot);
1425
1426 /* Restore ageing filter */
1427 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1428
1429 mutex_unlock(&ocelot->mact_lock);
1430
1431 return err;
1432 }
1433 EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1434
ocelot_fdb_dump(struct ocelot * ocelot,int port,dsa_fdb_dump_cb_t * cb,void * data)1435 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1436 dsa_fdb_dump_cb_t *cb, void *data)
1437 {
1438 int err = 0;
1439 int i, j;
1440
1441 /* We could take the lock just around ocelot_mact_read, but doing so
1442 * thousands of times in a row seems rather pointless and inefficient.
1443 */
1444 mutex_lock(&ocelot->mact_lock);
1445
1446 /* Loop through all the mac tables entries. */
1447 for (i = 0; i < ocelot->num_mact_rows; i++) {
1448 for (j = 0; j < 4; j++) {
1449 struct ocelot_mact_entry entry;
1450 bool is_static;
1451
1452 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1453 /* If the entry is invalid (wrong port, invalid...),
1454 * skip it.
1455 */
1456 if (err == -EINVAL)
1457 continue;
1458 else if (err)
1459 break;
1460
1461 is_static = (entry.type == ENTRYTYPE_LOCKED);
1462
1463 /* Hide the reserved VLANs used for
1464 * VLAN-unaware bridging.
1465 */
1466 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1467 entry.vid = 0;
1468
1469 err = cb(entry.mac, entry.vid, is_static, data);
1470 if (err)
1471 break;
1472 }
1473 }
1474
1475 mutex_unlock(&ocelot->mact_lock);
1476
1477 return err;
1478 }
1479 EXPORT_SYMBOL(ocelot_fdb_dump);
1480
ocelot_trap_add(struct ocelot * ocelot,int port,unsigned long cookie,bool take_ts,void (* populate)(struct ocelot_vcap_filter * f))1481 int ocelot_trap_add(struct ocelot *ocelot, int port,
1482 unsigned long cookie, bool take_ts,
1483 void (*populate)(struct ocelot_vcap_filter *f))
1484 {
1485 struct ocelot_vcap_block *block_vcap_is2;
1486 struct ocelot_vcap_filter *trap;
1487 bool new = false;
1488 int err;
1489
1490 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1491
1492 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1493 false);
1494 if (!trap) {
1495 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1496 if (!trap)
1497 return -ENOMEM;
1498
1499 populate(trap);
1500 trap->prio = 1;
1501 trap->id.cookie = cookie;
1502 trap->id.tc_offload = false;
1503 trap->block_id = VCAP_IS2;
1504 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1505 trap->lookup = 0;
1506 trap->action.cpu_copy_ena = true;
1507 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1508 trap->action.port_mask = 0;
1509 trap->take_ts = take_ts;
1510 trap->is_trap = true;
1511 new = true;
1512 }
1513
1514 trap->ingress_port_mask |= BIT(port);
1515
1516 if (new)
1517 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1518 else
1519 err = ocelot_vcap_filter_replace(ocelot, trap);
1520 if (err) {
1521 trap->ingress_port_mask &= ~BIT(port);
1522 if (!trap->ingress_port_mask)
1523 kfree(trap);
1524 return err;
1525 }
1526
1527 return 0;
1528 }
1529
ocelot_trap_del(struct ocelot * ocelot,int port,unsigned long cookie)1530 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1531 {
1532 struct ocelot_vcap_block *block_vcap_is2;
1533 struct ocelot_vcap_filter *trap;
1534
1535 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1536
1537 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1538 false);
1539 if (!trap)
1540 return 0;
1541
1542 trap->ingress_port_mask &= ~BIT(port);
1543 if (!trap->ingress_port_mask)
1544 return ocelot_vcap_filter_del(ocelot, trap);
1545
1546 return ocelot_vcap_filter_replace(ocelot, trap);
1547 }
1548
ocelot_get_bond_mask(struct ocelot * ocelot,struct net_device * bond)1549 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1550 {
1551 u32 mask = 0;
1552 int port;
1553
1554 lockdep_assert_held(&ocelot->fwd_domain_lock);
1555
1556 for (port = 0; port < ocelot->num_phys_ports; port++) {
1557 struct ocelot_port *ocelot_port = ocelot->ports[port];
1558
1559 if (!ocelot_port)
1560 continue;
1561
1562 if (ocelot_port->bond == bond)
1563 mask |= BIT(port);
1564 }
1565
1566 return mask;
1567 }
1568
1569 /* The logical port number of a LAG is equal to the lowest numbered physical
1570 * port ID present in that LAG. It may change if that port ever leaves the LAG.
1571 */
ocelot_bond_get_id(struct ocelot * ocelot,struct net_device * bond)1572 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1573 {
1574 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1575
1576 if (!bond_mask)
1577 return -ENOENT;
1578
1579 return __ffs(bond_mask);
1580 }
1581 EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1582
1583 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1584 * Note that when CPU ports are in a LAG, the user ports are assigned to the
1585 * 'primary' CPU port, the one whose physical port number gives the logical
1586 * port number of the LAG.
1587 *
1588 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1589 * (to which no user port is assigned), but it appears that forwarding from
1590 * this secondary CPU port looks at the PGID_SRC associated with the logical
1591 * port ID that it's assigned to, which *is* configured properly.
1592 */
ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot * ocelot,struct ocelot_port * cpu)1593 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1594 struct ocelot_port *cpu)
1595 {
1596 u32 mask = 0;
1597 int port;
1598
1599 for (port = 0; port < ocelot->num_phys_ports; port++) {
1600 struct ocelot_port *ocelot_port = ocelot->ports[port];
1601
1602 if (!ocelot_port)
1603 continue;
1604
1605 if (ocelot_port->dsa_8021q_cpu == cpu)
1606 mask |= BIT(port);
1607 }
1608
1609 if (cpu->bond)
1610 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1611
1612 return mask;
1613 }
1614
1615 /* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1616 * or the bit mask of CPU ports if said CPU port is in a LAG.
1617 */
ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot * ocelot,int port)1618 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1619 {
1620 struct ocelot_port *ocelot_port = ocelot->ports[port];
1621 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1622
1623 if (!cpu_port)
1624 return 0;
1625
1626 if (cpu_port->bond)
1627 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1628
1629 return BIT(cpu_port->index);
1630 }
1631 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1632
ocelot_get_bridge_fwd_mask(struct ocelot * ocelot,int src_port)1633 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1634 {
1635 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1636 const struct net_device *bridge;
1637 u32 mask = 0;
1638 int port;
1639
1640 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1641 return 0;
1642
1643 bridge = ocelot_port->bridge;
1644 if (!bridge)
1645 return 0;
1646
1647 for (port = 0; port < ocelot->num_phys_ports; port++) {
1648 ocelot_port = ocelot->ports[port];
1649
1650 if (!ocelot_port)
1651 continue;
1652
1653 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1654 ocelot_port->bridge == bridge)
1655 mask |= BIT(port);
1656 }
1657
1658 return mask;
1659 }
1660 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1661
ocelot_apply_bridge_fwd_mask(struct ocelot * ocelot,bool joining)1662 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1663 {
1664 int port;
1665
1666 lockdep_assert_held(&ocelot->fwd_domain_lock);
1667
1668 /* If cut-through forwarding is supported, update the masks before a
1669 * port joins the forwarding domain, to avoid potential underruns if it
1670 * has the highest speed from the new domain.
1671 */
1672 if (joining && ocelot->ops->cut_through_fwd)
1673 ocelot->ops->cut_through_fwd(ocelot);
1674
1675 /* Apply FWD mask. The loop is needed to add/remove the current port as
1676 * a source for the other ports.
1677 */
1678 for (port = 0; port < ocelot->num_phys_ports; port++) {
1679 struct ocelot_port *ocelot_port = ocelot->ports[port];
1680 unsigned long mask;
1681
1682 if (!ocelot_port) {
1683 /* Unused ports can't send anywhere */
1684 mask = 0;
1685 } else if (ocelot_port->is_dsa_8021q_cpu) {
1686 /* The DSA tag_8021q CPU ports need to be able to
1687 * forward packets to all ports assigned to them.
1688 */
1689 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1690 ocelot_port);
1691 } else if (ocelot_port->bridge) {
1692 struct net_device *bond = ocelot_port->bond;
1693
1694 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1695 mask &= ~BIT(port);
1696
1697 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1698 port);
1699
1700 if (bond)
1701 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1702 } else {
1703 /* Standalone ports forward only to DSA tag_8021q CPU
1704 * ports (if those exist), or to the hardware CPU port
1705 * module otherwise.
1706 */
1707 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1708 port);
1709 }
1710
1711 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1712 }
1713
1714 /* If cut-through forwarding is supported and a port is leaving, there
1715 * is a chance that cut-through was disabled on the other ports due to
1716 * the port which is leaving (it has a higher link speed). We need to
1717 * update the cut-through masks of the remaining ports no earlier than
1718 * after the port has left, to prevent underruns from happening between
1719 * the cut-through update and the forwarding domain update.
1720 */
1721 if (!joining && ocelot->ops->cut_through_fwd)
1722 ocelot->ops->cut_through_fwd(ocelot);
1723 }
1724
1725 /* Update PGID_CPU which is the destination port mask used for whitelisting
1726 * unicast addresses filtered towards the host. In the normal and NPI modes,
1727 * this points to the analyzer entry for the CPU port module, while in DSA
1728 * tag_8021q mode, it is a bit mask of all active CPU ports.
1729 * PGID_SRC will take care of forwarding a packet from one user port to
1730 * no more than a single CPU port.
1731 */
ocelot_update_pgid_cpu(struct ocelot * ocelot)1732 static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1733 {
1734 int pgid_cpu = 0;
1735 int port;
1736
1737 for (port = 0; port < ocelot->num_phys_ports; port++) {
1738 struct ocelot_port *ocelot_port = ocelot->ports[port];
1739
1740 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1741 continue;
1742
1743 pgid_cpu |= BIT(port);
1744 }
1745
1746 if (!pgid_cpu)
1747 pgid_cpu = BIT(ocelot->num_phys_ports);
1748
1749 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1750 }
1751
ocelot_port_setup_dsa_8021q_cpu(struct ocelot * ocelot,int cpu)1752 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1753 {
1754 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1755 u16 vid;
1756
1757 mutex_lock(&ocelot->fwd_domain_lock);
1758
1759 cpu_port->is_dsa_8021q_cpu = true;
1760
1761 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1762 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1763
1764 ocelot_update_pgid_cpu(ocelot);
1765
1766 mutex_unlock(&ocelot->fwd_domain_lock);
1767 }
1768 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1769
ocelot_port_teardown_dsa_8021q_cpu(struct ocelot * ocelot,int cpu)1770 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1771 {
1772 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1773 u16 vid;
1774
1775 mutex_lock(&ocelot->fwd_domain_lock);
1776
1777 cpu_port->is_dsa_8021q_cpu = false;
1778
1779 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1780 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1781
1782 ocelot_update_pgid_cpu(ocelot);
1783
1784 mutex_unlock(&ocelot->fwd_domain_lock);
1785 }
1786 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1787
ocelot_port_assign_dsa_8021q_cpu(struct ocelot * ocelot,int port,int cpu)1788 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1789 int cpu)
1790 {
1791 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1792
1793 mutex_lock(&ocelot->fwd_domain_lock);
1794
1795 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1796 ocelot_apply_bridge_fwd_mask(ocelot, true);
1797
1798 mutex_unlock(&ocelot->fwd_domain_lock);
1799 }
1800 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1801
ocelot_port_unassign_dsa_8021q_cpu(struct ocelot * ocelot,int port)1802 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1803 {
1804 mutex_lock(&ocelot->fwd_domain_lock);
1805
1806 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1807 ocelot_apply_bridge_fwd_mask(ocelot, true);
1808
1809 mutex_unlock(&ocelot->fwd_domain_lock);
1810 }
1811 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1812
ocelot_bridge_stp_state_set(struct ocelot * ocelot,int port,u8 state)1813 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1814 {
1815 struct ocelot_port *ocelot_port = ocelot->ports[port];
1816 u32 learn_ena = 0;
1817
1818 mutex_lock(&ocelot->fwd_domain_lock);
1819
1820 ocelot_port->stp_state = state;
1821
1822 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1823 ocelot_port->learn_ena)
1824 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1825
1826 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1827 ANA_PORT_PORT_CFG, port);
1828
1829 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1830
1831 mutex_unlock(&ocelot->fwd_domain_lock);
1832 }
1833 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1834
ocelot_set_ageing_time(struct ocelot * ocelot,unsigned int msecs)1835 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1836 {
1837 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1838
1839 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1840 * which is clearly not what our intention is. So avoid that.
1841 */
1842 if (!age_period)
1843 age_period = 1;
1844
1845 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1846 }
1847 EXPORT_SYMBOL(ocelot_set_ageing_time);
1848
ocelot_multicast_get(struct ocelot * ocelot,const unsigned char * addr,u16 vid)1849 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1850 const unsigned char *addr,
1851 u16 vid)
1852 {
1853 struct ocelot_multicast *mc;
1854
1855 list_for_each_entry(mc, &ocelot->multicast, list) {
1856 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1857 return mc;
1858 }
1859
1860 return NULL;
1861 }
1862
ocelot_classify_mdb(const unsigned char * addr)1863 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1864 {
1865 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1866 return ENTRYTYPE_MACv4;
1867 if (addr[0] == 0x33 && addr[1] == 0x33)
1868 return ENTRYTYPE_MACv6;
1869 return ENTRYTYPE_LOCKED;
1870 }
1871
ocelot_pgid_alloc(struct ocelot * ocelot,int index,unsigned long ports)1872 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1873 unsigned long ports)
1874 {
1875 struct ocelot_pgid *pgid;
1876
1877 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1878 if (!pgid)
1879 return ERR_PTR(-ENOMEM);
1880
1881 pgid->ports = ports;
1882 pgid->index = index;
1883 refcount_set(&pgid->refcount, 1);
1884 list_add_tail(&pgid->list, &ocelot->pgids);
1885
1886 return pgid;
1887 }
1888
ocelot_pgid_free(struct ocelot * ocelot,struct ocelot_pgid * pgid)1889 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1890 {
1891 if (!refcount_dec_and_test(&pgid->refcount))
1892 return;
1893
1894 list_del(&pgid->list);
1895 kfree(pgid);
1896 }
1897
ocelot_mdb_get_pgid(struct ocelot * ocelot,const struct ocelot_multicast * mc)1898 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1899 const struct ocelot_multicast *mc)
1900 {
1901 struct ocelot_pgid *pgid;
1902 int index;
1903
1904 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1905 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1906 * destination mask table (PGID), the destination set is programmed as
1907 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1908 */
1909 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1910 mc->entry_type == ENTRYTYPE_MACv6)
1911 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1912
1913 list_for_each_entry(pgid, &ocelot->pgids, list) {
1914 /* When searching for a nonreserved multicast PGID, ignore the
1915 * dummy PGID of zero that we have for MACv4/MACv6 entries
1916 */
1917 if (pgid->index && pgid->ports == mc->ports) {
1918 refcount_inc(&pgid->refcount);
1919 return pgid;
1920 }
1921 }
1922
1923 /* Search for a free index in the nonreserved multicast PGID area */
1924 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1925 bool used = false;
1926
1927 list_for_each_entry(pgid, &ocelot->pgids, list) {
1928 if (pgid->index == index) {
1929 used = true;
1930 break;
1931 }
1932 }
1933
1934 if (!used)
1935 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1936 }
1937
1938 return ERR_PTR(-ENOSPC);
1939 }
1940
ocelot_encode_ports_to_mdb(unsigned char * addr,struct ocelot_multicast * mc)1941 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1942 struct ocelot_multicast *mc)
1943 {
1944 ether_addr_copy(addr, mc->addr);
1945
1946 if (mc->entry_type == ENTRYTYPE_MACv4) {
1947 addr[0] = 0;
1948 addr[1] = mc->ports >> 8;
1949 addr[2] = mc->ports & 0xff;
1950 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1951 addr[0] = mc->ports >> 8;
1952 addr[1] = mc->ports & 0xff;
1953 }
1954 }
1955
ocelot_port_mdb_add(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb,const struct net_device * bridge)1956 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1957 const struct switchdev_obj_port_mdb *mdb,
1958 const struct net_device *bridge)
1959 {
1960 unsigned char addr[ETH_ALEN];
1961 struct ocelot_multicast *mc;
1962 struct ocelot_pgid *pgid;
1963 u16 vid = mdb->vid;
1964
1965 if (!vid)
1966 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1967
1968 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1969 if (!mc) {
1970 /* New entry */
1971 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1972 if (!mc)
1973 return -ENOMEM;
1974
1975 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1976 ether_addr_copy(mc->addr, mdb->addr);
1977 mc->vid = vid;
1978
1979 list_add_tail(&mc->list, &ocelot->multicast);
1980 } else {
1981 /* Existing entry. Clean up the current port mask from
1982 * hardware now, because we'll be modifying it.
1983 */
1984 ocelot_pgid_free(ocelot, mc->pgid);
1985 ocelot_encode_ports_to_mdb(addr, mc);
1986 ocelot_mact_forget(ocelot, addr, vid);
1987 }
1988
1989 mc->ports |= BIT(port);
1990
1991 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1992 if (IS_ERR(pgid)) {
1993 dev_err(ocelot->dev,
1994 "Cannot allocate PGID for mdb %pM vid %d\n",
1995 mc->addr, mc->vid);
1996 devm_kfree(ocelot->dev, mc);
1997 return PTR_ERR(pgid);
1998 }
1999 mc->pgid = pgid;
2000
2001 ocelot_encode_ports_to_mdb(addr, mc);
2002
2003 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2004 mc->entry_type != ENTRYTYPE_MACv6)
2005 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2006 pgid->index);
2007
2008 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2009 mc->entry_type);
2010 }
2011 EXPORT_SYMBOL(ocelot_port_mdb_add);
2012
ocelot_port_mdb_del(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb,const struct net_device * bridge)2013 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2014 const struct switchdev_obj_port_mdb *mdb,
2015 const struct net_device *bridge)
2016 {
2017 unsigned char addr[ETH_ALEN];
2018 struct ocelot_multicast *mc;
2019 struct ocelot_pgid *pgid;
2020 u16 vid = mdb->vid;
2021
2022 if (!vid)
2023 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2024
2025 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2026 if (!mc)
2027 return -ENOENT;
2028
2029 ocelot_encode_ports_to_mdb(addr, mc);
2030 ocelot_mact_forget(ocelot, addr, vid);
2031
2032 ocelot_pgid_free(ocelot, mc->pgid);
2033 mc->ports &= ~BIT(port);
2034 if (!mc->ports) {
2035 list_del(&mc->list);
2036 devm_kfree(ocelot->dev, mc);
2037 return 0;
2038 }
2039
2040 /* We have a PGID with fewer ports now */
2041 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2042 if (IS_ERR(pgid))
2043 return PTR_ERR(pgid);
2044 mc->pgid = pgid;
2045
2046 ocelot_encode_ports_to_mdb(addr, mc);
2047
2048 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2049 mc->entry_type != ENTRYTYPE_MACv6)
2050 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2051 pgid->index);
2052
2053 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2054 mc->entry_type);
2055 }
2056 EXPORT_SYMBOL(ocelot_port_mdb_del);
2057
ocelot_port_bridge_join(struct ocelot * ocelot,int port,struct net_device * bridge,int bridge_num,struct netlink_ext_ack * extack)2058 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2059 struct net_device *bridge, int bridge_num,
2060 struct netlink_ext_ack *extack)
2061 {
2062 struct ocelot_port *ocelot_port = ocelot->ports[port];
2063 int err;
2064
2065 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
2066 if (err)
2067 return err;
2068
2069 mutex_lock(&ocelot->fwd_domain_lock);
2070
2071 ocelot_port->bridge = bridge;
2072 ocelot_port->bridge_num = bridge_num;
2073
2074 ocelot_apply_bridge_fwd_mask(ocelot, true);
2075
2076 mutex_unlock(&ocelot->fwd_domain_lock);
2077
2078 if (br_vlan_enabled(bridge))
2079 return 0;
2080
2081 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2082 }
2083 EXPORT_SYMBOL(ocelot_port_bridge_join);
2084
ocelot_port_bridge_leave(struct ocelot * ocelot,int port,struct net_device * bridge)2085 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2086 struct net_device *bridge)
2087 {
2088 struct ocelot_port *ocelot_port = ocelot->ports[port];
2089
2090 mutex_lock(&ocelot->fwd_domain_lock);
2091
2092 if (!br_vlan_enabled(bridge))
2093 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2094
2095 ocelot_port->bridge = NULL;
2096 ocelot_port->bridge_num = -1;
2097
2098 ocelot_port_set_pvid(ocelot, port, NULL);
2099 ocelot_port_manage_port_tag(ocelot, port);
2100 ocelot_apply_bridge_fwd_mask(ocelot, false);
2101
2102 mutex_unlock(&ocelot->fwd_domain_lock);
2103 }
2104 EXPORT_SYMBOL(ocelot_port_bridge_leave);
2105
ocelot_set_aggr_pgids(struct ocelot * ocelot)2106 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2107 {
2108 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2109 int i, port, lag;
2110
2111 /* Reset destination and aggregation PGIDS */
2112 for_each_unicast_dest_pgid(ocelot, port)
2113 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2114
2115 for_each_aggr_pgid(ocelot, i)
2116 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2117 ANA_PGID_PGID, i);
2118
2119 /* The visited ports bitmask holds the list of ports offloading any
2120 * bonding interface. Initially we mark all these ports as unvisited,
2121 * then every time we visit a port in this bitmask, we know that it is
2122 * the lowest numbered port, i.e. the one whose logical ID == physical
2123 * port ID == LAG ID. So we mark as visited all further ports in the
2124 * bitmask that are offloading the same bonding interface. This way,
2125 * we set up the aggregation PGIDs only once per bonding interface.
2126 */
2127 for (port = 0; port < ocelot->num_phys_ports; port++) {
2128 struct ocelot_port *ocelot_port = ocelot->ports[port];
2129
2130 if (!ocelot_port || !ocelot_port->bond)
2131 continue;
2132
2133 visited &= ~BIT(port);
2134 }
2135
2136 /* Now, set PGIDs for each active LAG */
2137 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2138 struct net_device *bond = ocelot->ports[lag]->bond;
2139 int num_active_ports = 0;
2140 unsigned long bond_mask;
2141 u8 aggr_idx[16];
2142
2143 if (!bond || (visited & BIT(lag)))
2144 continue;
2145
2146 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2147
2148 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2149 struct ocelot_port *ocelot_port = ocelot->ports[port];
2150
2151 // Destination mask
2152 ocelot_write_rix(ocelot, bond_mask,
2153 ANA_PGID_PGID, port);
2154
2155 if (ocelot_port->lag_tx_active)
2156 aggr_idx[num_active_ports++] = port;
2157 }
2158
2159 for_each_aggr_pgid(ocelot, i) {
2160 u32 ac;
2161
2162 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2163 ac &= ~bond_mask;
2164 /* Don't do division by zero if there was no active
2165 * port. Just make all aggregation codes zero.
2166 */
2167 if (num_active_ports)
2168 ac |= BIT(aggr_idx[i % num_active_ports]);
2169 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2170 }
2171
2172 /* Mark all ports in the same LAG as visited to avoid applying
2173 * the same config again.
2174 */
2175 for (port = lag; port < ocelot->num_phys_ports; port++) {
2176 struct ocelot_port *ocelot_port = ocelot->ports[port];
2177
2178 if (!ocelot_port)
2179 continue;
2180
2181 if (ocelot_port->bond == bond)
2182 visited |= BIT(port);
2183 }
2184 }
2185 }
2186
2187 /* When offloading a bonding interface, the switch ports configured under the
2188 * same bond must have the same logical port ID, equal to the physical port ID
2189 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2190 * bridged mode, each port has a logical port ID equal to its physical port ID.
2191 */
ocelot_setup_logical_port_ids(struct ocelot * ocelot)2192 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2193 {
2194 int port;
2195
2196 for (port = 0; port < ocelot->num_phys_ports; port++) {
2197 struct ocelot_port *ocelot_port = ocelot->ports[port];
2198 struct net_device *bond;
2199
2200 if (!ocelot_port)
2201 continue;
2202
2203 bond = ocelot_port->bond;
2204 if (bond) {
2205 int lag = ocelot_bond_get_id(ocelot, bond);
2206
2207 ocelot_rmw_gix(ocelot,
2208 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2209 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2210 ANA_PORT_PORT_CFG, port);
2211 } else {
2212 ocelot_rmw_gix(ocelot,
2213 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2214 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2215 ANA_PORT_PORT_CFG, port);
2216 }
2217 }
2218 }
2219
ocelot_migrate_mc(struct ocelot * ocelot,struct ocelot_multicast * mc,unsigned long from_mask,unsigned long to_mask)2220 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2221 unsigned long from_mask, unsigned long to_mask)
2222 {
2223 unsigned char addr[ETH_ALEN];
2224 struct ocelot_pgid *pgid;
2225 u16 vid = mc->vid;
2226
2227 dev_dbg(ocelot->dev,
2228 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2229 mc->addr, mc->vid, from_mask, to_mask);
2230
2231 /* First clean up the current port mask from hardware, because
2232 * we'll be modifying it.
2233 */
2234 ocelot_pgid_free(ocelot, mc->pgid);
2235 ocelot_encode_ports_to_mdb(addr, mc);
2236 ocelot_mact_forget(ocelot, addr, vid);
2237
2238 mc->ports &= ~from_mask;
2239 mc->ports |= to_mask;
2240
2241 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2242 if (IS_ERR(pgid)) {
2243 dev_err(ocelot->dev,
2244 "Cannot allocate PGID for mdb %pM vid %d\n",
2245 mc->addr, mc->vid);
2246 devm_kfree(ocelot->dev, mc);
2247 return PTR_ERR(pgid);
2248 }
2249 mc->pgid = pgid;
2250
2251 ocelot_encode_ports_to_mdb(addr, mc);
2252
2253 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2254 mc->entry_type != ENTRYTYPE_MACv6)
2255 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2256 pgid->index);
2257
2258 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2259 mc->entry_type);
2260 }
2261
ocelot_migrate_mdbs(struct ocelot * ocelot,unsigned long from_mask,unsigned long to_mask)2262 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2263 unsigned long to_mask)
2264 {
2265 struct ocelot_multicast *mc;
2266 int err;
2267
2268 list_for_each_entry(mc, &ocelot->multicast, list) {
2269 if (!(mc->ports & from_mask))
2270 continue;
2271
2272 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2273 if (err)
2274 return err;
2275 }
2276
2277 return 0;
2278 }
2279 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2280
2281 /* Documentation for PORTID_VAL says:
2282 * Logical port number for front port. If port is not a member of a LLAG,
2283 * then PORTID must be set to the physical port number.
2284 * If port is a member of a LLAG, then PORTID must be set to the common
2285 * PORTID_VAL used for all member ports of the LLAG.
2286 * The value must not exceed the number of physical ports on the device.
2287 *
2288 * This means we have little choice but to migrate FDB entries pointing towards
2289 * a logical port when that changes.
2290 */
ocelot_migrate_lag_fdbs(struct ocelot * ocelot,struct net_device * bond,int lag)2291 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2292 struct net_device *bond,
2293 int lag)
2294 {
2295 struct ocelot_lag_fdb *fdb;
2296 int err;
2297
2298 lockdep_assert_held(&ocelot->fwd_domain_lock);
2299
2300 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2301 if (fdb->bond != bond)
2302 continue;
2303
2304 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2305 if (err) {
2306 dev_err(ocelot->dev,
2307 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2308 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2309 }
2310
2311 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2312 ENTRYTYPE_LOCKED);
2313 if (err) {
2314 dev_err(ocelot->dev,
2315 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2316 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2317 }
2318 }
2319 }
2320
ocelot_port_lag_join(struct ocelot * ocelot,int port,struct net_device * bond,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)2321 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2322 struct net_device *bond,
2323 struct netdev_lag_upper_info *info,
2324 struct netlink_ext_ack *extack)
2325 {
2326 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2327 NL_SET_ERR_MSG_MOD(extack,
2328 "Can only offload LAG using hash TX type");
2329 return -EOPNOTSUPP;
2330 }
2331
2332 mutex_lock(&ocelot->fwd_domain_lock);
2333
2334 ocelot->ports[port]->bond = bond;
2335
2336 ocelot_setup_logical_port_ids(ocelot);
2337 ocelot_apply_bridge_fwd_mask(ocelot, true);
2338 ocelot_set_aggr_pgids(ocelot);
2339
2340 mutex_unlock(&ocelot->fwd_domain_lock);
2341
2342 return 0;
2343 }
2344 EXPORT_SYMBOL(ocelot_port_lag_join);
2345
ocelot_port_lag_leave(struct ocelot * ocelot,int port,struct net_device * bond)2346 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2347 struct net_device *bond)
2348 {
2349 int old_lag_id, new_lag_id;
2350
2351 mutex_lock(&ocelot->fwd_domain_lock);
2352
2353 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2354
2355 ocelot->ports[port]->bond = NULL;
2356
2357 ocelot_setup_logical_port_ids(ocelot);
2358 ocelot_apply_bridge_fwd_mask(ocelot, false);
2359 ocelot_set_aggr_pgids(ocelot);
2360
2361 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2362
2363 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2364 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2365
2366 mutex_unlock(&ocelot->fwd_domain_lock);
2367 }
2368 EXPORT_SYMBOL(ocelot_port_lag_leave);
2369
ocelot_port_lag_change(struct ocelot * ocelot,int port,bool lag_tx_active)2370 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2371 {
2372 struct ocelot_port *ocelot_port = ocelot->ports[port];
2373
2374 mutex_lock(&ocelot->fwd_domain_lock);
2375
2376 ocelot_port->lag_tx_active = lag_tx_active;
2377
2378 /* Rebalance the LAGs */
2379 ocelot_set_aggr_pgids(ocelot);
2380
2381 mutex_unlock(&ocelot->fwd_domain_lock);
2382 }
2383 EXPORT_SYMBOL(ocelot_port_lag_change);
2384
ocelot_lag_fdb_add(struct ocelot * ocelot,struct net_device * bond,const unsigned char * addr,u16 vid,const struct net_device * bridge)2385 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2386 const unsigned char *addr, u16 vid,
2387 const struct net_device *bridge)
2388 {
2389 struct ocelot_lag_fdb *fdb;
2390 int lag, err;
2391
2392 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2393 if (!fdb)
2394 return -ENOMEM;
2395
2396 mutex_lock(&ocelot->fwd_domain_lock);
2397
2398 if (!vid)
2399 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2400
2401 ether_addr_copy(fdb->addr, addr);
2402 fdb->vid = vid;
2403 fdb->bond = bond;
2404
2405 lag = ocelot_bond_get_id(ocelot, bond);
2406
2407 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2408 if (err) {
2409 mutex_unlock(&ocelot->fwd_domain_lock);
2410 kfree(fdb);
2411 return err;
2412 }
2413
2414 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2415 mutex_unlock(&ocelot->fwd_domain_lock);
2416
2417 return 0;
2418 }
2419 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2420
ocelot_lag_fdb_del(struct ocelot * ocelot,struct net_device * bond,const unsigned char * addr,u16 vid,const struct net_device * bridge)2421 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2422 const unsigned char *addr, u16 vid,
2423 const struct net_device *bridge)
2424 {
2425 struct ocelot_lag_fdb *fdb, *tmp;
2426
2427 mutex_lock(&ocelot->fwd_domain_lock);
2428
2429 if (!vid)
2430 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2431
2432 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2433 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2434 fdb->bond != bond)
2435 continue;
2436
2437 ocelot_mact_forget(ocelot, addr, vid);
2438 list_del(&fdb->list);
2439 mutex_unlock(&ocelot->fwd_domain_lock);
2440 kfree(fdb);
2441
2442 return 0;
2443 }
2444
2445 mutex_unlock(&ocelot->fwd_domain_lock);
2446
2447 return -ENOENT;
2448 }
2449 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2450
2451 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2452 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2453 * In the special case that it's the NPI port that we're configuring, the
2454 * length of the tag and optional prefix needs to be accounted for privately,
2455 * in order to be able to sustain communication at the requested @sdu.
2456 */
ocelot_port_set_maxlen(struct ocelot * ocelot,int port,size_t sdu)2457 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2458 {
2459 struct ocelot_port *ocelot_port = ocelot->ports[port];
2460 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2461 int pause_start, pause_stop;
2462 int atop, atop_tot;
2463
2464 if (port == ocelot->npi) {
2465 maxlen += OCELOT_TAG_LEN;
2466
2467 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2468 maxlen += OCELOT_SHORT_PREFIX_LEN;
2469 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2470 maxlen += OCELOT_LONG_PREFIX_LEN;
2471 }
2472
2473 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2474
2475 /* Set Pause watermark hysteresis */
2476 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2477 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2478 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2479 pause_start);
2480 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2481 pause_stop);
2482
2483 /* Tail dropping watermarks */
2484 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2485 OCELOT_BUFFER_CELL_SZ;
2486 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2487 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2488 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2489 }
2490 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2491
ocelot_get_max_mtu(struct ocelot * ocelot,int port)2492 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2493 {
2494 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2495
2496 if (port == ocelot->npi) {
2497 max_mtu -= OCELOT_TAG_LEN;
2498
2499 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2500 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2501 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2502 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2503 }
2504
2505 return max_mtu;
2506 }
2507 EXPORT_SYMBOL(ocelot_get_max_mtu);
2508
ocelot_port_set_learning(struct ocelot * ocelot,int port,bool enabled)2509 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2510 bool enabled)
2511 {
2512 struct ocelot_port *ocelot_port = ocelot->ports[port];
2513 u32 val = 0;
2514
2515 if (enabled)
2516 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2517
2518 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2519 ANA_PORT_PORT_CFG, port);
2520
2521 ocelot_port->learn_ena = enabled;
2522 }
2523
ocelot_port_set_ucast_flood(struct ocelot * ocelot,int port,bool enabled)2524 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2525 bool enabled)
2526 {
2527 u32 val = 0;
2528
2529 if (enabled)
2530 val = BIT(port);
2531
2532 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2533 }
2534
ocelot_port_set_mcast_flood(struct ocelot * ocelot,int port,bool enabled)2535 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2536 bool enabled)
2537 {
2538 u32 val = 0;
2539
2540 if (enabled)
2541 val = BIT(port);
2542
2543 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2544 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2545 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2546 }
2547
ocelot_port_set_bcast_flood(struct ocelot * ocelot,int port,bool enabled)2548 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2549 bool enabled)
2550 {
2551 u32 val = 0;
2552
2553 if (enabled)
2554 val = BIT(port);
2555
2556 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2557 }
2558
ocelot_port_pre_bridge_flags(struct ocelot * ocelot,int port,struct switchdev_brport_flags flags)2559 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2560 struct switchdev_brport_flags flags)
2561 {
2562 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2563 BR_BCAST_FLOOD))
2564 return -EINVAL;
2565
2566 return 0;
2567 }
2568 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2569
ocelot_port_bridge_flags(struct ocelot * ocelot,int port,struct switchdev_brport_flags flags)2570 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2571 struct switchdev_brport_flags flags)
2572 {
2573 if (flags.mask & BR_LEARNING)
2574 ocelot_port_set_learning(ocelot, port,
2575 !!(flags.val & BR_LEARNING));
2576
2577 if (flags.mask & BR_FLOOD)
2578 ocelot_port_set_ucast_flood(ocelot, port,
2579 !!(flags.val & BR_FLOOD));
2580
2581 if (flags.mask & BR_MCAST_FLOOD)
2582 ocelot_port_set_mcast_flood(ocelot, port,
2583 !!(flags.val & BR_MCAST_FLOOD));
2584
2585 if (flags.mask & BR_BCAST_FLOOD)
2586 ocelot_port_set_bcast_flood(ocelot, port,
2587 !!(flags.val & BR_BCAST_FLOOD));
2588 }
2589 EXPORT_SYMBOL(ocelot_port_bridge_flags);
2590
ocelot_port_get_default_prio(struct ocelot * ocelot,int port)2591 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2592 {
2593 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2594
2595 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2596 }
2597 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2598
ocelot_port_set_default_prio(struct ocelot * ocelot,int port,u8 prio)2599 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2600 {
2601 if (prio >= OCELOT_NUM_TC)
2602 return -ERANGE;
2603
2604 ocelot_rmw_gix(ocelot,
2605 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2606 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2607 ANA_PORT_QOS_CFG,
2608 port);
2609
2610 return 0;
2611 }
2612 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2613
ocelot_port_get_dscp_prio(struct ocelot * ocelot,int port,u8 dscp)2614 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2615 {
2616 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2617 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2618
2619 /* Return error if DSCP prioritization isn't enabled */
2620 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2621 return -EOPNOTSUPP;
2622
2623 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2624 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2625 /* Re-read ANA_DSCP_CFG for the translated DSCP */
2626 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2627 }
2628
2629 /* If the DSCP value is not trusted, the QoS classification falls back
2630 * to VLAN PCP or port-based default.
2631 */
2632 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2633 return -EOPNOTSUPP;
2634
2635 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2636 }
2637 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2638
ocelot_port_add_dscp_prio(struct ocelot * ocelot,int port,u8 dscp,u8 prio)2639 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2640 {
2641 int mask, val;
2642
2643 if (prio >= OCELOT_NUM_TC)
2644 return -ERANGE;
2645
2646 /* There is at least one app table priority (this one), so we need to
2647 * make sure DSCP prioritization is enabled on the port.
2648 * Also make sure DSCP translation is disabled
2649 * (dcbnl doesn't support it).
2650 */
2651 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2652 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2653
2654 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2655 ANA_PORT_QOS_CFG, port);
2656
2657 /* Trust this DSCP value and map it to the given QoS class */
2658 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2659
2660 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2661
2662 return 0;
2663 }
2664 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2665
ocelot_port_del_dscp_prio(struct ocelot * ocelot,int port,u8 dscp,u8 prio)2666 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2667 {
2668 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2669 int mask, i;
2670
2671 /* During a "dcb app replace" command, the new app table entry will be
2672 * added first, then the old one will be deleted. But the hardware only
2673 * supports one QoS class per DSCP value (duh), so if we blindly delete
2674 * the app table entry for this DSCP value, we end up deleting the
2675 * entry with the new priority. Avoid that by checking whether user
2676 * space wants to delete the priority which is currently configured, or
2677 * something else which is no longer current.
2678 */
2679 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2680 return 0;
2681
2682 /* Untrust this DSCP value */
2683 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2684
2685 for (i = 0; i < 64; i++) {
2686 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2687
2688 /* There are still app table entries on the port, so we need to
2689 * keep DSCP enabled, nothing to do.
2690 */
2691 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2692 return 0;
2693 }
2694
2695 /* Disable DSCP QoS classification if there isn't any trusted
2696 * DSCP value left.
2697 */
2698 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2699 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2700
2701 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2702
2703 return 0;
2704 }
2705 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2706
ocelot_mirror_get(struct ocelot * ocelot,int to,struct netlink_ext_ack * extack)2707 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2708 struct netlink_ext_ack *extack)
2709 {
2710 struct ocelot_mirror *m = ocelot->mirror;
2711
2712 if (m) {
2713 if (m->to != to) {
2714 NL_SET_ERR_MSG_MOD(extack,
2715 "Mirroring already configured towards different egress port");
2716 return ERR_PTR(-EBUSY);
2717 }
2718
2719 refcount_inc(&m->refcount);
2720 return m;
2721 }
2722
2723 m = kzalloc(sizeof(*m), GFP_KERNEL);
2724 if (!m)
2725 return ERR_PTR(-ENOMEM);
2726
2727 m->to = to;
2728 refcount_set(&m->refcount, 1);
2729 ocelot->mirror = m;
2730
2731 /* Program the mirror port to hardware */
2732 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2733
2734 return m;
2735 }
2736
ocelot_mirror_put(struct ocelot * ocelot)2737 void ocelot_mirror_put(struct ocelot *ocelot)
2738 {
2739 struct ocelot_mirror *m = ocelot->mirror;
2740
2741 if (!refcount_dec_and_test(&m->refcount))
2742 return;
2743
2744 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2745 ocelot->mirror = NULL;
2746 kfree(m);
2747 }
2748
ocelot_port_mirror_add(struct ocelot * ocelot,int from,int to,bool ingress,struct netlink_ext_ack * extack)2749 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2750 bool ingress, struct netlink_ext_ack *extack)
2751 {
2752 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2753
2754 if (IS_ERR(m))
2755 return PTR_ERR(m);
2756
2757 if (ingress) {
2758 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2759 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2760 ANA_PORT_PORT_CFG, from);
2761 } else {
2762 ocelot_rmw(ocelot, BIT(from), BIT(from),
2763 ANA_EMIRRORPORTS);
2764 }
2765
2766 return 0;
2767 }
2768 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2769
ocelot_port_mirror_del(struct ocelot * ocelot,int from,bool ingress)2770 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2771 {
2772 if (ingress) {
2773 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2774 ANA_PORT_PORT_CFG, from);
2775 } else {
2776 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2777 }
2778
2779 ocelot_mirror_put(ocelot);
2780 }
2781 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2782
ocelot_port_reset_mqprio(struct ocelot * ocelot,int port)2783 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port)
2784 {
2785 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2786
2787 netdev_reset_tc(dev);
2788 ocelot_port_change_fp(ocelot, port, 0);
2789 }
2790
ocelot_port_mqprio(struct ocelot * ocelot,int port,struct tc_mqprio_qopt_offload * mqprio)2791 int ocelot_port_mqprio(struct ocelot *ocelot, int port,
2792 struct tc_mqprio_qopt_offload *mqprio)
2793 {
2794 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2795 struct netlink_ext_ack *extack = mqprio->extack;
2796 struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2797 int num_tc = qopt->num_tc;
2798 int tc, err;
2799
2800 if (!num_tc) {
2801 ocelot_port_reset_mqprio(ocelot, port);
2802 return 0;
2803 }
2804
2805 err = netdev_set_num_tc(dev, num_tc);
2806 if (err)
2807 return err;
2808
2809 for (tc = 0; tc < num_tc; tc++) {
2810 if (qopt->count[tc] != 1) {
2811 NL_SET_ERR_MSG_MOD(extack,
2812 "Only one TXQ per TC supported");
2813 return -EINVAL;
2814 }
2815
2816 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]);
2817 if (err)
2818 goto err_reset_tc;
2819 }
2820
2821 err = netif_set_real_num_tx_queues(dev, num_tc);
2822 if (err)
2823 goto err_reset_tc;
2824
2825 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs);
2826
2827 return 0;
2828
2829 err_reset_tc:
2830 ocelot_port_reset_mqprio(ocelot, port);
2831 return err;
2832 }
2833 EXPORT_SYMBOL_GPL(ocelot_port_mqprio);
2834
ocelot_init_port(struct ocelot * ocelot,int port)2835 void ocelot_init_port(struct ocelot *ocelot, int port)
2836 {
2837 struct ocelot_port *ocelot_port = ocelot->ports[port];
2838
2839 skb_queue_head_init(&ocelot_port->tx_skbs);
2840
2841 /* Basic L2 initialization */
2842
2843 /* Set MAC IFG Gaps
2844 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2845 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2846 */
2847 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2848 DEV_MAC_IFG_CFG);
2849
2850 /* Load seed (0) and set MAC HDX late collision */
2851 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2852 DEV_MAC_HDX_CFG_SEED_LOAD,
2853 DEV_MAC_HDX_CFG);
2854 mdelay(1);
2855 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2856 DEV_MAC_HDX_CFG);
2857
2858 /* Set Max Length and maximum tags allowed */
2859 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2860 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2861 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2862 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2863 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2864 DEV_MAC_TAGS_CFG);
2865
2866 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2867 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2868 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2869
2870 /* Enable transmission of pause frames */
2871 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2872
2873 /* Drop frames with multicast source address */
2874 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2875 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2876 ANA_PORT_DROP_CFG, port);
2877
2878 /* Set default VLAN and tag type to 8021Q. */
2879 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2880 REW_PORT_VLAN_CFG_PORT_TPID_M,
2881 REW_PORT_VLAN_CFG, port);
2882
2883 /* Disable source address learning for standalone mode */
2884 ocelot_port_set_learning(ocelot, port, false);
2885
2886 /* Set the port's initial logical port ID value, enable receiving
2887 * frames on it, and configure the MAC address learning type to
2888 * automatic.
2889 */
2890 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2891 ANA_PORT_PORT_CFG_RECV_ENA |
2892 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2893 ANA_PORT_PORT_CFG, port);
2894
2895 /* Enable vcap lookups */
2896 ocelot_vcap_enable(ocelot, port);
2897 }
2898 EXPORT_SYMBOL(ocelot_init_port);
2899
2900 /* Configure and enable the CPU port module, which is a set of queues
2901 * accessible through register MMIO, frame DMA or Ethernet (in case
2902 * NPI mode is used).
2903 */
ocelot_cpu_port_init(struct ocelot * ocelot)2904 static void ocelot_cpu_port_init(struct ocelot *ocelot)
2905 {
2906 int cpu = ocelot->num_phys_ports;
2907
2908 /* The unicast destination PGID for the CPU port module is unused */
2909 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2910 /* Instead set up a multicast destination PGID for traffic copied to
2911 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2912 * addresses will be copied to the CPU via this PGID.
2913 */
2914 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2915 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2916 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2917 ANA_PORT_PORT_CFG, cpu);
2918
2919 /* Enable CPU port module */
2920 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2921 /* CPU port Injection/Extraction configuration */
2922 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2923 OCELOT_TAG_PREFIX_NONE);
2924 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2925 OCELOT_TAG_PREFIX_NONE);
2926
2927 /* Configure the CPU port to be VLAN aware */
2928 ocelot_write_gix(ocelot,
2929 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
2930 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2931 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2932 ANA_PORT_VLAN_CFG, cpu);
2933 }
2934
ocelot_detect_features(struct ocelot * ocelot)2935 static void ocelot_detect_features(struct ocelot *ocelot)
2936 {
2937 int mmgt, eq_ctrl;
2938
2939 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2940 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2941 * 192 bytes as the documentation incorrectly says.
2942 */
2943 mmgt = ocelot_read(ocelot, SYS_MMGT);
2944 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2945
2946 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2947 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2948 }
2949
ocelot_mem_init_status(struct ocelot * ocelot)2950 static int ocelot_mem_init_status(struct ocelot *ocelot)
2951 {
2952 unsigned int val;
2953 int err;
2954
2955 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
2956 &val);
2957
2958 return err ?: val;
2959 }
2960
ocelot_reset(struct ocelot * ocelot)2961 int ocelot_reset(struct ocelot *ocelot)
2962 {
2963 int err;
2964 u32 val;
2965
2966 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
2967 if (err)
2968 return err;
2969
2970 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
2971 if (err)
2972 return err;
2973
2974 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
2975 * 100us) before enabling the switch core.
2976 */
2977 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
2978 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
2979 if (err)
2980 return err;
2981
2982 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
2983 if (err)
2984 return err;
2985
2986 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
2987 }
2988 EXPORT_SYMBOL(ocelot_reset);
2989
ocelot_init(struct ocelot * ocelot)2990 int ocelot_init(struct ocelot *ocelot)
2991 {
2992 int i, ret;
2993 u32 port;
2994
2995 if (ocelot->ops->reset) {
2996 ret = ocelot->ops->reset(ocelot);
2997 if (ret) {
2998 dev_err(ocelot->dev, "Switch reset failed\n");
2999 return ret;
3000 }
3001 }
3002
3003 mutex_init(&ocelot->mact_lock);
3004 mutex_init(&ocelot->fwd_domain_lock);
3005 spin_lock_init(&ocelot->ptp_clock_lock);
3006 spin_lock_init(&ocelot->ts_id_lock);
3007 spin_lock_init(&ocelot->inj_lock);
3008 spin_lock_init(&ocelot->xtr_lock);
3009
3010 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
3011 if (!ocelot->owq)
3012 return -ENOMEM;
3013
3014 ret = ocelot_stats_init(ocelot);
3015 if (ret)
3016 goto err_stats_init;
3017
3018 INIT_LIST_HEAD(&ocelot->multicast);
3019 INIT_LIST_HEAD(&ocelot->pgids);
3020 INIT_LIST_HEAD(&ocelot->vlans);
3021 INIT_LIST_HEAD(&ocelot->lag_fdbs);
3022 ocelot_detect_features(ocelot);
3023 ocelot_mact_init(ocelot);
3024 ocelot_vlan_init(ocelot);
3025 ocelot_vcap_init(ocelot);
3026 ocelot_cpu_port_init(ocelot);
3027
3028 if (ocelot->ops->psfp_init)
3029 ocelot->ops->psfp_init(ocelot);
3030
3031 if (ocelot->mm_supported) {
3032 ret = ocelot_mm_init(ocelot);
3033 if (ret)
3034 goto err_mm_init;
3035 }
3036
3037 for (port = 0; port < ocelot->num_phys_ports; port++) {
3038 /* Clear all counters (5 groups) */
3039 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
3040 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
3041 SYS_STAT_CFG);
3042 }
3043
3044 /* Only use S-Tag */
3045 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
3046
3047 /* Aggregation mode */
3048 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
3049 ANA_AGGR_CFG_AC_DMAC_ENA |
3050 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
3051 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
3052 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
3053 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
3054 ANA_AGGR_CFG);
3055
3056 /* Set MAC age time to default value. The entry is aged after
3057 * 2*AGE_PERIOD
3058 */
3059 ocelot_write(ocelot,
3060 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
3061 ANA_AUTOAGE);
3062
3063 /* Disable learning for frames discarded by VLAN ingress filtering */
3064 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
3065
3066 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
3067 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
3068 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
3069
3070 /* Setup flooding PGIDs */
3071 for (i = 0; i < ocelot->num_flooding_pgids; i++)
3072 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
3073 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
3074 ANA_FLOODING_FLD_UNICAST(PGID_UC),
3075 ANA_FLOODING, i);
3076 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3077 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
3078 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
3079 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
3080 ANA_FLOODING_IPMC);
3081
3082 for (port = 0; port < ocelot->num_phys_ports; port++) {
3083 /* Transmit the frame to the local port. */
3084 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3085 /* Do not forward BPDU frames to the front ports. */
3086 ocelot_write_gix(ocelot,
3087 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
3088 ANA_PORT_CPU_FWD_BPDU_CFG,
3089 port);
3090 /* Ensure bridging is disabled */
3091 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3092 }
3093
3094 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3095 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3096
3097 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3098 }
3099
3100 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3101
3102 /* Allow broadcast and unknown L2 multicast to the CPU. */
3103 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3104 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3105 ANA_PGID_PGID, PGID_MC);
3106 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3107 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3108 ANA_PGID_PGID, PGID_BC);
3109 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3110 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3111
3112 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
3113 * registers endianness.
3114 */
3115 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3116 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
3117 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3118 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
3119 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3120 ANA_CPUQ_CFG_CPUQ_LRN(2) |
3121 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
3122 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
3123 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
3124 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
3125 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
3126 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
3127 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
3128 for (i = 0; i < 16; i++)
3129 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3130 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
3131 ANA_CPUQ_8021_CFG, i);
3132
3133 return 0;
3134
3135 err_mm_init:
3136 ocelot_stats_deinit(ocelot);
3137 err_stats_init:
3138 destroy_workqueue(ocelot->owq);
3139 return ret;
3140 }
3141 EXPORT_SYMBOL(ocelot_init);
3142
ocelot_deinit(struct ocelot * ocelot)3143 void ocelot_deinit(struct ocelot *ocelot)
3144 {
3145 ocelot_stats_deinit(ocelot);
3146 destroy_workqueue(ocelot->owq);
3147 }
3148 EXPORT_SYMBOL(ocelot_deinit);
3149
ocelot_deinit_port(struct ocelot * ocelot,int port)3150 void ocelot_deinit_port(struct ocelot *ocelot, int port)
3151 {
3152 struct ocelot_port *ocelot_port = ocelot->ports[port];
3153
3154 skb_queue_purge(&ocelot_port->tx_skbs);
3155 }
3156 EXPORT_SYMBOL(ocelot_deinit_port);
3157
3158 MODULE_LICENSE("Dual MIT/GPL");
3159