1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2018-2020 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 10 lsio_subsys: bus@5d000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, 15 <0x08000000 0x0 0x08000000 0x10000000>; 16 17 lsio_mem_clk: clock-lsio-mem { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <200000000>; 21 clock-output-names = "lsio_mem_clk"; 22 }; 23 24 lsio_bus_clk: clock-lsio-bus { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 clock-output-names = "lsio_bus_clk"; 29 }; 30 31 lsio_pwm0: pwm@5d000000 { 32 compatible = "fsl,imx27-pwm"; 33 reg = <0x5d000000 0x10000>; 34 clock-names = "ipg", "per"; 35 clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>, 36 <&pwm0_lpcg IMX_LPCG_CLK_1>; 37 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 38 assigned-clock-rates = <24000000>; 39 #pwm-cells = <3>; 40 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 41 status = "disabled"; 42 }; 43 44 lsio_pwm1: pwm@5d010000 { 45 compatible = "fsl,imx27-pwm"; 46 reg = <0x5d010000 0x10000>; 47 clock-names = "ipg", "per"; 48 clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, 49 <&pwm1_lpcg IMX_LPCG_CLK_1>; 50 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 51 assigned-clock-rates = <24000000>; 52 #pwm-cells = <3>; 53 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 54 status = "disabled"; 55 }; 56 57 lsio_pwm2: pwm@5d020000 { 58 compatible = "fsl,imx27-pwm"; 59 reg = <0x5d020000 0x10000>; 60 clock-names = "ipg", "per"; 61 clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>, 62 <&pwm2_lpcg IMX_LPCG_CLK_1>; 63 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 64 assigned-clock-rates = <24000000>; 65 #pwm-cells = <3>; 66 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 67 status = "disabled"; 68 }; 69 70 lsio_pwm3: pwm@5d030000 { 71 compatible = "fsl,imx27-pwm"; 72 reg = <0x5d030000 0x10000>; 73 clock-names = "ipg", "per"; 74 clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>, 75 <&pwm3_lpcg IMX_LPCG_CLK_1>; 76 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 77 assigned-clock-rates = <24000000>; 78 #pwm-cells = <3>; 79 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 80 status = "disabled"; 81 }; 82 83 lsio_gpio0: gpio@5d080000 { 84 reg = <0x5d080000 0x10000>; 85 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 86 gpio-controller; 87 #gpio-cells = <2>; 88 interrupt-controller; 89 #interrupt-cells = <2>; 90 power-domains = <&pd IMX_SC_R_GPIO_0>; 91 }; 92 93 lsio_gpio1: gpio@5d090000 { 94 reg = <0x5d090000 0x10000>; 95 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 96 gpio-controller; 97 #gpio-cells = <2>; 98 interrupt-controller; 99 #interrupt-cells = <2>; 100 power-domains = <&pd IMX_SC_R_GPIO_1>; 101 }; 102 103 lsio_gpio2: gpio@5d0a0000 { 104 reg = <0x5d0a0000 0x10000>; 105 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 106 gpio-controller; 107 #gpio-cells = <2>; 108 interrupt-controller; 109 #interrupt-cells = <2>; 110 power-domains = <&pd IMX_SC_R_GPIO_2>; 111 }; 112 113 lsio_gpio3: gpio@5d0b0000 { 114 reg = <0x5d0b0000 0x10000>; 115 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 power-domains = <&pd IMX_SC_R_GPIO_3>; 121 }; 122 123 lsio_gpio4: gpio@5d0c0000 { 124 reg = <0x5d0c0000 0x10000>; 125 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 126 gpio-controller; 127 #gpio-cells = <2>; 128 interrupt-controller; 129 #interrupt-cells = <2>; 130 power-domains = <&pd IMX_SC_R_GPIO_4>; 131 }; 132 133 lsio_gpio5: gpio@5d0d0000 { 134 reg = <0x5d0d0000 0x10000>; 135 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 136 gpio-controller; 137 #gpio-cells = <2>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 power-domains = <&pd IMX_SC_R_GPIO_5>; 141 }; 142 143 lsio_gpio6: gpio@5d0e0000 { 144 reg = <0x5d0e0000 0x10000>; 145 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 power-domains = <&pd IMX_SC_R_GPIO_6>; 151 }; 152 153 lsio_gpio7: gpio@5d0f0000 { 154 reg = <0x5d0f0000 0x10000>; 155 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 interrupt-controller; 159 #interrupt-cells = <2>; 160 power-domains = <&pd IMX_SC_R_GPIO_7>; 161 }; 162 163 flexspi0: spi@5d120000 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 compatible = "nxp,imx8qxp-fspi"; 167 reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; 168 reg-names = "fspi_base", "fspi_mmap"; 169 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, 171 <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; 172 clock-names = "fspi_en", "fspi"; 173 power-domains = <&pd IMX_SC_R_FSPI_0>; 174 status = "disabled"; 175 }; 176 177 lsio_mu0: mailbox@5d1b0000 { 178 reg = <0x5d1b0000 0x10000>; 179 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 180 #mbox-cells = <2>; 181 status = "disabled"; 182 }; 183 184 lsio_mu1: mailbox@5d1c0000 { 185 reg = <0x5d1c0000 0x10000>; 186 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 187 #mbox-cells = <2>; 188 }; 189 190 lsio_mu2: mailbox@5d1d0000 { 191 reg = <0x5d1d0000 0x10000>; 192 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 193 #mbox-cells = <2>; 194 status = "disabled"; 195 }; 196 197 lsio_mu3: mailbox@5d1e0000 { 198 reg = <0x5d1e0000 0x10000>; 199 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 200 #mbox-cells = <2>; 201 status = "disabled"; 202 }; 203 204 lsio_mu4: mailbox@5d1f0000 { 205 reg = <0x5d1f0000 0x10000>; 206 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 207 #mbox-cells = <2>; 208 status = "disabled"; 209 }; 210 211 lsio_mu5: mailbox@5d200000 { 212 reg = <0x5d200000 0x10000>; 213 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 214 #mbox-cells = <2>; 215 power-domains = <&pd IMX_SC_R_MU_5A>; 216 status = "disabled"; 217 }; 218 219 lsio_mu6: mailbox@5d210000 { 220 reg = <0x5d210000 0x10000>; 221 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 222 #mbox-cells = <2>; 223 power-domains = <&pd IMX_SC_R_MU_6A>; 224 status = "disabled"; 225 }; 226 227 lsio_mu13: mailbox@5d280000 { 228 reg = <0x5d280000 0x10000>; 229 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 230 #mbox-cells = <2>; 231 power-domains = <&pd IMX_SC_R_MU_13A>; 232 }; 233 234 /* LPCG clocks */ 235 pwm0_lpcg: clock-controller@5d400000 { 236 compatible = "fsl,imx8qxp-lpcg"; 237 reg = <0x5d400000 0x10000>; 238 #clock-cells = <1>; 239 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 240 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 241 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 242 <&lsio_bus_clk>, 243 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 244 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 245 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 246 <IMX_LPCG_CLK_6>; 247 clock-output-names = "pwm0_lpcg_ipg_clk", 248 "pwm0_lpcg_ipg_hf_clk", 249 "pwm0_lpcg_ipg_s_clk", 250 "pwm0_lpcg_ipg_slv_clk", 251 "pwm0_lpcg_ipg_mstr_clk"; 252 power-domains = <&pd IMX_SC_R_PWM_0>; 253 }; 254 255 pwm1_lpcg: clock-controller@5d410000 { 256 compatible = "fsl,imx8qxp-lpcg"; 257 reg = <0x5d410000 0x10000>; 258 #clock-cells = <1>; 259 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 260 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 261 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 262 <&lsio_bus_clk>, 263 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 264 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 265 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 266 <IMX_LPCG_CLK_6>; 267 clock-output-names = "pwm1_lpcg_ipg_clk", 268 "pwm1_lpcg_ipg_hf_clk", 269 "pwm1_lpcg_ipg_s_clk", 270 "pwm1_lpcg_ipg_slv_clk", 271 "pwm1_lpcg_ipg_mstr_clk"; 272 power-domains = <&pd IMX_SC_R_PWM_1>; 273 }; 274 275 pwm2_lpcg: clock-controller@5d420000 { 276 compatible = "fsl,imx8qxp-lpcg"; 277 reg = <0x5d420000 0x10000>; 278 #clock-cells = <1>; 279 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 280 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 281 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 282 <&lsio_bus_clk>, 283 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 284 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 285 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 286 <IMX_LPCG_CLK_6>; 287 clock-output-names = "pwm2_lpcg_ipg_clk", 288 "pwm2_lpcg_ipg_hf_clk", 289 "pwm2_lpcg_ipg_s_clk", 290 "pwm2_lpcg_ipg_slv_clk", 291 "pwm2_lpcg_ipg_mstr_clk"; 292 power-domains = <&pd IMX_SC_R_PWM_2>; 293 }; 294 295 pwm3_lpcg: clock-controller@5d430000 { 296 compatible = "fsl,imx8qxp-lpcg"; 297 reg = <0x5d430000 0x10000>; 298 #clock-cells = <1>; 299 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 300 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 301 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 302 <&lsio_bus_clk>, 303 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 304 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 305 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 306 <IMX_LPCG_CLK_6>; 307 clock-output-names = "pwm3_lpcg_ipg_clk", 308 "pwm3_lpcg_ipg_hf_clk", 309 "pwm3_lpcg_ipg_s_clk", 310 "pwm3_lpcg_ipg_slv_clk", 311 "pwm3_lpcg_ipg_mstr_clk"; 312 power-domains = <&pd IMX_SC_R_PWM_3>; 313 }; 314 315 pwm4_lpcg: clock-controller@5d440000 { 316 compatible = "fsl,imx8qxp-lpcg"; 317 reg = <0x5d440000 0x10000>; 318 #clock-cells = <1>; 319 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 320 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 321 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 322 <&lsio_bus_clk>, 323 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; 324 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 325 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 326 <IMX_LPCG_CLK_6>; 327 clock-output-names = "pwm4_lpcg_ipg_clk", 328 "pwm4_lpcg_ipg_hf_clk", 329 "pwm4_lpcg_ipg_s_clk", 330 "pwm4_lpcg_ipg_slv_clk", 331 "pwm4_lpcg_ipg_mstr_clk"; 332 power-domains = <&pd IMX_SC_R_PWM_4>; 333 }; 334 335 pwm5_lpcg: clock-controller@5d450000 { 336 compatible = "fsl,imx8qxp-lpcg"; 337 reg = <0x5d450000 0x10000>; 338 #clock-cells = <1>; 339 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 340 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 341 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 342 <&lsio_bus_clk>, 343 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; 344 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 345 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 346 <IMX_LPCG_CLK_6>; 347 clock-output-names = "pwm5_lpcg_ipg_clk", 348 "pwm5_lpcg_ipg_hf_clk", 349 "pwm5_lpcg_ipg_s_clk", 350 "pwm5_lpcg_ipg_slv_clk", 351 "pwm5_lpcg_ipg_mstr_clk"; 352 power-domains = <&pd IMX_SC_R_PWM_5>; 353 }; 354 355 pwm6_lpcg: clock-controller@5d460000 { 356 compatible = "fsl,imx8qxp-lpcg"; 357 reg = <0x5d460000 0x10000>; 358 #clock-cells = <1>; 359 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 360 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 361 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 362 <&lsio_bus_clk>, 363 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; 364 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 365 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 366 <IMX_LPCG_CLK_6>; 367 clock-output-names = "pwm6_lpcg_ipg_clk", 368 "pwm6_lpcg_ipg_hf_clk", 369 "pwm6_lpcg_ipg_s_clk", 370 "pwm6_lpcg_ipg_slv_clk", 371 "pwm6_lpcg_ipg_mstr_clk"; 372 power-domains = <&pd IMX_SC_R_PWM_6>; 373 }; 374 375 pwm7_lpcg: clock-controller@5d470000 { 376 compatible = "fsl,imx8qxp-lpcg"; 377 reg = <0x5d470000 0x10000>; 378 #clock-cells = <1>; 379 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 380 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 381 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 382 <&lsio_bus_clk>, 383 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; 384 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 385 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 386 <IMX_LPCG_CLK_6>; 387 clock-output-names = "pwm7_lpcg_ipg_clk", 388 "pwm7_lpcg_ipg_hf_clk", 389 "pwm7_lpcg_ipg_s_clk", 390 "pwm7_lpcg_ipg_slv_clk", 391 "pwm7_lpcg_ipg_mstr_clk"; 392 power-domains = <&pd IMX_SC_R_PWM_7>; 393 }; 394 }; 395