xref: /openbmc/qemu/include/hw/i386/apic_internal.h (revision 774204cf)
1 /*
2  *  APIC support - internal interfaces
3  *
4  *  Copyright (c) 2004-2005 Fabrice Bellard
5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
19  */
20 
21 #ifndef QEMU_APIC_INTERNAL_H
22 #define QEMU_APIC_INTERNAL_H
23 
24 #include "cpu.h"
25 #include "exec/memory.h"
26 #include "qemu/timer.h"
27 #include "target/i386/cpu-qom.h"
28 #include "qom/object.h"
29 
30 /* APIC Local Vector Table */
31 #define APIC_LVT_TIMER                  0
32 #define APIC_LVT_THERMAL                1
33 #define APIC_LVT_PERFORM                2
34 #define APIC_LVT_LINT0                  3
35 #define APIC_LVT_LINT1                  4
36 #define APIC_LVT_ERROR                  5
37 #define APIC_LVT_NB                     6
38 
39 /* APIC delivery modes */
40 #define APIC_DM_FIXED                   0
41 #define APIC_DM_LOWPRI                  1
42 #define APIC_DM_SMI                     2
43 #define APIC_DM_NMI                     4
44 #define APIC_DM_INIT                    5
45 #define APIC_DM_SIPI                    6
46 #define APIC_DM_EXTINT                  7
47 
48 /* APIC destination mode */
49 #define APIC_DESTMODE_PHYSICAL          0
50 #define APIC_DESTMODE_LOGICAL           1
51 #define APIC_DESTMODE_LOGICAL_FLAT      0xf
52 #define APIC_DESTMODE_LOGICAL_CLUSTER   0
53 
54 #define APIC_TRIGGER_EDGE               0
55 #define APIC_TRIGGER_LEVEL              1
56 
57 #define APIC_VECTOR_MASK                0xff
58 #define APIC_DCR_MASK                   0xf
59 
60 #define APIC_LVT_TIMER_SHIFT            17
61 #define APIC_LVT_MASKED_SHIFT           16
62 #define APIC_LVT_LEVEL_TRIGGER_SHIFT    15
63 #define APIC_LVT_REMOTE_IRR_SHIFT       14
64 #define APIC_LVT_INT_POLARITY_SHIFT     13
65 #define APIC_LVT_DELIV_STS_SHIFT        12
66 #define APIC_LVT_DELIV_MOD_SHIFT        8
67 
68 #define APIC_LVT_TIMER_TSCDEADLINE      (2 << APIC_LVT_TIMER_SHIFT)
69 #define APIC_LVT_TIMER_PERIODIC         (1 << APIC_LVT_TIMER_SHIFT)
70 #define APIC_LVT_MASKED                 (1 << APIC_LVT_MASKED_SHIFT)
71 #define APIC_LVT_LEVEL_TRIGGER          (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
72 #define APIC_LVT_REMOTE_IRR             (1 << APIC_LVT_REMOTE_IRR_SHIFT)
73 #define APIC_LVT_INT_POLARITY           (1 << APIC_LVT_INT_POLARITY_SHIFT)
74 #define APIC_LVT_DELIV_STS              (1 << APIC_LVT_DELIV_STS_SHIFT)
75 #define APIC_LVT_DELIV_MOD              (7 << APIC_LVT_DELIV_MOD_SHIFT)
76 
77 #define APIC_ESR_ILL_ADDRESS_SHIFT      7
78 #define APIC_ESR_RECV_ILL_VECT_SHIFT    6
79 #define APIC_ESR_SEND_ILL_VECT_SHIFT    5
80 #define APIC_ESR_RECV_ACCEPT_SHIFT      3
81 #define APIC_ESR_SEND_ACCEPT_SHIFT      2
82 #define APIC_ESR_RECV_CHECK_SUM_SHIFT   1
83 
84 #define APIC_ESR_ILLEGAL_ADDRESS        (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
85 #define APIC_ESR_RECV_ILLEGAL_VECT      (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
86 #define APIC_ESR_SEND_ILLEGAL_VECT      (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
87 #define APIC_ESR_RECV_ACCEPT            (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
88 #define APIC_ESR_SEND_ACCEPT            (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
89 #define APIC_ESR_RECV_CHECK_SUM         (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
90 #define APIC_ESR_SEND_CHECK_SUM         1
91 
92 #define APIC_ICR_DEST_SHIFT             24
93 #define APIC_ICR_DEST_SHORT_SHIFT       18
94 #define APIC_ICR_TRIGGER_MOD_SHIFT      15
95 #define APIC_ICR_LEVEL_SHIFT            14
96 #define APIC_ICR_DELIV_STS_SHIFT        12
97 #define APIC_ICR_DEST_MOD_SHIFT         11
98 #define APIC_ICR_DELIV_MOD_SHIFT        8
99 
100 #define APIC_ICR_DEST_SHORT             (3 << APIC_ICR_DEST_SHORT_SHIFT)
101 #define APIC_ICR_TRIGGER_MOD            (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
102 #define APIC_ICR_LEVEL                  (1 << APIC_ICR_LEVEL_SHIFT)
103 #define APIC_ICR_DELIV_STS              (1 << APIC_ICR_DELIV_STS_SHIFT)
104 #define APIC_ICR_DEST_MOD               (1 << APIC_ICR_DEST_MOD_SHIFT)
105 #define APIC_ICR_DELIV_MOD              (7 << APIC_ICR_DELIV_MOD_SHIFT)
106 
107 #define APIC_PR_CLASS_SHIFT             4
108 #define APIC_PR_SUB_CLASS               0xf
109 
110 #define APIC_LOGDEST_XAPIC_SHIFT        4
111 #define APIC_LOGDEST_XAPIC_ID           0xf
112 
113 #define APIC_LOGDEST_X2APIC_SHIFT       16
114 #define APIC_LOGDEST_X2APIC_ID          0xffff
115 
116 #define APIC_SPURIO_FOCUS_SHIFT         9
117 #define APIC_SPURIO_ENABLED_SHIFT       8
118 
119 #define APIC_SPURIO_FOCUS               (1 << APIC_SPURIO_FOCUS_SHIFT)
120 #define APIC_SPURIO_ENABLED             (1 << APIC_SPURIO_ENABLED_SHIFT)
121 
122 #define APIC_SV_DIRECTED_IO             (1 << 12)
123 #define APIC_SV_ENABLE                  (1 << 8)
124 
125 #define VAPIC_ENABLE_BIT                0
126 #define VAPIC_ENABLE_MASK               (1 << VAPIC_ENABLE_BIT)
127 
128 typedef struct APICCommonState APICCommonState;
129 
130 #define TYPE_APIC_COMMON "apic-common"
131 typedef struct APICCommonClass APICCommonClass;
132 DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass,
133                      APIC_COMMON, TYPE_APIC_COMMON)
134 
135 struct APICCommonClass {
136     DeviceClass parent_class;
137 
138     DeviceRealize realize;
139     DeviceUnrealize unrealize;
140     int (*set_base)(APICCommonState *s, uint64_t val);
141     void (*set_tpr)(APICCommonState *s, uint8_t val);
142     uint8_t (*get_tpr)(APICCommonState *s);
143     void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
144     void (*vapic_base_update)(APICCommonState *s);
145     void (*external_nmi)(APICCommonState *s);
146     void (*pre_save)(APICCommonState *s);
147     void (*post_load)(APICCommonState *s);
148     void (*reset)(APICCommonState *s);
149     /* send_msi emulates an APIC bus and its proper place would be in a new
150      * device, but it's convenient to have it here for now.
151      */
152     void (*send_msi)(MSIMessage *msi);
153 };
154 
155 struct APICCommonState {
156     /*< private >*/
157     DeviceState parent_obj;
158     /*< public >*/
159 
160     MemoryRegion io_memory;
161     X86CPU *cpu;
162     uint32_t apicbase;
163     uint8_t id; /* legacy APIC ID */
164     uint32_t initial_apic_id;
165     uint8_t version;
166     uint8_t arb_id;
167     uint8_t tpr;
168     uint32_t spurious_vec;
169     uint8_t log_dest;
170     uint8_t dest_mode;
171     uint32_t isr[8];  /* in service register */
172     uint32_t tmr[8];  /* trigger mode register */
173     uint32_t irr[8]; /* interrupt request register */
174     uint32_t lvt[APIC_LVT_NB];
175     uint32_t esr; /* error register */
176     uint32_t icr[2];
177 
178     uint32_t divide_conf;
179     int count_shift;
180     uint32_t initial_count;
181     int64_t initial_count_load_time;
182     int64_t next_time;
183     QEMUTimer *timer;
184     int64_t timer_expiry;
185     int sipi_vector;
186     int wait_for_sipi;
187 
188     uint32_t vapic_control;
189     DeviceState *vapic;
190     hwaddr vapic_paddr; /* note: persistence via kvmvapic */
191     bool legacy_instance_id;
192     uint32_t extended_log_dest;
193 };
194 
195 typedef struct VAPICState {
196     uint8_t tpr;
197     uint8_t isr;
198     uint8_t zero;
199     uint8_t irr;
200     uint8_t enabled;
201 } QEMU_PACKED VAPICState;
202 
203 extern bool apic_report_tpr_access;
204 
205 bool apic_next_timer(APICCommonState *s, int64_t current_time);
206 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
207 void apic_enable_vapic(DeviceState *d, hwaddr paddr);
208 
209 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
210                              TPRAccess access);
211 
212 int apic_get_ppr(APICCommonState *s);
213 uint32_t apic_get_current_count(APICCommonState *s);
214 
apic_set_bit(uint32_t * tab,int index)215 static inline void apic_set_bit(uint32_t *tab, int index)
216 {
217     int i, mask;
218     i = index >> 5;
219     mask = 1 << (index & 0x1f);
220     tab[i] |= mask;
221 }
222 
apic_get_bit(uint32_t * tab,int index)223 static inline int apic_get_bit(uint32_t *tab, int index)
224 {
225     int i, mask;
226     i = index >> 5;
227     mask = 1 << (index & 0x1f);
228     return !!(tab[i] & mask);
229 }
230 
231 APICCommonClass *apic_get_class(Error **errp);
232 
233 #endif /* QEMU_APIC_INTERNAL_H */
234