1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/export.h>
22 #include <linux/gpio.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_data/b53.h>
26 #include <linux/phy.h>
27 #include <linux/phylink.h>
28 #include <linux/etherdevice.h>
29 #include <linux/if_bridge.h>
30 #include <linux/if_vlan.h>
31 #include <net/dsa.h>
32
33 #include "b53_regs.h"
34 #include "b53_priv.h"
35
36 struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40 };
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 };
77
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124 };
125
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 };
166
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224 };
225
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
230
b53_do_vlan_op(struct b53_device * dev,u8 op)231 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
232 {
233 unsigned int i;
234
235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
236
237 for (i = 0; i < 10; i++) {
238 u8 vta;
239
240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
241 if (!(vta & VTA_START_CMD))
242 return 0;
243
244 usleep_range(100, 200);
245 }
246
247 return -EIO;
248 }
249
b53_set_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
251 struct b53_vlan *vlan)
252 {
253 if (is5325(dev)) {
254 u32 entry = 0;
255
256 if (vlan->members) {
257 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
258 VA_UNTAG_S_25) | vlan->members;
259 if (dev->core_rev >= 3)
260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
261 else
262 entry |= VA_VALID_25;
263 }
264
265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
267 VTA_RW_STATE_WR | VTA_RW_OP_EN);
268 } else if (is5365(dev)) {
269 u16 entry = 0;
270
271 if (vlan->members)
272 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
274
275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
277 VTA_RW_STATE_WR | VTA_RW_OP_EN);
278 } else {
279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
281 (vlan->untag << VTE_UNTAG_S) | vlan->members);
282
283 b53_do_vlan_op(dev, VTA_CMD_WRITE);
284 }
285
286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
287 vid, vlan->members, vlan->untag);
288 }
289
b53_get_vlan_entry(struct b53_device * dev,u16 vid,struct b53_vlan * vlan)290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
291 struct b53_vlan *vlan)
292 {
293 if (is5325(dev)) {
294 u32 entry = 0;
295
296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
297 VTA_RW_STATE_RD | VTA_RW_OP_EN);
298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
299
300 if (dev->core_rev >= 3)
301 vlan->valid = !!(entry & VA_VALID_25_R4);
302 else
303 vlan->valid = !!(entry & VA_VALID_25);
304 vlan->members = entry & VA_MEMBER_MASK;
305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
306
307 } else if (is5365(dev)) {
308 u16 entry = 0;
309
310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
311 VTA_RW_STATE_WR | VTA_RW_OP_EN);
312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
313
314 vlan->valid = !!(entry & VA_VALID_65);
315 vlan->members = entry & VA_MEMBER_MASK;
316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
317 } else {
318 u32 entry = 0;
319
320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
321 b53_do_vlan_op(dev, VTA_CMD_READ);
322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
323 vlan->members = entry & VTE_MEMBERS;
324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
325 vlan->valid = true;
326 }
327 }
328
b53_set_forwarding(struct b53_device * dev,int enable)329 static void b53_set_forwarding(struct b53_device *dev, int enable)
330 {
331 u8 mgmt;
332
333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
334
335 if (enable)
336 mgmt |= SM_SW_FWD_EN;
337 else
338 mgmt &= ~SM_SW_FWD_EN;
339
340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
341
342 /* Include IMP port in dumb forwarding mode
343 */
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347
348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
349 * frames should be flooded or not.
350 */
351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
354 }
355
b53_enable_vlan(struct b53_device * dev,int port,bool enable,bool enable_filtering)356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
357 bool enable_filtering)
358 {
359 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
360
361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
364
365 if (is5325(dev) || is5365(dev)) {
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
368 } else if (is63xx(dev)) {
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
371 } else {
372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
374 }
375
376 if (enable) {
377 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
378 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
379 vc4 &= ~VC4_ING_VID_CHECK_MASK;
380 if (enable_filtering) {
381 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
382 vc5 |= VC5_DROP_VTABLE_MISS;
383 } else {
384 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
385 vc5 &= ~VC5_DROP_VTABLE_MISS;
386 }
387
388 if (is5325(dev))
389 vc0 &= ~VC0_RESERVED_1;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 |= VC1_RX_MCST_TAG_EN;
393
394 } else {
395 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
396 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
397 vc4 &= ~VC4_ING_VID_CHECK_MASK;
398 vc5 &= ~VC5_DROP_VTABLE_MISS;
399
400 if (is5325(dev) || is5365(dev))
401 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
402 else
403 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
404
405 if (is5325(dev) || is5365(dev))
406 vc1 &= ~VC1_RX_MCST_TAG_EN;
407 }
408
409 if (!is5325(dev) && !is5365(dev))
410 vc5 &= ~VC5_VID_FFF_EN;
411
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
414
415 if (is5325(dev) || is5365(dev)) {
416 /* enable the high 8 bit vid check on 5325 */
417 if (is5325(dev) && enable)
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
419 VC3_HIGH_8BIT_EN);
420 else
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
422
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
425 } else if (is63xx(dev)) {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
429 } else {
430 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
431 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
432 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
433 }
434
435 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
436
437 dev->vlan_enabled = enable;
438
439 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
440 port, enable, enable_filtering);
441 }
442
b53_set_jumbo(struct b53_device * dev,bool enable,bool allow_10_100)443 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
444 {
445 u32 port_mask = 0;
446 u16 max_size = JMS_MIN_SIZE;
447
448 if (is5325(dev) || is5365(dev))
449 return -EINVAL;
450
451 if (enable) {
452 port_mask = dev->enabled_ports;
453 max_size = JMS_MAX_SIZE;
454 if (allow_10_100)
455 port_mask |= JPM_10_100_JUMBO_EN;
456 }
457
458 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
459 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
460 }
461
b53_flush_arl(struct b53_device * dev,u8 mask)462 static int b53_flush_arl(struct b53_device *dev, u8 mask)
463 {
464 unsigned int i;
465
466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
467 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
468
469 for (i = 0; i < 10; i++) {
470 u8 fast_age_ctrl;
471
472 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
473 &fast_age_ctrl);
474
475 if (!(fast_age_ctrl & FAST_AGE_DONE))
476 goto out;
477
478 msleep(1);
479 }
480
481 return -ETIMEDOUT;
482 out:
483 /* Only age dynamic entries (default behavior) */
484 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
485 return 0;
486 }
487
b53_fast_age_port(struct b53_device * dev,int port)488 static int b53_fast_age_port(struct b53_device *dev, int port)
489 {
490 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
491
492 return b53_flush_arl(dev, FAST_AGE_PORT);
493 }
494
b53_fast_age_vlan(struct b53_device * dev,u16 vid)495 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
496 {
497 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
498
499 return b53_flush_arl(dev, FAST_AGE_VLAN);
500 }
501
b53_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)502 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
503 {
504 struct b53_device *dev = ds->priv;
505 unsigned int i;
506 u16 pvlan;
507
508 /* Enable the IMP port to be in the same VLAN as the other ports
509 * on a per-port basis such that we only have Port i and IMP in
510 * the same VLAN.
511 */
512 b53_for_each_port(dev, i) {
513 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
514 pvlan |= BIT(cpu_port);
515 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
516 }
517 }
518 EXPORT_SYMBOL(b53_imp_vlan_setup);
519
b53_port_set_ucast_flood(struct b53_device * dev,int port,bool unicast)520 static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
521 bool unicast)
522 {
523 u16 uc;
524
525 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
526 if (unicast)
527 uc |= BIT(port);
528 else
529 uc &= ~BIT(port);
530 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
531 }
532
b53_port_set_mcast_flood(struct b53_device * dev,int port,bool multicast)533 static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
534 bool multicast)
535 {
536 u16 mc;
537
538 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
539 if (multicast)
540 mc |= BIT(port);
541 else
542 mc &= ~BIT(port);
543 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
544
545 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
546 if (multicast)
547 mc |= BIT(port);
548 else
549 mc &= ~BIT(port);
550 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
551 }
552
b53_port_set_learning(struct b53_device * dev,int port,bool learning)553 static void b53_port_set_learning(struct b53_device *dev, int port,
554 bool learning)
555 {
556 u16 reg;
557
558 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
559 if (learning)
560 reg &= ~BIT(port);
561 else
562 reg |= BIT(port);
563 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
564 }
565
b53_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)566 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
567 {
568 struct b53_device *dev = ds->priv;
569 unsigned int cpu_port;
570 int ret = 0;
571 u16 pvlan;
572
573 if (!dsa_is_user_port(ds, port))
574 return 0;
575
576 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
577
578 b53_port_set_ucast_flood(dev, port, true);
579 b53_port_set_mcast_flood(dev, port, true);
580 b53_port_set_learning(dev, port, false);
581
582 if (dev->ops->irq_enable)
583 ret = dev->ops->irq_enable(dev, port);
584 if (ret)
585 return ret;
586
587 /* Clear the Rx and Tx disable bits and set to no spanning tree */
588 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
589
590 /* Set this port, and only this one to be in the default VLAN,
591 * if member of a bridge, restore its membership prior to
592 * bringing down this port.
593 */
594 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
595 pvlan &= ~0x1ff;
596 pvlan |= BIT(port);
597 pvlan |= dev->ports[port].vlan_ctl_mask;
598 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
599
600 b53_imp_vlan_setup(ds, cpu_port);
601
602 /* If EEE was enabled, restore it */
603 if (dev->ports[port].eee.eee_enabled)
604 b53_eee_enable_set(ds, port, true);
605
606 return 0;
607 }
608 EXPORT_SYMBOL(b53_enable_port);
609
b53_disable_port(struct dsa_switch * ds,int port)610 void b53_disable_port(struct dsa_switch *ds, int port)
611 {
612 struct b53_device *dev = ds->priv;
613 u8 reg;
614
615 /* Disable Tx/Rx for the port */
616 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
617 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
618 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
619
620 if (dev->ops->irq_disable)
621 dev->ops->irq_disable(dev, port);
622 }
623 EXPORT_SYMBOL(b53_disable_port);
624
b53_brcm_hdr_setup(struct dsa_switch * ds,int port)625 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
626 {
627 struct b53_device *dev = ds->priv;
628 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
629 u8 hdr_ctl, val;
630 u16 reg;
631
632 /* Resolve which bit controls the Broadcom tag */
633 switch (port) {
634 case 8:
635 val = BRCM_HDR_P8_EN;
636 break;
637 case 7:
638 val = BRCM_HDR_P7_EN;
639 break;
640 case 5:
641 val = BRCM_HDR_P5_EN;
642 break;
643 default:
644 val = 0;
645 break;
646 }
647
648 /* Enable management mode if tagging is requested */
649 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
650 if (tag_en)
651 hdr_ctl |= SM_SW_FWD_MODE;
652 else
653 hdr_ctl &= ~SM_SW_FWD_MODE;
654 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
655
656 /* Configure the appropriate IMP port */
657 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
658 if (port == 8)
659 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
660 else if (port == 5)
661 hdr_ctl |= GC_FRM_MGMT_PORT_M;
662 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
663
664 /* Enable Broadcom tags for IMP port */
665 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
666 if (tag_en)
667 hdr_ctl |= val;
668 else
669 hdr_ctl &= ~val;
670 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
671
672 /* Registers below are only accessible on newer devices */
673 if (!is58xx(dev))
674 return;
675
676 /* Enable reception Broadcom tag for CPU TX (switch RX) to
677 * allow us to tag outgoing frames
678 */
679 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
680 if (tag_en)
681 reg &= ~BIT(port);
682 else
683 reg |= BIT(port);
684 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
685
686 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
687 * allow delivering frames to the per-port net_devices
688 */
689 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
690 if (tag_en)
691 reg &= ~BIT(port);
692 else
693 reg |= BIT(port);
694 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
695 }
696 EXPORT_SYMBOL(b53_brcm_hdr_setup);
697
b53_enable_cpu_port(struct b53_device * dev,int port)698 static void b53_enable_cpu_port(struct b53_device *dev, int port)
699 {
700 u8 port_ctrl;
701
702 /* BCM5325 CPU port is at 8 */
703 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
704 port = B53_CPU_PORT;
705
706 port_ctrl = PORT_CTRL_RX_BCST_EN |
707 PORT_CTRL_RX_MCST_EN |
708 PORT_CTRL_RX_UCST_EN;
709 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
710
711 b53_brcm_hdr_setup(dev->ds, port);
712
713 b53_port_set_ucast_flood(dev, port, true);
714 b53_port_set_mcast_flood(dev, port, true);
715 b53_port_set_learning(dev, port, false);
716 }
717
b53_enable_mib(struct b53_device * dev)718 static void b53_enable_mib(struct b53_device *dev)
719 {
720 u8 gc;
721
722 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
723 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
724 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
725 }
726
b53_default_pvid(struct b53_device * dev)727 static u16 b53_default_pvid(struct b53_device *dev)
728 {
729 if (is5325(dev) || is5365(dev))
730 return 1;
731 else
732 return 0;
733 }
734
b53_vlan_port_needs_forced_tagged(struct dsa_switch * ds,int port)735 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
736 {
737 struct b53_device *dev = ds->priv;
738
739 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
740 }
741
b53_configure_vlan(struct dsa_switch * ds)742 int b53_configure_vlan(struct dsa_switch *ds)
743 {
744 struct b53_device *dev = ds->priv;
745 struct b53_vlan vl = { 0 };
746 struct b53_vlan *v;
747 int i, def_vid;
748 u16 vid;
749
750 def_vid = b53_default_pvid(dev);
751
752 /* clear all vlan entries */
753 if (is5325(dev) || is5365(dev)) {
754 for (i = def_vid; i < dev->num_vlans; i++)
755 b53_set_vlan_entry(dev, i, &vl);
756 } else {
757 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
758 }
759
760 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
761
762 /* Create an untagged VLAN entry for the default PVID in case
763 * CONFIG_VLAN_8021Q is disabled and there are no calls to
764 * dsa_slave_vlan_rx_add_vid() to create the default VLAN
765 * entry. Do this only when the tagging protocol is not
766 * DSA_TAG_PROTO_NONE
767 */
768 b53_for_each_port(dev, i) {
769 v = &dev->vlans[def_vid];
770 v->members |= BIT(i);
771 if (!b53_vlan_port_needs_forced_tagged(ds, i))
772 v->untag = v->members;
773 b53_write16(dev, B53_VLAN_PAGE,
774 B53_VLAN_PORT_DEF_TAG(i), def_vid);
775 }
776
777 /* Upon initial call we have not set-up any VLANs, but upon
778 * system resume, we need to restore all VLAN entries.
779 */
780 for (vid = def_vid; vid < dev->num_vlans; vid++) {
781 v = &dev->vlans[vid];
782
783 if (!v->members)
784 continue;
785
786 b53_set_vlan_entry(dev, vid, v);
787 b53_fast_age_vlan(dev, vid);
788 }
789
790 return 0;
791 }
792 EXPORT_SYMBOL(b53_configure_vlan);
793
b53_switch_reset_gpio(struct b53_device * dev)794 static void b53_switch_reset_gpio(struct b53_device *dev)
795 {
796 int gpio = dev->reset_gpio;
797
798 if (gpio < 0)
799 return;
800
801 /* Reset sequence: RESET low(50ms)->high(20ms)
802 */
803 gpio_set_value(gpio, 0);
804 mdelay(50);
805
806 gpio_set_value(gpio, 1);
807 mdelay(20);
808
809 dev->current_page = 0xff;
810 }
811
b53_switch_reset(struct b53_device * dev)812 static int b53_switch_reset(struct b53_device *dev)
813 {
814 unsigned int timeout = 1000;
815 u8 mgmt, reg;
816
817 b53_switch_reset_gpio(dev);
818
819 if (is539x(dev)) {
820 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
821 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
822 }
823
824 /* This is specific to 58xx devices here, do not use is58xx() which
825 * covers the larger Starfigther 2 family, including 7445/7278 which
826 * still use this driver as a library and need to perform the reset
827 * earlier.
828 */
829 if (dev->chip_id == BCM58XX_DEVICE_ID ||
830 dev->chip_id == BCM583XX_DEVICE_ID) {
831 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
832 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
833 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
834
835 do {
836 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
837 if (!(reg & SW_RST))
838 break;
839
840 usleep_range(1000, 2000);
841 } while (timeout-- > 0);
842
843 if (timeout == 0) {
844 dev_err(dev->dev,
845 "Timeout waiting for SW_RST to clear!\n");
846 return -ETIMEDOUT;
847 }
848 }
849
850 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
851
852 if (!(mgmt & SM_SW_FWD_EN)) {
853 mgmt &= ~SM_SW_FWD_MODE;
854 mgmt |= SM_SW_FWD_EN;
855
856 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
857 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
858
859 if (!(mgmt & SM_SW_FWD_EN)) {
860 dev_err(dev->dev, "Failed to enable switch!\n");
861 return -EINVAL;
862 }
863 }
864
865 b53_enable_mib(dev);
866
867 return b53_flush_arl(dev, FAST_AGE_STATIC);
868 }
869
b53_phy_read16(struct dsa_switch * ds,int addr,int reg)870 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
871 {
872 struct b53_device *priv = ds->priv;
873 u16 value = 0;
874 int ret;
875
876 if (priv->ops->phy_read16)
877 ret = priv->ops->phy_read16(priv, addr, reg, &value);
878 else
879 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
880 reg * 2, &value);
881
882 return ret ? ret : value;
883 }
884
b53_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)885 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
886 {
887 struct b53_device *priv = ds->priv;
888
889 if (priv->ops->phy_write16)
890 return priv->ops->phy_write16(priv, addr, reg, val);
891
892 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
893 }
894
b53_reset_switch(struct b53_device * priv)895 static int b53_reset_switch(struct b53_device *priv)
896 {
897 /* reset vlans */
898 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
899 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
900
901 priv->serdes_lane = B53_INVALID_LANE;
902
903 return b53_switch_reset(priv);
904 }
905
b53_apply_config(struct b53_device * priv)906 static int b53_apply_config(struct b53_device *priv)
907 {
908 /* disable switching */
909 b53_set_forwarding(priv, 0);
910
911 b53_configure_vlan(priv->ds);
912
913 /* enable switching */
914 b53_set_forwarding(priv, 1);
915
916 return 0;
917 }
918
b53_reset_mib(struct b53_device * priv)919 static void b53_reset_mib(struct b53_device *priv)
920 {
921 u8 gc;
922
923 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
924
925 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
926 msleep(1);
927 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
928 msleep(1);
929 }
930
b53_get_mib(struct b53_device * dev)931 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
932 {
933 if (is5365(dev))
934 return b53_mibs_65;
935 else if (is63xx(dev))
936 return b53_mibs_63xx;
937 else if (is58xx(dev))
938 return b53_mibs_58xx;
939 else
940 return b53_mibs;
941 }
942
b53_get_mib_size(struct b53_device * dev)943 static unsigned int b53_get_mib_size(struct b53_device *dev)
944 {
945 if (is5365(dev))
946 return B53_MIBS_65_SIZE;
947 else if (is63xx(dev))
948 return B53_MIBS_63XX_SIZE;
949 else if (is58xx(dev))
950 return B53_MIBS_58XX_SIZE;
951 else
952 return B53_MIBS_SIZE;
953 }
954
b53_get_phy_device(struct dsa_switch * ds,int port)955 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
956 {
957 /* These ports typically do not have built-in PHYs */
958 switch (port) {
959 case B53_CPU_PORT_25:
960 case 7:
961 case B53_CPU_PORT:
962 return NULL;
963 }
964
965 return mdiobus_get_phy(ds->slave_mii_bus, port);
966 }
967
b53_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)968 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
969 uint8_t *data)
970 {
971 struct b53_device *dev = ds->priv;
972 const struct b53_mib_desc *mibs = b53_get_mib(dev);
973 unsigned int mib_size = b53_get_mib_size(dev);
974 struct phy_device *phydev;
975 unsigned int i;
976
977 if (stringset == ETH_SS_STATS) {
978 for (i = 0; i < mib_size; i++)
979 strscpy(data + i * ETH_GSTRING_LEN,
980 mibs[i].name, ETH_GSTRING_LEN);
981 } else if (stringset == ETH_SS_PHY_STATS) {
982 phydev = b53_get_phy_device(ds, port);
983 if (!phydev)
984 return;
985
986 phy_ethtool_get_strings(phydev, data);
987 }
988 }
989 EXPORT_SYMBOL(b53_get_strings);
990
b53_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)991 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
992 {
993 struct b53_device *dev = ds->priv;
994 const struct b53_mib_desc *mibs = b53_get_mib(dev);
995 unsigned int mib_size = b53_get_mib_size(dev);
996 const struct b53_mib_desc *s;
997 unsigned int i;
998 u64 val = 0;
999
1000 if (is5365(dev) && port == 5)
1001 port = 8;
1002
1003 mutex_lock(&dev->stats_mutex);
1004
1005 for (i = 0; i < mib_size; i++) {
1006 s = &mibs[i];
1007
1008 if (s->size == 8) {
1009 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1010 } else {
1011 u32 val32;
1012
1013 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1014 &val32);
1015 val = val32;
1016 }
1017 data[i] = (u64)val;
1018 }
1019
1020 mutex_unlock(&dev->stats_mutex);
1021 }
1022 EXPORT_SYMBOL(b53_get_ethtool_stats);
1023
b53_get_ethtool_phy_stats(struct dsa_switch * ds,int port,uint64_t * data)1024 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1025 {
1026 struct phy_device *phydev;
1027
1028 phydev = b53_get_phy_device(ds, port);
1029 if (!phydev)
1030 return;
1031
1032 phy_ethtool_get_stats(phydev, NULL, data);
1033 }
1034 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1035
b53_get_sset_count(struct dsa_switch * ds,int port,int sset)1036 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1037 {
1038 struct b53_device *dev = ds->priv;
1039 struct phy_device *phydev;
1040
1041 if (sset == ETH_SS_STATS) {
1042 return b53_get_mib_size(dev);
1043 } else if (sset == ETH_SS_PHY_STATS) {
1044 phydev = b53_get_phy_device(ds, port);
1045 if (!phydev)
1046 return 0;
1047
1048 return phy_ethtool_get_sset_count(phydev);
1049 }
1050
1051 return 0;
1052 }
1053 EXPORT_SYMBOL(b53_get_sset_count);
1054
1055 enum b53_devlink_resource_id {
1056 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1057 };
1058
b53_devlink_vlan_table_get(void * priv)1059 static u64 b53_devlink_vlan_table_get(void *priv)
1060 {
1061 struct b53_device *dev = priv;
1062 struct b53_vlan *vl;
1063 unsigned int i;
1064 u64 count = 0;
1065
1066 for (i = 0; i < dev->num_vlans; i++) {
1067 vl = &dev->vlans[i];
1068 if (vl->members)
1069 count++;
1070 }
1071
1072 return count;
1073 }
1074
b53_setup_devlink_resources(struct dsa_switch * ds)1075 int b53_setup_devlink_resources(struct dsa_switch *ds)
1076 {
1077 struct devlink_resource_size_params size_params;
1078 struct b53_device *dev = ds->priv;
1079 int err;
1080
1081 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1082 dev->num_vlans,
1083 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1084
1085 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1086 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1087 DEVLINK_RESOURCE_ID_PARENT_TOP,
1088 &size_params);
1089 if (err)
1090 goto out;
1091
1092 dsa_devlink_resource_occ_get_register(ds,
1093 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1094 b53_devlink_vlan_table_get, dev);
1095
1096 return 0;
1097 out:
1098 dsa_devlink_resources_unregister(ds);
1099 return err;
1100 }
1101 EXPORT_SYMBOL(b53_setup_devlink_resources);
1102
b53_setup(struct dsa_switch * ds)1103 static int b53_setup(struct dsa_switch *ds)
1104 {
1105 struct b53_device *dev = ds->priv;
1106 unsigned int port;
1107 int ret;
1108
1109 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1110 * which forces the CPU port to be tagged in all VLANs.
1111 */
1112 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1113
1114 ret = b53_reset_switch(dev);
1115 if (ret) {
1116 dev_err(ds->dev, "failed to reset switch\n");
1117 return ret;
1118 }
1119
1120 b53_reset_mib(dev);
1121
1122 ret = b53_apply_config(dev);
1123 if (ret) {
1124 dev_err(ds->dev, "failed to apply configuration\n");
1125 return ret;
1126 }
1127
1128 /* Configure IMP/CPU port, disable all other ports. Enabled
1129 * ports will be configured with .port_enable
1130 */
1131 for (port = 0; port < dev->num_ports; port++) {
1132 if (dsa_is_cpu_port(ds, port))
1133 b53_enable_cpu_port(dev, port);
1134 else
1135 b53_disable_port(ds, port);
1136 }
1137
1138 return b53_setup_devlink_resources(ds);
1139 }
1140
b53_teardown(struct dsa_switch * ds)1141 static void b53_teardown(struct dsa_switch *ds)
1142 {
1143 dsa_devlink_resources_unregister(ds);
1144 }
1145
b53_force_link(struct b53_device * dev,int port,int link)1146 static void b53_force_link(struct b53_device *dev, int port, int link)
1147 {
1148 u8 reg, val, off;
1149
1150 /* Override the port settings */
1151 if (port == dev->imp_port) {
1152 off = B53_PORT_OVERRIDE_CTRL;
1153 val = PORT_OVERRIDE_EN;
1154 } else {
1155 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1156 val = GMII_PO_EN;
1157 }
1158
1159 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1160 reg |= val;
1161 if (link)
1162 reg |= PORT_OVERRIDE_LINK;
1163 else
1164 reg &= ~PORT_OVERRIDE_LINK;
1165 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1166 }
1167
b53_force_port_config(struct b53_device * dev,int port,int speed,int duplex,bool tx_pause,bool rx_pause)1168 static void b53_force_port_config(struct b53_device *dev, int port,
1169 int speed, int duplex,
1170 bool tx_pause, bool rx_pause)
1171 {
1172 u8 reg, val, off;
1173
1174 /* Override the port settings */
1175 if (port == dev->imp_port) {
1176 off = B53_PORT_OVERRIDE_CTRL;
1177 val = PORT_OVERRIDE_EN;
1178 } else {
1179 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1180 val = GMII_PO_EN;
1181 }
1182
1183 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1184 reg |= val;
1185 if (duplex == DUPLEX_FULL)
1186 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1187 else
1188 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1189
1190 switch (speed) {
1191 case 2000:
1192 reg |= PORT_OVERRIDE_SPEED_2000M;
1193 fallthrough;
1194 case SPEED_1000:
1195 reg |= PORT_OVERRIDE_SPEED_1000M;
1196 break;
1197 case SPEED_100:
1198 reg |= PORT_OVERRIDE_SPEED_100M;
1199 break;
1200 case SPEED_10:
1201 reg |= PORT_OVERRIDE_SPEED_10M;
1202 break;
1203 default:
1204 dev_err(dev->dev, "unknown speed: %d\n", speed);
1205 return;
1206 }
1207
1208 if (rx_pause)
1209 reg |= PORT_OVERRIDE_RX_FLOW;
1210 if (tx_pause)
1211 reg |= PORT_OVERRIDE_TX_FLOW;
1212
1213 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1214 }
1215
b53_adjust_63xx_rgmii(struct dsa_switch * ds,int port,phy_interface_t interface)1216 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1217 phy_interface_t interface)
1218 {
1219 struct b53_device *dev = ds->priv;
1220 u8 rgmii_ctrl = 0, off;
1221
1222 if (port == dev->imp_port)
1223 off = B53_RGMII_CTRL_IMP;
1224 else
1225 off = B53_RGMII_CTRL_P(port);
1226
1227 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1228
1229 switch (interface) {
1230 case PHY_INTERFACE_MODE_RGMII_ID:
1231 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1232 break;
1233 case PHY_INTERFACE_MODE_RGMII_RXID:
1234 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC);
1235 rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
1236 break;
1237 case PHY_INTERFACE_MODE_RGMII_TXID:
1238 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC);
1239 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1240 break;
1241 case PHY_INTERFACE_MODE_RGMII:
1242 default:
1243 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1244 break;
1245 }
1246
1247 if (port != dev->imp_port) {
1248 if (is63268(dev))
1249 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1250
1251 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1252 }
1253
1254 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1255
1256 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1257 phy_modes(interface));
1258 }
1259
b53_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)1260 static void b53_adjust_link(struct dsa_switch *ds, int port,
1261 struct phy_device *phydev)
1262 {
1263 struct b53_device *dev = ds->priv;
1264 struct ethtool_eee *p = &dev->ports[port].eee;
1265 u8 rgmii_ctrl = 0, reg = 0, off;
1266 bool tx_pause = false;
1267 bool rx_pause = false;
1268
1269 if (!phy_is_pseudo_fixed_link(phydev))
1270 return;
1271
1272 /* Enable flow control on BCM5301x's CPU port */
1273 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1274 tx_pause = rx_pause = true;
1275
1276 if (phydev->pause) {
1277 if (phydev->asym_pause)
1278 tx_pause = true;
1279 rx_pause = true;
1280 }
1281
1282 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1283 tx_pause, rx_pause);
1284 b53_force_link(dev, port, phydev->link);
1285
1286 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1287 b53_adjust_63xx_rgmii(ds, port, phydev->interface);
1288
1289 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1290 if (port == dev->imp_port)
1291 off = B53_RGMII_CTRL_IMP;
1292 else
1293 off = B53_RGMII_CTRL_P(port);
1294
1295 /* Configure the port RGMII clock delay by DLL disabled and
1296 * tx_clk aligned timing (restoring to reset defaults)
1297 */
1298 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1299 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1300 RGMII_CTRL_TIMING_SEL);
1301
1302 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1303 * sure that we enable the port TX clock internal delay to
1304 * account for this internal delay that is inserted, otherwise
1305 * the switch won't be able to receive correctly.
1306 *
1307 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1308 * any delay neither on transmission nor reception, so the
1309 * BCM53125 must also be configured accordingly to account for
1310 * the lack of delay and introduce
1311 *
1312 * The BCM53125 switch has its RX clock and TX clock control
1313 * swapped, hence the reason why we modify the TX clock path in
1314 * the "RGMII" case
1315 */
1316 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1317 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1318 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1319 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1320 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1321 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1322
1323 dev_info(ds->dev, "Configured port %d for %s\n", port,
1324 phy_modes(phydev->interface));
1325 }
1326
1327 /* configure MII port if necessary */
1328 if (is5325(dev)) {
1329 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1330 ®);
1331
1332 /* reverse mii needs to be enabled */
1333 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1334 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1335 reg | PORT_OVERRIDE_RV_MII_25);
1336 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1337 ®);
1338
1339 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1340 dev_err(ds->dev,
1341 "Failed to enable reverse MII mode\n");
1342 return;
1343 }
1344 }
1345 }
1346
1347 /* Re-negotiate EEE if it was enabled already */
1348 p->eee_enabled = b53_eee_init(ds, port, phydev);
1349 }
1350
b53_port_event(struct dsa_switch * ds,int port)1351 void b53_port_event(struct dsa_switch *ds, int port)
1352 {
1353 struct b53_device *dev = ds->priv;
1354 bool link;
1355 u16 sts;
1356
1357 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1358 link = !!(sts & BIT(port));
1359 dsa_port_phylink_mac_change(ds, port, link);
1360 }
1361 EXPORT_SYMBOL(b53_port_event);
1362
b53_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1363 static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1364 struct phylink_config *config)
1365 {
1366 struct b53_device *dev = ds->priv;
1367
1368 /* Internal ports need GMII for PHYLIB */
1369 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1370
1371 /* These switches appear to support MII and RevMII too, but beyond
1372 * this, the code gives very few clues. FIXME: We probably need more
1373 * interface modes here.
1374 *
1375 * According to b53_srab_mux_init(), ports 3..5 can support:
1376 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1377 * However, the interface mode read from the MUX configuration is
1378 * not passed back to DSA, so phylink uses NA.
1379 * DT can specify RGMII for ports 0, 1.
1380 * For MDIO, port 8 can be RGMII_TXID.
1381 */
1382 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1383 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1384
1385 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1386 MAC_10 | MAC_100;
1387
1388 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1389 * Note: the original code also exclulded Gigagbit for MII, RevMII
1390 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1391 * so will be excluded by the generic validator implementation.
1392 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1393 */
1394 if (!(is5325(dev) || is5365(dev)))
1395 config->mac_capabilities |= MAC_1000;
1396
1397 /* Get the implementation specific capabilities */
1398 if (dev->ops->phylink_get_caps)
1399 dev->ops->phylink_get_caps(dev, port, config);
1400 }
1401
b53_phylink_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)1402 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1403 int port,
1404 phy_interface_t interface)
1405 {
1406 struct b53_device *dev = ds->priv;
1407
1408 if (!dev->ops->phylink_mac_select_pcs)
1409 return NULL;
1410
1411 return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1412 }
1413
b53_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)1414 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1415 unsigned int mode,
1416 const struct phylink_link_state *state)
1417 {
1418 }
1419 EXPORT_SYMBOL(b53_phylink_mac_config);
1420
b53_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1421 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1422 unsigned int mode,
1423 phy_interface_t interface)
1424 {
1425 struct b53_device *dev = ds->priv;
1426
1427 if (mode == MLO_AN_PHY)
1428 return;
1429
1430 if (mode == MLO_AN_FIXED) {
1431 b53_force_link(dev, port, false);
1432 return;
1433 }
1434
1435 if (phy_interface_mode_is_8023z(interface) &&
1436 dev->ops->serdes_link_set)
1437 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1438 }
1439 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1440
b53_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1441 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1442 unsigned int mode,
1443 phy_interface_t interface,
1444 struct phy_device *phydev,
1445 int speed, int duplex,
1446 bool tx_pause, bool rx_pause)
1447 {
1448 struct b53_device *dev = ds->priv;
1449
1450 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1451 b53_adjust_63xx_rgmii(ds, port, interface);
1452
1453 if (mode == MLO_AN_PHY)
1454 return;
1455
1456 if (mode == MLO_AN_FIXED) {
1457 b53_force_port_config(dev, port, speed, duplex,
1458 tx_pause, rx_pause);
1459 b53_force_link(dev, port, true);
1460 return;
1461 }
1462
1463 if (phy_interface_mode_is_8023z(interface) &&
1464 dev->ops->serdes_link_set)
1465 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1466 }
1467 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1468
b53_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1469 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1470 struct netlink_ext_ack *extack)
1471 {
1472 struct b53_device *dev = ds->priv;
1473
1474 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1475
1476 return 0;
1477 }
1478 EXPORT_SYMBOL(b53_vlan_filtering);
1479
b53_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1480 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1481 const struct switchdev_obj_port_vlan *vlan)
1482 {
1483 struct b53_device *dev = ds->priv;
1484
1485 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1486 return -EOPNOTSUPP;
1487
1488 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1489 * receiving VLAN tagged frames at all, we can still allow the port to
1490 * be configured for egress untagged.
1491 */
1492 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1493 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1494 return -EINVAL;
1495
1496 if (vlan->vid >= dev->num_vlans)
1497 return -ERANGE;
1498
1499 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1500
1501 return 0;
1502 }
1503
b53_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1504 int b53_vlan_add(struct dsa_switch *ds, int port,
1505 const struct switchdev_obj_port_vlan *vlan,
1506 struct netlink_ext_ack *extack)
1507 {
1508 struct b53_device *dev = ds->priv;
1509 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1510 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1511 struct b53_vlan *vl;
1512 int err;
1513
1514 err = b53_vlan_prepare(ds, port, vlan);
1515 if (err)
1516 return err;
1517
1518 vl = &dev->vlans[vlan->vid];
1519
1520 b53_get_vlan_entry(dev, vlan->vid, vl);
1521
1522 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1523 untagged = true;
1524
1525 vl->members |= BIT(port);
1526 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1527 vl->untag |= BIT(port);
1528 else
1529 vl->untag &= ~BIT(port);
1530
1531 b53_set_vlan_entry(dev, vlan->vid, vl);
1532 b53_fast_age_vlan(dev, vlan->vid);
1533
1534 if (pvid && !dsa_is_cpu_port(ds, port)) {
1535 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1536 vlan->vid);
1537 b53_fast_age_vlan(dev, vlan->vid);
1538 }
1539
1540 return 0;
1541 }
1542 EXPORT_SYMBOL(b53_vlan_add);
1543
b53_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1544 int b53_vlan_del(struct dsa_switch *ds, int port,
1545 const struct switchdev_obj_port_vlan *vlan)
1546 {
1547 struct b53_device *dev = ds->priv;
1548 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1549 struct b53_vlan *vl;
1550 u16 pvid;
1551
1552 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1553
1554 vl = &dev->vlans[vlan->vid];
1555
1556 b53_get_vlan_entry(dev, vlan->vid, vl);
1557
1558 vl->members &= ~BIT(port);
1559
1560 if (pvid == vlan->vid)
1561 pvid = b53_default_pvid(dev);
1562
1563 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1564 vl->untag &= ~(BIT(port));
1565
1566 b53_set_vlan_entry(dev, vlan->vid, vl);
1567 b53_fast_age_vlan(dev, vlan->vid);
1568
1569 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1570 b53_fast_age_vlan(dev, pvid);
1571
1572 return 0;
1573 }
1574 EXPORT_SYMBOL(b53_vlan_del);
1575
1576 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
b53_arl_op_wait(struct b53_device * dev)1577 static int b53_arl_op_wait(struct b53_device *dev)
1578 {
1579 unsigned int timeout = 10;
1580 u8 reg;
1581
1582 do {
1583 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1584 if (!(reg & ARLTBL_START_DONE))
1585 return 0;
1586
1587 usleep_range(1000, 2000);
1588 } while (timeout--);
1589
1590 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1591
1592 return -ETIMEDOUT;
1593 }
1594
b53_arl_rw_op(struct b53_device * dev,unsigned int op)1595 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1596 {
1597 u8 reg;
1598
1599 if (op > ARLTBL_RW)
1600 return -EINVAL;
1601
1602 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1603 reg |= ARLTBL_START_DONE;
1604 if (op)
1605 reg |= ARLTBL_RW;
1606 else
1607 reg &= ~ARLTBL_RW;
1608 if (dev->vlan_enabled)
1609 reg &= ~ARLTBL_IVL_SVL_SELECT;
1610 else
1611 reg |= ARLTBL_IVL_SVL_SELECT;
1612 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1613
1614 return b53_arl_op_wait(dev);
1615 }
1616
b53_arl_read(struct b53_device * dev,u64 mac,u16 vid,struct b53_arl_entry * ent,u8 * idx)1617 static int b53_arl_read(struct b53_device *dev, u64 mac,
1618 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1619 {
1620 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1621 unsigned int i;
1622 int ret;
1623
1624 ret = b53_arl_op_wait(dev);
1625 if (ret)
1626 return ret;
1627
1628 bitmap_zero(free_bins, dev->num_arl_bins);
1629
1630 /* Read the bins */
1631 for (i = 0; i < dev->num_arl_bins; i++) {
1632 u64 mac_vid;
1633 u32 fwd_entry;
1634
1635 b53_read64(dev, B53_ARLIO_PAGE,
1636 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1637 b53_read32(dev, B53_ARLIO_PAGE,
1638 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1639 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1640
1641 if (!(fwd_entry & ARLTBL_VALID)) {
1642 set_bit(i, free_bins);
1643 continue;
1644 }
1645 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1646 continue;
1647 if (dev->vlan_enabled &&
1648 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1649 continue;
1650 *idx = i;
1651 return 0;
1652 }
1653
1654 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1655 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1656 }
1657
b53_arl_op(struct b53_device * dev,int op,int port,const unsigned char * addr,u16 vid,bool is_valid)1658 static int b53_arl_op(struct b53_device *dev, int op, int port,
1659 const unsigned char *addr, u16 vid, bool is_valid)
1660 {
1661 struct b53_arl_entry ent;
1662 u32 fwd_entry;
1663 u64 mac, mac_vid = 0;
1664 u8 idx = 0;
1665 int ret;
1666
1667 /* Convert the array into a 64-bit MAC */
1668 mac = ether_addr_to_u64(addr);
1669
1670 /* Perform a read for the given MAC and VID */
1671 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1672 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1673
1674 /* Issue a read operation for this MAC */
1675 ret = b53_arl_rw_op(dev, 1);
1676 if (ret)
1677 return ret;
1678
1679 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1680
1681 /* If this is a read, just finish now */
1682 if (op)
1683 return ret;
1684
1685 switch (ret) {
1686 case -ETIMEDOUT:
1687 return ret;
1688 case -ENOSPC:
1689 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1690 addr, vid);
1691 return is_valid ? ret : 0;
1692 case -ENOENT:
1693 /* We could not find a matching MAC, so reset to a new entry */
1694 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1695 addr, vid, idx);
1696 fwd_entry = 0;
1697 break;
1698 default:
1699 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1700 addr, vid, idx);
1701 break;
1702 }
1703
1704 /* For multicast address, the port is a bitmask and the validity
1705 * is determined by having at least one port being still active
1706 */
1707 if (!is_multicast_ether_addr(addr)) {
1708 ent.port = port;
1709 ent.is_valid = is_valid;
1710 } else {
1711 if (is_valid)
1712 ent.port |= BIT(port);
1713 else
1714 ent.port &= ~BIT(port);
1715
1716 ent.is_valid = !!(ent.port);
1717 }
1718
1719 ent.vid = vid;
1720 ent.is_static = true;
1721 ent.is_age = false;
1722 memcpy(ent.mac, addr, ETH_ALEN);
1723 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1724
1725 b53_write64(dev, B53_ARLIO_PAGE,
1726 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1727 b53_write32(dev, B53_ARLIO_PAGE,
1728 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1729
1730 return b53_arl_rw_op(dev, 0);
1731 }
1732
b53_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1733 int b53_fdb_add(struct dsa_switch *ds, int port,
1734 const unsigned char *addr, u16 vid,
1735 struct dsa_db db)
1736 {
1737 struct b53_device *priv = ds->priv;
1738 int ret;
1739
1740 /* 5325 and 5365 require some more massaging, but could
1741 * be supported eventually
1742 */
1743 if (is5325(priv) || is5365(priv))
1744 return -EOPNOTSUPP;
1745
1746 mutex_lock(&priv->arl_mutex);
1747 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1748 mutex_unlock(&priv->arl_mutex);
1749
1750 return ret;
1751 }
1752 EXPORT_SYMBOL(b53_fdb_add);
1753
b53_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1754 int b53_fdb_del(struct dsa_switch *ds, int port,
1755 const unsigned char *addr, u16 vid,
1756 struct dsa_db db)
1757 {
1758 struct b53_device *priv = ds->priv;
1759 int ret;
1760
1761 mutex_lock(&priv->arl_mutex);
1762 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1763 mutex_unlock(&priv->arl_mutex);
1764
1765 return ret;
1766 }
1767 EXPORT_SYMBOL(b53_fdb_del);
1768
b53_arl_search_wait(struct b53_device * dev)1769 static int b53_arl_search_wait(struct b53_device *dev)
1770 {
1771 unsigned int timeout = 1000;
1772 u8 reg;
1773
1774 do {
1775 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1776 if (!(reg & ARL_SRCH_STDN))
1777 return 0;
1778
1779 if (reg & ARL_SRCH_VLID)
1780 return 0;
1781
1782 usleep_range(1000, 2000);
1783 } while (timeout--);
1784
1785 return -ETIMEDOUT;
1786 }
1787
b53_arl_search_rd(struct b53_device * dev,u8 idx,struct b53_arl_entry * ent)1788 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1789 struct b53_arl_entry *ent)
1790 {
1791 u64 mac_vid;
1792 u32 fwd_entry;
1793
1794 b53_read64(dev, B53_ARLIO_PAGE,
1795 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1796 b53_read32(dev, B53_ARLIO_PAGE,
1797 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1798 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1799 }
1800
b53_fdb_copy(int port,const struct b53_arl_entry * ent,dsa_fdb_dump_cb_t * cb,void * data)1801 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1802 dsa_fdb_dump_cb_t *cb, void *data)
1803 {
1804 if (!ent->is_valid)
1805 return 0;
1806
1807 if (port != ent->port)
1808 return 0;
1809
1810 return cb(ent->mac, ent->vid, ent->is_static, data);
1811 }
1812
b53_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1813 int b53_fdb_dump(struct dsa_switch *ds, int port,
1814 dsa_fdb_dump_cb_t *cb, void *data)
1815 {
1816 struct b53_device *priv = ds->priv;
1817 struct b53_arl_entry results[2];
1818 unsigned int count = 0;
1819 int ret;
1820 u8 reg;
1821
1822 mutex_lock(&priv->arl_mutex);
1823
1824 /* Start search operation */
1825 reg = ARL_SRCH_STDN;
1826 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1827
1828 do {
1829 ret = b53_arl_search_wait(priv);
1830 if (ret)
1831 break;
1832
1833 b53_arl_search_rd(priv, 0, &results[0]);
1834 ret = b53_fdb_copy(port, &results[0], cb, data);
1835 if (ret)
1836 break;
1837
1838 if (priv->num_arl_bins > 2) {
1839 b53_arl_search_rd(priv, 1, &results[1]);
1840 ret = b53_fdb_copy(port, &results[1], cb, data);
1841 if (ret)
1842 break;
1843
1844 if (!results[0].is_valid && !results[1].is_valid)
1845 break;
1846 }
1847
1848 } while (count++ < b53_max_arl_entries(priv) / 2);
1849
1850 mutex_unlock(&priv->arl_mutex);
1851
1852 return 0;
1853 }
1854 EXPORT_SYMBOL(b53_fdb_dump);
1855
b53_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1856 int b53_mdb_add(struct dsa_switch *ds, int port,
1857 const struct switchdev_obj_port_mdb *mdb,
1858 struct dsa_db db)
1859 {
1860 struct b53_device *priv = ds->priv;
1861 int ret;
1862
1863 /* 5325 and 5365 require some more massaging, but could
1864 * be supported eventually
1865 */
1866 if (is5325(priv) || is5365(priv))
1867 return -EOPNOTSUPP;
1868
1869 mutex_lock(&priv->arl_mutex);
1870 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1871 mutex_unlock(&priv->arl_mutex);
1872
1873 return ret;
1874 }
1875 EXPORT_SYMBOL(b53_mdb_add);
1876
b53_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1877 int b53_mdb_del(struct dsa_switch *ds, int port,
1878 const struct switchdev_obj_port_mdb *mdb,
1879 struct dsa_db db)
1880 {
1881 struct b53_device *priv = ds->priv;
1882 int ret;
1883
1884 mutex_lock(&priv->arl_mutex);
1885 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1886 mutex_unlock(&priv->arl_mutex);
1887 if (ret)
1888 dev_err(ds->dev, "failed to delete MDB entry\n");
1889
1890 return ret;
1891 }
1892 EXPORT_SYMBOL(b53_mdb_del);
1893
b53_br_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1894 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1895 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1896 {
1897 struct b53_device *dev = ds->priv;
1898 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1899 u16 pvlan, reg;
1900 unsigned int i;
1901
1902 /* On 7278, port 7 which connects to the ASP should only receive
1903 * traffic from matching CFP rules.
1904 */
1905 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1906 return -EINVAL;
1907
1908 /* Make this port leave the all VLANs join since we will have proper
1909 * VLAN entries from now on
1910 */
1911 if (is58xx(dev)) {
1912 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1913 reg &= ~BIT(port);
1914 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1915 reg &= ~BIT(cpu_port);
1916 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1917 }
1918
1919 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1920
1921 b53_for_each_port(dev, i) {
1922 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1923 continue;
1924
1925 /* Add this local port to the remote port VLAN control
1926 * membership and update the remote port bitmask
1927 */
1928 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1929 reg |= BIT(port);
1930 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1931 dev->ports[i].vlan_ctl_mask = reg;
1932
1933 pvlan |= BIT(i);
1934 }
1935
1936 /* Configure the local port VLAN control membership to include
1937 * remote ports and update the local port bitmask
1938 */
1939 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1940 dev->ports[port].vlan_ctl_mask = pvlan;
1941
1942 return 0;
1943 }
1944 EXPORT_SYMBOL(b53_br_join);
1945
b53_br_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1946 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1947 {
1948 struct b53_device *dev = ds->priv;
1949 struct b53_vlan *vl = &dev->vlans[0];
1950 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1951 unsigned int i;
1952 u16 pvlan, reg, pvid;
1953
1954 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1955
1956 b53_for_each_port(dev, i) {
1957 /* Don't touch the remaining ports */
1958 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1959 continue;
1960
1961 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1962 reg &= ~BIT(port);
1963 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1964 dev->ports[port].vlan_ctl_mask = reg;
1965
1966 /* Prevent self removal to preserve isolation */
1967 if (port != i)
1968 pvlan &= ~BIT(i);
1969 }
1970
1971 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1972 dev->ports[port].vlan_ctl_mask = pvlan;
1973
1974 pvid = b53_default_pvid(dev);
1975
1976 /* Make this port join all VLANs without VLAN entries */
1977 if (is58xx(dev)) {
1978 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1979 reg |= BIT(port);
1980 if (!(reg & BIT(cpu_port)))
1981 reg |= BIT(cpu_port);
1982 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1983 } else {
1984 b53_get_vlan_entry(dev, pvid, vl);
1985 vl->members |= BIT(port) | BIT(cpu_port);
1986 vl->untag |= BIT(port) | BIT(cpu_port);
1987 b53_set_vlan_entry(dev, pvid, vl);
1988 }
1989 }
1990 EXPORT_SYMBOL(b53_br_leave);
1991
b53_br_set_stp_state(struct dsa_switch * ds,int port,u8 state)1992 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1993 {
1994 struct b53_device *dev = ds->priv;
1995 u8 hw_state;
1996 u8 reg;
1997
1998 switch (state) {
1999 case BR_STATE_DISABLED:
2000 hw_state = PORT_CTRL_DIS_STATE;
2001 break;
2002 case BR_STATE_LISTENING:
2003 hw_state = PORT_CTRL_LISTEN_STATE;
2004 break;
2005 case BR_STATE_LEARNING:
2006 hw_state = PORT_CTRL_LEARN_STATE;
2007 break;
2008 case BR_STATE_FORWARDING:
2009 hw_state = PORT_CTRL_FWD_STATE;
2010 break;
2011 case BR_STATE_BLOCKING:
2012 hw_state = PORT_CTRL_BLOCK_STATE;
2013 break;
2014 default:
2015 dev_err(ds->dev, "invalid STP state: %d\n", state);
2016 return;
2017 }
2018
2019 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2020 reg &= ~PORT_CTRL_STP_STATE_MASK;
2021 reg |= hw_state;
2022 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2023 }
2024 EXPORT_SYMBOL(b53_br_set_stp_state);
2025
b53_br_fast_age(struct dsa_switch * ds,int port)2026 void b53_br_fast_age(struct dsa_switch *ds, int port)
2027 {
2028 struct b53_device *dev = ds->priv;
2029
2030 if (b53_fast_age_port(dev, port))
2031 dev_err(ds->dev, "fast ageing failed\n");
2032 }
2033 EXPORT_SYMBOL(b53_br_fast_age);
2034
b53_br_flags_pre(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2035 int b53_br_flags_pre(struct dsa_switch *ds, int port,
2036 struct switchdev_brport_flags flags,
2037 struct netlink_ext_ack *extack)
2038 {
2039 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2040 return -EINVAL;
2041
2042 return 0;
2043 }
2044 EXPORT_SYMBOL(b53_br_flags_pre);
2045
b53_br_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2046 int b53_br_flags(struct dsa_switch *ds, int port,
2047 struct switchdev_brport_flags flags,
2048 struct netlink_ext_ack *extack)
2049 {
2050 if (flags.mask & BR_FLOOD)
2051 b53_port_set_ucast_flood(ds->priv, port,
2052 !!(flags.val & BR_FLOOD));
2053 if (flags.mask & BR_MCAST_FLOOD)
2054 b53_port_set_mcast_flood(ds->priv, port,
2055 !!(flags.val & BR_MCAST_FLOOD));
2056 if (flags.mask & BR_LEARNING)
2057 b53_port_set_learning(ds->priv, port,
2058 !!(flags.val & BR_LEARNING));
2059
2060 return 0;
2061 }
2062 EXPORT_SYMBOL(b53_br_flags);
2063
b53_possible_cpu_port(struct dsa_switch * ds,int port)2064 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2065 {
2066 /* Broadcom switches will accept enabling Broadcom tags on the
2067 * following ports: 5, 7 and 8, any other port is not supported
2068 */
2069 switch (port) {
2070 case B53_CPU_PORT_25:
2071 case 7:
2072 case B53_CPU_PORT:
2073 return true;
2074 }
2075
2076 return false;
2077 }
2078
b53_can_enable_brcm_tags(struct dsa_switch * ds,int port,enum dsa_tag_protocol tag_protocol)2079 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2080 enum dsa_tag_protocol tag_protocol)
2081 {
2082 bool ret = b53_possible_cpu_port(ds, port);
2083
2084 if (!ret) {
2085 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2086 port);
2087 return ret;
2088 }
2089
2090 switch (tag_protocol) {
2091 case DSA_TAG_PROTO_BRCM:
2092 case DSA_TAG_PROTO_BRCM_PREPEND:
2093 dev_warn(ds->dev,
2094 "Port %d is stacked to Broadcom tag switch\n", port);
2095 ret = false;
2096 break;
2097 default:
2098 ret = true;
2099 break;
2100 }
2101
2102 return ret;
2103 }
2104
b53_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mprot)2105 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2106 enum dsa_tag_protocol mprot)
2107 {
2108 struct b53_device *dev = ds->priv;
2109
2110 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2111 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2112 goto out;
2113 }
2114
2115 /* Older models require a different 6 byte tag */
2116 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2117 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2118 goto out;
2119 }
2120
2121 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2122 * which requires us to use the prepended Broadcom tag type
2123 */
2124 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2125 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2126 goto out;
2127 }
2128
2129 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2130 out:
2131 return dev->tag_protocol;
2132 }
2133 EXPORT_SYMBOL(b53_get_tag_protocol);
2134
b53_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2135 int b53_mirror_add(struct dsa_switch *ds, int port,
2136 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2137 struct netlink_ext_ack *extack)
2138 {
2139 struct b53_device *dev = ds->priv;
2140 u16 reg, loc;
2141
2142 if (ingress)
2143 loc = B53_IG_MIR_CTL;
2144 else
2145 loc = B53_EG_MIR_CTL;
2146
2147 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2148 reg |= BIT(port);
2149 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2150
2151 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2152 reg &= ~CAP_PORT_MASK;
2153 reg |= mirror->to_local_port;
2154 reg |= MIRROR_EN;
2155 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2156
2157 return 0;
2158 }
2159 EXPORT_SYMBOL(b53_mirror_add);
2160
b53_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2161 void b53_mirror_del(struct dsa_switch *ds, int port,
2162 struct dsa_mall_mirror_tc_entry *mirror)
2163 {
2164 struct b53_device *dev = ds->priv;
2165 bool loc_disable = false, other_loc_disable = false;
2166 u16 reg, loc;
2167
2168 if (mirror->ingress)
2169 loc = B53_IG_MIR_CTL;
2170 else
2171 loc = B53_EG_MIR_CTL;
2172
2173 /* Update the desired ingress/egress register */
2174 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2175 reg &= ~BIT(port);
2176 if (!(reg & MIRROR_MASK))
2177 loc_disable = true;
2178 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2179
2180 /* Now look at the other one to know if we can disable mirroring
2181 * entirely
2182 */
2183 if (mirror->ingress)
2184 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2185 else
2186 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2187 if (!(reg & MIRROR_MASK))
2188 other_loc_disable = true;
2189
2190 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2191 /* Both no longer have ports, let's disable mirroring */
2192 if (loc_disable && other_loc_disable) {
2193 reg &= ~MIRROR_EN;
2194 reg &= ~mirror->to_local_port;
2195 }
2196 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2197 }
2198 EXPORT_SYMBOL(b53_mirror_del);
2199
b53_eee_enable_set(struct dsa_switch * ds,int port,bool enable)2200 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2201 {
2202 struct b53_device *dev = ds->priv;
2203 u16 reg;
2204
2205 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2206 if (enable)
2207 reg |= BIT(port);
2208 else
2209 reg &= ~BIT(port);
2210 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2211 }
2212 EXPORT_SYMBOL(b53_eee_enable_set);
2213
2214
2215 /* Returns 0 if EEE was not enabled, or 1 otherwise
2216 */
b53_eee_init(struct dsa_switch * ds,int port,struct phy_device * phy)2217 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2218 {
2219 int ret;
2220
2221 ret = phy_init_eee(phy, false);
2222 if (ret)
2223 return 0;
2224
2225 b53_eee_enable_set(ds, port, true);
2226
2227 return 1;
2228 }
2229 EXPORT_SYMBOL(b53_eee_init);
2230
b53_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2231 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2232 {
2233 struct b53_device *dev = ds->priv;
2234 struct ethtool_eee *p = &dev->ports[port].eee;
2235 u16 reg;
2236
2237 if (is5325(dev) || is5365(dev))
2238 return -EOPNOTSUPP;
2239
2240 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2241 e->eee_enabled = p->eee_enabled;
2242 e->eee_active = !!(reg & BIT(port));
2243
2244 return 0;
2245 }
2246 EXPORT_SYMBOL(b53_get_mac_eee);
2247
b53_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2248 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2249 {
2250 struct b53_device *dev = ds->priv;
2251 struct ethtool_eee *p = &dev->ports[port].eee;
2252
2253 if (is5325(dev) || is5365(dev))
2254 return -EOPNOTSUPP;
2255
2256 p->eee_enabled = e->eee_enabled;
2257 b53_eee_enable_set(ds, port, e->eee_enabled);
2258
2259 return 0;
2260 }
2261 EXPORT_SYMBOL(b53_set_mac_eee);
2262
b53_change_mtu(struct dsa_switch * ds,int port,int mtu)2263 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2264 {
2265 struct b53_device *dev = ds->priv;
2266 bool enable_jumbo;
2267 bool allow_10_100;
2268
2269 if (is5325(dev) || is5365(dev))
2270 return 0;
2271
2272 if (!dsa_is_cpu_port(ds, port))
2273 return 0;
2274
2275 enable_jumbo = (mtu > ETH_DATA_LEN);
2276 allow_10_100 = !is63xx(dev);
2277
2278 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2279 }
2280
b53_get_max_mtu(struct dsa_switch * ds,int port)2281 static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2282 {
2283 struct b53_device *dev = ds->priv;
2284
2285 if (is5325(dev) || is5365(dev))
2286 return B53_MAX_MTU_25;
2287
2288 return B53_MAX_MTU;
2289 }
2290
2291 static const struct dsa_switch_ops b53_switch_ops = {
2292 .get_tag_protocol = b53_get_tag_protocol,
2293 .setup = b53_setup,
2294 .teardown = b53_teardown,
2295 .get_strings = b53_get_strings,
2296 .get_ethtool_stats = b53_get_ethtool_stats,
2297 .get_sset_count = b53_get_sset_count,
2298 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2299 .phy_read = b53_phy_read16,
2300 .phy_write = b53_phy_write16,
2301 .adjust_link = b53_adjust_link,
2302 .phylink_get_caps = b53_phylink_get_caps,
2303 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2304 .phylink_mac_config = b53_phylink_mac_config,
2305 .phylink_mac_link_down = b53_phylink_mac_link_down,
2306 .phylink_mac_link_up = b53_phylink_mac_link_up,
2307 .port_enable = b53_enable_port,
2308 .port_disable = b53_disable_port,
2309 .get_mac_eee = b53_get_mac_eee,
2310 .set_mac_eee = b53_set_mac_eee,
2311 .port_bridge_join = b53_br_join,
2312 .port_bridge_leave = b53_br_leave,
2313 .port_pre_bridge_flags = b53_br_flags_pre,
2314 .port_bridge_flags = b53_br_flags,
2315 .port_stp_state_set = b53_br_set_stp_state,
2316 .port_fast_age = b53_br_fast_age,
2317 .port_vlan_filtering = b53_vlan_filtering,
2318 .port_vlan_add = b53_vlan_add,
2319 .port_vlan_del = b53_vlan_del,
2320 .port_fdb_dump = b53_fdb_dump,
2321 .port_fdb_add = b53_fdb_add,
2322 .port_fdb_del = b53_fdb_del,
2323 .port_mirror_add = b53_mirror_add,
2324 .port_mirror_del = b53_mirror_del,
2325 .port_mdb_add = b53_mdb_add,
2326 .port_mdb_del = b53_mdb_del,
2327 .port_max_mtu = b53_get_max_mtu,
2328 .port_change_mtu = b53_change_mtu,
2329 };
2330
2331 struct b53_chip_data {
2332 u32 chip_id;
2333 const char *dev_name;
2334 u16 vlans;
2335 u16 enabled_ports;
2336 u8 imp_port;
2337 u8 cpu_port;
2338 u8 vta_regs[3];
2339 u8 arl_bins;
2340 u16 arl_buckets;
2341 u8 duplex_reg;
2342 u8 jumbo_pm_reg;
2343 u8 jumbo_size_reg;
2344 };
2345
2346 #define B53_VTA_REGS \
2347 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2348 #define B53_VTA_REGS_9798 \
2349 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2350 #define B53_VTA_REGS_63XX \
2351 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2352
2353 static const struct b53_chip_data b53_switch_chips[] = {
2354 {
2355 .chip_id = BCM5325_DEVICE_ID,
2356 .dev_name = "BCM5325",
2357 .vlans = 16,
2358 .enabled_ports = 0x3f,
2359 .arl_bins = 2,
2360 .arl_buckets = 1024,
2361 .imp_port = 5,
2362 .duplex_reg = B53_DUPLEX_STAT_FE,
2363 },
2364 {
2365 .chip_id = BCM5365_DEVICE_ID,
2366 .dev_name = "BCM5365",
2367 .vlans = 256,
2368 .enabled_ports = 0x3f,
2369 .arl_bins = 2,
2370 .arl_buckets = 1024,
2371 .imp_port = 5,
2372 .duplex_reg = B53_DUPLEX_STAT_FE,
2373 },
2374 {
2375 .chip_id = BCM5389_DEVICE_ID,
2376 .dev_name = "BCM5389",
2377 .vlans = 4096,
2378 .enabled_ports = 0x11f,
2379 .arl_bins = 4,
2380 .arl_buckets = 1024,
2381 .imp_port = 8,
2382 .vta_regs = B53_VTA_REGS,
2383 .duplex_reg = B53_DUPLEX_STAT_GE,
2384 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2385 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2386 },
2387 {
2388 .chip_id = BCM5395_DEVICE_ID,
2389 .dev_name = "BCM5395",
2390 .vlans = 4096,
2391 .enabled_ports = 0x11f,
2392 .arl_bins = 4,
2393 .arl_buckets = 1024,
2394 .imp_port = 8,
2395 .vta_regs = B53_VTA_REGS,
2396 .duplex_reg = B53_DUPLEX_STAT_GE,
2397 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2398 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2399 },
2400 {
2401 .chip_id = BCM5397_DEVICE_ID,
2402 .dev_name = "BCM5397",
2403 .vlans = 4096,
2404 .enabled_ports = 0x11f,
2405 .arl_bins = 4,
2406 .arl_buckets = 1024,
2407 .imp_port = 8,
2408 .vta_regs = B53_VTA_REGS_9798,
2409 .duplex_reg = B53_DUPLEX_STAT_GE,
2410 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2411 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2412 },
2413 {
2414 .chip_id = BCM5398_DEVICE_ID,
2415 .dev_name = "BCM5398",
2416 .vlans = 4096,
2417 .enabled_ports = 0x17f,
2418 .arl_bins = 4,
2419 .arl_buckets = 1024,
2420 .imp_port = 8,
2421 .vta_regs = B53_VTA_REGS_9798,
2422 .duplex_reg = B53_DUPLEX_STAT_GE,
2423 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2424 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2425 },
2426 {
2427 .chip_id = BCM53115_DEVICE_ID,
2428 .dev_name = "BCM53115",
2429 .vlans = 4096,
2430 .enabled_ports = 0x11f,
2431 .arl_bins = 4,
2432 .arl_buckets = 1024,
2433 .vta_regs = B53_VTA_REGS,
2434 .imp_port = 8,
2435 .duplex_reg = B53_DUPLEX_STAT_GE,
2436 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2437 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2438 },
2439 {
2440 .chip_id = BCM53125_DEVICE_ID,
2441 .dev_name = "BCM53125",
2442 .vlans = 4096,
2443 .enabled_ports = 0x1ff,
2444 .arl_bins = 4,
2445 .arl_buckets = 1024,
2446 .imp_port = 8,
2447 .vta_regs = B53_VTA_REGS,
2448 .duplex_reg = B53_DUPLEX_STAT_GE,
2449 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2450 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2451 },
2452 {
2453 .chip_id = BCM53128_DEVICE_ID,
2454 .dev_name = "BCM53128",
2455 .vlans = 4096,
2456 .enabled_ports = 0x1ff,
2457 .arl_bins = 4,
2458 .arl_buckets = 1024,
2459 .imp_port = 8,
2460 .vta_regs = B53_VTA_REGS,
2461 .duplex_reg = B53_DUPLEX_STAT_GE,
2462 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2463 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2464 },
2465 {
2466 .chip_id = BCM63XX_DEVICE_ID,
2467 .dev_name = "BCM63xx",
2468 .vlans = 4096,
2469 .enabled_ports = 0, /* pdata must provide them */
2470 .arl_bins = 4,
2471 .arl_buckets = 1024,
2472 .imp_port = 8,
2473 .vta_regs = B53_VTA_REGS_63XX,
2474 .duplex_reg = B53_DUPLEX_STAT_63XX,
2475 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2476 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2477 },
2478 {
2479 .chip_id = BCM63268_DEVICE_ID,
2480 .dev_name = "BCM63268",
2481 .vlans = 4096,
2482 .enabled_ports = 0, /* pdata must provide them */
2483 .arl_bins = 4,
2484 .arl_buckets = 1024,
2485 .imp_port = 8,
2486 .vta_regs = B53_VTA_REGS_63XX,
2487 .duplex_reg = B53_DUPLEX_STAT_63XX,
2488 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2489 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2490 },
2491 {
2492 .chip_id = BCM53010_DEVICE_ID,
2493 .dev_name = "BCM53010",
2494 .vlans = 4096,
2495 .enabled_ports = 0x1bf,
2496 .arl_bins = 4,
2497 .arl_buckets = 1024,
2498 .imp_port = 8,
2499 .vta_regs = B53_VTA_REGS,
2500 .duplex_reg = B53_DUPLEX_STAT_GE,
2501 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2502 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2503 },
2504 {
2505 .chip_id = BCM53011_DEVICE_ID,
2506 .dev_name = "BCM53011",
2507 .vlans = 4096,
2508 .enabled_ports = 0x1bf,
2509 .arl_bins = 4,
2510 .arl_buckets = 1024,
2511 .imp_port = 8,
2512 .vta_regs = B53_VTA_REGS,
2513 .duplex_reg = B53_DUPLEX_STAT_GE,
2514 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2515 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2516 },
2517 {
2518 .chip_id = BCM53012_DEVICE_ID,
2519 .dev_name = "BCM53012",
2520 .vlans = 4096,
2521 .enabled_ports = 0x1bf,
2522 .arl_bins = 4,
2523 .arl_buckets = 1024,
2524 .imp_port = 8,
2525 .vta_regs = B53_VTA_REGS,
2526 .duplex_reg = B53_DUPLEX_STAT_GE,
2527 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2528 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2529 },
2530 {
2531 .chip_id = BCM53018_DEVICE_ID,
2532 .dev_name = "BCM53018",
2533 .vlans = 4096,
2534 .enabled_ports = 0x1bf,
2535 .arl_bins = 4,
2536 .arl_buckets = 1024,
2537 .imp_port = 8,
2538 .vta_regs = B53_VTA_REGS,
2539 .duplex_reg = B53_DUPLEX_STAT_GE,
2540 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2541 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2542 },
2543 {
2544 .chip_id = BCM53019_DEVICE_ID,
2545 .dev_name = "BCM53019",
2546 .vlans = 4096,
2547 .enabled_ports = 0x1bf,
2548 .arl_bins = 4,
2549 .arl_buckets = 1024,
2550 .imp_port = 8,
2551 .vta_regs = B53_VTA_REGS,
2552 .duplex_reg = B53_DUPLEX_STAT_GE,
2553 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2554 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2555 },
2556 {
2557 .chip_id = BCM58XX_DEVICE_ID,
2558 .dev_name = "BCM585xx/586xx/88312",
2559 .vlans = 4096,
2560 .enabled_ports = 0x1ff,
2561 .arl_bins = 4,
2562 .arl_buckets = 1024,
2563 .imp_port = 8,
2564 .vta_regs = B53_VTA_REGS,
2565 .duplex_reg = B53_DUPLEX_STAT_GE,
2566 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2567 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2568 },
2569 {
2570 .chip_id = BCM583XX_DEVICE_ID,
2571 .dev_name = "BCM583xx/11360",
2572 .vlans = 4096,
2573 .enabled_ports = 0x103,
2574 .arl_bins = 4,
2575 .arl_buckets = 1024,
2576 .imp_port = 8,
2577 .vta_regs = B53_VTA_REGS,
2578 .duplex_reg = B53_DUPLEX_STAT_GE,
2579 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2580 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2581 },
2582 /* Starfighter 2 */
2583 {
2584 .chip_id = BCM4908_DEVICE_ID,
2585 .dev_name = "BCM4908",
2586 .vlans = 4096,
2587 .enabled_ports = 0x1bf,
2588 .arl_bins = 4,
2589 .arl_buckets = 256,
2590 .imp_port = 8,
2591 .vta_regs = B53_VTA_REGS,
2592 .duplex_reg = B53_DUPLEX_STAT_GE,
2593 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2594 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2595 },
2596 {
2597 .chip_id = BCM7445_DEVICE_ID,
2598 .dev_name = "BCM7445",
2599 .vlans = 4096,
2600 .enabled_ports = 0x1ff,
2601 .arl_bins = 4,
2602 .arl_buckets = 1024,
2603 .imp_port = 8,
2604 .vta_regs = B53_VTA_REGS,
2605 .duplex_reg = B53_DUPLEX_STAT_GE,
2606 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2607 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2608 },
2609 {
2610 .chip_id = BCM7278_DEVICE_ID,
2611 .dev_name = "BCM7278",
2612 .vlans = 4096,
2613 .enabled_ports = 0x1ff,
2614 .arl_bins = 4,
2615 .arl_buckets = 256,
2616 .imp_port = 8,
2617 .vta_regs = B53_VTA_REGS,
2618 .duplex_reg = B53_DUPLEX_STAT_GE,
2619 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2620 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2621 },
2622 {
2623 .chip_id = BCM53134_DEVICE_ID,
2624 .dev_name = "BCM53134",
2625 .vlans = 4096,
2626 .enabled_ports = 0x12f,
2627 .imp_port = 8,
2628 .cpu_port = B53_CPU_PORT,
2629 .vta_regs = B53_VTA_REGS,
2630 .arl_bins = 4,
2631 .arl_buckets = 1024,
2632 .duplex_reg = B53_DUPLEX_STAT_GE,
2633 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2634 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2635 },
2636 };
2637
b53_switch_init(struct b53_device * dev)2638 static int b53_switch_init(struct b53_device *dev)
2639 {
2640 unsigned int i;
2641 int ret;
2642
2643 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2644 const struct b53_chip_data *chip = &b53_switch_chips[i];
2645
2646 if (chip->chip_id == dev->chip_id) {
2647 if (!dev->enabled_ports)
2648 dev->enabled_ports = chip->enabled_ports;
2649 dev->name = chip->dev_name;
2650 dev->duplex_reg = chip->duplex_reg;
2651 dev->vta_regs[0] = chip->vta_regs[0];
2652 dev->vta_regs[1] = chip->vta_regs[1];
2653 dev->vta_regs[2] = chip->vta_regs[2];
2654 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2655 dev->imp_port = chip->imp_port;
2656 dev->num_vlans = chip->vlans;
2657 dev->num_arl_bins = chip->arl_bins;
2658 dev->num_arl_buckets = chip->arl_buckets;
2659 break;
2660 }
2661 }
2662
2663 /* check which BCM5325x version we have */
2664 if (is5325(dev)) {
2665 u8 vc4;
2666
2667 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2668
2669 /* check reserved bits */
2670 switch (vc4 & 3) {
2671 case 1:
2672 /* BCM5325E */
2673 break;
2674 case 3:
2675 /* BCM5325F - do not use port 4 */
2676 dev->enabled_ports &= ~BIT(4);
2677 break;
2678 default:
2679 /* On the BCM47XX SoCs this is the supported internal switch.*/
2680 #ifndef CONFIG_BCM47XX
2681 /* BCM5325M */
2682 return -EINVAL;
2683 #else
2684 break;
2685 #endif
2686 }
2687 }
2688
2689 dev->num_ports = fls(dev->enabled_ports);
2690
2691 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2692
2693 /* Include non standard CPU port built-in PHYs to be probed */
2694 if (is539x(dev) || is531x5(dev)) {
2695 for (i = 0; i < dev->num_ports; i++) {
2696 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2697 !b53_possible_cpu_port(dev->ds, i))
2698 dev->ds->phys_mii_mask |= BIT(i);
2699 }
2700 }
2701
2702 dev->ports = devm_kcalloc(dev->dev,
2703 dev->num_ports, sizeof(struct b53_port),
2704 GFP_KERNEL);
2705 if (!dev->ports)
2706 return -ENOMEM;
2707
2708 dev->vlans = devm_kcalloc(dev->dev,
2709 dev->num_vlans, sizeof(struct b53_vlan),
2710 GFP_KERNEL);
2711 if (!dev->vlans)
2712 return -ENOMEM;
2713
2714 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2715 if (dev->reset_gpio >= 0) {
2716 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2717 GPIOF_OUT_INIT_HIGH, "robo_reset");
2718 if (ret)
2719 return ret;
2720 }
2721
2722 return 0;
2723 }
2724
b53_switch_alloc(struct device * base,const struct b53_io_ops * ops,void * priv)2725 struct b53_device *b53_switch_alloc(struct device *base,
2726 const struct b53_io_ops *ops,
2727 void *priv)
2728 {
2729 struct dsa_switch *ds;
2730 struct b53_device *dev;
2731
2732 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2733 if (!ds)
2734 return NULL;
2735
2736 ds->dev = base;
2737
2738 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2739 if (!dev)
2740 return NULL;
2741
2742 ds->priv = dev;
2743 dev->dev = base;
2744
2745 dev->ds = ds;
2746 dev->priv = priv;
2747 dev->ops = ops;
2748 ds->ops = &b53_switch_ops;
2749 dev->vlan_enabled = true;
2750 /* Let DSA handle the case were multiple bridges span the same switch
2751 * device and different VLAN awareness settings are requested, which
2752 * would be breaking filtering semantics for any of the other bridge
2753 * devices. (not hardware supported)
2754 */
2755 ds->vlan_filtering_is_global = true;
2756
2757 mutex_init(&dev->reg_mutex);
2758 mutex_init(&dev->stats_mutex);
2759 mutex_init(&dev->arl_mutex);
2760
2761 return dev;
2762 }
2763 EXPORT_SYMBOL(b53_switch_alloc);
2764
b53_switch_detect(struct b53_device * dev)2765 int b53_switch_detect(struct b53_device *dev)
2766 {
2767 u32 id32;
2768 u16 tmp;
2769 u8 id8;
2770 int ret;
2771
2772 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2773 if (ret)
2774 return ret;
2775
2776 switch (id8) {
2777 case 0:
2778 /* BCM5325 and BCM5365 do not have this register so reads
2779 * return 0. But the read operation did succeed, so assume this
2780 * is one of them.
2781 *
2782 * Next check if we can write to the 5325's VTA register; for
2783 * 5365 it is read only.
2784 */
2785 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2786 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2787
2788 if (tmp == 0xf)
2789 dev->chip_id = BCM5325_DEVICE_ID;
2790 else
2791 dev->chip_id = BCM5365_DEVICE_ID;
2792 break;
2793 case BCM5389_DEVICE_ID:
2794 case BCM5395_DEVICE_ID:
2795 case BCM5397_DEVICE_ID:
2796 case BCM5398_DEVICE_ID:
2797 dev->chip_id = id8;
2798 break;
2799 default:
2800 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2801 if (ret)
2802 return ret;
2803
2804 switch (id32) {
2805 case BCM53115_DEVICE_ID:
2806 case BCM53125_DEVICE_ID:
2807 case BCM53128_DEVICE_ID:
2808 case BCM53010_DEVICE_ID:
2809 case BCM53011_DEVICE_ID:
2810 case BCM53012_DEVICE_ID:
2811 case BCM53018_DEVICE_ID:
2812 case BCM53019_DEVICE_ID:
2813 case BCM53134_DEVICE_ID:
2814 dev->chip_id = id32;
2815 break;
2816 default:
2817 dev_err(dev->dev,
2818 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2819 id8, id32);
2820 return -ENODEV;
2821 }
2822 }
2823
2824 if (dev->chip_id == BCM5325_DEVICE_ID)
2825 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2826 &dev->core_rev);
2827 else
2828 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2829 &dev->core_rev);
2830 }
2831 EXPORT_SYMBOL(b53_switch_detect);
2832
b53_switch_register(struct b53_device * dev)2833 int b53_switch_register(struct b53_device *dev)
2834 {
2835 int ret;
2836
2837 if (dev->pdata) {
2838 dev->chip_id = dev->pdata->chip_id;
2839 dev->enabled_ports = dev->pdata->enabled_ports;
2840 }
2841
2842 if (!dev->chip_id && b53_switch_detect(dev))
2843 return -EINVAL;
2844
2845 ret = b53_switch_init(dev);
2846 if (ret)
2847 return ret;
2848
2849 dev_info(dev->dev, "found switch: %s, rev %i\n",
2850 dev->name, dev->core_rev);
2851
2852 return dsa_register_switch(dev->ds);
2853 }
2854 EXPORT_SYMBOL(b53_switch_register);
2855
2856 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2857 MODULE_DESCRIPTION("B53 switch library");
2858 MODULE_LICENSE("Dual BSD/GPL");
2859