1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2023 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <linux/irq_poll.h> 24 #include <linux/cpufreq.h> 25 26 #if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS) 27 #define CONFIG_SCSI_LPFC_DEBUG_FS 28 #endif 29 30 #define LPFC_ACTIVE_MBOX_WAIT_CNT 100 31 #define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000 32 #define LPFC_XRI_EXCH_BUSY_WAIT_T1 10 33 #define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000 34 #define LPFC_RPI_LOW_WATER_MARK 10 35 36 #define LPFC_UNREG_FCF 1 37 #define LPFC_SKIP_UNREG_FCF 0 38 39 /* Amount of time in seconds for waiting FCF rediscovery to complete */ 40 #define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */ 41 42 /* Number of SGL entries can be posted in a 4KB nonembedded mbox command */ 43 #define LPFC_NEMBED_MBOX_SGL_CNT 254 44 45 /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */ 46 #define LPFC_HBA_HDWQ_MIN 0 47 #define LPFC_HBA_HDWQ_MAX 256 48 #define LPFC_HBA_HDWQ_DEF LPFC_HBA_HDWQ_MIN 49 50 /* irq_chann range, values */ 51 #define LPFC_IRQ_CHANN_MIN 0 52 #define LPFC_IRQ_CHANN_MAX 256 53 #define LPFC_IRQ_CHANN_DEF LPFC_IRQ_CHANN_MIN 54 55 /* FCP MQ queue count limiting */ 56 #define LPFC_FCP_MQ_THRESHOLD_MIN 0 57 #define LPFC_FCP_MQ_THRESHOLD_MAX 256 58 #define LPFC_FCP_MQ_THRESHOLD_DEF 8 59 60 /* 61 * Provide the default FCF Record attributes used by the driver 62 * when nonFIP mode is configured and there is no other default 63 * FCF Record attributes. 64 */ 65 #define LPFC_FCOE_FCF_DEF_INDEX 0 66 #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF 67 #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF 68 69 #define LPFC_FCOE_NULL_VID 0xFFF 70 #define LPFC_FCOE_IGNORE_VID 0xFFFF 71 72 /* First 3 bytes of default FCF MAC is specified by FC_MAP */ 73 #define LPFC_FCOE_FCF_MAC3 0xFF 74 #define LPFC_FCOE_FCF_MAC4 0xFF 75 #define LPFC_FCOE_FCF_MAC5 0xFE 76 #define LPFC_FCOE_FCF_MAP0 0x0E 77 #define LPFC_FCOE_FCF_MAP1 0xFC 78 #define LPFC_FCOE_FCF_MAP2 0x00 79 #define LPFC_FCOE_MAX_RCV_SIZE 0x800 80 #define LPFC_FCOE_FKA_ADV_PER 0 81 #define LPFC_FCOE_FIP_PRIORITY 0x80 82 83 #define sli4_sid_from_fc_hdr(fc_hdr) \ 84 ((fc_hdr)->fh_s_id[0] << 16 | \ 85 (fc_hdr)->fh_s_id[1] << 8 | \ 86 (fc_hdr)->fh_s_id[2]) 87 88 #define sli4_did_from_fc_hdr(fc_hdr) \ 89 ((fc_hdr)->fh_d_id[0] << 16 | \ 90 (fc_hdr)->fh_d_id[1] << 8 | \ 91 (fc_hdr)->fh_d_id[2]) 92 93 #define sli4_fctl_from_fc_hdr(fc_hdr) \ 94 ((fc_hdr)->fh_f_ctl[0] << 16 | \ 95 (fc_hdr)->fh_f_ctl[1] << 8 | \ 96 (fc_hdr)->fh_f_ctl[2]) 97 98 #define sli4_type_from_fc_hdr(fc_hdr) \ 99 ((fc_hdr)->fh_type) 100 101 #define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000 102 103 #define INT_FW_UPGRADE 0 104 #define RUN_FW_UPGRADE 1 105 106 enum lpfc_sli4_queue_type { 107 LPFC_EQ, 108 LPFC_GCQ, 109 LPFC_MCQ, 110 LPFC_WCQ, 111 LPFC_RCQ, 112 LPFC_MQ, 113 LPFC_WQ, 114 LPFC_HRQ, 115 LPFC_DRQ 116 }; 117 118 /* The queue sub-type defines the functional purpose of the queue */ 119 enum lpfc_sli4_queue_subtype { 120 LPFC_NONE, 121 LPFC_MBOX, 122 LPFC_IO, 123 LPFC_ELS, 124 LPFC_NVMET, 125 LPFC_NVME_LS, 126 LPFC_USOL 127 }; 128 129 /* RQ buffer list */ 130 struct lpfc_rqb { 131 uint16_t entry_count; /* Current number of RQ slots */ 132 uint16_t buffer_count; /* Current number of buffers posted */ 133 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */ 134 /* Callback for HBQ buffer allocation */ 135 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *); 136 /* Callback for HBQ buffer free */ 137 void (*rqb_free_buffer)(struct lpfc_hba *, 138 struct rqb_dmabuf *); 139 }; 140 141 enum lpfc_poll_mode { 142 LPFC_QUEUE_WORK, 143 LPFC_THREADED_IRQ, 144 }; 145 146 struct lpfc_idle_stat { 147 u64 prev_idle; 148 u64 prev_wall; 149 }; 150 151 struct lpfc_queue { 152 struct list_head list; 153 struct list_head wq_list; 154 155 /* 156 * If interrupts are in effect on _all_ the eq's the footprint 157 * of polling code is zero (except mode). This memory is chec- 158 * ked for every io to see if the io needs to be polled and 159 * while completion to check if the eq's needs to be rearmed. 160 * Keep in same cacheline as the queue ptr to avoid cpu fetch 161 * stalls. Using 1B memory will leave us with 7B hole. Fill 162 * it with other frequently used members. 163 */ 164 uint16_t last_cpu; /* most recent cpu */ 165 uint16_t hdwq; 166 uint8_t qe_valid; 167 uint8_t mode; /* interrupt or polling */ 168 #define LPFC_EQ_INTERRUPT 0 169 #define LPFC_EQ_POLL 1 170 171 struct list_head wqfull_list; 172 enum lpfc_sli4_queue_type type; 173 enum lpfc_sli4_queue_subtype subtype; 174 struct lpfc_hba *phba; 175 struct list_head child_list; 176 struct list_head page_list; 177 struct list_head sgl_list; 178 struct list_head cpu_list; 179 uint32_t entry_count; /* Number of entries to support on the queue */ 180 uint32_t entry_size; /* Size of each queue entry. */ 181 uint32_t entry_cnt_per_pg; 182 uint32_t notify_interval; /* Queue Notification Interval 183 * For chip->host queues (EQ, CQ, RQ): 184 * specifies the interval (number of 185 * entries) where the doorbell is rung to 186 * notify the chip of entry consumption. 187 * For host->chip queues (WQ): 188 * specifies the interval (number of 189 * entries) where consumption CQE is 190 * requested to indicate WQ entries 191 * consumed by the chip. 192 * Not used on an MQ. 193 */ 194 #define LPFC_EQ_NOTIFY_INTRVL 16 195 #define LPFC_CQ_NOTIFY_INTRVL 16 196 #define LPFC_WQ_NOTIFY_INTRVL 16 197 #define LPFC_RQ_NOTIFY_INTRVL 16 198 uint32_t max_proc_limit; /* Queue Processing Limit 199 * For chip->host queues (EQ, CQ): 200 * specifies the maximum number of 201 * entries to be consumed in one 202 * processing iteration sequence. Queue 203 * will be rearmed after each iteration. 204 * Not used on an MQ, RQ or WQ. 205 */ 206 #define LPFC_EQ_MAX_PROC_LIMIT 256 207 #define LPFC_CQ_MIN_PROC_LIMIT 64 208 #define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096 209 #define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024 210 #define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64 211 #define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT 212 #define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT 213 uint32_t queue_claimed; /* indicates queue is being processed */ 214 uint32_t queue_id; /* Queue ID assigned by the hardware */ 215 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */ 216 uint32_t host_index; /* The host's index for putting or getting */ 217 uint32_t hba_index; /* The last known hba index for get or put */ 218 uint32_t q_mode; 219 220 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */ 221 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */ 222 223 uint16_t page_count; /* Number of pages allocated for this queue */ 224 uint16_t page_size; /* size of page allocated for this queue */ 225 #define LPFC_EXPANDED_PAGE_SIZE 16384 226 #define LPFC_DEFAULT_PAGE_SIZE 4096 227 uint16_t chann; /* Hardware Queue association WQ/CQ */ 228 /* CPU affinity for EQ */ 229 #define LPFC_FIND_BY_EQ 0 230 #define LPFC_FIND_BY_HDWQ 1 231 uint8_t db_format; 232 #define LPFC_DB_RING_FORMAT 0x01 233 #define LPFC_DB_LIST_FORMAT 0x02 234 uint8_t q_flag; 235 #define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */ 236 #define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */ 237 #define HBA_EQ_DELAY_CHK 0x2 /* EQ is a candidate for coalescing */ 238 #define LPFC_NVMET_CQ_NOTIFY 4 239 void __iomem *db_regaddr; 240 uint16_t dpp_enable; 241 uint16_t dpp_id; 242 void __iomem *dpp_regaddr; 243 244 /* For q stats */ 245 uint32_t q_cnt_1; 246 uint32_t q_cnt_2; 247 uint32_t q_cnt_3; 248 uint64_t q_cnt_4; 249 /* defines for EQ stats */ 250 #define EQ_max_eqe q_cnt_1 251 #define EQ_no_entry q_cnt_2 252 #define EQ_cqe_cnt q_cnt_3 253 #define EQ_processed q_cnt_4 254 255 /* defines for CQ stats */ 256 #define CQ_mbox q_cnt_1 257 #define CQ_max_cqe q_cnt_1 258 #define CQ_release_wqe q_cnt_2 259 #define CQ_xri_aborted q_cnt_3 260 #define CQ_wq q_cnt_4 261 262 /* defines for WQ stats */ 263 #define WQ_overflow q_cnt_1 264 #define WQ_posted q_cnt_4 265 266 /* defines for RQ stats */ 267 #define RQ_no_posted_buf q_cnt_1 268 #define RQ_no_buf_found q_cnt_2 269 #define RQ_buf_posted q_cnt_3 270 #define RQ_rcv_buf q_cnt_4 271 272 struct work_struct irqwork; 273 struct work_struct spwork; 274 struct delayed_work sched_irqwork; 275 struct delayed_work sched_spwork; 276 277 uint64_t isr_timestamp; 278 struct lpfc_queue *assoc_qp; 279 struct list_head _poll_list; 280 void **q_pgs; /* array to index entries per page */ 281 282 enum lpfc_poll_mode poll_mode; 283 }; 284 285 struct lpfc_sli4_link { 286 uint32_t speed; 287 uint8_t duplex; 288 uint8_t status; 289 uint8_t type; 290 uint8_t number; 291 uint8_t fault; 292 uint8_t link_status; 293 uint16_t topology; 294 uint32_t logical_speed; 295 }; 296 297 struct lpfc_fcf_rec { 298 uint8_t fabric_name[8]; 299 uint8_t switch_name[8]; 300 uint8_t mac_addr[6]; 301 uint16_t fcf_indx; 302 uint32_t priority; 303 uint16_t vlan_id; 304 uint32_t addr_mode; 305 uint32_t flag; 306 #define BOOT_ENABLE 0x01 307 #define RECORD_VALID 0x02 308 }; 309 310 struct lpfc_fcf_pri_rec { 311 uint16_t fcf_index; 312 #define LPFC_FCF_ON_PRI_LIST 0x0001 313 #define LPFC_FCF_FLOGI_FAILED 0x0002 314 uint16_t flag; 315 uint32_t priority; 316 }; 317 318 struct lpfc_fcf_pri { 319 struct list_head list; 320 struct lpfc_fcf_pri_rec fcf_rec; 321 }; 322 323 /* 324 * Maximum FCF table index, it is for driver internal book keeping, it 325 * just needs to be no less than the supported HBA's FCF table size. 326 */ 327 #define LPFC_SLI4_FCF_TBL_INDX_MAX 32 328 329 struct lpfc_fcf { 330 uint16_t fcfi; 331 uint32_t fcf_flag; 332 #define FCF_AVAILABLE 0x01 /* FCF available for discovery */ 333 #define FCF_REGISTERED 0x02 /* FCF registered with FW */ 334 #define FCF_SCAN_DONE 0x04 /* FCF table scan done */ 335 #define FCF_IN_USE 0x08 /* Atleast one discovery completed */ 336 #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */ 337 #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */ 338 #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */ 339 #define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC) 340 #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */ 341 #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */ 342 #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */ 343 #define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT) 344 uint16_t fcf_redisc_attempted; 345 uint32_t addr_mode; 346 uint32_t eligible_fcf_cnt; 347 struct lpfc_fcf_rec current_rec; 348 struct lpfc_fcf_rec failover_rec; 349 struct list_head fcf_pri_list; 350 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX]; 351 uint32_t current_fcf_scan_pri; 352 struct timer_list redisc_wait; 353 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */ 354 }; 355 356 357 #define LPFC_REGION23_SIGNATURE "RG23" 358 #define LPFC_REGION23_VERSION 1 359 #define LPFC_REGION23_LAST_REC 0xff 360 #define DRIVER_SPECIFIC_TYPE 0xA2 361 #define LINUX_DRIVER_ID 0x20 362 #define PORT_STE_TYPE 0x1 363 364 struct lpfc_fip_param_hdr { 365 uint8_t type; 366 #define FCOE_PARAM_TYPE 0xA0 367 uint8_t length; 368 #define FCOE_PARAM_LENGTH 2 369 uint8_t parm_version; 370 #define FIPP_VERSION 0x01 371 uint8_t parm_flags; 372 #define lpfc_fip_param_hdr_fipp_mode_SHIFT 6 373 #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3 374 #define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags 375 #define FIPP_MODE_ON 0x1 376 #define FIPP_MODE_OFF 0x0 377 #define FIPP_VLAN_VALID 0x1 378 }; 379 380 struct lpfc_fcoe_params { 381 uint8_t fc_map[3]; 382 uint8_t reserved1; 383 uint16_t vlan_tag; 384 uint8_t reserved[2]; 385 }; 386 387 struct lpfc_fcf_conn_hdr { 388 uint8_t type; 389 #define FCOE_CONN_TBL_TYPE 0xA1 390 uint8_t length; /* words */ 391 uint8_t reserved[2]; 392 }; 393 394 struct lpfc_fcf_conn_rec { 395 uint16_t flags; 396 #define FCFCNCT_VALID 0x0001 397 #define FCFCNCT_BOOT 0x0002 398 #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */ 399 #define FCFCNCT_FBNM_VALID 0x0008 400 #define FCFCNCT_SWNM_VALID 0x0010 401 #define FCFCNCT_VLAN_VALID 0x0020 402 #define FCFCNCT_AM_VALID 0x0040 403 #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */ 404 #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */ 405 406 uint16_t vlan_tag; 407 uint8_t fabric_name[8]; 408 uint8_t switch_name[8]; 409 }; 410 411 struct lpfc_fcf_conn_entry { 412 struct list_head list; 413 struct lpfc_fcf_conn_rec conn_rec; 414 }; 415 416 /* 417 * Define the host's bootstrap mailbox. This structure contains 418 * the member attributes needed to create, use, and destroy the 419 * bootstrap mailbox region. 420 * 421 * The macro definitions for the bmbx data structure are defined 422 * in lpfc_hw4.h with the register definition. 423 */ 424 struct lpfc_bmbx { 425 struct lpfc_dmabuf *dmabuf; 426 struct dma_address dma_address; 427 void *avirt; 428 dma_addr_t aphys; 429 uint32_t bmbx_size; 430 }; 431 432 #define LPFC_EQE_SIZE LPFC_EQE_SIZE_4 433 434 #define LPFC_EQE_SIZE_4B 4 435 #define LPFC_EQE_SIZE_16B 16 436 #define LPFC_CQE_SIZE 16 437 #define LPFC_WQE_SIZE 64 438 #define LPFC_WQE128_SIZE 128 439 #define LPFC_MQE_SIZE 256 440 #define LPFC_RQE_SIZE 8 441 442 #define LPFC_EQE_DEF_COUNT 1024 443 #define LPFC_CQE_DEF_COUNT 1024 444 #define LPFC_CQE_EXP_COUNT 4096 445 #define LPFC_WQE_DEF_COUNT 256 446 #define LPFC_WQE_EXP_COUNT 1024 447 #define LPFC_MQE_DEF_COUNT 16 448 #define LPFC_RQE_DEF_COUNT 512 449 450 #define LPFC_QUEUE_NOARM false 451 #define LPFC_QUEUE_REARM true 452 453 454 /* 455 * SLI4 CT field defines 456 */ 457 #define SLI4_CT_RPI 0 458 #define SLI4_CT_VPI 1 459 #define SLI4_CT_VFI 2 460 #define SLI4_CT_FCFI 3 461 462 /* 463 * SLI4 specific data structures 464 */ 465 struct lpfc_max_cfg_param { 466 uint16_t max_xri; 467 uint16_t xri_base; 468 uint16_t xri_used; 469 uint16_t max_rpi; 470 uint16_t rpi_base; 471 uint16_t rpi_used; 472 uint16_t max_vpi; 473 uint16_t vpi_base; 474 uint16_t vpi_used; 475 uint16_t max_vfi; 476 uint16_t vfi_base; 477 uint16_t vfi_used; 478 uint16_t max_fcfi; 479 uint16_t fcfi_used; 480 uint16_t max_eq; 481 uint16_t max_rq; 482 uint16_t max_cq; 483 uint16_t max_wq; 484 }; 485 486 struct lpfc_hba; 487 /* SLI4 HBA multi-fcp queue handler struct */ 488 #define LPFC_SLI4_HANDLER_NAME_SZ 16 489 struct lpfc_hba_eq_hdl { 490 uint32_t idx; 491 int irq; 492 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ]; 493 struct lpfc_hba *phba; 494 struct lpfc_queue *eq; 495 struct cpumask aff_mask; 496 }; 497 498 #define lpfc_get_eq_hdl(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx]) 499 #define lpfc_get_aff_mask(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx].aff_mask) 500 #define lpfc_get_irq(eqidx) (phba->sli4_hba.hba_eq_hdl[eqidx].irq) 501 502 /*BB Credit recovery value*/ 503 struct lpfc_bbscn_params { 504 uint32_t word0; 505 #define lpfc_bbscn_min_SHIFT 0 506 #define lpfc_bbscn_min_MASK 0x0000000F 507 #define lpfc_bbscn_min_WORD word0 508 #define lpfc_bbscn_max_SHIFT 4 509 #define lpfc_bbscn_max_MASK 0x0000000F 510 #define lpfc_bbscn_max_WORD word0 511 #define lpfc_bbscn_def_SHIFT 8 512 #define lpfc_bbscn_def_MASK 0x0000000F 513 #define lpfc_bbscn_def_WORD word0 514 }; 515 516 /* Port Capabilities for SLI4 Parameters */ 517 struct lpfc_pc_sli4_params { 518 uint32_t supported; 519 uint32_t if_type; 520 uint32_t sli_rev; 521 uint32_t sli_family; 522 uint32_t featurelevel_1; 523 uint32_t featurelevel_2; 524 uint32_t proto_types; 525 #define LPFC_SLI4_PROTO_FCOE 0x0000001 526 #define LPFC_SLI4_PROTO_FC 0x0000002 527 #define LPFC_SLI4_PROTO_NIC 0x0000004 528 #define LPFC_SLI4_PROTO_ISCSI 0x0000008 529 #define LPFC_SLI4_PROTO_RDMA 0x0000010 530 uint32_t sge_supp_len; 531 uint32_t if_page_sz; 532 uint32_t rq_db_window; 533 uint32_t loopbk_scope; 534 uint32_t oas_supported; 535 uint32_t eq_pages_max; 536 uint32_t eqe_size; 537 uint32_t cq_pages_max; 538 uint32_t cqe_size; 539 uint32_t mq_pages_max; 540 uint32_t mqe_size; 541 uint32_t mq_elem_cnt; 542 uint32_t wq_pages_max; 543 uint32_t wqe_size; 544 uint32_t rq_pages_max; 545 uint32_t rqe_size; 546 uint32_t hdr_pages_max; 547 uint32_t hdr_size; 548 uint32_t hdr_pp_align; 549 uint32_t sgl_pages_max; 550 uint32_t sgl_pp_align; 551 uint32_t mib_size; 552 uint16_t mi_ver; 553 #define LPFC_MIB1_SUPPORT 1 554 #define LPFC_MIB2_SUPPORT 2 555 #define LPFC_MIB3_SUPPORT 3 556 uint16_t mi_value; 557 #define LPFC_DFLT_MIB_VAL 2 558 uint8_t mi_cap; 559 uint8_t mib_bde_cnt; 560 uint8_t cmf; 561 uint8_t cqv; 562 uint8_t mqv; 563 uint8_t wqv; 564 uint8_t rqv; 565 uint8_t eqav; 566 uint8_t cqav; 567 uint8_t wqsize; 568 uint8_t bv1s; 569 uint8_t pls; 570 #define LPFC_WQ_SZ64_SUPPORT 1 571 #define LPFC_WQ_SZ128_SUPPORT 2 572 uint8_t wqpcnt; 573 uint8_t nvme; 574 }; 575 576 #define LPFC_CQ_4K_PAGE_SZ 0x1 577 #define LPFC_CQ_16K_PAGE_SZ 0x4 578 #define LPFC_WQ_4K_PAGE_SZ 0x1 579 #define LPFC_WQ_16K_PAGE_SZ 0x4 580 581 struct lpfc_iov { 582 uint32_t pf_number; 583 uint32_t vf_number; 584 }; 585 586 struct lpfc_sli4_lnk_info { 587 uint8_t lnk_dv; 588 #define LPFC_LNK_DAT_INVAL 0 589 #define LPFC_LNK_DAT_VAL 1 590 uint8_t lnk_tp; 591 #define LPFC_LNK_GE 0x0 /* FCoE */ 592 #define LPFC_LNK_FC 0x1 /* FC */ 593 #define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */ 594 uint8_t lnk_no; 595 uint8_t optic_state; 596 }; 597 598 #define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \ 599 LPFC_FOF_IO_CHAN_NUM) 600 601 /* Used for tracking CPU mapping attributes */ 602 struct lpfc_vector_map_info { 603 uint16_t phys_id; 604 uint16_t core_id; 605 uint16_t eq; 606 uint16_t hdwq; 607 uint16_t flag; 608 #define LPFC_CPU_MAP_HYPER 0x1 609 #define LPFC_CPU_MAP_UNASSIGN 0x2 610 #define LPFC_CPU_FIRST_IRQ 0x4 611 }; 612 #define LPFC_VECTOR_MAP_EMPTY 0xffff 613 614 #define LPFC_IRQ_EMPTY 0xffffffff 615 616 /* Multi-XRI pool */ 617 #define XRI_BATCH 8 618 619 struct lpfc_pbl_pool { 620 struct list_head list; 621 u32 count; 622 spinlock_t lock; /* lock for pbl_pool*/ 623 }; 624 625 struct lpfc_pvt_pool { 626 u32 low_watermark; 627 u32 high_watermark; 628 629 struct list_head list; 630 u32 count; 631 spinlock_t lock; /* lock for pvt_pool */ 632 }; 633 634 struct lpfc_multixri_pool { 635 u32 xri_limit; 636 637 /* Starting point when searching a pbl_pool with round-robin method */ 638 u32 rrb_next_hwqid; 639 640 /* Used by lpfc_adjust_pvt_pool_count. 641 * io_req_count is incremented by 1 during IO submission. The heartbeat 642 * handler uses these two variables to determine if pvt_pool is idle or 643 * busy. 644 */ 645 u32 prev_io_req_count; 646 u32 io_req_count; 647 648 /* statistics */ 649 u32 pbl_empty_count; 650 #ifdef LPFC_MXP_STAT 651 u32 above_limit_count; 652 u32 below_limit_count; 653 u32 local_pbl_hit_count; 654 u32 other_pbl_hit_count; 655 u32 stat_max_hwm; 656 657 #define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */ 658 u32 stat_pbl_count; 659 u32 stat_pvt_count; 660 u32 stat_busy_count; 661 u32 stat_snapshot_taken; 662 #endif 663 664 /* TODO: Separate pvt_pool into get and put list */ 665 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */ 666 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */ 667 }; 668 669 struct lpfc_fc4_ctrl_stat { 670 u32 input_requests; 671 u32 output_requests; 672 u32 control_requests; 673 u32 io_cmpls; 674 }; 675 676 #ifdef LPFC_HDWQ_LOCK_STAT 677 struct lpfc_lock_stat { 678 uint32_t alloc_xri_get; 679 uint32_t alloc_xri_put; 680 uint32_t free_xri; 681 uint32_t wq_access; 682 uint32_t alloc_pvt_pool; 683 uint32_t mv_from_pvt_pool; 684 uint32_t mv_to_pub_pool; 685 uint32_t mv_to_pvt_pool; 686 uint32_t free_pub_pool; 687 uint32_t free_pvt_pool; 688 }; 689 #endif 690 691 struct lpfc_eq_intr_info { 692 struct list_head list; 693 uint32_t icnt; 694 }; 695 696 /* SLI4 HBA data structure entries */ 697 struct lpfc_sli4_hdw_queue { 698 /* Pointers to the constructed SLI4 queues */ 699 struct lpfc_queue *hba_eq; /* Event queues for HBA */ 700 struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */ 701 struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */ 702 uint16_t io_cq_map; 703 704 /* Keep track of IO buffers for this hardware queue */ 705 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */ 706 struct list_head lpfc_io_buf_list_get; 707 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */ 708 struct list_head lpfc_io_buf_list_put; 709 spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */ 710 struct list_head lpfc_abts_io_buf_list; 711 uint32_t total_io_bufs; 712 uint32_t get_io_bufs; 713 uint32_t put_io_bufs; 714 uint32_t empty_io_bufs; 715 uint32_t abts_scsi_io_bufs; 716 uint32_t abts_nvme_io_bufs; 717 718 /* Multi-XRI pool per HWQ */ 719 struct lpfc_multixri_pool *p_multixri_pool; 720 721 /* FC-4 Stats counters */ 722 struct lpfc_fc4_ctrl_stat nvme_cstat; 723 struct lpfc_fc4_ctrl_stat scsi_cstat; 724 #ifdef LPFC_HDWQ_LOCK_STAT 725 struct lpfc_lock_stat lock_conflict; 726 #endif 727 728 /* Per HDWQ pool resources */ 729 struct list_head sgl_list; 730 struct list_head cmd_rsp_buf_list; 731 732 /* Lock for syncing Per HDWQ pool resources */ 733 spinlock_t hdwq_lock; 734 }; 735 736 #ifdef LPFC_HDWQ_LOCK_STAT 737 /* compile time trylock stats */ 738 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \ 739 { \ 740 int only_once = 1; \ 741 while (spin_trylock_irqsave(lock, flag) == 0) { \ 742 if (only_once) { \ 743 only_once = 0; \ 744 qp->lock_conflict.lstat++; \ 745 } \ 746 } \ 747 } 748 #define lpfc_qp_spin_lock(lock, qp, lstat) \ 749 { \ 750 int only_once = 1; \ 751 while (spin_trylock(lock) == 0) { \ 752 if (only_once) { \ 753 only_once = 0; \ 754 qp->lock_conflict.lstat++; \ 755 } \ 756 } \ 757 } 758 #else 759 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \ 760 spin_lock_irqsave(lock, flag) 761 #define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock) 762 #endif 763 764 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS 765 struct lpfc_hdwq_stat { 766 u32 hdwq_no; 767 u32 rcv_io; 768 u32 xmt_io; 769 u32 cmpl_io; 770 }; 771 #endif 772 773 struct lpfc_sli4_hba { 774 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for 775 * config space registers 776 */ 777 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for 778 * control registers 779 */ 780 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for 781 * doorbell registers 782 */ 783 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for 784 * dpp registers 785 */ 786 union { 787 struct { 788 /* IF Type 0, BAR 0 PCI cfg space reg mem map */ 789 void __iomem *UERRLOregaddr; 790 void __iomem *UERRHIregaddr; 791 void __iomem *UEMASKLOregaddr; 792 void __iomem *UEMASKHIregaddr; 793 } if_type0; 794 struct { 795 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */ 796 void __iomem *STATUSregaddr; 797 void __iomem *CTRLregaddr; 798 void __iomem *ERR1regaddr; 799 #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1 800 #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2 801 void __iomem *ERR2regaddr; 802 #define SLIPORT_ERR2_REG_FW_RESTART 0x0 803 #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1 804 #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2 805 #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3 806 #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4 807 #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5 808 #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6 809 void __iomem *EQDregaddr; 810 } if_type2; 811 } u; 812 813 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */ 814 void __iomem *PSMPHRregaddr; 815 816 /* Well-known SLI INTF register memory map. */ 817 void __iomem *SLIINTFregaddr; 818 819 /* IF type 0, BAR 1 function CSR register memory map */ 820 void __iomem *ISRregaddr; /* HST_ISR register */ 821 void __iomem *IMRregaddr; /* HST_IMR register */ 822 void __iomem *ISCRregaddr; /* HST_ISCR register */ 823 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */ 824 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */ 825 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */ 826 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */ 827 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */ 828 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */ 829 void __iomem *BMBXregaddr; /* BootStrap MBX register */ 830 831 uint32_t ue_mask_lo; 832 uint32_t ue_mask_hi; 833 uint32_t ue_to_sr; 834 uint32_t ue_to_rp; 835 struct lpfc_register sli_intf; 836 struct lpfc_pc_sli4_params pc_sli4_params; 837 struct lpfc_bbscn_params bbscn_params; 838 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */ 839 840 void (*sli4_eq_clr_intr)(struct lpfc_queue *q); 841 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq, 842 uint32_t count, bool arm); 843 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq, 844 uint32_t count, bool arm); 845 846 /* Pointers to the constructed SLI4 queues */ 847 struct lpfc_sli4_hdw_queue *hdwq; 848 struct list_head lpfc_wq_list; 849 850 /* Pointers to the constructed SLI4 queues for NVMET */ 851 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */ 852 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */ 853 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */ 854 855 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */ 856 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */ 857 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */ 858 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */ 859 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */ 860 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */ 861 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */ 862 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */ 863 864 struct lpfc_name wwnn; 865 struct lpfc_name wwpn; 866 867 uint32_t fw_func_mode; /* FW function protocol mode */ 868 uint32_t ulp0_mode; /* ULP0 protocol mode */ 869 uint32_t ulp1_mode; /* ULP1 protocol mode */ 870 871 /* Optimized Access Storage specific queues/structures */ 872 uint64_t oas_next_lun; 873 uint8_t oas_next_tgt_wwpn[8]; 874 uint8_t oas_next_vpt_wwpn[8]; 875 876 /* Setup information for various queue parameters */ 877 int eq_esize; 878 int eq_ecount; 879 int cq_esize; 880 int cq_ecount; 881 int wq_esize; 882 int wq_ecount; 883 int mq_esize; 884 int mq_ecount; 885 int rq_esize; 886 int rq_ecount; 887 #define LPFC_SP_EQ_MAX_INTR_SEC 10000 888 #define LPFC_FP_EQ_MAX_INTR_SEC 10000 889 890 uint32_t intr_enable; 891 struct lpfc_bmbx bmbx; 892 struct lpfc_max_cfg_param max_cfg_param; 893 uint16_t extents_in_use; /* must allocate resource extents. */ 894 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */ 895 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */ 896 uint16_t next_rpi; 897 uint16_t io_xri_max; 898 uint16_t io_xri_cnt; 899 uint16_t io_xri_start; 900 uint16_t els_xri_cnt; 901 uint16_t nvmet_xri_cnt; 902 uint16_t nvmet_io_wait_cnt; 903 uint16_t nvmet_io_wait_total; 904 uint16_t cq_max; 905 struct lpfc_queue **cq_lookup; 906 struct list_head lpfc_els_sgl_list; 907 struct list_head lpfc_abts_els_sgl_list; 908 spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */ 909 struct list_head lpfc_abts_io_buf_list; 910 struct list_head lpfc_nvmet_sgl_list; 911 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */ 912 struct list_head lpfc_abts_nvmet_ctx_list; 913 spinlock_t t_active_list_lock; /* list of active NVMET IOs */ 914 struct list_head t_active_ctx_list; 915 struct list_head lpfc_nvmet_io_wait_list; 916 struct lpfc_nvmet_ctx_info *nvmet_ctx_info; 917 struct lpfc_sglq **lpfc_sglq_active_list; 918 struct list_head lpfc_rpi_hdr_list; 919 unsigned long *rpi_bmask; 920 uint16_t *rpi_ids; 921 uint16_t rpi_count; 922 struct list_head lpfc_rpi_blk_list; 923 unsigned long *xri_bmask; 924 uint16_t *xri_ids; 925 struct list_head lpfc_xri_blk_list; 926 unsigned long *vfi_bmask; 927 uint16_t *vfi_ids; 928 uint16_t vfi_count; 929 struct list_head lpfc_vfi_blk_list; 930 struct lpfc_sli4_flags sli4_flags; 931 struct list_head sp_queue_event; 932 struct list_head sp_cqe_event_pool; 933 struct list_head sp_asynce_work_queue; 934 spinlock_t asynce_list_lock; /* protect sp_asynce_work_queue list */ 935 struct list_head sp_els_xri_aborted_work_queue; 936 spinlock_t els_xri_abrt_list_lock; /* protect els_xri_aborted list */ 937 struct list_head sp_unsol_work_queue; 938 struct lpfc_sli4_link link_state; 939 struct lpfc_sli4_lnk_info lnk_info; 940 uint32_t pport_name_sta; 941 #define LPFC_SLI4_PPNAME_NON 0 942 #define LPFC_SLI4_PPNAME_GET 1 943 struct lpfc_iov iov; 944 spinlock_t sgl_list_lock; /* list of aborted els IOs */ 945 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */ 946 uint32_t physical_port; 947 948 /* CPU to vector mapping information */ 949 struct lpfc_vector_map_info *cpu_map; 950 uint16_t num_possible_cpu; 951 uint16_t num_present_cpu; 952 struct cpumask irq_aff_mask; 953 uint16_t curr_disp_cpu; 954 struct lpfc_eq_intr_info __percpu *eq_info; 955 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS 956 struct lpfc_hdwq_stat __percpu *c_stat; 957 #endif 958 struct lpfc_idle_stat *idle_stat; 959 uint32_t conf_trunk; 960 #define lpfc_conf_trunk_port0_WORD conf_trunk 961 #define lpfc_conf_trunk_port0_SHIFT 0 962 #define lpfc_conf_trunk_port0_MASK 0x1 963 #define lpfc_conf_trunk_port1_WORD conf_trunk 964 #define lpfc_conf_trunk_port1_SHIFT 1 965 #define lpfc_conf_trunk_port1_MASK 0x1 966 #define lpfc_conf_trunk_port2_WORD conf_trunk 967 #define lpfc_conf_trunk_port2_SHIFT 2 968 #define lpfc_conf_trunk_port2_MASK 0x1 969 #define lpfc_conf_trunk_port3_WORD conf_trunk 970 #define lpfc_conf_trunk_port3_SHIFT 3 971 #define lpfc_conf_trunk_port3_MASK 0x1 972 #define lpfc_conf_trunk_port0_nd_WORD conf_trunk 973 #define lpfc_conf_trunk_port0_nd_SHIFT 4 974 #define lpfc_conf_trunk_port0_nd_MASK 0x1 975 #define lpfc_conf_trunk_port1_nd_WORD conf_trunk 976 #define lpfc_conf_trunk_port1_nd_SHIFT 5 977 #define lpfc_conf_trunk_port1_nd_MASK 0x1 978 #define lpfc_conf_trunk_port2_nd_WORD conf_trunk 979 #define lpfc_conf_trunk_port2_nd_SHIFT 6 980 #define lpfc_conf_trunk_port2_nd_MASK 0x1 981 #define lpfc_conf_trunk_port3_nd_WORD conf_trunk 982 #define lpfc_conf_trunk_port3_nd_SHIFT 7 983 #define lpfc_conf_trunk_port3_nd_MASK 0x1 984 uint8_t flash_id; 985 uint8_t asic_rev; 986 uint16_t fawwpn_flag; /* FA-WWPN support state */ 987 #define LPFC_FAWWPN_CONFIG 0x1 /* FA-PWWN is configured */ 988 #define LPFC_FAWWPN_FABRIC 0x2 /* FA-PWWN success with Fabric */ 989 }; 990 991 enum lpfc_sge_type { 992 GEN_BUFF_TYPE, 993 SCSI_BUFF_TYPE, 994 NVMET_BUFF_TYPE 995 }; 996 997 enum lpfc_sgl_state { 998 SGL_FREED, 999 SGL_ALLOCATED, 1000 SGL_XRI_ABORTED 1001 }; 1002 1003 struct lpfc_sglq { 1004 /* lpfc_sglqs are used in double linked lists */ 1005 struct list_head list; 1006 struct list_head clist; 1007 enum lpfc_sge_type buff_type; /* is this a scsi sgl */ 1008 enum lpfc_sgl_state state; 1009 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */ 1010 uint16_t iotag; /* pre-assigned IO tag */ 1011 uint16_t sli4_lxritag; /* logical pre-assigned xri. */ 1012 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */ 1013 struct sli4_sge *sgl; /* pre-assigned SGL */ 1014 void *virt; /* virtual address. */ 1015 dma_addr_t phys; /* physical address */ 1016 }; 1017 1018 struct lpfc_rpi_hdr { 1019 struct list_head list; 1020 uint32_t len; 1021 struct lpfc_dmabuf *dmabuf; 1022 uint32_t page_count; 1023 uint32_t start_rpi; 1024 uint16_t next_rpi; 1025 }; 1026 1027 struct lpfc_rsrc_blks { 1028 struct list_head list; 1029 uint16_t rsrc_start; 1030 uint16_t rsrc_size; 1031 uint16_t rsrc_used; 1032 }; 1033 1034 struct lpfc_rdp_context { 1035 struct lpfc_nodelist *ndlp; 1036 uint16_t ox_id; 1037 uint16_t rx_id; 1038 READ_LNK_VAR link_stat; 1039 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE]; 1040 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE]; 1041 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int); 1042 }; 1043 1044 struct lpfc_lcb_context { 1045 uint8_t sub_command; 1046 uint8_t type; 1047 uint8_t capability; 1048 uint8_t frequency; 1049 uint16_t duration; 1050 uint16_t ox_id; 1051 uint16_t rx_id; 1052 struct lpfc_nodelist *ndlp; 1053 }; 1054 1055 1056 /* 1057 * SLI4 specific function prototypes 1058 */ 1059 int lpfc_pci_function_reset(struct lpfc_hba *); 1060 int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *); 1061 int lpfc_sli4_hba_setup(struct lpfc_hba *); 1062 int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t, 1063 uint8_t, uint32_t, bool); 1064 void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *); 1065 void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t); 1066 void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t, 1067 struct lpfc_mbx_sge *); 1068 int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *, 1069 uint16_t); 1070 1071 void lpfc_sli4_hba_reset(struct lpfc_hba *); 1072 struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba, 1073 uint32_t page_size, 1074 uint32_t entry_size, 1075 uint32_t entry_count, int cpu); 1076 void lpfc_sli4_queue_free(struct lpfc_queue *); 1077 int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t); 1078 void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq, 1079 uint32_t numq, uint32_t usdelay); 1080 int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *, 1081 struct lpfc_queue *, uint32_t, uint32_t); 1082 int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp, 1083 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type, 1084 uint32_t subtype); 1085 int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *, 1086 struct lpfc_queue *, uint32_t); 1087 int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *, 1088 struct lpfc_queue *, uint32_t); 1089 int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *, 1090 struct lpfc_queue *, struct lpfc_queue *, uint32_t); 1091 int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp, 1092 struct lpfc_queue **drqp, struct lpfc_queue **cqp, 1093 uint32_t subtype); 1094 int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1095 int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1096 int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1097 int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *); 1098 int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *, 1099 struct lpfc_queue *); 1100 int lpfc_sli4_queue_setup(struct lpfc_hba *); 1101 void lpfc_sli4_queue_unset(struct lpfc_hba *); 1102 int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t); 1103 int lpfc_repost_io_sgl_list(struct lpfc_hba *phba); 1104 uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *); 1105 void lpfc_sli4_free_xri(struct lpfc_hba *, int); 1106 int lpfc_sli4_post_async_mbox(struct lpfc_hba *); 1107 struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *); 1108 struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *); 1109 void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); 1110 void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); 1111 int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *); 1112 int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *); 1113 int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *); 1114 struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *); 1115 void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *); 1116 int lpfc_sli4_alloc_rpi(struct lpfc_hba *); 1117 void lpfc_sli4_free_rpi(struct lpfc_hba *, int); 1118 void lpfc_sli4_remove_rpis(struct lpfc_hba *); 1119 void lpfc_sli4_async_event_proc(struct lpfc_hba *); 1120 void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *); 1121 int lpfc_sli4_resume_rpi(struct lpfc_nodelist *, 1122 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *); 1123 void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *phba); 1124 void lpfc_sli4_nvme_pci_offline_aborted(struct lpfc_hba *phba, 1125 struct lpfc_io_buf *lpfc_ncmd); 1126 void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba, 1127 struct sli4_wcqe_xri_aborted *axri, 1128 struct lpfc_io_buf *lpfc_ncmd); 1129 void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba, 1130 struct sli4_wcqe_xri_aborted *axri, int idx); 1131 void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba, 1132 struct sli4_wcqe_xri_aborted *axri); 1133 void lpfc_sli4_els_xri_aborted(struct lpfc_hba *, 1134 struct sli4_wcqe_xri_aborted *); 1135 void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *); 1136 void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *); 1137 int lpfc_sli4_brdreset(struct lpfc_hba *); 1138 int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *); 1139 void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *); 1140 int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *); 1141 int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba); 1142 int lpfc_sli4_init_vpi(struct lpfc_vport *); 1143 void lpfc_sli4_eq_clr_intr(struct lpfc_queue *); 1144 void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1145 uint32_t count, bool arm); 1146 void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1147 uint32_t count, bool arm); 1148 void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q); 1149 void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1150 uint32_t count, bool arm); 1151 void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q, 1152 uint32_t count, bool arm); 1153 void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t); 1154 int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t); 1155 int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t); 1156 int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t); 1157 void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1158 void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1159 void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); 1160 int lpfc_sli4_unregister_fcf(struct lpfc_hba *); 1161 int lpfc_sli4_post_status_check(struct lpfc_hba *); 1162 uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *); 1163 uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *); 1164 void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba); 1165 struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba, 1166 struct lpfc_io_buf *buf); 1167 struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1168 struct lpfc_io_buf *buf); 1169 int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf); 1170 int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1171 struct lpfc_io_buf *buf); 1172 void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba, 1173 struct lpfc_sli4_hdw_queue *hdwq); 1174 void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba, 1175 struct lpfc_sli4_hdw_queue *hdwq); lpfc_sli4_qe(struct lpfc_queue * q,uint16_t idx)1176 static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx) 1177 { 1178 return q->q_pgs[idx / q->entry_cnt_per_pg] + 1179 (q->entry_size * (idx % q->entry_cnt_per_pg)); 1180 } 1181 1182 /** 1183 * lpfc_sli4_unrecoverable_port - Check ERR and RN bits in portstat_reg 1184 * @portstat_reg: portstat_reg pointer containing portstat_reg contents 1185 * 1186 * Description: 1187 * Use only for SLI4 interface type-2 or later. If ERR is set && RN is 0, then 1188 * port is deemed unrecoverable. 1189 * 1190 * Returns: 1191 * true - ERR && !RN 1192 * false - otherwise 1193 */ 1194 static inline bool lpfc_sli4_unrecoverable_port(struct lpfc_register * portstat_reg)1195 lpfc_sli4_unrecoverable_port(struct lpfc_register *portstat_reg) 1196 { 1197 return bf_get(lpfc_sliport_status_err, portstat_reg) && 1198 !bf_get(lpfc_sliport_status_rn, portstat_reg); 1199 } 1200