1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards 4 * 5 * Author Andreas Eversberg (jolly@eversberg.eu) 6 * ported to mqueue mechanism: 7 * Peter Sprenger (sprengermoving-bytes.de) 8 * 9 * inspired by existing hfc-pci driver: 10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) 11 * Copyright 2008 by Karsten Keil (kkeil@suse.de) 12 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) 13 * 14 * Thanks to Cologne Chip AG for this great controller! 15 */ 16 17 /* 18 * module parameters: 19 * type: 20 * By default (0), the card is automatically detected. 21 * Or use the following combinations: 22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port) 23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) 24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) 25 * Bit 8 = 0x00100 = uLaw (instead of aLaw) 26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware 27 * Bit 10 = spare 28 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) 29 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) 30 * Bit 13 = spare 31 * Bit 14 = 0x04000 = Use external ram (128K) 32 * Bit 15 = 0x08000 = Use external ram (512K) 33 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 34 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else 35 * Bit 18 = spare 36 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) 37 * (all other bits are reserved and shall be 0) 38 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM 39 * bus (PCM master) 40 * 41 * port: (optional or required for all ports on all installed cards) 42 * HFC-4S/HFC-8S only bits: 43 * Bit 0 = 0x001 = Use master clock for this S/T interface 44 * (ony once per chip). 45 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) 46 * Don't use this unless you know what you are doing! 47 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) 48 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock 49 * received from port 1 50 * 51 * HFC-E1 only bits: 52 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical 53 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) 54 * Bit 2 = 0x0004 = Report LOS 55 * Bit 3 = 0x0008 = Report AIS 56 * Bit 4 = 0x0010 = Report SLIP 57 * Bit 5 = 0x0020 = Report RDI 58 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame 59 * mode instead. 60 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. 61 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. 62 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. 63 * (E1 only) 64 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 65 * for default. 66 * (all other bits are reserved and shall be 0) 67 * 68 * debug: 69 * NOTE: only one debug value must be given for all cards 70 * enable debugging (see hfc_multi.h for debug options) 71 * 72 * poll: 73 * NOTE: only one poll value must be given for all cards 74 * Give the number of samples for each fifo process. 75 * By default 128 is used. Decrease to reduce delay, increase to 76 * reduce cpu load. If unsure, don't mess with it! 77 * Valid is 8, 16, 32, 64, 128, 256. 78 * 79 * pcm: 80 * NOTE: only one pcm value must be given for every card. 81 * The PCM bus id tells the mISDNdsp module about the connected PCM bus. 82 * By default (0), the PCM bus id is 100 for the card that is PCM master. 83 * If multiple cards are PCM master (because they are not interconnected), 84 * each card with PCM master will have increasing PCM id. 85 * All PCM busses with the same ID are expected to be connected and have 86 * common time slots slots. 87 * Only one chip of the PCM bus must be master, the others slave. 88 * -1 means no support of PCM bus not even. 89 * Omit this value, if all cards are interconnected or none is connected. 90 * If unsure, don't give this parameter. 91 * 92 * dmask and bmask: 93 * NOTE: One dmask value must be given for every HFC-E1 card. 94 * If omitted, the E1 card has D-channel on time slot 16, which is default. 95 * dmask is a 32 bit mask. The bit must be set for an alternate time slot. 96 * If multiple bits are set, multiple virtual card fragments are created. 97 * For each bit set, a bmask value must be given. Each bit on the bmask 98 * value stands for a B-channel. The bmask may not overlap with dmask or 99 * with other bmask values for that card. 100 * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000 101 * This will create one fragment with D-channel on slot 1 with 102 * B-channels on slots 2..15, and a second fragment with D-channel 103 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused. 104 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will 105 * not function. 106 * Example: dmask=0x00000001 bmask=0xfffffffe 107 * This will create a port with all 31 usable timeslots as 108 * B-channels. 109 * If no bits are set on bmask, no B-channel is created for that fragment. 110 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask) 111 * This will create 31 ports with one D-channel only. 112 * If you don't know how to use it, you don't need it! 113 * 114 * iomode: 115 * NOTE: only one mode value must be given for every card. 116 * -> See hfc_multi.h for HFC_IO_MODE_* values 117 * By default, the IO mode is pci memory IO (MEMIO). 118 * Some cards require specific IO mode, so it cannot be changed. 119 * It may be useful to set IO mode to register io (REGIO) to solve 120 * PCI bridge problems. 121 * If unsure, don't give this parameter. 122 * 123 * clockdelay_nt: 124 * NOTE: only one clockdelay_nt value must be given once for all cards. 125 * Give the value of the clock control register (A_ST_CLK_DLY) 126 * of the S/T interfaces in NT mode. 127 * This register is needed for the TBR3 certification, so don't change it. 128 * 129 * clockdelay_te: 130 * NOTE: only one clockdelay_te value must be given once 131 * Give the value of the clock control register (A_ST_CLK_DLY) 132 * of the S/T interfaces in TE mode. 133 * This register is needed for the TBR3 certification, so don't change it. 134 * 135 * clock: 136 * NOTE: only one clock value must be given once 137 * Selects interface with clock source for mISDN and applications. 138 * Set to card number starting with 1. Set to -1 to disable. 139 * By default, the first card is used as clock source. 140 * 141 * hwid: 142 * NOTE: only one hwid value must be given once 143 * Enable special embedded devices with XHFC controllers. 144 */ 145 146 /* 147 * debug register access (never use this, it will flood your system log) 148 * #define HFC_REGISTER_DEBUG 149 */ 150 151 #define HFC_MULTI_VERSION "2.03" 152 153 #include <linux/interrupt.h> 154 #include <linux/module.h> 155 #include <linux/slab.h> 156 #include <linux/pci.h> 157 #include <linux/delay.h> 158 #include <linux/mISDNhw.h> 159 #include <linux/mISDNdsp.h> 160 161 /* 162 #define IRQCOUNT_DEBUG 163 #define IRQ_DEBUG 164 */ 165 166 #include "hfc_multi.h" 167 #ifdef ECHOPREP 168 #include "gaintab.h" 169 #endif 170 171 #define MAX_CARDS 8 172 #define MAX_PORTS (8 * MAX_CARDS) 173 #define MAX_FRAGS (32 * MAX_CARDS) 174 175 static LIST_HEAD(HFClist); 176 static DEFINE_SPINLOCK(HFClock); /* global hfc list lock */ 177 178 static void ph_state_change(struct dchannel *); 179 180 static struct hfc_multi *syncmaster; 181 static int plxsd_master; /* if we have a master card (yet) */ 182 static DEFINE_SPINLOCK(plx_lock); /* may not acquire other lock inside */ 183 184 #define TYP_E1 1 185 #define TYP_4S 4 186 #define TYP_8S 8 187 188 static int poll_timer = 6; /* default = 128 samples = 16ms */ 189 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ 190 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; 191 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ 192 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode 193 (0x60 MUST be included!) */ 194 195 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ 196 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ 197 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ 198 199 /* 200 * module stuff 201 */ 202 203 static uint type[MAX_CARDS]; 204 static int pcm[MAX_CARDS]; 205 static uint dmask[MAX_CARDS]; 206 static uint bmask[MAX_FRAGS]; 207 static uint iomode[MAX_CARDS]; 208 static uint port[MAX_PORTS]; 209 static uint debug; 210 static uint poll; 211 static int clock; 212 static uint timer; 213 static uint clockdelay_te = CLKDEL_TE; 214 static uint clockdelay_nt = CLKDEL_NT; 215 #define HWID_NONE 0 216 #define HWID_MINIP4 1 217 #define HWID_MINIP8 2 218 #define HWID_MINIP16 3 219 static uint hwid = HWID_NONE; 220 221 static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99; 222 223 MODULE_AUTHOR("Andreas Eversberg"); 224 MODULE_LICENSE("GPL"); 225 MODULE_VERSION(HFC_MULTI_VERSION); 226 module_param(debug, uint, S_IRUGO | S_IWUSR); 227 module_param(poll, uint, S_IRUGO | S_IWUSR); 228 module_param(clock, int, S_IRUGO | S_IWUSR); 229 module_param(timer, uint, S_IRUGO | S_IWUSR); 230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); 231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); 232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); 233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR); 234 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR); 235 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR); 236 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); 237 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); 238 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */ 239 240 #ifdef HFC_REGISTER_DEBUG 241 #define HFC_outb(hc, reg, val) \ 242 (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) 243 #define HFC_outb_nodebug(hc, reg, val) \ 244 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) 245 #define HFC_inb(hc, reg) \ 246 (hc->HFC_inb(hc, reg, __func__, __LINE__)) 247 #define HFC_inb_nodebug(hc, reg) \ 248 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) 249 #define HFC_inw(hc, reg) \ 250 (hc->HFC_inw(hc, reg, __func__, __LINE__)) 251 #define HFC_inw_nodebug(hc, reg) \ 252 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) 253 #define HFC_wait(hc) \ 254 (hc->HFC_wait(hc, __func__, __LINE__)) 255 #define HFC_wait_nodebug(hc) \ 256 (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) 257 #else 258 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) 259 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) 260 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) 261 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) 262 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) 263 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) 264 #define HFC_wait(hc) (hc->HFC_wait(hc)) 265 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) 266 #endif 267 268 #ifdef CONFIG_MISDN_HFCMULTI_8xx 269 #include "hfc_multi_8xx.h" 270 #endif 271 272 /* HFC_IO_MODE_PCIMEM */ 273 static void 274 #ifdef HFC_REGISTER_DEBUG HFC_outb_pcimem(struct hfc_multi * hc,u_char reg,u_char val,const char * function,int line)275 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, 276 const char *function, int line) 277 #else 278 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) 279 #endif 280 { 281 writeb(val, hc->pci_membase + reg); 282 } 283 static u_char 284 #ifdef HFC_REGISTER_DEBUG HFC_inb_pcimem(struct hfc_multi * hc,u_char reg,const char * function,int line)285 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 286 #else 287 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) 288 #endif 289 { 290 return readb(hc->pci_membase + reg); 291 } 292 static u_short 293 #ifdef HFC_REGISTER_DEBUG HFC_inw_pcimem(struct hfc_multi * hc,u_char reg,const char * function,int line)294 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 295 #else 296 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) 297 #endif 298 { 299 return readw(hc->pci_membase + reg); 300 } 301 static void 302 #ifdef HFC_REGISTER_DEBUG HFC_wait_pcimem(struct hfc_multi * hc,const char * function,int line)303 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) 304 #else 305 HFC_wait_pcimem(struct hfc_multi *hc) 306 #endif 307 { 308 while (readb(hc->pci_membase + R_STATUS) & V_BUSY) 309 cpu_relax(); 310 } 311 312 /* HFC_IO_MODE_REGIO */ 313 static void 314 #ifdef HFC_REGISTER_DEBUG HFC_outb_regio(struct hfc_multi * hc,u_char reg,u_char val,const char * function,int line)315 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, 316 const char *function, int line) 317 #else 318 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) 319 #endif 320 { 321 outb(reg, hc->pci_iobase + 4); 322 outb(val, hc->pci_iobase); 323 } 324 static u_char 325 #ifdef HFC_REGISTER_DEBUG HFC_inb_regio(struct hfc_multi * hc,u_char reg,const char * function,int line)326 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 327 #else 328 HFC_inb_regio(struct hfc_multi *hc, u_char reg) 329 #endif 330 { 331 outb(reg, hc->pci_iobase + 4); 332 return inb(hc->pci_iobase); 333 } 334 static u_short 335 #ifdef HFC_REGISTER_DEBUG HFC_inw_regio(struct hfc_multi * hc,u_char reg,const char * function,int line)336 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 337 #else 338 HFC_inw_regio(struct hfc_multi *hc, u_char reg) 339 #endif 340 { 341 outb(reg, hc->pci_iobase + 4); 342 return inw(hc->pci_iobase); 343 } 344 static void 345 #ifdef HFC_REGISTER_DEBUG HFC_wait_regio(struct hfc_multi * hc,const char * function,int line)346 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) 347 #else 348 HFC_wait_regio(struct hfc_multi *hc) 349 #endif 350 { 351 outb(R_STATUS, hc->pci_iobase + 4); 352 while (inb(hc->pci_iobase) & V_BUSY) 353 cpu_relax(); 354 } 355 356 #ifdef HFC_REGISTER_DEBUG 357 static void HFC_outb_debug(struct hfc_multi * hc,u_char reg,u_char val,const char * function,int line)358 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, 359 const char *function, int line) 360 { 361 char regname[256] = "", bits[9] = "xxxxxxxx"; 362 int i; 363 364 i = -1; 365 while (hfc_register_names[++i].name) { 366 if (hfc_register_names[i].reg == reg) 367 strcat(regname, hfc_register_names[i].name); 368 } 369 if (regname[0] == '\0') 370 strcpy(regname, "register"); 371 372 bits[7] = '0' + (!!(val & 1)); 373 bits[6] = '0' + (!!(val & 2)); 374 bits[5] = '0' + (!!(val & 4)); 375 bits[4] = '0' + (!!(val & 8)); 376 bits[3] = '0' + (!!(val & 16)); 377 bits[2] = '0' + (!!(val & 32)); 378 bits[1] = '0' + (!!(val & 64)); 379 bits[0] = '0' + (!!(val & 128)); 380 printk(KERN_DEBUG 381 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", 382 hc->id, reg, regname, val, bits, function, line); 383 HFC_outb_nodebug(hc, reg, val); 384 } 385 static u_char HFC_inb_debug(struct hfc_multi * hc,u_char reg,const char * function,int line)386 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 387 { 388 char regname[256] = "", bits[9] = "xxxxxxxx"; 389 u_char val = HFC_inb_nodebug(hc, reg); 390 int i; 391 392 i = 0; 393 while (hfc_register_names[i++].name) 394 ; 395 while (hfc_register_names[++i].name) { 396 if (hfc_register_names[i].reg == reg) 397 strcat(regname, hfc_register_names[i].name); 398 } 399 if (regname[0] == '\0') 400 strcpy(regname, "register"); 401 402 bits[7] = '0' + (!!(val & 1)); 403 bits[6] = '0' + (!!(val & 2)); 404 bits[5] = '0' + (!!(val & 4)); 405 bits[4] = '0' + (!!(val & 8)); 406 bits[3] = '0' + (!!(val & 16)); 407 bits[2] = '0' + (!!(val & 32)); 408 bits[1] = '0' + (!!(val & 64)); 409 bits[0] = '0' + (!!(val & 128)); 410 printk(KERN_DEBUG 411 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", 412 hc->id, reg, regname, val, bits, function, line); 413 return val; 414 } 415 static u_short HFC_inw_debug(struct hfc_multi * hc,u_char reg,const char * function,int line)416 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 417 { 418 char regname[256] = ""; 419 u_short val = HFC_inw_nodebug(hc, reg); 420 int i; 421 422 i = 0; 423 while (hfc_register_names[i++].name) 424 ; 425 while (hfc_register_names[++i].name) { 426 if (hfc_register_names[i].reg == reg) 427 strcat(regname, hfc_register_names[i].name); 428 } 429 if (regname[0] == '\0') 430 strcpy(regname, "register"); 431 432 printk(KERN_DEBUG 433 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", 434 hc->id, reg, regname, val, function, line); 435 return val; 436 } 437 static void HFC_wait_debug(struct hfc_multi * hc,const char * function,int line)438 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) 439 { 440 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", 441 hc->id, function, line); 442 HFC_wait_nodebug(hc); 443 } 444 #endif 445 446 /* write fifo data (REGIO) */ 447 static void write_fifo_regio(struct hfc_multi * hc,u_char * data,int len)448 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 449 { 450 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4); 451 while (len >> 2) { 452 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); 453 data += 4; 454 len -= 4; 455 } 456 while (len >> 1) { 457 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); 458 data += 2; 459 len -= 2; 460 } 461 while (len) { 462 outb(*data, hc->pci_iobase); 463 data++; 464 len--; 465 } 466 } 467 /* write fifo data (PCIMEM) */ 468 static void write_fifo_pcimem(struct hfc_multi * hc,u_char * data,int len)469 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 470 { 471 while (len >> 2) { 472 writel(cpu_to_le32(*(u32 *)data), 473 hc->pci_membase + A_FIFO_DATA0); 474 data += 4; 475 len -= 4; 476 } 477 while (len >> 1) { 478 writew(cpu_to_le16(*(u16 *)data), 479 hc->pci_membase + A_FIFO_DATA0); 480 data += 2; 481 len -= 2; 482 } 483 while (len) { 484 writeb(*data, hc->pci_membase + A_FIFO_DATA0); 485 data++; 486 len--; 487 } 488 } 489 490 /* read fifo data (REGIO) */ 491 static void read_fifo_regio(struct hfc_multi * hc,u_char * data,int len)492 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 493 { 494 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4); 495 while (len >> 2) { 496 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); 497 data += 4; 498 len -= 4; 499 } 500 while (len >> 1) { 501 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); 502 data += 2; 503 len -= 2; 504 } 505 while (len) { 506 *data = inb(hc->pci_iobase); 507 data++; 508 len--; 509 } 510 } 511 512 /* read fifo data (PCIMEM) */ 513 static void read_fifo_pcimem(struct hfc_multi * hc,u_char * data,int len)514 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 515 { 516 while (len >> 2) { 517 *(u32 *)data = 518 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); 519 data += 4; 520 len -= 4; 521 } 522 while (len >> 1) { 523 *(u16 *)data = 524 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); 525 data += 2; 526 len -= 2; 527 } 528 while (len) { 529 *data = readb(hc->pci_membase + A_FIFO_DATA0); 530 data++; 531 len--; 532 } 533 } 534 535 static void enable_hwirq(struct hfc_multi * hc)536 enable_hwirq(struct hfc_multi *hc) 537 { 538 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; 539 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 540 } 541 542 static void disable_hwirq(struct hfc_multi * hc)543 disable_hwirq(struct hfc_multi *hc) 544 { 545 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); 546 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 547 } 548 549 #define NUM_EC 2 550 #define MAX_TDM_CHAN 32 551 552 553 static inline void enablepcibridge(struct hfc_multi * c)554 enablepcibridge(struct hfc_multi *c) 555 { 556 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ 557 } 558 559 static inline void disablepcibridge(struct hfc_multi * c)560 disablepcibridge(struct hfc_multi *c) 561 { 562 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ 563 } 564 565 static inline unsigned char readpcibridge(struct hfc_multi * hc,unsigned char address)566 readpcibridge(struct hfc_multi *hc, unsigned char address) 567 { 568 unsigned short cipv; 569 unsigned char data; 570 571 if (!hc->pci_iobase) 572 return 0; 573 574 /* slow down a PCI read access by 1 PCI clock cycle */ 575 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ 576 577 if (address == 0) 578 cipv = 0x4000; 579 else 580 cipv = 0x5800; 581 582 /* select local bridge port address by writing to CIP port */ 583 /* data = HFC_inb(c, cipv); * was _io before */ 584 outw(cipv, hc->pci_iobase + 4); 585 data = inb(hc->pci_iobase); 586 587 /* restore R_CTRL for normal PCI read cycle speed */ 588 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ 589 590 return data; 591 } 592 593 static inline void writepcibridge(struct hfc_multi * hc,unsigned char address,unsigned char data)594 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) 595 { 596 unsigned short cipv; 597 unsigned int datav; 598 599 if (!hc->pci_iobase) 600 return; 601 602 if (address == 0) 603 cipv = 0x4000; 604 else 605 cipv = 0x5800; 606 607 /* select local bridge port address by writing to CIP port */ 608 outw(cipv, hc->pci_iobase + 4); 609 /* define a 32 bit dword with 4 identical bytes for write sequence */ 610 datav = data | ((__u32) data << 8) | ((__u32) data << 16) | 611 ((__u32) data << 24); 612 613 /* 614 * write this 32 bit dword to the bridge data port 615 * this will initiate a write sequence of up to 4 writes to the same 616 * address on the local bus interface the number of write accesses 617 * is undefined but >=1 and depends on the next PCI transaction 618 * during write sequence on the local bus 619 */ 620 outl(datav, hc->pci_iobase); 621 } 622 623 static inline void cpld_set_reg(struct hfc_multi * hc,unsigned char reg)624 cpld_set_reg(struct hfc_multi *hc, unsigned char reg) 625 { 626 /* Do data pin read low byte */ 627 HFC_outb(hc, R_GPIO_OUT1, reg); 628 } 629 630 static inline void cpld_write_reg(struct hfc_multi * hc,unsigned char reg,unsigned char val)631 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) 632 { 633 cpld_set_reg(hc, reg); 634 635 enablepcibridge(hc); 636 writepcibridge(hc, 1, val); 637 disablepcibridge(hc); 638 639 return; 640 } 641 642 static inline void vpm_write_address(struct hfc_multi * hc,unsigned short addr)643 vpm_write_address(struct hfc_multi *hc, unsigned short addr) 644 { 645 cpld_write_reg(hc, 0, 0xff & addr); 646 cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); 647 } 648 649 static inline unsigned char vpm_in(struct hfc_multi * c,int which,unsigned short addr)650 vpm_in(struct hfc_multi *c, int which, unsigned short addr) 651 { 652 unsigned char res; 653 654 vpm_write_address(c, addr); 655 656 if (!which) 657 cpld_set_reg(c, 2); 658 else 659 cpld_set_reg(c, 3); 660 661 enablepcibridge(c); 662 res = readpcibridge(c, 1); 663 disablepcibridge(c); 664 665 cpld_set_reg(c, 0); 666 667 return res; 668 } 669 670 static inline void vpm_out(struct hfc_multi * c,int which,unsigned short addr,unsigned char data)671 vpm_out(struct hfc_multi *c, int which, unsigned short addr, 672 unsigned char data) 673 { 674 vpm_write_address(c, addr); 675 676 enablepcibridge(c); 677 678 if (!which) 679 cpld_set_reg(c, 2); 680 else 681 cpld_set_reg(c, 3); 682 683 writepcibridge(c, 1, data); 684 685 cpld_set_reg(c, 0); 686 687 disablepcibridge(c); 688 689 { 690 unsigned char regin; 691 regin = vpm_in(c, which, addr); 692 if (regin != data) 693 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " 694 "0x%x\n", data, addr, regin); 695 } 696 697 } 698 699 700 static void vpm_init(struct hfc_multi * wc)701 vpm_init(struct hfc_multi *wc) 702 { 703 unsigned char reg; 704 unsigned int mask; 705 unsigned int i, x, y; 706 unsigned int ver; 707 708 for (x = 0; x < NUM_EC; x++) { 709 /* Setup GPIO's */ 710 if (!x) { 711 ver = vpm_in(wc, x, 0x1a0); 712 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); 713 } 714 715 for (y = 0; y < 4; y++) { 716 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ 717 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ 718 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ 719 } 720 721 /* Setup TDM path - sets fsync and tdm_clk as inputs */ 722 reg = vpm_in(wc, x, 0x1a3); /* misc_con */ 723 vpm_out(wc, x, 0x1a3, reg & ~2); 724 725 /* Setup Echo length (256 taps) */ 726 vpm_out(wc, x, 0x022, 1); 727 vpm_out(wc, x, 0x023, 0xff); 728 729 /* Setup timeslots */ 730 vpm_out(wc, x, 0x02f, 0x00); 731 mask = 0x02020202 << (x * 4); 732 733 /* Setup the tdm channel masks for all chips */ 734 for (i = 0; i < 4; i++) 735 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); 736 737 /* Setup convergence rate */ 738 printk(KERN_DEBUG "VPM: A-law mode\n"); 739 reg = 0x00 | 0x10 | 0x01; 740 vpm_out(wc, x, 0x20, reg); 741 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); 742 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ 743 744 vpm_out(wc, x, 0x24, 0x02); 745 reg = vpm_in(wc, x, 0x24); 746 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); 747 748 /* Initialize echo cans */ 749 for (i = 0; i < MAX_TDM_CHAN; i++) { 750 if (mask & (0x00000001 << i)) 751 vpm_out(wc, x, i, 0x00); 752 } 753 754 /* 755 * ARM arch at least disallows a udelay of 756 * more than 2ms... it gives a fake "__bad_udelay" 757 * reference at link-time. 758 * long delays in kernel code are pretty sucky anyway 759 * for now work around it using 5 x 2ms instead of 1 x 10ms 760 */ 761 762 udelay(2000); 763 udelay(2000); 764 udelay(2000); 765 udelay(2000); 766 udelay(2000); 767 768 /* Put in bypass mode */ 769 for (i = 0; i < MAX_TDM_CHAN; i++) { 770 if (mask & (0x00000001 << i)) 771 vpm_out(wc, x, i, 0x01); 772 } 773 774 /* Enable bypass */ 775 for (i = 0; i < MAX_TDM_CHAN; i++) { 776 if (mask & (0x00000001 << i)) 777 vpm_out(wc, x, 0x78 + i, 0x01); 778 } 779 780 } 781 } 782 783 #ifdef UNUSED 784 static void vpm_check(struct hfc_multi * hctmp)785 vpm_check(struct hfc_multi *hctmp) 786 { 787 unsigned char gpi2; 788 789 gpi2 = HFC_inb(hctmp, R_GPI_IN2); 790 791 if ((gpi2 & 0x3) != 0x3) 792 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); 793 } 794 #endif /* UNUSED */ 795 796 797 /* 798 * Interface to enable/disable the HW Echocan 799 * 800 * these functions are called within a spin_lock_irqsave on 801 * the channel instance lock, so we are not disturbed by irqs 802 * 803 * we can later easily change the interface to make other 804 * things configurable, for now we configure the taps 805 * 806 */ 807 808 static void vpm_echocan_on(struct hfc_multi * hc,int ch,int taps)809 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) 810 { 811 unsigned int timeslot; 812 unsigned int unit; 813 struct bchannel *bch = hc->chan[ch].bch; 814 #ifdef TXADJ 815 int txadj = -4; 816 struct sk_buff *skb; 817 #endif 818 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 819 return; 820 821 if (!bch) 822 return; 823 824 #ifdef TXADJ 825 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 826 sizeof(int), &txadj, GFP_ATOMIC); 827 if (skb) 828 recv_Bchannel_skb(bch, skb); 829 #endif 830 831 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1; 832 unit = ch % 4; 833 834 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", 835 taps, timeslot); 836 837 vpm_out(hc, unit, timeslot, 0x7e); 838 } 839 840 static void vpm_echocan_off(struct hfc_multi * hc,int ch)841 vpm_echocan_off(struct hfc_multi *hc, int ch) 842 { 843 unsigned int timeslot; 844 unsigned int unit; 845 struct bchannel *bch = hc->chan[ch].bch; 846 #ifdef TXADJ 847 int txadj = 0; 848 struct sk_buff *skb; 849 #endif 850 851 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 852 return; 853 854 if (!bch) 855 return; 856 857 #ifdef TXADJ 858 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 859 sizeof(int), &txadj, GFP_ATOMIC); 860 if (skb) 861 recv_Bchannel_skb(bch, skb); 862 #endif 863 864 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1; 865 unit = ch % 4; 866 867 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", 868 timeslot); 869 /* FILLME */ 870 vpm_out(hc, unit, timeslot, 0x01); 871 } 872 873 874 /* 875 * Speech Design resync feature 876 * NOTE: This is called sometimes outside interrupt handler. 877 * We must lock irqsave, so no other interrupt (other card) will occur! 878 * Also multiple interrupts may nest, so must lock each access (lists, card)! 879 */ 880 static inline void hfcmulti_resync(struct hfc_multi * locked,struct hfc_multi * newmaster,int rm)881 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) 882 { 883 struct hfc_multi *hc, *next, *pcmmaster = NULL; 884 void __iomem *plx_acc_32; 885 u_int pv; 886 u_long flags; 887 888 spin_lock_irqsave(&HFClock, flags); 889 spin_lock(&plx_lock); /* must be locked inside other locks */ 890 891 if (debug & DEBUG_HFCMULTI_PLXSD) 892 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", 893 __func__, syncmaster); 894 895 /* select new master */ 896 if (newmaster) { 897 if (debug & DEBUG_HFCMULTI_PLXSD) 898 printk(KERN_DEBUG "using provided controller\n"); 899 } else { 900 list_for_each_entry_safe(hc, next, &HFClist, list) { 901 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 902 if (hc->syncronized) { 903 newmaster = hc; 904 break; 905 } 906 } 907 } 908 } 909 910 /* Disable sync of all cards */ 911 list_for_each_entry_safe(hc, next, &HFClist, list) { 912 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 913 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 914 pv = readl(plx_acc_32); 915 pv &= ~PLX_SYNC_O_EN; 916 writel(pv, plx_acc_32); 917 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 918 pcmmaster = hc; 919 if (hc->ctype == HFC_TYPE_E1) { 920 if (debug & DEBUG_HFCMULTI_PLXSD) 921 printk(KERN_DEBUG 922 "Schedule SYNC_I\n"); 923 hc->e1_resync |= 1; /* get SYNC_I */ 924 } 925 } 926 } 927 } 928 929 if (newmaster) { 930 hc = newmaster; 931 if (debug & DEBUG_HFCMULTI_PLXSD) 932 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " 933 "interface.\n", hc->id, hc); 934 /* Enable new sync master */ 935 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 936 pv = readl(plx_acc_32); 937 pv |= PLX_SYNC_O_EN; 938 writel(pv, plx_acc_32); 939 /* switch to jatt PLL, if not disabled by RX_SYNC */ 940 if (hc->ctype == HFC_TYPE_E1 941 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { 942 if (debug & DEBUG_HFCMULTI_PLXSD) 943 printk(KERN_DEBUG "Schedule jatt PLL\n"); 944 hc->e1_resync |= 2; /* switch to jatt */ 945 } 946 } else { 947 if (pcmmaster) { 948 hc = pcmmaster; 949 if (debug & DEBUG_HFCMULTI_PLXSD) 950 printk(KERN_DEBUG 951 "id=%d (0x%p) = PCM master syncronized " 952 "with QUARTZ\n", hc->id, hc); 953 if (hc->ctype == HFC_TYPE_E1) { 954 /* Use the crystal clock for the PCM 955 master card */ 956 if (debug & DEBUG_HFCMULTI_PLXSD) 957 printk(KERN_DEBUG 958 "Schedule QUARTZ for HFC-E1\n"); 959 hc->e1_resync |= 4; /* switch quartz */ 960 } else { 961 if (debug & DEBUG_HFCMULTI_PLXSD) 962 printk(KERN_DEBUG 963 "QUARTZ is automatically " 964 "enabled by HFC-%dS\n", hc->ctype); 965 } 966 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 967 pv = readl(plx_acc_32); 968 pv |= PLX_SYNC_O_EN; 969 writel(pv, plx_acc_32); 970 } else 971 if (!rm) 972 printk(KERN_ERR "%s no pcm master, this MUST " 973 "not happen!\n", __func__); 974 } 975 syncmaster = newmaster; 976 977 spin_unlock(&plx_lock); 978 spin_unlock_irqrestore(&HFClock, flags); 979 } 980 981 /* This must be called AND hc must be locked irqsave!!! */ 982 static inline void plxsd_checksync(struct hfc_multi * hc,int rm)983 plxsd_checksync(struct hfc_multi *hc, int rm) 984 { 985 if (hc->syncronized) { 986 if (syncmaster == NULL) { 987 if (debug & DEBUG_HFCMULTI_PLXSD) 988 printk(KERN_DEBUG "%s: GOT sync on card %d" 989 " (id=%d)\n", __func__, hc->id + 1, 990 hc->id); 991 hfcmulti_resync(hc, hc, rm); 992 } 993 } else { 994 if (syncmaster == hc) { 995 if (debug & DEBUG_HFCMULTI_PLXSD) 996 printk(KERN_DEBUG "%s: LOST sync on card %d" 997 " (id=%d)\n", __func__, hc->id + 1, 998 hc->id); 999 hfcmulti_resync(hc, NULL, rm); 1000 } 1001 } 1002 } 1003 1004 1005 /* 1006 * free hardware resources used by driver 1007 */ 1008 static void release_io_hfcmulti(struct hfc_multi * hc)1009 release_io_hfcmulti(struct hfc_multi *hc) 1010 { 1011 void __iomem *plx_acc_32; 1012 u_int pv; 1013 u_long plx_flags; 1014 1015 if (debug & DEBUG_HFCMULTI_INIT) 1016 printk(KERN_DEBUG "%s: entered\n", __func__); 1017 1018 /* soft reset also masks all interrupts */ 1019 hc->hw.r_cirm |= V_SRES; 1020 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1021 udelay(1000); 1022 hc->hw.r_cirm &= ~V_SRES; 1023 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1024 udelay(1000); /* instead of 'wait' that may cause locking */ 1025 1026 /* release Speech Design card, if PLX was initialized */ 1027 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { 1028 if (debug & DEBUG_HFCMULTI_PLXSD) 1029 printk(KERN_DEBUG "%s: release PLXSD card %d\n", 1030 __func__, hc->id + 1); 1031 spin_lock_irqsave(&plx_lock, plx_flags); 1032 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1033 writel(PLX_GPIOC_INIT, plx_acc_32); 1034 pv = readl(plx_acc_32); 1035 /* Termination off */ 1036 pv &= ~PLX_TERM_ON; 1037 /* Disconnect the PCM */ 1038 pv |= PLX_SLAVE_EN_N; 1039 pv &= ~PLX_MASTER_EN; 1040 pv &= ~PLX_SYNC_O_EN; 1041 /* Put the DSP in Reset */ 1042 pv &= ~PLX_DSP_RES_N; 1043 writel(pv, plx_acc_32); 1044 if (debug & DEBUG_HFCMULTI_INIT) 1045 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n", 1046 __func__, pv); 1047 spin_unlock_irqrestore(&plx_lock, plx_flags); 1048 } 1049 1050 /* disable memory mapped ports / io ports */ 1051 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ 1052 if (hc->pci_dev) 1053 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); 1054 if (hc->pci_membase) 1055 iounmap(hc->pci_membase); 1056 if (hc->plx_membase) 1057 iounmap(hc->plx_membase); 1058 if (hc->pci_iobase) 1059 release_region(hc->pci_iobase, 8); 1060 if (hc->xhfc_membase) 1061 iounmap((void *)hc->xhfc_membase); 1062 1063 if (hc->pci_dev) { 1064 pci_disable_device(hc->pci_dev); 1065 pci_set_drvdata(hc->pci_dev, NULL); 1066 } 1067 if (debug & DEBUG_HFCMULTI_INIT) 1068 printk(KERN_DEBUG "%s: done\n", __func__); 1069 } 1070 1071 /* 1072 * function called to reset the HFC chip. A complete software reset of chip 1073 * and fifos is done. All configuration of the chip is done. 1074 */ 1075 1076 static int init_chip(struct hfc_multi * hc)1077 init_chip(struct hfc_multi *hc) 1078 { 1079 u_long flags, val, val2 = 0, rev; 1080 int i, err = 0; 1081 u_char r_conf_en, rval; 1082 void __iomem *plx_acc_32; 1083 u_int pv; 1084 u_long plx_flags, hfc_flags; 1085 int plx_count; 1086 struct hfc_multi *pos, *next, *plx_last_hc; 1087 1088 spin_lock_irqsave(&hc->lock, flags); 1089 /* reset all registers */ 1090 memset(&hc->hw, 0, sizeof(struct hfcm_hw)); 1091 1092 /* revision check */ 1093 if (debug & DEBUG_HFCMULTI_INIT) 1094 printk(KERN_DEBUG "%s: entered\n", __func__); 1095 val = HFC_inb(hc, R_CHIP_ID); 1096 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe && 1097 (val >> 1) != 0x31) { 1098 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); 1099 err = -EIO; 1100 goto out; 1101 } 1102 rev = HFC_inb(hc, R_CHIP_RV); 1103 printk(KERN_INFO 1104 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", 1105 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ? 1106 " (old FIFO handling)" : ""); 1107 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) { 1108 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); 1109 printk(KERN_WARNING 1110 "HFC_multi: NOTE: Your chip is revision 0, " 1111 "ask Cologne Chip for update. Newer chips " 1112 "have a better FIFO handling. Old chips " 1113 "still work but may have slightly lower " 1114 "HDLC transmit performance.\n"); 1115 } 1116 if (rev > 1) { 1117 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " 1118 "consider chip revision = %ld. The chip / " 1119 "bridge may not work.\n", rev); 1120 } 1121 1122 /* set s-ram size */ 1123 hc->Flen = 0x10; 1124 hc->Zmin = 0x80; 1125 hc->Zlen = 384; 1126 hc->DTMFbase = 0x1000; 1127 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { 1128 if (debug & DEBUG_HFCMULTI_INIT) 1129 printk(KERN_DEBUG "%s: changing to 128K external RAM\n", 1130 __func__); 1131 hc->hw.r_ctrl |= V_EXT_RAM; 1132 hc->hw.r_ram_sz = 1; 1133 hc->Flen = 0x20; 1134 hc->Zmin = 0xc0; 1135 hc->Zlen = 1856; 1136 hc->DTMFbase = 0x2000; 1137 } 1138 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { 1139 if (debug & DEBUG_HFCMULTI_INIT) 1140 printk(KERN_DEBUG "%s: changing to 512K external RAM\n", 1141 __func__); 1142 hc->hw.r_ctrl |= V_EXT_RAM; 1143 hc->hw.r_ram_sz = 2; 1144 hc->Flen = 0x20; 1145 hc->Zmin = 0xc0; 1146 hc->Zlen = 8000; 1147 hc->DTMFbase = 0x2000; 1148 } 1149 if (hc->ctype == HFC_TYPE_XHFC) { 1150 hc->Flen = 0x8; 1151 hc->Zmin = 0x0; 1152 hc->Zlen = 64; 1153 hc->DTMFbase = 0x0; 1154 } 1155 hc->max_trans = poll << 1; 1156 if (hc->max_trans > hc->Zlen) 1157 hc->max_trans = hc->Zlen; 1158 1159 /* Speech Design PLX bridge */ 1160 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1161 if (debug & DEBUG_HFCMULTI_PLXSD) 1162 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", 1163 __func__, hc->id + 1); 1164 spin_lock_irqsave(&plx_lock, plx_flags); 1165 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1166 writel(PLX_GPIOC_INIT, plx_acc_32); 1167 pv = readl(plx_acc_32); 1168 /* The first and the last cards are terminating the PCM bus */ 1169 pv |= PLX_TERM_ON; /* hc is currently the last */ 1170 /* Disconnect the PCM */ 1171 pv |= PLX_SLAVE_EN_N; 1172 pv &= ~PLX_MASTER_EN; 1173 pv &= ~PLX_SYNC_O_EN; 1174 /* Put the DSP in Reset */ 1175 pv &= ~PLX_DSP_RES_N; 1176 writel(pv, plx_acc_32); 1177 spin_unlock_irqrestore(&plx_lock, plx_flags); 1178 if (debug & DEBUG_HFCMULTI_INIT) 1179 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n", 1180 __func__, pv); 1181 /* 1182 * If we are the 3rd PLXSD card or higher, we must turn 1183 * termination of last PLXSD card off. 1184 */ 1185 spin_lock_irqsave(&HFClock, hfc_flags); 1186 plx_count = 0; 1187 plx_last_hc = NULL; 1188 list_for_each_entry_safe(pos, next, &HFClist, list) { 1189 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { 1190 plx_count++; 1191 if (pos != hc) 1192 plx_last_hc = pos; 1193 } 1194 } 1195 if (plx_count >= 3) { 1196 if (debug & DEBUG_HFCMULTI_PLXSD) 1197 printk(KERN_DEBUG "%s: card %d is between, so " 1198 "we disable termination\n", 1199 __func__, plx_last_hc->id + 1); 1200 spin_lock_irqsave(&plx_lock, plx_flags); 1201 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; 1202 pv = readl(plx_acc_32); 1203 pv &= ~PLX_TERM_ON; 1204 writel(pv, plx_acc_32); 1205 spin_unlock_irqrestore(&plx_lock, plx_flags); 1206 if (debug & DEBUG_HFCMULTI_INIT) 1207 printk(KERN_DEBUG 1208 "%s: term off: PLX_GPIO=%x\n", 1209 __func__, pv); 1210 } 1211 spin_unlock_irqrestore(&HFClock, hfc_flags); 1212 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1213 } 1214 1215 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1216 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1217 1218 /* we only want the real Z2 read-pointer for revision > 0 */ 1219 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) 1220 hc->hw.r_ram_sz |= V_FZ_MD; 1221 1222 /* select pcm mode */ 1223 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1224 if (debug & DEBUG_HFCMULTI_INIT) 1225 printk(KERN_DEBUG "%s: setting PCM into slave mode\n", 1226 __func__); 1227 } else 1228 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { 1229 if (debug & DEBUG_HFCMULTI_INIT) 1230 printk(KERN_DEBUG "%s: setting PCM into master mode\n", 1231 __func__); 1232 hc->hw.r_pcm_md0 |= V_PCM_MD; 1233 } else { 1234 if (debug & DEBUG_HFCMULTI_INIT) 1235 printk(KERN_DEBUG "%s: performing PCM auto detect\n", 1236 __func__); 1237 } 1238 1239 /* soft reset */ 1240 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); 1241 if (hc->ctype == HFC_TYPE_XHFC) 1242 HFC_outb(hc, 0x0C /* R_FIFO_THRES */, 1243 0x11 /* 16 Bytes TX/RX */); 1244 else 1245 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1246 HFC_outb(hc, R_FIFO_MD, 0); 1247 if (hc->ctype == HFC_TYPE_XHFC) 1248 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES; 1249 else 1250 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES 1251 | V_RLD_EPR; 1252 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1253 udelay(100); 1254 hc->hw.r_cirm = 0; 1255 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1256 udelay(100); 1257 if (hc->ctype != HFC_TYPE_XHFC) 1258 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1259 1260 /* Speech Design PLX bridge pcm and sync mode */ 1261 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1262 spin_lock_irqsave(&plx_lock, plx_flags); 1263 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1264 pv = readl(plx_acc_32); 1265 /* Connect PCM */ 1266 if (hc->hw.r_pcm_md0 & V_PCM_MD) { 1267 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1268 pv |= PLX_SYNC_O_EN; 1269 if (debug & DEBUG_HFCMULTI_INIT) 1270 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n", 1271 __func__, pv); 1272 } else { 1273 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); 1274 pv &= ~PLX_SYNC_O_EN; 1275 if (debug & DEBUG_HFCMULTI_INIT) 1276 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n", 1277 __func__, pv); 1278 } 1279 writel(pv, plx_acc_32); 1280 spin_unlock_irqrestore(&plx_lock, plx_flags); 1281 } 1282 1283 /* PCM setup */ 1284 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); 1285 if (hc->slots == 32) 1286 HFC_outb(hc, R_PCM_MD1, 0x00); 1287 if (hc->slots == 64) 1288 HFC_outb(hc, R_PCM_MD1, 0x10); 1289 if (hc->slots == 128) 1290 HFC_outb(hc, R_PCM_MD1, 0x20); 1291 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); 1292 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 1293 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ 1294 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1295 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */ 1296 else 1297 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ 1298 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1299 for (i = 0; i < 256; i++) { 1300 HFC_outb_nodebug(hc, R_SLOT, i); 1301 HFC_outb_nodebug(hc, A_SL_CFG, 0); 1302 if (hc->ctype != HFC_TYPE_XHFC) 1303 HFC_outb_nodebug(hc, A_CONF, 0); 1304 hc->slot_owner[i] = -1; 1305 } 1306 1307 /* set clock speed */ 1308 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { 1309 if (debug & DEBUG_HFCMULTI_INIT) 1310 printk(KERN_DEBUG 1311 "%s: setting double clock\n", __func__); 1312 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1313 } 1314 1315 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1316 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */); 1317 1318 /* B410P GPIO */ 1319 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1320 printk(KERN_NOTICE "Setting GPIOs\n"); 1321 HFC_outb(hc, R_GPIO_SEL, 0x30); 1322 HFC_outb(hc, R_GPIO_EN1, 0x3); 1323 udelay(1000); 1324 printk(KERN_NOTICE "calling vpm_init\n"); 1325 vpm_init(hc); 1326 } 1327 1328 /* check if R_F0_CNT counts (8 kHz frame count) */ 1329 val = HFC_inb(hc, R_F0_CNTL); 1330 val += HFC_inb(hc, R_F0_CNTH) << 8; 1331 if (debug & DEBUG_HFCMULTI_INIT) 1332 printk(KERN_DEBUG 1333 "HFC_multi F0_CNT %ld after reset\n", val); 1334 spin_unlock_irqrestore(&hc->lock, flags); 1335 set_current_state(TASK_UNINTERRUPTIBLE); 1336 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */ 1337 spin_lock_irqsave(&hc->lock, flags); 1338 val2 = HFC_inb(hc, R_F0_CNTL); 1339 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1340 if (debug & DEBUG_HFCMULTI_INIT) 1341 printk(KERN_DEBUG 1342 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", 1343 val2); 1344 if (val2 >= val + 8) { /* 1 ms */ 1345 /* it counts, so we keep the pcm mode */ 1346 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1347 printk(KERN_INFO "controller is PCM bus MASTER\n"); 1348 else 1349 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) 1350 printk(KERN_INFO "controller is PCM bus SLAVE\n"); 1351 else { 1352 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 1353 printk(KERN_INFO "controller is PCM bus SLAVE " 1354 "(auto detected)\n"); 1355 } 1356 } else { 1357 /* does not count */ 1358 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 1359 controller_fail: 1360 printk(KERN_ERR "HFC_multi ERROR, getting no 125us " 1361 "pulse. Seems that controller fails.\n"); 1362 err = -EIO; 1363 goto out; 1364 } 1365 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1366 printk(KERN_INFO "controller is PCM bus SLAVE " 1367 "(ignoring missing PCM clock)\n"); 1368 } else { 1369 /* only one pcm master */ 1370 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 1371 && plxsd_master) { 1372 printk(KERN_ERR "HFC_multi ERROR, no clock " 1373 "on another Speech Design card found. " 1374 "Please be sure to connect PCM cable.\n"); 1375 err = -EIO; 1376 goto out; 1377 } 1378 /* retry with master clock */ 1379 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1380 spin_lock_irqsave(&plx_lock, plx_flags); 1381 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1382 pv = readl(plx_acc_32); 1383 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1384 pv |= PLX_SYNC_O_EN; 1385 writel(pv, plx_acc_32); 1386 spin_unlock_irqrestore(&plx_lock, plx_flags); 1387 if (debug & DEBUG_HFCMULTI_INIT) 1388 printk(KERN_DEBUG "%s: master: " 1389 "PLX_GPIO=%x\n", __func__, pv); 1390 } 1391 hc->hw.r_pcm_md0 |= V_PCM_MD; 1392 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1393 spin_unlock_irqrestore(&hc->lock, flags); 1394 set_current_state(TASK_UNINTERRUPTIBLE); 1395 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */ 1396 spin_lock_irqsave(&hc->lock, flags); 1397 val2 = HFC_inb(hc, R_F0_CNTL); 1398 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1399 if (debug & DEBUG_HFCMULTI_INIT) 1400 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " 1401 "10 ms (2nd try)\n", val2); 1402 if (val2 >= val + 8) { /* 1 ms */ 1403 test_and_set_bit(HFC_CHIP_PCM_MASTER, 1404 &hc->chip); 1405 printk(KERN_INFO "controller is PCM bus MASTER " 1406 "(auto detected)\n"); 1407 } else 1408 goto controller_fail; 1409 } 1410 } 1411 1412 /* Release the DSP Reset */ 1413 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1414 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1415 plxsd_master = 1; 1416 spin_lock_irqsave(&plx_lock, plx_flags); 1417 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1418 pv = readl(plx_acc_32); 1419 pv |= PLX_DSP_RES_N; 1420 writel(pv, plx_acc_32); 1421 spin_unlock_irqrestore(&plx_lock, plx_flags); 1422 if (debug & DEBUG_HFCMULTI_INIT) 1423 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n", 1424 __func__, pv); 1425 } 1426 1427 /* pcm id */ 1428 if (hc->pcm) 1429 printk(KERN_INFO "controller has given PCM BUS ID %d\n", 1430 hc->pcm); 1431 else { 1432 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) 1433 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1434 PCM_cnt++; /* SD has proprietary bridging */ 1435 } 1436 hc->pcm = PCM_cnt; 1437 printk(KERN_INFO "controller has PCM BUS ID %d " 1438 "(auto selected)\n", hc->pcm); 1439 } 1440 1441 /* set up timer */ 1442 HFC_outb(hc, R_TI_WD, poll_timer); 1443 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; 1444 1445 /* set E1 state machine IRQ */ 1446 if (hc->ctype == HFC_TYPE_E1) 1447 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; 1448 1449 /* set DTMF detection */ 1450 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { 1451 if (debug & DEBUG_HFCMULTI_INIT) 1452 printk(KERN_DEBUG "%s: enabling DTMF detection " 1453 "for all B-channel\n", __func__); 1454 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; 1455 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1456 hc->hw.r_dtmf |= V_ULAW_SEL; 1457 HFC_outb(hc, R_DTMF_N, 102 - 1); 1458 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; 1459 } 1460 1461 /* conference engine */ 1462 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1463 r_conf_en = V_CONF_EN | V_ULAW; 1464 else 1465 r_conf_en = V_CONF_EN; 1466 if (hc->ctype != HFC_TYPE_XHFC) 1467 HFC_outb(hc, R_CONF_EN, r_conf_en); 1468 1469 /* setting leds */ 1470 switch (hc->leds) { 1471 case 1: /* HFC-E1 OEM */ 1472 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 1473 HFC_outb(hc, R_GPIO_SEL, 0x32); 1474 else 1475 HFC_outb(hc, R_GPIO_SEL, 0x30); 1476 1477 HFC_outb(hc, R_GPIO_EN1, 0x0f); 1478 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1479 1480 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1481 break; 1482 1483 case 2: /* HFC-4S OEM */ 1484 case 3: 1485 HFC_outb(hc, R_GPIO_SEL, 0xf0); 1486 HFC_outb(hc, R_GPIO_EN1, 0xff); 1487 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1488 break; 1489 } 1490 1491 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) { 1492 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */ 1493 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1494 } 1495 1496 /* set master clock */ 1497 if (hc->masterclk >= 0) { 1498 if (debug & DEBUG_HFCMULTI_INIT) 1499 printk(KERN_DEBUG "%s: setting ST master clock " 1500 "to port %d (0..%d)\n", 1501 __func__, hc->masterclk, hc->ports - 1); 1502 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC); 1503 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1504 } 1505 1506 1507 1508 /* setting misc irq */ 1509 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); 1510 if (debug & DEBUG_HFCMULTI_INIT) 1511 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", 1512 hc->hw.r_irqmsk_misc); 1513 1514 /* RAM access test */ 1515 HFC_outb(hc, R_RAM_ADDR0, 0); 1516 HFC_outb(hc, R_RAM_ADDR1, 0); 1517 HFC_outb(hc, R_RAM_ADDR2, 0); 1518 for (i = 0; i < 256; i++) { 1519 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1520 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff)); 1521 } 1522 for (i = 0; i < 256; i++) { 1523 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1524 HFC_inb_nodebug(hc, R_RAM_DATA); 1525 rval = HFC_inb_nodebug(hc, R_INT_DATA); 1526 if (rval != ((i * 3) & 0xff)) { 1527 printk(KERN_DEBUG 1528 "addr:%x val:%x should:%x\n", i, rval, 1529 (i * 3) & 0xff); 1530 err++; 1531 } 1532 } 1533 if (err) { 1534 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); 1535 err = -EIO; 1536 goto out; 1537 } 1538 1539 if (debug & DEBUG_HFCMULTI_INIT) 1540 printk(KERN_DEBUG "%s: done\n", __func__); 1541 out: 1542 spin_unlock_irqrestore(&hc->lock, flags); 1543 return err; 1544 } 1545 1546 1547 /* 1548 * control the watchdog 1549 */ 1550 static void hfcmulti_watchdog(struct hfc_multi * hc)1551 hfcmulti_watchdog(struct hfc_multi *hc) 1552 { 1553 hc->wdcount++; 1554 1555 if (hc->wdcount > 10) { 1556 hc->wdcount = 0; 1557 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? 1558 V_GPIO_OUT3 : V_GPIO_OUT2; 1559 1560 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ 1561 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1562 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); 1563 } 1564 } 1565 1566 1567 1568 /* 1569 * output leds 1570 */ 1571 static void hfcmulti_leds(struct hfc_multi * hc)1572 hfcmulti_leds(struct hfc_multi *hc) 1573 { 1574 unsigned long lled; 1575 unsigned long leddw; 1576 int i, state, active, leds; 1577 struct dchannel *dch; 1578 int led[4]; 1579 1580 switch (hc->leds) { 1581 case 1: /* HFC-E1 OEM */ 1582 /* 2 red steady: LOS 1583 * 1 red steady: L1 not active 1584 * 2 green steady: L1 active 1585 * 1st green flashing: activity on TX 1586 * 2nd green flashing: activity on RX 1587 */ 1588 led[0] = 0; 1589 led[1] = 0; 1590 led[2] = 0; 1591 led[3] = 0; 1592 dch = hc->chan[hc->dnum[0]].dch; 1593 if (dch) { 1594 if (hc->chan[hc->dnum[0]].los) 1595 led[1] = 1; 1596 if (hc->e1_state != 1) { 1597 led[0] = 1; 1598 hc->flash[2] = 0; 1599 hc->flash[3] = 0; 1600 } else { 1601 led[2] = 1; 1602 led[3] = 1; 1603 if (!hc->flash[2] && hc->activity_tx) 1604 hc->flash[2] = poll; 1605 if (!hc->flash[3] && hc->activity_rx) 1606 hc->flash[3] = poll; 1607 if (hc->flash[2] && hc->flash[2] < 1024) 1608 led[2] = 0; 1609 if (hc->flash[3] && hc->flash[3] < 1024) 1610 led[3] = 0; 1611 if (hc->flash[2] >= 2048) 1612 hc->flash[2] = 0; 1613 if (hc->flash[3] >= 2048) 1614 hc->flash[3] = 0; 1615 if (hc->flash[2]) 1616 hc->flash[2] += poll; 1617 if (hc->flash[3]) 1618 hc->flash[3] += poll; 1619 } 1620 } 1621 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; 1622 /* leds are inverted */ 1623 if (leds != (int)hc->ledstate) { 1624 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); 1625 hc->ledstate = leds; 1626 } 1627 break; 1628 1629 case 2: /* HFC-4S OEM */ 1630 /* red steady: PH_DEACTIVATE 1631 * green steady: PH_ACTIVATE 1632 * green flashing: activity on TX 1633 */ 1634 for (i = 0; i < 4; i++) { 1635 state = 0; 1636 active = -1; 1637 dch = hc->chan[(i << 2) | 2].dch; 1638 if (dch) { 1639 state = dch->state; 1640 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1641 active = 3; 1642 else 1643 active = 7; 1644 } 1645 if (state) { 1646 if (state == active) { 1647 led[i] = 1; /* led green */ 1648 hc->activity_tx |= hc->activity_rx; 1649 if (!hc->flash[i] && 1650 (hc->activity_tx & (1 << i))) 1651 hc->flash[i] = poll; 1652 if (hc->flash[i] && hc->flash[i] < 1024) 1653 led[i] = 0; /* led off */ 1654 if (hc->flash[i] >= 2048) 1655 hc->flash[i] = 0; 1656 if (hc->flash[i]) 1657 hc->flash[i] += poll; 1658 } else { 1659 led[i] = 2; /* led red */ 1660 hc->flash[i] = 0; 1661 } 1662 } else 1663 led[i] = 0; /* led off */ 1664 } 1665 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1666 leds = 0; 1667 for (i = 0; i < 4; i++) { 1668 if (led[i] == 1) { 1669 /*green*/ 1670 leds |= (0x2 << (i * 2)); 1671 } else if (led[i] == 2) { 1672 /*red*/ 1673 leds |= (0x1 << (i * 2)); 1674 } 1675 } 1676 if (leds != (int)hc->ledstate) { 1677 vpm_out(hc, 0, 0x1a8 + 3, leds); 1678 hc->ledstate = leds; 1679 } 1680 } else { 1681 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | 1682 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | 1683 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | 1684 ((led[0] & 1) << 6) | ((led[2] & 1) << 7); 1685 if (leds != (int)hc->ledstate) { 1686 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); 1687 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); 1688 hc->ledstate = leds; 1689 } 1690 } 1691 break; 1692 1693 case 3: /* HFC 1S/2S Beronet */ 1694 /* red steady: PH_DEACTIVATE 1695 * green steady: PH_ACTIVATE 1696 * green flashing: activity on TX 1697 */ 1698 for (i = 0; i < 2; i++) { 1699 state = 0; 1700 active = -1; 1701 dch = hc->chan[(i << 2) | 2].dch; 1702 if (dch) { 1703 state = dch->state; 1704 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1705 active = 3; 1706 else 1707 active = 7; 1708 } 1709 if (state) { 1710 if (state == active) { 1711 led[i] = 1; /* led green */ 1712 hc->activity_tx |= hc->activity_rx; 1713 if (!hc->flash[i] && 1714 (hc->activity_tx & (1 << i))) 1715 hc->flash[i] = poll; 1716 if (hc->flash[i] < 1024) 1717 led[i] = 0; /* led off */ 1718 if (hc->flash[i] >= 2048) 1719 hc->flash[i] = 0; 1720 if (hc->flash[i]) 1721 hc->flash[i] += poll; 1722 } else { 1723 led[i] = 2; /* led red */ 1724 hc->flash[i] = 0; 1725 } 1726 } else 1727 led[i] = 0; /* led off */ 1728 } 1729 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2) 1730 | ((led[1]&1) << 3); 1731 if (leds != (int)hc->ledstate) { 1732 HFC_outb_nodebug(hc, R_GPIO_EN1, 1733 ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); 1734 HFC_outb_nodebug(hc, R_GPIO_OUT1, 1735 ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); 1736 hc->ledstate = leds; 1737 } 1738 break; 1739 case 8: /* HFC 8S+ Beronet */ 1740 /* off: PH_DEACTIVATE 1741 * steady: PH_ACTIVATE 1742 * flashing: activity on TX 1743 */ 1744 lled = 0xff; /* leds off */ 1745 for (i = 0; i < 8; i++) { 1746 state = 0; 1747 active = -1; 1748 dch = hc->chan[(i << 2) | 2].dch; 1749 if (dch) { 1750 state = dch->state; 1751 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1752 active = 3; 1753 else 1754 active = 7; 1755 } 1756 if (state) { 1757 if (state == active) { 1758 lled &= ~(1 << i); /* led on */ 1759 hc->activity_tx |= hc->activity_rx; 1760 if (!hc->flash[i] && 1761 (hc->activity_tx & (1 << i))) 1762 hc->flash[i] = poll; 1763 if (hc->flash[i] < 1024) 1764 lled |= 1 << i; /* led off */ 1765 if (hc->flash[i] >= 2048) 1766 hc->flash[i] = 0; 1767 if (hc->flash[i]) 1768 hc->flash[i] += poll; 1769 } else 1770 hc->flash[i] = 0; 1771 } 1772 } 1773 leddw = lled << 24 | lled << 16 | lled << 8 | lled; 1774 if (leddw != hc->ledstate) { 1775 /* HFC_outb(hc, R_BRG_PCM_CFG, 1); 1776 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ 1777 /* was _io before */ 1778 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 1779 outw(0x4000, hc->pci_iobase + 4); 1780 outl(leddw, hc->pci_iobase); 1781 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1782 hc->ledstate = leddw; 1783 } 1784 break; 1785 } 1786 hc->activity_tx = 0; 1787 hc->activity_rx = 0; 1788 } 1789 /* 1790 * read dtmf coefficients 1791 */ 1792 1793 static void hfcmulti_dtmf(struct hfc_multi * hc)1794 hfcmulti_dtmf(struct hfc_multi *hc) 1795 { 1796 s32 *coeff; 1797 u_int mantissa; 1798 int co, ch; 1799 struct bchannel *bch = NULL; 1800 u8 exponent; 1801 int dtmf = 0; 1802 int addr; 1803 u16 w_float; 1804 struct sk_buff *skb; 1805 struct mISDNhead *hh; 1806 1807 if (debug & DEBUG_HFCMULTI_DTMF) 1808 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); 1809 for (ch = 0; ch <= 31; ch++) { 1810 /* only process enabled B-channels */ 1811 bch = hc->chan[ch].bch; 1812 if (!bch) 1813 continue; 1814 if (!hc->created[hc->chan[ch].port]) 1815 continue; 1816 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 1817 continue; 1818 if (debug & DEBUG_HFCMULTI_DTMF) 1819 printk(KERN_DEBUG "%s: dtmf channel %d:", 1820 __func__, ch); 1821 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); 1822 dtmf = 1; 1823 for (co = 0; co < 8; co++) { 1824 /* read W(n-1) coefficient */ 1825 addr = hc->DTMFbase + ((co << 7) | (ch << 2)); 1826 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); 1827 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8); 1828 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16) 1829 | V_ADDR_INC); 1830 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1831 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1832 if (debug & DEBUG_HFCMULTI_DTMF) 1833 printk(" %04x", w_float); 1834 1835 /* decode float (see chip doc) */ 1836 mantissa = w_float & 0x0fff; 1837 if (w_float & 0x8000) 1838 mantissa |= 0xfffff000; 1839 exponent = (w_float >> 12) & 0x7; 1840 if (exponent) { 1841 mantissa ^= 0x1000; 1842 mantissa <<= (exponent - 1); 1843 } 1844 1845 /* store coefficient */ 1846 coeff[co << 1] = mantissa; 1847 1848 /* read W(n) coefficient */ 1849 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1850 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1851 if (debug & DEBUG_HFCMULTI_DTMF) 1852 printk(" %04x", w_float); 1853 1854 /* decode float (see chip doc) */ 1855 mantissa = w_float & 0x0fff; 1856 if (w_float & 0x8000) 1857 mantissa |= 0xfffff000; 1858 exponent = (w_float >> 12) & 0x7; 1859 if (exponent) { 1860 mantissa ^= 0x1000; 1861 mantissa <<= (exponent - 1); 1862 } 1863 1864 /* store coefficient */ 1865 coeff[(co << 1) | 1] = mantissa; 1866 } 1867 if (debug & DEBUG_HFCMULTI_DTMF) 1868 printk(" DTMF ready %08x %08x %08x %08x " 1869 "%08x %08x %08x %08x\n", 1870 coeff[0], coeff[1], coeff[2], coeff[3], 1871 coeff[4], coeff[5], coeff[6], coeff[7]); 1872 hc->chan[ch].coeff_count++; 1873 if (hc->chan[ch].coeff_count == 8) { 1874 hc->chan[ch].coeff_count = 0; 1875 skb = mI_alloc_skb(512, GFP_ATOMIC); 1876 if (!skb) { 1877 printk(KERN_DEBUG "%s: No memory for skb\n", 1878 __func__); 1879 continue; 1880 } 1881 hh = mISDN_HEAD_P(skb); 1882 hh->prim = PH_CONTROL_IND; 1883 hh->id = DTMF_HFC_COEF; 1884 skb_put_data(skb, hc->chan[ch].coeff, 512); 1885 recv_Bchannel_skb(bch, skb); 1886 } 1887 } 1888 1889 /* restart DTMF processing */ 1890 hc->dtmf = dtmf; 1891 if (dtmf) 1892 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); 1893 } 1894 1895 1896 /* 1897 * fill fifo as much as possible 1898 */ 1899 1900 static void hfcmulti_tx(struct hfc_multi * hc,int ch)1901 hfcmulti_tx(struct hfc_multi *hc, int ch) 1902 { 1903 int i, ii, temp, tmp_len, len = 0; 1904 int Zspace, z1, z2; /* must be int for calculation */ 1905 int Fspace, f1, f2; 1906 u_char *d; 1907 int *txpending, slot_tx; 1908 struct bchannel *bch; 1909 struct dchannel *dch; 1910 struct sk_buff **sp = NULL; 1911 int *idxp; 1912 1913 bch = hc->chan[ch].bch; 1914 dch = hc->chan[ch].dch; 1915 if ((!dch) && (!bch)) 1916 return; 1917 1918 txpending = &hc->chan[ch].txpending; 1919 slot_tx = hc->chan[ch].slot_tx; 1920 if (dch) { 1921 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 1922 return; 1923 sp = &dch->tx_skb; 1924 idxp = &dch->tx_idx; 1925 } else { 1926 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 1927 return; 1928 sp = &bch->tx_skb; 1929 idxp = &bch->tx_idx; 1930 } 1931 if (*sp) 1932 len = (*sp)->len; 1933 1934 if ((!len) && *txpending != 1) 1935 return; /* no data */ 1936 1937 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 1938 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 1939 (hc->chan[ch].slot_rx < 0) && 1940 (hc->chan[ch].slot_tx < 0)) 1941 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); 1942 else 1943 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 1944 HFC_wait_nodebug(hc); 1945 1946 if (*txpending == 2) { 1947 /* reset fifo */ 1948 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 1949 HFC_wait_nodebug(hc); 1950 HFC_outb(hc, A_SUBCH_CFG, 0); 1951 *txpending = 1; 1952 } 1953 next_frame: 1954 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 1955 f1 = HFC_inb_nodebug(hc, A_F1); 1956 f2 = HFC_inb_nodebug(hc, A_F2); 1957 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { 1958 if (debug & DEBUG_HFCMULTI_FIFO) 1959 printk(KERN_DEBUG 1960 "%s(card %d): reread f2 because %d!=%d\n", 1961 __func__, hc->id + 1, temp, f2); 1962 f2 = temp; /* repeat until F2 is equal */ 1963 } 1964 Fspace = f2 - f1 - 1; 1965 if (Fspace < 0) 1966 Fspace += hc->Flen; 1967 /* 1968 * Old FIFO handling doesn't give us the current Z2 read 1969 * pointer, so we cannot send the next frame before the fifo 1970 * is empty. It makes no difference except for a slightly 1971 * lower performance. 1972 */ 1973 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { 1974 if (f1 != f2) 1975 Fspace = 0; 1976 else 1977 Fspace = 1; 1978 } 1979 /* one frame only for ST D-channels, to allow resending */ 1980 if (hc->ctype != HFC_TYPE_E1 && dch) { 1981 if (f1 != f2) 1982 Fspace = 0; 1983 } 1984 /* F-counter full condition */ 1985 if (Fspace == 0) 1986 return; 1987 } 1988 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 1989 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 1990 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { 1991 if (debug & DEBUG_HFCMULTI_FIFO) 1992 printk(KERN_DEBUG "%s(card %d): reread z2 because " 1993 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 1994 z2 = temp; /* repeat unti Z2 is equal */ 1995 } 1996 hc->chan[ch].Zfill = z1 - z2; 1997 if (hc->chan[ch].Zfill < 0) 1998 hc->chan[ch].Zfill += hc->Zlen; 1999 Zspace = z2 - z1; 2000 if (Zspace <= 0) 2001 Zspace += hc->Zlen; 2002 Zspace -= 4; /* keep not too full, so pointers will not overrun */ 2003 /* fill transparent data only to maxinum transparent load (minus 4) */ 2004 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2005 Zspace = Zspace - hc->Zlen + hc->max_trans; 2006 if (Zspace <= 0) /* no space of 4 bytes */ 2007 return; 2008 2009 /* if no data */ 2010 if (!len) { 2011 if (z1 == z2) { /* empty */ 2012 /* if done with FIFO audio data during PCM connection */ 2013 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && 2014 *txpending && slot_tx >= 0) { 2015 if (debug & DEBUG_HFCMULTI_MODE) 2016 printk(KERN_DEBUG 2017 "%s: reconnecting PCM due to no " 2018 "more FIFO data: channel %d " 2019 "slot_tx %d\n", 2020 __func__, ch, slot_tx); 2021 /* connect slot */ 2022 if (hc->ctype == HFC_TYPE_XHFC) 2023 HFC_outb(hc, A_CON_HDLC, 0xc0 2024 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2025 /* Enable FIFO, no interrupt */ 2026 else 2027 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2028 V_HDLC_TRP | V_IFF); 2029 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1); 2030 HFC_wait_nodebug(hc); 2031 if (hc->ctype == HFC_TYPE_XHFC) 2032 HFC_outb(hc, A_CON_HDLC, 0xc0 2033 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2034 /* Enable FIFO, no interrupt */ 2035 else 2036 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2037 V_HDLC_TRP | V_IFF); 2038 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 2039 HFC_wait_nodebug(hc); 2040 } 2041 *txpending = 0; 2042 } 2043 return; /* no data */ 2044 } 2045 2046 /* "fill fifo if empty" feature */ 2047 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags) 2048 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) { 2049 if (debug & DEBUG_HFCMULTI_FILL) 2050 printk(KERN_DEBUG "%s: buffer empty, so we have " 2051 "underrun\n", __func__); 2052 /* fill buffer, to prevent future underrun */ 2053 hc->write_fifo(hc, hc->silence_data, poll >> 1); 2054 Zspace -= (poll >> 1); 2055 } 2056 2057 /* if audio data and connected slot */ 2058 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) 2059 && slot_tx >= 0) { 2060 if (debug & DEBUG_HFCMULTI_MODE) 2061 printk(KERN_DEBUG "%s: disconnecting PCM due to " 2062 "FIFO data: channel %d slot_tx %d\n", 2063 __func__, ch, slot_tx); 2064 /* disconnect slot */ 2065 if (hc->ctype == HFC_TYPE_XHFC) 2066 HFC_outb(hc, A_CON_HDLC, 0x80 2067 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2068 /* Enable FIFO, no interrupt */ 2069 else 2070 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2071 V_HDLC_TRP | V_IFF); 2072 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1); 2073 HFC_wait_nodebug(hc); 2074 if (hc->ctype == HFC_TYPE_XHFC) 2075 HFC_outb(hc, A_CON_HDLC, 0x80 2076 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2077 /* Enable FIFO, no interrupt */ 2078 else 2079 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2080 V_HDLC_TRP | V_IFF); 2081 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 2082 HFC_wait_nodebug(hc); 2083 } 2084 *txpending = 1; 2085 2086 /* show activity */ 2087 if (dch) 2088 hc->activity_tx |= 1 << hc->chan[ch].port; 2089 2090 /* fill fifo to what we have left */ 2091 ii = len; 2092 if (dch || test_bit(FLG_HDLC, &bch->Flags)) 2093 temp = 1; 2094 else 2095 temp = 0; 2096 i = *idxp; 2097 d = (*sp)->data + i; 2098 if (ii - i > Zspace) 2099 ii = Zspace + i; 2100 if (debug & DEBUG_HFCMULTI_FIFO) 2101 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " 2102 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", 2103 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, 2104 temp ? "HDLC" : "TRANS"); 2105 2106 /* Have to prep the audio data */ 2107 hc->write_fifo(hc, d, ii - i); 2108 hc->chan[ch].Zfill += ii - i; 2109 *idxp = ii; 2110 2111 /* if not all data has been written */ 2112 if (ii != len) { 2113 /* NOTE: fifo is started by the calling function */ 2114 return; 2115 } 2116 2117 /* if all data has been written, terminate frame */ 2118 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2119 /* increment f-counter */ 2120 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2121 HFC_wait_nodebug(hc); 2122 } 2123 2124 tmp_len = (*sp)->len; 2125 dev_kfree_skb(*sp); 2126 /* check for next frame */ 2127 if (bch && get_next_bframe(bch)) { 2128 len = tmp_len; 2129 goto next_frame; 2130 } 2131 if (dch && get_next_dframe(dch)) { 2132 len = tmp_len; 2133 goto next_frame; 2134 } 2135 2136 /* 2137 * now we have no more data, so in case of transparent, 2138 * we set the last byte in fifo to 'silence' in case we will get 2139 * no more data at all. this prevents sending an undefined value. 2140 */ 2141 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2142 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 2143 } 2144 2145 2146 /* NOTE: only called if E1 card is in active state */ 2147 static void hfcmulti_rx(struct hfc_multi * hc,int ch)2148 hfcmulti_rx(struct hfc_multi *hc, int ch) 2149 { 2150 int temp; 2151 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ 2152 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ 2153 int again = 0; 2154 struct bchannel *bch; 2155 struct dchannel *dch = NULL; 2156 struct sk_buff *skb, **sp = NULL; 2157 int maxlen; 2158 2159 bch = hc->chan[ch].bch; 2160 if (bch) { 2161 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 2162 return; 2163 } else if (hc->chan[ch].dch) { 2164 dch = hc->chan[ch].dch; 2165 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 2166 return; 2167 } else { 2168 return; 2169 } 2170 next_frame: 2171 /* on first AND before getting next valid frame, R_FIFO must be written 2172 to. */ 2173 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2174 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 2175 (hc->chan[ch].slot_rx < 0) && 2176 (hc->chan[ch].slot_tx < 0)) 2177 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1); 2178 else 2179 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1); 2180 HFC_wait_nodebug(hc); 2181 2182 /* ignore if rx is off BUT change fifo (above) to start pending TX */ 2183 if (hc->chan[ch].rx_off) { 2184 if (bch) 2185 bch->dropcnt += poll; /* not exact but fair enough */ 2186 return; 2187 } 2188 2189 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2190 f1 = HFC_inb_nodebug(hc, A_F1); 2191 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { 2192 if (debug & DEBUG_HFCMULTI_FIFO) 2193 printk(KERN_DEBUG 2194 "%s(card %d): reread f1 because %d!=%d\n", 2195 __func__, hc->id + 1, temp, f1); 2196 f1 = temp; /* repeat until F1 is equal */ 2197 } 2198 f2 = HFC_inb_nodebug(hc, A_F2); 2199 } 2200 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 2201 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { 2202 if (debug & DEBUG_HFCMULTI_FIFO) 2203 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2204 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2205 z1 = temp; /* repeat until Z1 is equal */ 2206 } 2207 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 2208 Zsize = z1 - z2; 2209 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) 2210 /* complete hdlc frame */ 2211 Zsize++; 2212 if (Zsize < 0) 2213 Zsize += hc->Zlen; 2214 /* if buffer is empty */ 2215 if (Zsize <= 0) 2216 return; 2217 2218 if (bch) { 2219 maxlen = bchannel_get_rxbuf(bch, Zsize); 2220 if (maxlen < 0) { 2221 pr_warn("card%d.B%d: No bufferspace for %d bytes\n", 2222 hc->id + 1, bch->nr, Zsize); 2223 return; 2224 } 2225 sp = &bch->rx_skb; 2226 maxlen = bch->maxlen; 2227 } else { /* Dchannel */ 2228 sp = &dch->rx_skb; 2229 maxlen = dch->maxlen + 3; 2230 if (*sp == NULL) { 2231 *sp = mI_alloc_skb(maxlen, GFP_ATOMIC); 2232 if (*sp == NULL) { 2233 pr_warn("card%d: No mem for dch rx_skb\n", 2234 hc->id + 1); 2235 return; 2236 } 2237 } 2238 } 2239 /* show activity */ 2240 if (dch) 2241 hc->activity_rx |= 1 << hc->chan[ch].port; 2242 2243 /* empty fifo with what we have */ 2244 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2245 if (debug & DEBUG_HFCMULTI_FIFO) 2246 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " 2247 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " 2248 "got=%d (again %d)\n", __func__, hc->id + 1, ch, 2249 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", 2250 f1, f2, Zsize + (*sp)->len, again); 2251 /* HDLC */ 2252 if ((Zsize + (*sp)->len) > maxlen) { 2253 if (debug & DEBUG_HFCMULTI_FIFO) 2254 printk(KERN_DEBUG 2255 "%s(card %d): hdlc-frame too large.\n", 2256 __func__, hc->id + 1); 2257 skb_trim(*sp, 0); 2258 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 2259 HFC_wait_nodebug(hc); 2260 return; 2261 } 2262 2263 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2264 2265 if (f1 != f2) { 2266 /* increment Z2,F2-counter */ 2267 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2268 HFC_wait_nodebug(hc); 2269 /* check size */ 2270 if ((*sp)->len < 4) { 2271 if (debug & DEBUG_HFCMULTI_FIFO) 2272 printk(KERN_DEBUG 2273 "%s(card %d): Frame below minimum " 2274 "size\n", __func__, hc->id + 1); 2275 skb_trim(*sp, 0); 2276 goto next_frame; 2277 } 2278 /* there is at least one complete frame, check crc */ 2279 if ((*sp)->data[(*sp)->len - 1]) { 2280 if (debug & DEBUG_HFCMULTI_CRC) 2281 printk(KERN_DEBUG 2282 "%s: CRC-error\n", __func__); 2283 skb_trim(*sp, 0); 2284 goto next_frame; 2285 } 2286 skb_trim(*sp, (*sp)->len - 3); 2287 if ((*sp)->len < MISDN_COPY_SIZE) { 2288 skb = *sp; 2289 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2290 if (*sp) { 2291 skb_put_data(*sp, skb->data, skb->len); 2292 skb_trim(skb, 0); 2293 } else { 2294 printk(KERN_DEBUG "%s: No mem\n", 2295 __func__); 2296 *sp = skb; 2297 skb = NULL; 2298 } 2299 } else { 2300 skb = NULL; 2301 } 2302 if (debug & DEBUG_HFCMULTI_FIFO) { 2303 printk(KERN_DEBUG "%s(card %d):", 2304 __func__, hc->id + 1); 2305 temp = 0; 2306 while (temp < (*sp)->len) 2307 printk(" %02x", (*sp)->data[temp++]); 2308 printk("\n"); 2309 } 2310 if (dch) 2311 recv_Dchannel(dch); 2312 else 2313 recv_Bchannel(bch, MISDN_ID_ANY, false); 2314 *sp = skb; 2315 again++; 2316 goto next_frame; 2317 } 2318 /* there is an incomplete frame */ 2319 } else { 2320 /* transparent */ 2321 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2322 if (debug & DEBUG_HFCMULTI_FIFO) 2323 printk(KERN_DEBUG 2324 "%s(card %d): fifo(%d) reading %d bytes " 2325 "(z1=%04x, z2=%04x) TRANS\n", 2326 __func__, hc->id + 1, ch, Zsize, z1, z2); 2327 /* only bch is transparent */ 2328 recv_Bchannel(bch, hc->chan[ch].Zfill, false); 2329 } 2330 } 2331 2332 2333 /* 2334 * Interrupt handler 2335 */ 2336 static void signal_state_up(struct dchannel * dch,int info,char * msg)2337 signal_state_up(struct dchannel *dch, int info, char *msg) 2338 { 2339 struct sk_buff *skb; 2340 int id, data = info; 2341 2342 if (debug & DEBUG_HFCMULTI_STATE) 2343 printk(KERN_DEBUG "%s: %s\n", __func__, msg); 2344 2345 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ 2346 2347 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, 2348 GFP_ATOMIC); 2349 if (!skb) 2350 return; 2351 recv_Dchannel_skb(dch, skb); 2352 } 2353 2354 static inline void handle_timer_irq(struct hfc_multi * hc)2355 handle_timer_irq(struct hfc_multi *hc) 2356 { 2357 int ch, temp; 2358 struct dchannel *dch; 2359 u_long flags; 2360 2361 /* process queued resync jobs */ 2362 if (hc->e1_resync) { 2363 /* lock, so e1_resync gets not changed */ 2364 spin_lock_irqsave(&HFClock, flags); 2365 if (hc->e1_resync & 1) { 2366 if (debug & DEBUG_HFCMULTI_PLXSD) 2367 printk(KERN_DEBUG "Enable SYNC_I\n"); 2368 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); 2369 /* disable JATT, if RX_SYNC is set */ 2370 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 2371 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 2372 } 2373 if (hc->e1_resync & 2) { 2374 if (debug & DEBUG_HFCMULTI_PLXSD) 2375 printk(KERN_DEBUG "Enable jatt PLL\n"); 2376 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 2377 } 2378 if (hc->e1_resync & 4) { 2379 if (debug & DEBUG_HFCMULTI_PLXSD) 2380 printk(KERN_DEBUG 2381 "Enable QUARTZ for HFC-E1\n"); 2382 /* set jatt to quartz */ 2383 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC 2384 | V_JATT_OFF); 2385 /* switch to JATT, in case it is not already */ 2386 HFC_outb(hc, R_SYNC_OUT, 0); 2387 } 2388 hc->e1_resync = 0; 2389 spin_unlock_irqrestore(&HFClock, flags); 2390 } 2391 2392 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1) 2393 for (ch = 0; ch <= 31; ch++) { 2394 if (hc->created[hc->chan[ch].port]) { 2395 hfcmulti_tx(hc, ch); 2396 /* fifo is started when switching to rx-fifo */ 2397 hfcmulti_rx(hc, ch); 2398 if (hc->chan[ch].dch && 2399 hc->chan[ch].nt_timer > -1) { 2400 dch = hc->chan[ch].dch; 2401 if (!(--hc->chan[ch].nt_timer)) { 2402 schedule_event(dch, 2403 FLG_PHCHANGE); 2404 if (debug & 2405 DEBUG_HFCMULTI_STATE) 2406 printk(KERN_DEBUG 2407 "%s: nt_timer at " 2408 "state %x\n", 2409 __func__, 2410 dch->state); 2411 } 2412 } 2413 } 2414 } 2415 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) { 2416 dch = hc->chan[hc->dnum[0]].dch; 2417 /* LOS */ 2418 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; 2419 hc->chan[hc->dnum[0]].los = temp; 2420 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) { 2421 if (!temp && hc->chan[hc->dnum[0]].los) 2422 signal_state_up(dch, L1_SIGNAL_LOS_ON, 2423 "LOS detected"); 2424 if (temp && !hc->chan[hc->dnum[0]].los) 2425 signal_state_up(dch, L1_SIGNAL_LOS_OFF, 2426 "LOS gone"); 2427 } 2428 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) { 2429 /* AIS */ 2430 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; 2431 if (!temp && hc->chan[hc->dnum[0]].ais) 2432 signal_state_up(dch, L1_SIGNAL_AIS_ON, 2433 "AIS detected"); 2434 if (temp && !hc->chan[hc->dnum[0]].ais) 2435 signal_state_up(dch, L1_SIGNAL_AIS_OFF, 2436 "AIS gone"); 2437 hc->chan[hc->dnum[0]].ais = temp; 2438 } 2439 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) { 2440 /* SLIP */ 2441 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; 2442 if (!temp && hc->chan[hc->dnum[0]].slip_rx) 2443 signal_state_up(dch, L1_SIGNAL_SLIP_RX, 2444 " bit SLIP detected RX"); 2445 hc->chan[hc->dnum[0]].slip_rx = temp; 2446 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; 2447 if (!temp && hc->chan[hc->dnum[0]].slip_tx) 2448 signal_state_up(dch, L1_SIGNAL_SLIP_TX, 2449 " bit SLIP detected TX"); 2450 hc->chan[hc->dnum[0]].slip_tx = temp; 2451 } 2452 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) { 2453 /* RDI */ 2454 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; 2455 if (!temp && hc->chan[hc->dnum[0]].rdi) 2456 signal_state_up(dch, L1_SIGNAL_RDI_ON, 2457 "RDI detected"); 2458 if (temp && !hc->chan[hc->dnum[0]].rdi) 2459 signal_state_up(dch, L1_SIGNAL_RDI_OFF, 2460 "RDI gone"); 2461 hc->chan[hc->dnum[0]].rdi = temp; 2462 } 2463 temp = HFC_inb_nodebug(hc, R_JATT_DIR); 2464 switch (hc->chan[hc->dnum[0]].sync) { 2465 case 0: 2466 if ((temp & 0x60) == 0x60) { 2467 if (debug & DEBUG_HFCMULTI_SYNC) 2468 printk(KERN_DEBUG 2469 "%s: (id=%d) E1 now " 2470 "in clock sync\n", 2471 __func__, hc->id); 2472 HFC_outb(hc, R_RX_OFF, 2473 hc->chan[hc->dnum[0]].jitter | V_RX_INIT); 2474 HFC_outb(hc, R_TX_OFF, 2475 hc->chan[hc->dnum[0]].jitter | V_RX_INIT); 2476 hc->chan[hc->dnum[0]].sync = 1; 2477 goto check_framesync; 2478 } 2479 break; 2480 case 1: 2481 if ((temp & 0x60) != 0x60) { 2482 if (debug & DEBUG_HFCMULTI_SYNC) 2483 printk(KERN_DEBUG 2484 "%s: (id=%d) E1 " 2485 "lost clock sync\n", 2486 __func__, hc->id); 2487 hc->chan[hc->dnum[0]].sync = 0; 2488 break; 2489 } 2490 check_framesync: 2491 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2492 if (temp == 0x27) { 2493 if (debug & DEBUG_HFCMULTI_SYNC) 2494 printk(KERN_DEBUG 2495 "%s: (id=%d) E1 " 2496 "now in frame sync\n", 2497 __func__, hc->id); 2498 hc->chan[hc->dnum[0]].sync = 2; 2499 } 2500 break; 2501 case 2: 2502 if ((temp & 0x60) != 0x60) { 2503 if (debug & DEBUG_HFCMULTI_SYNC) 2504 printk(KERN_DEBUG 2505 "%s: (id=%d) E1 lost " 2506 "clock & frame sync\n", 2507 __func__, hc->id); 2508 hc->chan[hc->dnum[0]].sync = 0; 2509 break; 2510 } 2511 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2512 if (temp != 0x27) { 2513 if (debug & DEBUG_HFCMULTI_SYNC) 2514 printk(KERN_DEBUG 2515 "%s: (id=%d) E1 " 2516 "lost frame sync\n", 2517 __func__, hc->id); 2518 hc->chan[hc->dnum[0]].sync = 1; 2519 } 2520 break; 2521 } 2522 } 2523 2524 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 2525 hfcmulti_watchdog(hc); 2526 2527 if (hc->leds) 2528 hfcmulti_leds(hc); 2529 } 2530 2531 static void ph_state_irq(struct hfc_multi * hc,u_char r_irq_statech)2532 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) 2533 { 2534 struct dchannel *dch; 2535 int ch; 2536 int active; 2537 u_char st_status, temp; 2538 2539 /* state machine */ 2540 for (ch = 0; ch <= 31; ch++) { 2541 if (hc->chan[ch].dch) { 2542 dch = hc->chan[ch].dch; 2543 if (r_irq_statech & 1) { 2544 HFC_outb_nodebug(hc, R_ST_SEL, 2545 hc->chan[ch].port); 2546 /* undocumented: delay after R_ST_SEL */ 2547 udelay(1); 2548 /* undocumented: status changes during read */ 2549 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); 2550 while (st_status != (temp = 2551 HFC_inb_nodebug(hc, A_ST_RD_STATE))) { 2552 if (debug & DEBUG_HFCMULTI_STATE) 2553 printk(KERN_DEBUG "%s: reread " 2554 "STATE because %d!=%d\n", 2555 __func__, temp, 2556 st_status); 2557 st_status = temp; /* repeat */ 2558 } 2559 2560 /* Speech Design TE-sync indication */ 2561 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && 2562 dch->dev.D.protocol == ISDN_P_TE_S0) { 2563 if (st_status & V_FR_SYNC_ST) 2564 hc->syncronized |= 2565 (1 << hc->chan[ch].port); 2566 else 2567 hc->syncronized &= 2568 ~(1 << hc->chan[ch].port); 2569 } 2570 dch->state = st_status & 0x0f; 2571 if (dch->dev.D.protocol == ISDN_P_NT_S0) 2572 active = 3; 2573 else 2574 active = 7; 2575 if (dch->state == active) { 2576 HFC_outb_nodebug(hc, R_FIFO, 2577 (ch << 1) | 1); 2578 HFC_wait_nodebug(hc); 2579 HFC_outb_nodebug(hc, 2580 R_INC_RES_FIFO, V_RES_F); 2581 HFC_wait_nodebug(hc); 2582 dch->tx_idx = 0; 2583 } 2584 schedule_event(dch, FLG_PHCHANGE); 2585 if (debug & DEBUG_HFCMULTI_STATE) 2586 printk(KERN_DEBUG 2587 "%s: S/T newstate %x port %d\n", 2588 __func__, dch->state, 2589 hc->chan[ch].port); 2590 } 2591 r_irq_statech >>= 1; 2592 } 2593 } 2594 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2595 plxsd_checksync(hc, 0); 2596 } 2597 2598 static void fifo_irq(struct hfc_multi * hc,int block)2599 fifo_irq(struct hfc_multi *hc, int block) 2600 { 2601 int ch, j; 2602 struct dchannel *dch; 2603 struct bchannel *bch; 2604 u_char r_irq_fifo_bl; 2605 2606 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); 2607 j = 0; 2608 while (j < 8) { 2609 ch = (block << 2) + (j >> 1); 2610 dch = hc->chan[ch].dch; 2611 bch = hc->chan[ch].bch; 2612 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { 2613 j += 2; 2614 continue; 2615 } 2616 if (dch && (r_irq_fifo_bl & (1 << j)) && 2617 test_bit(FLG_ACTIVE, &dch->Flags)) { 2618 hfcmulti_tx(hc, ch); 2619 /* start fifo */ 2620 HFC_outb_nodebug(hc, R_FIFO, 0); 2621 HFC_wait_nodebug(hc); 2622 } 2623 if (bch && (r_irq_fifo_bl & (1 << j)) && 2624 test_bit(FLG_ACTIVE, &bch->Flags)) { 2625 hfcmulti_tx(hc, ch); 2626 /* start fifo */ 2627 HFC_outb_nodebug(hc, R_FIFO, 0); 2628 HFC_wait_nodebug(hc); 2629 } 2630 j++; 2631 if (dch && (r_irq_fifo_bl & (1 << j)) && 2632 test_bit(FLG_ACTIVE, &dch->Flags)) { 2633 hfcmulti_rx(hc, ch); 2634 } 2635 if (bch && (r_irq_fifo_bl & (1 << j)) && 2636 test_bit(FLG_ACTIVE, &bch->Flags)) { 2637 hfcmulti_rx(hc, ch); 2638 } 2639 j++; 2640 } 2641 } 2642 2643 #ifdef IRQ_DEBUG 2644 int irqsem; 2645 #endif 2646 static irqreturn_t hfcmulti_interrupt(int intno,void * dev_id)2647 hfcmulti_interrupt(int intno, void *dev_id) 2648 { 2649 #ifdef IRQCOUNT_DEBUG 2650 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, 2651 iq5 = 0, iq6 = 0, iqcnt = 0; 2652 #endif 2653 struct hfc_multi *hc = dev_id; 2654 struct dchannel *dch; 2655 u_char r_irq_statech, status, r_irq_misc, r_irq_oview; 2656 int i; 2657 void __iomem *plx_acc; 2658 u_short wval; 2659 u_char e1_syncsta, temp, temp2; 2660 u_long flags; 2661 2662 if (!hc) { 2663 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); 2664 return IRQ_NONE; 2665 } 2666 2667 spin_lock(&hc->lock); 2668 2669 #ifdef IRQ_DEBUG 2670 if (irqsem) 2671 printk(KERN_ERR "irq for card %d during irq from " 2672 "card %d, this is no bug.\n", hc->id + 1, irqsem); 2673 irqsem = hc->id + 1; 2674 #endif 2675 #ifdef CONFIG_MISDN_HFCMULTI_8xx 2676 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk) 2677 goto irq_notforus; 2678 #endif 2679 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 2680 spin_lock_irqsave(&plx_lock, flags); 2681 plx_acc = hc->plx_membase + PLX_INTCSR; 2682 wval = readw(plx_acc); 2683 spin_unlock_irqrestore(&plx_lock, flags); 2684 if (!(wval & PLX_INTCSR_LINTI1_STATUS)) 2685 goto irq_notforus; 2686 } 2687 2688 status = HFC_inb_nodebug(hc, R_STATUS); 2689 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); 2690 #ifdef IRQCOUNT_DEBUG 2691 if (r_irq_statech) 2692 iq1++; 2693 if (status & V_DTMF_STA) 2694 iq2++; 2695 if (status & V_LOST_STA) 2696 iq3++; 2697 if (status & V_EXT_IRQSTA) 2698 iq4++; 2699 if (status & V_MISC_IRQSTA) 2700 iq5++; 2701 if (status & V_FR_IRQSTA) 2702 iq6++; 2703 if (iqcnt++ > 5000) { 2704 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", 2705 iq1, iq2, iq3, iq4, iq5, iq6); 2706 iqcnt = 0; 2707 } 2708 #endif 2709 2710 if (!r_irq_statech && 2711 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | 2712 V_MISC_IRQSTA | V_FR_IRQSTA))) { 2713 /* irq is not for us */ 2714 goto irq_notforus; 2715 } 2716 hc->irqcnt++; 2717 if (r_irq_statech) { 2718 if (hc->ctype != HFC_TYPE_E1) 2719 ph_state_irq(hc, r_irq_statech); 2720 } 2721 if (status & V_LOST_STA) { 2722 /* LOST IRQ */ 2723 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ 2724 } 2725 if (status & V_MISC_IRQSTA) { 2726 /* misc IRQ */ 2727 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); 2728 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */ 2729 if (r_irq_misc & V_STA_IRQ) { 2730 if (hc->ctype == HFC_TYPE_E1) { 2731 /* state machine */ 2732 dch = hc->chan[hc->dnum[0]].dch; 2733 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); 2734 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 2735 && hc->e1_getclock) { 2736 if (e1_syncsta & V_FR_SYNC_E1) 2737 hc->syncronized = 1; 2738 else 2739 hc->syncronized = 0; 2740 } 2741 /* undocumented: status changes during read */ 2742 temp = HFC_inb_nodebug(hc, R_E1_RD_STA); 2743 while (temp != (temp2 = 2744 HFC_inb_nodebug(hc, R_E1_RD_STA))) { 2745 if (debug & DEBUG_HFCMULTI_STATE) 2746 printk(KERN_DEBUG "%s: reread " 2747 "STATE because %d!=%d\n", 2748 __func__, temp, temp2); 2749 temp = temp2; /* repeat */ 2750 } 2751 /* broadcast state change to all fragments */ 2752 if (debug & DEBUG_HFCMULTI_STATE) 2753 printk(KERN_DEBUG 2754 "%s: E1 (id=%d) newstate %x\n", 2755 __func__, hc->id, temp & 0x7); 2756 for (i = 0; i < hc->ports; i++) { 2757 dch = hc->chan[hc->dnum[i]].dch; 2758 dch->state = temp & 0x7; 2759 schedule_event(dch, FLG_PHCHANGE); 2760 } 2761 2762 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2763 plxsd_checksync(hc, 0); 2764 } 2765 } 2766 if (r_irq_misc & V_TI_IRQ) { 2767 if (hc->iclock_on) 2768 mISDN_clock_update(hc->iclock, poll, NULL); 2769 handle_timer_irq(hc); 2770 } 2771 2772 if (r_irq_misc & V_DTMF_IRQ) 2773 hfcmulti_dtmf(hc); 2774 2775 if (r_irq_misc & V_IRQ_PROC) { 2776 static int irq_proc_cnt; 2777 if (!irq_proc_cnt++) 2778 printk(KERN_DEBUG "%s: got V_IRQ_PROC -" 2779 " this should not happen\n", __func__); 2780 } 2781 2782 } 2783 if (status & V_FR_IRQSTA) { 2784 /* FIFO IRQ */ 2785 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); 2786 for (i = 0; i < 8; i++) { 2787 if (r_irq_oview & (1 << i)) 2788 fifo_irq(hc, i); 2789 } 2790 } 2791 2792 #ifdef IRQ_DEBUG 2793 irqsem = 0; 2794 #endif 2795 spin_unlock(&hc->lock); 2796 return IRQ_HANDLED; 2797 2798 irq_notforus: 2799 #ifdef IRQ_DEBUG 2800 irqsem = 0; 2801 #endif 2802 spin_unlock(&hc->lock); 2803 return IRQ_NONE; 2804 } 2805 2806 2807 /* 2808 * timer callback for D-chan busy resolution. Currently no function 2809 */ 2810 2811 static void hfcmulti_dbusy_timer(struct timer_list * t)2812 hfcmulti_dbusy_timer(struct timer_list *t) 2813 { 2814 } 2815 2816 2817 /* 2818 * activate/deactivate hardware for selected channels and mode 2819 * 2820 * configure B-channel with the given protocol 2821 * ch eqals to the HFC-channel (0-31) 2822 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 2823 * for S/T, 1-31 for E1) 2824 * the hdlc interrupts will be set/unset 2825 */ 2826 static int mode_hfcmulti(struct hfc_multi * hc,int ch,int protocol,int slot_tx,int bank_tx,int slot_rx,int bank_rx)2827 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, 2828 int bank_tx, int slot_rx, int bank_rx) 2829 { 2830 int flow_tx = 0, flow_rx = 0, routing = 0; 2831 int oslot_tx, oslot_rx; 2832 int conf; 2833 2834 if (ch < 0 || ch > 31) 2835 return -EINVAL; 2836 oslot_tx = hc->chan[ch].slot_tx; 2837 oslot_rx = hc->chan[ch].slot_rx; 2838 conf = hc->chan[ch].conf; 2839 2840 if (debug & DEBUG_HFCMULTI_MODE) 2841 printk(KERN_DEBUG 2842 "%s: card %d channel %d protocol %x slot old=%d new=%d " 2843 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", 2844 __func__, hc->id, ch, protocol, oslot_tx, slot_tx, 2845 bank_tx, oslot_rx, slot_rx, bank_rx); 2846 2847 if (oslot_tx >= 0 && slot_tx != oslot_tx) { 2848 /* remove from slot */ 2849 if (debug & DEBUG_HFCMULTI_MODE) 2850 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", 2851 __func__, oslot_tx); 2852 if (hc->slot_owner[oslot_tx << 1] == ch) { 2853 HFC_outb(hc, R_SLOT, oslot_tx << 1); 2854 HFC_outb(hc, A_SL_CFG, 0); 2855 if (hc->ctype != HFC_TYPE_XHFC) 2856 HFC_outb(hc, A_CONF, 0); 2857 hc->slot_owner[oslot_tx << 1] = -1; 2858 } else { 2859 if (debug & DEBUG_HFCMULTI_MODE) 2860 printk(KERN_DEBUG 2861 "%s: we are not owner of this tx slot " 2862 "anymore, channel %d is.\n", 2863 __func__, hc->slot_owner[oslot_tx << 1]); 2864 } 2865 } 2866 2867 if (oslot_rx >= 0 && slot_rx != oslot_rx) { 2868 /* remove from slot */ 2869 if (debug & DEBUG_HFCMULTI_MODE) 2870 printk(KERN_DEBUG 2871 "%s: remove from slot %d (RX)\n", 2872 __func__, oslot_rx); 2873 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { 2874 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); 2875 HFC_outb(hc, A_SL_CFG, 0); 2876 hc->slot_owner[(oslot_rx << 1) | 1] = -1; 2877 } else { 2878 if (debug & DEBUG_HFCMULTI_MODE) 2879 printk(KERN_DEBUG 2880 "%s: we are not owner of this rx slot " 2881 "anymore, channel %d is.\n", 2882 __func__, 2883 hc->slot_owner[(oslot_rx << 1) | 1]); 2884 } 2885 } 2886 2887 if (slot_tx < 0) { 2888 flow_tx = 0x80; /* FIFO->ST */ 2889 /* disable pcm slot */ 2890 hc->chan[ch].slot_tx = -1; 2891 hc->chan[ch].bank_tx = 0; 2892 } else { 2893 /* set pcm slot */ 2894 if (hc->chan[ch].txpending) 2895 flow_tx = 0x80; /* FIFO->ST */ 2896 else 2897 flow_tx = 0xc0; /* PCM->ST */ 2898 /* put on slot */ 2899 routing = bank_tx ? 0xc0 : 0x80; 2900 if (conf >= 0 || bank_tx > 1) 2901 routing = 0x40; /* loop */ 2902 if (debug & DEBUG_HFCMULTI_MODE) 2903 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2904 " %d flow %02x routing %02x conf %d (TX)\n", 2905 __func__, ch, slot_tx, bank_tx, 2906 flow_tx, routing, conf); 2907 HFC_outb(hc, R_SLOT, slot_tx << 1); 2908 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing); 2909 if (hc->ctype != HFC_TYPE_XHFC) 2910 HFC_outb(hc, A_CONF, 2911 (conf < 0) ? 0 : (conf | V_CONF_SL)); 2912 hc->slot_owner[slot_tx << 1] = ch; 2913 hc->chan[ch].slot_tx = slot_tx; 2914 hc->chan[ch].bank_tx = bank_tx; 2915 } 2916 if (slot_rx < 0) { 2917 /* disable pcm slot */ 2918 flow_rx = 0x80; /* ST->FIFO */ 2919 hc->chan[ch].slot_rx = -1; 2920 hc->chan[ch].bank_rx = 0; 2921 } else { 2922 /* set pcm slot */ 2923 if (hc->chan[ch].txpending) 2924 flow_rx = 0x80; /* ST->FIFO */ 2925 else 2926 flow_rx = 0xc0; /* ST->(FIFO,PCM) */ 2927 /* put on slot */ 2928 routing = bank_rx ? 0x80 : 0xc0; /* reversed */ 2929 if (conf >= 0 || bank_rx > 1) 2930 routing = 0x40; /* loop */ 2931 if (debug & DEBUG_HFCMULTI_MODE) 2932 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2933 " %d flow %02x routing %02x conf %d (RX)\n", 2934 __func__, ch, slot_rx, bank_rx, 2935 flow_rx, routing, conf); 2936 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR); 2937 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing); 2938 hc->slot_owner[(slot_rx << 1) | 1] = ch; 2939 hc->chan[ch].slot_rx = slot_rx; 2940 hc->chan[ch].bank_rx = bank_rx; 2941 } 2942 2943 switch (protocol) { 2944 case (ISDN_P_NONE): 2945 /* disable TX fifo */ 2946 HFC_outb(hc, R_FIFO, ch << 1); 2947 HFC_wait(hc); 2948 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); 2949 HFC_outb(hc, A_SUBCH_CFG, 0); 2950 HFC_outb(hc, A_IRQ_MSK, 0); 2951 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2952 HFC_wait(hc); 2953 /* disable RX fifo */ 2954 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 2955 HFC_wait(hc); 2956 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); 2957 HFC_outb(hc, A_SUBCH_CFG, 0); 2958 HFC_outb(hc, A_IRQ_MSK, 0); 2959 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2960 HFC_wait(hc); 2961 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) { 2962 hc->hw.a_st_ctrl0[hc->chan[ch].port] &= 2963 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN; 2964 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 2965 /* undocumented: delay after R_ST_SEL */ 2966 udelay(1); 2967 HFC_outb(hc, A_ST_CTRL0, 2968 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 2969 } 2970 if (hc->chan[ch].bch) { 2971 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 2972 test_and_clear_bit(FLG_TRANSPARENT, 2973 &hc->chan[ch].bch->Flags); 2974 } 2975 break; 2976 case (ISDN_P_B_RAW): /* B-channel */ 2977 2978 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2979 (hc->chan[ch].slot_rx < 0) && 2980 (hc->chan[ch].slot_tx < 0)) { 2981 2982 printk(KERN_DEBUG 2983 "Setting B-channel %d to echo cancelable " 2984 "state on PCM slot %d\n", ch, 2985 ((ch / 4) * 8) + ((ch % 4) * 4) + 1); 2986 printk(KERN_DEBUG 2987 "Enabling pass through for channel\n"); 2988 vpm_out(hc, ch, ((ch / 4) * 8) + 2989 ((ch % 4) * 4) + 1, 0x01); 2990 /* rx path */ 2991 /* S/T -> PCM */ 2992 HFC_outb(hc, R_FIFO, (ch << 1)); 2993 HFC_wait(hc); 2994 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 2995 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 2996 ((ch % 4) * 4) + 1) << 1); 2997 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); 2998 2999 /* PCM -> FIFO */ 3000 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); 3001 HFC_wait(hc); 3002 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3003 HFC_outb(hc, A_SUBCH_CFG, 0); 3004 HFC_outb(hc, A_IRQ_MSK, 0); 3005 if (hc->chan[ch].protocol != protocol) { 3006 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3007 HFC_wait(hc); 3008 } 3009 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3010 ((ch % 4) * 4) + 1) << 1) | 1); 3011 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); 3012 3013 /* tx path */ 3014 /* PCM -> S/T */ 3015 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3016 HFC_wait(hc); 3017 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3018 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3019 ((ch % 4) * 4)) << 1) | 1); 3020 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); 3021 3022 /* FIFO -> PCM */ 3023 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); 3024 HFC_wait(hc); 3025 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3026 HFC_outb(hc, A_SUBCH_CFG, 0); 3027 HFC_outb(hc, A_IRQ_MSK, 0); 3028 if (hc->chan[ch].protocol != protocol) { 3029 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3030 HFC_wait(hc); 3031 } 3032 /* tx silence */ 3033 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3034 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3035 ((ch % 4) * 4)) << 1); 3036 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); 3037 } else { 3038 /* enable TX fifo */ 3039 HFC_outb(hc, R_FIFO, ch << 1); 3040 HFC_wait(hc); 3041 if (hc->ctype == HFC_TYPE_XHFC) 3042 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 | 3043 V_HDLC_TRP | V_IFF); 3044 /* Enable FIFO, no interrupt */ 3045 else 3046 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | 3047 V_HDLC_TRP | V_IFF); 3048 HFC_outb(hc, A_SUBCH_CFG, 0); 3049 HFC_outb(hc, A_IRQ_MSK, 0); 3050 if (hc->chan[ch].protocol != protocol) { 3051 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3052 HFC_wait(hc); 3053 } 3054 /* tx silence */ 3055 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3056 /* enable RX fifo */ 3057 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3058 HFC_wait(hc); 3059 if (hc->ctype == HFC_TYPE_XHFC) 3060 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 | 3061 V_HDLC_TRP); 3062 /* Enable FIFO, no interrupt*/ 3063 else 3064 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | 3065 V_HDLC_TRP); 3066 HFC_outb(hc, A_SUBCH_CFG, 0); 3067 HFC_outb(hc, A_IRQ_MSK, 0); 3068 if (hc->chan[ch].protocol != protocol) { 3069 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3070 HFC_wait(hc); 3071 } 3072 } 3073 if (hc->ctype != HFC_TYPE_E1) { 3074 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3075 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3076 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3077 /* undocumented: delay after R_ST_SEL */ 3078 udelay(1); 3079 HFC_outb(hc, A_ST_CTRL0, 3080 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3081 } 3082 if (hc->chan[ch].bch) 3083 test_and_set_bit(FLG_TRANSPARENT, 3084 &hc->chan[ch].bch->Flags); 3085 break; 3086 case (ISDN_P_B_HDLC): /* B-channel */ 3087 case (ISDN_P_TE_S0): /* D-channel */ 3088 case (ISDN_P_NT_S0): 3089 case (ISDN_P_TE_E1): 3090 case (ISDN_P_NT_E1): 3091 /* enable TX fifo */ 3092 HFC_outb(hc, R_FIFO, ch << 1); 3093 HFC_wait(hc); 3094 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) { 3095 /* E1 or B-channel */ 3096 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); 3097 HFC_outb(hc, A_SUBCH_CFG, 0); 3098 } else { 3099 /* D-Channel without HDLC fill flags */ 3100 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); 3101 HFC_outb(hc, A_SUBCH_CFG, 2); 3102 } 3103 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3104 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3105 HFC_wait(hc); 3106 /* enable RX fifo */ 3107 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3108 HFC_wait(hc); 3109 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); 3110 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) 3111 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ 3112 else 3113 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ 3114 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3115 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3116 HFC_wait(hc); 3117 if (hc->chan[ch].bch) { 3118 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 3119 if (hc->ctype != HFC_TYPE_E1) { 3120 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3121 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3122 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3123 /* undocumented: delay after R_ST_SEL */ 3124 udelay(1); 3125 HFC_outb(hc, A_ST_CTRL0, 3126 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3127 } 3128 } 3129 break; 3130 default: 3131 printk(KERN_DEBUG "%s: protocol not known %x\n", 3132 __func__, protocol); 3133 hc->chan[ch].protocol = ISDN_P_NONE; 3134 return -ENOPROTOOPT; 3135 } 3136 hc->chan[ch].protocol = protocol; 3137 return 0; 3138 } 3139 3140 3141 /* 3142 * connect/disconnect PCM 3143 */ 3144 3145 static void hfcmulti_pcm(struct hfc_multi * hc,int ch,int slot_tx,int bank_tx,int slot_rx,int bank_rx)3146 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, 3147 int slot_rx, int bank_rx) 3148 { 3149 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { 3150 /* disable PCM */ 3151 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); 3152 return; 3153 } 3154 3155 /* enable pcm */ 3156 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, 3157 slot_rx, bank_rx); 3158 } 3159 3160 /* 3161 * set/disable conference 3162 */ 3163 3164 static void hfcmulti_conf(struct hfc_multi * hc,int ch,int num)3165 hfcmulti_conf(struct hfc_multi *hc, int ch, int num) 3166 { 3167 if (num >= 0 && num <= 7) 3168 hc->chan[ch].conf = num; 3169 else 3170 hc->chan[ch].conf = -1; 3171 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, 3172 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, 3173 hc->chan[ch].bank_rx); 3174 } 3175 3176 3177 /* 3178 * set/disable sample loop 3179 */ 3180 3181 /* NOTE: this function is experimental and therefore disabled */ 3182 3183 /* 3184 * Layer 1 callback function 3185 */ 3186 static int hfcm_l1callback(struct dchannel * dch,u_int cmd)3187 hfcm_l1callback(struct dchannel *dch, u_int cmd) 3188 { 3189 struct hfc_multi *hc = dch->hw; 3190 struct sk_buff_head free_queue; 3191 u_long flags; 3192 3193 switch (cmd) { 3194 case INFO3_P8: 3195 case INFO3_P10: 3196 break; 3197 case HW_RESET_REQ: 3198 /* start activation */ 3199 spin_lock_irqsave(&hc->lock, flags); 3200 if (hc->ctype == HFC_TYPE_E1) { 3201 if (debug & DEBUG_HFCMULTI_MSG) 3202 printk(KERN_DEBUG 3203 "%s: HW_RESET_REQ no BRI\n", 3204 __func__); 3205 } else { 3206 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3207 /* undocumented: delay after R_ST_SEL */ 3208 udelay(1); 3209 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ 3210 udelay(6); /* wait at least 5,21us */ 3211 HFC_outb(hc, A_ST_WR_STATE, 3); 3212 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3)); 3213 /* activate */ 3214 } 3215 spin_unlock_irqrestore(&hc->lock, flags); 3216 l1_event(dch->l1, HW_POWERUP_IND); 3217 break; 3218 case HW_DEACT_REQ: 3219 __skb_queue_head_init(&free_queue); 3220 /* start deactivation */ 3221 spin_lock_irqsave(&hc->lock, flags); 3222 if (hc->ctype == HFC_TYPE_E1) { 3223 if (debug & DEBUG_HFCMULTI_MSG) 3224 printk(KERN_DEBUG 3225 "%s: HW_DEACT_REQ no BRI\n", 3226 __func__); 3227 } else { 3228 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3229 /* undocumented: delay after R_ST_SEL */ 3230 udelay(1); 3231 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3232 /* deactivate */ 3233 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3234 hc->syncronized &= 3235 ~(1 << hc->chan[dch->slot].port); 3236 plxsd_checksync(hc, 0); 3237 } 3238 } 3239 skb_queue_splice_init(&dch->squeue, &free_queue); 3240 if (dch->tx_skb) { 3241 __skb_queue_tail(&free_queue, dch->tx_skb); 3242 dch->tx_skb = NULL; 3243 } 3244 dch->tx_idx = 0; 3245 if (dch->rx_skb) { 3246 __skb_queue_tail(&free_queue, dch->rx_skb); 3247 dch->rx_skb = NULL; 3248 } 3249 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3250 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3251 del_timer(&dch->timer); 3252 spin_unlock_irqrestore(&hc->lock, flags); 3253 __skb_queue_purge(&free_queue); 3254 break; 3255 case HW_POWERUP_REQ: 3256 spin_lock_irqsave(&hc->lock, flags); 3257 if (hc->ctype == HFC_TYPE_E1) { 3258 if (debug & DEBUG_HFCMULTI_MSG) 3259 printk(KERN_DEBUG 3260 "%s: HW_POWERUP_REQ no BRI\n", 3261 __func__); 3262 } else { 3263 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3264 /* undocumented: delay after R_ST_SEL */ 3265 udelay(1); 3266 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ 3267 udelay(6); /* wait at least 5,21us */ 3268 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ 3269 } 3270 spin_unlock_irqrestore(&hc->lock, flags); 3271 break; 3272 case PH_ACTIVATE_IND: 3273 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3274 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3275 GFP_ATOMIC); 3276 break; 3277 case PH_DEACTIVATE_IND: 3278 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3279 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3280 GFP_ATOMIC); 3281 break; 3282 default: 3283 if (dch->debug & DEBUG_HW) 3284 printk(KERN_DEBUG "%s: unknown command %x\n", 3285 __func__, cmd); 3286 return -1; 3287 } 3288 return 0; 3289 } 3290 3291 /* 3292 * Layer2 -> Layer 1 Transfer 3293 */ 3294 3295 static int handle_dmsg(struct mISDNchannel * ch,struct sk_buff * skb)3296 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3297 { 3298 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 3299 struct dchannel *dch = container_of(dev, struct dchannel, dev); 3300 struct hfc_multi *hc = dch->hw; 3301 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3302 int ret = -EINVAL; 3303 unsigned int id; 3304 u_long flags; 3305 3306 switch (hh->prim) { 3307 case PH_DATA_REQ: 3308 if (skb->len < 1) 3309 break; 3310 spin_lock_irqsave(&hc->lock, flags); 3311 ret = dchannel_senddata(dch, skb); 3312 if (ret > 0) { /* direct TX */ 3313 id = hh->id; /* skb can be freed */ 3314 hfcmulti_tx(hc, dch->slot); 3315 ret = 0; 3316 /* start fifo */ 3317 HFC_outb(hc, R_FIFO, 0); 3318 HFC_wait(hc); 3319 spin_unlock_irqrestore(&hc->lock, flags); 3320 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3321 } else 3322 spin_unlock_irqrestore(&hc->lock, flags); 3323 return ret; 3324 case PH_ACTIVATE_REQ: 3325 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3326 spin_lock_irqsave(&hc->lock, flags); 3327 ret = 0; 3328 if (debug & DEBUG_HFCMULTI_MSG) 3329 printk(KERN_DEBUG 3330 "%s: PH_ACTIVATE port %d (0..%d)\n", 3331 __func__, hc->chan[dch->slot].port, 3332 hc->ports - 1); 3333 /* start activation */ 3334 if (hc->ctype == HFC_TYPE_E1) { 3335 ph_state_change(dch); 3336 if (debug & DEBUG_HFCMULTI_STATE) 3337 printk(KERN_DEBUG 3338 "%s: E1 report state %x \n", 3339 __func__, dch->state); 3340 } else { 3341 HFC_outb(hc, R_ST_SEL, 3342 hc->chan[dch->slot].port); 3343 /* undocumented: delay after R_ST_SEL */ 3344 udelay(1); 3345 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); 3346 /* G1 */ 3347 udelay(6); /* wait at least 5,21us */ 3348 HFC_outb(hc, A_ST_WR_STATE, 1); 3349 HFC_outb(hc, A_ST_WR_STATE, 1 | 3350 (V_ST_ACT * 3)); /* activate */ 3351 dch->state = 1; 3352 } 3353 spin_unlock_irqrestore(&hc->lock, flags); 3354 } else 3355 ret = l1_event(dch->l1, hh->prim); 3356 break; 3357 case PH_DEACTIVATE_REQ: 3358 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 3359 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3360 struct sk_buff_head free_queue; 3361 3362 __skb_queue_head_init(&free_queue); 3363 spin_lock_irqsave(&hc->lock, flags); 3364 if (debug & DEBUG_HFCMULTI_MSG) 3365 printk(KERN_DEBUG 3366 "%s: PH_DEACTIVATE port %d (0..%d)\n", 3367 __func__, hc->chan[dch->slot].port, 3368 hc->ports - 1); 3369 /* start deactivation */ 3370 if (hc->ctype == HFC_TYPE_E1) { 3371 if (debug & DEBUG_HFCMULTI_MSG) 3372 printk(KERN_DEBUG 3373 "%s: PH_DEACTIVATE no BRI\n", 3374 __func__); 3375 } else { 3376 HFC_outb(hc, R_ST_SEL, 3377 hc->chan[dch->slot].port); 3378 /* undocumented: delay after R_ST_SEL */ 3379 udelay(1); 3380 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3381 /* deactivate */ 3382 dch->state = 1; 3383 } 3384 skb_queue_splice_init(&dch->squeue, &free_queue); 3385 if (dch->tx_skb) { 3386 __skb_queue_tail(&free_queue, dch->tx_skb); 3387 dch->tx_skb = NULL; 3388 } 3389 dch->tx_idx = 0; 3390 if (dch->rx_skb) { 3391 __skb_queue_tail(&free_queue, dch->rx_skb); 3392 dch->rx_skb = NULL; 3393 } 3394 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3395 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3396 del_timer(&dch->timer); 3397 #ifdef FIXME 3398 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) 3399 dchannel_sched_event(&hc->dch, D_CLEARBUSY); 3400 #endif 3401 ret = 0; 3402 spin_unlock_irqrestore(&hc->lock, flags); 3403 __skb_queue_purge(&free_queue); 3404 } else 3405 ret = l1_event(dch->l1, hh->prim); 3406 break; 3407 } 3408 if (!ret) 3409 dev_kfree_skb(skb); 3410 return ret; 3411 } 3412 3413 static void deactivate_bchannel(struct bchannel * bch)3414 deactivate_bchannel(struct bchannel *bch) 3415 { 3416 struct hfc_multi *hc = bch->hw; 3417 u_long flags; 3418 3419 spin_lock_irqsave(&hc->lock, flags); 3420 mISDN_clear_bchannel(bch); 3421 hc->chan[bch->slot].coeff_count = 0; 3422 hc->chan[bch->slot].rx_off = 0; 3423 hc->chan[bch->slot].conf = -1; 3424 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); 3425 spin_unlock_irqrestore(&hc->lock, flags); 3426 } 3427 3428 static int handle_bmsg(struct mISDNchannel * ch,struct sk_buff * skb)3429 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3430 { 3431 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3432 struct hfc_multi *hc = bch->hw; 3433 int ret = -EINVAL; 3434 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3435 unsigned long flags; 3436 3437 switch (hh->prim) { 3438 case PH_DATA_REQ: 3439 if (!skb->len) 3440 break; 3441 spin_lock_irqsave(&hc->lock, flags); 3442 ret = bchannel_senddata(bch, skb); 3443 if (ret > 0) { /* direct TX */ 3444 hfcmulti_tx(hc, bch->slot); 3445 ret = 0; 3446 /* start fifo */ 3447 HFC_outb_nodebug(hc, R_FIFO, 0); 3448 HFC_wait_nodebug(hc); 3449 } 3450 spin_unlock_irqrestore(&hc->lock, flags); 3451 return ret; 3452 case PH_ACTIVATE_REQ: 3453 if (debug & DEBUG_HFCMULTI_MSG) 3454 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", 3455 __func__, bch->slot); 3456 spin_lock_irqsave(&hc->lock, flags); 3457 /* activate B-channel if not already activated */ 3458 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { 3459 hc->chan[bch->slot].txpending = 0; 3460 ret = mode_hfcmulti(hc, bch->slot, 3461 ch->protocol, 3462 hc->chan[bch->slot].slot_tx, 3463 hc->chan[bch->slot].bank_tx, 3464 hc->chan[bch->slot].slot_rx, 3465 hc->chan[bch->slot].bank_rx); 3466 if (!ret) { 3467 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf 3468 && test_bit(HFC_CHIP_DTMF, &hc->chip)) { 3469 /* start decoder */ 3470 hc->dtmf = 1; 3471 if (debug & DEBUG_HFCMULTI_DTMF) 3472 printk(KERN_DEBUG 3473 "%s: start dtmf decoder\n", 3474 __func__); 3475 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | 3476 V_RST_DTMF); 3477 } 3478 } 3479 } else 3480 ret = 0; 3481 spin_unlock_irqrestore(&hc->lock, flags); 3482 if (!ret) 3483 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3484 GFP_KERNEL); 3485 break; 3486 case PH_CONTROL_REQ: 3487 spin_lock_irqsave(&hc->lock, flags); 3488 switch (hh->id) { 3489 case HFC_SPL_LOOP_ON: /* set sample loop */ 3490 if (debug & DEBUG_HFCMULTI_MSG) 3491 printk(KERN_DEBUG 3492 "%s: HFC_SPL_LOOP_ON (len = %d)\n", 3493 __func__, skb->len); 3494 ret = 0; 3495 break; 3496 case HFC_SPL_LOOP_OFF: /* set silence */ 3497 if (debug & DEBUG_HFCMULTI_MSG) 3498 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", 3499 __func__); 3500 ret = 0; 3501 break; 3502 default: 3503 printk(KERN_ERR 3504 "%s: unknown PH_CONTROL_REQ info %x\n", 3505 __func__, hh->id); 3506 ret = -EINVAL; 3507 } 3508 spin_unlock_irqrestore(&hc->lock, flags); 3509 break; 3510 case PH_DEACTIVATE_REQ: 3511 deactivate_bchannel(bch); /* locked there */ 3512 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3513 GFP_KERNEL); 3514 ret = 0; 3515 break; 3516 } 3517 if (!ret) 3518 dev_kfree_skb(skb); 3519 return ret; 3520 } 3521 3522 /* 3523 * bchannel control function 3524 */ 3525 static int channel_bctrl(struct bchannel * bch,struct mISDN_ctrl_req * cq)3526 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 3527 { 3528 int ret = 0; 3529 struct dsp_features *features = 3530 (struct dsp_features *)(*((u_long *)&cq->p1)); 3531 struct hfc_multi *hc = bch->hw; 3532 int slot_tx; 3533 int bank_tx; 3534 int slot_rx; 3535 int bank_rx; 3536 int num; 3537 3538 switch (cq->op) { 3539 case MISDN_CTRL_GETOP: 3540 ret = mISDN_ctrl_bchannel(bch, cq); 3541 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP; 3542 break; 3543 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ 3544 ret = mISDN_ctrl_bchannel(bch, cq); 3545 hc->chan[bch->slot].rx_off = !!cq->p1; 3546 if (!hc->chan[bch->slot].rx_off) { 3547 /* reset fifo on rx on */ 3548 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); 3549 HFC_wait_nodebug(hc); 3550 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 3551 HFC_wait_nodebug(hc); 3552 } 3553 if (debug & DEBUG_HFCMULTI_MSG) 3554 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", 3555 __func__, bch->nr, hc->chan[bch->slot].rx_off); 3556 break; 3557 case MISDN_CTRL_FILL_EMPTY: 3558 ret = mISDN_ctrl_bchannel(bch, cq); 3559 hc->silence = bch->fill[0]; 3560 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data)); 3561 break; 3562 case MISDN_CTRL_HW_FEATURES: /* fill features structure */ 3563 if (debug & DEBUG_HFCMULTI_MSG) 3564 printk(KERN_DEBUG "%s: HW_FEATURE request\n", 3565 __func__); 3566 /* create confirm */ 3567 features->hfc_id = hc->id; 3568 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) 3569 features->hfc_dtmf = 1; 3570 if (test_bit(HFC_CHIP_CONF, &hc->chip)) 3571 features->hfc_conf = 1; 3572 features->hfc_loops = 0; 3573 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 3574 features->hfc_echocanhw = 1; 3575 } else { 3576 features->pcm_id = hc->pcm; 3577 features->pcm_slots = hc->slots; 3578 features->pcm_banks = 2; 3579 } 3580 break; 3581 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ 3582 slot_tx = cq->p1 & 0xff; 3583 bank_tx = cq->p1 >> 8; 3584 slot_rx = cq->p2 & 0xff; 3585 bank_rx = cq->p2 >> 8; 3586 if (debug & DEBUG_HFCMULTI_MSG) 3587 printk(KERN_DEBUG 3588 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3589 "slot %d bank %d (RX)\n", 3590 __func__, slot_tx, bank_tx, 3591 slot_rx, bank_rx); 3592 if (slot_tx < hc->slots && bank_tx <= 2 && 3593 slot_rx < hc->slots && bank_rx <= 2) 3594 hfcmulti_pcm(hc, bch->slot, 3595 slot_tx, bank_tx, slot_rx, bank_rx); 3596 else { 3597 printk(KERN_WARNING 3598 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3599 "slot %d bank %d (RX) out of range\n", 3600 __func__, slot_tx, bank_tx, 3601 slot_rx, bank_rx); 3602 ret = -EINVAL; 3603 } 3604 break; 3605 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ 3606 if (debug & DEBUG_HFCMULTI_MSG) 3607 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", 3608 __func__); 3609 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); 3610 break; 3611 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ 3612 num = cq->p1 & 0xff; 3613 if (debug & DEBUG_HFCMULTI_MSG) 3614 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", 3615 __func__, num); 3616 if (num <= 7) 3617 hfcmulti_conf(hc, bch->slot, num); 3618 else { 3619 printk(KERN_WARNING 3620 "%s: HW_CONF_JOIN conf %d out of range\n", 3621 __func__, num); 3622 ret = -EINVAL; 3623 } 3624 break; 3625 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ 3626 if (debug & DEBUG_HFCMULTI_MSG) 3627 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); 3628 hfcmulti_conf(hc, bch->slot, -1); 3629 break; 3630 case MISDN_CTRL_HFC_ECHOCAN_ON: 3631 if (debug & DEBUG_HFCMULTI_MSG) 3632 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); 3633 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3634 vpm_echocan_on(hc, bch->slot, cq->p1); 3635 else 3636 ret = -EINVAL; 3637 break; 3638 3639 case MISDN_CTRL_HFC_ECHOCAN_OFF: 3640 if (debug & DEBUG_HFCMULTI_MSG) 3641 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", 3642 __func__); 3643 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3644 vpm_echocan_off(hc, bch->slot); 3645 else 3646 ret = -EINVAL; 3647 break; 3648 default: 3649 ret = mISDN_ctrl_bchannel(bch, cq); 3650 break; 3651 } 3652 return ret; 3653 } 3654 3655 static int hfcm_bctrl(struct mISDNchannel * ch,u_int cmd,void * arg)3656 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 3657 { 3658 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3659 struct hfc_multi *hc = bch->hw; 3660 int err = -EINVAL; 3661 u_long flags; 3662 3663 if (bch->debug & DEBUG_HW) 3664 printk(KERN_DEBUG "%s: cmd:%x %p\n", 3665 __func__, cmd, arg); 3666 switch (cmd) { 3667 case CLOSE_CHANNEL: 3668 test_and_clear_bit(FLG_OPEN, &bch->Flags); 3669 deactivate_bchannel(bch); /* locked there */ 3670 ch->protocol = ISDN_P_NONE; 3671 ch->peer = NULL; 3672 module_put(THIS_MODULE); 3673 err = 0; 3674 break; 3675 case CONTROL_CHANNEL: 3676 spin_lock_irqsave(&hc->lock, flags); 3677 err = channel_bctrl(bch, arg); 3678 spin_unlock_irqrestore(&hc->lock, flags); 3679 break; 3680 default: 3681 printk(KERN_WARNING "%s: unknown prim(%x)\n", 3682 __func__, cmd); 3683 } 3684 return err; 3685 } 3686 3687 /* 3688 * handle D-channel events 3689 * 3690 * handle state change event 3691 */ 3692 static void ph_state_change(struct dchannel * dch)3693 ph_state_change(struct dchannel *dch) 3694 { 3695 struct hfc_multi *hc; 3696 int ch, i; 3697 3698 if (!dch) { 3699 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__); 3700 return; 3701 } 3702 hc = dch->hw; 3703 ch = dch->slot; 3704 3705 if (hc->ctype == HFC_TYPE_E1) { 3706 if (dch->dev.D.protocol == ISDN_P_TE_E1) { 3707 if (debug & DEBUG_HFCMULTI_STATE) 3708 printk(KERN_DEBUG 3709 "%s: E1 TE (id=%d) newstate %x\n", 3710 __func__, hc->id, dch->state); 3711 } else { 3712 if (debug & DEBUG_HFCMULTI_STATE) 3713 printk(KERN_DEBUG 3714 "%s: E1 NT (id=%d) newstate %x\n", 3715 __func__, hc->id, dch->state); 3716 } 3717 switch (dch->state) { 3718 case (1): 3719 if (hc->e1_state != 1) { 3720 for (i = 1; i <= 31; i++) { 3721 /* reset fifos on e1 activation */ 3722 HFC_outb_nodebug(hc, R_FIFO, 3723 (i << 1) | 1); 3724 HFC_wait_nodebug(hc); 3725 HFC_outb_nodebug(hc, R_INC_RES_FIFO, 3726 V_RES_F); 3727 HFC_wait_nodebug(hc); 3728 } 3729 } 3730 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3731 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3732 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3733 break; 3734 3735 default: 3736 if (hc->e1_state != 1) 3737 return; 3738 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3739 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3740 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3741 } 3742 hc->e1_state = dch->state; 3743 } else { 3744 if (dch->dev.D.protocol == ISDN_P_TE_S0) { 3745 if (debug & DEBUG_HFCMULTI_STATE) 3746 printk(KERN_DEBUG 3747 "%s: S/T TE newstate %x\n", 3748 __func__, dch->state); 3749 switch (dch->state) { 3750 case (0): 3751 l1_event(dch->l1, HW_RESET_IND); 3752 break; 3753 case (3): 3754 l1_event(dch->l1, HW_DEACT_IND); 3755 break; 3756 case (5): 3757 case (8): 3758 l1_event(dch->l1, ANYSIGNAL); 3759 break; 3760 case (6): 3761 l1_event(dch->l1, INFO2); 3762 break; 3763 case (7): 3764 l1_event(dch->l1, INFO4_P8); 3765 break; 3766 } 3767 } else { 3768 if (debug & DEBUG_HFCMULTI_STATE) 3769 printk(KERN_DEBUG "%s: S/T NT newstate %x\n", 3770 __func__, dch->state); 3771 switch (dch->state) { 3772 case (2): 3773 if (hc->chan[ch].nt_timer == 0) { 3774 hc->chan[ch].nt_timer = -1; 3775 HFC_outb(hc, R_ST_SEL, 3776 hc->chan[ch].port); 3777 /* undocumented: delay after R_ST_SEL */ 3778 udelay(1); 3779 HFC_outb(hc, A_ST_WR_STATE, 4 | 3780 V_ST_LD_STA); /* G4 */ 3781 udelay(6); /* wait at least 5,21us */ 3782 HFC_outb(hc, A_ST_WR_STATE, 4); 3783 dch->state = 4; 3784 } else { 3785 /* one extra count for the next event */ 3786 hc->chan[ch].nt_timer = 3787 nt_t1_count[poll_timer] + 1; 3788 HFC_outb(hc, R_ST_SEL, 3789 hc->chan[ch].port); 3790 /* undocumented: delay after R_ST_SEL */ 3791 udelay(1); 3792 /* allow G2 -> G3 transition */ 3793 HFC_outb(hc, A_ST_WR_STATE, 2 | 3794 V_SET_G2_G3); 3795 } 3796 break; 3797 case (1): 3798 hc->chan[ch].nt_timer = -1; 3799 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3800 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3801 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3802 break; 3803 case (4): 3804 hc->chan[ch].nt_timer = -1; 3805 break; 3806 case (3): 3807 hc->chan[ch].nt_timer = -1; 3808 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3809 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3810 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3811 break; 3812 } 3813 } 3814 } 3815 } 3816 3817 /* 3818 * called for card mode init message 3819 */ 3820 3821 static void hfcmulti_initmode(struct dchannel * dch)3822 hfcmulti_initmode(struct dchannel *dch) 3823 { 3824 struct hfc_multi *hc = dch->hw; 3825 u_char a_st_wr_state, r_e1_wr_sta; 3826 int i, pt; 3827 3828 if (debug & DEBUG_HFCMULTI_INIT) 3829 printk(KERN_DEBUG "%s: entered\n", __func__); 3830 3831 i = dch->slot; 3832 pt = hc->chan[i].port; 3833 if (hc->ctype == HFC_TYPE_E1) { 3834 /* E1 */ 3835 hc->chan[hc->dnum[pt]].slot_tx = -1; 3836 hc->chan[hc->dnum[pt]].slot_rx = -1; 3837 hc->chan[hc->dnum[pt]].conf = -1; 3838 if (hc->dnum[pt]) { 3839 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol, 3840 -1, 0, -1, 0); 3841 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0); 3842 } 3843 for (i = 1; i <= 31; i++) { 3844 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */ 3845 continue; 3846 hc->chan[i].slot_tx = -1; 3847 hc->chan[i].slot_rx = -1; 3848 hc->chan[i].conf = -1; 3849 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); 3850 } 3851 } 3852 if (hc->ctype == HFC_TYPE_E1 && pt == 0) { 3853 /* E1, port 0 */ 3854 dch = hc->chan[hc->dnum[0]].dch; 3855 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) { 3856 HFC_outb(hc, R_LOS0, 255); /* 2 ms */ 3857 HFC_outb(hc, R_LOS1, 255); /* 512 ms */ 3858 } 3859 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) { 3860 HFC_outb(hc, R_RX0, 0); 3861 hc->hw.r_tx0 = 0 | V_OUT_EN; 3862 } else { 3863 HFC_outb(hc, R_RX0, 1); 3864 hc->hw.r_tx0 = 1 | V_OUT_EN; 3865 } 3866 hc->hw.r_tx1 = V_ATX | V_NTRI; 3867 HFC_outb(hc, R_TX0, hc->hw.r_tx0); 3868 HFC_outb(hc, R_TX1, hc->hw.r_tx1); 3869 HFC_outb(hc, R_TX_FR0, 0x00); 3870 HFC_outb(hc, R_TX_FR1, 0xf8); 3871 3872 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg)) 3873 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); 3874 3875 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); 3876 3877 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg)) 3878 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); 3879 3880 if (dch->dev.D.protocol == ISDN_P_NT_E1) { 3881 if (debug & DEBUG_HFCMULTI_INIT) 3882 printk(KERN_DEBUG "%s: E1 port is NT-mode\n", 3883 __func__); 3884 r_e1_wr_sta = 0; /* G0 */ 3885 hc->e1_getclock = 0; 3886 } else { 3887 if (debug & DEBUG_HFCMULTI_INIT) 3888 printk(KERN_DEBUG "%s: E1 port is TE-mode\n", 3889 __func__); 3890 r_e1_wr_sta = 0; /* F0 */ 3891 hc->e1_getclock = 1; 3892 } 3893 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 3894 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 3895 else 3896 HFC_outb(hc, R_SYNC_OUT, 0); 3897 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) 3898 hc->e1_getclock = 1; 3899 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) 3900 hc->e1_getclock = 0; 3901 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 3902 /* SLAVE (clock master) */ 3903 if (debug & DEBUG_HFCMULTI_INIT) 3904 printk(KERN_DEBUG 3905 "%s: E1 port is clock master " 3906 "(clock from PCM)\n", __func__); 3907 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); 3908 } else { 3909 if (hc->e1_getclock) { 3910 /* MASTER (clock slave) */ 3911 if (debug & DEBUG_HFCMULTI_INIT) 3912 printk(KERN_DEBUG 3913 "%s: E1 port is clock slave " 3914 "(clock to PCM)\n", __func__); 3915 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 3916 } else { 3917 /* MASTER (clock master) */ 3918 if (debug & DEBUG_HFCMULTI_INIT) 3919 printk(KERN_DEBUG "%s: E1 port is " 3920 "clock master " 3921 "(clock from QUARTZ)\n", 3922 __func__); 3923 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | 3924 V_PCM_SYNC | V_JATT_OFF); 3925 HFC_outb(hc, R_SYNC_OUT, 0); 3926 } 3927 } 3928 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ 3929 HFC_outb(hc, R_PWM_MD, V_PWM0_MD); 3930 HFC_outb(hc, R_PWM0, 0x50); 3931 HFC_outb(hc, R_PWM1, 0xff); 3932 /* state machine setup */ 3933 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); 3934 udelay(6); /* wait at least 5,21us */ 3935 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); 3936 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3937 hc->syncronized = 0; 3938 plxsd_checksync(hc, 0); 3939 } 3940 } 3941 if (hc->ctype != HFC_TYPE_E1) { 3942 /* ST */ 3943 hc->chan[i].slot_tx = -1; 3944 hc->chan[i].slot_rx = -1; 3945 hc->chan[i].conf = -1; 3946 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); 3947 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0); 3948 hc->chan[i - 2].slot_tx = -1; 3949 hc->chan[i - 2].slot_rx = -1; 3950 hc->chan[i - 2].conf = -1; 3951 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); 3952 hc->chan[i - 1].slot_tx = -1; 3953 hc->chan[i - 1].slot_rx = -1; 3954 hc->chan[i - 1].conf = -1; 3955 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); 3956 /* select interface */ 3957 HFC_outb(hc, R_ST_SEL, pt); 3958 /* undocumented: delay after R_ST_SEL */ 3959 udelay(1); 3960 if (dch->dev.D.protocol == ISDN_P_NT_S0) { 3961 if (debug & DEBUG_HFCMULTI_INIT) 3962 printk(KERN_DEBUG 3963 "%s: ST port %d is NT-mode\n", 3964 __func__, pt); 3965 /* clock delay */ 3966 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); 3967 a_st_wr_state = 1; /* G1 */ 3968 hc->hw.a_st_ctrl0[pt] = V_ST_MD; 3969 } else { 3970 if (debug & DEBUG_HFCMULTI_INIT) 3971 printk(KERN_DEBUG 3972 "%s: ST port %d is TE-mode\n", 3973 __func__, pt); 3974 /* clock delay */ 3975 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); 3976 a_st_wr_state = 2; /* F2 */ 3977 hc->hw.a_st_ctrl0[pt] = 0; 3978 } 3979 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) 3980 hc->hw.a_st_ctrl0[pt] |= V_TX_LI; 3981 if (hc->ctype == HFC_TYPE_XHFC) { 3982 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */; 3983 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */, 3984 0x7c << 1 /* V_ST_PULSE */); 3985 } 3986 /* line setup */ 3987 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); 3988 /* disable E-channel */ 3989 if ((dch->dev.D.protocol == ISDN_P_NT_S0) || 3990 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) 3991 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); 3992 else 3993 HFC_outb(hc, A_ST_CTRL1, 0); 3994 /* enable B-channel receive */ 3995 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); 3996 /* state machine setup */ 3997 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); 3998 udelay(6); /* wait at least 5,21us */ 3999 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); 4000 hc->hw.r_sci_msk |= 1 << pt; 4001 /* state machine interrupts */ 4002 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); 4003 /* unset sync on port */ 4004 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4005 hc->syncronized &= 4006 ~(1 << hc->chan[dch->slot].port); 4007 plxsd_checksync(hc, 0); 4008 } 4009 } 4010 if (debug & DEBUG_HFCMULTI_INIT) 4011 printk("%s: done\n", __func__); 4012 } 4013 4014 4015 static int open_dchannel(struct hfc_multi * hc,struct dchannel * dch,struct channel_req * rq)4016 open_dchannel(struct hfc_multi *hc, struct dchannel *dch, 4017 struct channel_req *rq) 4018 { 4019 int err = 0; 4020 u_long flags; 4021 4022 if (debug & DEBUG_HW_OPEN) 4023 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, 4024 dch->dev.id, __builtin_return_address(0)); 4025 if (rq->protocol == ISDN_P_NONE) 4026 return -EINVAL; 4027 if ((dch->dev.D.protocol != ISDN_P_NONE) && 4028 (dch->dev.D.protocol != rq->protocol)) { 4029 if (debug & DEBUG_HFCMULTI_MODE) 4030 printk(KERN_DEBUG "%s: change protocol %x to %x\n", 4031 __func__, dch->dev.D.protocol, rq->protocol); 4032 } 4033 if ((dch->dev.D.protocol == ISDN_P_TE_S0) && 4034 (rq->protocol != ISDN_P_TE_S0)) 4035 l1_event(dch->l1, CLOSE_CHANNEL); 4036 if (dch->dev.D.protocol != rq->protocol) { 4037 if (rq->protocol == ISDN_P_TE_S0) { 4038 err = create_l1(dch, hfcm_l1callback); 4039 if (err) 4040 return err; 4041 } 4042 dch->dev.D.protocol = rq->protocol; 4043 spin_lock_irqsave(&hc->lock, flags); 4044 hfcmulti_initmode(dch); 4045 spin_unlock_irqrestore(&hc->lock, flags); 4046 } 4047 if (test_bit(FLG_ACTIVE, &dch->Flags)) 4048 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, 4049 0, NULL, GFP_KERNEL); 4050 rq->ch = &dch->dev.D; 4051 if (!try_module_get(THIS_MODULE)) 4052 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4053 return 0; 4054 } 4055 4056 static int open_bchannel(struct hfc_multi * hc,struct dchannel * dch,struct channel_req * rq)4057 open_bchannel(struct hfc_multi *hc, struct dchannel *dch, 4058 struct channel_req *rq) 4059 { 4060 struct bchannel *bch; 4061 int ch; 4062 4063 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) 4064 return -EINVAL; 4065 if (rq->protocol == ISDN_P_NONE) 4066 return -EINVAL; 4067 if (hc->ctype == HFC_TYPE_E1) 4068 ch = rq->adr.channel; 4069 else 4070 ch = (rq->adr.channel - 1) + (dch->slot - 2); 4071 bch = hc->chan[ch].bch; 4072 if (!bch) { 4073 printk(KERN_ERR "%s:internal error ch %d has no bch\n", 4074 __func__, ch); 4075 return -EINVAL; 4076 } 4077 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 4078 return -EBUSY; /* b-channel can be only open once */ 4079 bch->ch.protocol = rq->protocol; 4080 hc->chan[ch].rx_off = 0; 4081 rq->ch = &bch->ch; 4082 if (!try_module_get(THIS_MODULE)) 4083 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4084 return 0; 4085 } 4086 4087 /* 4088 * device control function 4089 */ 4090 static int channel_dctrl(struct dchannel * dch,struct mISDN_ctrl_req * cq)4091 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) 4092 { 4093 struct hfc_multi *hc = dch->hw; 4094 int ret = 0; 4095 int wd_mode, wd_cnt; 4096 4097 switch (cq->op) { 4098 case MISDN_CTRL_GETOP: 4099 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3; 4100 break; 4101 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */ 4102 wd_cnt = cq->p1 & 0xf; 4103 wd_mode = !!(cq->p1 >> 4); 4104 if (debug & DEBUG_HFCMULTI_MSG) 4105 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s" 4106 ", counter 0x%x\n", __func__, 4107 wd_mode ? "AUTO" : "MANUAL", wd_cnt); 4108 /* set the watchdog timer */ 4109 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4)); 4110 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0); 4111 if (hc->ctype == HFC_TYPE_XHFC) 4112 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */; 4113 /* init the watchdog register and reset the counter */ 4114 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4115 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4116 /* enable the watchdog output for Speech-Design */ 4117 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7); 4118 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15); 4119 HFC_outb(hc, R_GPIO_OUT1, 0); 4120 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15); 4121 } 4122 break; 4123 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */ 4124 if (debug & DEBUG_HFCMULTI_MSG) 4125 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n", 4126 __func__); 4127 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4128 break; 4129 case MISDN_CTRL_L1_TIMER3: 4130 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff)); 4131 break; 4132 default: 4133 printk(KERN_WARNING "%s: unknown Op %x\n", 4134 __func__, cq->op); 4135 ret = -EINVAL; 4136 break; 4137 } 4138 return ret; 4139 } 4140 4141 static int hfcm_dctrl(struct mISDNchannel * ch,u_int cmd,void * arg)4142 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 4143 { 4144 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 4145 struct dchannel *dch = container_of(dev, struct dchannel, dev); 4146 struct hfc_multi *hc = dch->hw; 4147 struct channel_req *rq; 4148 int err = 0; 4149 u_long flags; 4150 4151 if (dch->debug & DEBUG_HW) 4152 printk(KERN_DEBUG "%s: cmd:%x %p\n", 4153 __func__, cmd, arg); 4154 switch (cmd) { 4155 case OPEN_CHANNEL: 4156 rq = arg; 4157 switch (rq->protocol) { 4158 case ISDN_P_TE_S0: 4159 case ISDN_P_NT_S0: 4160 if (hc->ctype == HFC_TYPE_E1) { 4161 err = -EINVAL; 4162 break; 4163 } 4164 err = open_dchannel(hc, dch, rq); /* locked there */ 4165 break; 4166 case ISDN_P_TE_E1: 4167 case ISDN_P_NT_E1: 4168 if (hc->ctype != HFC_TYPE_E1) { 4169 err = -EINVAL; 4170 break; 4171 } 4172 err = open_dchannel(hc, dch, rq); /* locked there */ 4173 break; 4174 default: 4175 spin_lock_irqsave(&hc->lock, flags); 4176 err = open_bchannel(hc, dch, rq); 4177 spin_unlock_irqrestore(&hc->lock, flags); 4178 } 4179 break; 4180 case CLOSE_CHANNEL: 4181 if (debug & DEBUG_HW_OPEN) 4182 printk(KERN_DEBUG "%s: dev(%d) close from %p\n", 4183 __func__, dch->dev.id, 4184 __builtin_return_address(0)); 4185 module_put(THIS_MODULE); 4186 break; 4187 case CONTROL_CHANNEL: 4188 spin_lock_irqsave(&hc->lock, flags); 4189 err = channel_dctrl(dch, arg); 4190 spin_unlock_irqrestore(&hc->lock, flags); 4191 break; 4192 default: 4193 if (dch->debug & DEBUG_HW) 4194 printk(KERN_DEBUG "%s: unknown command %x\n", 4195 __func__, cmd); 4196 err = -EINVAL; 4197 } 4198 return err; 4199 } 4200 4201 static int clockctl(void * priv,int enable)4202 clockctl(void *priv, int enable) 4203 { 4204 struct hfc_multi *hc = priv; 4205 4206 hc->iclock_on = enable; 4207 return 0; 4208 } 4209 4210 /* 4211 * initialize the card 4212 */ 4213 4214 /* 4215 * start timer irq, wait some time and check if we have interrupts. 4216 * if not, reset chip and try again. 4217 */ 4218 static int init_card(struct hfc_multi * hc)4219 init_card(struct hfc_multi *hc) 4220 { 4221 int err = -EIO; 4222 u_long flags; 4223 void __iomem *plx_acc; 4224 u_long plx_flags; 4225 4226 if (debug & DEBUG_HFCMULTI_INIT) 4227 printk(KERN_DEBUG "%s: entered\n", __func__); 4228 4229 spin_lock_irqsave(&hc->lock, flags); 4230 /* set interrupts but leave global interrupt disabled */ 4231 hc->hw.r_irq_ctrl = V_FIFO_IRQ; 4232 disable_hwirq(hc); 4233 spin_unlock_irqrestore(&hc->lock, flags); 4234 4235 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED, 4236 "HFC-multi", hc)) { 4237 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", 4238 hc->irq); 4239 hc->irq = 0; 4240 return -EIO; 4241 } 4242 4243 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4244 spin_lock_irqsave(&plx_lock, plx_flags); 4245 plx_acc = hc->plx_membase + PLX_INTCSR; 4246 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), 4247 plx_acc); /* enable PCI & LINT1 irq */ 4248 spin_unlock_irqrestore(&plx_lock, plx_flags); 4249 } 4250 4251 if (debug & DEBUG_HFCMULTI_INIT) 4252 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4253 __func__, hc->irq, hc->irqcnt); 4254 err = init_chip(hc); 4255 if (err) 4256 goto error; 4257 /* 4258 * Finally enable IRQ output 4259 * this is only allowed, if an IRQ routine is already 4260 * established for this HFC, so don't do that earlier 4261 */ 4262 spin_lock_irqsave(&hc->lock, flags); 4263 enable_hwirq(hc); 4264 spin_unlock_irqrestore(&hc->lock, flags); 4265 /* printk(KERN_DEBUG "no master irq set!!!\n"); */ 4266 set_current_state(TASK_UNINTERRUPTIBLE); 4267 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */ 4268 /* turn IRQ off until chip is completely initialized */ 4269 spin_lock_irqsave(&hc->lock, flags); 4270 disable_hwirq(hc); 4271 spin_unlock_irqrestore(&hc->lock, flags); 4272 if (debug & DEBUG_HFCMULTI_INIT) 4273 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4274 __func__, hc->irq, hc->irqcnt); 4275 if (hc->irqcnt) { 4276 if (debug & DEBUG_HFCMULTI_INIT) 4277 printk(KERN_DEBUG "%s: done\n", __func__); 4278 4279 return 0; 4280 } 4281 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 4282 printk(KERN_INFO "ignoring missing interrupts\n"); 4283 return 0; 4284 } 4285 4286 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", 4287 hc->irq); 4288 4289 err = -EIO; 4290 4291 error: 4292 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4293 spin_lock_irqsave(&plx_lock, plx_flags); 4294 plx_acc = hc->plx_membase + PLX_INTCSR; 4295 writew(0x00, plx_acc); /*disable IRQs*/ 4296 spin_unlock_irqrestore(&plx_lock, plx_flags); 4297 } 4298 4299 if (debug & DEBUG_HFCMULTI_INIT) 4300 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq); 4301 if (hc->irq) { 4302 free_irq(hc->irq, hc); 4303 hc->irq = 0; 4304 } 4305 4306 if (debug & DEBUG_HFCMULTI_INIT) 4307 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); 4308 return err; 4309 } 4310 4311 /* 4312 * find pci device and set it up 4313 */ 4314 4315 static int setup_pci(struct hfc_multi * hc,struct pci_dev * pdev,const struct pci_device_id * ent)4316 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, 4317 const struct pci_device_id *ent) 4318 { 4319 struct hm_map *m = (struct hm_map *)ent->driver_data; 4320 4321 printk(KERN_INFO 4322 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", 4323 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); 4324 4325 hc->pci_dev = pdev; 4326 if (m->clock2) 4327 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); 4328 4329 if (ent->vendor == PCI_VENDOR_ID_DIGIUM && 4330 ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) { 4331 test_and_set_bit(HFC_CHIP_B410P, &hc->chip); 4332 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 4333 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 4334 hc->slots = 32; 4335 } 4336 4337 if (hc->pci_dev->irq <= 0) { 4338 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); 4339 return -EIO; 4340 } 4341 if (pci_enable_device(hc->pci_dev)) { 4342 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); 4343 return -EIO; 4344 } 4345 hc->leds = m->leds; 4346 hc->ledstate = 0xAFFEAFFE; 4347 hc->opticalsupport = m->opticalsupport; 4348 4349 hc->pci_iobase = 0; 4350 hc->pci_membase = NULL; 4351 hc->plx_membase = NULL; 4352 4353 /* set memory access methods */ 4354 if (m->io_mode) /* use mode from card config */ 4355 hc->io_mode = m->io_mode; 4356 switch (hc->io_mode) { 4357 case HFC_IO_MODE_PLXSD: 4358 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); 4359 hc->slots = 128; /* required */ 4360 hc->HFC_outb = HFC_outb_pcimem; 4361 hc->HFC_inb = HFC_inb_pcimem; 4362 hc->HFC_inw = HFC_inw_pcimem; 4363 hc->HFC_wait = HFC_wait_pcimem; 4364 hc->read_fifo = read_fifo_pcimem; 4365 hc->write_fifo = write_fifo_pcimem; 4366 hc->plx_origmembase = hc->pci_dev->resource[0].start; 4367 /* MEMBASE 1 is PLX PCI Bridge */ 4368 4369 if (!hc->plx_origmembase) { 4370 printk(KERN_WARNING 4371 "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); 4372 pci_disable_device(hc->pci_dev); 4373 return -EIO; 4374 } 4375 4376 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); 4377 if (!hc->plx_membase) { 4378 printk(KERN_WARNING 4379 "HFC-multi: failed to remap plx address space. " 4380 "(internal error)\n"); 4381 pci_disable_device(hc->pci_dev); 4382 return -EIO; 4383 } 4384 printk(KERN_INFO 4385 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", 4386 (u_long)hc->plx_membase, hc->plx_origmembase); 4387 4388 hc->pci_origmembase = hc->pci_dev->resource[2].start; 4389 /* MEMBASE 1 is PLX PCI Bridge */ 4390 if (!hc->pci_origmembase) { 4391 printk(KERN_WARNING 4392 "HFC-multi: No IO-Memory for PCI card found\n"); 4393 pci_disable_device(hc->pci_dev); 4394 return -EIO; 4395 } 4396 4397 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); 4398 if (!hc->pci_membase) { 4399 printk(KERN_WARNING "HFC-multi: failed to remap io " 4400 "address space. (internal error)\n"); 4401 pci_disable_device(hc->pci_dev); 4402 return -EIO; 4403 } 4404 4405 printk(KERN_INFO 4406 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " 4407 "leds-type %d\n", 4408 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, 4409 hc->pci_dev->irq, HZ, hc->leds); 4410 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4411 break; 4412 case HFC_IO_MODE_PCIMEM: 4413 hc->HFC_outb = HFC_outb_pcimem; 4414 hc->HFC_inb = HFC_inb_pcimem; 4415 hc->HFC_inw = HFC_inw_pcimem; 4416 hc->HFC_wait = HFC_wait_pcimem; 4417 hc->read_fifo = read_fifo_pcimem; 4418 hc->write_fifo = write_fifo_pcimem; 4419 hc->pci_origmembase = hc->pci_dev->resource[1].start; 4420 if (!hc->pci_origmembase) { 4421 printk(KERN_WARNING 4422 "HFC-multi: No IO-Memory for PCI card found\n"); 4423 pci_disable_device(hc->pci_dev); 4424 return -EIO; 4425 } 4426 4427 hc->pci_membase = ioremap(hc->pci_origmembase, 256); 4428 if (!hc->pci_membase) { 4429 printk(KERN_WARNING 4430 "HFC-multi: failed to remap io address space. " 4431 "(internal error)\n"); 4432 pci_disable_device(hc->pci_dev); 4433 return -EIO; 4434 } 4435 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ " 4436 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, 4437 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); 4438 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4439 break; 4440 case HFC_IO_MODE_REGIO: 4441 hc->HFC_outb = HFC_outb_regio; 4442 hc->HFC_inb = HFC_inb_regio; 4443 hc->HFC_inw = HFC_inw_regio; 4444 hc->HFC_wait = HFC_wait_regio; 4445 hc->read_fifo = read_fifo_regio; 4446 hc->write_fifo = write_fifo_regio; 4447 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; 4448 if (!hc->pci_iobase) { 4449 printk(KERN_WARNING 4450 "HFC-multi: No IO for PCI card found\n"); 4451 pci_disable_device(hc->pci_dev); 4452 return -EIO; 4453 } 4454 4455 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { 4456 printk(KERN_WARNING "HFC-multi: failed to request " 4457 "address space at 0x%08lx (internal error)\n", 4458 hc->pci_iobase); 4459 pci_disable_device(hc->pci_dev); 4460 return -EIO; 4461 } 4462 4463 printk(KERN_INFO 4464 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", 4465 m->vendor_name, m->card_name, (u_int) hc->pci_iobase, 4466 hc->pci_dev->irq, HZ, hc->leds); 4467 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); 4468 break; 4469 default: 4470 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); 4471 pci_disable_device(hc->pci_dev); 4472 return -EIO; 4473 } 4474 4475 pci_set_drvdata(hc->pci_dev, hc); 4476 4477 /* At this point the needed PCI config is done */ 4478 /* fifos are still not enabled */ 4479 return 0; 4480 } 4481 4482 4483 /* 4484 * remove port 4485 */ 4486 4487 static void release_port(struct hfc_multi * hc,struct dchannel * dch)4488 release_port(struct hfc_multi *hc, struct dchannel *dch) 4489 { 4490 int pt, ci, i = 0; 4491 u_long flags; 4492 struct bchannel *pb; 4493 4494 ci = dch->slot; 4495 pt = hc->chan[ci].port; 4496 4497 if (debug & DEBUG_HFCMULTI_INIT) 4498 printk(KERN_DEBUG "%s: entered for port %d\n", 4499 __func__, pt + 1); 4500 4501 if (pt >= hc->ports) { 4502 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", 4503 __func__, pt + 1); 4504 return; 4505 } 4506 4507 if (debug & DEBUG_HFCMULTI_INIT) 4508 printk(KERN_DEBUG "%s: releasing port=%d\n", 4509 __func__, pt + 1); 4510 4511 if (dch->dev.D.protocol == ISDN_P_TE_S0) 4512 l1_event(dch->l1, CLOSE_CHANNEL); 4513 4514 hc->chan[ci].dch = NULL; 4515 4516 if (hc->created[pt]) { 4517 hc->created[pt] = 0; 4518 mISDN_unregister_device(&dch->dev); 4519 } 4520 4521 spin_lock_irqsave(&hc->lock, flags); 4522 4523 if (dch->timer.function) { 4524 del_timer(&dch->timer); 4525 dch->timer.function = NULL; 4526 } 4527 4528 if (hc->ctype == HFC_TYPE_E1) { /* E1 */ 4529 /* remove sync */ 4530 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4531 hc->syncronized = 0; 4532 plxsd_checksync(hc, 1); 4533 } 4534 /* free channels */ 4535 for (i = 0; i <= 31; i++) { 4536 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */ 4537 continue; 4538 if (hc->chan[i].bch) { 4539 if (debug & DEBUG_HFCMULTI_INIT) 4540 printk(KERN_DEBUG 4541 "%s: free port %d channel %d\n", 4542 __func__, hc->chan[i].port + 1, i); 4543 pb = hc->chan[i].bch; 4544 hc->chan[i].bch = NULL; 4545 spin_unlock_irqrestore(&hc->lock, flags); 4546 mISDN_freebchannel(pb); 4547 kfree(pb); 4548 kfree(hc->chan[i].coeff); 4549 spin_lock_irqsave(&hc->lock, flags); 4550 } 4551 } 4552 } else { 4553 /* remove sync */ 4554 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4555 hc->syncronized &= 4556 ~(1 << hc->chan[ci].port); 4557 plxsd_checksync(hc, 1); 4558 } 4559 /* free channels */ 4560 if (hc->chan[ci - 2].bch) { 4561 if (debug & DEBUG_HFCMULTI_INIT) 4562 printk(KERN_DEBUG 4563 "%s: free port %d channel %d\n", 4564 __func__, hc->chan[ci - 2].port + 1, 4565 ci - 2); 4566 pb = hc->chan[ci - 2].bch; 4567 hc->chan[ci - 2].bch = NULL; 4568 spin_unlock_irqrestore(&hc->lock, flags); 4569 mISDN_freebchannel(pb); 4570 kfree(pb); 4571 kfree(hc->chan[ci - 2].coeff); 4572 spin_lock_irqsave(&hc->lock, flags); 4573 } 4574 if (hc->chan[ci - 1].bch) { 4575 if (debug & DEBUG_HFCMULTI_INIT) 4576 printk(KERN_DEBUG 4577 "%s: free port %d channel %d\n", 4578 __func__, hc->chan[ci - 1].port + 1, 4579 ci - 1); 4580 pb = hc->chan[ci - 1].bch; 4581 hc->chan[ci - 1].bch = NULL; 4582 spin_unlock_irqrestore(&hc->lock, flags); 4583 mISDN_freebchannel(pb); 4584 kfree(pb); 4585 kfree(hc->chan[ci - 1].coeff); 4586 spin_lock_irqsave(&hc->lock, flags); 4587 } 4588 } 4589 4590 spin_unlock_irqrestore(&hc->lock, flags); 4591 4592 if (debug & DEBUG_HFCMULTI_INIT) 4593 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__, 4594 pt+1, ci); 4595 mISDN_freedchannel(dch); 4596 kfree(dch); 4597 4598 if (debug & DEBUG_HFCMULTI_INIT) 4599 printk(KERN_DEBUG "%s: done!\n", __func__); 4600 } 4601 4602 static void release_card(struct hfc_multi * hc)4603 release_card(struct hfc_multi *hc) 4604 { 4605 u_long flags; 4606 int ch; 4607 4608 if (debug & DEBUG_HFCMULTI_INIT) 4609 printk(KERN_DEBUG "%s: release card (%d) entered\n", 4610 __func__, hc->id); 4611 4612 /* unregister clock source */ 4613 if (hc->iclock) 4614 mISDN_unregister_clock(hc->iclock); 4615 4616 /* disable and free irq */ 4617 spin_lock_irqsave(&hc->lock, flags); 4618 disable_hwirq(hc); 4619 spin_unlock_irqrestore(&hc->lock, flags); 4620 udelay(1000); 4621 if (hc->irq) { 4622 if (debug & DEBUG_HFCMULTI_INIT) 4623 printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n", 4624 __func__, hc->irq, hc); 4625 free_irq(hc->irq, hc); 4626 hc->irq = 0; 4627 4628 } 4629 4630 /* disable D-channels & B-channels */ 4631 if (debug & DEBUG_HFCMULTI_INIT) 4632 printk(KERN_DEBUG "%s: disable all channels (d and b)\n", 4633 __func__); 4634 for (ch = 0; ch <= 31; ch++) { 4635 if (hc->chan[ch].dch) 4636 release_port(hc, hc->chan[ch].dch); 4637 } 4638 4639 /* dimm leds */ 4640 if (hc->leds) 4641 hfcmulti_leds(hc); 4642 4643 /* release hardware */ 4644 release_io_hfcmulti(hc); 4645 4646 if (debug & DEBUG_HFCMULTI_INIT) 4647 printk(KERN_DEBUG "%s: remove instance from list\n", 4648 __func__); 4649 list_del(&hc->list); 4650 4651 if (debug & DEBUG_HFCMULTI_INIT) 4652 printk(KERN_DEBUG "%s: delete instance\n", __func__); 4653 if (hc == syncmaster) 4654 syncmaster = NULL; 4655 kfree(hc); 4656 if (debug & DEBUG_HFCMULTI_INIT) 4657 printk(KERN_DEBUG "%s: card successfully removed\n", 4658 __func__); 4659 } 4660 4661 static void init_e1_port_hw(struct hfc_multi * hc,struct hm_map * m)4662 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m) 4663 { 4664 /* set optical line type */ 4665 if (port[Port_cnt] & 0x001) { 4666 if (!m->opticalsupport) { 4667 printk(KERN_INFO 4668 "This board has no optical " 4669 "support\n"); 4670 } else { 4671 if (debug & DEBUG_HFCMULTI_INIT) 4672 printk(KERN_DEBUG 4673 "%s: PORT set optical " 4674 "interfacs: card(%d) " 4675 "port(%d)\n", 4676 __func__, 4677 HFC_cnt + 1, 1); 4678 test_and_set_bit(HFC_CFG_OPTICAL, 4679 &hc->chan[hc->dnum[0]].cfg); 4680 } 4681 } 4682 /* set LOS report */ 4683 if (port[Port_cnt] & 0x004) { 4684 if (debug & DEBUG_HFCMULTI_INIT) 4685 printk(KERN_DEBUG "%s: PORT set " 4686 "LOS report: card(%d) port(%d)\n", 4687 __func__, HFC_cnt + 1, 1); 4688 test_and_set_bit(HFC_CFG_REPORT_LOS, 4689 &hc->chan[hc->dnum[0]].cfg); 4690 } 4691 /* set AIS report */ 4692 if (port[Port_cnt] & 0x008) { 4693 if (debug & DEBUG_HFCMULTI_INIT) 4694 printk(KERN_DEBUG "%s: PORT set " 4695 "AIS report: card(%d) port(%d)\n", 4696 __func__, HFC_cnt + 1, 1); 4697 test_and_set_bit(HFC_CFG_REPORT_AIS, 4698 &hc->chan[hc->dnum[0]].cfg); 4699 } 4700 /* set SLIP report */ 4701 if (port[Port_cnt] & 0x010) { 4702 if (debug & DEBUG_HFCMULTI_INIT) 4703 printk(KERN_DEBUG 4704 "%s: PORT set SLIP report: " 4705 "card(%d) port(%d)\n", 4706 __func__, HFC_cnt + 1, 1); 4707 test_and_set_bit(HFC_CFG_REPORT_SLIP, 4708 &hc->chan[hc->dnum[0]].cfg); 4709 } 4710 /* set RDI report */ 4711 if (port[Port_cnt] & 0x020) { 4712 if (debug & DEBUG_HFCMULTI_INIT) 4713 printk(KERN_DEBUG 4714 "%s: PORT set RDI report: " 4715 "card(%d) port(%d)\n", 4716 __func__, HFC_cnt + 1, 1); 4717 test_and_set_bit(HFC_CFG_REPORT_RDI, 4718 &hc->chan[hc->dnum[0]].cfg); 4719 } 4720 /* set CRC-4 Mode */ 4721 if (!(port[Port_cnt] & 0x100)) { 4722 if (debug & DEBUG_HFCMULTI_INIT) 4723 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" 4724 " card(%d) port(%d)\n", 4725 __func__, HFC_cnt + 1, 1); 4726 test_and_set_bit(HFC_CFG_CRC4, 4727 &hc->chan[hc->dnum[0]].cfg); 4728 } else { 4729 if (debug & DEBUG_HFCMULTI_INIT) 4730 printk(KERN_DEBUG "%s: PORT turn off CRC4" 4731 " report: card(%d) port(%d)\n", 4732 __func__, HFC_cnt + 1, 1); 4733 } 4734 /* set forced clock */ 4735 if (port[Port_cnt] & 0x0200) { 4736 if (debug & DEBUG_HFCMULTI_INIT) 4737 printk(KERN_DEBUG "%s: PORT force getting clock from " 4738 "E1: card(%d) port(%d)\n", 4739 __func__, HFC_cnt + 1, 1); 4740 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); 4741 } else 4742 if (port[Port_cnt] & 0x0400) { 4743 if (debug & DEBUG_HFCMULTI_INIT) 4744 printk(KERN_DEBUG "%s: PORT force putting clock to " 4745 "E1: card(%d) port(%d)\n", 4746 __func__, HFC_cnt + 1, 1); 4747 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); 4748 } 4749 /* set JATT PLL */ 4750 if (port[Port_cnt] & 0x0800) { 4751 if (debug & DEBUG_HFCMULTI_INIT) 4752 printk(KERN_DEBUG "%s: PORT disable JATT PLL on " 4753 "E1: card(%d) port(%d)\n", 4754 __func__, HFC_cnt + 1, 1); 4755 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); 4756 } 4757 /* set elastic jitter buffer */ 4758 if (port[Port_cnt] & 0x3000) { 4759 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3; 4760 if (debug & DEBUG_HFCMULTI_INIT) 4761 printk(KERN_DEBUG 4762 "%s: PORT set elastic " 4763 "buffer to %d: card(%d) port(%d)\n", 4764 __func__, hc->chan[hc->dnum[0]].jitter, 4765 HFC_cnt + 1, 1); 4766 } else 4767 hc->chan[hc->dnum[0]].jitter = 2; /* default */ 4768 } 4769 4770 static int init_e1_port(struct hfc_multi * hc,struct hm_map * m,int pt)4771 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt) 4772 { 4773 struct dchannel *dch; 4774 struct bchannel *bch; 4775 int ch, ret = 0; 4776 char name[MISDN_MAX_IDLEN]; 4777 int bcount = 0; 4778 4779 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4780 if (!dch) 4781 return -ENOMEM; 4782 dch->debug = debug; 4783 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4784 dch->hw = hc; 4785 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); 4786 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4787 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4788 dch->dev.D.send = handle_dmsg; 4789 dch->dev.D.ctrl = hfcm_dctrl; 4790 dch->slot = hc->dnum[pt]; 4791 hc->chan[hc->dnum[pt]].dch = dch; 4792 hc->chan[hc->dnum[pt]].port = pt; 4793 hc->chan[hc->dnum[pt]].nt_timer = -1; 4794 for (ch = 1; ch <= 31; ch++) { 4795 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */ 4796 continue; 4797 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4798 if (!bch) { 4799 printk(KERN_ERR "%s: no memory for bchannel\n", 4800 __func__); 4801 ret = -ENOMEM; 4802 goto free_chan; 4803 } 4804 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); 4805 if (!hc->chan[ch].coeff) { 4806 printk(KERN_ERR "%s: no memory for coeffs\n", 4807 __func__); 4808 ret = -ENOMEM; 4809 kfree(bch); 4810 goto free_chan; 4811 } 4812 bch->nr = ch; 4813 bch->slot = ch; 4814 bch->debug = debug; 4815 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1); 4816 bch->hw = hc; 4817 bch->ch.send = handle_bmsg; 4818 bch->ch.ctrl = hfcm_bctrl; 4819 bch->ch.nr = ch; 4820 list_add(&bch->ch.list, &dch->dev.bchannels); 4821 hc->chan[ch].bch = bch; 4822 hc->chan[ch].port = pt; 4823 set_channelmap(bch->nr, dch->dev.channelmap); 4824 bcount++; 4825 } 4826 dch->dev.nrbchan = bcount; 4827 if (pt == 0) 4828 init_e1_port_hw(hc, m); 4829 if (hc->ports > 1) 4830 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d", 4831 HFC_cnt + 1, pt+1); 4832 else 4833 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); 4834 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4835 if (ret) 4836 goto free_chan; 4837 hc->created[pt] = 1; 4838 return ret; 4839 free_chan: 4840 release_port(hc, dch); 4841 return ret; 4842 } 4843 4844 static int init_multi_port(struct hfc_multi * hc,int pt)4845 init_multi_port(struct hfc_multi *hc, int pt) 4846 { 4847 struct dchannel *dch; 4848 struct bchannel *bch; 4849 int ch, i, ret = 0; 4850 char name[MISDN_MAX_IDLEN]; 4851 4852 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4853 if (!dch) 4854 return -ENOMEM; 4855 dch->debug = debug; 4856 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4857 dch->hw = hc; 4858 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); 4859 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4860 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4861 dch->dev.D.send = handle_dmsg; 4862 dch->dev.D.ctrl = hfcm_dctrl; 4863 dch->dev.nrbchan = 2; 4864 i = pt << 2; 4865 dch->slot = i + 2; 4866 hc->chan[i + 2].dch = dch; 4867 hc->chan[i + 2].port = pt; 4868 hc->chan[i + 2].nt_timer = -1; 4869 for (ch = 0; ch < dch->dev.nrbchan; ch++) { 4870 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4871 if (!bch) { 4872 printk(KERN_ERR "%s: no memory for bchannel\n", 4873 __func__); 4874 ret = -ENOMEM; 4875 goto free_chan; 4876 } 4877 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); 4878 if (!hc->chan[i + ch].coeff) { 4879 printk(KERN_ERR "%s: no memory for coeffs\n", 4880 __func__); 4881 ret = -ENOMEM; 4882 kfree(bch); 4883 goto free_chan; 4884 } 4885 bch->nr = ch + 1; 4886 bch->slot = i + ch; 4887 bch->debug = debug; 4888 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1); 4889 bch->hw = hc; 4890 bch->ch.send = handle_bmsg; 4891 bch->ch.ctrl = hfcm_bctrl; 4892 bch->ch.nr = ch + 1; 4893 list_add(&bch->ch.list, &dch->dev.bchannels); 4894 hc->chan[i + ch].bch = bch; 4895 hc->chan[i + ch].port = pt; 4896 set_channelmap(bch->nr, dch->dev.channelmap); 4897 } 4898 /* set master clock */ 4899 if (port[Port_cnt] & 0x001) { 4900 if (debug & DEBUG_HFCMULTI_INIT) 4901 printk(KERN_DEBUG 4902 "%s: PROTOCOL set master clock: " 4903 "card(%d) port(%d)\n", 4904 __func__, HFC_cnt + 1, pt + 1); 4905 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 4906 printk(KERN_ERR "Error: Master clock " 4907 "for port(%d) of card(%d) is only" 4908 " possible with TE-mode\n", 4909 pt + 1, HFC_cnt + 1); 4910 ret = -EINVAL; 4911 goto free_chan; 4912 } 4913 if (hc->masterclk >= 0) { 4914 printk(KERN_ERR "Error: Master clock " 4915 "for port(%d) of card(%d) already " 4916 "defined for port(%d)\n", 4917 pt + 1, HFC_cnt + 1, hc->masterclk + 1); 4918 ret = -EINVAL; 4919 goto free_chan; 4920 } 4921 hc->masterclk = pt; 4922 } 4923 /* set transmitter line to non capacitive */ 4924 if (port[Port_cnt] & 0x002) { 4925 if (debug & DEBUG_HFCMULTI_INIT) 4926 printk(KERN_DEBUG 4927 "%s: PROTOCOL set non capacitive " 4928 "transmitter: card(%d) port(%d)\n", 4929 __func__, HFC_cnt + 1, pt + 1); 4930 test_and_set_bit(HFC_CFG_NONCAP_TX, 4931 &hc->chan[i + 2].cfg); 4932 } 4933 /* disable E-channel */ 4934 if (port[Port_cnt] & 0x004) { 4935 if (debug & DEBUG_HFCMULTI_INIT) 4936 printk(KERN_DEBUG 4937 "%s: PROTOCOL disable E-channel: " 4938 "card(%d) port(%d)\n", 4939 __func__, HFC_cnt + 1, pt + 1); 4940 test_and_set_bit(HFC_CFG_DIS_ECHANNEL, 4941 &hc->chan[i + 2].cfg); 4942 } 4943 if (hc->ctype == HFC_TYPE_XHFC) { 4944 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d", 4945 HFC_cnt + 1, pt + 1); 4946 ret = mISDN_register_device(&dch->dev, NULL, name); 4947 } else { 4948 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d", 4949 hc->ctype, HFC_cnt + 1, pt + 1); 4950 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4951 } 4952 if (ret) 4953 goto free_chan; 4954 hc->created[pt] = 1; 4955 return ret; 4956 free_chan: 4957 release_port(hc, dch); 4958 return ret; 4959 } 4960 4961 static int hfcmulti_init(struct hm_map * m,struct pci_dev * pdev,const struct pci_device_id * ent)4962 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev, 4963 const struct pci_device_id *ent) 4964 { 4965 int ret_err = 0; 4966 int pt; 4967 struct hfc_multi *hc; 4968 u_long flags; 4969 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ 4970 int i, ch; 4971 u_int maskcheck; 4972 4973 if (HFC_cnt >= MAX_CARDS) { 4974 printk(KERN_ERR "too many cards (max=%d).\n", 4975 MAX_CARDS); 4976 return -EINVAL; 4977 } 4978 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { 4979 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " 4980 "type[%d] %d was supplied as module parameter\n", 4981 m->vendor_name, m->card_name, m->type, HFC_cnt, 4982 type[HFC_cnt] & 0xff); 4983 printk(KERN_WARNING "HFC-MULTI: Load module without parameters " 4984 "first, to see cards and their types."); 4985 return -EINVAL; 4986 } 4987 if (debug & DEBUG_HFCMULTI_INIT) 4988 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", 4989 __func__, m->vendor_name, m->card_name, m->type, 4990 type[HFC_cnt]); 4991 4992 /* allocate card+fifo structure */ 4993 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); 4994 if (!hc) { 4995 printk(KERN_ERR "No kmem for HFC-Multi card\n"); 4996 return -ENOMEM; 4997 } 4998 spin_lock_init(&hc->lock); 4999 hc->mtyp = m; 5000 hc->ctype = m->type; 5001 hc->ports = m->ports; 5002 hc->id = HFC_cnt; 5003 hc->pcm = pcm[HFC_cnt]; 5004 hc->io_mode = iomode[HFC_cnt]; 5005 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) { 5006 /* fragment card */ 5007 pt = 0; 5008 maskcheck = 0; 5009 for (ch = 0; ch <= 31; ch++) { 5010 if (!((1 << ch) & dmask[E1_cnt])) 5011 continue; 5012 hc->dnum[pt] = ch; 5013 hc->bmask[pt] = bmask[bmask_cnt++]; 5014 if ((maskcheck & hc->bmask[pt]) 5015 || (dmask[E1_cnt] & hc->bmask[pt])) { 5016 printk(KERN_INFO 5017 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n", 5018 E1_cnt + 1, pt); 5019 kfree(hc); 5020 return -EINVAL; 5021 } 5022 maskcheck |= hc->bmask[pt]; 5023 printk(KERN_INFO 5024 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n", 5025 E1_cnt + 1, ch, hc->bmask[pt]); 5026 pt++; 5027 } 5028 hc->ports = pt; 5029 } 5030 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) { 5031 /* default card layout */ 5032 hc->dnum[0] = 16; 5033 hc->bmask[0] = 0xfffefffe; 5034 hc->ports = 1; 5035 } 5036 5037 /* set chip specific features */ 5038 hc->masterclk = -1; 5039 if (type[HFC_cnt] & 0x100) { 5040 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); 5041 hc->silence = 0xff; /* ulaw silence */ 5042 } else 5043 hc->silence = 0x2a; /* alaw silence */ 5044 if ((poll >> 1) > sizeof(hc->silence_data)) { 5045 printk(KERN_ERR "HFCMULTI error: silence_data too small, " 5046 "please fix\n"); 5047 kfree(hc); 5048 return -EINVAL; 5049 } 5050 for (i = 0; i < (poll >> 1); i++) 5051 hc->silence_data[i] = hc->silence; 5052 5053 if (hc->ctype != HFC_TYPE_XHFC) { 5054 if (!(type[HFC_cnt] & 0x200)) 5055 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); 5056 test_and_set_bit(HFC_CHIP_CONF, &hc->chip); 5057 } 5058 5059 if (type[HFC_cnt] & 0x800) 5060 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5061 if (type[HFC_cnt] & 0x1000) { 5062 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 5063 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5064 } 5065 if (type[HFC_cnt] & 0x4000) 5066 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); 5067 if (type[HFC_cnt] & 0x8000) 5068 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); 5069 hc->slots = 32; 5070 if (type[HFC_cnt] & 0x10000) 5071 hc->slots = 64; 5072 if (type[HFC_cnt] & 0x20000) 5073 hc->slots = 128; 5074 if (type[HFC_cnt] & 0x80000) { 5075 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); 5076 hc->wdcount = 0; 5077 hc->wdbyte = V_GPIO_OUT2; 5078 printk(KERN_NOTICE "Watchdog enabled\n"); 5079 } 5080 5081 if (pdev && ent) 5082 /* setup pci, hc->slots may change due to PLXSD */ 5083 ret_err = setup_pci(hc, pdev, ent); 5084 else 5085 #ifdef CONFIG_MISDN_HFCMULTI_8xx 5086 ret_err = setup_embedded(hc, m); 5087 #else 5088 { 5089 printk(KERN_WARNING "Embedded IO Mode not selected\n"); 5090 ret_err = -EIO; 5091 } 5092 #endif 5093 if (ret_err) { 5094 if (hc == syncmaster) 5095 syncmaster = NULL; 5096 kfree(hc); 5097 return ret_err; 5098 } 5099 5100 hc->HFC_outb_nodebug = hc->HFC_outb; 5101 hc->HFC_inb_nodebug = hc->HFC_inb; 5102 hc->HFC_inw_nodebug = hc->HFC_inw; 5103 hc->HFC_wait_nodebug = hc->HFC_wait; 5104 #ifdef HFC_REGISTER_DEBUG 5105 hc->HFC_outb = HFC_outb_debug; 5106 hc->HFC_inb = HFC_inb_debug; 5107 hc->HFC_inw = HFC_inw_debug; 5108 hc->HFC_wait = HFC_wait_debug; 5109 #endif 5110 /* create channels */ 5111 for (pt = 0; pt < hc->ports; pt++) { 5112 if (Port_cnt >= MAX_PORTS) { 5113 printk(KERN_ERR "too many ports (max=%d).\n", 5114 MAX_PORTS); 5115 ret_err = -EINVAL; 5116 goto free_card; 5117 } 5118 if (hc->ctype == HFC_TYPE_E1) 5119 ret_err = init_e1_port(hc, m, pt); 5120 else 5121 ret_err = init_multi_port(hc, pt); 5122 if (debug & DEBUG_HFCMULTI_INIT) 5123 printk(KERN_DEBUG 5124 "%s: Registering D-channel, card(%d) port(%d) " 5125 "result %d\n", 5126 __func__, HFC_cnt + 1, pt + 1, ret_err); 5127 5128 if (ret_err) { 5129 while (pt) { /* release already registered ports */ 5130 pt--; 5131 if (hc->ctype == HFC_TYPE_E1) 5132 release_port(hc, 5133 hc->chan[hc->dnum[pt]].dch); 5134 else 5135 release_port(hc, 5136 hc->chan[(pt << 2) + 2].dch); 5137 } 5138 goto free_card; 5139 } 5140 if (hc->ctype != HFC_TYPE_E1) 5141 Port_cnt++; /* for each S0 port */ 5142 } 5143 if (hc->ctype == HFC_TYPE_E1) { 5144 Port_cnt++; /* for each E1 port */ 5145 E1_cnt++; 5146 } 5147 5148 /* disp switches */ 5149 switch (m->dip_type) { 5150 case DIP_4S: 5151 /* 5152 * Get DIP setting for beroNet 1S/2S/4S cards 5153 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + 5154 * GPI 19/23 (R_GPI_IN2)) 5155 */ 5156 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | 5157 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | 5158 (~HFC_inb(hc, R_GPI_IN2) & 0x08); 5159 5160 /* Port mode (TE/NT) jumpers */ 5161 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); 5162 5163 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 5164 pmj = ~pmj & 0xf; 5165 5166 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", 5167 m->vendor_name, m->card_name, dips, pmj); 5168 break; 5169 case DIP_8S: 5170 /* 5171 * Get DIP Setting for beroNet 8S0+ cards 5172 * Enable PCI auxbridge function 5173 */ 5174 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 5175 /* prepare access to auxport */ 5176 outw(0x4000, hc->pci_iobase + 4); 5177 /* 5178 * some dummy reads are required to 5179 * read valid DIP switch data 5180 */ 5181 dips = inb(hc->pci_iobase); 5182 dips = inb(hc->pci_iobase); 5183 dips = inb(hc->pci_iobase); 5184 dips = ~inb(hc->pci_iobase) & 0x3F; 5185 outw(0x0, hc->pci_iobase + 4); 5186 /* disable PCI auxbridge function */ 5187 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 5188 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5189 m->vendor_name, m->card_name, dips); 5190 break; 5191 case DIP_E1: 5192 /* 5193 * get DIP Setting for beroNet E1 cards 5194 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) 5195 */ 5196 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4; 5197 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5198 m->vendor_name, m->card_name, dips); 5199 break; 5200 } 5201 5202 /* add to list */ 5203 spin_lock_irqsave(&HFClock, flags); 5204 list_add_tail(&hc->list, &HFClist); 5205 spin_unlock_irqrestore(&HFClock, flags); 5206 5207 /* use as clock source */ 5208 if (clock == HFC_cnt + 1) 5209 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc); 5210 5211 /* initialize hardware */ 5212 hc->irq = (m->irq) ? : hc->pci_dev->irq; 5213 ret_err = init_card(hc); 5214 if (ret_err) { 5215 printk(KERN_ERR "init card returns %d\n", ret_err); 5216 release_card(hc); 5217 return ret_err; 5218 } 5219 5220 /* start IRQ and return */ 5221 spin_lock_irqsave(&hc->lock, flags); 5222 enable_hwirq(hc); 5223 spin_unlock_irqrestore(&hc->lock, flags); 5224 return 0; 5225 5226 free_card: 5227 release_io_hfcmulti(hc); 5228 if (hc == syncmaster) 5229 syncmaster = NULL; 5230 kfree(hc); 5231 return ret_err; 5232 } 5233 hfc_remove_pci(struct pci_dev * pdev)5234 static void hfc_remove_pci(struct pci_dev *pdev) 5235 { 5236 struct hfc_multi *card = pci_get_drvdata(pdev); 5237 u_long flags; 5238 5239 if (debug) 5240 printk(KERN_INFO "removing hfc_multi card vendor:%x " 5241 "device:%x subvendor:%x subdevice:%x\n", 5242 pdev->vendor, pdev->device, 5243 pdev->subsystem_vendor, pdev->subsystem_device); 5244 5245 if (card) { 5246 spin_lock_irqsave(&HFClock, flags); 5247 release_card(card); 5248 spin_unlock_irqrestore(&HFClock, flags); 5249 } else { 5250 if (debug) 5251 printk(KERN_DEBUG "%s: drvdata already removed\n", 5252 __func__); 5253 } 5254 } 5255 5256 #define VENDOR_CCD "Cologne Chip AG" 5257 #define VENDOR_BN "beroNet GmbH" 5258 #define VENDOR_DIG "Digium Inc." 5259 #define VENDOR_JH "Junghanns.NET GmbH" 5260 #define VENDOR_PRIM "PrimuX" 5261 5262 static const struct hm_map hfcm_map[] = { 5263 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0}, 5264 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5265 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5266 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5267 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0}, 5268 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0}, 5269 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5270 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0}, 5271 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0}, 5272 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0}, 5273 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0}, 5274 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0}, 5275 5276 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0}, 5277 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, 5278 HFC_IO_MODE_REGIO, 0}, 5279 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0}, 5280 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0}, 5281 5282 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0}, 5283 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5284 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5285 5286 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5287 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0}, 5288 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5289 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5290 5291 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0}, 5292 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5293 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5294 5295 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, 5296 HFC_IO_MODE_PLXSD, 0}, 5297 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, 5298 HFC_IO_MODE_PLXSD, 0}, 5299 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0}, 5300 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0}, 5301 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0}, 5302 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0, 5303 HFC_IO_MODE_EMBSD, XHFC_IRQ}, 5304 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0}, 5305 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5306 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5307 }; 5308 5309 #undef H 5310 #define H(x) ((unsigned long)&hfcm_map[x]) 5311 static const struct pci_device_id hfmultipci_ids[] = { 5312 5313 /* Cards with HFC-4S Chip */ 5314 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5315 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ 5316 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5317 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ 5318 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5319 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ 5320 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5321 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ 5322 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5323 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ 5324 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5325 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ 5326 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5327 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ 5328 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5329 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ 5330 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 5331 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, 5332 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5333 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ 5334 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5335 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, 5336 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5337 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ 5338 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5339 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ 5340 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5341 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ 5342 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5343 0xb761, 0, 0, H(33)}, /* BN2S PCIe */ 5344 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5345 0xb762, 0, 0, H(34)}, /* BN4S PCIe */ 5346 5347 /* Cards with HFC-8S Chip */ 5348 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5349 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ 5350 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5351 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ 5352 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5353 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ 5354 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5355 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */ 5356 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5357 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ 5358 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5359 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ 5360 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5361 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ 5362 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5363 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ 5364 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5365 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */ 5366 5367 5368 /* Cards with HFC-E1 Chip */ 5369 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5370 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ 5371 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5372 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ 5373 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5374 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ 5375 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5376 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ 5377 5378 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5379 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ 5380 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5381 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ 5382 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5383 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ 5384 5385 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5386 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ 5387 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5388 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ 5389 5390 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5391 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */ 5392 5393 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 }, 5394 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 }, 5395 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 }, 5396 {0, } 5397 }; 5398 #undef H 5399 5400 MODULE_DEVICE_TABLE(pci, hfmultipci_ids); 5401 5402 static int hfcmulti_probe(struct pci_dev * pdev,const struct pci_device_id * ent)5403 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 5404 { 5405 struct hm_map *m = (struct hm_map *)ent->driver_data; 5406 int ret; 5407 5408 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && ( 5409 ent->device == PCI_DEVICE_ID_CCD_HFC4S || 5410 ent->device == PCI_DEVICE_ID_CCD_HFC8S || 5411 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) { 5412 printk(KERN_ERR 5413 "Unknown HFC multiport controller (vendor:%04x device:%04x " 5414 "subvendor:%04x subdevice:%04x)\n", pdev->vendor, 5415 pdev->device, pdev->subsystem_vendor, 5416 pdev->subsystem_device); 5417 printk(KERN_ERR 5418 "Please contact the driver maintainer for support.\n"); 5419 return -ENODEV; 5420 } 5421 ret = hfcmulti_init(m, pdev, ent); 5422 if (ret) 5423 return ret; 5424 HFC_cnt++; 5425 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5426 return 0; 5427 } 5428 5429 static struct pci_driver hfcmultipci_driver = { 5430 .name = "hfc_multi", 5431 .probe = hfcmulti_probe, 5432 .remove = hfc_remove_pci, 5433 .id_table = hfmultipci_ids, 5434 }; 5435 5436 static void __exit HFCmulti_cleanup(void)5437 HFCmulti_cleanup(void) 5438 { 5439 struct hfc_multi *card, *next; 5440 5441 /* get rid of all devices of this driver */ 5442 list_for_each_entry_safe(card, next, &HFClist, list) 5443 release_card(card); 5444 pci_unregister_driver(&hfcmultipci_driver); 5445 } 5446 5447 static int __init HFCmulti_init(void)5448 HFCmulti_init(void) 5449 { 5450 int err; 5451 int i, xhfc = 0; 5452 struct hm_map m; 5453 5454 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION); 5455 5456 #ifdef IRQ_DEBUG 5457 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__); 5458 #endif 5459 5460 if (debug & DEBUG_HFCMULTI_INIT) 5461 printk(KERN_DEBUG "%s: init entered\n", __func__); 5462 5463 switch (poll) { 5464 case 0: 5465 poll_timer = 6; 5466 poll = 128; 5467 break; 5468 case 8: 5469 poll_timer = 2; 5470 break; 5471 case 16: 5472 poll_timer = 3; 5473 break; 5474 case 32: 5475 poll_timer = 4; 5476 break; 5477 case 64: 5478 poll_timer = 5; 5479 break; 5480 case 128: 5481 poll_timer = 6; 5482 break; 5483 case 256: 5484 poll_timer = 7; 5485 break; 5486 default: 5487 printk(KERN_ERR 5488 "%s: Wrong poll value (%d).\n", __func__, poll); 5489 err = -EINVAL; 5490 return err; 5491 5492 } 5493 5494 if (!clock) 5495 clock = 1; 5496 5497 /* Register the embedded devices. 5498 * This should be done before the PCI cards registration */ 5499 switch (hwid) { 5500 case HWID_MINIP4: 5501 xhfc = 1; 5502 m = hfcm_map[31]; 5503 break; 5504 case HWID_MINIP8: 5505 xhfc = 2; 5506 m = hfcm_map[31]; 5507 break; 5508 case HWID_MINIP16: 5509 xhfc = 4; 5510 m = hfcm_map[31]; 5511 break; 5512 default: 5513 xhfc = 0; 5514 } 5515 5516 for (i = 0; i < xhfc; ++i) { 5517 err = hfcmulti_init(&m, NULL, NULL); 5518 if (err) { 5519 printk(KERN_ERR "error registering embedded driver: " 5520 "%x\n", err); 5521 return err; 5522 } 5523 HFC_cnt++; 5524 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5525 } 5526 5527 /* Register the PCI cards */ 5528 err = pci_register_driver(&hfcmultipci_driver); 5529 if (err < 0) { 5530 printk(KERN_ERR "error registering pci driver: %x\n", err); 5531 return err; 5532 } 5533 5534 return 0; 5535 } 5536 5537 5538 module_init(HFCmulti_init); 5539 module_exit(HFCmulti_cleanup); 5540