1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * CE4100 on Falcon Falls 4 * 5 * (c) Copyright 2010 Intel Corporation 6 */ 7/dts-v1/; 8/ { 9 model = "intel,falconfalls"; 10 compatible = "intel,falconfalls"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "intel,ce4100"; 21 reg = <0>; 22 lapic = <&lapic0>; 23 }; 24 }; 25 26 soc@0 { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "intel,ce4100-cp"; 30 ranges; 31 32 ioapic1: interrupt-controller@fec00000 { 33 #interrupt-cells = <2>; 34 compatible = "intel,ce4100-ioapic"; 35 interrupt-controller; 36 reg = <0xfec00000 0x1000>; 37 }; 38 39 timer@fed00000 { 40 compatible = "intel,ce4100-hpet"; 41 reg = <0xfed00000 0x200>; 42 }; 43 44 lapic0: interrupt-controller@fee00000 { 45 compatible = "intel,ce4100-lapic"; 46 reg = <0xfee00000 0x1000>; 47 }; 48 49 pci@3fc { 50 #address-cells = <3>; 51 #size-cells = <2>; 52 compatible = "intel,ce4100-pci", "pci"; 53 device_type = "pci"; 54 bus-range = <0 0>; 55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000 56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000 57 0x0000000 0 0x0 0x0 0 0x100>; 58 59 /* Secondary IO-APIC */ 60 ioapic2: interrupt-controller@0,1 { 61 #interrupt-cells = <2>; 62 compatible = "intel,ce4100-ioapic"; 63 interrupt-controller; 64 reg = <0x100 0x0 0x0 0x0 0x0>; 65 assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>; 66 }; 67 68 pci@1,0 { 69 #address-cells = <3>; 70 #size-cells = <2>; 71 compatible = "intel,ce4100-pci", "pci"; 72 device_type = "pci"; 73 bus-range = <1 1>; 74 reg = <0x0800 0x0 0x0 0x0 0x0>; 75 ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>; 76 77 interrupt-parent = <&ioapic2>; 78 79 display@2,0 { 80 compatible = "pci8086,2e5b.2", 81 "pci8086,2e5b", 82 "pciclass038000", 83 "pciclass0380"; 84 85 reg = <0x11000 0x0 0x0 0x0 0x0>; 86 interrupts = <0 1>; 87 }; 88 89 multimedia@3,0 { 90 compatible = "pci8086,2e5c.2", 91 "pci8086,2e5c", 92 "pciclass048000", 93 "pciclass0480"; 94 95 reg = <0x11800 0x0 0x0 0x0 0x0>; 96 interrupts = <2 1>; 97 }; 98 99 multimedia@4,0 { 100 compatible = "pci8086,2e5d.2", 101 "pci8086,2e5d", 102 "pciclass048000", 103 "pciclass0480"; 104 105 reg = <0x12000 0x0 0x0 0x0 0x0>; 106 interrupts = <4 1>; 107 }; 108 109 multimedia@4,1 { 110 compatible = "pci8086,2e5e.2", 111 "pci8086,2e5e", 112 "pciclass048000", 113 "pciclass0480"; 114 115 reg = <0x12100 0x0 0x0 0x0 0x0>; 116 interrupts = <5 1>; 117 }; 118 119 sound@6,0 { 120 compatible = "pci8086,2e5f.2", 121 "pci8086,2e5f", 122 "pciclass040100", 123 "pciclass0401"; 124 125 reg = <0x13000 0x0 0x0 0x0 0x0>; 126 interrupts = <6 1>; 127 }; 128 129 sound@6,1 { 130 compatible = "pci8086,2e5f.2", 131 "pci8086,2e5f", 132 "pciclass040100", 133 "pciclass0401"; 134 135 reg = <0x13100 0x0 0x0 0x0 0x0>; 136 interrupts = <7 1>; 137 }; 138 139 sound@6,2 { 140 compatible = "pci8086,2e60.2", 141 "pci8086,2e60", 142 "pciclass040100", 143 "pciclass0401"; 144 145 reg = <0x13200 0x0 0x0 0x0 0x0>; 146 interrupts = <8 1>; 147 }; 148 149 display@8,0 { 150 compatible = "pci8086,2e61.2", 151 "pci8086,2e61", 152 "pciclass038000", 153 "pciclass0380"; 154 155 reg = <0x14000 0x0 0x0 0x0 0x0>; 156 interrupts = <9 1>; 157 }; 158 159 display@8,1 { 160 compatible = "pci8086,2e62.2", 161 "pci8086,2e62", 162 "pciclass038000", 163 "pciclass0380"; 164 165 reg = <0x14100 0x0 0x0 0x0 0x0>; 166 interrupts = <10 1>; 167 }; 168 169 multimedia@8,2 { 170 compatible = "pci8086,2e63.2", 171 "pci8086,2e63", 172 "pciclass048000", 173 "pciclass0480"; 174 175 reg = <0x14200 0x0 0x0 0x0 0x0>; 176 interrupts = <11 1>; 177 }; 178 179 entertainment-encryption@9,0 { 180 compatible = "pci8086,2e64.2", 181 "pci8086,2e64", 182 "pciclass101000", 183 "pciclass1010"; 184 185 reg = <0x14800 0x0 0x0 0x0 0x0>; 186 interrupts = <12 1>; 187 }; 188 189 localbus@a,0 { 190 compatible = "pci8086,2e65.2", 191 "pci8086,2e65", 192 "pciclassff0000", 193 "pciclassff00"; 194 195 reg = <0x15000 0x0 0x0 0x0 0x0>; 196 }; 197 198 serial@b,0 { 199 compatible = "pci8086,2e66.2", 200 "pci8086,2e66", 201 "pciclass070003", 202 "pciclass0700"; 203 204 reg = <0x15800 0x0 0x0 0x0 0x0>; 205 interrupts = <14 1>; 206 }; 207 208 pcigpio: gpio@b,1 { 209 #gpio-cells = <2>; 210 #interrupt-cells = <2>; 211 compatible = "pci8086,2e67.2", 212 "pci8086,2e67", 213 "pciclassff0000", 214 "pciclassff00"; 215 216 reg = <0x15900 0x0 0x0 0x0 0x0>; 217 interrupts = <15 1>; 218 interrupt-controller; 219 gpio-controller; 220 intel,muxctl = <0>; 221 }; 222 223 i2c-controller@b,2 { 224 #address-cells = <2>; 225 #size-cells = <1>; 226 compatible = "pci8086,2e68.2", 227 "pci8086,2e68", 228 "pciclass,ff0000", 229 "pciclass,ff00"; 230 231 reg = <0x15a00 0x0 0x0 0x0 0x0>; 232 interrupts = <16 1>; 233 ranges = <0 0 0x02000000 0 0xdffe0500 0x100 234 1 0 0x02000000 0 0xdffe0600 0x100 235 2 0 0x02000000 0 0xdffe0700 0x100>; 236 237 i2c@0 { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 compatible = "intel,ce4100-i2c-controller"; 241 reg = <0 0 0x100>; 242 }; 243 244 i2c@1 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "intel,ce4100-i2c-controller"; 248 reg = <1 0 0x100>; 249 250 gpio@26 { 251 #gpio-cells = <2>; 252 compatible = "nxp,pcf8575"; 253 reg = <0x26>; 254 gpio-controller; 255 }; 256 }; 257 258 i2c@2 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "intel,ce4100-i2c-controller"; 262 reg = <2 0 0x100>; 263 264 gpio@26 { 265 #gpio-cells = <2>; 266 compatible = "nxp,pcf8575"; 267 reg = <0x26>; 268 gpio-controller; 269 }; 270 }; 271 }; 272 273 smard-card@b,3 { 274 compatible = "pci8086,2e69.2", 275 "pci8086,2e69", 276 "pciclass070500", 277 "pciclass0705"; 278 279 reg = <0x15b00 0x0 0x0 0x0 0x0>; 280 interrupts = <15 1>; 281 }; 282 283 spi-controller@b,4 { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 compatible = 287 "pci8086,2e6a.2", 288 "pci8086,2e6a", 289 "pciclass,ff0000", 290 "pciclass,ff00"; 291 292 reg = <0x15c00 0x0 0x0 0x0 0x0>; 293 interrupts = <15 1>; 294 295 dac@0 { 296 compatible = "ti,pcm1755"; 297 reg = <0>; 298 spi-max-frequency = <115200>; 299 }; 300 301 dac@1 { 302 compatible = "ti,pcm1609a"; 303 reg = <1>; 304 spi-max-frequency = <115200>; 305 }; 306 307 eeprom@2 { 308 compatible = "atmel,at93c46"; 309 reg = <2>; 310 spi-max-frequency = <115200>; 311 }; 312 }; 313 314 multimedia@b,7 { 315 compatible = "pci8086,2e6d.2", 316 "pci8086,2e6d", 317 "pciclassff0000", 318 "pciclassff00"; 319 320 reg = <0x15f00 0x0 0x0 0x0 0x0>; 321 }; 322 323 ethernet@c,0 { 324 compatible = "pci8086,2e6e.2", 325 "pci8086,2e6e", 326 "pciclass020000", 327 "pciclass0200"; 328 329 reg = <0x16000 0x0 0x0 0x0 0x0>; 330 interrupts = <21 1>; 331 }; 332 333 clock@c,1 { 334 compatible = "pci8086,2e6f.2", 335 "pci8086,2e6f", 336 "pciclassff0000", 337 "pciclassff00"; 338 339 reg = <0x16100 0x0 0x0 0x0 0x0>; 340 interrupts = <3 1>; 341 }; 342 343 usb@d,0 { 344 compatible = "pci8086,2e70.2", 345 "pci8086,2e70", 346 "pciclass0c0320", 347 "pciclass0c03"; 348 349 reg = <0x16800 0x0 0x0 0x0 0x0>; 350 interrupts = <22 1>; 351 }; 352 353 usb@d,1 { 354 compatible = "pci8086,2e70.2", 355 "pci8086,2e70", 356 "pciclass0c0320", 357 "pciclass0c03"; 358 359 reg = <0x16900 0x0 0x0 0x0 0x0>; 360 interrupts = <22 1>; 361 }; 362 363 sata@e,0 { 364 compatible = "pci8086,2e71.0", 365 "pci8086,2e71", 366 "pciclass010601", 367 "pciclass0106"; 368 369 reg = <0x17000 0x0 0x0 0x0 0x0>; 370 interrupts = <23 1>; 371 }; 372 373 flash@f,0 { 374 compatible = "pci8086,701.1", 375 "pci8086,701", 376 "pciclass050100", 377 "pciclass0501"; 378 379 reg = <0x17800 0x0 0x0 0x0 0x0>; 380 interrupts = <13 1>; 381 }; 382 383 entertainment-encryption@10,0 { 384 compatible = "pci8086,702.1", 385 "pci8086,702", 386 "pciclass101000", 387 "pciclass1010"; 388 389 reg = <0x18000 0x0 0x0 0x0 0x0>; 390 }; 391 392 co-processor@11,0 { 393 compatible = "pci8086,703.1", 394 "pci8086,703", 395 "pciclass0b4000", 396 "pciclass0b40"; 397 398 reg = <0x18800 0x0 0x0 0x0 0x0>; 399 interrupts = <1 1>; 400 }; 401 402 multimedia@12,0 { 403 compatible = "pci8086,704.0", 404 "pci8086,704", 405 "pciclass048000", 406 "pciclass0480"; 407 408 reg = <0x19000 0x0 0x0 0x0 0x0>; 409 }; 410 }; 411 412 isa@1f,0 { 413 #address-cells = <2>; 414 #size-cells = <1>; 415 compatible = "isa"; 416 reg = <0xf800 0x0 0x0 0x0 0x0>; 417 ranges = <1 0 0 0 0 0x100>; 418 419 rtc@70 { 420 compatible = "intel,ce4100-rtc", "motorola,mc146818"; 421 interrupts = <8 3>; 422 interrupt-parent = <&ioapic1>; 423 ctrl-reg = <2>; 424 freq-reg = <0x26>; 425 reg = <1 0x70 2>; 426 }; 427 }; 428 }; 429 }; 430}; 431