1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/mailbox/tegra186-hsp.h> 7 #include <dt-bindings/memory/tegra234-mc.h> 8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9 #include <dt-bindings/power/tegra234-powergate.h> 10 #include <dt-bindings/reset/tegra234-reset.h> 11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 12 13 / { 14 compatible = "nvidia,tegra234"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 bus@0 { 20 compatible = "simple-bus"; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra234-misc"; 28 reg = <0x0 0x00100000 0x0 0xf000>, 29 <0x0 0x0010f000 0x0 0x1000>; 30 status = "okay"; 31 }; 32 33 timer@2080000 { 34 compatible = "nvidia,tegra234-timer"; 35 reg = <0x0 0x02080000 0x0 0x00121000>; 36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 52 status = "okay"; 53 }; 54 55 gpio: gpio@2200000 { 56 compatible = "nvidia,tegra234-gpio"; 57 reg-names = "security", "gpio"; 58 reg = <0x0 0x02200000 0x0 0x10000>, 59 <0x0 0x02210000 0x0 0x10000>; 60 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 108 #interrupt-cells = <2>; 109 interrupt-controller; 110 #gpio-cells = <2>; 111 gpio-controller; 112 gpio-ranges = <&pinmux 0 0 164>; 113 }; 114 115 pinmux: pinmux@2430000 { 116 compatible = "nvidia,tegra234-pinmux"; 117 reg = <0x0 0x2430000 0x0 0x19100>; 118 }; 119 120 gpcdma: dma-controller@2600000 { 121 compatible = "nvidia,tegra234-gpcdma", 122 "nvidia,tegra186-gpcdma"; 123 reg = <0x0 0x2600000 0x0 0x210000>; 124 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 125 reset-names = "gpcdma"; 126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 158 #dma-cells = <1>; 159 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 160 dma-channel-mask = <0xfffffffe>; 161 dma-coherent; 162 }; 163 164 aconnect@2900000 { 165 compatible = "nvidia,tegra234-aconnect", 166 "nvidia,tegra210-aconnect"; 167 clocks = <&bpmp TEGRA234_CLK_APE>, 168 <&bpmp TEGRA234_CLK_APB2APE>; 169 clock-names = "ape", "apb2ape"; 170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 171 status = "disabled"; 172 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 176 177 tegra_ahub: ahub@2900800 { 178 compatible = "nvidia,tegra234-ahub"; 179 reg = <0x0 0x02900800 0x0 0x800>; 180 clocks = <&bpmp TEGRA234_CLK_AHUB>; 181 clock-names = "ahub"; 182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 184 assigned-clock-rates = <81600000>; 185 status = "disabled"; 186 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 190 191 tegra_i2s1: i2s@2901000 { 192 compatible = "nvidia,tegra234-i2s", 193 "nvidia,tegra210-i2s"; 194 reg = <0x0 0x2901000 0x0 0x100>; 195 clocks = <&bpmp TEGRA234_CLK_I2S1>, 196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 197 clock-names = "i2s", "sync_input"; 198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 200 assigned-clock-rates = <1536000>; 201 sound-name-prefix = "I2S1"; 202 status = "disabled"; 203 }; 204 205 tegra_i2s2: i2s@2901100 { 206 compatible = "nvidia,tegra234-i2s", 207 "nvidia,tegra210-i2s"; 208 reg = <0x0 0x2901100 0x0 0x100>; 209 clocks = <&bpmp TEGRA234_CLK_I2S2>, 210 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 211 clock-names = "i2s", "sync_input"; 212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 214 assigned-clock-rates = <1536000>; 215 sound-name-prefix = "I2S2"; 216 status = "disabled"; 217 }; 218 219 tegra_i2s3: i2s@2901200 { 220 compatible = "nvidia,tegra234-i2s", 221 "nvidia,tegra210-i2s"; 222 reg = <0x0 0x2901200 0x0 0x100>; 223 clocks = <&bpmp TEGRA234_CLK_I2S3>, 224 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 225 clock-names = "i2s", "sync_input"; 226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 228 assigned-clock-rates = <1536000>; 229 sound-name-prefix = "I2S3"; 230 status = "disabled"; 231 }; 232 233 tegra_i2s4: i2s@2901300 { 234 compatible = "nvidia,tegra234-i2s", 235 "nvidia,tegra210-i2s"; 236 reg = <0x0 0x2901300 0x0 0x100>; 237 clocks = <&bpmp TEGRA234_CLK_I2S4>, 238 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 239 clock-names = "i2s", "sync_input"; 240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 242 assigned-clock-rates = <1536000>; 243 sound-name-prefix = "I2S4"; 244 status = "disabled"; 245 }; 246 247 tegra_i2s5: i2s@2901400 { 248 compatible = "nvidia,tegra234-i2s", 249 "nvidia,tegra210-i2s"; 250 reg = <0x0 0x2901400 0x0 0x100>; 251 clocks = <&bpmp TEGRA234_CLK_I2S5>, 252 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 253 clock-names = "i2s", "sync_input"; 254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 256 assigned-clock-rates = <1536000>; 257 sound-name-prefix = "I2S5"; 258 status = "disabled"; 259 }; 260 261 tegra_i2s6: i2s@2901500 { 262 compatible = "nvidia,tegra234-i2s", 263 "nvidia,tegra210-i2s"; 264 reg = <0x0 0x2901500 0x0 0x100>; 265 clocks = <&bpmp TEGRA234_CLK_I2S6>, 266 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 267 clock-names = "i2s", "sync_input"; 268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 270 assigned-clock-rates = <1536000>; 271 sound-name-prefix = "I2S6"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc1: sfc@2902000 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902000 0x0 0x200>; 279 sound-name-prefix = "SFC1"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc2: sfc@2902200 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902200 0x0 0x200>; 287 sound-name-prefix = "SFC2"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc3: sfc@2902400 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902400 0x0 0x200>; 295 sound-name-prefix = "SFC3"; 296 status = "disabled"; 297 }; 298 299 tegra_sfc4: sfc@2902600 { 300 compatible = "nvidia,tegra234-sfc", 301 "nvidia,tegra210-sfc"; 302 reg = <0x0 0x2902600 0x0 0x200>; 303 sound-name-prefix = "SFC4"; 304 status = "disabled"; 305 }; 306 307 tegra_amx1: amx@2903000 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903000 0x0 0x100>; 311 sound-name-prefix = "AMX1"; 312 status = "disabled"; 313 }; 314 315 tegra_amx2: amx@2903100 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903100 0x0 0x100>; 319 sound-name-prefix = "AMX2"; 320 status = "disabled"; 321 }; 322 323 tegra_amx3: amx@2903200 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903200 0x0 0x100>; 327 sound-name-prefix = "AMX3"; 328 status = "disabled"; 329 }; 330 331 tegra_amx4: amx@2903300 { 332 compatible = "nvidia,tegra234-amx", 333 "nvidia,tegra194-amx"; 334 reg = <0x0 0x2903300 0x0 0x100>; 335 sound-name-prefix = "AMX4"; 336 status = "disabled"; 337 }; 338 339 tegra_adx1: adx@2903800 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903800 0x0 0x100>; 343 sound-name-prefix = "ADX1"; 344 status = "disabled"; 345 }; 346 347 tegra_adx2: adx@2903900 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903900 0x0 0x100>; 351 sound-name-prefix = "ADX2"; 352 status = "disabled"; 353 }; 354 355 tegra_adx3: adx@2903a00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903a00 0x0 0x100>; 359 sound-name-prefix = "ADX3"; 360 status = "disabled"; 361 }; 362 363 tegra_adx4: adx@2903b00 { 364 compatible = "nvidia,tegra234-adx", 365 "nvidia,tegra210-adx"; 366 reg = <0x0 0x2903b00 0x0 0x100>; 367 sound-name-prefix = "ADX4"; 368 status = "disabled"; 369 }; 370 371 372 tegra_dmic1: dmic@2904000 { 373 compatible = "nvidia,tegra234-dmic", 374 "nvidia,tegra210-dmic"; 375 reg = <0x0 0x2904000 0x0 0x100>; 376 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 377 clock-names = "dmic"; 378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 380 assigned-clock-rates = <3072000>; 381 sound-name-prefix = "DMIC1"; 382 status = "disabled"; 383 }; 384 385 tegra_dmic2: dmic@2904100 { 386 compatible = "nvidia,tegra234-dmic", 387 "nvidia,tegra210-dmic"; 388 reg = <0x0 0x2904100 0x0 0x100>; 389 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 390 clock-names = "dmic"; 391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 393 assigned-clock-rates = <3072000>; 394 sound-name-prefix = "DMIC2"; 395 status = "disabled"; 396 }; 397 398 tegra_dmic3: dmic@2904200 { 399 compatible = "nvidia,tegra234-dmic", 400 "nvidia,tegra210-dmic"; 401 reg = <0x0 0x2904200 0x0 0x100>; 402 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 403 clock-names = "dmic"; 404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 406 assigned-clock-rates = <3072000>; 407 sound-name-prefix = "DMIC3"; 408 status = "disabled"; 409 }; 410 411 tegra_dmic4: dmic@2904300 { 412 compatible = "nvidia,tegra234-dmic", 413 "nvidia,tegra210-dmic"; 414 reg = <0x0 0x2904300 0x0 0x100>; 415 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 416 clock-names = "dmic"; 417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 419 assigned-clock-rates = <3072000>; 420 sound-name-prefix = "DMIC4"; 421 status = "disabled"; 422 }; 423 424 tegra_dspk1: dspk@2905000 { 425 compatible = "nvidia,tegra234-dspk", 426 "nvidia,tegra186-dspk"; 427 reg = <0x0 0x2905000 0x0 0x100>; 428 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 429 clock-names = "dspk"; 430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 432 assigned-clock-rates = <12288000>; 433 sound-name-prefix = "DSPK1"; 434 status = "disabled"; 435 }; 436 437 tegra_dspk2: dspk@2905100 { 438 compatible = "nvidia,tegra234-dspk", 439 "nvidia,tegra186-dspk"; 440 reg = <0x0 0x2905100 0x0 0x100>; 441 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 442 clock-names = "dspk"; 443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 445 assigned-clock-rates = <12288000>; 446 sound-name-prefix = "DSPK2"; 447 status = "disabled"; 448 }; 449 450 tegra_ope1: processing-engine@2908000 { 451 compatible = "nvidia,tegra234-ope", 452 "nvidia,tegra210-ope"; 453 reg = <0x0 0x2908000 0x0 0x100>; 454 sound-name-prefix = "OPE1"; 455 status = "disabled"; 456 457 #address-cells = <2>; 458 #size-cells = <2>; 459 ranges; 460 461 equalizer@2908100 { 462 compatible = "nvidia,tegra234-peq", 463 "nvidia,tegra210-peq"; 464 reg = <0x0 0x2908100 0x0 0x100>; 465 }; 466 467 dynamic-range-compressor@2908200 { 468 compatible = "nvidia,tegra234-mbdrc", 469 "nvidia,tegra210-mbdrc"; 470 reg = <0x0 0x2908200 0x0 0x200>; 471 }; 472 }; 473 474 tegra_mvc1: mvc@290a000 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a000 0x0 0x200>; 478 sound-name-prefix = "MVC1"; 479 status = "disabled"; 480 }; 481 482 tegra_mvc2: mvc@290a200 { 483 compatible = "nvidia,tegra234-mvc", 484 "nvidia,tegra210-mvc"; 485 reg = <0x0 0x290a200 0x0 0x200>; 486 sound-name-prefix = "MVC2"; 487 status = "disabled"; 488 }; 489 490 tegra_amixer: amixer@290bb00 { 491 compatible = "nvidia,tegra234-amixer", 492 "nvidia,tegra210-amixer"; 493 reg = <0x0 0x290bb00 0x0 0x800>; 494 sound-name-prefix = "MIXER1"; 495 status = "disabled"; 496 }; 497 498 tegra_admaif: admaif@290f000 { 499 compatible = "nvidia,tegra234-admaif", 500 "nvidia,tegra186-admaif"; 501 reg = <0x0 0x0290f000 0x0 0x1000>; 502 dmas = <&adma 1>, <&adma 1>, 503 <&adma 2>, <&adma 2>, 504 <&adma 3>, <&adma 3>, 505 <&adma 4>, <&adma 4>, 506 <&adma 5>, <&adma 5>, 507 <&adma 6>, <&adma 6>, 508 <&adma 7>, <&adma 7>, 509 <&adma 8>, <&adma 8>, 510 <&adma 9>, <&adma 9>, 511 <&adma 10>, <&adma 10>, 512 <&adma 11>, <&adma 11>, 513 <&adma 12>, <&adma 12>, 514 <&adma 13>, <&adma 13>, 515 <&adma 14>, <&adma 14>, 516 <&adma 15>, <&adma 15>, 517 <&adma 16>, <&adma 16>, 518 <&adma 17>, <&adma 17>, 519 <&adma 18>, <&adma 18>, 520 <&adma 19>, <&adma 19>, 521 <&adma 20>, <&adma 20>; 522 dma-names = "rx1", "tx1", 523 "rx2", "tx2", 524 "rx3", "tx3", 525 "rx4", "tx4", 526 "rx5", "tx5", 527 "rx6", "tx6", 528 "rx7", "tx7", 529 "rx8", "tx8", 530 "rx9", "tx9", 531 "rx10", "tx10", 532 "rx11", "tx11", 533 "rx12", "tx12", 534 "rx13", "tx13", 535 "rx14", "tx14", 536 "rx15", "tx15", 537 "rx16", "tx16", 538 "rx17", "tx17", 539 "rx18", "tx18", 540 "rx19", "tx19", 541 "rx20", "tx20"; 542 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 543 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 544 interconnect-names = "dma-mem", "write"; 545 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 546 status = "disabled"; 547 }; 548 549 tegra_asrc: asrc@2910000 { 550 compatible = "nvidia,tegra234-asrc", 551 "nvidia,tegra186-asrc"; 552 reg = <0x0 0x2910000 0x0 0x2000>; 553 sound-name-prefix = "ASRC1"; 554 status = "disabled"; 555 }; 556 }; 557 558 adma: dma-controller@2930000 { 559 compatible = "nvidia,tegra234-adma", 560 "nvidia,tegra186-adma"; 561 reg = <0x0 0x02930000 0x0 0x20000>; 562 interrupt-parent = <&agic>; 563 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 595 #dma-cells = <1>; 596 clocks = <&bpmp TEGRA234_CLK_AHUB>; 597 clock-names = "d_audio"; 598 status = "disabled"; 599 }; 600 601 agic: interrupt-controller@2a40000 { 602 compatible = "nvidia,tegra234-agic", 603 "nvidia,tegra210-agic"; 604 #interrupt-cells = <3>; 605 interrupt-controller; 606 reg = <0x0 0x02a41000 0x0 0x1000>, 607 <0x0 0x02a42000 0x0 0x2000>; 608 interrupts = <GIC_SPI 145 609 (GIC_CPU_MASK_SIMPLE(4) | 610 IRQ_TYPE_LEVEL_HIGH)>; 611 clocks = <&bpmp TEGRA234_CLK_APE>; 612 clock-names = "clk"; 613 status = "disabled"; 614 }; 615 }; 616 617 mc: memory-controller@2c00000 { 618 compatible = "nvidia,tegra234-mc"; 619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 620 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 621 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 622 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 623 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 624 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 625 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 626 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 627 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 628 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 629 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 630 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 631 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 632 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 633 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 634 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 635 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 636 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 638 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 639 "ch11", "ch12", "ch13", "ch14", "ch15"; 640 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 641 #interconnect-cells = <1>; 642 status = "okay"; 643 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 647 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 648 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 649 650 /* 651 * Bit 39 of addresses passing through the memory 652 * controller selects the XBAR format used when memory 653 * is accessed. This is used to transparently access 654 * memory in the XBAR format used by the discrete GPU 655 * (bit 39 set) or Tegra (bit 39 clear). 656 * 657 * As a consequence, the operating system must ensure 658 * that bit 39 is never used implicitly, for example 659 * via an I/O virtual address mapping of an IOMMU. If 660 * devices require access to the XBAR switch, their 661 * drivers must set this bit explicitly. 662 * 663 * Limit the DMA range for memory clients to [38:0]. 664 */ 665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 666 667 emc: external-memory-controller@2c60000 { 668 compatible = "nvidia,tegra234-emc"; 669 reg = <0x0 0x02c60000 0x0 0x90000>, 670 <0x0 0x01780000 0x0 0x80000>; 671 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&bpmp TEGRA234_CLK_EMC>; 673 clock-names = "emc"; 674 status = "okay"; 675 676 #interconnect-cells = <0>; 677 678 nvidia,bpmp = <&bpmp>; 679 }; 680 }; 681 682 uarta: serial@3100000 { 683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 684 reg = <0x0 0x03100000 0x0 0x10000>; 685 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&bpmp TEGRA234_CLK_UARTA>; 687 resets = <&bpmp TEGRA234_RESET_UARTA>; 688 status = "disabled"; 689 }; 690 691 uarte: serial@3140000 { 692 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 693 reg = <0x0 0x03140000 0x0 0x10000>; 694 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&bpmp TEGRA234_CLK_UARTE>; 696 resets = <&bpmp TEGRA234_RESET_UARTE>; 697 status = "disabled"; 698 }; 699 700 gen1_i2c: i2c@3160000 { 701 compatible = "nvidia,tegra194-i2c"; 702 reg = <0x0 0x3160000 0x0 0x100>; 703 status = "disabled"; 704 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 clock-frequency = <400000>; 708 clocks = <&bpmp TEGRA234_CLK_I2C1 709 &bpmp TEGRA234_CLK_PLLP_OUT0>; 710 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 712 clock-names = "div-clk", "parent"; 713 resets = <&bpmp TEGRA234_RESET_I2C1>; 714 reset-names = "i2c"; 715 dmas = <&gpcdma 21>, <&gpcdma 21>; 716 dma-names = "rx", "tx"; 717 }; 718 719 cam_i2c: i2c@3180000 { 720 compatible = "nvidia,tegra194-i2c"; 721 reg = <0x0 0x3180000 0x0 0x100>; 722 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 clock-frequency = <400000>; 727 clocks = <&bpmp TEGRA234_CLK_I2C3 728 &bpmp TEGRA234_CLK_PLLP_OUT0>; 729 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 731 clock-names = "div-clk", "parent"; 732 resets = <&bpmp TEGRA234_RESET_I2C3>; 733 reset-names = "i2c"; 734 dmas = <&gpcdma 23>, <&gpcdma 23>; 735 dma-names = "rx", "tx"; 736 }; 737 738 dp_aux_ch1_i2c: i2c@3190000 { 739 compatible = "nvidia,tegra194-i2c"; 740 reg = <0x0 0x3190000 0x0 0x100>; 741 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 clock-frequency = <100000>; 746 clocks = <&bpmp TEGRA234_CLK_I2C4 747 &bpmp TEGRA234_CLK_PLLP_OUT0>; 748 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 749 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 750 clock-names = "div-clk", "parent"; 751 resets = <&bpmp TEGRA234_RESET_I2C4>; 752 reset-names = "i2c"; 753 dmas = <&gpcdma 26>, <&gpcdma 26>; 754 dma-names = "rx", "tx"; 755 }; 756 757 dp_aux_ch0_i2c: i2c@31b0000 { 758 compatible = "nvidia,tegra194-i2c"; 759 reg = <0x0 0x31b0000 0x0 0x100>; 760 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 clock-frequency = <100000>; 765 clocks = <&bpmp TEGRA234_CLK_I2C6 766 &bpmp TEGRA234_CLK_PLLP_OUT0>; 767 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 768 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 769 clock-names = "div-clk", "parent"; 770 resets = <&bpmp TEGRA234_RESET_I2C6>; 771 reset-names = "i2c"; 772 dmas = <&gpcdma 30>, <&gpcdma 30>; 773 dma-names = "rx", "tx"; 774 }; 775 776 dp_aux_ch2_i2c: i2c@31c0000 { 777 compatible = "nvidia,tegra194-i2c"; 778 reg = <0x0 0x31c0000 0x0 0x100>; 779 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 status = "disabled"; 783 clock-frequency = <100000>; 784 clocks = <&bpmp TEGRA234_CLK_I2C7 785 &bpmp TEGRA234_CLK_PLLP_OUT0>; 786 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 787 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 788 clock-names = "div-clk", "parent"; 789 resets = <&bpmp TEGRA234_RESET_I2C7>; 790 reset-names = "i2c"; 791 dmas = <&gpcdma 27>, <&gpcdma 27>; 792 dma-names = "rx", "tx"; 793 }; 794 795 uarti: serial@31d0000 { 796 compatible = "arm,sbsa-uart"; 797 reg = <0x0 0x31d0000 0x0 0x10000>; 798 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 799 status = "disabled"; 800 }; 801 802 dp_aux_ch3_i2c: i2c@31e0000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x0 0x31e0000 0x0 0x100>; 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 clock-frequency = <100000>; 810 clocks = <&bpmp TEGRA234_CLK_I2C9 811 &bpmp TEGRA234_CLK_PLLP_OUT0>; 812 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 814 clock-names = "div-clk", "parent"; 815 resets = <&bpmp TEGRA234_RESET_I2C9>; 816 reset-names = "i2c"; 817 dmas = <&gpcdma 31>, <&gpcdma 31>; 818 dma-names = "rx", "tx"; 819 }; 820 821 spi@3210000 { 822 compatible = "nvidia,tegra210-spi"; 823 reg = <0x0 0x03210000 0x0 0x1000>; 824 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 clocks = <&bpmp TEGRA234_CLK_SPI1>; 828 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; 829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 830 clock-names = "spi"; 831 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 832 resets = <&bpmp TEGRA234_RESET_SPI1>; 833 reset-names = "spi"; 834 dmas = <&gpcdma 15>, <&gpcdma 15>; 835 dma-names = "rx", "tx"; 836 dma-coherent; 837 status = "disabled"; 838 }; 839 840 spi@3230000 { 841 compatible = "nvidia,tegra210-spi"; 842 reg = <0x0 0x03230000 0x0 0x1000>; 843 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 clocks = <&bpmp TEGRA234_CLK_SPI3>; 847 clock-names = "spi"; 848 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 849 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; 850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 851 resets = <&bpmp TEGRA234_RESET_SPI3>; 852 reset-names = "spi"; 853 dmas = <&gpcdma 17>, <&gpcdma 17>; 854 dma-names = "rx", "tx"; 855 dma-coherent; 856 status = "disabled"; 857 }; 858 859 spi@3270000 { 860 compatible = "nvidia,tegra234-qspi"; 861 reg = <0x0 0x3270000 0x0 0x1000>; 862 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 866 <&bpmp TEGRA234_CLK_QSPI0_PM>; 867 clock-names = "qspi", "qspi_out"; 868 resets = <&bpmp TEGRA234_RESET_QSPI0>; 869 status = "disabled"; 870 }; 871 872 pwm1: pwm@3280000 { 873 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 874 reg = <0x0 0x3280000 0x0 0x10000>; 875 clocks = <&bpmp TEGRA234_CLK_PWM1>; 876 resets = <&bpmp TEGRA234_RESET_PWM1>; 877 reset-names = "pwm"; 878 status = "disabled"; 879 #pwm-cells = <2>; 880 }; 881 882 pwm2: pwm@3290000 { 883 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 884 reg = <0x0 0x3290000 0x0 0x10000>; 885 clocks = <&bpmp TEGRA234_CLK_PWM2>; 886 resets = <&bpmp TEGRA234_RESET_PWM2>; 887 reset-names = "pwm"; 888 status = "disabled"; 889 #pwm-cells = <2>; 890 }; 891 892 pwm3: pwm@32a0000 { 893 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 894 reg = <0x0 0x32a0000 0x0 0x10000>; 895 clocks = <&bpmp TEGRA234_CLK_PWM3>; 896 resets = <&bpmp TEGRA234_RESET_PWM3>; 897 reset-names = "pwm"; 898 status = "disabled"; 899 #pwm-cells = <2>; 900 }; 901 902 pwm5: pwm@32c0000 { 903 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 904 reg = <0x0 0x32c0000 0x0 0x10000>; 905 clocks = <&bpmp TEGRA234_CLK_PWM5>; 906 resets = <&bpmp TEGRA234_RESET_PWM5>; 907 reset-names = "pwm"; 908 status = "disabled"; 909 #pwm-cells = <2>; 910 }; 911 912 pwm6: pwm@32d0000 { 913 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 914 reg = <0x0 0x32d0000 0x0 0x10000>; 915 clocks = <&bpmp TEGRA234_CLK_PWM6>; 916 resets = <&bpmp TEGRA234_RESET_PWM6>; 917 reset-names = "pwm"; 918 status = "disabled"; 919 #pwm-cells = <2>; 920 }; 921 922 pwm7: pwm@32e0000 { 923 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 924 reg = <0x0 0x32e0000 0x0 0x10000>; 925 clocks = <&bpmp TEGRA234_CLK_PWM7>; 926 resets = <&bpmp TEGRA234_RESET_PWM7>; 927 reset-names = "pwm"; 928 status = "disabled"; 929 #pwm-cells = <2>; 930 }; 931 932 pwm8: pwm@32f0000 { 933 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 934 reg = <0x0 0x32f0000 0x0 0x10000>; 935 clocks = <&bpmp TEGRA234_CLK_PWM8>; 936 resets = <&bpmp TEGRA234_RESET_PWM8>; 937 reset-names = "pwm"; 938 status = "disabled"; 939 #pwm-cells = <2>; 940 }; 941 942 spi@3300000 { 943 compatible = "nvidia,tegra234-qspi"; 944 reg = <0x0 0x3300000 0x0 0x1000>; 945 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 949 <&bpmp TEGRA234_CLK_QSPI1_PM>; 950 clock-names = "qspi", "qspi_out"; 951 resets = <&bpmp TEGRA234_RESET_QSPI1>; 952 status = "disabled"; 953 }; 954 955 mmc@3400000 { 956 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 957 reg = <0x0 0x03400000 0x0 0x20000>; 958 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 960 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 961 clock-names = "sdhci", "tmclk"; 962 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 963 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 964 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 965 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 966 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 967 reset-names = "sdhci"; 968 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 969 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 970 interconnect-names = "dma-mem", "write"; 971 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 972 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 973 pinctrl-0 = <&sdmmc1_3v3>; 974 pinctrl-1 = <&sdmmc1_1v8>; 975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 977 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 978 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 979 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 980 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 981 nvidia,default-tap = <14>; 982 nvidia,default-trim = <0x8>; 983 sd-uhs-sdr25; 984 sd-uhs-sdr50; 985 sd-uhs-ddr50; 986 sd-uhs-sdr104; 987 status = "disabled"; 988 }; 989 990 mmc@3460000 { 991 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 992 reg = <0x0 0x03460000 0x0 0x20000>; 993 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 995 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 996 clock-names = "sdhci", "tmclk"; 997 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 998 <&bpmp TEGRA234_CLK_PLLC4>; 999 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 1000 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 1001 reset-names = "sdhci"; 1002 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 1003 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 1004 interconnect-names = "dma-mem", "write"; 1005 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 1006 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1007 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1008 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1009 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 1010 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1011 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 1012 nvidia,default-tap = <0x8>; 1013 nvidia,default-trim = <0x14>; 1014 nvidia,dqs-trim = <40>; 1015 supports-cqe; 1016 status = "disabled"; 1017 }; 1018 1019 hda@3510000 { 1020 compatible = "nvidia,tegra234-hda"; 1021 reg = <0x0 0x3510000 0x0 0x10000>; 1022 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 1024 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 1025 clock-names = "hda", "hda2codec_2x"; 1026 resets = <&bpmp TEGRA234_RESET_HDA>, 1027 <&bpmp TEGRA234_RESET_HDACODEC>; 1028 reset-names = "hda", "hda2codec_2x"; 1029 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 1030 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 1031 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 1032 interconnect-names = "dma-mem", "write"; 1033 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 1034 status = "disabled"; 1035 }; 1036 1037 xusb_padctl: padctl@3520000 { 1038 compatible = "nvidia,tegra234-xusb-padctl"; 1039 reg = <0x0 0x03520000 0x0 0x20000>, 1040 <0x0 0x03540000 0x0 0x10000>; 1041 reg-names = "padctl", "ao"; 1042 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1043 1044 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 1045 reset-names = "padctl"; 1046 1047 status = "disabled"; 1048 1049 pads { 1050 usb2 { 1051 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 1052 clock-names = "trk"; 1053 1054 lanes { 1055 usb2-0 { 1056 nvidia,function = "xusb"; 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 }; 1060 1061 usb2-1 { 1062 nvidia,function = "xusb"; 1063 status = "disabled"; 1064 #phy-cells = <0>; 1065 }; 1066 1067 usb2-2 { 1068 nvidia,function = "xusb"; 1069 status = "disabled"; 1070 #phy-cells = <0>; 1071 }; 1072 1073 usb2-3 { 1074 nvidia,function = "xusb"; 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 }; 1079 }; 1080 1081 usb3 { 1082 lanes { 1083 usb3-0 { 1084 nvidia,function = "xusb"; 1085 status = "disabled"; 1086 #phy-cells = <0>; 1087 }; 1088 1089 usb3-1 { 1090 nvidia,function = "xusb"; 1091 status = "disabled"; 1092 #phy-cells = <0>; 1093 }; 1094 1095 usb3-2 { 1096 nvidia,function = "xusb"; 1097 status = "disabled"; 1098 #phy-cells = <0>; 1099 }; 1100 1101 usb3-3 { 1102 nvidia,function = "xusb"; 1103 status = "disabled"; 1104 #phy-cells = <0>; 1105 }; 1106 }; 1107 }; 1108 }; 1109 1110 ports { 1111 usb2-0 { 1112 status = "disabled"; 1113 }; 1114 1115 usb2-1 { 1116 status = "disabled"; 1117 }; 1118 1119 usb2-2 { 1120 status = "disabled"; 1121 }; 1122 1123 usb2-3 { 1124 status = "disabled"; 1125 }; 1126 1127 usb3-0 { 1128 status = "disabled"; 1129 }; 1130 1131 usb3-1 { 1132 status = "disabled"; 1133 }; 1134 1135 usb3-2 { 1136 status = "disabled"; 1137 }; 1138 1139 usb3-3 { 1140 status = "disabled"; 1141 }; 1142 }; 1143 }; 1144 1145 usb@3550000 { 1146 compatible = "nvidia,tegra234-xudc"; 1147 reg = <0x0 0x03550000 0x0 0x8000>, 1148 <0x0 0x03558000 0x0 0x8000>; 1149 reg-names = "base", "fpci"; 1150 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1152 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1153 <&bpmp TEGRA234_CLK_XUSB_SS>, 1154 <&bpmp TEGRA234_CLK_XUSB_FS>; 1155 clock-names = "dev", "ss", "ss_src", "fs_src"; 1156 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1157 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1158 interconnect-names = "dma-mem", "write"; 1159 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1160 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1161 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1162 power-domain-names = "dev", "ss"; 1163 nvidia,xusb-padctl = <&xusb_padctl>; 1164 dma-coherent; 1165 status = "disabled"; 1166 }; 1167 1168 usb@3610000 { 1169 compatible = "nvidia,tegra234-xusb"; 1170 reg = <0x0 0x03610000 0x0 0x40000>, 1171 <0x0 0x03600000 0x0 0x10000>, 1172 <0x0 0x03650000 0x0 0x10000>; 1173 reg-names = "hcd", "fpci", "bar2"; 1174 1175 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1177 1178 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1179 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1180 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1181 <&bpmp TEGRA234_CLK_XUSB_SS>, 1182 <&bpmp TEGRA234_CLK_CLK_M>, 1183 <&bpmp TEGRA234_CLK_XUSB_FS>, 1184 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1185 <&bpmp TEGRA234_CLK_CLK_M>, 1186 <&bpmp TEGRA234_CLK_PLLE>; 1187 clock-names = "xusb_host", "xusb_falcon_src", 1188 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1189 "xusb_fs_src", "pll_u_480m", "clk_m", 1190 "pll_e"; 1191 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1192 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1193 interconnect-names = "dma-mem", "write"; 1194 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1195 1196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1197 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1198 power-domain-names = "xusb_host", "xusb_ss"; 1199 1200 nvidia,xusb-padctl = <&xusb_padctl>; 1201 dma-coherent; 1202 status = "disabled"; 1203 }; 1204 1205 fuse@3810000 { 1206 compatible = "nvidia,tegra234-efuse"; 1207 reg = <0x0 0x03810000 0x0 0x10000>; 1208 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1209 clock-names = "fuse"; 1210 }; 1211 1212 hte_lic: hardware-timestamp@3aa0000 { 1213 compatible = "nvidia,tegra234-gte-lic"; 1214 reg = <0x0 0x3aa0000 0x0 0x10000>; 1215 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1216 nvidia,int-threshold = <1>; 1217 #timestamp-cells = <1>; 1218 }; 1219 1220 hsp_top0: hsp@3c00000 { 1221 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1222 reg = <0x0 0x03c00000 0x0 0xa0000>; 1223 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1232 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1233 "shared3", "shared4", "shared5", "shared6", 1234 "shared7"; 1235 #mbox-cells = <2>; 1236 }; 1237 1238 p2u_hsio_0: phy@3e00000 { 1239 compatible = "nvidia,tegra234-p2u"; 1240 reg = <0x0 0x03e00000 0x0 0x10000>; 1241 reg-names = "ctl"; 1242 1243 #phy-cells = <0>; 1244 }; 1245 1246 p2u_hsio_1: phy@3e10000 { 1247 compatible = "nvidia,tegra234-p2u"; 1248 reg = <0x0 0x03e10000 0x0 0x10000>; 1249 reg-names = "ctl"; 1250 1251 #phy-cells = <0>; 1252 }; 1253 1254 p2u_hsio_2: phy@3e20000 { 1255 compatible = "nvidia,tegra234-p2u"; 1256 reg = <0x0 0x03e20000 0x0 0x10000>; 1257 reg-names = "ctl"; 1258 1259 #phy-cells = <0>; 1260 }; 1261 1262 p2u_hsio_3: phy@3e30000 { 1263 compatible = "nvidia,tegra234-p2u"; 1264 reg = <0x0 0x03e30000 0x0 0x10000>; 1265 reg-names = "ctl"; 1266 1267 #phy-cells = <0>; 1268 }; 1269 1270 p2u_hsio_4: phy@3e40000 { 1271 compatible = "nvidia,tegra234-p2u"; 1272 reg = <0x0 0x03e40000 0x0 0x10000>; 1273 reg-names = "ctl"; 1274 1275 #phy-cells = <0>; 1276 }; 1277 1278 p2u_hsio_5: phy@3e50000 { 1279 compatible = "nvidia,tegra234-p2u"; 1280 reg = <0x0 0x03e50000 0x0 0x10000>; 1281 reg-names = "ctl"; 1282 1283 #phy-cells = <0>; 1284 }; 1285 1286 p2u_hsio_6: phy@3e60000 { 1287 compatible = "nvidia,tegra234-p2u"; 1288 reg = <0x0 0x03e60000 0x0 0x10000>; 1289 reg-names = "ctl"; 1290 1291 #phy-cells = <0>; 1292 }; 1293 1294 p2u_hsio_7: phy@3e70000 { 1295 compatible = "nvidia,tegra234-p2u"; 1296 reg = <0x0 0x03e70000 0x0 0x10000>; 1297 reg-names = "ctl"; 1298 1299 #phy-cells = <0>; 1300 }; 1301 1302 p2u_nvhs_0: phy@3e90000 { 1303 compatible = "nvidia,tegra234-p2u"; 1304 reg = <0x0 0x03e90000 0x0 0x10000>; 1305 reg-names = "ctl"; 1306 1307 #phy-cells = <0>; 1308 }; 1309 1310 p2u_nvhs_1: phy@3ea0000 { 1311 compatible = "nvidia,tegra234-p2u"; 1312 reg = <0x0 0x03ea0000 0x0 0x10000>; 1313 reg-names = "ctl"; 1314 1315 #phy-cells = <0>; 1316 }; 1317 1318 p2u_nvhs_2: phy@3eb0000 { 1319 compatible = "nvidia,tegra234-p2u"; 1320 reg = <0x0 0x03eb0000 0x0 0x10000>; 1321 reg-names = "ctl"; 1322 1323 #phy-cells = <0>; 1324 }; 1325 1326 p2u_nvhs_3: phy@3ec0000 { 1327 compatible = "nvidia,tegra234-p2u"; 1328 reg = <0x0 0x03ec0000 0x0 0x10000>; 1329 reg-names = "ctl"; 1330 1331 #phy-cells = <0>; 1332 }; 1333 1334 p2u_nvhs_4: phy@3ed0000 { 1335 compatible = "nvidia,tegra234-p2u"; 1336 reg = <0x0 0x03ed0000 0x0 0x10000>; 1337 reg-names = "ctl"; 1338 1339 #phy-cells = <0>; 1340 }; 1341 1342 p2u_nvhs_5: phy@3ee0000 { 1343 compatible = "nvidia,tegra234-p2u"; 1344 reg = <0x0 0x03ee0000 0x0 0x10000>; 1345 reg-names = "ctl"; 1346 1347 #phy-cells = <0>; 1348 }; 1349 1350 p2u_nvhs_6: phy@3ef0000 { 1351 compatible = "nvidia,tegra234-p2u"; 1352 reg = <0x0 0x03ef0000 0x0 0x10000>; 1353 reg-names = "ctl"; 1354 1355 #phy-cells = <0>; 1356 }; 1357 1358 p2u_nvhs_7: phy@3f00000 { 1359 compatible = "nvidia,tegra234-p2u"; 1360 reg = <0x0 0x03f00000 0x0 0x10000>; 1361 reg-names = "ctl"; 1362 1363 #phy-cells = <0>; 1364 }; 1365 1366 p2u_gbe_0: phy@3f20000 { 1367 compatible = "nvidia,tegra234-p2u"; 1368 reg = <0x0 0x03f20000 0x0 0x10000>; 1369 reg-names = "ctl"; 1370 1371 #phy-cells = <0>; 1372 }; 1373 1374 p2u_gbe_1: phy@3f30000 { 1375 compatible = "nvidia,tegra234-p2u"; 1376 reg = <0x0 0x03f30000 0x0 0x10000>; 1377 reg-names = "ctl"; 1378 1379 #phy-cells = <0>; 1380 }; 1381 1382 p2u_gbe_2: phy@3f40000 { 1383 compatible = "nvidia,tegra234-p2u"; 1384 reg = <0x0 0x03f40000 0x0 0x10000>; 1385 reg-names = "ctl"; 1386 1387 #phy-cells = <0>; 1388 }; 1389 1390 p2u_gbe_3: phy@3f50000 { 1391 compatible = "nvidia,tegra234-p2u"; 1392 reg = <0x0 0x03f50000 0x0 0x10000>; 1393 reg-names = "ctl"; 1394 1395 #phy-cells = <0>; 1396 }; 1397 1398 p2u_gbe_4: phy@3f60000 { 1399 compatible = "nvidia,tegra234-p2u"; 1400 reg = <0x0 0x03f60000 0x0 0x10000>; 1401 reg-names = "ctl"; 1402 1403 #phy-cells = <0>; 1404 }; 1405 1406 p2u_gbe_5: phy@3f70000 { 1407 compatible = "nvidia,tegra234-p2u"; 1408 reg = <0x0 0x03f70000 0x0 0x10000>; 1409 reg-names = "ctl"; 1410 1411 #phy-cells = <0>; 1412 }; 1413 1414 p2u_gbe_6: phy@3f80000 { 1415 compatible = "nvidia,tegra234-p2u"; 1416 reg = <0x0 0x03f80000 0x0 0x10000>; 1417 reg-names = "ctl"; 1418 1419 #phy-cells = <0>; 1420 }; 1421 1422 p2u_gbe_7: phy@3f90000 { 1423 compatible = "nvidia,tegra234-p2u"; 1424 reg = <0x0 0x03f90000 0x0 0x10000>; 1425 reg-names = "ctl"; 1426 1427 #phy-cells = <0>; 1428 }; 1429 1430 ethernet@6800000 { 1431 compatible = "nvidia,tegra234-mgbe"; 1432 reg = <0x0 0x06800000 0x0 0x10000>, 1433 <0x0 0x06810000 0x0 0x10000>, 1434 <0x0 0x068a0000 0x0 0x10000>; 1435 reg-names = "hypervisor", "mac", "xpcs"; 1436 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1437 interrupt-names = "common"; 1438 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1439 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1440 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1441 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1442 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1443 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1444 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1445 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1446 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1447 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1448 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1449 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1450 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1451 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1452 "rx-pcs", "tx-pcs"; 1453 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1454 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1455 reset-names = "mac", "pcs"; 1456 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1457 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1458 interconnect-names = "dma-mem", "write"; 1459 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1460 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1461 status = "disabled"; 1462 }; 1463 1464 ethernet@6900000 { 1465 compatible = "nvidia,tegra234-mgbe"; 1466 reg = <0x0 0x06900000 0x0 0x10000>, 1467 <0x0 0x06910000 0x0 0x10000>, 1468 <0x0 0x069a0000 0x0 0x10000>; 1469 reg-names = "hypervisor", "mac", "xpcs"; 1470 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1471 interrupt-names = "common"; 1472 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1473 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1474 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1475 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1476 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1477 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1478 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1479 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1480 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1481 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1482 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1483 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1484 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1485 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1486 "rx-pcs", "tx-pcs"; 1487 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1488 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1489 reset-names = "mac", "pcs"; 1490 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1491 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1492 interconnect-names = "dma-mem", "write"; 1493 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1494 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1495 status = "disabled"; 1496 }; 1497 1498 ethernet@6a00000 { 1499 compatible = "nvidia,tegra234-mgbe"; 1500 reg = <0x0 0x06a00000 0x0 0x10000>, 1501 <0x0 0x06a10000 0x0 0x10000>, 1502 <0x0 0x06aa0000 0x0 0x10000>; 1503 reg-names = "hypervisor", "mac", "xpcs"; 1504 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1505 interrupt-names = "common"; 1506 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1507 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1508 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1509 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1510 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1511 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1512 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1513 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1514 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1515 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1516 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1517 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1518 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1519 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1520 "rx-pcs", "tx-pcs"; 1521 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1522 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1523 reset-names = "mac", "pcs"; 1524 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1525 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1526 interconnect-names = "dma-mem", "write"; 1527 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1528 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1529 status = "disabled"; 1530 }; 1531 1532 ethernet@6b00000 { 1533 compatible = "nvidia,tegra234-mgbe"; 1534 reg = <0x0 0x06b00000 0x0 0x10000>, 1535 <0x0 0x06b10000 0x0 0x10000>, 1536 <0x0 0x06ba0000 0x0 0x10000>; 1537 reg-names = "hypervisor", "mac", "xpcs"; 1538 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1539 interrupt-names = "common"; 1540 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1541 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1542 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1543 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1544 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1545 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1546 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1547 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1548 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1549 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1550 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1551 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1552 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1553 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1554 "rx-pcs", "tx-pcs"; 1555 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1556 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1557 reset-names = "mac", "pcs"; 1558 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1559 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1560 interconnect-names = "dma-mem", "write"; 1561 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1562 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1563 status = "disabled"; 1564 }; 1565 1566 smmu_niso1: iommu@8000000 { 1567 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1568 reg = <0x0 0x8000000 0x0 0x1000000>, 1569 <0x0 0x7000000 0x0 0x1000000>; 1570 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1700 stream-match-mask = <0x7f80>; 1701 #global-interrupts = <2>; 1702 #iommu-cells = <1>; 1703 1704 nvidia,memory-controller = <&mc>; 1705 status = "okay"; 1706 }; 1707 1708 sce-fabric@b600000 { 1709 compatible = "nvidia,tegra234-sce-fabric"; 1710 reg = <0x0 0xb600000 0x0 0x40000>; 1711 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1712 status = "disabled"; 1713 }; 1714 1715 rce-fabric@be00000 { 1716 compatible = "nvidia,tegra234-rce-fabric"; 1717 reg = <0x0 0xbe00000 0x0 0x40000>; 1718 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1719 status = "okay"; 1720 }; 1721 1722 hsp_aon: hsp@c150000 { 1723 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1724 reg = <0x0 0x0c150000 0x0 0x90000>; 1725 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1729 /* 1730 * Shared interrupt 0 is routed only to AON/SPE, so 1731 * we only have 4 shared interrupts for the CCPLEX. 1732 */ 1733 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1734 #mbox-cells = <2>; 1735 }; 1736 1737 hte_aon: hardware-timestamp@c1e0000 { 1738 compatible = "nvidia,tegra234-gte-aon"; 1739 reg = <0x0 0xc1e0000 0x0 0x10000>; 1740 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1741 nvidia,int-threshold = <1>; 1742 nvidia,gpio-controller = <&gpio_aon>; 1743 #timestamp-cells = <1>; 1744 }; 1745 1746 gen2_i2c: i2c@c240000 { 1747 compatible = "nvidia,tegra194-i2c"; 1748 reg = <0x0 0xc240000 0x0 0x100>; 1749 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 clock-frequency = <100000>; 1754 clocks = <&bpmp TEGRA234_CLK_I2C2 1755 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1756 clock-names = "div-clk", "parent"; 1757 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1758 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1759 resets = <&bpmp TEGRA234_RESET_I2C2>; 1760 reset-names = "i2c"; 1761 dmas = <&gpcdma 22>, <&gpcdma 22>; 1762 dma-names = "rx", "tx"; 1763 }; 1764 1765 gen8_i2c: i2c@c250000 { 1766 compatible = "nvidia,tegra194-i2c"; 1767 reg = <0x0 0xc250000 0x0 0x100>; 1768 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 status = "disabled"; 1772 clock-frequency = <400000>; 1773 clocks = <&bpmp TEGRA234_CLK_I2C8 1774 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1775 clock-names = "div-clk", "parent"; 1776 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1777 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1778 resets = <&bpmp TEGRA234_RESET_I2C8>; 1779 reset-names = "i2c"; 1780 dmas = <&gpcdma 0>, <&gpcdma 0>; 1781 dma-names = "rx", "tx"; 1782 }; 1783 1784 spi@c260000 { 1785 compatible = "nvidia,tegra210-spi"; 1786 reg = <0x0 0x0c260000 0x0 0x1000>; 1787 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1788 #address-cells = <1>; 1789 #size-cells = <0>; 1790 clocks = <&bpmp TEGRA234_CLK_SPI2>; 1791 clock-names = "spi"; 1792 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 1793 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; 1794 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1795 resets = <&bpmp TEGRA234_RESET_SPI2>; 1796 reset-names = "spi"; 1797 dmas = <&gpcdma 16>, <&gpcdma 16>; 1798 dma-names = "rx", "tx"; 1799 dma-coherent; 1800 status = "disabled"; 1801 }; 1802 1803 rtc@c2a0000 { 1804 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1805 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1806 interrupt-parent = <&pmc>; 1807 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1808 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1809 clock-names = "rtc"; 1810 status = "disabled"; 1811 }; 1812 1813 gpio_aon: gpio@c2f0000 { 1814 compatible = "nvidia,tegra234-gpio-aon"; 1815 reg-names = "security", "gpio"; 1816 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1817 <0x0 0x0c2f1000 0x0 0x1000>; 1818 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1822 #interrupt-cells = <2>; 1823 interrupt-controller; 1824 #gpio-cells = <2>; 1825 gpio-controller; 1826 gpio-ranges = <&pinmux_aon 0 0 32>; 1827 }; 1828 1829 pinmux_aon: pinmux@c300000 { 1830 compatible = "nvidia,tegra234-pinmux-aon"; 1831 reg = <0x0 0xc300000 0x0 0x4000>; 1832 }; 1833 1834 pwm4: pwm@c340000 { 1835 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1836 reg = <0x0 0xc340000 0x0 0x10000>; 1837 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1838 resets = <&bpmp TEGRA234_RESET_PWM4>; 1839 reset-names = "pwm"; 1840 status = "disabled"; 1841 #pwm-cells = <2>; 1842 }; 1843 1844 pmc: pmc@c360000 { 1845 compatible = "nvidia,tegra234-pmc"; 1846 reg = <0x0 0x0c360000 0x0 0x10000>, 1847 <0x0 0x0c370000 0x0 0x10000>, 1848 <0x0 0x0c380000 0x0 0x10000>, 1849 <0x0 0x0c390000 0x0 0x10000>, 1850 <0x0 0x0c3a0000 0x0 0x10000>; 1851 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1852 1853 #interrupt-cells = <2>; 1854 interrupt-controller; 1855 1856 sdmmc1_1v8: sdmmc1-1v8 { 1857 pins = "sdmmc1-hv"; 1858 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1859 }; 1860 1861 sdmmc1_3v3: sdmmc1-3v3 { 1862 pins = "sdmmc1-hv"; 1863 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1864 }; 1865 1866 sdmmc3_1v8: sdmmc3-1v8 { 1867 pins = "sdmmc3-hv"; 1868 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1869 }; 1870 1871 sdmmc3_3v3: sdmmc3-3v3 { 1872 pins = "sdmmc3-hv"; 1873 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1874 }; 1875 }; 1876 1877 aon-fabric@c600000 { 1878 compatible = "nvidia,tegra234-aon-fabric"; 1879 reg = <0x0 0xc600000 0x0 0x40000>; 1880 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1881 status = "okay"; 1882 }; 1883 1884 bpmp-fabric@d600000 { 1885 compatible = "nvidia,tegra234-bpmp-fabric"; 1886 reg = <0x0 0xd600000 0x0 0x40000>; 1887 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1888 status = "okay"; 1889 }; 1890 1891 dce-fabric@de00000 { 1892 compatible = "nvidia,tegra234-dce-fabric"; 1893 reg = <0x0 0xde00000 0x0 0x40000>; 1894 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1895 status = "okay"; 1896 }; 1897 1898 ccplex@e000000 { 1899 compatible = "nvidia,tegra234-ccplex-cluster"; 1900 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1901 nvidia,bpmp = <&bpmp>; 1902 status = "okay"; 1903 }; 1904 1905 gic: interrupt-controller@f400000 { 1906 compatible = "arm,gic-v3"; 1907 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1908 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1909 interrupt-parent = <&gic>; 1910 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1911 1912 #redistributor-regions = <1>; 1913 #interrupt-cells = <3>; 1914 interrupt-controller; 1915 1916 #address-cells = <0>; 1917 }; 1918 1919 smmu_iso: iommu@10000000 { 1920 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1921 reg = <0x0 0x10000000 0x0 0x1000000>; 1922 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 2051 stream-match-mask = <0x7f80>; 2052 #global-interrupts = <1>; 2053 #iommu-cells = <1>; 2054 2055 nvidia,memory-controller = <&mc>; 2056 status = "okay"; 2057 }; 2058 2059 smmu_niso0: iommu@12000000 { 2060 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 2061 reg = <0x0 0x12000000 0x0 0x1000000>, 2062 <0x0 0x11000000 0x0 0x1000000>; 2063 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2193 stream-match-mask = <0x7f80>; 2194 #global-interrupts = <2>; 2195 #iommu-cells = <1>; 2196 2197 nvidia,memory-controller = <&mc>; 2198 status = "okay"; 2199 }; 2200 2201 cbb-fabric@13a00000 { 2202 compatible = "nvidia,tegra234-cbb-fabric"; 2203 reg = <0x0 0x13a00000 0x0 0x400000>; 2204 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2205 status = "okay"; 2206 }; 2207 2208 host1x@13e00000 { 2209 compatible = "nvidia,tegra234-host1x"; 2210 reg = <0x0 0x13e00000 0x0 0x10000>, 2211 <0x0 0x13e10000 0x0 0x10000>, 2212 <0x0 0x13e40000 0x0 0x10000>; 2213 reg-names = "common", "hypervisor", "vm"; 2214 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2223 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2224 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2225 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2226 clock-names = "host1x"; 2227 2228 #address-cells = <2>; 2229 #size-cells = <2>; 2230 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2231 2232 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2233 interconnect-names = "dma-mem"; 2234 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2235 dma-coherent; 2236 2237 /* Context isolation domains */ 2238 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2239 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2240 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2241 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2242 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2243 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2244 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2245 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2246 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2247 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2248 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2249 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2250 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2251 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2252 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2253 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2254 2255 vic@15340000 { 2256 compatible = "nvidia,tegra234-vic"; 2257 reg = <0x0 0x15340000 0x0 0x00040000>; 2258 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2259 clocks = <&bpmp TEGRA234_CLK_VIC>; 2260 clock-names = "vic"; 2261 resets = <&bpmp TEGRA234_RESET_VIC>; 2262 reset-names = "vic"; 2263 2264 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2265 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2266 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2267 interconnect-names = "dma-mem", "write"; 2268 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2269 dma-coherent; 2270 }; 2271 2272 nvdec@15480000 { 2273 compatible = "nvidia,tegra234-nvdec"; 2274 reg = <0x0 0x15480000 0x0 0x00040000>; 2275 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2276 <&bpmp TEGRA234_CLK_FUSE>, 2277 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2278 clock-names = "nvdec", "fuse", "tsec_pka"; 2279 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2280 reset-names = "nvdec"; 2281 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2282 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2283 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2284 interconnect-names = "dma-mem", "write"; 2285 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2286 dma-coherent; 2287 2288 nvidia,memory-controller = <&mc>; 2289 2290 /* 2291 * Placeholder values that firmware needs to update with the real 2292 * offsets parsed from the microcode headers. 2293 */ 2294 nvidia,bl-manifest-offset = <0>; 2295 nvidia,bl-data-offset = <0>; 2296 nvidia,bl-code-offset = <0>; 2297 nvidia,os-manifest-offset = <0>; 2298 nvidia,os-data-offset = <0>; 2299 nvidia,os-code-offset = <0>; 2300 2301 /* 2302 * Firmware needs to set this to "okay" once the above values have 2303 * been updated. 2304 */ 2305 status = "disabled"; 2306 }; 2307 }; 2308 2309 pcie@140a0000 { 2310 compatible = "nvidia,tegra234-pcie"; 2311 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2312 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2313 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2314 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2315 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2316 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2317 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2318 2319 #address-cells = <3>; 2320 #size-cells = <2>; 2321 device_type = "pci"; 2322 num-lanes = <4>; 2323 num-viewport = <8>; 2324 linux,pci-domain = <8>; 2325 2326 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2327 clock-names = "core"; 2328 2329 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2330 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2331 reset-names = "apb", "core"; 2332 2333 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2334 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2335 interrupt-names = "intr", "msi"; 2336 2337 #interrupt-cells = <1>; 2338 interrupt-map-mask = <0 0 0 0>; 2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2340 2341 nvidia,bpmp = <&bpmp 8>; 2342 2343 nvidia,aspm-cmrt-us = <60>; 2344 nvidia,aspm-pwr-on-t-us = <20>; 2345 nvidia,aspm-l0s-entrance-latency-us = <3>; 2346 2347 bus-range = <0x0 0xff>; 2348 2349 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2350 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2351 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2352 2353 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2354 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2355 interconnect-names = "dma-mem", "write"; 2356 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2357 iommu-map-mask = <0x0>; 2358 dma-coherent; 2359 2360 status = "disabled"; 2361 }; 2362 2363 pcie@140c0000 { 2364 compatible = "nvidia,tegra234-pcie"; 2365 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2366 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2367 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2368 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2369 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2370 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2371 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2372 2373 #address-cells = <3>; 2374 #size-cells = <2>; 2375 device_type = "pci"; 2376 num-lanes = <4>; 2377 num-viewport = <8>; 2378 linux,pci-domain = <9>; 2379 2380 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2381 clock-names = "core"; 2382 2383 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2384 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2385 reset-names = "apb", "core"; 2386 2387 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2388 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2389 interrupt-names = "intr", "msi"; 2390 2391 #interrupt-cells = <1>; 2392 interrupt-map-mask = <0 0 0 0>; 2393 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2394 2395 nvidia,bpmp = <&bpmp 9>; 2396 2397 nvidia,aspm-cmrt-us = <60>; 2398 nvidia,aspm-pwr-on-t-us = <20>; 2399 nvidia,aspm-l0s-entrance-latency-us = <3>; 2400 2401 bus-range = <0x0 0xff>; 2402 2403 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2404 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2405 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2406 2407 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2408 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2409 interconnect-names = "dma-mem", "write"; 2410 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2411 iommu-map-mask = <0x0>; 2412 dma-coherent; 2413 2414 status = "disabled"; 2415 }; 2416 2417 pcie@140e0000 { 2418 compatible = "nvidia,tegra234-pcie"; 2419 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2420 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2421 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2422 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2423 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2424 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2425 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2426 2427 #address-cells = <3>; 2428 #size-cells = <2>; 2429 device_type = "pci"; 2430 num-lanes = <4>; 2431 num-viewport = <8>; 2432 linux,pci-domain = <10>; 2433 2434 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2435 clock-names = "core"; 2436 2437 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2438 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2439 reset-names = "apb", "core"; 2440 2441 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2442 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2443 interrupt-names = "intr", "msi"; 2444 2445 #interrupt-cells = <1>; 2446 interrupt-map-mask = <0 0 0 0>; 2447 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2448 2449 nvidia,bpmp = <&bpmp 10>; 2450 2451 nvidia,aspm-cmrt-us = <60>; 2452 nvidia,aspm-pwr-on-t-us = <20>; 2453 nvidia,aspm-l0s-entrance-latency-us = <3>; 2454 2455 bus-range = <0x0 0xff>; 2456 2457 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2458 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2459 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2460 2461 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2462 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2463 interconnect-names = "dma-mem", "write"; 2464 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2465 iommu-map-mask = <0x0>; 2466 dma-coherent; 2467 2468 status = "disabled"; 2469 }; 2470 2471 pcie-ep@140e0000 { 2472 compatible = "nvidia,tegra234-pcie-ep"; 2473 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2474 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2475 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2476 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2477 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2478 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2479 2480 num-lanes = <4>; 2481 2482 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2483 clock-names = "core"; 2484 2485 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2486 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2487 reset-names = "apb", "core"; 2488 2489 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2490 interrupt-names = "intr"; 2491 2492 nvidia,bpmp = <&bpmp 10>; 2493 2494 nvidia,enable-ext-refclk; 2495 nvidia,aspm-cmrt-us = <60>; 2496 nvidia,aspm-pwr-on-t-us = <20>; 2497 nvidia,aspm-l0s-entrance-latency-us = <3>; 2498 2499 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2500 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2501 interconnect-names = "dma-mem", "write"; 2502 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2503 iommu-map-mask = <0x0>; 2504 dma-coherent; 2505 2506 status = "disabled"; 2507 }; 2508 2509 pcie@14100000 { 2510 compatible = "nvidia,tegra234-pcie"; 2511 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2512 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2513 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2514 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2515 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2516 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2517 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2518 2519 #address-cells = <3>; 2520 #size-cells = <2>; 2521 device_type = "pci"; 2522 num-lanes = <1>; 2523 num-viewport = <8>; 2524 linux,pci-domain = <1>; 2525 2526 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2527 clock-names = "core"; 2528 2529 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2530 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2531 reset-names = "apb", "core"; 2532 2533 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2534 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2535 interrupt-names = "intr", "msi"; 2536 2537 #interrupt-cells = <1>; 2538 interrupt-map-mask = <0 0 0 0>; 2539 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2540 2541 nvidia,bpmp = <&bpmp 1>; 2542 2543 nvidia,aspm-cmrt-us = <60>; 2544 nvidia,aspm-pwr-on-t-us = <20>; 2545 nvidia,aspm-l0s-entrance-latency-us = <3>; 2546 2547 bus-range = <0x0 0xff>; 2548 2549 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2550 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2551 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2552 2553 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2554 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2555 interconnect-names = "dma-mem", "write"; 2556 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2557 iommu-map-mask = <0x0>; 2558 dma-coherent; 2559 2560 status = "disabled"; 2561 }; 2562 2563 pcie@14120000 { 2564 compatible = "nvidia,tegra234-pcie"; 2565 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2566 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2567 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2568 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2569 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2570 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2571 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2572 2573 #address-cells = <3>; 2574 #size-cells = <2>; 2575 device_type = "pci"; 2576 num-lanes = <1>; 2577 num-viewport = <8>; 2578 linux,pci-domain = <2>; 2579 2580 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2581 clock-names = "core"; 2582 2583 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2584 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2585 reset-names = "apb", "core"; 2586 2587 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2588 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2589 interrupt-names = "intr", "msi"; 2590 2591 #interrupt-cells = <1>; 2592 interrupt-map-mask = <0 0 0 0>; 2593 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2594 2595 nvidia,bpmp = <&bpmp 2>; 2596 2597 nvidia,aspm-cmrt-us = <60>; 2598 nvidia,aspm-pwr-on-t-us = <20>; 2599 nvidia,aspm-l0s-entrance-latency-us = <3>; 2600 2601 bus-range = <0x0 0xff>; 2602 2603 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2604 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2605 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2606 2607 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2608 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2609 interconnect-names = "dma-mem", "write"; 2610 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2611 iommu-map-mask = <0x0>; 2612 dma-coherent; 2613 2614 status = "disabled"; 2615 }; 2616 2617 pcie@14140000 { 2618 compatible = "nvidia,tegra234-pcie"; 2619 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2620 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2621 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2622 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2623 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2624 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2625 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2626 2627 #address-cells = <3>; 2628 #size-cells = <2>; 2629 device_type = "pci"; 2630 num-lanes = <1>; 2631 num-viewport = <8>; 2632 linux,pci-domain = <3>; 2633 2634 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2635 clock-names = "core"; 2636 2637 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2638 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2639 reset-names = "apb", "core"; 2640 2641 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2642 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2643 interrupt-names = "intr", "msi"; 2644 2645 #interrupt-cells = <1>; 2646 interrupt-map-mask = <0 0 0 0>; 2647 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2648 2649 nvidia,bpmp = <&bpmp 3>; 2650 2651 nvidia,aspm-cmrt-us = <60>; 2652 nvidia,aspm-pwr-on-t-us = <20>; 2653 nvidia,aspm-l0s-entrance-latency-us = <3>; 2654 2655 bus-range = <0x0 0xff>; 2656 2657 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2658 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2659 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2660 2661 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2662 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2663 interconnect-names = "dma-mem", "write"; 2664 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2665 iommu-map-mask = <0x0>; 2666 dma-coherent; 2667 2668 status = "disabled"; 2669 }; 2670 2671 pcie@14160000 { 2672 compatible = "nvidia,tegra234-pcie"; 2673 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2674 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2675 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2676 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2677 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2678 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2679 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2680 2681 #address-cells = <3>; 2682 #size-cells = <2>; 2683 device_type = "pci"; 2684 num-lanes = <4>; 2685 num-viewport = <8>; 2686 linux,pci-domain = <4>; 2687 2688 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2689 clock-names = "core"; 2690 2691 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2692 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2693 reset-names = "apb", "core"; 2694 2695 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2696 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2697 interrupt-names = "intr", "msi"; 2698 2699 #interrupt-cells = <1>; 2700 interrupt-map-mask = <0 0 0 0>; 2701 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2702 2703 nvidia,bpmp = <&bpmp 4>; 2704 2705 nvidia,aspm-cmrt-us = <60>; 2706 nvidia,aspm-pwr-on-t-us = <20>; 2707 nvidia,aspm-l0s-entrance-latency-us = <3>; 2708 2709 bus-range = <0x0 0xff>; 2710 2711 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2712 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2713 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2714 2715 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2716 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2717 interconnect-names = "dma-mem", "write"; 2718 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2719 iommu-map-mask = <0x0>; 2720 dma-coherent; 2721 2722 status = "disabled"; 2723 }; 2724 2725 pcie@14180000 { 2726 compatible = "nvidia,tegra234-pcie"; 2727 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2728 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2729 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2730 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2731 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2732 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2733 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2734 2735 #address-cells = <3>; 2736 #size-cells = <2>; 2737 device_type = "pci"; 2738 num-lanes = <4>; 2739 num-viewport = <8>; 2740 linux,pci-domain = <0>; 2741 2742 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2743 clock-names = "core"; 2744 2745 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2746 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2747 reset-names = "apb", "core"; 2748 2749 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2750 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2751 interrupt-names = "intr", "msi"; 2752 2753 #interrupt-cells = <1>; 2754 interrupt-map-mask = <0 0 0 0>; 2755 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2756 2757 nvidia,bpmp = <&bpmp 0>; 2758 2759 nvidia,aspm-cmrt-us = <60>; 2760 nvidia,aspm-pwr-on-t-us = <20>; 2761 nvidia,aspm-l0s-entrance-latency-us = <3>; 2762 2763 bus-range = <0x0 0xff>; 2764 2765 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2766 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2767 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2768 2769 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2770 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2771 interconnect-names = "dma-mem", "write"; 2772 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2773 iommu-map-mask = <0x0>; 2774 dma-coherent; 2775 2776 status = "disabled"; 2777 }; 2778 2779 pcie@141a0000 { 2780 compatible = "nvidia,tegra234-pcie"; 2781 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2782 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2783 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2784 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2785 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2786 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2787 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2788 2789 #address-cells = <3>; 2790 #size-cells = <2>; 2791 device_type = "pci"; 2792 num-lanes = <8>; 2793 num-viewport = <8>; 2794 linux,pci-domain = <5>; 2795 2796 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2797 clock-names = "core"; 2798 2799 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2800 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2801 reset-names = "apb", "core"; 2802 2803 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2804 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2805 interrupt-names = "intr", "msi"; 2806 2807 #interrupt-cells = <1>; 2808 interrupt-map-mask = <0 0 0 0>; 2809 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2810 2811 nvidia,bpmp = <&bpmp 5>; 2812 2813 nvidia,aspm-cmrt-us = <60>; 2814 nvidia,aspm-pwr-on-t-us = <20>; 2815 nvidia,aspm-l0s-entrance-latency-us = <3>; 2816 2817 bus-range = <0x0 0xff>; 2818 2819 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2820 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2821 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2822 2823 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2824 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2825 interconnect-names = "dma-mem", "write"; 2826 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2827 iommu-map-mask = <0x0>; 2828 dma-coherent; 2829 2830 status = "disabled"; 2831 }; 2832 2833 pcie-ep@141a0000 { 2834 compatible = "nvidia,tegra234-pcie-ep"; 2835 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2836 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2837 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2838 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2839 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2840 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2841 2842 num-lanes = <8>; 2843 2844 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2845 clock-names = "core"; 2846 2847 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2848 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2849 reset-names = "apb", "core"; 2850 2851 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2852 interrupt-names = "intr"; 2853 2854 nvidia,bpmp = <&bpmp 5>; 2855 2856 nvidia,enable-ext-refclk; 2857 nvidia,aspm-cmrt-us = <60>; 2858 nvidia,aspm-pwr-on-t-us = <20>; 2859 nvidia,aspm-l0s-entrance-latency-us = <3>; 2860 2861 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2862 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2863 interconnect-names = "dma-mem", "write"; 2864 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2865 iommu-map-mask = <0x0>; 2866 dma-coherent; 2867 2868 status = "disabled"; 2869 }; 2870 2871 pcie@141c0000 { 2872 compatible = "nvidia,tegra234-pcie"; 2873 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2874 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2875 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2876 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2877 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2878 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2879 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2880 2881 #address-cells = <3>; 2882 #size-cells = <2>; 2883 device_type = "pci"; 2884 num-lanes = <4>; 2885 num-viewport = <8>; 2886 linux,pci-domain = <6>; 2887 2888 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2889 clock-names = "core"; 2890 2891 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2892 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2893 reset-names = "apb", "core"; 2894 2895 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2896 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2897 interrupt-names = "intr", "msi"; 2898 2899 #interrupt-cells = <1>; 2900 interrupt-map-mask = <0 0 0 0>; 2901 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2902 2903 nvidia,bpmp = <&bpmp 6>; 2904 2905 nvidia,aspm-cmrt-us = <60>; 2906 nvidia,aspm-pwr-on-t-us = <20>; 2907 nvidia,aspm-l0s-entrance-latency-us = <3>; 2908 2909 bus-range = <0x0 0xff>; 2910 2911 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2912 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2913 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2914 2915 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2916 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2917 interconnect-names = "dma-mem", "write"; 2918 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2919 iommu-map-mask = <0x0>; 2920 dma-coherent; 2921 2922 status = "disabled"; 2923 }; 2924 2925 pcie-ep@141c0000 { 2926 compatible = "nvidia,tegra234-pcie-ep"; 2927 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2928 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2929 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2930 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2931 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2932 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2933 2934 num-lanes = <4>; 2935 2936 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2937 clock-names = "core"; 2938 2939 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2940 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2941 reset-names = "apb", "core"; 2942 2943 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2944 interrupt-names = "intr"; 2945 2946 nvidia,bpmp = <&bpmp 6>; 2947 2948 nvidia,enable-ext-refclk; 2949 nvidia,aspm-cmrt-us = <60>; 2950 nvidia,aspm-pwr-on-t-us = <20>; 2951 nvidia,aspm-l0s-entrance-latency-us = <3>; 2952 2953 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2954 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2955 interconnect-names = "dma-mem", "write"; 2956 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2957 iommu-map-mask = <0x0>; 2958 dma-coherent; 2959 2960 status = "disabled"; 2961 }; 2962 2963 pcie@141e0000 { 2964 compatible = "nvidia,tegra234-pcie"; 2965 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2966 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2967 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2968 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2969 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2970 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2971 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2972 2973 #address-cells = <3>; 2974 #size-cells = <2>; 2975 device_type = "pci"; 2976 num-lanes = <8>; 2977 num-viewport = <8>; 2978 linux,pci-domain = <7>; 2979 2980 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2981 clock-names = "core"; 2982 2983 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2984 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2985 reset-names = "apb", "core"; 2986 2987 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2988 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2989 interrupt-names = "intr", "msi"; 2990 2991 #interrupt-cells = <1>; 2992 interrupt-map-mask = <0 0 0 0>; 2993 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2994 2995 nvidia,bpmp = <&bpmp 7>; 2996 2997 nvidia,aspm-cmrt-us = <60>; 2998 nvidia,aspm-pwr-on-t-us = <20>; 2999 nvidia,aspm-l0s-entrance-latency-us = <3>; 3000 3001 bus-range = <0x0 0xff>; 3002 3003 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 3004 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 3005 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 3006 3007 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 3008 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 3009 interconnect-names = "dma-mem", "write"; 3010 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 3011 iommu-map-mask = <0x0>; 3012 dma-coherent; 3013 3014 status = "disabled"; 3015 }; 3016 3017 pcie-ep@141e0000 { 3018 compatible = "nvidia,tegra234-pcie-ep"; 3019 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 3020 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 3021 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 3022 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 3023 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 3024 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 3025 3026 num-lanes = <8>; 3027 3028 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 3029 clock-names = "core"; 3030 3031 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 3032 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 3033 reset-names = "apb", "core"; 3034 3035 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 3036 interrupt-names = "intr"; 3037 3038 nvidia,bpmp = <&bpmp 7>; 3039 3040 nvidia,enable-ext-refclk; 3041 nvidia,aspm-cmrt-us = <60>; 3042 nvidia,aspm-pwr-on-t-us = <20>; 3043 nvidia,aspm-l0s-entrance-latency-us = <3>; 3044 3045 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 3046 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 3047 interconnect-names = "dma-mem", "write"; 3048 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 3049 iommu-map-mask = <0x0>; 3050 dma-coherent; 3051 3052 status = "disabled"; 3053 }; 3054 }; 3055 3056 sram@40000000 { 3057 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 3058 reg = <0x0 0x40000000 0x0 0x80000>; 3059 3060 #address-cells = <1>; 3061 #size-cells = <1>; 3062 ranges = <0x0 0x0 0x40000000 0x80000>; 3063 3064 no-memory-wc; 3065 3066 cpu_bpmp_tx: sram@70000 { 3067 reg = <0x70000 0x1000>; 3068 label = "cpu-bpmp-tx"; 3069 pool; 3070 }; 3071 3072 cpu_bpmp_rx: sram@71000 { 3073 reg = <0x71000 0x1000>; 3074 label = "cpu-bpmp-rx"; 3075 pool; 3076 }; 3077 }; 3078 3079 bpmp: bpmp { 3080 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 3081 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3082 TEGRA_HSP_DB_MASTER_BPMP>; 3083 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 3084 #clock-cells = <1>; 3085 #reset-cells = <1>; 3086 #power-domain-cells = <1>; 3087 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 3088 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 3089 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 3090 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 3091 interconnect-names = "read", "write", "dma-mem", "dma-write"; 3092 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 3093 3094 bpmp_i2c: i2c { 3095 compatible = "nvidia,tegra186-bpmp-i2c"; 3096 nvidia,bpmp-bus-id = <5>; 3097 #address-cells = <1>; 3098 #size-cells = <0>; 3099 }; 3100 3101 bpmp_thermal: thermal { 3102 compatible = "nvidia,tegra186-bpmp-thermal"; 3103 #thermal-sensor-cells = <1>; 3104 }; 3105 }; 3106 3107 cpus { 3108 #address-cells = <1>; 3109 #size-cells = <0>; 3110 3111 cpu0_0: cpu@0 { 3112 compatible = "arm,cortex-a78"; 3113 device_type = "cpu"; 3114 reg = <0x00000>; 3115 3116 enable-method = "psci"; 3117 3118 operating-points-v2 = <&cl0_opp_tbl>; 3119 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3120 3121 i-cache-size = <65536>; 3122 i-cache-line-size = <64>; 3123 i-cache-sets = <256>; 3124 d-cache-size = <65536>; 3125 d-cache-line-size = <64>; 3126 d-cache-sets = <256>; 3127 next-level-cache = <&l2c0_0>; 3128 }; 3129 3130 cpu0_1: cpu@100 { 3131 compatible = "arm,cortex-a78"; 3132 device_type = "cpu"; 3133 reg = <0x00100>; 3134 3135 enable-method = "psci"; 3136 3137 operating-points-v2 = <&cl0_opp_tbl>; 3138 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3139 3140 i-cache-size = <65536>; 3141 i-cache-line-size = <64>; 3142 i-cache-sets = <256>; 3143 d-cache-size = <65536>; 3144 d-cache-line-size = <64>; 3145 d-cache-sets = <256>; 3146 next-level-cache = <&l2c0_1>; 3147 }; 3148 3149 cpu0_2: cpu@200 { 3150 compatible = "arm,cortex-a78"; 3151 device_type = "cpu"; 3152 reg = <0x00200>; 3153 3154 enable-method = "psci"; 3155 3156 operating-points-v2 = <&cl0_opp_tbl>; 3157 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3158 3159 i-cache-size = <65536>; 3160 i-cache-line-size = <64>; 3161 i-cache-sets = <256>; 3162 d-cache-size = <65536>; 3163 d-cache-line-size = <64>; 3164 d-cache-sets = <256>; 3165 next-level-cache = <&l2c0_2>; 3166 }; 3167 3168 cpu0_3: cpu@300 { 3169 compatible = "arm,cortex-a78"; 3170 device_type = "cpu"; 3171 reg = <0x00300>; 3172 3173 enable-method = "psci"; 3174 3175 operating-points-v2 = <&cl0_opp_tbl>; 3176 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 3177 3178 i-cache-size = <65536>; 3179 i-cache-line-size = <64>; 3180 i-cache-sets = <256>; 3181 d-cache-size = <65536>; 3182 d-cache-line-size = <64>; 3183 d-cache-sets = <256>; 3184 next-level-cache = <&l2c0_3>; 3185 }; 3186 3187 cpu1_0: cpu@10000 { 3188 compatible = "arm,cortex-a78"; 3189 device_type = "cpu"; 3190 reg = <0x10000>; 3191 3192 enable-method = "psci"; 3193 3194 operating-points-v2 = <&cl1_opp_tbl>; 3195 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3196 3197 i-cache-size = <65536>; 3198 i-cache-line-size = <64>; 3199 i-cache-sets = <256>; 3200 d-cache-size = <65536>; 3201 d-cache-line-size = <64>; 3202 d-cache-sets = <256>; 3203 next-level-cache = <&l2c1_0>; 3204 }; 3205 3206 cpu1_1: cpu@10100 { 3207 compatible = "arm,cortex-a78"; 3208 device_type = "cpu"; 3209 reg = <0x10100>; 3210 3211 enable-method = "psci"; 3212 3213 operating-points-v2 = <&cl1_opp_tbl>; 3214 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3215 3216 i-cache-size = <65536>; 3217 i-cache-line-size = <64>; 3218 i-cache-sets = <256>; 3219 d-cache-size = <65536>; 3220 d-cache-line-size = <64>; 3221 d-cache-sets = <256>; 3222 next-level-cache = <&l2c1_1>; 3223 }; 3224 3225 cpu1_2: cpu@10200 { 3226 compatible = "arm,cortex-a78"; 3227 device_type = "cpu"; 3228 reg = <0x10200>; 3229 3230 enable-method = "psci"; 3231 3232 operating-points-v2 = <&cl1_opp_tbl>; 3233 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3234 3235 i-cache-size = <65536>; 3236 i-cache-line-size = <64>; 3237 i-cache-sets = <256>; 3238 d-cache-size = <65536>; 3239 d-cache-line-size = <64>; 3240 d-cache-sets = <256>; 3241 next-level-cache = <&l2c1_2>; 3242 }; 3243 3244 cpu1_3: cpu@10300 { 3245 compatible = "arm,cortex-a78"; 3246 device_type = "cpu"; 3247 reg = <0x10300>; 3248 3249 enable-method = "psci"; 3250 3251 operating-points-v2 = <&cl1_opp_tbl>; 3252 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 3253 3254 i-cache-size = <65536>; 3255 i-cache-line-size = <64>; 3256 i-cache-sets = <256>; 3257 d-cache-size = <65536>; 3258 d-cache-line-size = <64>; 3259 d-cache-sets = <256>; 3260 next-level-cache = <&l2c1_3>; 3261 }; 3262 3263 cpu2_0: cpu@20000 { 3264 compatible = "arm,cortex-a78"; 3265 device_type = "cpu"; 3266 reg = <0x20000>; 3267 3268 enable-method = "psci"; 3269 3270 operating-points-v2 = <&cl2_opp_tbl>; 3271 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3272 3273 i-cache-size = <65536>; 3274 i-cache-line-size = <64>; 3275 i-cache-sets = <256>; 3276 d-cache-size = <65536>; 3277 d-cache-line-size = <64>; 3278 d-cache-sets = <256>; 3279 next-level-cache = <&l2c2_0>; 3280 }; 3281 3282 cpu2_1: cpu@20100 { 3283 compatible = "arm,cortex-a78"; 3284 device_type = "cpu"; 3285 reg = <0x20100>; 3286 3287 enable-method = "psci"; 3288 3289 operating-points-v2 = <&cl2_opp_tbl>; 3290 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3291 3292 i-cache-size = <65536>; 3293 i-cache-line-size = <64>; 3294 i-cache-sets = <256>; 3295 d-cache-size = <65536>; 3296 d-cache-line-size = <64>; 3297 d-cache-sets = <256>; 3298 next-level-cache = <&l2c2_1>; 3299 }; 3300 3301 cpu2_2: cpu@20200 { 3302 compatible = "arm,cortex-a78"; 3303 device_type = "cpu"; 3304 reg = <0x20200>; 3305 3306 enable-method = "psci"; 3307 3308 operating-points-v2 = <&cl2_opp_tbl>; 3309 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3310 3311 i-cache-size = <65536>; 3312 i-cache-line-size = <64>; 3313 i-cache-sets = <256>; 3314 d-cache-size = <65536>; 3315 d-cache-line-size = <64>; 3316 d-cache-sets = <256>; 3317 next-level-cache = <&l2c2_2>; 3318 }; 3319 3320 cpu2_3: cpu@20300 { 3321 compatible = "arm,cortex-a78"; 3322 device_type = "cpu"; 3323 reg = <0x20300>; 3324 3325 enable-method = "psci"; 3326 3327 operating-points-v2 = <&cl2_opp_tbl>; 3328 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 3329 3330 i-cache-size = <65536>; 3331 i-cache-line-size = <64>; 3332 i-cache-sets = <256>; 3333 d-cache-size = <65536>; 3334 d-cache-line-size = <64>; 3335 d-cache-sets = <256>; 3336 next-level-cache = <&l2c2_3>; 3337 }; 3338 3339 cpu-map { 3340 cluster0 { 3341 core0 { 3342 cpu = <&cpu0_0>; 3343 }; 3344 3345 core1 { 3346 cpu = <&cpu0_1>; 3347 }; 3348 3349 core2 { 3350 cpu = <&cpu0_2>; 3351 }; 3352 3353 core3 { 3354 cpu = <&cpu0_3>; 3355 }; 3356 }; 3357 3358 cluster1 { 3359 core0 { 3360 cpu = <&cpu1_0>; 3361 }; 3362 3363 core1 { 3364 cpu = <&cpu1_1>; 3365 }; 3366 3367 core2 { 3368 cpu = <&cpu1_2>; 3369 }; 3370 3371 core3 { 3372 cpu = <&cpu1_3>; 3373 }; 3374 }; 3375 3376 cluster2 { 3377 core0 { 3378 cpu = <&cpu2_0>; 3379 }; 3380 3381 core1 { 3382 cpu = <&cpu2_1>; 3383 }; 3384 3385 core2 { 3386 cpu = <&cpu2_2>; 3387 }; 3388 3389 core3 { 3390 cpu = <&cpu2_3>; 3391 }; 3392 }; 3393 }; 3394 3395 l2c0_0: l2-cache00 { 3396 compatible = "cache"; 3397 cache-size = <262144>; 3398 cache-line-size = <64>; 3399 cache-sets = <512>; 3400 cache-unified; 3401 cache-level = <2>; 3402 next-level-cache = <&l3c0>; 3403 }; 3404 3405 l2c0_1: l2-cache01 { 3406 compatible = "cache"; 3407 cache-size = <262144>; 3408 cache-line-size = <64>; 3409 cache-sets = <512>; 3410 cache-unified; 3411 cache-level = <2>; 3412 next-level-cache = <&l3c0>; 3413 }; 3414 3415 l2c0_2: l2-cache02 { 3416 compatible = "cache"; 3417 cache-size = <262144>; 3418 cache-line-size = <64>; 3419 cache-sets = <512>; 3420 cache-unified; 3421 cache-level = <2>; 3422 next-level-cache = <&l3c0>; 3423 }; 3424 3425 l2c0_3: l2-cache03 { 3426 compatible = "cache"; 3427 cache-size = <262144>; 3428 cache-line-size = <64>; 3429 cache-sets = <512>; 3430 cache-unified; 3431 cache-level = <2>; 3432 next-level-cache = <&l3c0>; 3433 }; 3434 3435 l2c1_0: l2-cache10 { 3436 compatible = "cache"; 3437 cache-size = <262144>; 3438 cache-line-size = <64>; 3439 cache-sets = <512>; 3440 cache-unified; 3441 cache-level = <2>; 3442 next-level-cache = <&l3c1>; 3443 }; 3444 3445 l2c1_1: l2-cache11 { 3446 compatible = "cache"; 3447 cache-size = <262144>; 3448 cache-line-size = <64>; 3449 cache-sets = <512>; 3450 cache-unified; 3451 cache-level = <2>; 3452 next-level-cache = <&l3c1>; 3453 }; 3454 3455 l2c1_2: l2-cache12 { 3456 compatible = "cache"; 3457 cache-size = <262144>; 3458 cache-line-size = <64>; 3459 cache-sets = <512>; 3460 cache-unified; 3461 cache-level = <2>; 3462 next-level-cache = <&l3c1>; 3463 }; 3464 3465 l2c1_3: l2-cache13 { 3466 compatible = "cache"; 3467 cache-size = <262144>; 3468 cache-line-size = <64>; 3469 cache-sets = <512>; 3470 cache-unified; 3471 cache-level = <2>; 3472 next-level-cache = <&l3c1>; 3473 }; 3474 3475 l2c2_0: l2-cache20 { 3476 compatible = "cache"; 3477 cache-size = <262144>; 3478 cache-line-size = <64>; 3479 cache-sets = <512>; 3480 cache-unified; 3481 cache-level = <2>; 3482 next-level-cache = <&l3c2>; 3483 }; 3484 3485 l2c2_1: l2-cache21 { 3486 compatible = "cache"; 3487 cache-size = <262144>; 3488 cache-line-size = <64>; 3489 cache-sets = <512>; 3490 cache-unified; 3491 cache-level = <2>; 3492 next-level-cache = <&l3c2>; 3493 }; 3494 3495 l2c2_2: l2-cache22 { 3496 compatible = "cache"; 3497 cache-size = <262144>; 3498 cache-line-size = <64>; 3499 cache-sets = <512>; 3500 cache-unified; 3501 cache-level = <2>; 3502 next-level-cache = <&l3c2>; 3503 }; 3504 3505 l2c2_3: l2-cache23 { 3506 compatible = "cache"; 3507 cache-size = <262144>; 3508 cache-line-size = <64>; 3509 cache-sets = <512>; 3510 cache-unified; 3511 cache-level = <2>; 3512 next-level-cache = <&l3c2>; 3513 }; 3514 3515 l3c0: l3-cache0 { 3516 compatible = "cache"; 3517 cache-unified; 3518 cache-size = <2097152>; 3519 cache-line-size = <64>; 3520 cache-sets = <2048>; 3521 cache-level = <3>; 3522 }; 3523 3524 l3c1: l3-cache1 { 3525 compatible = "cache"; 3526 cache-unified; 3527 cache-size = <2097152>; 3528 cache-line-size = <64>; 3529 cache-sets = <2048>; 3530 cache-level = <3>; 3531 }; 3532 3533 l3c2: l3-cache2 { 3534 compatible = "cache"; 3535 cache-unified; 3536 cache-size = <2097152>; 3537 cache-line-size = <64>; 3538 cache-sets = <2048>; 3539 cache-level = <3>; 3540 }; 3541 }; 3542 3543 dsu-pmu0 { 3544 compatible = "arm,dsu-pmu"; 3545 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 3546 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 3547 }; 3548 3549 dsu-pmu1 { 3550 compatible = "arm,dsu-pmu"; 3551 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 3552 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 3553 }; 3554 3555 dsu-pmu2 { 3556 compatible = "arm,dsu-pmu"; 3557 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 3558 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 3559 }; 3560 3561 pmu { 3562 compatible = "arm,cortex-a78-pmu"; 3563 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3564 status = "okay"; 3565 }; 3566 3567 psci { 3568 compatible = "arm,psci-1.0"; 3569 status = "okay"; 3570 method = "smc"; 3571 }; 3572 3573 tcu: serial { 3574 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3575 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3576 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3577 mbox-names = "rx", "tx"; 3578 status = "disabled"; 3579 }; 3580 3581 sound { 3582 status = "disabled"; 3583 3584 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3585 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3586 clock-names = "pll_a", "plla_out0"; 3587 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3588 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3589 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3590 assigned-clock-parents = <0>, 3591 <&bpmp TEGRA234_CLK_PLLA>, 3592 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3593 }; 3594 3595 thermal-zones { 3596 cpu-thermal { 3597 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 3598 status = "disabled"; 3599 }; 3600 3601 gpu-thermal { 3602 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 3603 status = "disabled"; 3604 }; 3605 3606 cv0-thermal { 3607 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 3608 status = "disabled"; 3609 }; 3610 3611 cv1-thermal { 3612 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 3613 status = "disabled"; 3614 }; 3615 3616 cv2-thermal { 3617 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 3618 status = "disabled"; 3619 }; 3620 3621 soc0-thermal { 3622 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 3623 status = "disabled"; 3624 }; 3625 3626 soc1-thermal { 3627 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 3628 status = "disabled"; 3629 }; 3630 3631 soc2-thermal { 3632 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 3633 status = "disabled"; 3634 }; 3635 3636 tj-thermal { 3637 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 3638 status = "disabled"; 3639 }; 3640 }; 3641 3642 timer { 3643 compatible = "arm,armv8-timer"; 3644 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3645 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3646 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3647 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3648 interrupt-parent = <&gic>; 3649 always-on; 3650 }; 3651 3652 cl0_opp_tbl: opp-table-cluster0 { 3653 compatible = "operating-points-v2"; 3654 opp-shared; 3655 3656 cl0_ch1_opp1: opp-115200000 { 3657 opp-hz = /bits/ 64 <115200000>; 3658 opp-peak-kBps = <816000>; 3659 }; 3660 3661 cl0_ch1_opp2: opp-192000000 { 3662 opp-hz = /bits/ 64 <192000000>; 3663 opp-peak-kBps = <816000>; 3664 }; 3665 3666 cl0_ch1_opp3: opp-268800000 { 3667 opp-hz = /bits/ 64 <268800000>; 3668 opp-peak-kBps = <816000>; 3669 }; 3670 3671 cl0_ch1_opp4: opp-345600000 { 3672 opp-hz = /bits/ 64 <345600000>; 3673 opp-peak-kBps = <816000>; 3674 }; 3675 3676 cl0_ch1_opp5: opp-422400000 { 3677 opp-hz = /bits/ 64 <422400000>; 3678 opp-peak-kBps = <816000>; 3679 }; 3680 3681 cl0_ch1_opp6: opp-499200000 { 3682 opp-hz = /bits/ 64 <499200000>; 3683 opp-peak-kBps = <816000>; 3684 }; 3685 3686 cl0_ch1_opp7: opp-576000000 { 3687 opp-hz = /bits/ 64 <576000000>; 3688 opp-peak-kBps = <816000>; 3689 }; 3690 3691 cl0_ch1_opp8: opp-652800000 { 3692 opp-hz = /bits/ 64 <652800000>; 3693 opp-peak-kBps = <816000>; 3694 }; 3695 3696 cl0_ch1_opp9: opp-729600000 { 3697 opp-hz = /bits/ 64 <729600000>; 3698 opp-peak-kBps = <816000>; 3699 }; 3700 3701 cl0_ch1_opp10: opp-806400000 { 3702 opp-hz = /bits/ 64 <806400000>; 3703 opp-peak-kBps = <816000>; 3704 }; 3705 3706 cl0_ch1_opp11: opp-883200000 { 3707 opp-hz = /bits/ 64 <883200000>; 3708 opp-peak-kBps = <816000>; 3709 }; 3710 3711 cl0_ch1_opp12: opp-960000000 { 3712 opp-hz = /bits/ 64 <960000000>; 3713 opp-peak-kBps = <816000>; 3714 }; 3715 3716 cl0_ch1_opp13: opp-1036800000 { 3717 opp-hz = /bits/ 64 <1036800000>; 3718 opp-peak-kBps = <816000>; 3719 }; 3720 3721 cl0_ch1_opp14: opp-1113600000 { 3722 opp-hz = /bits/ 64 <1113600000>; 3723 opp-peak-kBps = <1632000>; 3724 }; 3725 3726 cl0_ch1_opp15: opp-1190400000 { 3727 opp-hz = /bits/ 64 <1190400000>; 3728 opp-peak-kBps = <1632000>; 3729 }; 3730 3731 cl0_ch1_opp16: opp-1267200000 { 3732 opp-hz = /bits/ 64 <1267200000>; 3733 opp-peak-kBps = <1632000>; 3734 }; 3735 3736 cl0_ch1_opp17: opp-1344000000 { 3737 opp-hz = /bits/ 64 <1344000000>; 3738 opp-peak-kBps = <1632000>; 3739 }; 3740 3741 cl0_ch1_opp18: opp-1420800000 { 3742 opp-hz = /bits/ 64 <1420800000>; 3743 opp-peak-kBps = <1632000>; 3744 }; 3745 3746 cl0_ch1_opp19: opp-1497600000 { 3747 opp-hz = /bits/ 64 <1497600000>; 3748 opp-peak-kBps = <3200000>; 3749 }; 3750 3751 cl0_ch1_opp20: opp-1574400000 { 3752 opp-hz = /bits/ 64 <1574400000>; 3753 opp-peak-kBps = <3200000>; 3754 }; 3755 3756 cl0_ch1_opp21: opp-1651200000 { 3757 opp-hz = /bits/ 64 <1651200000>; 3758 opp-peak-kBps = <3200000>; 3759 }; 3760 3761 cl0_ch1_opp22: opp-1728000000 { 3762 opp-hz = /bits/ 64 <1728000000>; 3763 opp-peak-kBps = <3200000>; 3764 }; 3765 3766 cl0_ch1_opp23: opp-1804800000 { 3767 opp-hz = /bits/ 64 <1804800000>; 3768 opp-peak-kBps = <3200000>; 3769 }; 3770 3771 cl0_ch1_opp24: opp-1881600000 { 3772 opp-hz = /bits/ 64 <1881600000>; 3773 opp-peak-kBps = <3200000>; 3774 }; 3775 3776 cl0_ch1_opp25: opp-1958400000 { 3777 opp-hz = /bits/ 64 <1958400000>; 3778 opp-peak-kBps = <3200000>; 3779 }; 3780 3781 cl0_ch1_opp26: opp-2035200000 { 3782 opp-hz = /bits/ 64 <2035200000>; 3783 opp-peak-kBps = <3200000>; 3784 }; 3785 3786 cl0_ch1_opp27: opp-2112000000 { 3787 opp-hz = /bits/ 64 <2112000000>; 3788 opp-peak-kBps = <6400000>; 3789 }; 3790 3791 cl0_ch1_opp28: opp-2188800000 { 3792 opp-hz = /bits/ 64 <2188800000>; 3793 opp-peak-kBps = <6400000>; 3794 }; 3795 3796 cl0_ch1_opp29: opp-2201600000 { 3797 opp-hz = /bits/ 64 <2201600000>; 3798 opp-peak-kBps = <6400000>; 3799 }; 3800 }; 3801 3802 cl1_opp_tbl: opp-table-cluster1 { 3803 compatible = "operating-points-v2"; 3804 opp-shared; 3805 3806 cl1_ch1_opp1: opp-115200000 { 3807 opp-hz = /bits/ 64 <115200000>; 3808 opp-peak-kBps = <816000>; 3809 }; 3810 3811 cl1_ch1_opp2: opp-192000000 { 3812 opp-hz = /bits/ 64 <192000000>; 3813 opp-peak-kBps = <816000>; 3814 }; 3815 3816 cl1_ch1_opp3: opp-268800000 { 3817 opp-hz = /bits/ 64 <268800000>; 3818 opp-peak-kBps = <816000>; 3819 }; 3820 3821 cl1_ch1_opp4: opp-345600000 { 3822 opp-hz = /bits/ 64 <345600000>; 3823 opp-peak-kBps = <816000>; 3824 }; 3825 3826 cl1_ch1_opp5: opp-422400000 { 3827 opp-hz = /bits/ 64 <422400000>; 3828 opp-peak-kBps = <816000>; 3829 }; 3830 3831 cl1_ch1_opp6: opp-499200000 { 3832 opp-hz = /bits/ 64 <499200000>; 3833 opp-peak-kBps = <816000>; 3834 }; 3835 3836 cl1_ch1_opp7: opp-576000000 { 3837 opp-hz = /bits/ 64 <576000000>; 3838 opp-peak-kBps = <816000>; 3839 }; 3840 3841 cl1_ch1_opp8: opp-652800000 { 3842 opp-hz = /bits/ 64 <652800000>; 3843 opp-peak-kBps = <816000>; 3844 }; 3845 3846 cl1_ch1_opp9: opp-729600000 { 3847 opp-hz = /bits/ 64 <729600000>; 3848 opp-peak-kBps = <816000>; 3849 }; 3850 3851 cl1_ch1_opp10: opp-806400000 { 3852 opp-hz = /bits/ 64 <806400000>; 3853 opp-peak-kBps = <816000>; 3854 }; 3855 3856 cl1_ch1_opp11: opp-883200000 { 3857 opp-hz = /bits/ 64 <883200000>; 3858 opp-peak-kBps = <816000>; 3859 }; 3860 3861 cl1_ch1_opp12: opp-960000000 { 3862 opp-hz = /bits/ 64 <960000000>; 3863 opp-peak-kBps = <816000>; 3864 }; 3865 3866 cl1_ch1_opp13: opp-1036800000 { 3867 opp-hz = /bits/ 64 <1036800000>; 3868 opp-peak-kBps = <816000>; 3869 }; 3870 3871 cl1_ch1_opp14: opp-1113600000 { 3872 opp-hz = /bits/ 64 <1113600000>; 3873 opp-peak-kBps = <1632000>; 3874 }; 3875 3876 cl1_ch1_opp15: opp-1190400000 { 3877 opp-hz = /bits/ 64 <1190400000>; 3878 opp-peak-kBps = <1632000>; 3879 }; 3880 3881 cl1_ch1_opp16: opp-1267200000 { 3882 opp-hz = /bits/ 64 <1267200000>; 3883 opp-peak-kBps = <1632000>; 3884 }; 3885 3886 cl1_ch1_opp17: opp-1344000000 { 3887 opp-hz = /bits/ 64 <1344000000>; 3888 opp-peak-kBps = <1632000>; 3889 }; 3890 3891 cl1_ch1_opp18: opp-1420800000 { 3892 opp-hz = /bits/ 64 <1420800000>; 3893 opp-peak-kBps = <1632000>; 3894 }; 3895 3896 cl1_ch1_opp19: opp-1497600000 { 3897 opp-hz = /bits/ 64 <1497600000>; 3898 opp-peak-kBps = <3200000>; 3899 }; 3900 3901 cl1_ch1_opp20: opp-1574400000 { 3902 opp-hz = /bits/ 64 <1574400000>; 3903 opp-peak-kBps = <3200000>; 3904 }; 3905 3906 cl1_ch1_opp21: opp-1651200000 { 3907 opp-hz = /bits/ 64 <1651200000>; 3908 opp-peak-kBps = <3200000>; 3909 }; 3910 3911 cl1_ch1_opp22: opp-1728000000 { 3912 opp-hz = /bits/ 64 <1728000000>; 3913 opp-peak-kBps = <3200000>; 3914 }; 3915 3916 cl1_ch1_opp23: opp-1804800000 { 3917 opp-hz = /bits/ 64 <1804800000>; 3918 opp-peak-kBps = <3200000>; 3919 }; 3920 3921 cl1_ch1_opp24: opp-1881600000 { 3922 opp-hz = /bits/ 64 <1881600000>; 3923 opp-peak-kBps = <3200000>; 3924 }; 3925 3926 cl1_ch1_opp25: opp-1958400000 { 3927 opp-hz = /bits/ 64 <1958400000>; 3928 opp-peak-kBps = <3200000>; 3929 }; 3930 3931 cl1_ch1_opp26: opp-2035200000 { 3932 opp-hz = /bits/ 64 <2035200000>; 3933 opp-peak-kBps = <3200000>; 3934 }; 3935 3936 cl1_ch1_opp27: opp-2112000000 { 3937 opp-hz = /bits/ 64 <2112000000>; 3938 opp-peak-kBps = <6400000>; 3939 }; 3940 3941 cl1_ch1_opp28: opp-2188800000 { 3942 opp-hz = /bits/ 64 <2188800000>; 3943 opp-peak-kBps = <6400000>; 3944 }; 3945 3946 cl1_ch1_opp29: opp-2201600000 { 3947 opp-hz = /bits/ 64 <2201600000>; 3948 opp-peak-kBps = <6400000>; 3949 }; 3950 }; 3951 3952 cl2_opp_tbl: opp-table-cluster2 { 3953 compatible = "operating-points-v2"; 3954 opp-shared; 3955 3956 cl2_ch1_opp1: opp-115200000 { 3957 opp-hz = /bits/ 64 <115200000>; 3958 opp-peak-kBps = <816000>; 3959 }; 3960 3961 cl2_ch1_opp2: opp-192000000 { 3962 opp-hz = /bits/ 64 <192000000>; 3963 opp-peak-kBps = <816000>; 3964 }; 3965 3966 cl2_ch1_opp3: opp-268800000 { 3967 opp-hz = /bits/ 64 <268800000>; 3968 opp-peak-kBps = <816000>; 3969 }; 3970 3971 cl2_ch1_opp4: opp-345600000 { 3972 opp-hz = /bits/ 64 <345600000>; 3973 opp-peak-kBps = <816000>; 3974 }; 3975 3976 cl2_ch1_opp5: opp-422400000 { 3977 opp-hz = /bits/ 64 <422400000>; 3978 opp-peak-kBps = <816000>; 3979 }; 3980 3981 cl2_ch1_opp6: opp-499200000 { 3982 opp-hz = /bits/ 64 <499200000>; 3983 opp-peak-kBps = <816000>; 3984 }; 3985 3986 cl2_ch1_opp7: opp-576000000 { 3987 opp-hz = /bits/ 64 <576000000>; 3988 opp-peak-kBps = <816000>; 3989 }; 3990 3991 cl2_ch1_opp8: opp-652800000 { 3992 opp-hz = /bits/ 64 <652800000>; 3993 opp-peak-kBps = <816000>; 3994 }; 3995 3996 cl2_ch1_opp9: opp-729600000 { 3997 opp-hz = /bits/ 64 <729600000>; 3998 opp-peak-kBps = <816000>; 3999 }; 4000 4001 cl2_ch1_opp10: opp-806400000 { 4002 opp-hz = /bits/ 64 <806400000>; 4003 opp-peak-kBps = <816000>; 4004 }; 4005 4006 cl2_ch1_opp11: opp-883200000 { 4007 opp-hz = /bits/ 64 <883200000>; 4008 opp-peak-kBps = <816000>; 4009 }; 4010 4011 cl2_ch1_opp12: opp-960000000 { 4012 opp-hz = /bits/ 64 <960000000>; 4013 opp-peak-kBps = <816000>; 4014 }; 4015 4016 cl2_ch1_opp13: opp-1036800000 { 4017 opp-hz = /bits/ 64 <1036800000>; 4018 opp-peak-kBps = <816000>; 4019 }; 4020 4021 cl2_ch1_opp14: opp-1113600000 { 4022 opp-hz = /bits/ 64 <1113600000>; 4023 opp-peak-kBps = <1632000>; 4024 }; 4025 4026 cl2_ch1_opp15: opp-1190400000 { 4027 opp-hz = /bits/ 64 <1190400000>; 4028 opp-peak-kBps = <1632000>; 4029 }; 4030 4031 cl2_ch1_opp16: opp-1267200000 { 4032 opp-hz = /bits/ 64 <1267200000>; 4033 opp-peak-kBps = <1632000>; 4034 }; 4035 4036 cl2_ch1_opp17: opp-1344000000 { 4037 opp-hz = /bits/ 64 <1344000000>; 4038 opp-peak-kBps = <1632000>; 4039 }; 4040 4041 cl2_ch1_opp18: opp-1420800000 { 4042 opp-hz = /bits/ 64 <1420800000>; 4043 opp-peak-kBps = <1632000>; 4044 }; 4045 4046 cl2_ch1_opp19: opp-1497600000 { 4047 opp-hz = /bits/ 64 <1497600000>; 4048 opp-peak-kBps = <3200000>; 4049 }; 4050 4051 cl2_ch1_opp20: opp-1574400000 { 4052 opp-hz = /bits/ 64 <1574400000>; 4053 opp-peak-kBps = <3200000>; 4054 }; 4055 4056 cl2_ch1_opp21: opp-1651200000 { 4057 opp-hz = /bits/ 64 <1651200000>; 4058 opp-peak-kBps = <3200000>; 4059 }; 4060 4061 cl2_ch1_opp22: opp-1728000000 { 4062 opp-hz = /bits/ 64 <1728000000>; 4063 opp-peak-kBps = <3200000>; 4064 }; 4065 4066 cl2_ch1_opp23: opp-1804800000 { 4067 opp-hz = /bits/ 64 <1804800000>; 4068 opp-peak-kBps = <3200000>; 4069 }; 4070 4071 cl2_ch1_opp24: opp-1881600000 { 4072 opp-hz = /bits/ 64 <1881600000>; 4073 opp-peak-kBps = <3200000>; 4074 }; 4075 4076 cl2_ch1_opp25: opp-1958400000 { 4077 opp-hz = /bits/ 64 <1958400000>; 4078 opp-peak-kBps = <3200000>; 4079 }; 4080 4081 cl2_ch1_opp26: opp-2035200000 { 4082 opp-hz = /bits/ 64 <2035200000>; 4083 opp-peak-kBps = <3200000>; 4084 }; 4085 4086 cl2_ch1_opp27: opp-2112000000 { 4087 opp-hz = /bits/ 64 <2112000000>; 4088 opp-peak-kBps = <6400000>; 4089 }; 4090 4091 cl2_ch1_opp28: opp-2188800000 { 4092 opp-hz = /bits/ 64 <2188800000>; 4093 opp-peak-kBps = <6400000>; 4094 }; 4095 4096 cl2_ch1_opp29: opp-2201600000 { 4097 opp-hz = /bits/ 64 <2201600000>; 4098 opp-peak-kBps = <6400000>; 4099 }; 4100 }; 4101 }; 4102