1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/micrel_phy.h>
25 #include <net/dsa.h>
26 #include <net/pkt_cls.h>
27 #include <net/switchdev.h>
28
29 #include "ksz_common.h"
30 #include "ksz_ptp.h"
31 #include "ksz8.h"
32 #include "ksz9477.h"
33 #include "lan937x.h"
34
35 #define MIB_COUNTER_NUM 0x20
36
37 struct ksz_stats_raw {
38 u64 rx_hi;
39 u64 rx_undersize;
40 u64 rx_fragments;
41 u64 rx_oversize;
42 u64 rx_jabbers;
43 u64 rx_symbol_err;
44 u64 rx_crc_err;
45 u64 rx_align_err;
46 u64 rx_mac_ctrl;
47 u64 rx_pause;
48 u64 rx_bcast;
49 u64 rx_mcast;
50 u64 rx_ucast;
51 u64 rx_64_or_less;
52 u64 rx_65_127;
53 u64 rx_128_255;
54 u64 rx_256_511;
55 u64 rx_512_1023;
56 u64 rx_1024_1522;
57 u64 rx_1523_2000;
58 u64 rx_2001;
59 u64 tx_hi;
60 u64 tx_late_col;
61 u64 tx_pause;
62 u64 tx_bcast;
63 u64 tx_mcast;
64 u64 tx_ucast;
65 u64 tx_deferred;
66 u64 tx_total_col;
67 u64 tx_exc_col;
68 u64 tx_single_col;
69 u64 tx_mult_col;
70 u64 rx_total;
71 u64 tx_total;
72 u64 rx_discards;
73 u64 tx_discards;
74 };
75
76 struct ksz88xx_stats_raw {
77 u64 rx;
78 u64 rx_hi;
79 u64 rx_undersize;
80 u64 rx_fragments;
81 u64 rx_oversize;
82 u64 rx_jabbers;
83 u64 rx_symbol_err;
84 u64 rx_crc_err;
85 u64 rx_align_err;
86 u64 rx_mac_ctrl;
87 u64 rx_pause;
88 u64 rx_bcast;
89 u64 rx_mcast;
90 u64 rx_ucast;
91 u64 rx_64_or_less;
92 u64 rx_65_127;
93 u64 rx_128_255;
94 u64 rx_256_511;
95 u64 rx_512_1023;
96 u64 rx_1024_1522;
97 u64 tx;
98 u64 tx_hi;
99 u64 tx_late_col;
100 u64 tx_pause;
101 u64 tx_bcast;
102 u64 tx_mcast;
103 u64 tx_ucast;
104 u64 tx_deferred;
105 u64 tx_total_col;
106 u64 tx_exc_col;
107 u64 tx_single_col;
108 u64 tx_mult_col;
109 u64 rx_discards;
110 u64 tx_discards;
111 };
112
113 static const struct ksz_mib_names ksz88xx_mib_names[] = {
114 { 0x00, "rx" },
115 { 0x01, "rx_hi" },
116 { 0x02, "rx_undersize" },
117 { 0x03, "rx_fragments" },
118 { 0x04, "rx_oversize" },
119 { 0x05, "rx_jabbers" },
120 { 0x06, "rx_symbol_err" },
121 { 0x07, "rx_crc_err" },
122 { 0x08, "rx_align_err" },
123 { 0x09, "rx_mac_ctrl" },
124 { 0x0a, "rx_pause" },
125 { 0x0b, "rx_bcast" },
126 { 0x0c, "rx_mcast" },
127 { 0x0d, "rx_ucast" },
128 { 0x0e, "rx_64_or_less" },
129 { 0x0f, "rx_65_127" },
130 { 0x10, "rx_128_255" },
131 { 0x11, "rx_256_511" },
132 { 0x12, "rx_512_1023" },
133 { 0x13, "rx_1024_1522" },
134 { 0x14, "tx" },
135 { 0x15, "tx_hi" },
136 { 0x16, "tx_late_col" },
137 { 0x17, "tx_pause" },
138 { 0x18, "tx_bcast" },
139 { 0x19, "tx_mcast" },
140 { 0x1a, "tx_ucast" },
141 { 0x1b, "tx_deferred" },
142 { 0x1c, "tx_total_col" },
143 { 0x1d, "tx_exc_col" },
144 { 0x1e, "tx_single_col" },
145 { 0x1f, "tx_mult_col" },
146 { 0x100, "rx_discards" },
147 { 0x101, "tx_discards" },
148 };
149
150 static const struct ksz_mib_names ksz9477_mib_names[] = {
151 { 0x00, "rx_hi" },
152 { 0x01, "rx_undersize" },
153 { 0x02, "rx_fragments" },
154 { 0x03, "rx_oversize" },
155 { 0x04, "rx_jabbers" },
156 { 0x05, "rx_symbol_err" },
157 { 0x06, "rx_crc_err" },
158 { 0x07, "rx_align_err" },
159 { 0x08, "rx_mac_ctrl" },
160 { 0x09, "rx_pause" },
161 { 0x0A, "rx_bcast" },
162 { 0x0B, "rx_mcast" },
163 { 0x0C, "rx_ucast" },
164 { 0x0D, "rx_64_or_less" },
165 { 0x0E, "rx_65_127" },
166 { 0x0F, "rx_128_255" },
167 { 0x10, "rx_256_511" },
168 { 0x11, "rx_512_1023" },
169 { 0x12, "rx_1024_1522" },
170 { 0x13, "rx_1523_2000" },
171 { 0x14, "rx_2001" },
172 { 0x15, "tx_hi" },
173 { 0x16, "tx_late_col" },
174 { 0x17, "tx_pause" },
175 { 0x18, "tx_bcast" },
176 { 0x19, "tx_mcast" },
177 { 0x1A, "tx_ucast" },
178 { 0x1B, "tx_deferred" },
179 { 0x1C, "tx_total_col" },
180 { 0x1D, "tx_exc_col" },
181 { 0x1E, "tx_single_col" },
182 { 0x1F, "tx_mult_col" },
183 { 0x80, "rx_total" },
184 { 0x81, "tx_total" },
185 { 0x82, "rx_discards" },
186 { 0x83, "tx_discards" },
187 };
188
189 static const struct ksz_dev_ops ksz8_dev_ops = {
190 .setup = ksz8_setup,
191 .get_port_addr = ksz8_get_port_addr,
192 .cfg_port_member = ksz8_cfg_port_member,
193 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
194 .port_setup = ksz8_port_setup,
195 .r_phy = ksz8_r_phy,
196 .w_phy = ksz8_w_phy,
197 .r_mib_cnt = ksz8_r_mib_cnt,
198 .r_mib_pkt = ksz8_r_mib_pkt,
199 .r_mib_stat64 = ksz88xx_r_mib_stats64,
200 .freeze_mib = ksz8_freeze_mib,
201 .port_init_cnt = ksz8_port_init_cnt,
202 .fdb_dump = ksz8_fdb_dump,
203 .fdb_add = ksz8_fdb_add,
204 .fdb_del = ksz8_fdb_del,
205 .mdb_add = ksz8_mdb_add,
206 .mdb_del = ksz8_mdb_del,
207 .vlan_filtering = ksz8_port_vlan_filtering,
208 .vlan_add = ksz8_port_vlan_add,
209 .vlan_del = ksz8_port_vlan_del,
210 .mirror_add = ksz8_port_mirror_add,
211 .mirror_del = ksz8_port_mirror_del,
212 .get_caps = ksz8_get_caps,
213 .config_cpu_port = ksz8_config_cpu_port,
214 .enable_stp_addr = ksz8_enable_stp_addr,
215 .reset = ksz8_reset_switch,
216 .init = ksz8_switch_init,
217 .exit = ksz8_switch_exit,
218 .change_mtu = ksz8_change_mtu,
219 };
220
221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
222 unsigned int mode,
223 phy_interface_t interface,
224 struct phy_device *phydev, int speed,
225 int duplex, bool tx_pause,
226 bool rx_pause);
227
228 static const struct ksz_dev_ops ksz9477_dev_ops = {
229 .setup = ksz9477_setup,
230 .get_port_addr = ksz9477_get_port_addr,
231 .cfg_port_member = ksz9477_cfg_port_member,
232 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
233 .port_setup = ksz9477_port_setup,
234 .set_ageing_time = ksz9477_set_ageing_time,
235 .r_phy = ksz9477_r_phy,
236 .w_phy = ksz9477_w_phy,
237 .r_mib_cnt = ksz9477_r_mib_cnt,
238 .r_mib_pkt = ksz9477_r_mib_pkt,
239 .r_mib_stat64 = ksz_r_mib_stats64,
240 .freeze_mib = ksz9477_freeze_mib,
241 .port_init_cnt = ksz9477_port_init_cnt,
242 .vlan_filtering = ksz9477_port_vlan_filtering,
243 .vlan_add = ksz9477_port_vlan_add,
244 .vlan_del = ksz9477_port_vlan_del,
245 .mirror_add = ksz9477_port_mirror_add,
246 .mirror_del = ksz9477_port_mirror_del,
247 .get_caps = ksz9477_get_caps,
248 .fdb_dump = ksz9477_fdb_dump,
249 .fdb_add = ksz9477_fdb_add,
250 .fdb_del = ksz9477_fdb_del,
251 .mdb_add = ksz9477_mdb_add,
252 .mdb_del = ksz9477_mdb_del,
253 .change_mtu = ksz9477_change_mtu,
254 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
255 .config_cpu_port = ksz9477_config_cpu_port,
256 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
257 .enable_stp_addr = ksz9477_enable_stp_addr,
258 .reset = ksz9477_reset_switch,
259 .init = ksz9477_switch_init,
260 .exit = ksz9477_switch_exit,
261 };
262
263 static const struct ksz_dev_ops lan937x_dev_ops = {
264 .setup = lan937x_setup,
265 .teardown = lan937x_teardown,
266 .get_port_addr = ksz9477_get_port_addr,
267 .cfg_port_member = ksz9477_cfg_port_member,
268 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
269 .port_setup = lan937x_port_setup,
270 .set_ageing_time = lan937x_set_ageing_time,
271 .r_phy = lan937x_r_phy,
272 .w_phy = lan937x_w_phy,
273 .r_mib_cnt = ksz9477_r_mib_cnt,
274 .r_mib_pkt = ksz9477_r_mib_pkt,
275 .r_mib_stat64 = ksz_r_mib_stats64,
276 .freeze_mib = ksz9477_freeze_mib,
277 .port_init_cnt = ksz9477_port_init_cnt,
278 .vlan_filtering = ksz9477_port_vlan_filtering,
279 .vlan_add = ksz9477_port_vlan_add,
280 .vlan_del = ksz9477_port_vlan_del,
281 .mirror_add = ksz9477_port_mirror_add,
282 .mirror_del = ksz9477_port_mirror_del,
283 .get_caps = lan937x_phylink_get_caps,
284 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
285 .fdb_dump = ksz9477_fdb_dump,
286 .fdb_add = ksz9477_fdb_add,
287 .fdb_del = ksz9477_fdb_del,
288 .mdb_add = ksz9477_mdb_add,
289 .mdb_del = ksz9477_mdb_del,
290 .change_mtu = lan937x_change_mtu,
291 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
292 .config_cpu_port = lan937x_config_cpu_port,
293 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
294 .enable_stp_addr = ksz9477_enable_stp_addr,
295 .reset = lan937x_reset_switch,
296 .init = lan937x_switch_init,
297 .exit = lan937x_switch_exit,
298 };
299
300 static const u16 ksz8795_regs[] = {
301 [REG_IND_CTRL_0] = 0x6E,
302 [REG_IND_DATA_8] = 0x70,
303 [REG_IND_DATA_CHECK] = 0x72,
304 [REG_IND_DATA_HI] = 0x71,
305 [REG_IND_DATA_LO] = 0x75,
306 [REG_IND_MIB_CHECK] = 0x74,
307 [REG_IND_BYTE] = 0xA0,
308 [P_FORCE_CTRL] = 0x0C,
309 [P_LINK_STATUS] = 0x0E,
310 [P_LOCAL_CTRL] = 0x07,
311 [P_NEG_RESTART_CTRL] = 0x0D,
312 [P_REMOTE_STATUS] = 0x08,
313 [P_SPEED_STATUS] = 0x09,
314 [S_TAIL_TAG_CTRL] = 0x0C,
315 [P_STP_CTRL] = 0x02,
316 [S_START_CTRL] = 0x01,
317 [S_BROADCAST_CTRL] = 0x06,
318 [S_MULTICAST_CTRL] = 0x04,
319 [P_XMII_CTRL_0] = 0x06,
320 [P_XMII_CTRL_1] = 0x06,
321 };
322
323 static const u32 ksz8795_masks[] = {
324 [PORT_802_1P_REMAPPING] = BIT(7),
325 [SW_TAIL_TAG_ENABLE] = BIT(1),
326 [MIB_COUNTER_OVERFLOW] = BIT(6),
327 [MIB_COUNTER_VALID] = BIT(5),
328 [VLAN_TABLE_FID] = GENMASK(6, 0),
329 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
330 [VLAN_TABLE_VALID] = BIT(12),
331 [STATIC_MAC_TABLE_VALID] = BIT(21),
332 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
334 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
335 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
336 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
337 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
338 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
339 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
340 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
342 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
343 [P_MII_TX_FLOW_CTRL] = BIT(5),
344 [P_MII_RX_FLOW_CTRL] = BIT(5),
345 };
346
347 static const u8 ksz8795_xmii_ctrl0[] = {
348 [P_MII_100MBIT] = 0,
349 [P_MII_10MBIT] = 1,
350 [P_MII_FULL_DUPLEX] = 0,
351 [P_MII_HALF_DUPLEX] = 1,
352 };
353
354 static const u8 ksz8795_xmii_ctrl1[] = {
355 [P_RGMII_SEL] = 3,
356 [P_GMII_SEL] = 2,
357 [P_RMII_SEL] = 1,
358 [P_MII_SEL] = 0,
359 [P_GMII_1GBIT] = 1,
360 [P_GMII_NOT_1GBIT] = 0,
361 };
362
363 static const u8 ksz8795_shifts[] = {
364 [VLAN_TABLE_MEMBERSHIP_S] = 7,
365 [VLAN_TABLE] = 16,
366 [STATIC_MAC_FWD_PORTS] = 16,
367 [STATIC_MAC_FID] = 24,
368 [DYNAMIC_MAC_ENTRIES_H] = 3,
369 [DYNAMIC_MAC_ENTRIES] = 29,
370 [DYNAMIC_MAC_FID] = 16,
371 [DYNAMIC_MAC_TIMESTAMP] = 27,
372 [DYNAMIC_MAC_SRC_PORT] = 24,
373 };
374
375 static const u16 ksz8863_regs[] = {
376 [REG_IND_CTRL_0] = 0x79,
377 [REG_IND_DATA_8] = 0x7B,
378 [REG_IND_DATA_CHECK] = 0x7B,
379 [REG_IND_DATA_HI] = 0x7C,
380 [REG_IND_DATA_LO] = 0x80,
381 [REG_IND_MIB_CHECK] = 0x80,
382 [P_FORCE_CTRL] = 0x0C,
383 [P_LINK_STATUS] = 0x0E,
384 [P_LOCAL_CTRL] = 0x0C,
385 [P_NEG_RESTART_CTRL] = 0x0D,
386 [P_REMOTE_STATUS] = 0x0E,
387 [P_SPEED_STATUS] = 0x0F,
388 [S_TAIL_TAG_CTRL] = 0x03,
389 [P_STP_CTRL] = 0x02,
390 [S_START_CTRL] = 0x01,
391 [S_BROADCAST_CTRL] = 0x06,
392 [S_MULTICAST_CTRL] = 0x04,
393 };
394
395 static const u32 ksz8863_masks[] = {
396 [PORT_802_1P_REMAPPING] = BIT(3),
397 [SW_TAIL_TAG_ENABLE] = BIT(6),
398 [MIB_COUNTER_OVERFLOW] = BIT(7),
399 [MIB_COUNTER_VALID] = BIT(6),
400 [VLAN_TABLE_FID] = GENMASK(15, 12),
401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
402 [VLAN_TABLE_VALID] = BIT(19),
403 [STATIC_MAC_TABLE_VALID] = BIT(19),
404 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
405 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
415 };
416
417 static u8 ksz8863_shifts[] = {
418 [VLAN_TABLE_MEMBERSHIP_S] = 16,
419 [STATIC_MAC_FWD_PORTS] = 16,
420 [STATIC_MAC_FID] = 22,
421 [DYNAMIC_MAC_ENTRIES_H] = 8,
422 [DYNAMIC_MAC_ENTRIES] = 24,
423 [DYNAMIC_MAC_FID] = 16,
424 [DYNAMIC_MAC_TIMESTAMP] = 22,
425 [DYNAMIC_MAC_SRC_PORT] = 20,
426 };
427
428 static const u16 ksz9477_regs[] = {
429 [P_STP_CTRL] = 0x0B04,
430 [S_START_CTRL] = 0x0300,
431 [S_BROADCAST_CTRL] = 0x0332,
432 [S_MULTICAST_CTRL] = 0x0331,
433 [P_XMII_CTRL_0] = 0x0300,
434 [P_XMII_CTRL_1] = 0x0301,
435 };
436
437 static const u32 ksz9477_masks[] = {
438 [ALU_STAT_WRITE] = 0,
439 [ALU_STAT_READ] = 1,
440 [P_MII_TX_FLOW_CTRL] = BIT(5),
441 [P_MII_RX_FLOW_CTRL] = BIT(3),
442 };
443
444 static const u8 ksz9477_shifts[] = {
445 [ALU_STAT_INDEX] = 16,
446 };
447
448 static const u8 ksz9477_xmii_ctrl0[] = {
449 [P_MII_100MBIT] = 1,
450 [P_MII_10MBIT] = 0,
451 [P_MII_FULL_DUPLEX] = 1,
452 [P_MII_HALF_DUPLEX] = 0,
453 };
454
455 static const u8 ksz9477_xmii_ctrl1[] = {
456 [P_RGMII_SEL] = 0,
457 [P_RMII_SEL] = 1,
458 [P_GMII_SEL] = 2,
459 [P_MII_SEL] = 3,
460 [P_GMII_1GBIT] = 0,
461 [P_GMII_NOT_1GBIT] = 1,
462 };
463
464 static const u32 lan937x_masks[] = {
465 [ALU_STAT_WRITE] = 1,
466 [ALU_STAT_READ] = 2,
467 [P_MII_TX_FLOW_CTRL] = BIT(5),
468 [P_MII_RX_FLOW_CTRL] = BIT(3),
469 };
470
471 static const u8 lan937x_shifts[] = {
472 [ALU_STAT_INDEX] = 8,
473 };
474
475 static const struct regmap_range ksz8563_valid_regs[] = {
476 regmap_reg_range(0x0000, 0x0003),
477 regmap_reg_range(0x0006, 0x0006),
478 regmap_reg_range(0x000f, 0x001f),
479 regmap_reg_range(0x0100, 0x0100),
480 regmap_reg_range(0x0104, 0x0107),
481 regmap_reg_range(0x010d, 0x010d),
482 regmap_reg_range(0x0110, 0x0113),
483 regmap_reg_range(0x0120, 0x012b),
484 regmap_reg_range(0x0201, 0x0201),
485 regmap_reg_range(0x0210, 0x0213),
486 regmap_reg_range(0x0300, 0x0300),
487 regmap_reg_range(0x0302, 0x031b),
488 regmap_reg_range(0x0320, 0x032b),
489 regmap_reg_range(0x0330, 0x0336),
490 regmap_reg_range(0x0338, 0x033e),
491 regmap_reg_range(0x0340, 0x035f),
492 regmap_reg_range(0x0370, 0x0370),
493 regmap_reg_range(0x0378, 0x0378),
494 regmap_reg_range(0x037c, 0x037d),
495 regmap_reg_range(0x0390, 0x0393),
496 regmap_reg_range(0x0400, 0x040e),
497 regmap_reg_range(0x0410, 0x042f),
498 regmap_reg_range(0x0500, 0x0519),
499 regmap_reg_range(0x0520, 0x054b),
500 regmap_reg_range(0x0550, 0x05b3),
501
502 /* port 1 */
503 regmap_reg_range(0x1000, 0x1001),
504 regmap_reg_range(0x1004, 0x100b),
505 regmap_reg_range(0x1013, 0x1013),
506 regmap_reg_range(0x1017, 0x1017),
507 regmap_reg_range(0x101b, 0x101b),
508 regmap_reg_range(0x101f, 0x1021),
509 regmap_reg_range(0x1030, 0x1030),
510 regmap_reg_range(0x1100, 0x1111),
511 regmap_reg_range(0x111a, 0x111d),
512 regmap_reg_range(0x1122, 0x1127),
513 regmap_reg_range(0x112a, 0x112b),
514 regmap_reg_range(0x1136, 0x1139),
515 regmap_reg_range(0x113e, 0x113f),
516 regmap_reg_range(0x1400, 0x1401),
517 regmap_reg_range(0x1403, 0x1403),
518 regmap_reg_range(0x1410, 0x1417),
519 regmap_reg_range(0x1420, 0x1423),
520 regmap_reg_range(0x1500, 0x1507),
521 regmap_reg_range(0x1600, 0x1612),
522 regmap_reg_range(0x1800, 0x180f),
523 regmap_reg_range(0x1900, 0x1907),
524 regmap_reg_range(0x1914, 0x191b),
525 regmap_reg_range(0x1a00, 0x1a03),
526 regmap_reg_range(0x1a04, 0x1a08),
527 regmap_reg_range(0x1b00, 0x1b01),
528 regmap_reg_range(0x1b04, 0x1b04),
529 regmap_reg_range(0x1c00, 0x1c05),
530 regmap_reg_range(0x1c08, 0x1c1b),
531
532 /* port 2 */
533 regmap_reg_range(0x2000, 0x2001),
534 regmap_reg_range(0x2004, 0x200b),
535 regmap_reg_range(0x2013, 0x2013),
536 regmap_reg_range(0x2017, 0x2017),
537 regmap_reg_range(0x201b, 0x201b),
538 regmap_reg_range(0x201f, 0x2021),
539 regmap_reg_range(0x2030, 0x2030),
540 regmap_reg_range(0x2100, 0x2111),
541 regmap_reg_range(0x211a, 0x211d),
542 regmap_reg_range(0x2122, 0x2127),
543 regmap_reg_range(0x212a, 0x212b),
544 regmap_reg_range(0x2136, 0x2139),
545 regmap_reg_range(0x213e, 0x213f),
546 regmap_reg_range(0x2400, 0x2401),
547 regmap_reg_range(0x2403, 0x2403),
548 regmap_reg_range(0x2410, 0x2417),
549 regmap_reg_range(0x2420, 0x2423),
550 regmap_reg_range(0x2500, 0x2507),
551 regmap_reg_range(0x2600, 0x2612),
552 regmap_reg_range(0x2800, 0x280f),
553 regmap_reg_range(0x2900, 0x2907),
554 regmap_reg_range(0x2914, 0x291b),
555 regmap_reg_range(0x2a00, 0x2a03),
556 regmap_reg_range(0x2a04, 0x2a08),
557 regmap_reg_range(0x2b00, 0x2b01),
558 regmap_reg_range(0x2b04, 0x2b04),
559 regmap_reg_range(0x2c00, 0x2c05),
560 regmap_reg_range(0x2c08, 0x2c1b),
561
562 /* port 3 */
563 regmap_reg_range(0x3000, 0x3001),
564 regmap_reg_range(0x3004, 0x300b),
565 regmap_reg_range(0x3013, 0x3013),
566 regmap_reg_range(0x3017, 0x3017),
567 regmap_reg_range(0x301b, 0x301b),
568 regmap_reg_range(0x301f, 0x3021),
569 regmap_reg_range(0x3030, 0x3030),
570 regmap_reg_range(0x3300, 0x3301),
571 regmap_reg_range(0x3303, 0x3303),
572 regmap_reg_range(0x3400, 0x3401),
573 regmap_reg_range(0x3403, 0x3403),
574 regmap_reg_range(0x3410, 0x3417),
575 regmap_reg_range(0x3420, 0x3423),
576 regmap_reg_range(0x3500, 0x3507),
577 regmap_reg_range(0x3600, 0x3612),
578 regmap_reg_range(0x3800, 0x380f),
579 regmap_reg_range(0x3900, 0x3907),
580 regmap_reg_range(0x3914, 0x391b),
581 regmap_reg_range(0x3a00, 0x3a03),
582 regmap_reg_range(0x3a04, 0x3a08),
583 regmap_reg_range(0x3b00, 0x3b01),
584 regmap_reg_range(0x3b04, 0x3b04),
585 regmap_reg_range(0x3c00, 0x3c05),
586 regmap_reg_range(0x3c08, 0x3c1b),
587 };
588
589 static const struct regmap_access_table ksz8563_register_set = {
590 .yes_ranges = ksz8563_valid_regs,
591 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
592 };
593
594 static const struct regmap_range ksz9477_valid_regs[] = {
595 regmap_reg_range(0x0000, 0x0003),
596 regmap_reg_range(0x0006, 0x0006),
597 regmap_reg_range(0x0010, 0x001f),
598 regmap_reg_range(0x0100, 0x0100),
599 regmap_reg_range(0x0103, 0x0107),
600 regmap_reg_range(0x010d, 0x010d),
601 regmap_reg_range(0x0110, 0x0113),
602 regmap_reg_range(0x0120, 0x012b),
603 regmap_reg_range(0x0201, 0x0201),
604 regmap_reg_range(0x0210, 0x0213),
605 regmap_reg_range(0x0300, 0x0300),
606 regmap_reg_range(0x0302, 0x031b),
607 regmap_reg_range(0x0320, 0x032b),
608 regmap_reg_range(0x0330, 0x0336),
609 regmap_reg_range(0x0338, 0x033b),
610 regmap_reg_range(0x033e, 0x033e),
611 regmap_reg_range(0x0340, 0x035f),
612 regmap_reg_range(0x0370, 0x0370),
613 regmap_reg_range(0x0378, 0x0378),
614 regmap_reg_range(0x037c, 0x037d),
615 regmap_reg_range(0x0390, 0x0393),
616 regmap_reg_range(0x0400, 0x040e),
617 regmap_reg_range(0x0410, 0x042f),
618 regmap_reg_range(0x0444, 0x044b),
619 regmap_reg_range(0x0450, 0x046f),
620 regmap_reg_range(0x0500, 0x0519),
621 regmap_reg_range(0x0520, 0x054b),
622 regmap_reg_range(0x0550, 0x05b3),
623 regmap_reg_range(0x0604, 0x060b),
624 regmap_reg_range(0x0610, 0x0612),
625 regmap_reg_range(0x0614, 0x062c),
626 regmap_reg_range(0x0640, 0x0645),
627 regmap_reg_range(0x0648, 0x064d),
628
629 /* port 1 */
630 regmap_reg_range(0x1000, 0x1001),
631 regmap_reg_range(0x1013, 0x1013),
632 regmap_reg_range(0x1017, 0x1017),
633 regmap_reg_range(0x101b, 0x101b),
634 regmap_reg_range(0x101f, 0x1020),
635 regmap_reg_range(0x1030, 0x1030),
636 regmap_reg_range(0x1100, 0x1115),
637 regmap_reg_range(0x111a, 0x111f),
638 regmap_reg_range(0x1120, 0x112b),
639 regmap_reg_range(0x1134, 0x113b),
640 regmap_reg_range(0x113c, 0x113f),
641 regmap_reg_range(0x1400, 0x1401),
642 regmap_reg_range(0x1403, 0x1403),
643 regmap_reg_range(0x1410, 0x1417),
644 regmap_reg_range(0x1420, 0x1423),
645 regmap_reg_range(0x1500, 0x1507),
646 regmap_reg_range(0x1600, 0x1613),
647 regmap_reg_range(0x1800, 0x180f),
648 regmap_reg_range(0x1820, 0x1827),
649 regmap_reg_range(0x1830, 0x1837),
650 regmap_reg_range(0x1840, 0x184b),
651 regmap_reg_range(0x1900, 0x1907),
652 regmap_reg_range(0x1914, 0x191b),
653 regmap_reg_range(0x1920, 0x1920),
654 regmap_reg_range(0x1923, 0x1927),
655 regmap_reg_range(0x1a00, 0x1a03),
656 regmap_reg_range(0x1a04, 0x1a07),
657 regmap_reg_range(0x1b00, 0x1b01),
658 regmap_reg_range(0x1b04, 0x1b04),
659 regmap_reg_range(0x1c00, 0x1c05),
660 regmap_reg_range(0x1c08, 0x1c1b),
661
662 /* port 2 */
663 regmap_reg_range(0x2000, 0x2001),
664 regmap_reg_range(0x2013, 0x2013),
665 regmap_reg_range(0x2017, 0x2017),
666 regmap_reg_range(0x201b, 0x201b),
667 regmap_reg_range(0x201f, 0x2020),
668 regmap_reg_range(0x2030, 0x2030),
669 regmap_reg_range(0x2100, 0x2115),
670 regmap_reg_range(0x211a, 0x211f),
671 regmap_reg_range(0x2120, 0x212b),
672 regmap_reg_range(0x2134, 0x213b),
673 regmap_reg_range(0x213c, 0x213f),
674 regmap_reg_range(0x2400, 0x2401),
675 regmap_reg_range(0x2403, 0x2403),
676 regmap_reg_range(0x2410, 0x2417),
677 regmap_reg_range(0x2420, 0x2423),
678 regmap_reg_range(0x2500, 0x2507),
679 regmap_reg_range(0x2600, 0x2613),
680 regmap_reg_range(0x2800, 0x280f),
681 regmap_reg_range(0x2820, 0x2827),
682 regmap_reg_range(0x2830, 0x2837),
683 regmap_reg_range(0x2840, 0x284b),
684 regmap_reg_range(0x2900, 0x2907),
685 regmap_reg_range(0x2914, 0x291b),
686 regmap_reg_range(0x2920, 0x2920),
687 regmap_reg_range(0x2923, 0x2927),
688 regmap_reg_range(0x2a00, 0x2a03),
689 regmap_reg_range(0x2a04, 0x2a07),
690 regmap_reg_range(0x2b00, 0x2b01),
691 regmap_reg_range(0x2b04, 0x2b04),
692 regmap_reg_range(0x2c00, 0x2c05),
693 regmap_reg_range(0x2c08, 0x2c1b),
694
695 /* port 3 */
696 regmap_reg_range(0x3000, 0x3001),
697 regmap_reg_range(0x3013, 0x3013),
698 regmap_reg_range(0x3017, 0x3017),
699 regmap_reg_range(0x301b, 0x301b),
700 regmap_reg_range(0x301f, 0x3020),
701 regmap_reg_range(0x3030, 0x3030),
702 regmap_reg_range(0x3100, 0x3115),
703 regmap_reg_range(0x311a, 0x311f),
704 regmap_reg_range(0x3120, 0x312b),
705 regmap_reg_range(0x3134, 0x313b),
706 regmap_reg_range(0x313c, 0x313f),
707 regmap_reg_range(0x3400, 0x3401),
708 regmap_reg_range(0x3403, 0x3403),
709 regmap_reg_range(0x3410, 0x3417),
710 regmap_reg_range(0x3420, 0x3423),
711 regmap_reg_range(0x3500, 0x3507),
712 regmap_reg_range(0x3600, 0x3613),
713 regmap_reg_range(0x3800, 0x380f),
714 regmap_reg_range(0x3820, 0x3827),
715 regmap_reg_range(0x3830, 0x3837),
716 regmap_reg_range(0x3840, 0x384b),
717 regmap_reg_range(0x3900, 0x3907),
718 regmap_reg_range(0x3914, 0x391b),
719 regmap_reg_range(0x3920, 0x3920),
720 regmap_reg_range(0x3923, 0x3927),
721 regmap_reg_range(0x3a00, 0x3a03),
722 regmap_reg_range(0x3a04, 0x3a07),
723 regmap_reg_range(0x3b00, 0x3b01),
724 regmap_reg_range(0x3b04, 0x3b04),
725 regmap_reg_range(0x3c00, 0x3c05),
726 regmap_reg_range(0x3c08, 0x3c1b),
727
728 /* port 4 */
729 regmap_reg_range(0x4000, 0x4001),
730 regmap_reg_range(0x4013, 0x4013),
731 regmap_reg_range(0x4017, 0x4017),
732 regmap_reg_range(0x401b, 0x401b),
733 regmap_reg_range(0x401f, 0x4020),
734 regmap_reg_range(0x4030, 0x4030),
735 regmap_reg_range(0x4100, 0x4115),
736 regmap_reg_range(0x411a, 0x411f),
737 regmap_reg_range(0x4120, 0x412b),
738 regmap_reg_range(0x4134, 0x413b),
739 regmap_reg_range(0x413c, 0x413f),
740 regmap_reg_range(0x4400, 0x4401),
741 regmap_reg_range(0x4403, 0x4403),
742 regmap_reg_range(0x4410, 0x4417),
743 regmap_reg_range(0x4420, 0x4423),
744 regmap_reg_range(0x4500, 0x4507),
745 regmap_reg_range(0x4600, 0x4613),
746 regmap_reg_range(0x4800, 0x480f),
747 regmap_reg_range(0x4820, 0x4827),
748 regmap_reg_range(0x4830, 0x4837),
749 regmap_reg_range(0x4840, 0x484b),
750 regmap_reg_range(0x4900, 0x4907),
751 regmap_reg_range(0x4914, 0x491b),
752 regmap_reg_range(0x4920, 0x4920),
753 regmap_reg_range(0x4923, 0x4927),
754 regmap_reg_range(0x4a00, 0x4a03),
755 regmap_reg_range(0x4a04, 0x4a07),
756 regmap_reg_range(0x4b00, 0x4b01),
757 regmap_reg_range(0x4b04, 0x4b04),
758 regmap_reg_range(0x4c00, 0x4c05),
759 regmap_reg_range(0x4c08, 0x4c1b),
760
761 /* port 5 */
762 regmap_reg_range(0x5000, 0x5001),
763 regmap_reg_range(0x5013, 0x5013),
764 regmap_reg_range(0x5017, 0x5017),
765 regmap_reg_range(0x501b, 0x501b),
766 regmap_reg_range(0x501f, 0x5020),
767 regmap_reg_range(0x5030, 0x5030),
768 regmap_reg_range(0x5100, 0x5115),
769 regmap_reg_range(0x511a, 0x511f),
770 regmap_reg_range(0x5120, 0x512b),
771 regmap_reg_range(0x5134, 0x513b),
772 regmap_reg_range(0x513c, 0x513f),
773 regmap_reg_range(0x5400, 0x5401),
774 regmap_reg_range(0x5403, 0x5403),
775 regmap_reg_range(0x5410, 0x5417),
776 regmap_reg_range(0x5420, 0x5423),
777 regmap_reg_range(0x5500, 0x5507),
778 regmap_reg_range(0x5600, 0x5613),
779 regmap_reg_range(0x5800, 0x580f),
780 regmap_reg_range(0x5820, 0x5827),
781 regmap_reg_range(0x5830, 0x5837),
782 regmap_reg_range(0x5840, 0x584b),
783 regmap_reg_range(0x5900, 0x5907),
784 regmap_reg_range(0x5914, 0x591b),
785 regmap_reg_range(0x5920, 0x5920),
786 regmap_reg_range(0x5923, 0x5927),
787 regmap_reg_range(0x5a00, 0x5a03),
788 regmap_reg_range(0x5a04, 0x5a07),
789 regmap_reg_range(0x5b00, 0x5b01),
790 regmap_reg_range(0x5b04, 0x5b04),
791 regmap_reg_range(0x5c00, 0x5c05),
792 regmap_reg_range(0x5c08, 0x5c1b),
793
794 /* port 6 */
795 regmap_reg_range(0x6000, 0x6001),
796 regmap_reg_range(0x6013, 0x6013),
797 regmap_reg_range(0x6017, 0x6017),
798 regmap_reg_range(0x601b, 0x601b),
799 regmap_reg_range(0x601f, 0x6020),
800 regmap_reg_range(0x6030, 0x6030),
801 regmap_reg_range(0x6300, 0x6301),
802 regmap_reg_range(0x6400, 0x6401),
803 regmap_reg_range(0x6403, 0x6403),
804 regmap_reg_range(0x6410, 0x6417),
805 regmap_reg_range(0x6420, 0x6423),
806 regmap_reg_range(0x6500, 0x6507),
807 regmap_reg_range(0x6600, 0x6613),
808 regmap_reg_range(0x6800, 0x680f),
809 regmap_reg_range(0x6820, 0x6827),
810 regmap_reg_range(0x6830, 0x6837),
811 regmap_reg_range(0x6840, 0x684b),
812 regmap_reg_range(0x6900, 0x6907),
813 regmap_reg_range(0x6914, 0x691b),
814 regmap_reg_range(0x6920, 0x6920),
815 regmap_reg_range(0x6923, 0x6927),
816 regmap_reg_range(0x6a00, 0x6a03),
817 regmap_reg_range(0x6a04, 0x6a07),
818 regmap_reg_range(0x6b00, 0x6b01),
819 regmap_reg_range(0x6b04, 0x6b04),
820 regmap_reg_range(0x6c00, 0x6c05),
821 regmap_reg_range(0x6c08, 0x6c1b),
822
823 /* port 7 */
824 regmap_reg_range(0x7000, 0x7001),
825 regmap_reg_range(0x7013, 0x7013),
826 regmap_reg_range(0x7017, 0x7017),
827 regmap_reg_range(0x701b, 0x701b),
828 regmap_reg_range(0x701f, 0x7020),
829 regmap_reg_range(0x7030, 0x7030),
830 regmap_reg_range(0x7200, 0x7203),
831 regmap_reg_range(0x7206, 0x7207),
832 regmap_reg_range(0x7300, 0x7301),
833 regmap_reg_range(0x7400, 0x7401),
834 regmap_reg_range(0x7403, 0x7403),
835 regmap_reg_range(0x7410, 0x7417),
836 regmap_reg_range(0x7420, 0x7423),
837 regmap_reg_range(0x7500, 0x7507),
838 regmap_reg_range(0x7600, 0x7613),
839 regmap_reg_range(0x7800, 0x780f),
840 regmap_reg_range(0x7820, 0x7827),
841 regmap_reg_range(0x7830, 0x7837),
842 regmap_reg_range(0x7840, 0x784b),
843 regmap_reg_range(0x7900, 0x7907),
844 regmap_reg_range(0x7914, 0x791b),
845 regmap_reg_range(0x7920, 0x7920),
846 regmap_reg_range(0x7923, 0x7927),
847 regmap_reg_range(0x7a00, 0x7a03),
848 regmap_reg_range(0x7a04, 0x7a07),
849 regmap_reg_range(0x7b00, 0x7b01),
850 regmap_reg_range(0x7b04, 0x7b04),
851 regmap_reg_range(0x7c00, 0x7c05),
852 regmap_reg_range(0x7c08, 0x7c1b),
853 };
854
855 static const struct regmap_access_table ksz9477_register_set = {
856 .yes_ranges = ksz9477_valid_regs,
857 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
858 };
859
860 static const struct regmap_range ksz9896_valid_regs[] = {
861 regmap_reg_range(0x0000, 0x0003),
862 regmap_reg_range(0x0006, 0x0006),
863 regmap_reg_range(0x0010, 0x001f),
864 regmap_reg_range(0x0100, 0x0100),
865 regmap_reg_range(0x0103, 0x0107),
866 regmap_reg_range(0x010d, 0x010d),
867 regmap_reg_range(0x0110, 0x0113),
868 regmap_reg_range(0x0120, 0x0127),
869 regmap_reg_range(0x0201, 0x0201),
870 regmap_reg_range(0x0210, 0x0213),
871 regmap_reg_range(0x0300, 0x0300),
872 regmap_reg_range(0x0302, 0x030b),
873 regmap_reg_range(0x0310, 0x031b),
874 regmap_reg_range(0x0320, 0x032b),
875 regmap_reg_range(0x0330, 0x0336),
876 regmap_reg_range(0x0338, 0x033b),
877 regmap_reg_range(0x033e, 0x033e),
878 regmap_reg_range(0x0340, 0x035f),
879 regmap_reg_range(0x0370, 0x0370),
880 regmap_reg_range(0x0378, 0x0378),
881 regmap_reg_range(0x037c, 0x037d),
882 regmap_reg_range(0x0390, 0x0393),
883 regmap_reg_range(0x0400, 0x040e),
884 regmap_reg_range(0x0410, 0x042f),
885
886 /* port 1 */
887 regmap_reg_range(0x1000, 0x1001),
888 regmap_reg_range(0x1013, 0x1013),
889 regmap_reg_range(0x1017, 0x1017),
890 regmap_reg_range(0x101b, 0x101b),
891 regmap_reg_range(0x101f, 0x1020),
892 regmap_reg_range(0x1030, 0x1030),
893 regmap_reg_range(0x1100, 0x1115),
894 regmap_reg_range(0x111a, 0x111f),
895 regmap_reg_range(0x1120, 0x112b),
896 regmap_reg_range(0x1134, 0x113b),
897 regmap_reg_range(0x113c, 0x113f),
898 regmap_reg_range(0x1400, 0x1401),
899 regmap_reg_range(0x1403, 0x1403),
900 regmap_reg_range(0x1410, 0x1417),
901 regmap_reg_range(0x1420, 0x1423),
902 regmap_reg_range(0x1500, 0x1507),
903 regmap_reg_range(0x1600, 0x1612),
904 regmap_reg_range(0x1800, 0x180f),
905 regmap_reg_range(0x1820, 0x1827),
906 regmap_reg_range(0x1830, 0x1837),
907 regmap_reg_range(0x1840, 0x184b),
908 regmap_reg_range(0x1900, 0x1907),
909 regmap_reg_range(0x1914, 0x1915),
910 regmap_reg_range(0x1a00, 0x1a03),
911 regmap_reg_range(0x1a04, 0x1a07),
912 regmap_reg_range(0x1b00, 0x1b01),
913 regmap_reg_range(0x1b04, 0x1b04),
914
915 /* port 2 */
916 regmap_reg_range(0x2000, 0x2001),
917 regmap_reg_range(0x2013, 0x2013),
918 regmap_reg_range(0x2017, 0x2017),
919 regmap_reg_range(0x201b, 0x201b),
920 regmap_reg_range(0x201f, 0x2020),
921 regmap_reg_range(0x2030, 0x2030),
922 regmap_reg_range(0x2100, 0x2115),
923 regmap_reg_range(0x211a, 0x211f),
924 regmap_reg_range(0x2120, 0x212b),
925 regmap_reg_range(0x2134, 0x213b),
926 regmap_reg_range(0x213c, 0x213f),
927 regmap_reg_range(0x2400, 0x2401),
928 regmap_reg_range(0x2403, 0x2403),
929 regmap_reg_range(0x2410, 0x2417),
930 regmap_reg_range(0x2420, 0x2423),
931 regmap_reg_range(0x2500, 0x2507),
932 regmap_reg_range(0x2600, 0x2612),
933 regmap_reg_range(0x2800, 0x280f),
934 regmap_reg_range(0x2820, 0x2827),
935 regmap_reg_range(0x2830, 0x2837),
936 regmap_reg_range(0x2840, 0x284b),
937 regmap_reg_range(0x2900, 0x2907),
938 regmap_reg_range(0x2914, 0x2915),
939 regmap_reg_range(0x2a00, 0x2a03),
940 regmap_reg_range(0x2a04, 0x2a07),
941 regmap_reg_range(0x2b00, 0x2b01),
942 regmap_reg_range(0x2b04, 0x2b04),
943
944 /* port 3 */
945 regmap_reg_range(0x3000, 0x3001),
946 regmap_reg_range(0x3013, 0x3013),
947 regmap_reg_range(0x3017, 0x3017),
948 regmap_reg_range(0x301b, 0x301b),
949 regmap_reg_range(0x301f, 0x3020),
950 regmap_reg_range(0x3030, 0x3030),
951 regmap_reg_range(0x3100, 0x3115),
952 regmap_reg_range(0x311a, 0x311f),
953 regmap_reg_range(0x3120, 0x312b),
954 regmap_reg_range(0x3134, 0x313b),
955 regmap_reg_range(0x313c, 0x313f),
956 regmap_reg_range(0x3400, 0x3401),
957 regmap_reg_range(0x3403, 0x3403),
958 regmap_reg_range(0x3410, 0x3417),
959 regmap_reg_range(0x3420, 0x3423),
960 regmap_reg_range(0x3500, 0x3507),
961 regmap_reg_range(0x3600, 0x3612),
962 regmap_reg_range(0x3800, 0x380f),
963 regmap_reg_range(0x3820, 0x3827),
964 regmap_reg_range(0x3830, 0x3837),
965 regmap_reg_range(0x3840, 0x384b),
966 regmap_reg_range(0x3900, 0x3907),
967 regmap_reg_range(0x3914, 0x3915),
968 regmap_reg_range(0x3a00, 0x3a03),
969 regmap_reg_range(0x3a04, 0x3a07),
970 regmap_reg_range(0x3b00, 0x3b01),
971 regmap_reg_range(0x3b04, 0x3b04),
972
973 /* port 4 */
974 regmap_reg_range(0x4000, 0x4001),
975 regmap_reg_range(0x4013, 0x4013),
976 regmap_reg_range(0x4017, 0x4017),
977 regmap_reg_range(0x401b, 0x401b),
978 regmap_reg_range(0x401f, 0x4020),
979 regmap_reg_range(0x4030, 0x4030),
980 regmap_reg_range(0x4100, 0x4115),
981 regmap_reg_range(0x411a, 0x411f),
982 regmap_reg_range(0x4120, 0x412b),
983 regmap_reg_range(0x4134, 0x413b),
984 regmap_reg_range(0x413c, 0x413f),
985 regmap_reg_range(0x4400, 0x4401),
986 regmap_reg_range(0x4403, 0x4403),
987 regmap_reg_range(0x4410, 0x4417),
988 regmap_reg_range(0x4420, 0x4423),
989 regmap_reg_range(0x4500, 0x4507),
990 regmap_reg_range(0x4600, 0x4612),
991 regmap_reg_range(0x4800, 0x480f),
992 regmap_reg_range(0x4820, 0x4827),
993 regmap_reg_range(0x4830, 0x4837),
994 regmap_reg_range(0x4840, 0x484b),
995 regmap_reg_range(0x4900, 0x4907),
996 regmap_reg_range(0x4914, 0x4915),
997 regmap_reg_range(0x4a00, 0x4a03),
998 regmap_reg_range(0x4a04, 0x4a07),
999 regmap_reg_range(0x4b00, 0x4b01),
1000 regmap_reg_range(0x4b04, 0x4b04),
1001
1002 /* port 5 */
1003 regmap_reg_range(0x5000, 0x5001),
1004 regmap_reg_range(0x5013, 0x5013),
1005 regmap_reg_range(0x5017, 0x5017),
1006 regmap_reg_range(0x501b, 0x501b),
1007 regmap_reg_range(0x501f, 0x5020),
1008 regmap_reg_range(0x5030, 0x5030),
1009 regmap_reg_range(0x5100, 0x5115),
1010 regmap_reg_range(0x511a, 0x511f),
1011 regmap_reg_range(0x5120, 0x512b),
1012 regmap_reg_range(0x5134, 0x513b),
1013 regmap_reg_range(0x513c, 0x513f),
1014 regmap_reg_range(0x5400, 0x5401),
1015 regmap_reg_range(0x5403, 0x5403),
1016 regmap_reg_range(0x5410, 0x5417),
1017 regmap_reg_range(0x5420, 0x5423),
1018 regmap_reg_range(0x5500, 0x5507),
1019 regmap_reg_range(0x5600, 0x5612),
1020 regmap_reg_range(0x5800, 0x580f),
1021 regmap_reg_range(0x5820, 0x5827),
1022 regmap_reg_range(0x5830, 0x5837),
1023 regmap_reg_range(0x5840, 0x584b),
1024 regmap_reg_range(0x5900, 0x5907),
1025 regmap_reg_range(0x5914, 0x5915),
1026 regmap_reg_range(0x5a00, 0x5a03),
1027 regmap_reg_range(0x5a04, 0x5a07),
1028 regmap_reg_range(0x5b00, 0x5b01),
1029 regmap_reg_range(0x5b04, 0x5b04),
1030
1031 /* port 6 */
1032 regmap_reg_range(0x6000, 0x6001),
1033 regmap_reg_range(0x6013, 0x6013),
1034 regmap_reg_range(0x6017, 0x6017),
1035 regmap_reg_range(0x601b, 0x601b),
1036 regmap_reg_range(0x601f, 0x6020),
1037 regmap_reg_range(0x6030, 0x6030),
1038 regmap_reg_range(0x6100, 0x6115),
1039 regmap_reg_range(0x611a, 0x611f),
1040 regmap_reg_range(0x6120, 0x612b),
1041 regmap_reg_range(0x6134, 0x613b),
1042 regmap_reg_range(0x613c, 0x613f),
1043 regmap_reg_range(0x6300, 0x6301),
1044 regmap_reg_range(0x6400, 0x6401),
1045 regmap_reg_range(0x6403, 0x6403),
1046 regmap_reg_range(0x6410, 0x6417),
1047 regmap_reg_range(0x6420, 0x6423),
1048 regmap_reg_range(0x6500, 0x6507),
1049 regmap_reg_range(0x6600, 0x6612),
1050 regmap_reg_range(0x6800, 0x680f),
1051 regmap_reg_range(0x6820, 0x6827),
1052 regmap_reg_range(0x6830, 0x6837),
1053 regmap_reg_range(0x6840, 0x684b),
1054 regmap_reg_range(0x6900, 0x6907),
1055 regmap_reg_range(0x6914, 0x6915),
1056 regmap_reg_range(0x6a00, 0x6a03),
1057 regmap_reg_range(0x6a04, 0x6a07),
1058 regmap_reg_range(0x6b00, 0x6b01),
1059 regmap_reg_range(0x6b04, 0x6b04),
1060 };
1061
1062 static const struct regmap_access_table ksz9896_register_set = {
1063 .yes_ranges = ksz9896_valid_regs,
1064 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1065 };
1066
1067 static const struct regmap_range ksz8873_valid_regs[] = {
1068 regmap_reg_range(0x00, 0x01),
1069 /* global control register */
1070 regmap_reg_range(0x02, 0x0f),
1071
1072 /* port registers */
1073 regmap_reg_range(0x10, 0x1d),
1074 regmap_reg_range(0x1e, 0x1f),
1075 regmap_reg_range(0x20, 0x2d),
1076 regmap_reg_range(0x2e, 0x2f),
1077 regmap_reg_range(0x30, 0x39),
1078 regmap_reg_range(0x3f, 0x3f),
1079
1080 /* advanced control registers */
1081 regmap_reg_range(0x60, 0x6f),
1082 regmap_reg_range(0x70, 0x75),
1083 regmap_reg_range(0x76, 0x78),
1084 regmap_reg_range(0x79, 0x7a),
1085 regmap_reg_range(0x7b, 0x83),
1086 regmap_reg_range(0x8e, 0x99),
1087 regmap_reg_range(0x9a, 0xa5),
1088 regmap_reg_range(0xa6, 0xa6),
1089 regmap_reg_range(0xa7, 0xaa),
1090 regmap_reg_range(0xab, 0xae),
1091 regmap_reg_range(0xaf, 0xba),
1092 regmap_reg_range(0xbb, 0xbc),
1093 regmap_reg_range(0xbd, 0xbd),
1094 regmap_reg_range(0xc0, 0xc0),
1095 regmap_reg_range(0xc2, 0xc2),
1096 regmap_reg_range(0xc3, 0xc3),
1097 regmap_reg_range(0xc4, 0xc4),
1098 regmap_reg_range(0xc6, 0xc6),
1099 };
1100
1101 static const struct regmap_access_table ksz8873_register_set = {
1102 .yes_ranges = ksz8873_valid_regs,
1103 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1104 };
1105
1106 const struct ksz_chip_data ksz_switch_chips[] = {
1107 [KSZ8563] = {
1108 .chip_id = KSZ8563_CHIP_ID,
1109 .dev_name = "KSZ8563",
1110 .num_vlans = 4096,
1111 .num_alus = 4096,
1112 .num_statics = 16,
1113 .cpu_ports = 0x07, /* can be configured as cpu port */
1114 .port_cnt = 3, /* total port count */
1115 .port_nirqs = 3,
1116 .num_tx_queues = 4,
1117 .tc_cbs_supported = true,
1118 .tc_ets_supported = true,
1119 .ops = &ksz9477_dev_ops,
1120 .mib_names = ksz9477_mib_names,
1121 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1122 .reg_mib_cnt = MIB_COUNTER_NUM,
1123 .regs = ksz9477_regs,
1124 .masks = ksz9477_masks,
1125 .shifts = ksz9477_shifts,
1126 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1127 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1128 .supports_mii = {false, false, true},
1129 .supports_rmii = {false, false, true},
1130 .supports_rgmii = {false, false, true},
1131 .internal_phy = {true, true, false},
1132 .gbit_capable = {false, false, true},
1133 .wr_table = &ksz8563_register_set,
1134 .rd_table = &ksz8563_register_set,
1135 },
1136
1137 [KSZ8795] = {
1138 .chip_id = KSZ8795_CHIP_ID,
1139 .dev_name = "KSZ8795",
1140 .num_vlans = 4096,
1141 .num_alus = 0,
1142 .num_statics = 8,
1143 .cpu_ports = 0x10, /* can be configured as cpu port */
1144 .port_cnt = 5, /* total cpu and user ports */
1145 .num_tx_queues = 4,
1146 .ops = &ksz8_dev_ops,
1147 .ksz87xx_eee_link_erratum = true,
1148 .mib_names = ksz9477_mib_names,
1149 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1150 .reg_mib_cnt = MIB_COUNTER_NUM,
1151 .regs = ksz8795_regs,
1152 .masks = ksz8795_masks,
1153 .shifts = ksz8795_shifts,
1154 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1155 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1156 .supports_mii = {false, false, false, false, true},
1157 .supports_rmii = {false, false, false, false, true},
1158 .supports_rgmii = {false, false, false, false, true},
1159 .internal_phy = {true, true, true, true, false},
1160 },
1161
1162 [KSZ8794] = {
1163 /* WARNING
1164 * =======
1165 * KSZ8794 is similar to KSZ8795, except the port map
1166 * contains a gap between external and CPU ports, the
1167 * port map is NOT continuous. The per-port register
1168 * map is shifted accordingly too, i.e. registers at
1169 * offset 0x40 are NOT used on KSZ8794 and they ARE
1170 * used on KSZ8795 for external port 3.
1171 * external cpu
1172 * KSZ8794 0,1,2 4
1173 * KSZ8795 0,1,2,3 4
1174 * KSZ8765 0,1,2,3 4
1175 * port_cnt is configured as 5, even though it is 4
1176 */
1177 .chip_id = KSZ8794_CHIP_ID,
1178 .dev_name = "KSZ8794",
1179 .num_vlans = 4096,
1180 .num_alus = 0,
1181 .num_statics = 8,
1182 .cpu_ports = 0x10, /* can be configured as cpu port */
1183 .port_cnt = 5, /* total cpu and user ports */
1184 .num_tx_queues = 4,
1185 .ops = &ksz8_dev_ops,
1186 .ksz87xx_eee_link_erratum = true,
1187 .mib_names = ksz9477_mib_names,
1188 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1189 .reg_mib_cnt = MIB_COUNTER_NUM,
1190 .regs = ksz8795_regs,
1191 .masks = ksz8795_masks,
1192 .shifts = ksz8795_shifts,
1193 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1194 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1195 .supports_mii = {false, false, false, false, true},
1196 .supports_rmii = {false, false, false, false, true},
1197 .supports_rgmii = {false, false, false, false, true},
1198 .internal_phy = {true, true, true, false, false},
1199 },
1200
1201 [KSZ8765] = {
1202 .chip_id = KSZ8765_CHIP_ID,
1203 .dev_name = "KSZ8765",
1204 .num_vlans = 4096,
1205 .num_alus = 0,
1206 .num_statics = 8,
1207 .cpu_ports = 0x10, /* can be configured as cpu port */
1208 .port_cnt = 5, /* total cpu and user ports */
1209 .num_tx_queues = 4,
1210 .ops = &ksz8_dev_ops,
1211 .ksz87xx_eee_link_erratum = true,
1212 .mib_names = ksz9477_mib_names,
1213 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1214 .reg_mib_cnt = MIB_COUNTER_NUM,
1215 .regs = ksz8795_regs,
1216 .masks = ksz8795_masks,
1217 .shifts = ksz8795_shifts,
1218 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1219 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1220 .supports_mii = {false, false, false, false, true},
1221 .supports_rmii = {false, false, false, false, true},
1222 .supports_rgmii = {false, false, false, false, true},
1223 .internal_phy = {true, true, true, true, false},
1224 },
1225
1226 [KSZ8830] = {
1227 .chip_id = KSZ8830_CHIP_ID,
1228 .dev_name = "KSZ8863/KSZ8873",
1229 .num_vlans = 16,
1230 .num_alus = 0,
1231 .num_statics = 8,
1232 .cpu_ports = 0x4, /* can be configured as cpu port */
1233 .port_cnt = 3,
1234 .num_tx_queues = 4,
1235 .ops = &ksz8_dev_ops,
1236 .mib_names = ksz88xx_mib_names,
1237 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1238 .reg_mib_cnt = MIB_COUNTER_NUM,
1239 .regs = ksz8863_regs,
1240 .masks = ksz8863_masks,
1241 .shifts = ksz8863_shifts,
1242 .supports_mii = {false, false, true},
1243 .supports_rmii = {false, false, true},
1244 .internal_phy = {true, true, false},
1245 .wr_table = &ksz8873_register_set,
1246 .rd_table = &ksz8873_register_set,
1247 },
1248
1249 [KSZ9477] = {
1250 .chip_id = KSZ9477_CHIP_ID,
1251 .dev_name = "KSZ9477",
1252 .num_vlans = 4096,
1253 .num_alus = 4096,
1254 .num_statics = 16,
1255 .cpu_ports = 0x7F, /* can be configured as cpu port */
1256 .port_cnt = 7, /* total physical port count */
1257 .port_nirqs = 4,
1258 .num_tx_queues = 4,
1259 .tc_cbs_supported = true,
1260 .tc_ets_supported = true,
1261 .ops = &ksz9477_dev_ops,
1262 .mib_names = ksz9477_mib_names,
1263 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1264 .reg_mib_cnt = MIB_COUNTER_NUM,
1265 .regs = ksz9477_regs,
1266 .masks = ksz9477_masks,
1267 .shifts = ksz9477_shifts,
1268 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1269 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1270 .supports_mii = {false, false, false, false,
1271 false, true, false},
1272 .supports_rmii = {false, false, false, false,
1273 false, true, false},
1274 .supports_rgmii = {false, false, false, false,
1275 false, true, false},
1276 .internal_phy = {true, true, true, true,
1277 true, false, false},
1278 .gbit_capable = {true, true, true, true, true, true, true},
1279 .wr_table = &ksz9477_register_set,
1280 .rd_table = &ksz9477_register_set,
1281 },
1282
1283 [KSZ9896] = {
1284 .chip_id = KSZ9896_CHIP_ID,
1285 .dev_name = "KSZ9896",
1286 .num_vlans = 4096,
1287 .num_alus = 4096,
1288 .num_statics = 16,
1289 .cpu_ports = 0x3F, /* can be configured as cpu port */
1290 .port_cnt = 6, /* total physical port count */
1291 .port_nirqs = 2,
1292 .num_tx_queues = 4,
1293 .ops = &ksz9477_dev_ops,
1294 .mib_names = ksz9477_mib_names,
1295 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1296 .reg_mib_cnt = MIB_COUNTER_NUM,
1297 .regs = ksz9477_regs,
1298 .masks = ksz9477_masks,
1299 .shifts = ksz9477_shifts,
1300 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1301 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1302 .supports_mii = {false, false, false, false,
1303 false, true},
1304 .supports_rmii = {false, false, false, false,
1305 false, true},
1306 .supports_rgmii = {false, false, false, false,
1307 false, true},
1308 .internal_phy = {true, true, true, true,
1309 true, false},
1310 .gbit_capable = {true, true, true, true, true, true},
1311 .wr_table = &ksz9896_register_set,
1312 .rd_table = &ksz9896_register_set,
1313 },
1314
1315 [KSZ9897] = {
1316 .chip_id = KSZ9897_CHIP_ID,
1317 .dev_name = "KSZ9897",
1318 .num_vlans = 4096,
1319 .num_alus = 4096,
1320 .num_statics = 16,
1321 .cpu_ports = 0x7F, /* can be configured as cpu port */
1322 .port_cnt = 7, /* total physical port count */
1323 .port_nirqs = 2,
1324 .num_tx_queues = 4,
1325 .ops = &ksz9477_dev_ops,
1326 .mib_names = ksz9477_mib_names,
1327 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1328 .reg_mib_cnt = MIB_COUNTER_NUM,
1329 .regs = ksz9477_regs,
1330 .masks = ksz9477_masks,
1331 .shifts = ksz9477_shifts,
1332 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1333 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1334 .supports_mii = {false, false, false, false,
1335 false, true, true},
1336 .supports_rmii = {false, false, false, false,
1337 false, true, true},
1338 .supports_rgmii = {false, false, false, false,
1339 false, true, true},
1340 .internal_phy = {true, true, true, true,
1341 true, false, false},
1342 .gbit_capable = {true, true, true, true, true, true, true},
1343 },
1344
1345 [KSZ9893] = {
1346 .chip_id = KSZ9893_CHIP_ID,
1347 .dev_name = "KSZ9893",
1348 .num_vlans = 4096,
1349 .num_alus = 4096,
1350 .num_statics = 16,
1351 .cpu_ports = 0x07, /* can be configured as cpu port */
1352 .port_cnt = 3, /* total port count */
1353 .port_nirqs = 2,
1354 .num_tx_queues = 4,
1355 .ops = &ksz9477_dev_ops,
1356 .mib_names = ksz9477_mib_names,
1357 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1358 .reg_mib_cnt = MIB_COUNTER_NUM,
1359 .regs = ksz9477_regs,
1360 .masks = ksz9477_masks,
1361 .shifts = ksz9477_shifts,
1362 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1363 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1364 .supports_mii = {false, false, true},
1365 .supports_rmii = {false, false, true},
1366 .supports_rgmii = {false, false, true},
1367 .internal_phy = {true, true, false},
1368 .gbit_capable = {true, true, true},
1369 },
1370
1371 [KSZ9563] = {
1372 .chip_id = KSZ9563_CHIP_ID,
1373 .dev_name = "KSZ9563",
1374 .num_vlans = 4096,
1375 .num_alus = 4096,
1376 .num_statics = 16,
1377 .cpu_ports = 0x07, /* can be configured as cpu port */
1378 .port_cnt = 3, /* total port count */
1379 .port_nirqs = 3,
1380 .num_tx_queues = 4,
1381 .tc_cbs_supported = true,
1382 .tc_ets_supported = true,
1383 .ops = &ksz9477_dev_ops,
1384 .mib_names = ksz9477_mib_names,
1385 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1386 .reg_mib_cnt = MIB_COUNTER_NUM,
1387 .regs = ksz9477_regs,
1388 .masks = ksz9477_masks,
1389 .shifts = ksz9477_shifts,
1390 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1391 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1392 .supports_mii = {false, false, true},
1393 .supports_rmii = {false, false, true},
1394 .supports_rgmii = {false, false, true},
1395 .internal_phy = {true, true, false},
1396 .gbit_capable = {true, true, true},
1397 },
1398
1399 [KSZ9567] = {
1400 .chip_id = KSZ9567_CHIP_ID,
1401 .dev_name = "KSZ9567",
1402 .num_vlans = 4096,
1403 .num_alus = 4096,
1404 .num_statics = 16,
1405 .cpu_ports = 0x7F, /* can be configured as cpu port */
1406 .port_cnt = 7, /* total physical port count */
1407 .port_nirqs = 3,
1408 .num_tx_queues = 4,
1409 .tc_cbs_supported = true,
1410 .tc_ets_supported = true,
1411 .ops = &ksz9477_dev_ops,
1412 .mib_names = ksz9477_mib_names,
1413 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1414 .reg_mib_cnt = MIB_COUNTER_NUM,
1415 .regs = ksz9477_regs,
1416 .masks = ksz9477_masks,
1417 .shifts = ksz9477_shifts,
1418 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1419 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1420 .supports_mii = {false, false, false, false,
1421 false, true, true},
1422 .supports_rmii = {false, false, false, false,
1423 false, true, true},
1424 .supports_rgmii = {false, false, false, false,
1425 false, true, true},
1426 .internal_phy = {true, true, true, true,
1427 true, false, false},
1428 .gbit_capable = {true, true, true, true, true, true, true},
1429 },
1430
1431 [LAN9370] = {
1432 .chip_id = LAN9370_CHIP_ID,
1433 .dev_name = "LAN9370",
1434 .num_vlans = 4096,
1435 .num_alus = 1024,
1436 .num_statics = 256,
1437 .cpu_ports = 0x10, /* can be configured as cpu port */
1438 .port_cnt = 5, /* total physical port count */
1439 .port_nirqs = 6,
1440 .num_tx_queues = 8,
1441 .tc_cbs_supported = true,
1442 .tc_ets_supported = true,
1443 .ops = &lan937x_dev_ops,
1444 .mib_names = ksz9477_mib_names,
1445 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1446 .reg_mib_cnt = MIB_COUNTER_NUM,
1447 .regs = ksz9477_regs,
1448 .masks = lan937x_masks,
1449 .shifts = lan937x_shifts,
1450 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1451 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1452 .supports_mii = {false, false, false, false, true},
1453 .supports_rmii = {false, false, false, false, true},
1454 .supports_rgmii = {false, false, false, false, true},
1455 .internal_phy = {true, true, true, true, false},
1456 },
1457
1458 [LAN9371] = {
1459 .chip_id = LAN9371_CHIP_ID,
1460 .dev_name = "LAN9371",
1461 .num_vlans = 4096,
1462 .num_alus = 1024,
1463 .num_statics = 256,
1464 .cpu_ports = 0x30, /* can be configured as cpu port */
1465 .port_cnt = 6, /* total physical port count */
1466 .port_nirqs = 6,
1467 .num_tx_queues = 8,
1468 .tc_cbs_supported = true,
1469 .tc_ets_supported = true,
1470 .ops = &lan937x_dev_ops,
1471 .mib_names = ksz9477_mib_names,
1472 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1473 .reg_mib_cnt = MIB_COUNTER_NUM,
1474 .regs = ksz9477_regs,
1475 .masks = lan937x_masks,
1476 .shifts = lan937x_shifts,
1477 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1478 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1479 .supports_mii = {false, false, false, false, true, true},
1480 .supports_rmii = {false, false, false, false, true, true},
1481 .supports_rgmii = {false, false, false, false, true, true},
1482 .internal_phy = {true, true, true, true, false, false},
1483 },
1484
1485 [LAN9372] = {
1486 .chip_id = LAN9372_CHIP_ID,
1487 .dev_name = "LAN9372",
1488 .num_vlans = 4096,
1489 .num_alus = 1024,
1490 .num_statics = 256,
1491 .cpu_ports = 0x30, /* can be configured as cpu port */
1492 .port_cnt = 8, /* total physical port count */
1493 .port_nirqs = 6,
1494 .num_tx_queues = 8,
1495 .tc_cbs_supported = true,
1496 .tc_ets_supported = true,
1497 .ops = &lan937x_dev_ops,
1498 .mib_names = ksz9477_mib_names,
1499 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1500 .reg_mib_cnt = MIB_COUNTER_NUM,
1501 .regs = ksz9477_regs,
1502 .masks = lan937x_masks,
1503 .shifts = lan937x_shifts,
1504 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1505 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1506 .supports_mii = {false, false, false, false,
1507 true, true, false, false},
1508 .supports_rmii = {false, false, false, false,
1509 true, true, false, false},
1510 .supports_rgmii = {false, false, false, false,
1511 true, true, false, false},
1512 .internal_phy = {true, true, true, true,
1513 false, false, true, true},
1514 },
1515
1516 [LAN9373] = {
1517 .chip_id = LAN9373_CHIP_ID,
1518 .dev_name = "LAN9373",
1519 .num_vlans = 4096,
1520 .num_alus = 1024,
1521 .num_statics = 256,
1522 .cpu_ports = 0x38, /* can be configured as cpu port */
1523 .port_cnt = 5, /* total physical port count */
1524 .port_nirqs = 6,
1525 .num_tx_queues = 8,
1526 .tc_cbs_supported = true,
1527 .tc_ets_supported = true,
1528 .ops = &lan937x_dev_ops,
1529 .mib_names = ksz9477_mib_names,
1530 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1531 .reg_mib_cnt = MIB_COUNTER_NUM,
1532 .regs = ksz9477_regs,
1533 .masks = lan937x_masks,
1534 .shifts = lan937x_shifts,
1535 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1536 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1537 .supports_mii = {false, false, false, false,
1538 true, true, false, false},
1539 .supports_rmii = {false, false, false, false,
1540 true, true, false, false},
1541 .supports_rgmii = {false, false, false, false,
1542 true, true, false, false},
1543 .internal_phy = {true, true, true, false,
1544 false, false, true, true},
1545 },
1546
1547 [LAN9374] = {
1548 .chip_id = LAN9374_CHIP_ID,
1549 .dev_name = "LAN9374",
1550 .num_vlans = 4096,
1551 .num_alus = 1024,
1552 .num_statics = 256,
1553 .cpu_ports = 0x30, /* can be configured as cpu port */
1554 .port_cnt = 8, /* total physical port count */
1555 .port_nirqs = 6,
1556 .num_tx_queues = 8,
1557 .tc_cbs_supported = true,
1558 .tc_ets_supported = true,
1559 .ops = &lan937x_dev_ops,
1560 .mib_names = ksz9477_mib_names,
1561 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1562 .reg_mib_cnt = MIB_COUNTER_NUM,
1563 .regs = ksz9477_regs,
1564 .masks = lan937x_masks,
1565 .shifts = lan937x_shifts,
1566 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1567 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1568 .supports_mii = {false, false, false, false,
1569 true, true, false, false},
1570 .supports_rmii = {false, false, false, false,
1571 true, true, false, false},
1572 .supports_rgmii = {false, false, false, false,
1573 true, true, false, false},
1574 .internal_phy = {true, true, true, true,
1575 false, false, true, true},
1576 },
1577 };
1578 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1579
ksz_lookup_info(unsigned int prod_num)1580 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1581 {
1582 int i;
1583
1584 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1585 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1586
1587 if (chip->chip_id == prod_num)
1588 return chip;
1589 }
1590
1591 return NULL;
1592 }
1593
ksz_check_device_id(struct ksz_device * dev)1594 static int ksz_check_device_id(struct ksz_device *dev)
1595 {
1596 const struct ksz_chip_data *dt_chip_data;
1597
1598 dt_chip_data = of_device_get_match_data(dev->dev);
1599
1600 /* Check for Device Tree and Chip ID */
1601 if (dt_chip_data->chip_id != dev->chip_id) {
1602 dev_err(dev->dev,
1603 "Device tree specifies chip %s but found %s, please fix it!\n",
1604 dt_chip_data->dev_name, dev->info->dev_name);
1605 return -ENODEV;
1606 }
1607
1608 return 0;
1609 }
1610
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1611 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1612 struct phylink_config *config)
1613 {
1614 struct ksz_device *dev = ds->priv;
1615
1616 if (dev->info->supports_mii[port])
1617 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1618
1619 if (dev->info->supports_rmii[port])
1620 __set_bit(PHY_INTERFACE_MODE_RMII,
1621 config->supported_interfaces);
1622
1623 if (dev->info->supports_rgmii[port])
1624 phy_interface_set_rgmii(config->supported_interfaces);
1625
1626 if (dev->info->internal_phy[port]) {
1627 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1628 config->supported_interfaces);
1629 /* Compatibility for phylib's default interface type when the
1630 * phy-mode property is absent
1631 */
1632 __set_bit(PHY_INTERFACE_MODE_GMII,
1633 config->supported_interfaces);
1634 }
1635
1636 if (dev->dev_ops->get_caps)
1637 dev->dev_ops->get_caps(dev, port, config);
1638 }
1639
ksz_r_mib_stats64(struct ksz_device * dev,int port)1640 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1641 {
1642 struct ethtool_pause_stats *pstats;
1643 struct rtnl_link_stats64 *stats;
1644 struct ksz_stats_raw *raw;
1645 struct ksz_port_mib *mib;
1646
1647 mib = &dev->ports[port].mib;
1648 stats = &mib->stats64;
1649 pstats = &mib->pause_stats;
1650 raw = (struct ksz_stats_raw *)mib->counters;
1651
1652 spin_lock(&mib->stats64_lock);
1653
1654 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1655 raw->rx_pause;
1656 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1657 raw->tx_pause;
1658
1659 /* HW counters are counting bytes + FCS which is not acceptable
1660 * for rtnl_link_stats64 interface
1661 */
1662 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1663 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1664
1665 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1666 raw->rx_oversize;
1667
1668 stats->rx_crc_errors = raw->rx_crc_err;
1669 stats->rx_frame_errors = raw->rx_align_err;
1670 stats->rx_dropped = raw->rx_discards;
1671 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1672 stats->rx_frame_errors + stats->rx_dropped;
1673
1674 stats->tx_window_errors = raw->tx_late_col;
1675 stats->tx_fifo_errors = raw->tx_discards;
1676 stats->tx_aborted_errors = raw->tx_exc_col;
1677 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1678 stats->tx_aborted_errors;
1679
1680 stats->multicast = raw->rx_mcast;
1681 stats->collisions = raw->tx_total_col;
1682
1683 pstats->tx_pause_frames = raw->tx_pause;
1684 pstats->rx_pause_frames = raw->rx_pause;
1685
1686 spin_unlock(&mib->stats64_lock);
1687 }
1688
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)1689 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1690 {
1691 struct ethtool_pause_stats *pstats;
1692 struct rtnl_link_stats64 *stats;
1693 struct ksz88xx_stats_raw *raw;
1694 struct ksz_port_mib *mib;
1695
1696 mib = &dev->ports[port].mib;
1697 stats = &mib->stats64;
1698 pstats = &mib->pause_stats;
1699 raw = (struct ksz88xx_stats_raw *)mib->counters;
1700
1701 spin_lock(&mib->stats64_lock);
1702
1703 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1704 raw->rx_pause;
1705 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1706 raw->tx_pause;
1707
1708 /* HW counters are counting bytes + FCS which is not acceptable
1709 * for rtnl_link_stats64 interface
1710 */
1711 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1712 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1713
1714 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1715 raw->rx_oversize;
1716
1717 stats->rx_crc_errors = raw->rx_crc_err;
1718 stats->rx_frame_errors = raw->rx_align_err;
1719 stats->rx_dropped = raw->rx_discards;
1720 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1721 stats->rx_frame_errors + stats->rx_dropped;
1722
1723 stats->tx_window_errors = raw->tx_late_col;
1724 stats->tx_fifo_errors = raw->tx_discards;
1725 stats->tx_aborted_errors = raw->tx_exc_col;
1726 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1727 stats->tx_aborted_errors;
1728
1729 stats->multicast = raw->rx_mcast;
1730 stats->collisions = raw->tx_total_col;
1731
1732 pstats->tx_pause_frames = raw->tx_pause;
1733 pstats->rx_pause_frames = raw->rx_pause;
1734
1735 spin_unlock(&mib->stats64_lock);
1736 }
1737
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1738 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1739 struct rtnl_link_stats64 *s)
1740 {
1741 struct ksz_device *dev = ds->priv;
1742 struct ksz_port_mib *mib;
1743
1744 mib = &dev->ports[port].mib;
1745
1746 spin_lock(&mib->stats64_lock);
1747 memcpy(s, &mib->stats64, sizeof(*s));
1748 spin_unlock(&mib->stats64_lock);
1749 }
1750
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1751 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1752 struct ethtool_pause_stats *pause_stats)
1753 {
1754 struct ksz_device *dev = ds->priv;
1755 struct ksz_port_mib *mib;
1756
1757 mib = &dev->ports[port].mib;
1758
1759 spin_lock(&mib->stats64_lock);
1760 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1761 spin_unlock(&mib->stats64_lock);
1762 }
1763
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1764 static void ksz_get_strings(struct dsa_switch *ds, int port,
1765 u32 stringset, uint8_t *buf)
1766 {
1767 struct ksz_device *dev = ds->priv;
1768 int i;
1769
1770 if (stringset != ETH_SS_STATS)
1771 return;
1772
1773 for (i = 0; i < dev->info->mib_cnt; i++) {
1774 memcpy(buf + i * ETH_GSTRING_LEN,
1775 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1776 }
1777 }
1778
ksz_update_port_member(struct ksz_device * dev,int port)1779 static void ksz_update_port_member(struct ksz_device *dev, int port)
1780 {
1781 struct ksz_port *p = &dev->ports[port];
1782 struct dsa_switch *ds = dev->ds;
1783 u8 port_member = 0, cpu_port;
1784 const struct dsa_port *dp;
1785 int i, j;
1786
1787 if (!dsa_is_user_port(ds, port))
1788 return;
1789
1790 dp = dsa_to_port(ds, port);
1791 cpu_port = BIT(dsa_upstream_port(ds, port));
1792
1793 for (i = 0; i < ds->num_ports; i++) {
1794 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1795 struct ksz_port *other_p = &dev->ports[i];
1796 u8 val = 0;
1797
1798 if (!dsa_is_user_port(ds, i))
1799 continue;
1800 if (port == i)
1801 continue;
1802 if (!dsa_port_bridge_same(dp, other_dp))
1803 continue;
1804 if (other_p->stp_state != BR_STATE_FORWARDING)
1805 continue;
1806
1807 if (p->stp_state == BR_STATE_FORWARDING) {
1808 val |= BIT(port);
1809 port_member |= BIT(i);
1810 }
1811
1812 /* Retain port [i]'s relationship to other ports than [port] */
1813 for (j = 0; j < ds->num_ports; j++) {
1814 const struct dsa_port *third_dp;
1815 struct ksz_port *third_p;
1816
1817 if (j == i)
1818 continue;
1819 if (j == port)
1820 continue;
1821 if (!dsa_is_user_port(ds, j))
1822 continue;
1823 third_p = &dev->ports[j];
1824 if (third_p->stp_state != BR_STATE_FORWARDING)
1825 continue;
1826 third_dp = dsa_to_port(ds, j);
1827 if (dsa_port_bridge_same(other_dp, third_dp))
1828 val |= BIT(j);
1829 }
1830
1831 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1832 }
1833
1834 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1835 }
1836
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)1837 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1838 {
1839 struct ksz_device *dev = bus->priv;
1840 u16 val;
1841 int ret;
1842
1843 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1844 if (ret < 0)
1845 return ret;
1846
1847 return val;
1848 }
1849
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)1850 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1851 u16 val)
1852 {
1853 struct ksz_device *dev = bus->priv;
1854
1855 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1856 }
1857
ksz_irq_phy_setup(struct ksz_device * dev)1858 static int ksz_irq_phy_setup(struct ksz_device *dev)
1859 {
1860 struct dsa_switch *ds = dev->ds;
1861 int phy;
1862 int irq;
1863 int ret;
1864
1865 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1866 if (BIT(phy) & ds->phys_mii_mask) {
1867 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1868 PORT_SRC_PHY_INT);
1869 if (irq < 0) {
1870 ret = irq;
1871 goto out;
1872 }
1873 ds->slave_mii_bus->irq[phy] = irq;
1874 }
1875 }
1876 return 0;
1877 out:
1878 while (phy--)
1879 if (BIT(phy) & ds->phys_mii_mask)
1880 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1881
1882 return ret;
1883 }
1884
ksz_irq_phy_free(struct ksz_device * dev)1885 static void ksz_irq_phy_free(struct ksz_device *dev)
1886 {
1887 struct dsa_switch *ds = dev->ds;
1888 int phy;
1889
1890 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1891 if (BIT(phy) & ds->phys_mii_mask)
1892 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1893 }
1894
ksz_mdio_register(struct ksz_device * dev)1895 static int ksz_mdio_register(struct ksz_device *dev)
1896 {
1897 struct dsa_switch *ds = dev->ds;
1898 struct device_node *mdio_np;
1899 struct mii_bus *bus;
1900 int ret;
1901
1902 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1903 if (!mdio_np)
1904 return 0;
1905
1906 bus = devm_mdiobus_alloc(ds->dev);
1907 if (!bus) {
1908 of_node_put(mdio_np);
1909 return -ENOMEM;
1910 }
1911
1912 bus->priv = dev;
1913 bus->read = ksz_sw_mdio_read;
1914 bus->write = ksz_sw_mdio_write;
1915 bus->name = "ksz slave smi";
1916 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1917 bus->parent = ds->dev;
1918 bus->phy_mask = ~ds->phys_mii_mask;
1919
1920 ds->slave_mii_bus = bus;
1921
1922 if (dev->irq > 0) {
1923 ret = ksz_irq_phy_setup(dev);
1924 if (ret) {
1925 of_node_put(mdio_np);
1926 return ret;
1927 }
1928 }
1929
1930 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1931 if (ret) {
1932 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1933 bus->id);
1934 if (dev->irq > 0)
1935 ksz_irq_phy_free(dev);
1936 }
1937
1938 of_node_put(mdio_np);
1939
1940 return ret;
1941 }
1942
ksz_irq_mask(struct irq_data * d)1943 static void ksz_irq_mask(struct irq_data *d)
1944 {
1945 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1946
1947 kirq->masked |= BIT(d->hwirq);
1948 }
1949
ksz_irq_unmask(struct irq_data * d)1950 static void ksz_irq_unmask(struct irq_data *d)
1951 {
1952 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1953
1954 kirq->masked &= ~BIT(d->hwirq);
1955 }
1956
ksz_irq_bus_lock(struct irq_data * d)1957 static void ksz_irq_bus_lock(struct irq_data *d)
1958 {
1959 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1960
1961 mutex_lock(&kirq->dev->lock_irq);
1962 }
1963
ksz_irq_bus_sync_unlock(struct irq_data * d)1964 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1965 {
1966 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1967 struct ksz_device *dev = kirq->dev;
1968 int ret;
1969
1970 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
1971 if (ret)
1972 dev_err(dev->dev, "failed to change IRQ mask\n");
1973
1974 mutex_unlock(&dev->lock_irq);
1975 }
1976
1977 static const struct irq_chip ksz_irq_chip = {
1978 .name = "ksz-irq",
1979 .irq_mask = ksz_irq_mask,
1980 .irq_unmask = ksz_irq_unmask,
1981 .irq_bus_lock = ksz_irq_bus_lock,
1982 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1983 };
1984
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)1985 static int ksz_irq_domain_map(struct irq_domain *d,
1986 unsigned int irq, irq_hw_number_t hwirq)
1987 {
1988 irq_set_chip_data(irq, d->host_data);
1989 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1990 irq_set_noprobe(irq);
1991
1992 return 0;
1993 }
1994
1995 static const struct irq_domain_ops ksz_irq_domain_ops = {
1996 .map = ksz_irq_domain_map,
1997 .xlate = irq_domain_xlate_twocell,
1998 };
1999
ksz_irq_free(struct ksz_irq * kirq)2000 static void ksz_irq_free(struct ksz_irq *kirq)
2001 {
2002 int irq, virq;
2003
2004 free_irq(kirq->irq_num, kirq);
2005
2006 for (irq = 0; irq < kirq->nirqs; irq++) {
2007 virq = irq_find_mapping(kirq->domain, irq);
2008 irq_dispose_mapping(virq);
2009 }
2010
2011 irq_domain_remove(kirq->domain);
2012 }
2013
ksz_irq_thread_fn(int irq,void * dev_id)2014 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2015 {
2016 struct ksz_irq *kirq = dev_id;
2017 unsigned int nhandled = 0;
2018 struct ksz_device *dev;
2019 unsigned int sub_irq;
2020 u8 data;
2021 int ret;
2022 u8 n;
2023
2024 dev = kirq->dev;
2025
2026 /* Read interrupt status register */
2027 ret = ksz_read8(dev, kirq->reg_status, &data);
2028 if (ret)
2029 goto out;
2030
2031 for (n = 0; n < kirq->nirqs; ++n) {
2032 if (data & BIT(n)) {
2033 sub_irq = irq_find_mapping(kirq->domain, n);
2034 handle_nested_irq(sub_irq);
2035 ++nhandled;
2036 }
2037 }
2038 out:
2039 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2040 }
2041
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2042 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2043 {
2044 int ret, n;
2045
2046 kirq->dev = dev;
2047 kirq->masked = ~0;
2048
2049 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2050 &ksz_irq_domain_ops, kirq);
2051 if (!kirq->domain)
2052 return -ENOMEM;
2053
2054 for (n = 0; n < kirq->nirqs; n++)
2055 irq_create_mapping(kirq->domain, n);
2056
2057 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2058 IRQF_ONESHOT, kirq->name, kirq);
2059 if (ret)
2060 goto out;
2061
2062 return 0;
2063
2064 out:
2065 ksz_irq_free(kirq);
2066
2067 return ret;
2068 }
2069
ksz_girq_setup(struct ksz_device * dev)2070 static int ksz_girq_setup(struct ksz_device *dev)
2071 {
2072 struct ksz_irq *girq = &dev->girq;
2073
2074 girq->nirqs = dev->info->port_cnt;
2075 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2076 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2077 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2078
2079 girq->irq_num = dev->irq;
2080
2081 return ksz_irq_common_setup(dev, girq);
2082 }
2083
ksz_pirq_setup(struct ksz_device * dev,u8 p)2084 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2085 {
2086 struct ksz_irq *pirq = &dev->ports[p].pirq;
2087
2088 pirq->nirqs = dev->info->port_nirqs;
2089 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2090 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2091 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2092
2093 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2094 if (pirq->irq_num < 0)
2095 return pirq->irq_num;
2096
2097 return ksz_irq_common_setup(dev, pirq);
2098 }
2099
ksz_setup(struct dsa_switch * ds)2100 static int ksz_setup(struct dsa_switch *ds)
2101 {
2102 struct ksz_device *dev = ds->priv;
2103 struct dsa_port *dp;
2104 struct ksz_port *p;
2105 const u16 *regs;
2106 int ret;
2107
2108 regs = dev->info->regs;
2109
2110 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2111 dev->info->num_vlans, GFP_KERNEL);
2112 if (!dev->vlan_cache)
2113 return -ENOMEM;
2114
2115 ret = dev->dev_ops->reset(dev);
2116 if (ret) {
2117 dev_err(ds->dev, "failed to reset switch\n");
2118 return ret;
2119 }
2120
2121 /* set broadcast storm protection 10% rate */
2122 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2123 BROADCAST_STORM_RATE,
2124 (BROADCAST_STORM_VALUE *
2125 BROADCAST_STORM_PROT_RATE) / 100);
2126
2127 dev->dev_ops->config_cpu_port(ds);
2128
2129 dev->dev_ops->enable_stp_addr(dev);
2130
2131 ds->num_tx_queues = dev->info->num_tx_queues;
2132
2133 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2134 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2135
2136 ksz_init_mib_timer(dev);
2137
2138 ds->configure_vlan_while_not_filtering = false;
2139
2140 if (dev->dev_ops->setup) {
2141 ret = dev->dev_ops->setup(ds);
2142 if (ret)
2143 return ret;
2144 }
2145
2146 /* Start with learning disabled on standalone user ports, and enabled
2147 * on the CPU port. In lack of other finer mechanisms, learning on the
2148 * CPU port will avoid flooding bridge local addresses on the network
2149 * in some cases.
2150 */
2151 p = &dev->ports[dev->cpu_port];
2152 p->learning = true;
2153
2154 if (dev->irq > 0) {
2155 ret = ksz_girq_setup(dev);
2156 if (ret)
2157 return ret;
2158
2159 dsa_switch_for_each_user_port(dp, dev->ds) {
2160 ret = ksz_pirq_setup(dev, dp->index);
2161 if (ret)
2162 goto out_girq;
2163
2164 ret = ksz_ptp_irq_setup(ds, dp->index);
2165 if (ret)
2166 goto out_pirq;
2167 }
2168 }
2169
2170 ret = ksz_ptp_clock_register(ds);
2171 if (ret) {
2172 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2173 goto out_ptpirq;
2174 }
2175
2176 ret = ksz_mdio_register(dev);
2177 if (ret < 0) {
2178 dev_err(dev->dev, "failed to register the mdio");
2179 goto out_ptp_clock_unregister;
2180 }
2181
2182 /* start switch */
2183 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2184 SW_START, SW_START);
2185
2186 return 0;
2187
2188 out_ptp_clock_unregister:
2189 ksz_ptp_clock_unregister(ds);
2190 out_ptpirq:
2191 if (dev->irq > 0)
2192 dsa_switch_for_each_user_port(dp, dev->ds)
2193 ksz_ptp_irq_free(ds, dp->index);
2194 out_pirq:
2195 if (dev->irq > 0)
2196 dsa_switch_for_each_user_port(dp, dev->ds)
2197 ksz_irq_free(&dev->ports[dp->index].pirq);
2198 out_girq:
2199 if (dev->irq > 0)
2200 ksz_irq_free(&dev->girq);
2201
2202 return ret;
2203 }
2204
ksz_teardown(struct dsa_switch * ds)2205 static void ksz_teardown(struct dsa_switch *ds)
2206 {
2207 struct ksz_device *dev = ds->priv;
2208 struct dsa_port *dp;
2209
2210 ksz_ptp_clock_unregister(ds);
2211
2212 if (dev->irq > 0) {
2213 dsa_switch_for_each_user_port(dp, dev->ds) {
2214 ksz_ptp_irq_free(ds, dp->index);
2215
2216 ksz_irq_free(&dev->ports[dp->index].pirq);
2217 }
2218
2219 ksz_irq_free(&dev->girq);
2220 }
2221
2222 if (dev->dev_ops->teardown)
2223 dev->dev_ops->teardown(ds);
2224 }
2225
port_r_cnt(struct ksz_device * dev,int port)2226 static void port_r_cnt(struct ksz_device *dev, int port)
2227 {
2228 struct ksz_port_mib *mib = &dev->ports[port].mib;
2229 u64 *dropped;
2230
2231 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2232 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2233 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2234 &mib->counters[mib->cnt_ptr]);
2235 ++mib->cnt_ptr;
2236 }
2237
2238 /* last one in storage */
2239 dropped = &mib->counters[dev->info->mib_cnt];
2240
2241 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2242 while (mib->cnt_ptr < dev->info->mib_cnt) {
2243 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2244 dropped, &mib->counters[mib->cnt_ptr]);
2245 ++mib->cnt_ptr;
2246 }
2247 mib->cnt_ptr = 0;
2248 }
2249
ksz_mib_read_work(struct work_struct * work)2250 static void ksz_mib_read_work(struct work_struct *work)
2251 {
2252 struct ksz_device *dev = container_of(work, struct ksz_device,
2253 mib_read.work);
2254 struct ksz_port_mib *mib;
2255 struct ksz_port *p;
2256 int i;
2257
2258 for (i = 0; i < dev->info->port_cnt; i++) {
2259 if (dsa_is_unused_port(dev->ds, i))
2260 continue;
2261
2262 p = &dev->ports[i];
2263 mib = &p->mib;
2264 mutex_lock(&mib->cnt_mutex);
2265
2266 /* Only read MIB counters when the port is told to do.
2267 * If not, read only dropped counters when link is not up.
2268 */
2269 if (!p->read) {
2270 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2271
2272 if (!netif_carrier_ok(dp->slave))
2273 mib->cnt_ptr = dev->info->reg_mib_cnt;
2274 }
2275 port_r_cnt(dev, i);
2276 p->read = false;
2277
2278 if (dev->dev_ops->r_mib_stat64)
2279 dev->dev_ops->r_mib_stat64(dev, i);
2280
2281 mutex_unlock(&mib->cnt_mutex);
2282 }
2283
2284 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2285 }
2286
ksz_init_mib_timer(struct ksz_device * dev)2287 void ksz_init_mib_timer(struct ksz_device *dev)
2288 {
2289 int i;
2290
2291 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2292
2293 for (i = 0; i < dev->info->port_cnt; i++) {
2294 struct ksz_port_mib *mib = &dev->ports[i].mib;
2295
2296 dev->dev_ops->port_init_cnt(dev, i);
2297
2298 mib->cnt_ptr = 0;
2299 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2300 }
2301 }
2302
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2303 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2304 {
2305 struct ksz_device *dev = ds->priv;
2306 u16 val = 0xffff;
2307 int ret;
2308
2309 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2310 if (ret)
2311 return ret;
2312
2313 return val;
2314 }
2315
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2316 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2317 {
2318 struct ksz_device *dev = ds->priv;
2319 int ret;
2320
2321 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2322 if (ret)
2323 return ret;
2324
2325 return 0;
2326 }
2327
ksz_get_phy_flags(struct dsa_switch * ds,int port)2328 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2329 {
2330 struct ksz_device *dev = ds->priv;
2331
2332 switch (dev->chip_id) {
2333 case KSZ8830_CHIP_ID:
2334 /* Silicon Errata Sheet (DS80000830A):
2335 * Port 1 does not work with LinkMD Cable-Testing.
2336 * Port 1 does not respond to received PAUSE control frames.
2337 */
2338 if (!port)
2339 return MICREL_KSZ8_P1_ERRATA;
2340 break;
2341 case KSZ9477_CHIP_ID:
2342 /* KSZ9477 Errata DS80000754C
2343 *
2344 * Module 4: Energy Efficient Ethernet (EEE) feature select must
2345 * be manually disabled
2346 * The EEE feature is enabled by default, but it is not fully
2347 * operational. It must be manually disabled through register
2348 * controls. If not disabled, the PHY ports can auto-negotiate
2349 * to enable EEE, and this feature can cause link drops when
2350 * linked to another device supporting EEE.
2351 */
2352 return MICREL_NO_EEE;
2353 }
2354
2355 return 0;
2356 }
2357
ksz_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2358 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2359 unsigned int mode, phy_interface_t interface)
2360 {
2361 struct ksz_device *dev = ds->priv;
2362 struct ksz_port *p = &dev->ports[port];
2363
2364 /* Read all MIB counters when the link is going down. */
2365 p->read = true;
2366 /* timer started */
2367 if (dev->mib_read_interval)
2368 schedule_delayed_work(&dev->mib_read, 0);
2369 }
2370
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2371 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2372 {
2373 struct ksz_device *dev = ds->priv;
2374
2375 if (sset != ETH_SS_STATS)
2376 return 0;
2377
2378 return dev->info->mib_cnt;
2379 }
2380
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2381 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2382 uint64_t *buf)
2383 {
2384 const struct dsa_port *dp = dsa_to_port(ds, port);
2385 struct ksz_device *dev = ds->priv;
2386 struct ksz_port_mib *mib;
2387
2388 mib = &dev->ports[port].mib;
2389 mutex_lock(&mib->cnt_mutex);
2390
2391 /* Only read dropped counters if no link. */
2392 if (!netif_carrier_ok(dp->slave))
2393 mib->cnt_ptr = dev->info->reg_mib_cnt;
2394 port_r_cnt(dev, port);
2395 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2396 mutex_unlock(&mib->cnt_mutex);
2397 }
2398
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2399 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2400 struct dsa_bridge bridge,
2401 bool *tx_fwd_offload,
2402 struct netlink_ext_ack *extack)
2403 {
2404 /* port_stp_state_set() will be called after to put the port in
2405 * appropriate state so there is no need to do anything.
2406 */
2407
2408 return 0;
2409 }
2410
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2411 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2412 struct dsa_bridge bridge)
2413 {
2414 /* port_stp_state_set() will be called after to put the port in
2415 * forwarding state so there is no need to do anything.
2416 */
2417 }
2418
ksz_port_fast_age(struct dsa_switch * ds,int port)2419 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2420 {
2421 struct ksz_device *dev = ds->priv;
2422
2423 dev->dev_ops->flush_dyn_mac_table(dev, port);
2424 }
2425
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)2426 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2427 {
2428 struct ksz_device *dev = ds->priv;
2429
2430 if (!dev->dev_ops->set_ageing_time)
2431 return -EOPNOTSUPP;
2432
2433 return dev->dev_ops->set_ageing_time(dev, msecs);
2434 }
2435
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2436 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2437 const unsigned char *addr, u16 vid,
2438 struct dsa_db db)
2439 {
2440 struct ksz_device *dev = ds->priv;
2441
2442 if (!dev->dev_ops->fdb_add)
2443 return -EOPNOTSUPP;
2444
2445 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2446 }
2447
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2448 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2449 const unsigned char *addr,
2450 u16 vid, struct dsa_db db)
2451 {
2452 struct ksz_device *dev = ds->priv;
2453
2454 if (!dev->dev_ops->fdb_del)
2455 return -EOPNOTSUPP;
2456
2457 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2458 }
2459
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2460 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2461 dsa_fdb_dump_cb_t *cb, void *data)
2462 {
2463 struct ksz_device *dev = ds->priv;
2464
2465 if (!dev->dev_ops->fdb_dump)
2466 return -EOPNOTSUPP;
2467
2468 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2469 }
2470
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2471 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2472 const struct switchdev_obj_port_mdb *mdb,
2473 struct dsa_db db)
2474 {
2475 struct ksz_device *dev = ds->priv;
2476
2477 if (!dev->dev_ops->mdb_add)
2478 return -EOPNOTSUPP;
2479
2480 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2481 }
2482
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2483 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2484 const struct switchdev_obj_port_mdb *mdb,
2485 struct dsa_db db)
2486 {
2487 struct ksz_device *dev = ds->priv;
2488
2489 if (!dev->dev_ops->mdb_del)
2490 return -EOPNOTSUPP;
2491
2492 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2493 }
2494
ksz_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)2495 static int ksz_enable_port(struct dsa_switch *ds, int port,
2496 struct phy_device *phy)
2497 {
2498 struct ksz_device *dev = ds->priv;
2499
2500 if (!dsa_is_user_port(ds, port))
2501 return 0;
2502
2503 /* setup slave port */
2504 dev->dev_ops->port_setup(dev, port, false);
2505
2506 /* port_stp_state_set() will be called after to enable the port so
2507 * there is no need to do anything.
2508 */
2509
2510 return 0;
2511 }
2512
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2513 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2514 {
2515 struct ksz_device *dev = ds->priv;
2516 struct ksz_port *p;
2517 const u16 *regs;
2518 u8 data;
2519
2520 regs = dev->info->regs;
2521
2522 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2523 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2524
2525 p = &dev->ports[port];
2526
2527 switch (state) {
2528 case BR_STATE_DISABLED:
2529 data |= PORT_LEARN_DISABLE;
2530 break;
2531 case BR_STATE_LISTENING:
2532 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2533 break;
2534 case BR_STATE_LEARNING:
2535 data |= PORT_RX_ENABLE;
2536 if (!p->learning)
2537 data |= PORT_LEARN_DISABLE;
2538 break;
2539 case BR_STATE_FORWARDING:
2540 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2541 if (!p->learning)
2542 data |= PORT_LEARN_DISABLE;
2543 break;
2544 case BR_STATE_BLOCKING:
2545 data |= PORT_LEARN_DISABLE;
2546 break;
2547 default:
2548 dev_err(ds->dev, "invalid STP state: %d\n", state);
2549 return;
2550 }
2551
2552 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2553
2554 p->stp_state = state;
2555
2556 ksz_update_port_member(dev, port);
2557 }
2558
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2559 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2560 struct switchdev_brport_flags flags,
2561 struct netlink_ext_ack *extack)
2562 {
2563 if (flags.mask & ~BR_LEARNING)
2564 return -EINVAL;
2565
2566 return 0;
2567 }
2568
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2569 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2570 struct switchdev_brport_flags flags,
2571 struct netlink_ext_ack *extack)
2572 {
2573 struct ksz_device *dev = ds->priv;
2574 struct ksz_port *p = &dev->ports[port];
2575
2576 if (flags.mask & BR_LEARNING) {
2577 p->learning = !!(flags.val & BR_LEARNING);
2578
2579 /* Make the change take effect immediately */
2580 ksz_port_stp_state_set(ds, port, p->stp_state);
2581 }
2582
2583 return 0;
2584 }
2585
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2586 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2587 int port,
2588 enum dsa_tag_protocol mp)
2589 {
2590 struct ksz_device *dev = ds->priv;
2591 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2592
2593 if (dev->chip_id == KSZ8795_CHIP_ID ||
2594 dev->chip_id == KSZ8794_CHIP_ID ||
2595 dev->chip_id == KSZ8765_CHIP_ID)
2596 proto = DSA_TAG_PROTO_KSZ8795;
2597
2598 if (dev->chip_id == KSZ8830_CHIP_ID ||
2599 dev->chip_id == KSZ8563_CHIP_ID ||
2600 dev->chip_id == KSZ9893_CHIP_ID ||
2601 dev->chip_id == KSZ9563_CHIP_ID)
2602 proto = DSA_TAG_PROTO_KSZ9893;
2603
2604 if (dev->chip_id == KSZ9477_CHIP_ID ||
2605 dev->chip_id == KSZ9896_CHIP_ID ||
2606 dev->chip_id == KSZ9897_CHIP_ID ||
2607 dev->chip_id == KSZ9567_CHIP_ID)
2608 proto = DSA_TAG_PROTO_KSZ9477;
2609
2610 if (is_lan937x(dev))
2611 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2612
2613 return proto;
2614 }
2615
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)2616 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2617 enum dsa_tag_protocol proto)
2618 {
2619 struct ksz_tagger_data *tagger_data;
2620
2621 switch (proto) {
2622 case DSA_TAG_PROTO_KSZ8795:
2623 return 0;
2624 case DSA_TAG_PROTO_KSZ9893:
2625 case DSA_TAG_PROTO_KSZ9477:
2626 case DSA_TAG_PROTO_LAN937X:
2627 tagger_data = ksz_tagger_data(ds);
2628 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2629 return 0;
2630 default:
2631 return -EPROTONOSUPPORT;
2632 }
2633 }
2634
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)2635 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2636 bool flag, struct netlink_ext_ack *extack)
2637 {
2638 struct ksz_device *dev = ds->priv;
2639
2640 if (!dev->dev_ops->vlan_filtering)
2641 return -EOPNOTSUPP;
2642
2643 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2644 }
2645
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2646 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2647 const struct switchdev_obj_port_vlan *vlan,
2648 struct netlink_ext_ack *extack)
2649 {
2650 struct ksz_device *dev = ds->priv;
2651
2652 if (!dev->dev_ops->vlan_add)
2653 return -EOPNOTSUPP;
2654
2655 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2656 }
2657
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2658 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2659 const struct switchdev_obj_port_vlan *vlan)
2660 {
2661 struct ksz_device *dev = ds->priv;
2662
2663 if (!dev->dev_ops->vlan_del)
2664 return -EOPNOTSUPP;
2665
2666 return dev->dev_ops->vlan_del(dev, port, vlan);
2667 }
2668
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2669 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2670 struct dsa_mall_mirror_tc_entry *mirror,
2671 bool ingress, struct netlink_ext_ack *extack)
2672 {
2673 struct ksz_device *dev = ds->priv;
2674
2675 if (!dev->dev_ops->mirror_add)
2676 return -EOPNOTSUPP;
2677
2678 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2679 }
2680
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2681 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2682 struct dsa_mall_mirror_tc_entry *mirror)
2683 {
2684 struct ksz_device *dev = ds->priv;
2685
2686 if (dev->dev_ops->mirror_del)
2687 dev->dev_ops->mirror_del(dev, port, mirror);
2688 }
2689
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)2690 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2691 {
2692 struct ksz_device *dev = ds->priv;
2693
2694 if (!dev->dev_ops->change_mtu)
2695 return -EOPNOTSUPP;
2696
2697 return dev->dev_ops->change_mtu(dev, port, mtu);
2698 }
2699
ksz_max_mtu(struct dsa_switch * ds,int port)2700 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2701 {
2702 struct ksz_device *dev = ds->priv;
2703
2704 switch (dev->chip_id) {
2705 case KSZ8795_CHIP_ID:
2706 case KSZ8794_CHIP_ID:
2707 case KSZ8765_CHIP_ID:
2708 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2709 case KSZ8830_CHIP_ID:
2710 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2711 case KSZ8563_CHIP_ID:
2712 case KSZ9477_CHIP_ID:
2713 case KSZ9563_CHIP_ID:
2714 case KSZ9567_CHIP_ID:
2715 case KSZ9893_CHIP_ID:
2716 case KSZ9896_CHIP_ID:
2717 case KSZ9897_CHIP_ID:
2718 case LAN9370_CHIP_ID:
2719 case LAN9371_CHIP_ID:
2720 case LAN9372_CHIP_ID:
2721 case LAN9373_CHIP_ID:
2722 case LAN9374_CHIP_ID:
2723 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2724 }
2725
2726 return -EOPNOTSUPP;
2727 }
2728
ksz_validate_eee(struct dsa_switch * ds,int port)2729 static int ksz_validate_eee(struct dsa_switch *ds, int port)
2730 {
2731 struct ksz_device *dev = ds->priv;
2732
2733 if (!dev->info->internal_phy[port])
2734 return -EOPNOTSUPP;
2735
2736 switch (dev->chip_id) {
2737 case KSZ8563_CHIP_ID:
2738 case KSZ9477_CHIP_ID:
2739 case KSZ9563_CHIP_ID:
2740 case KSZ9567_CHIP_ID:
2741 case KSZ9893_CHIP_ID:
2742 case KSZ9896_CHIP_ID:
2743 case KSZ9897_CHIP_ID:
2744 return 0;
2745 }
2746
2747 return -EOPNOTSUPP;
2748 }
2749
ksz_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2750 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2751 struct ethtool_eee *e)
2752 {
2753 int ret;
2754
2755 ret = ksz_validate_eee(ds, port);
2756 if (ret)
2757 return ret;
2758
2759 /* There is no documented control of Tx LPI configuration. */
2760 e->tx_lpi_enabled = true;
2761
2762 /* There is no documented control of Tx LPI timer. According to tests
2763 * Tx LPI timer seems to be set by default to minimal value.
2764 */
2765 e->tx_lpi_timer = 0;
2766
2767 return 0;
2768 }
2769
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2770 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2771 struct ethtool_eee *e)
2772 {
2773 struct ksz_device *dev = ds->priv;
2774 int ret;
2775
2776 ret = ksz_validate_eee(ds, port);
2777 if (ret)
2778 return ret;
2779
2780 if (!e->tx_lpi_enabled) {
2781 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2782 return -EINVAL;
2783 }
2784
2785 if (e->tx_lpi_timer) {
2786 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2787 return -EINVAL;
2788 }
2789
2790 return 0;
2791 }
2792
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)2793 static void ksz_set_xmii(struct ksz_device *dev, int port,
2794 phy_interface_t interface)
2795 {
2796 const u8 *bitval = dev->info->xmii_ctrl1;
2797 struct ksz_port *p = &dev->ports[port];
2798 const u16 *regs = dev->info->regs;
2799 u8 data8;
2800
2801 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2802
2803 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2804 P_RGMII_ID_EG_ENABLE);
2805
2806 switch (interface) {
2807 case PHY_INTERFACE_MODE_MII:
2808 data8 |= bitval[P_MII_SEL];
2809 break;
2810 case PHY_INTERFACE_MODE_RMII:
2811 data8 |= bitval[P_RMII_SEL];
2812 break;
2813 case PHY_INTERFACE_MODE_GMII:
2814 data8 |= bitval[P_GMII_SEL];
2815 break;
2816 case PHY_INTERFACE_MODE_RGMII:
2817 case PHY_INTERFACE_MODE_RGMII_ID:
2818 case PHY_INTERFACE_MODE_RGMII_TXID:
2819 case PHY_INTERFACE_MODE_RGMII_RXID:
2820 data8 |= bitval[P_RGMII_SEL];
2821 /* On KSZ9893, disable RGMII in-band status support */
2822 if (dev->chip_id == KSZ9893_CHIP_ID ||
2823 dev->chip_id == KSZ8563_CHIP_ID ||
2824 dev->chip_id == KSZ9563_CHIP_ID)
2825 data8 &= ~P_MII_MAC_MODE;
2826 break;
2827 default:
2828 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2829 phy_modes(interface), port);
2830 return;
2831 }
2832
2833 if (p->rgmii_tx_val)
2834 data8 |= P_RGMII_ID_EG_ENABLE;
2835
2836 if (p->rgmii_rx_val)
2837 data8 |= P_RGMII_ID_IG_ENABLE;
2838
2839 /* Write the updated value */
2840 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2841 }
2842
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)2843 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2844 {
2845 const u8 *bitval = dev->info->xmii_ctrl1;
2846 const u16 *regs = dev->info->regs;
2847 phy_interface_t interface;
2848 u8 data8;
2849 u8 val;
2850
2851 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2852
2853 val = FIELD_GET(P_MII_SEL_M, data8);
2854
2855 if (val == bitval[P_MII_SEL]) {
2856 if (gbit)
2857 interface = PHY_INTERFACE_MODE_GMII;
2858 else
2859 interface = PHY_INTERFACE_MODE_MII;
2860 } else if (val == bitval[P_RMII_SEL]) {
2861 interface = PHY_INTERFACE_MODE_RMII;
2862 } else {
2863 interface = PHY_INTERFACE_MODE_RGMII;
2864 if (data8 & P_RGMII_ID_EG_ENABLE)
2865 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2866 if (data8 & P_RGMII_ID_IG_ENABLE) {
2867 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2868 if (data8 & P_RGMII_ID_EG_ENABLE)
2869 interface = PHY_INTERFACE_MODE_RGMII_ID;
2870 }
2871 }
2872
2873 return interface;
2874 }
2875
ksz_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2876 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2877 unsigned int mode,
2878 const struct phylink_link_state *state)
2879 {
2880 struct ksz_device *dev = ds->priv;
2881
2882 if (ksz_is_ksz88x3(dev))
2883 return;
2884
2885 /* Internal PHYs */
2886 if (dev->info->internal_phy[port])
2887 return;
2888
2889 if (phylink_autoneg_inband(mode)) {
2890 dev_err(dev->dev, "In-band AN not supported!\n");
2891 return;
2892 }
2893
2894 ksz_set_xmii(dev, port, state->interface);
2895
2896 if (dev->dev_ops->phylink_mac_config)
2897 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2898
2899 if (dev->dev_ops->setup_rgmii_delay)
2900 dev->dev_ops->setup_rgmii_delay(dev, port);
2901 }
2902
ksz_get_gbit(struct ksz_device * dev,int port)2903 bool ksz_get_gbit(struct ksz_device *dev, int port)
2904 {
2905 const u8 *bitval = dev->info->xmii_ctrl1;
2906 const u16 *regs = dev->info->regs;
2907 bool gbit = false;
2908 u8 data8;
2909 bool val;
2910
2911 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2912
2913 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2914
2915 if (val == bitval[P_GMII_1GBIT])
2916 gbit = true;
2917
2918 return gbit;
2919 }
2920
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)2921 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2922 {
2923 const u8 *bitval = dev->info->xmii_ctrl1;
2924 const u16 *regs = dev->info->regs;
2925 u8 data8;
2926
2927 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2928
2929 data8 &= ~P_GMII_1GBIT_M;
2930
2931 if (gbit)
2932 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2933 else
2934 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2935
2936 /* Write the updated value */
2937 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2938 }
2939
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)2940 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2941 {
2942 const u8 *bitval = dev->info->xmii_ctrl0;
2943 const u16 *regs = dev->info->regs;
2944 u8 data8;
2945
2946 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2947
2948 data8 &= ~P_MII_100MBIT_M;
2949
2950 if (speed == SPEED_100)
2951 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2952 else
2953 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2954
2955 /* Write the updated value */
2956 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2957 }
2958
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)2959 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2960 {
2961 if (speed == SPEED_1000)
2962 ksz_set_gbit(dev, port, true);
2963 else
2964 ksz_set_gbit(dev, port, false);
2965
2966 if (speed == SPEED_100 || speed == SPEED_10)
2967 ksz_set_100_10mbit(dev, port, speed);
2968 }
2969
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)2970 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2971 bool tx_pause, bool rx_pause)
2972 {
2973 const u8 *bitval = dev->info->xmii_ctrl0;
2974 const u32 *masks = dev->info->masks;
2975 const u16 *regs = dev->info->regs;
2976 u8 mask;
2977 u8 val;
2978
2979 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2980 masks[P_MII_RX_FLOW_CTRL];
2981
2982 if (duplex == DUPLEX_FULL)
2983 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2984 else
2985 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2986
2987 if (tx_pause)
2988 val |= masks[P_MII_TX_FLOW_CTRL];
2989
2990 if (rx_pause)
2991 val |= masks[P_MII_RX_FLOW_CTRL];
2992
2993 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2994 }
2995
ksz9477_phylink_mac_link_up(struct ksz_device * dev,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2996 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2997 unsigned int mode,
2998 phy_interface_t interface,
2999 struct phy_device *phydev, int speed,
3000 int duplex, bool tx_pause,
3001 bool rx_pause)
3002 {
3003 struct ksz_port *p;
3004
3005 p = &dev->ports[port];
3006
3007 /* Internal PHYs */
3008 if (dev->info->internal_phy[port])
3009 return;
3010
3011 p->phydev.speed = speed;
3012
3013 ksz_port_set_xmii_speed(dev, port, speed);
3014
3015 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3016 }
3017
ksz_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)3018 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
3019 unsigned int mode,
3020 phy_interface_t interface,
3021 struct phy_device *phydev, int speed,
3022 int duplex, bool tx_pause, bool rx_pause)
3023 {
3024 struct ksz_device *dev = ds->priv;
3025
3026 if (dev->dev_ops->phylink_mac_link_up)
3027 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
3028 phydev, speed, duplex,
3029 tx_pause, rx_pause);
3030 }
3031
ksz_switch_detect(struct ksz_device * dev)3032 static int ksz_switch_detect(struct ksz_device *dev)
3033 {
3034 u8 id1, id2, id4;
3035 u16 id16;
3036 u32 id32;
3037 int ret;
3038
3039 /* read chip id */
3040 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3041 if (ret)
3042 return ret;
3043
3044 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3045 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3046
3047 switch (id1) {
3048 case KSZ87_FAMILY_ID:
3049 if (id2 == KSZ87_CHIP_ID_95) {
3050 u8 val;
3051
3052 dev->chip_id = KSZ8795_CHIP_ID;
3053
3054 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3055 if (val & KSZ8_PORT_FIBER_MODE)
3056 dev->chip_id = KSZ8765_CHIP_ID;
3057 } else if (id2 == KSZ87_CHIP_ID_94) {
3058 dev->chip_id = KSZ8794_CHIP_ID;
3059 } else {
3060 return -ENODEV;
3061 }
3062 break;
3063 case KSZ88_FAMILY_ID:
3064 if (id2 == KSZ88_CHIP_ID_63)
3065 dev->chip_id = KSZ8830_CHIP_ID;
3066 else
3067 return -ENODEV;
3068 break;
3069 default:
3070 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3071 if (ret)
3072 return ret;
3073
3074 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3075 id32 &= ~0xFF;
3076
3077 switch (id32) {
3078 case KSZ9477_CHIP_ID:
3079 case KSZ9896_CHIP_ID:
3080 case KSZ9897_CHIP_ID:
3081 case KSZ9567_CHIP_ID:
3082 case LAN9370_CHIP_ID:
3083 case LAN9371_CHIP_ID:
3084 case LAN9372_CHIP_ID:
3085 case LAN9373_CHIP_ID:
3086 case LAN9374_CHIP_ID:
3087 dev->chip_id = id32;
3088 break;
3089 case KSZ9893_CHIP_ID:
3090 ret = ksz_read8(dev, REG_CHIP_ID4,
3091 &id4);
3092 if (ret)
3093 return ret;
3094
3095 if (id4 == SKU_ID_KSZ8563)
3096 dev->chip_id = KSZ8563_CHIP_ID;
3097 else if (id4 == SKU_ID_KSZ9563)
3098 dev->chip_id = KSZ9563_CHIP_ID;
3099 else
3100 dev->chip_id = KSZ9893_CHIP_ID;
3101
3102 break;
3103 default:
3104 dev_err(dev->dev,
3105 "unsupported switch detected %x)\n", id32);
3106 return -ENODEV;
3107 }
3108 }
3109 return 0;
3110 }
3111
3112 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3113 * is converted to Hex-decimal using the successive multiplication method. On
3114 * every step, integer part is taken and decimal part is carry forwarded.
3115 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)3116 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3117 {
3118 u32 cinc = 0;
3119 u32 txrate;
3120 u32 rate;
3121 u8 temp;
3122 u8 i;
3123
3124 txrate = idle_slope - send_slope;
3125
3126 if (!txrate)
3127 return -EINVAL;
3128
3129 rate = idle_slope;
3130
3131 /* 24 bit register */
3132 for (i = 0; i < 6; i++) {
3133 rate = rate * 16;
3134
3135 temp = rate / txrate;
3136
3137 rate %= txrate;
3138
3139 cinc = ((cinc << 4) | temp);
3140 }
3141
3142 *bw = cinc;
3143
3144 return 0;
3145 }
3146
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)3147 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3148 u8 shaper)
3149 {
3150 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3151 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3152 FIELD_PREP(MTI_SHAPING_M, shaper));
3153 }
3154
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)3155 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3156 struct tc_cbs_qopt_offload *qopt)
3157 {
3158 struct ksz_device *dev = ds->priv;
3159 int ret;
3160 u32 bw;
3161
3162 if (!dev->info->tc_cbs_supported)
3163 return -EOPNOTSUPP;
3164
3165 if (qopt->queue > dev->info->num_tx_queues)
3166 return -EINVAL;
3167
3168 /* Queue Selection */
3169 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3170 if (ret)
3171 return ret;
3172
3173 if (!qopt->enable)
3174 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3175 MTI_SHAPING_OFF);
3176
3177 /* High Credit */
3178 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3179 qopt->hicredit);
3180 if (ret)
3181 return ret;
3182
3183 /* Low Credit */
3184 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3185 qopt->locredit);
3186 if (ret)
3187 return ret;
3188
3189 /* Credit Increment Register */
3190 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3191 if (ret)
3192 return ret;
3193
3194 if (dev->dev_ops->tc_cbs_set_cinc) {
3195 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3196 if (ret)
3197 return ret;
3198 }
3199
3200 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3201 MTI_SHAPING_SRP);
3202 }
3203
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)3204 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3205 {
3206 int queue, ret;
3207
3208 /* Configuration will not take effect until the last Port Queue X
3209 * Egress Limit Control Register is written.
3210 */
3211 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3212 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3213 KSZ9477_OUT_RATE_NO_LIMIT);
3214 if (ret)
3215 return ret;
3216 }
3217
3218 return 0;
3219 }
3220
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)3221 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3222 int band)
3223 {
3224 /* Compared to queues, bands prioritize packets differently. In strict
3225 * priority mode, the lowest priority is assigned to Queue 0 while the
3226 * highest priority is given to Band 0.
3227 */
3228 return p->bands - 1 - band;
3229 }
3230
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)3231 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3232 {
3233 int ret;
3234
3235 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3236 if (ret)
3237 return ret;
3238
3239 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3240 MTI_SHAPING_OFF);
3241 }
3242
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)3243 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3244 int weight)
3245 {
3246 int ret;
3247
3248 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3249 if (ret)
3250 return ret;
3251
3252 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3253 MTI_SHAPING_OFF);
3254 if (ret)
3255 return ret;
3256
3257 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3258 }
3259
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3260 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3261 struct tc_ets_qopt_offload_replace_params *p)
3262 {
3263 int ret, band, tc_prio;
3264 u32 queue_map = 0;
3265
3266 /* In order to ensure proper prioritization, it is necessary to set the
3267 * rate limit for the related queue to zero. Otherwise strict priority
3268 * or WRR mode will not work. This is a hardware limitation.
3269 */
3270 ret = ksz_disable_egress_rate_limit(dev, port);
3271 if (ret)
3272 return ret;
3273
3274 /* Configure queue scheduling mode for all bands. Currently only strict
3275 * prio mode is supported.
3276 */
3277 for (band = 0; band < p->bands; band++) {
3278 int queue = ksz_ets_band_to_queue(p, band);
3279
3280 ret = ksz_queue_set_strict(dev, port, queue);
3281 if (ret)
3282 return ret;
3283 }
3284
3285 /* Configure the mapping between traffic classes and queues. Note:
3286 * priomap variable support 16 traffic classes, but the chip can handle
3287 * only 8 classes.
3288 */
3289 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3290 int queue;
3291
3292 if (tc_prio > KSZ9477_MAX_TC_PRIO)
3293 break;
3294
3295 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3296 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3297 }
3298
3299 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3300 }
3301
ksz_tc_ets_del(struct ksz_device * dev,int port)3302 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3303 {
3304 int ret, queue, tc_prio, s;
3305 u32 queue_map = 0;
3306
3307 /* To restore the default chip configuration, set all queues to use the
3308 * WRR scheduler with a weight of 1.
3309 */
3310 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3311 ret = ksz_queue_set_wrr(dev, port, queue,
3312 KSZ9477_DEFAULT_WRR_WEIGHT);
3313 if (ret)
3314 return ret;
3315 }
3316
3317 switch (dev->info->num_tx_queues) {
3318 case 2:
3319 s = 2;
3320 break;
3321 case 4:
3322 s = 1;
3323 break;
3324 case 8:
3325 s = 0;
3326 break;
3327 default:
3328 return -EINVAL;
3329 }
3330
3331 /* Revert the queue mapping for TC-priority to its default setting on
3332 * the chip.
3333 */
3334 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3335 int queue;
3336
3337 queue = tc_prio >> s;
3338 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3339 }
3340
3341 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3342 }
3343
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3344 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3345 struct tc_ets_qopt_offload_replace_params *p)
3346 {
3347 int band;
3348
3349 /* Since it is not feasible to share one port among multiple qdisc,
3350 * the user must configure all available queues appropriately.
3351 */
3352 if (p->bands != dev->info->num_tx_queues) {
3353 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3354 dev->info->num_tx_queues);
3355 return -EOPNOTSUPP;
3356 }
3357
3358 for (band = 0; band < p->bands; ++band) {
3359 /* The KSZ switches utilize a weighted round robin configuration
3360 * where a certain number of packets can be transmitted from a
3361 * queue before the next queue is serviced. For more information
3362 * on this, refer to section 5.2.8.4 of the KSZ8565R
3363 * documentation on the Port Transmit Queue Control 1 Register.
3364 * However, the current ETS Qdisc implementation (as of February
3365 * 2023) assigns a weight to each queue based on the number of
3366 * bytes or extrapolated bandwidth in percentages. Since this
3367 * differs from the KSZ switches' method and we don't want to
3368 * fake support by converting bytes to packets, it is better to
3369 * return an error instead.
3370 */
3371 if (p->quanta[band]) {
3372 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3373 return -EOPNOTSUPP;
3374 }
3375 }
3376
3377 return 0;
3378 }
3379
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)3380 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3381 struct tc_ets_qopt_offload *qopt)
3382 {
3383 struct ksz_device *dev = ds->priv;
3384 int ret;
3385
3386 if (!dev->info->tc_ets_supported)
3387 return -EOPNOTSUPP;
3388
3389 if (qopt->parent != TC_H_ROOT) {
3390 dev_err(dev->dev, "Parent should be \"root\"\n");
3391 return -EOPNOTSUPP;
3392 }
3393
3394 switch (qopt->command) {
3395 case TC_ETS_REPLACE:
3396 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3397 if (ret)
3398 return ret;
3399
3400 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3401 case TC_ETS_DESTROY:
3402 return ksz_tc_ets_del(dev, port);
3403 case TC_ETS_STATS:
3404 case TC_ETS_GRAFT:
3405 return -EOPNOTSUPP;
3406 }
3407
3408 return -EOPNOTSUPP;
3409 }
3410
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)3411 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3412 enum tc_setup_type type, void *type_data)
3413 {
3414 switch (type) {
3415 case TC_SETUP_QDISC_CBS:
3416 return ksz_setup_tc_cbs(ds, port, type_data);
3417 case TC_SETUP_QDISC_ETS:
3418 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3419 default:
3420 return -EOPNOTSUPP;
3421 }
3422 }
3423
3424 static const struct dsa_switch_ops ksz_switch_ops = {
3425 .get_tag_protocol = ksz_get_tag_protocol,
3426 .connect_tag_protocol = ksz_connect_tag_protocol,
3427 .get_phy_flags = ksz_get_phy_flags,
3428 .setup = ksz_setup,
3429 .teardown = ksz_teardown,
3430 .phy_read = ksz_phy_read16,
3431 .phy_write = ksz_phy_write16,
3432 .phylink_get_caps = ksz_phylink_get_caps,
3433 .phylink_mac_config = ksz_phylink_mac_config,
3434 .phylink_mac_link_up = ksz_phylink_mac_link_up,
3435 .phylink_mac_link_down = ksz_mac_link_down,
3436 .port_enable = ksz_enable_port,
3437 .set_ageing_time = ksz_set_ageing_time,
3438 .get_strings = ksz_get_strings,
3439 .get_ethtool_stats = ksz_get_ethtool_stats,
3440 .get_sset_count = ksz_sset_count,
3441 .port_bridge_join = ksz_port_bridge_join,
3442 .port_bridge_leave = ksz_port_bridge_leave,
3443 .port_stp_state_set = ksz_port_stp_state_set,
3444 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3445 .port_bridge_flags = ksz_port_bridge_flags,
3446 .port_fast_age = ksz_port_fast_age,
3447 .port_vlan_filtering = ksz_port_vlan_filtering,
3448 .port_vlan_add = ksz_port_vlan_add,
3449 .port_vlan_del = ksz_port_vlan_del,
3450 .port_fdb_dump = ksz_port_fdb_dump,
3451 .port_fdb_add = ksz_port_fdb_add,
3452 .port_fdb_del = ksz_port_fdb_del,
3453 .port_mdb_add = ksz_port_mdb_add,
3454 .port_mdb_del = ksz_port_mdb_del,
3455 .port_mirror_add = ksz_port_mirror_add,
3456 .port_mirror_del = ksz_port_mirror_del,
3457 .get_stats64 = ksz_get_stats64,
3458 .get_pause_stats = ksz_get_pause_stats,
3459 .port_change_mtu = ksz_change_mtu,
3460 .port_max_mtu = ksz_max_mtu,
3461 .get_ts_info = ksz_get_ts_info,
3462 .port_hwtstamp_get = ksz_hwtstamp_get,
3463 .port_hwtstamp_set = ksz_hwtstamp_set,
3464 .port_txtstamp = ksz_port_txtstamp,
3465 .port_rxtstamp = ksz_port_rxtstamp,
3466 .port_setup_tc = ksz_setup_tc,
3467 .get_mac_eee = ksz_get_mac_eee,
3468 .set_mac_eee = ksz_set_mac_eee,
3469 };
3470
ksz_switch_alloc(struct device * base,void * priv)3471 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3472 {
3473 struct dsa_switch *ds;
3474 struct ksz_device *swdev;
3475
3476 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3477 if (!ds)
3478 return NULL;
3479
3480 ds->dev = base;
3481 ds->num_ports = DSA_MAX_PORTS;
3482 ds->ops = &ksz_switch_ops;
3483
3484 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3485 if (!swdev)
3486 return NULL;
3487
3488 ds->priv = swdev;
3489 swdev->dev = base;
3490
3491 swdev->ds = ds;
3492 swdev->priv = priv;
3493
3494 return swdev;
3495 }
3496 EXPORT_SYMBOL(ksz_switch_alloc);
3497
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)3498 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3499 struct device_node *port_dn)
3500 {
3501 phy_interface_t phy_mode = dev->ports[port_num].interface;
3502 int rx_delay = -1, tx_delay = -1;
3503
3504 if (!phy_interface_mode_is_rgmii(phy_mode))
3505 return;
3506
3507 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3508 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3509
3510 if (rx_delay == -1 && tx_delay == -1) {
3511 dev_warn(dev->dev,
3512 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3513 "please update device tree to specify \"rx-internal-delay-ps\" and "
3514 "\"tx-internal-delay-ps\"",
3515 port_num);
3516
3517 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3518 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3519 rx_delay = 2000;
3520
3521 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3522 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3523 tx_delay = 2000;
3524 }
3525
3526 if (rx_delay < 0)
3527 rx_delay = 0;
3528 if (tx_delay < 0)
3529 tx_delay = 0;
3530
3531 dev->ports[port_num].rgmii_rx_val = rx_delay;
3532 dev->ports[port_num].rgmii_tx_val = tx_delay;
3533 }
3534
ksz_switch_register(struct ksz_device * dev)3535 int ksz_switch_register(struct ksz_device *dev)
3536 {
3537 const struct ksz_chip_data *info;
3538 struct device_node *port, *ports;
3539 phy_interface_t interface;
3540 unsigned int port_num;
3541 int ret;
3542 int i;
3543
3544 if (dev->pdata)
3545 dev->chip_id = dev->pdata->chip_id;
3546
3547 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3548 GPIOD_OUT_LOW);
3549 if (IS_ERR(dev->reset_gpio))
3550 return PTR_ERR(dev->reset_gpio);
3551
3552 if (dev->reset_gpio) {
3553 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3554 usleep_range(10000, 12000);
3555 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3556 msleep(100);
3557 }
3558
3559 mutex_init(&dev->dev_mutex);
3560 mutex_init(&dev->regmap_mutex);
3561 mutex_init(&dev->alu_mutex);
3562 mutex_init(&dev->vlan_mutex);
3563
3564 ret = ksz_switch_detect(dev);
3565 if (ret)
3566 return ret;
3567
3568 info = ksz_lookup_info(dev->chip_id);
3569 if (!info)
3570 return -ENODEV;
3571
3572 /* Update the compatible info with the probed one */
3573 dev->info = info;
3574
3575 dev_info(dev->dev, "found switch: %s, rev %i\n",
3576 dev->info->dev_name, dev->chip_rev);
3577
3578 ret = ksz_check_device_id(dev);
3579 if (ret)
3580 return ret;
3581
3582 dev->dev_ops = dev->info->ops;
3583
3584 ret = dev->dev_ops->init(dev);
3585 if (ret)
3586 return ret;
3587
3588 dev->ports = devm_kzalloc(dev->dev,
3589 dev->info->port_cnt * sizeof(struct ksz_port),
3590 GFP_KERNEL);
3591 if (!dev->ports)
3592 return -ENOMEM;
3593
3594 for (i = 0; i < dev->info->port_cnt; i++) {
3595 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3596 mutex_init(&dev->ports[i].mib.cnt_mutex);
3597 dev->ports[i].mib.counters =
3598 devm_kzalloc(dev->dev,
3599 sizeof(u64) * (dev->info->mib_cnt + 1),
3600 GFP_KERNEL);
3601 if (!dev->ports[i].mib.counters)
3602 return -ENOMEM;
3603
3604 dev->ports[i].ksz_dev = dev;
3605 dev->ports[i].num = i;
3606 }
3607
3608 /* set the real number of ports */
3609 dev->ds->num_ports = dev->info->port_cnt;
3610
3611 /* Host port interface will be self detected, or specifically set in
3612 * device tree.
3613 */
3614 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3615 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3616 if (dev->dev->of_node) {
3617 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3618 if (ret == 0)
3619 dev->compat_interface = interface;
3620 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3621 if (!ports)
3622 ports = of_get_child_by_name(dev->dev->of_node, "ports");
3623 if (ports) {
3624 for_each_available_child_of_node(ports, port) {
3625 if (of_property_read_u32(port, "reg",
3626 &port_num))
3627 continue;
3628 if (!(dev->port_mask & BIT(port_num))) {
3629 of_node_put(port);
3630 of_node_put(ports);
3631 return -EINVAL;
3632 }
3633 of_get_phy_mode(port,
3634 &dev->ports[port_num].interface);
3635
3636 ksz_parse_rgmii_delay(dev, port_num, port);
3637 }
3638 of_node_put(ports);
3639 }
3640 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3641 "microchip,synclko-125");
3642 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3643 "microchip,synclko-disable");
3644 if (dev->synclko_125 && dev->synclko_disable) {
3645 dev_err(dev->dev, "inconsistent synclko settings\n");
3646 return -EINVAL;
3647 }
3648 }
3649
3650 ret = dsa_register_switch(dev->ds);
3651 if (ret) {
3652 dev->dev_ops->exit(dev);
3653 return ret;
3654 }
3655
3656 /* Read MIB counters every 30 seconds to avoid overflow. */
3657 dev->mib_read_interval = msecs_to_jiffies(5000);
3658
3659 /* Start the MIB timer. */
3660 schedule_delayed_work(&dev->mib_read, 0);
3661
3662 return ret;
3663 }
3664 EXPORT_SYMBOL(ksz_switch_register);
3665
ksz_switch_remove(struct ksz_device * dev)3666 void ksz_switch_remove(struct ksz_device *dev)
3667 {
3668 /* timer started */
3669 if (dev->mib_read_interval) {
3670 dev->mib_read_interval = 0;
3671 cancel_delayed_work_sync(&dev->mib_read);
3672 }
3673
3674 dev->dev_ops->exit(dev);
3675 dsa_unregister_switch(dev->ds);
3676
3677 if (dev->reset_gpio)
3678 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3679
3680 }
3681 EXPORT_SYMBOL(ksz_switch_remove);
3682
3683 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3684 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3685 MODULE_LICENSE("GPL");
3686