1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 RTW89_DEF_CHAN_5G(5845, 169), 81 RTW89_DEF_CHAN_5G(5865, 173), 82 RTW89_DEF_CHAN_5G(5885, 177), 83 }; 84 85 static struct ieee80211_channel rtw89_channels_6ghz[] = { 86 RTW89_DEF_CHAN_6G(5955, 1), 87 RTW89_DEF_CHAN_6G(5975, 5), 88 RTW89_DEF_CHAN_6G(5995, 9), 89 RTW89_DEF_CHAN_6G(6015, 13), 90 RTW89_DEF_CHAN_6G(6035, 17), 91 RTW89_DEF_CHAN_6G(6055, 21), 92 RTW89_DEF_CHAN_6G(6075, 25), 93 RTW89_DEF_CHAN_6G(6095, 29), 94 RTW89_DEF_CHAN_6G(6115, 33), 95 RTW89_DEF_CHAN_6G(6135, 37), 96 RTW89_DEF_CHAN_6G(6155, 41), 97 RTW89_DEF_CHAN_6G(6175, 45), 98 RTW89_DEF_CHAN_6G(6195, 49), 99 RTW89_DEF_CHAN_6G(6215, 53), 100 RTW89_DEF_CHAN_6G(6235, 57), 101 RTW89_DEF_CHAN_6G(6255, 61), 102 RTW89_DEF_CHAN_6G(6275, 65), 103 RTW89_DEF_CHAN_6G(6295, 69), 104 RTW89_DEF_CHAN_6G(6315, 73), 105 RTW89_DEF_CHAN_6G(6335, 77), 106 RTW89_DEF_CHAN_6G(6355, 81), 107 RTW89_DEF_CHAN_6G(6375, 85), 108 RTW89_DEF_CHAN_6G(6395, 89), 109 RTW89_DEF_CHAN_6G(6415, 93), 110 RTW89_DEF_CHAN_6G(6435, 97), 111 RTW89_DEF_CHAN_6G(6455, 101), 112 RTW89_DEF_CHAN_6G(6475, 105), 113 RTW89_DEF_CHAN_6G(6495, 109), 114 RTW89_DEF_CHAN_6G(6515, 113), 115 RTW89_DEF_CHAN_6G(6535, 117), 116 RTW89_DEF_CHAN_6G(6555, 121), 117 RTW89_DEF_CHAN_6G(6575, 125), 118 RTW89_DEF_CHAN_6G(6595, 129), 119 RTW89_DEF_CHAN_6G(6615, 133), 120 RTW89_DEF_CHAN_6G(6635, 137), 121 RTW89_DEF_CHAN_6G(6655, 141), 122 RTW89_DEF_CHAN_6G(6675, 145), 123 RTW89_DEF_CHAN_6G(6695, 149), 124 RTW89_DEF_CHAN_6G(6715, 153), 125 RTW89_DEF_CHAN_6G(6735, 157), 126 RTW89_DEF_CHAN_6G(6755, 161), 127 RTW89_DEF_CHAN_6G(6775, 165), 128 RTW89_DEF_CHAN_6G(6795, 169), 129 RTW89_DEF_CHAN_6G(6815, 173), 130 RTW89_DEF_CHAN_6G(6835, 177), 131 RTW89_DEF_CHAN_6G(6855, 181), 132 RTW89_DEF_CHAN_6G(6875, 185), 133 RTW89_DEF_CHAN_6G(6895, 189), 134 RTW89_DEF_CHAN_6G(6915, 193), 135 RTW89_DEF_CHAN_6G(6935, 197), 136 RTW89_DEF_CHAN_6G(6955, 201), 137 RTW89_DEF_CHAN_6G(6975, 205), 138 RTW89_DEF_CHAN_6G(6995, 209), 139 RTW89_DEF_CHAN_6G(7015, 213), 140 RTW89_DEF_CHAN_6G(7035, 217), 141 RTW89_DEF_CHAN_6G(7055, 221), 142 RTW89_DEF_CHAN_6G(7075, 225), 143 RTW89_DEF_CHAN_6G(7095, 229), 144 RTW89_DEF_CHAN_6G(7115, 233), 145 }; 146 147 static struct ieee80211_rate rtw89_bitrates[] = { 148 { .bitrate = 10, .hw_value = 0x00, }, 149 { .bitrate = 20, .hw_value = 0x01, }, 150 { .bitrate = 55, .hw_value = 0x02, }, 151 { .bitrate = 110, .hw_value = 0x03, }, 152 { .bitrate = 60, .hw_value = 0x04, }, 153 { .bitrate = 90, .hw_value = 0x05, }, 154 { .bitrate = 120, .hw_value = 0x06, }, 155 { .bitrate = 180, .hw_value = 0x07, }, 156 { .bitrate = 240, .hw_value = 0x08, }, 157 { .bitrate = 360, .hw_value = 0x09, }, 158 { .bitrate = 480, .hw_value = 0x0a, }, 159 { .bitrate = 540, .hw_value = 0x0b, }, 160 }; 161 162 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 163 { 164 .max = 1, 165 .types = BIT(NL80211_IFTYPE_STATION), 166 }, 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 170 BIT(NL80211_IFTYPE_P2P_GO) | 171 BIT(NL80211_IFTYPE_AP), 172 }, 173 }; 174 175 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 176 { 177 .limits = rtw89_iface_limits, 178 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 179 .max_interfaces = 2, 180 .num_different_channels = 1, 181 } 182 }; 183 rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)184 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 185 { 186 struct ieee80211_rate rate; 187 188 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 189 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 190 return false; 191 } 192 193 rate = rtw89_bitrates[rpt_rate]; 194 *bitrate = rate.bitrate; 195 196 return true; 197 } 198 199 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 200 .band = NL80211_BAND_2GHZ, 201 .channels = rtw89_channels_2ghz, 202 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 203 .bitrates = rtw89_bitrates, 204 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 205 .ht_cap = {0}, 206 .vht_cap = {0}, 207 }; 208 209 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 210 .band = NL80211_BAND_5GHZ, 211 .channels = rtw89_channels_5ghz, 212 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 213 214 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 215 .bitrates = rtw89_bitrates + 4, 216 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 217 .ht_cap = {0}, 218 .vht_cap = {0}, 219 }; 220 221 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 222 .band = NL80211_BAND_6GHZ, 223 .channels = rtw89_channels_6ghz, 224 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 225 226 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 227 .bitrates = rtw89_bitrates + 4, 228 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 229 }; 230 rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)231 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 232 struct rtw89_traffic_stats *stats, 233 struct sk_buff *skb, bool tx) 234 { 235 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 236 237 if (!ieee80211_is_data(hdr->frame_control)) 238 return; 239 240 if (is_broadcast_ether_addr(hdr->addr1) || 241 is_multicast_ether_addr(hdr->addr1)) 242 return; 243 244 if (tx) { 245 stats->tx_cnt++; 246 stats->tx_unicast += skb->len; 247 } else { 248 stats->rx_cnt++; 249 stats->rx_unicast += skb->len; 250 } 251 } 252 rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)253 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 254 { 255 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 256 NL80211_CHAN_NO_HT); 257 } 258 rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)259 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 260 struct rtw89_chan *chan) 261 { 262 struct ieee80211_channel *channel = chandef->chan; 263 enum nl80211_chan_width width = chandef->width; 264 u32 primary_freq, center_freq; 265 u8 center_chan; 266 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 267 u32 offset; 268 u8 band; 269 270 center_chan = channel->hw_value; 271 primary_freq = channel->center_freq; 272 center_freq = chandef->center_freq1; 273 274 switch (width) { 275 case NL80211_CHAN_WIDTH_20_NOHT: 276 case NL80211_CHAN_WIDTH_20: 277 bandwidth = RTW89_CHANNEL_WIDTH_20; 278 break; 279 case NL80211_CHAN_WIDTH_40: 280 bandwidth = RTW89_CHANNEL_WIDTH_40; 281 if (primary_freq > center_freq) { 282 center_chan -= 2; 283 } else { 284 center_chan += 2; 285 } 286 break; 287 case NL80211_CHAN_WIDTH_80: 288 case NL80211_CHAN_WIDTH_160: 289 bandwidth = nl_to_rtw89_bandwidth(width); 290 if (primary_freq > center_freq) { 291 offset = (primary_freq - center_freq - 10) / 20; 292 center_chan -= 2 + offset * 4; 293 } else { 294 offset = (center_freq - primary_freq - 10) / 20; 295 center_chan += 2 + offset * 4; 296 } 297 break; 298 default: 299 center_chan = 0; 300 break; 301 } 302 303 switch (channel->band) { 304 default: 305 case NL80211_BAND_2GHZ: 306 band = RTW89_BAND_2G; 307 break; 308 case NL80211_BAND_5GHZ: 309 band = RTW89_BAND_5G; 310 break; 311 case NL80211_BAND_6GHZ: 312 band = RTW89_BAND_6G; 313 break; 314 } 315 316 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 317 } 318 rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)319 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 320 { 321 struct rtw89_hal *hal = &rtwdev->hal; 322 const struct rtw89_chip_info *chip = rtwdev->chip; 323 const struct rtw89_chan *chan; 324 enum rtw89_sub_entity_idx sub_entity_idx; 325 enum rtw89_sub_entity_idx roc_idx; 326 enum rtw89_phy_idx phy_idx; 327 enum rtw89_entity_mode mode; 328 bool entity_active; 329 330 entity_active = rtw89_get_entity_state(rtwdev); 331 if (!entity_active) 332 return; 333 334 mode = rtw89_get_entity_mode(rtwdev); 335 switch (mode) { 336 case RTW89_ENTITY_MODE_SCC: 337 case RTW89_ENTITY_MODE_MCC: 338 sub_entity_idx = RTW89_SUB_ENTITY_0; 339 break; 340 case RTW89_ENTITY_MODE_MCC_PREPARE: 341 sub_entity_idx = RTW89_SUB_ENTITY_1; 342 break; 343 default: 344 WARN(1, "Invalid ent mode: %d\n", mode); 345 return; 346 } 347 348 roc_idx = atomic_read(&hal->roc_entity_idx); 349 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 350 sub_entity_idx = roc_idx; 351 352 phy_idx = RTW89_PHY_0; 353 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 354 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 355 } 356 rtw89_set_channel(struct rtw89_dev * rtwdev)357 void rtw89_set_channel(struct rtw89_dev *rtwdev) 358 { 359 struct rtw89_hal *hal = &rtwdev->hal; 360 const struct rtw89_chip_info *chip = rtwdev->chip; 361 const struct rtw89_chan_rcd *chan_rcd; 362 const struct rtw89_chan *chan; 363 enum rtw89_sub_entity_idx sub_entity_idx; 364 enum rtw89_sub_entity_idx roc_idx; 365 enum rtw89_mac_idx mac_idx; 366 enum rtw89_phy_idx phy_idx; 367 struct rtw89_channel_help_params bak; 368 enum rtw89_entity_mode mode; 369 bool entity_active; 370 371 entity_active = rtw89_get_entity_state(rtwdev); 372 373 mode = rtw89_entity_recalc(rtwdev); 374 switch (mode) { 375 case RTW89_ENTITY_MODE_SCC: 376 case RTW89_ENTITY_MODE_MCC: 377 sub_entity_idx = RTW89_SUB_ENTITY_0; 378 break; 379 case RTW89_ENTITY_MODE_MCC_PREPARE: 380 sub_entity_idx = RTW89_SUB_ENTITY_1; 381 break; 382 default: 383 WARN(1, "Invalid ent mode: %d\n", mode); 384 return; 385 } 386 387 roc_idx = atomic_read(&hal->roc_entity_idx); 388 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 389 sub_entity_idx = roc_idx; 390 391 mac_idx = RTW89_MAC_0; 392 phy_idx = RTW89_PHY_0; 393 394 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 395 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 396 397 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 398 399 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 400 401 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 402 403 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 404 405 if (!entity_active || chan_rcd->band_changed) { 406 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 407 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 408 } 409 410 rtw89_set_entity_state(rtwdev, true); 411 } 412 rtw89_get_channel(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_chan * chan)413 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 414 struct rtw89_chan *chan) 415 { 416 const struct cfg80211_chan_def *chandef; 417 418 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 419 rtw89_get_channel_params(chandef, chan); 420 } 421 422 static enum rtw89_core_tx_type rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)423 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 424 struct sk_buff *skb) 425 { 426 struct ieee80211_hdr *hdr = (void *)skb->data; 427 __le16 fc = hdr->frame_control; 428 429 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 430 return RTW89_CORE_TX_TYPE_MGMT; 431 432 return RTW89_CORE_TX_TYPE_DATA; 433 } 434 435 static void rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)436 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 437 struct rtw89_core_tx_request *tx_req, 438 enum btc_pkt_type pkt_type) 439 { 440 struct ieee80211_sta *sta = tx_req->sta; 441 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 442 struct sk_buff *skb = tx_req->skb; 443 struct rtw89_sta *rtwsta; 444 u8 ampdu_num; 445 u8 tid; 446 447 if (pkt_type == PACKET_EAPOL) { 448 desc_info->bk = true; 449 return; 450 } 451 452 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 453 return; 454 455 if (!sta) { 456 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 457 return; 458 } 459 460 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 461 rtwsta = (struct rtw89_sta *)sta->drv_priv; 462 463 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 464 rtwsta->ampdu_params[tid].agg_num : 465 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 466 467 desc_info->agg_en = true; 468 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 469 desc_info->ampdu_num = ampdu_num; 470 } 471 472 static void rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)473 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 474 struct rtw89_core_tx_request *tx_req) 475 { 476 const struct rtw89_chip_info *chip = rtwdev->chip; 477 struct ieee80211_vif *vif = tx_req->vif; 478 struct ieee80211_sta *sta = tx_req->sta; 479 struct ieee80211_tx_info *info; 480 struct ieee80211_key_conf *key; 481 struct rtw89_vif *rtwvif; 482 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 483 struct rtw89_addr_cam_entry *addr_cam; 484 struct rtw89_sec_cam_entry *sec_cam; 485 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 486 struct sk_buff *skb = tx_req->skb; 487 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 488 u64 pn64; 489 490 if (!vif) { 491 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 492 return; 493 } 494 495 rtwvif = (struct rtw89_vif *)vif->drv_priv; 496 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 497 498 info = IEEE80211_SKB_CB(skb); 499 key = info->control.hw_key; 500 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 501 if (!sec_cam) { 502 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 503 return; 504 } 505 506 switch (key->cipher) { 507 case WLAN_CIPHER_SUITE_WEP40: 508 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 509 break; 510 case WLAN_CIPHER_SUITE_WEP104: 511 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 512 break; 513 case WLAN_CIPHER_SUITE_TKIP: 514 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 515 break; 516 case WLAN_CIPHER_SUITE_CCMP: 517 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 518 break; 519 case WLAN_CIPHER_SUITE_CCMP_256: 520 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 521 break; 522 case WLAN_CIPHER_SUITE_GCMP: 523 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 524 break; 525 case WLAN_CIPHER_SUITE_GCMP_256: 526 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 527 break; 528 default: 529 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 530 return; 531 } 532 533 desc_info->sec_en = true; 534 desc_info->sec_keyid = key->keyidx; 535 desc_info->sec_type = sec_type; 536 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 537 538 if (!chip->hw_sec_hdr) 539 return; 540 541 pn64 = atomic64_inc_return(&key->tx_pn); 542 desc_info->sec_seq[0] = pn64; 543 desc_info->sec_seq[1] = pn64 >> 8; 544 desc_info->sec_seq[2] = pn64 >> 16; 545 desc_info->sec_seq[3] = pn64 >> 24; 546 desc_info->sec_seq[4] = pn64 >> 32; 547 desc_info->sec_seq[5] = pn64 >> 40; 548 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 549 } 550 rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)551 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 552 struct rtw89_core_tx_request *tx_req, 553 const struct rtw89_chan *chan) 554 { 555 struct sk_buff *skb = tx_req->skb; 556 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 557 struct ieee80211_vif *vif = tx_info->control.vif; 558 u16 lowest_rate; 559 560 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 561 (vif && vif->p2p)) 562 lowest_rate = RTW89_HW_RATE_OFDM6; 563 else if (chan->band_type == RTW89_BAND_2G) 564 lowest_rate = RTW89_HW_RATE_CCK1; 565 else 566 lowest_rate = RTW89_HW_RATE_OFDM6; 567 568 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 569 return lowest_rate; 570 571 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 572 } 573 rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)574 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 575 struct rtw89_core_tx_request *tx_req) 576 { 577 struct ieee80211_vif *vif = tx_req->vif; 578 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 579 struct ieee80211_sta *sta = tx_req->sta; 580 struct rtw89_sta *rtwsta; 581 582 if (!sta) 583 return rtwvif->mac_id; 584 585 rtwsta = (struct rtw89_sta *)sta->drv_priv; 586 return rtwsta->mac_id; 587 } 588 589 static void rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)590 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 591 struct rtw89_core_tx_request *tx_req) 592 { 593 struct ieee80211_vif *vif = tx_req->vif; 594 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 595 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 596 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 597 rtwvif->sub_entity_idx); 598 u8 qsel, ch_dma; 599 600 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 601 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 602 603 desc_info->qsel = qsel; 604 desc_info->ch_dma = ch_dma; 605 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 606 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 607 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 608 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 609 610 /* fixed data rate for mgmt frames */ 611 desc_info->en_wd_info = true; 612 desc_info->use_rate = true; 613 desc_info->dis_data_fb = true; 614 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 615 616 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 617 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 618 desc_info->data_rate, chan->channel, chan->band_type, 619 chan->band_width); 620 } 621 622 static void rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)623 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 624 struct rtw89_core_tx_request *tx_req) 625 { 626 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 627 628 desc_info->is_bmc = false; 629 desc_info->wd_page = false; 630 desc_info->ch_dma = RTW89_DMA_H2C; 631 } 632 rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)633 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 634 const struct rtw89_chan *chan) 635 { 636 static const u8 rtw89_bandwidth_to_om[] = { 637 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 638 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 639 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 640 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 641 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 642 }; 643 const struct rtw89_chip_info *chip = rtwdev->chip; 644 struct rtw89_hal *hal = &rtwdev->hal; 645 u8 om_bandwidth; 646 647 if (!chip->dis_2g_40m_ul_ofdma || 648 chan->band_type != RTW89_BAND_2G || 649 chan->band_width != RTW89_CHANNEL_WIDTH_40) 650 return; 651 652 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 653 rtw89_bandwidth_to_om[chan->band_width] : 0; 654 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 655 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 656 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 657 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 658 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 659 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 660 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 661 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 662 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 663 } 664 665 static bool __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)666 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 667 struct rtw89_core_tx_request *tx_req, 668 enum btc_pkt_type pkt_type) 669 { 670 struct ieee80211_sta *sta = tx_req->sta; 671 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 672 struct sk_buff *skb = tx_req->skb; 673 struct ieee80211_hdr *hdr = (void *)skb->data; 674 __le16 fc = hdr->frame_control; 675 676 /* AP IOT issue with EAPoL, ARP and DHCP */ 677 if (pkt_type < PACKET_MAX) 678 return false; 679 680 if (!sta || !sta->deflink.he_cap.has_he) 681 return false; 682 683 if (!ieee80211_is_data_qos(fc)) 684 return false; 685 686 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 687 return false; 688 689 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 690 return false; 691 692 return true; 693 } 694 695 static void __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)696 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 697 struct rtw89_core_tx_request *tx_req) 698 { 699 struct ieee80211_sta *sta = tx_req->sta; 700 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 701 struct sk_buff *skb = tx_req->skb; 702 struct ieee80211_hdr *hdr = (void *)skb->data; 703 __le16 fc = hdr->frame_control; 704 void *data; 705 __le32 *htc; 706 u8 *qc; 707 int hdr_len; 708 709 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 710 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 711 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 712 713 hdr = data; 714 htc = data + hdr_len; 715 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 716 *htc = rtwsta->htc_template ? rtwsta->htc_template : 717 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 718 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 719 720 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 721 qc[0] |= IEEE80211_QOS_CTL_EOSP; 722 } 723 724 static void rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)725 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 726 struct rtw89_core_tx_request *tx_req, 727 enum btc_pkt_type pkt_type) 728 { 729 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 730 struct ieee80211_vif *vif = tx_req->vif; 731 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 732 733 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 734 goto desc_bk; 735 736 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 737 738 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 739 desc_info->a_ctrl_bsr = true; 740 741 desc_bk: 742 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 743 return; 744 745 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 746 desc_info->bk = true; 747 } 748 rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)749 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 750 struct rtw89_core_tx_request *tx_req) 751 { 752 struct ieee80211_vif *vif = tx_req->vif; 753 struct ieee80211_sta *sta = tx_req->sta; 754 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 755 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 756 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 757 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 758 u16 lowest_rate; 759 760 if (rate_pattern->enable) 761 return rate_pattern->rate; 762 763 if (vif->p2p) 764 lowest_rate = RTW89_HW_RATE_OFDM6; 765 else if (chan->band_type == RTW89_BAND_2G) 766 lowest_rate = RTW89_HW_RATE_CCK1; 767 else 768 lowest_rate = RTW89_HW_RATE_OFDM6; 769 770 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 771 return lowest_rate; 772 773 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 774 } 775 776 static void rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)777 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 778 struct rtw89_core_tx_request *tx_req) 779 { 780 struct ieee80211_vif *vif = tx_req->vif; 781 struct ieee80211_sta *sta = tx_req->sta; 782 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 783 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 784 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 785 struct sk_buff *skb = tx_req->skb; 786 u8 tid, tid_indicate; 787 u8 qsel, ch_dma; 788 789 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 790 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 791 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 792 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 793 794 desc_info->ch_dma = ch_dma; 795 desc_info->tid_indicate = tid_indicate; 796 desc_info->qsel = qsel; 797 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 798 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 799 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 800 801 /* enable wd_info for AMPDU */ 802 desc_info->en_wd_info = true; 803 804 if (IEEE80211_SKB_CB(skb)->control.hw_key) 805 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 806 807 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 808 } 809 810 static enum btc_pkt_type rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)811 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 812 struct rtw89_core_tx_request *tx_req) 813 { 814 struct sk_buff *skb = tx_req->skb; 815 struct udphdr *udphdr; 816 817 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 818 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 819 return PACKET_EAPOL; 820 } 821 822 if (skb->protocol == htons(ETH_P_ARP)) { 823 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 824 return PACKET_ARP; 825 } 826 827 if (skb->protocol == htons(ETH_P_IP) && 828 ip_hdr(skb)->protocol == IPPROTO_UDP) { 829 udphdr = udp_hdr(skb); 830 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 831 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 832 skb->len > 282) { 833 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 834 return PACKET_DHCP; 835 } 836 } 837 838 if (skb->protocol == htons(ETH_P_IP) && 839 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 840 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 841 return PACKET_ICMP; 842 } 843 844 return PACKET_MAX; 845 } 846 rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)847 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 848 struct rtw89_tx_desc_info *desc_info, 849 struct sk_buff *skb) 850 { 851 struct ieee80211_hdr *hdr = (void *)skb->data; 852 __le16 fc = hdr->frame_control; 853 854 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 855 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 856 } 857 858 static void rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)859 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 860 struct rtw89_core_tx_request *tx_req) 861 { 862 const struct rtw89_chip_info *chip = rtwdev->chip; 863 864 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 865 return; 866 867 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 868 return; 869 870 if (chip->chip_id != RTL8852C && 871 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 872 return; 873 874 rtw89_mac_notify_wake(rtwdev); 875 } 876 877 static void rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)878 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 879 struct rtw89_core_tx_request *tx_req) 880 { 881 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 882 struct sk_buff *skb = tx_req->skb; 883 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 884 struct ieee80211_hdr *hdr = (void *)skb->data; 885 enum rtw89_core_tx_type tx_type; 886 enum btc_pkt_type pkt_type; 887 bool is_bmc; 888 u16 seq; 889 890 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 891 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 892 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 893 tx_req->tx_type = tx_type; 894 } 895 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 896 is_multicast_ether_addr(hdr->addr1)); 897 898 desc_info->seq = seq; 899 desc_info->pkt_size = skb->len; 900 desc_info->is_bmc = is_bmc; 901 desc_info->wd_page = true; 902 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 903 904 switch (tx_req->tx_type) { 905 case RTW89_CORE_TX_TYPE_MGMT: 906 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 907 break; 908 case RTW89_CORE_TX_TYPE_DATA: 909 rtw89_core_tx_update_data_info(rtwdev, tx_req); 910 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 911 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 912 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 913 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 914 break; 915 case RTW89_CORE_TX_TYPE_FWCMD: 916 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 917 break; 918 } 919 } 920 rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)921 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 922 { 923 u8 ch_dma; 924 925 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 926 927 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 928 } 929 rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)930 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 931 int qsel, unsigned int timeout) 932 { 933 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 934 struct rtw89_tx_wait_info *wait; 935 unsigned long time_left; 936 int ret = 0; 937 938 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 939 if (!wait) { 940 rtw89_core_tx_kick_off(rtwdev, qsel); 941 return 0; 942 } 943 944 init_completion(&wait->completion); 945 rcu_assign_pointer(skb_data->wait, wait); 946 947 rtw89_core_tx_kick_off(rtwdev, qsel); 948 time_left = wait_for_completion_timeout(&wait->completion, 949 msecs_to_jiffies(timeout)); 950 if (time_left == 0) 951 ret = -ETIMEDOUT; 952 else if (!wait->tx_done) 953 ret = -EAGAIN; 954 955 rcu_assign_pointer(skb_data->wait, NULL); 956 kfree_rcu(wait, rcu_head); 957 958 return ret; 959 } 960 rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)961 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 962 struct sk_buff *skb, bool fwdl) 963 { 964 struct rtw89_core_tx_request tx_req = {0}; 965 u32 cnt; 966 int ret; 967 968 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 969 rtw89_debug(rtwdev, RTW89_DBG_FW, 970 "ignore h2c due to power is off with firmware state=%d\n", 971 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 972 dev_kfree_skb(skb); 973 return 0; 974 } 975 976 tx_req.skb = skb; 977 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 978 if (fwdl) 979 tx_req.desc_info.fw_dl = true; 980 981 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 982 983 if (!fwdl) 984 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 985 986 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 987 if (cnt == 0) { 988 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 989 return -ENOSPC; 990 } 991 992 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 993 if (ret) { 994 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 995 return ret; 996 } 997 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 998 999 return 0; 1000 } 1001 rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1002 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1003 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1004 { 1005 struct rtw89_core_tx_request tx_req = {0}; 1006 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1007 int ret; 1008 1009 tx_req.skb = skb; 1010 tx_req.sta = sta; 1011 tx_req.vif = vif; 1012 1013 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1014 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1015 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1016 rtw89_core_tx_wake(rtwdev, &tx_req); 1017 1018 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1019 if (ret) { 1020 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1021 return ret; 1022 } 1023 1024 if (qsel) 1025 *qsel = tx_req.desc_info.qsel; 1026 1027 return 0; 1028 } 1029 rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1030 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1031 { 1032 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1033 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1034 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1035 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1036 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1037 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1038 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1039 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1040 1041 return cpu_to_le32(dword); 1042 } 1043 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1044 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1045 { 1046 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1047 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1048 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1049 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1050 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1051 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1052 1053 return cpu_to_le32(dword); 1054 } 1055 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1056 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1057 { 1058 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1059 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1060 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1061 1062 return cpu_to_le32(dword); 1063 } 1064 rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1065 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1066 { 1067 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1068 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1069 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1070 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1071 1072 return cpu_to_le32(dword); 1073 } 1074 rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1075 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1076 { 1077 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1078 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1079 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1080 1081 return cpu_to_le32(dword); 1082 } 1083 rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1084 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1085 { 1086 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1087 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1088 1089 return cpu_to_le32(dword); 1090 } 1091 rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1092 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1093 { 1094 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1095 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1096 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1097 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1098 1099 return cpu_to_le32(dword); 1100 } 1101 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1102 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1105 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1110 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1113 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1114 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1115 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1116 1117 return cpu_to_le32(dword); 1118 } 1119 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1120 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1121 { 1122 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1123 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1124 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1125 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1126 1127 return cpu_to_le32(dword); 1128 } 1129 rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1130 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1131 { 1132 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1133 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1134 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1135 desc_info->data_retry_lowest_rate); 1136 1137 return cpu_to_le32(dword); 1138 } 1139 rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1140 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1141 { 1142 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1143 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1144 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1145 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1146 1147 return cpu_to_le32(dword); 1148 } 1149 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1150 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1151 { 1152 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1153 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1154 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1155 1156 return cpu_to_le32(dword); 1157 } 1158 rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1159 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1160 { 1161 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1162 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1163 1164 return cpu_to_le32(dword); 1165 } 1166 rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1167 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1168 struct rtw89_tx_desc_info *desc_info, 1169 void *txdesc) 1170 { 1171 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1172 struct rtw89_txwd_info *txwd_info; 1173 1174 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1175 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1176 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1177 1178 if (!desc_info->en_wd_info) 1179 return; 1180 1181 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1182 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1183 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1184 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1185 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1186 1187 } 1188 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1189 rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1190 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1191 struct rtw89_tx_desc_info *desc_info, 1192 void *txdesc) 1193 { 1194 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1195 struct rtw89_txwd_info *txwd_info; 1196 1197 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1198 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1199 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1200 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1201 if (desc_info->sec_en) { 1202 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1203 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1204 } 1205 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1206 1207 if (!desc_info->en_wd_info) 1208 return; 1209 1210 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1211 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1212 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1213 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1214 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1215 } 1216 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1217 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1218 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1219 { 1220 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1221 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1222 RTW89_CORE_RX_TYPE_FWDL : 1223 RTW89_CORE_RX_TYPE_H2C); 1224 1225 return cpu_to_le32(dword); 1226 } 1227 rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1228 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1229 struct rtw89_tx_desc_info *desc_info, 1230 void *txdesc) 1231 { 1232 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1233 1234 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1235 } 1236 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1237 rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1238 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1239 struct sk_buff *skb, 1240 struct rtw89_rx_phy_ppdu *phy_ppdu) 1241 { 1242 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1243 bool rx_cnt_valid = false; 1244 u8 plcp_size = 0; 1245 u8 usr_num = 0; 1246 u8 *phy_sts; 1247 1248 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1249 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1250 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1251 if (usr_num > RTW89_PPDU_MAX_USR) { 1252 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1253 return -EINVAL; 1254 } 1255 1256 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1257 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1258 /* 8-byte alignment */ 1259 if (usr_num & BIT(0)) 1260 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1261 if (rx_cnt_valid) 1262 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1263 phy_sts += plcp_size; 1264 1265 phy_ppdu->buf = phy_sts; 1266 phy_ppdu->len = skb->data + skb->len - phy_sts; 1267 1268 return 0; 1269 } 1270 rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1271 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1272 struct ieee80211_sta *sta) 1273 { 1274 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1275 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1276 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1277 struct rtw89_hal *hal = &rtwdev->hal; 1278 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1279 u8 ant_pos = U8_MAX; 1280 u8 evm_pos = 0; 1281 int i; 1282 1283 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1284 return; 1285 1286 if (hal->ant_diversity && hal->antenna_rx) { 1287 ant_pos = __ffs(hal->antenna_rx); 1288 evm_pos = ant_pos; 1289 } 1290 1291 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1292 1293 if (ant_pos < ant_num) { 1294 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1295 } else { 1296 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1297 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1298 } 1299 1300 if (phy_ppdu->ofdm.has) { 1301 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1302 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1303 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1304 } 1305 } 1306 1307 #define VAR_LEN 0xff 1308 #define VAR_LEN_UNIT 8 rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1309 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1310 const struct rtw89_phy_sts_iehdr *iehdr) 1311 { 1312 static const u8 physts_ie_len_tab[32] = { 1313 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1314 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1315 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1316 }; 1317 u16 ie_len; 1318 u8 ie; 1319 1320 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1321 if (physts_ie_len_tab[ie] != VAR_LEN) 1322 ie_len = physts_ie_len_tab[ie]; 1323 else 1324 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1325 1326 return ie_len; 1327 } 1328 rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1329 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1330 const struct rtw89_phy_sts_iehdr *iehdr, 1331 struct rtw89_rx_phy_ppdu *phy_ppdu) 1332 { 1333 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1334 s16 cfo; 1335 u32 t; 1336 1337 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1338 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1339 return; 1340 1341 if (!phy_ppdu->to_self) 1342 return; 1343 1344 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1345 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1346 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1347 phy_ppdu->ofdm.has = true; 1348 1349 /* sign conversion for S(12,2) */ 1350 if (rtwdev->chip->cfo_src_fd) { 1351 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1352 cfo = sign_extend32(t, 11); 1353 } else { 1354 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1355 cfo = sign_extend32(t, 11); 1356 } 1357 1358 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1359 } 1360 rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1361 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1362 const struct rtw89_phy_sts_iehdr *iehdr, 1363 struct rtw89_rx_phy_ppdu *phy_ppdu) 1364 { 1365 u8 ie; 1366 1367 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1368 1369 switch (ie) { 1370 case RTW89_PHYSTS_IE01_CMN_OFDM: 1371 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1372 break; 1373 default: 1374 break; 1375 } 1376 1377 return 0; 1378 } 1379 rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1380 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1381 { 1382 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1383 u8 *rssi = phy_ppdu->rssi; 1384 1385 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1386 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1387 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1388 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1389 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1390 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1391 } 1392 rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1393 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1394 struct rtw89_rx_phy_ppdu *phy_ppdu) 1395 { 1396 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1397 u32 len_from_header; 1398 1399 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1400 1401 if (len_from_header != phy_ppdu->len) { 1402 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1403 return -EINVAL; 1404 } 1405 rtw89_core_update_phy_ppdu(phy_ppdu); 1406 1407 return 0; 1408 } 1409 rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1410 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1411 struct rtw89_rx_phy_ppdu *phy_ppdu) 1412 { 1413 u16 ie_len; 1414 void *pos, *end; 1415 1416 /* mark invalid reports and bypass them */ 1417 if (phy_ppdu->ie < RTW89_CCK_PKT) 1418 return -EINVAL; 1419 1420 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1421 end = phy_ppdu->buf + phy_ppdu->len; 1422 while (pos < end) { 1423 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1424 1425 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1426 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1427 pos += ie_len; 1428 if (pos > end || ie_len == 0) { 1429 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1430 "phy status parse failed\n"); 1431 return -EINVAL; 1432 } 1433 } 1434 1435 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1436 1437 return 0; 1438 } 1439 rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1440 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1441 struct rtw89_rx_phy_ppdu *phy_ppdu) 1442 { 1443 int ret; 1444 1445 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1446 if (ret) 1447 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1448 else 1449 phy_ppdu->valid = true; 1450 1451 ieee80211_iterate_stations_atomic(rtwdev->hw, 1452 rtw89_core_rx_process_phy_ppdu_iter, 1453 phy_ppdu); 1454 } 1455 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,const struct rtw89_rx_desc_info * desc_info,bool rx_status)1456 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1457 const struct rtw89_rx_desc_info *desc_info, 1458 bool rx_status) 1459 { 1460 switch (desc_info->gi_ltf) { 1461 case RTW89_GILTF_SGI_4XHE08: 1462 case RTW89_GILTF_2XHE08: 1463 case RTW89_GILTF_1XHE08: 1464 return NL80211_RATE_INFO_HE_GI_0_8; 1465 case RTW89_GILTF_2XHE16: 1466 case RTW89_GILTF_1XHE16: 1467 return NL80211_RATE_INFO_HE_GI_1_6; 1468 case RTW89_GILTF_LGI_4XHE32: 1469 return NL80211_RATE_INFO_HE_GI_3_2; 1470 default: 1471 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1472 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1473 } 1474 } 1475 rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1476 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1477 struct rtw89_rx_desc_info *desc_info, 1478 struct ieee80211_rx_status *status) 1479 { 1480 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1481 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1482 u16 data_rate; 1483 bool ret; 1484 1485 data_rate = desc_info->data_rate; 1486 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1487 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1488 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1489 /* rate_idx is still hardware value here */ 1490 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1491 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1492 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1493 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1494 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1495 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1496 } else { 1497 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1498 } 1499 1500 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1501 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1502 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1503 status->rate_idx == rate_idx && 1504 status->he_gi == gi_ltf && 1505 status->bw == bw; 1506 1507 return ret; 1508 } 1509 1510 struct rtw89_vif_rx_stats_iter_data { 1511 struct rtw89_dev *rtwdev; 1512 struct rtw89_rx_phy_ppdu *phy_ppdu; 1513 struct rtw89_rx_desc_info *desc_info; 1514 struct sk_buff *skb; 1515 const u8 *bssid; 1516 }; 1517 rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct sk_buff * skb)1518 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1519 struct ieee80211_vif *vif, 1520 struct sk_buff *skb) 1521 { 1522 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1523 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1524 u8 *pos, *end, type; 1525 u16 aid; 1526 1527 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1528 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1529 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1530 return; 1531 1532 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1533 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1534 return; 1535 1536 end = (u8 *)tf + skb->len; 1537 pos = tf->variable; 1538 1539 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1540 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1541 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1542 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1543 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1544 RTW89_GET_TF_USER_INFO_RUA(pos)); 1545 1546 if (aid == RTW89_TF_PAD) 1547 break; 1548 1549 if (aid == vif->cfg.aid) { 1550 rtwvif->stats.rx_tf_acc++; 1551 rtwdev->stats.rx_tf_acc++; 1552 break; 1553 } 1554 1555 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1556 } 1557 } 1558 rtw89_cancel_6ghz_probe_work(struct work_struct * work)1559 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1560 { 1561 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1562 cancel_6ghz_probe_work); 1563 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1564 struct rtw89_pktofld_info *info; 1565 1566 mutex_lock(&rtwdev->mutex); 1567 1568 if (!rtwdev->scanning) 1569 goto out; 1570 1571 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1572 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1573 continue; 1574 1575 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1576 1577 /* Don't delete/free info from pkt_list at this moment. Let it 1578 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1579 * since if during scanning, pkt_list is accessed in bottom half. 1580 */ 1581 } 1582 1583 out: 1584 mutex_unlock(&rtwdev->mutex); 1585 } 1586 rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)1587 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1588 struct sk_buff *skb) 1589 { 1590 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1591 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1592 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1593 struct rtw89_pktofld_info *info; 1594 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1595 bool queue_work = false; 1596 1597 if (rx_status->band != NL80211_BAND_6GHZ) 1598 return; 1599 1600 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1601 1602 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1603 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1604 info->cancel = true; 1605 queue_work = true; 1606 continue; 1607 } 1608 1609 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1610 continue; 1611 1612 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1613 info->cancel = true; 1614 queue_work = true; 1615 } 1616 } 1617 1618 if (queue_work) 1619 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1620 } 1621 rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1622 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1623 struct ieee80211_vif *vif) 1624 { 1625 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1626 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1627 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1628 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1629 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1630 struct sk_buff *skb = iter_data->skb; 1631 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1632 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1633 const u8 *bssid = iter_data->bssid; 1634 1635 if (rtwdev->scanning && 1636 (ieee80211_is_beacon(hdr->frame_control) || 1637 ieee80211_is_probe_resp(hdr->frame_control))) 1638 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1639 1640 if (!vif->bss_conf.bssid) 1641 return; 1642 1643 if (ieee80211_is_trigger(hdr->frame_control)) { 1644 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1645 return; 1646 } 1647 1648 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1649 return; 1650 1651 if (ieee80211_is_beacon(hdr->frame_control)) { 1652 if (vif->type == NL80211_IFTYPE_STATION) 1653 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1654 pkt_stat->beacon_nr++; 1655 } 1656 1657 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1658 return; 1659 1660 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1661 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1662 1663 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1664 } 1665 rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1666 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1667 struct rtw89_rx_phy_ppdu *phy_ppdu, 1668 struct rtw89_rx_desc_info *desc_info, 1669 struct sk_buff *skb) 1670 { 1671 struct rtw89_vif_rx_stats_iter_data iter_data; 1672 1673 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1674 1675 iter_data.rtwdev = rtwdev; 1676 iter_data.phy_ppdu = phy_ppdu; 1677 iter_data.desc_info = desc_info; 1678 iter_data.skb = skb; 1679 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1680 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1681 } 1682 rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)1683 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1684 struct ieee80211_rx_status *status) 1685 { 1686 const struct rtw89_chan_rcd *rcd = 1687 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1688 u16 chan = rcd->prev_primary_channel; 1689 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1690 1691 if (status->band != NL80211_BAND_2GHZ && 1692 status->encoding == RX_ENC_LEGACY && 1693 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1694 status->freq = ieee80211_channel_to_frequency(chan, band); 1695 status->band = band; 1696 } 1697 } 1698 rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)1699 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1700 { 1701 if (rx_status->band == NL80211_BAND_2GHZ || 1702 rx_status->encoding != RX_ENC_LEGACY) 1703 return; 1704 1705 /* Some control frames' freq(ACKs in this case) are reported wrong due 1706 * to FW notify timing, set to lowest rate to prevent overflow. 1707 */ 1708 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1709 rx_status->rate_idx = 0; 1710 return; 1711 } 1712 1713 /* No 4 CCK rates for non-2G */ 1714 rx_status->rate_idx -= 4; 1715 } 1716 rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)1717 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 1718 struct sk_buff *skb, 1719 struct ieee80211_rx_status *rx_status) 1720 { 1721 static const struct ieee80211_radiotap_he known_he = { 1722 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1723 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1724 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1725 }; 1726 struct ieee80211_radiotap_he *he; 1727 1728 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1729 return; 1730 1731 if (rx_status->encoding == RX_ENC_HE) { 1732 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 1733 he = skb_push(skb, sizeof(*he)); 1734 *he = known_he; 1735 } 1736 } 1737 rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)1738 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1739 struct rtw89_rx_phy_ppdu *phy_ppdu, 1740 struct rtw89_rx_desc_info *desc_info, 1741 struct sk_buff *skb_ppdu, 1742 struct ieee80211_rx_status *rx_status) 1743 { 1744 struct napi_struct *napi = &rtwdev->napi; 1745 1746 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1747 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1748 napi = NULL; 1749 1750 rtw89_core_hw_to_sband_rate(rx_status); 1751 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1752 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 1753 /* In low power mode, it does RX in thread context. */ 1754 local_bh_disable(); 1755 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1756 local_bh_enable(); 1757 rtwdev->napi_budget_countdown--; 1758 } 1759 rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1760 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1761 struct rtw89_rx_phy_ppdu *phy_ppdu, 1762 struct rtw89_rx_desc_info *desc_info, 1763 struct sk_buff *skb) 1764 { 1765 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1766 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1767 struct sk_buff *skb_ppdu = NULL, *tmp; 1768 struct ieee80211_rx_status *rx_status; 1769 1770 if (curr > RTW89_MAX_PPDU_CNT) 1771 return; 1772 1773 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1774 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1775 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1776 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1777 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1778 rtw89_correct_cck_chan(rtwdev, rx_status); 1779 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1780 } 1781 } 1782 rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1783 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1784 struct rtw89_rx_desc_info *desc_info, 1785 struct sk_buff *skb) 1786 { 1787 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1788 .len = skb->len, 1789 .to_self = desc_info->addr1_match, 1790 .rate = desc_info->data_rate, 1791 .mac_id = desc_info->mac_id}; 1792 int ret; 1793 1794 if (desc_info->mac_info_valid) 1795 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1796 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1797 if (ret) 1798 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1799 1800 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1801 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1802 dev_kfree_skb_any(skb); 1803 } 1804 rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1805 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1806 struct rtw89_rx_desc_info *desc_info, 1807 struct sk_buff *skb) 1808 { 1809 switch (desc_info->pkt_type) { 1810 case RTW89_CORE_RX_TYPE_C2H: 1811 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1812 break; 1813 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1814 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1815 break; 1816 default: 1817 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1818 desc_info->pkt_type); 1819 dev_kfree_skb_any(skb); 1820 break; 1821 } 1822 } 1823 rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)1824 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1825 struct rtw89_rx_desc_info *desc_info, 1826 u8 *data, u32 data_offset) 1827 { 1828 const struct rtw89_chip_info *chip = rtwdev->chip; 1829 struct rtw89_rxdesc_short *rxd_s; 1830 struct rtw89_rxdesc_long *rxd_l; 1831 u8 shift_len, drv_info_len; 1832 1833 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1834 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 1835 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 1836 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 1837 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 1838 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 1839 if (chip->chip_id == RTL8852C) 1840 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 1841 else 1842 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 1843 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 1844 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 1845 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 1846 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 1847 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 1848 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 1849 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 1850 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 1851 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 1852 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 1853 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 1854 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 1855 1856 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1857 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1858 desc_info->offset = data_offset + shift_len + drv_info_len; 1859 if (desc_info->long_rxdesc) 1860 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 1861 else 1862 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 1863 desc_info->ready = true; 1864 1865 if (!desc_info->long_rxdesc) 1866 return; 1867 1868 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1869 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 1870 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 1871 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 1872 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 1873 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 1874 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 1875 } 1876 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1877 1878 struct rtw89_core_iter_rx_status { 1879 struct rtw89_dev *rtwdev; 1880 struct ieee80211_rx_status *rx_status; 1881 struct rtw89_rx_desc_info *desc_info; 1882 u8 mac_id; 1883 }; 1884 1885 static rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)1886 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1887 { 1888 struct rtw89_core_iter_rx_status *iter_data = 1889 (struct rtw89_core_iter_rx_status *)data; 1890 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1891 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1892 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1893 u8 mac_id = iter_data->mac_id; 1894 1895 if (mac_id != rtwsta->mac_id) 1896 return; 1897 1898 rtwsta->rx_status = *rx_status; 1899 rtwsta->rx_hw_rate = desc_info->data_rate; 1900 } 1901 rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1902 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1903 struct rtw89_rx_desc_info *desc_info, 1904 struct ieee80211_rx_status *rx_status) 1905 { 1906 struct rtw89_core_iter_rx_status iter_data; 1907 1908 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1909 return; 1910 1911 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1912 return; 1913 1914 iter_data.rtwdev = rtwdev; 1915 iter_data.rx_status = rx_status; 1916 iter_data.desc_info = desc_info; 1917 iter_data.mac_id = desc_info->mac_id; 1918 ieee80211_iterate_stations_atomic(rtwdev->hw, 1919 rtw89_core_stats_sta_rx_status_iter, 1920 &iter_data); 1921 } 1922 rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1923 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1924 struct rtw89_rx_desc_info *desc_info, 1925 struct ieee80211_rx_status *rx_status) 1926 { 1927 const struct cfg80211_chan_def *chandef = 1928 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1929 u16 data_rate; 1930 u8 data_rate_mode; 1931 1932 /* currently using single PHY */ 1933 rx_status->freq = chandef->chan->center_freq; 1934 rx_status->band = chandef->chan->band; 1935 1936 if (rtwdev->scanning && 1937 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1938 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 1939 u8 chan = cur->primary_channel; 1940 u8 band = cur->band_type; 1941 enum nl80211_band nl_band; 1942 1943 nl_band = rtw89_hw_to_nl80211_band(band); 1944 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1945 rx_status->band = nl_band; 1946 } 1947 1948 if (desc_info->icv_err || desc_info->crc32_err) 1949 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1950 1951 if (desc_info->hw_dec && 1952 !(desc_info->sw_dec || desc_info->icv_err)) 1953 rx_status->flag |= RX_FLAG_DECRYPTED; 1954 1955 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1956 1957 data_rate = desc_info->data_rate; 1958 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1959 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1960 rx_status->encoding = RX_ENC_LEGACY; 1961 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1962 /* convert rate_idx after we get the correct band */ 1963 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1964 rx_status->encoding = RX_ENC_HT; 1965 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1966 if (desc_info->gi_ltf) 1967 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1968 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1969 rx_status->encoding = RX_ENC_VHT; 1970 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1971 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 1972 if (desc_info->gi_ltf) 1973 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1974 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1975 rx_status->encoding = RX_ENC_HE; 1976 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1977 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 1978 } else { 1979 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1980 } 1981 1982 /* he_gi is used to match ppdu, so we always fill it. */ 1983 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1984 rx_status->flag |= RX_FLAG_MACTIME_START; 1985 rx_status->mactime = desc_info->free_run_cnt; 1986 1987 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1988 } 1989 rtw89_update_ps_mode(struct rtw89_dev * rtwdev)1990 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1991 { 1992 const struct rtw89_chip_info *chip = rtwdev->chip; 1993 1994 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 1995 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 1996 return RTW89_PS_MODE_NONE; 1997 1998 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 1999 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2000 return RTW89_PS_MODE_PWR_GATED; 2001 2002 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2003 return RTW89_PS_MODE_CLK_GATED; 2004 2005 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2006 return RTW89_PS_MODE_RFOFF; 2007 2008 return RTW89_PS_MODE_NONE; 2009 } 2010 rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2011 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2012 struct rtw89_rx_desc_info *desc_info) 2013 { 2014 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2015 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2016 struct ieee80211_rx_status *rx_status; 2017 struct sk_buff *skb_ppdu, *tmp; 2018 2019 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2020 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2021 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2022 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2023 } 2024 } 2025 rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2026 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2027 struct rtw89_rx_desc_info *desc_info, 2028 struct sk_buff *skb) 2029 { 2030 struct ieee80211_rx_status *rx_status; 2031 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2032 u8 ppdu_cnt = desc_info->ppdu_cnt; 2033 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2034 2035 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2036 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2037 return; 2038 } 2039 2040 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2041 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2042 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2043 } 2044 2045 rx_status = IEEE80211_SKB_RXCB(skb); 2046 memset(rx_status, 0, sizeof(*rx_status)); 2047 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2048 if (desc_info->long_rxdesc && 2049 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2050 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2051 else 2052 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2053 } 2054 EXPORT_SYMBOL(rtw89_core_rx); 2055 rtw89_core_napi_start(struct rtw89_dev * rtwdev)2056 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2057 { 2058 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2059 return; 2060 2061 napi_enable(&rtwdev->napi); 2062 } 2063 EXPORT_SYMBOL(rtw89_core_napi_start); 2064 rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2065 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2066 { 2067 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2068 return; 2069 2070 napi_synchronize(&rtwdev->napi); 2071 napi_disable(&rtwdev->napi); 2072 } 2073 EXPORT_SYMBOL(rtw89_core_napi_stop); 2074 rtw89_core_napi_init(struct rtw89_dev * rtwdev)2075 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2076 { 2077 init_dummy_netdev(&rtwdev->netdev); 2078 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 2079 rtwdev->hci.ops->napi_poll); 2080 } 2081 EXPORT_SYMBOL(rtw89_core_napi_init); 2082 rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2083 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2084 { 2085 rtw89_core_napi_stop(rtwdev); 2086 netif_napi_del(&rtwdev->napi); 2087 } 2088 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2089 rtw89_core_ba_work(struct work_struct * work)2090 static void rtw89_core_ba_work(struct work_struct *work) 2091 { 2092 struct rtw89_dev *rtwdev = 2093 container_of(work, struct rtw89_dev, ba_work); 2094 struct rtw89_txq *rtwtxq, *tmp; 2095 int ret; 2096 2097 spin_lock_bh(&rtwdev->ba_lock); 2098 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2099 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2100 struct ieee80211_sta *sta = txq->sta; 2101 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2102 u8 tid = txq->tid; 2103 2104 if (!sta) { 2105 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2106 goto skip_ba_work; 2107 } 2108 2109 if (rtwsta->disassoc) { 2110 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2111 "cannot start BA with disassoc sta\n"); 2112 goto skip_ba_work; 2113 } 2114 2115 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2116 if (ret) { 2117 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2118 "failed to setup BA session for %pM:%2d: %d\n", 2119 sta->addr, tid, ret); 2120 if (ret == -EINVAL) 2121 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2122 } 2123 skip_ba_work: 2124 list_del_init(&rtwtxq->list); 2125 } 2126 spin_unlock_bh(&rtwdev->ba_lock); 2127 } 2128 rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2129 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2130 struct ieee80211_sta *sta) 2131 { 2132 struct rtw89_txq *rtwtxq, *tmp; 2133 2134 spin_lock_bh(&rtwdev->ba_lock); 2135 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2136 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2137 2138 if (sta == txq->sta) 2139 list_del_init(&rtwtxq->list); 2140 } 2141 spin_unlock_bh(&rtwdev->ba_lock); 2142 } 2143 rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2144 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2145 struct ieee80211_sta *sta) 2146 { 2147 struct rtw89_txq *rtwtxq, *tmp; 2148 2149 spin_lock_bh(&rtwdev->ba_lock); 2150 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2151 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2152 2153 if (sta == txq->sta) { 2154 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2155 list_del_init(&rtwtxq->list); 2156 } 2157 } 2158 spin_unlock_bh(&rtwdev->ba_lock); 2159 } 2160 rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2161 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2162 struct ieee80211_sta *sta) 2163 { 2164 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2165 struct sk_buff *skb, *tmp; 2166 2167 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2168 skb_unlink(skb, &rtwsta->roc_queue); 2169 dev_kfree_skb_any(skb); 2170 } 2171 } 2172 rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2173 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2174 struct rtw89_txq *rtwtxq) 2175 { 2176 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2177 struct ieee80211_sta *sta = txq->sta; 2178 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2179 2180 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2181 return; 2182 2183 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2184 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2185 return; 2186 2187 spin_lock_bh(&rtwdev->ba_lock); 2188 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2189 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2190 spin_unlock_bh(&rtwdev->ba_lock); 2191 2192 ieee80211_stop_tx_ba_session(sta, txq->tid); 2193 cancel_delayed_work(&rtwdev->forbid_ba_work); 2194 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2195 RTW89_FORBID_BA_TIMER); 2196 } 2197 rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2198 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2199 struct rtw89_txq *rtwtxq, 2200 struct sk_buff *skb) 2201 { 2202 struct ieee80211_hw *hw = rtwdev->hw; 2203 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2204 struct ieee80211_sta *sta = txq->sta; 2205 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2206 2207 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2208 return; 2209 2210 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2211 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2212 return; 2213 } 2214 2215 if (unlikely(!sta)) 2216 return; 2217 2218 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2219 return; 2220 2221 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2222 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2223 return; 2224 } 2225 2226 spin_lock_bh(&rtwdev->ba_lock); 2227 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2228 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2229 ieee80211_queue_work(hw, &rtwdev->ba_work); 2230 } 2231 spin_unlock_bh(&rtwdev->ba_lock); 2232 } 2233 rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)2234 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2235 struct rtw89_txq *rtwtxq, 2236 unsigned long frame_cnt, 2237 unsigned long byte_cnt) 2238 { 2239 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2240 struct ieee80211_vif *vif = txq->vif; 2241 struct ieee80211_sta *sta = txq->sta; 2242 struct sk_buff *skb; 2243 unsigned long i; 2244 int ret; 2245 2246 rcu_read_lock(); 2247 for (i = 0; i < frame_cnt; i++) { 2248 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2249 if (!skb) { 2250 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2251 goto out; 2252 } 2253 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2254 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2255 if (ret) { 2256 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2257 ieee80211_free_txskb(rtwdev->hw, skb); 2258 break; 2259 } 2260 } 2261 out: 2262 rcu_read_unlock(); 2263 } 2264 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)2265 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2266 { 2267 u8 qsel, ch_dma; 2268 2269 qsel = rtw89_core_get_qsel(rtwdev, tid); 2270 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2271 2272 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2273 } 2274 rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)2275 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2276 struct ieee80211_txq *txq, 2277 unsigned long *frame_cnt, 2278 bool *sched_txq, bool *reinvoke) 2279 { 2280 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2281 struct ieee80211_sta *sta = txq->sta; 2282 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2283 2284 if (!sta || rtwsta->max_agg_wait <= 0) 2285 return false; 2286 2287 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2288 return false; 2289 2290 if (*frame_cnt > 1) { 2291 *frame_cnt -= 1; 2292 *sched_txq = true; 2293 *reinvoke = true; 2294 rtwtxq->wait_cnt = 1; 2295 return false; 2296 } 2297 2298 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2299 *reinvoke = true; 2300 rtwtxq->wait_cnt++; 2301 return true; 2302 } 2303 2304 rtwtxq->wait_cnt = 0; 2305 return false; 2306 } 2307 rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2308 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2309 { 2310 struct ieee80211_hw *hw = rtwdev->hw; 2311 struct ieee80211_txq *txq; 2312 struct rtw89_vif *rtwvif; 2313 struct rtw89_txq *rtwtxq; 2314 unsigned long frame_cnt; 2315 unsigned long byte_cnt; 2316 u32 tx_resource; 2317 bool sched_txq; 2318 2319 ieee80211_txq_schedule_start(hw, ac); 2320 while ((txq = ieee80211_next_txq(hw, ac))) { 2321 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2322 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2323 2324 if (rtwvif->offchan) { 2325 ieee80211_return_txq(hw, txq, true); 2326 continue; 2327 } 2328 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2329 sched_txq = false; 2330 2331 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2332 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2333 ieee80211_return_txq(hw, txq, true); 2334 continue; 2335 } 2336 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2337 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2338 ieee80211_return_txq(hw, txq, sched_txq); 2339 if (frame_cnt != 0) 2340 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2341 2342 /* bound of tx_resource could get stuck due to burst traffic */ 2343 if (frame_cnt == tx_resource) 2344 *reinvoke = true; 2345 } 2346 ieee80211_txq_schedule_end(hw, ac); 2347 } 2348 rtw89_ips_work(struct work_struct * work)2349 static void rtw89_ips_work(struct work_struct *work) 2350 { 2351 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2352 ips_work); 2353 mutex_lock(&rtwdev->mutex); 2354 rtw89_enter_ips_by_hwflags(rtwdev); 2355 mutex_unlock(&rtwdev->mutex); 2356 } 2357 rtw89_core_txq_work(struct work_struct * w)2358 static void rtw89_core_txq_work(struct work_struct *w) 2359 { 2360 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2361 bool reinvoke = false; 2362 u8 ac; 2363 2364 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2365 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2366 2367 if (reinvoke) { 2368 /* reinvoke to process the last frame */ 2369 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2370 } 2371 } 2372 rtw89_core_txq_reinvoke_work(struct work_struct * w)2373 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2374 { 2375 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2376 txq_reinvoke_work.work); 2377 2378 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2379 } 2380 rtw89_forbid_ba_work(struct work_struct * w)2381 static void rtw89_forbid_ba_work(struct work_struct *w) 2382 { 2383 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2384 forbid_ba_work.work); 2385 struct rtw89_txq *rtwtxq, *tmp; 2386 2387 spin_lock_bh(&rtwdev->ba_lock); 2388 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2389 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2390 list_del_init(&rtwtxq->list); 2391 } 2392 spin_unlock_bh(&rtwdev->ba_lock); 2393 } 2394 rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)2395 static void rtw89_core_sta_pending_tx_iter(void *data, 2396 struct ieee80211_sta *sta) 2397 { 2398 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2399 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2400 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2401 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2402 struct sk_buff *skb, *tmp; 2403 int qsel, ret; 2404 2405 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2406 return; 2407 2408 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2409 return; 2410 2411 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2412 skb_unlink(skb, &rtwsta->roc_queue); 2413 2414 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2415 if (ret) { 2416 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2417 dev_kfree_skb_any(skb); 2418 } else { 2419 rtw89_core_tx_kick_off(rtwdev, qsel); 2420 } 2421 } 2422 } 2423 rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2424 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2425 struct rtw89_vif *rtwvif) 2426 { 2427 ieee80211_iterate_stations_atomic(rtwdev->hw, 2428 rtw89_core_sta_pending_tx_iter, 2429 rtwvif); 2430 } 2431 rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool qos,bool ps)2432 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2433 struct rtw89_vif *rtwvif, bool qos, bool ps) 2434 { 2435 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2436 struct ieee80211_sta *sta; 2437 struct ieee80211_hdr *hdr; 2438 struct sk_buff *skb; 2439 int ret, qsel; 2440 2441 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2442 return 0; 2443 2444 rcu_read_lock(); 2445 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2446 if (!sta) { 2447 ret = -EINVAL; 2448 goto out; 2449 } 2450 2451 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2452 if (!skb) { 2453 ret = -ENOMEM; 2454 goto out; 2455 } 2456 2457 hdr = (struct ieee80211_hdr *)skb->data; 2458 if (ps) 2459 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2460 2461 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2462 if (ret) { 2463 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2464 dev_kfree_skb_any(skb); 2465 goto out; 2466 } 2467 2468 rcu_read_unlock(); 2469 2470 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2471 RTW89_ROC_TX_TIMEOUT); 2472 out: 2473 rcu_read_unlock(); 2474 2475 return ret; 2476 } 2477 rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2478 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2479 { 2480 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2481 struct ieee80211_hw *hw = rtwdev->hw; 2482 struct rtw89_roc *roc = &rtwvif->roc; 2483 struct cfg80211_chan_def roc_chan; 2484 struct rtw89_vif *tmp; 2485 int ret; 2486 2487 lockdep_assert_held(&rtwdev->mutex); 2488 2489 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2490 msecs_to_jiffies(rtwvif->roc.duration)); 2491 2492 rtw89_leave_ips_by_hwflags(rtwdev); 2493 rtw89_leave_lps(rtwdev); 2494 2495 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2496 if (ret) 2497 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2498 "roc send null-1 failed: %d\n", ret); 2499 2500 rtw89_for_each_rtwvif(rtwdev, tmp) 2501 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2502 tmp->offchan = true; 2503 2504 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2505 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2506 rtw89_set_channel(rtwdev); 2507 rtw89_write32_clr(rtwdev, 2508 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2509 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2510 2511 ieee80211_ready_on_channel(hw); 2512 } 2513 rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2514 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2515 { 2516 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2517 struct ieee80211_hw *hw = rtwdev->hw; 2518 struct rtw89_roc *roc = &rtwvif->roc; 2519 struct rtw89_vif *tmp; 2520 int ret; 2521 2522 lockdep_assert_held(&rtwdev->mutex); 2523 2524 ieee80211_remain_on_channel_expired(hw); 2525 2526 rtw89_leave_ips_by_hwflags(rtwdev); 2527 rtw89_leave_lps(rtwdev); 2528 2529 rtw89_write32_mask(rtwdev, 2530 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2531 B_AX_RX_FLTR_CFG_MASK, 2532 rtwdev->hal.rx_fltr); 2533 2534 roc->state = RTW89_ROC_IDLE; 2535 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2536 rtw89_set_channel(rtwdev); 2537 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2538 if (ret) 2539 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2540 "roc send null-0 failed: %d\n", ret); 2541 2542 rtw89_for_each_rtwvif(rtwdev, tmp) 2543 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2544 tmp->offchan = false; 2545 2546 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 2547 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2548 2549 if (hw->conf.flags & IEEE80211_CONF_IDLE) 2550 ieee80211_queue_delayed_work(hw, &roc->roc_work, 2551 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 2552 } 2553 rtw89_roc_work(struct work_struct * work)2554 void rtw89_roc_work(struct work_struct *work) 2555 { 2556 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2557 roc.roc_work.work); 2558 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2559 struct rtw89_roc *roc = &rtwvif->roc; 2560 2561 mutex_lock(&rtwdev->mutex); 2562 2563 switch (roc->state) { 2564 case RTW89_ROC_IDLE: 2565 rtw89_enter_ips_by_hwflags(rtwdev); 2566 break; 2567 case RTW89_ROC_MGMT: 2568 case RTW89_ROC_NORMAL: 2569 rtw89_roc_end(rtwdev, rtwvif); 2570 break; 2571 default: 2572 break; 2573 } 2574 2575 mutex_unlock(&rtwdev->mutex); 2576 } 2577 rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)2578 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2579 u32 throughput, u64 cnt) 2580 { 2581 if (cnt < 100) 2582 return RTW89_TFC_IDLE; 2583 if (throughput > 50) 2584 return RTW89_TFC_HIGH; 2585 if (throughput > 10) 2586 return RTW89_TFC_MID; 2587 if (throughput > 2) 2588 return RTW89_TFC_LOW; 2589 return RTW89_TFC_ULTRA_LOW; 2590 } 2591 rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2592 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2593 struct rtw89_traffic_stats *stats) 2594 { 2595 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2596 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2597 2598 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2599 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2600 2601 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2602 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2603 2604 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2605 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2606 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2607 stats->tx_cnt); 2608 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2609 stats->rx_cnt); 2610 stats->tx_avg_len = stats->tx_cnt ? 2611 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2612 stats->rx_avg_len = stats->rx_cnt ? 2613 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2614 2615 stats->tx_unicast = 0; 2616 stats->rx_unicast = 0; 2617 stats->tx_cnt = 0; 2618 stats->rx_cnt = 0; 2619 stats->rx_tf_periodic = stats->rx_tf_acc; 2620 stats->rx_tf_acc = 0; 2621 2622 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2623 return true; 2624 2625 return false; 2626 } 2627 rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)2628 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2629 { 2630 struct rtw89_vif *rtwvif; 2631 bool tfc_changed; 2632 2633 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2634 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2635 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2636 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 2637 } 2638 2639 return tfc_changed; 2640 } 2641 rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2642 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2643 { 2644 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 2645 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 2646 rtwvif->tdls_peer) 2647 return; 2648 2649 if (rtwvif->offchan) 2650 return; 2651 2652 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2653 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2654 rtw89_enter_lps(rtwdev, rtwvif, true); 2655 } 2656 rtw89_enter_lps_track(struct rtw89_dev * rtwdev)2657 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2658 { 2659 struct rtw89_vif *rtwvif; 2660 2661 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2662 rtw89_vif_enter_lps(rtwdev, rtwvif); 2663 } 2664 rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2665 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2666 struct rtw89_traffic_stats *stats) 2667 { 2668 stats->tx_unicast = 0; 2669 stats->rx_unicast = 0; 2670 stats->tx_cnt = 0; 2671 stats->rx_cnt = 0; 2672 ewma_tp_init(&stats->tx_ewma_tp); 2673 ewma_tp_init(&stats->rx_ewma_tp); 2674 } 2675 rtw89_track_work(struct work_struct * work)2676 static void rtw89_track_work(struct work_struct *work) 2677 { 2678 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2679 track_work.work); 2680 bool tfc_changed; 2681 2682 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 2683 return; 2684 2685 mutex_lock(&rtwdev->mutex); 2686 2687 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2688 goto out; 2689 2690 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2691 RTW89_TRACK_WORK_PERIOD); 2692 2693 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2694 if (rtwdev->scanning) 2695 goto out; 2696 2697 rtw89_leave_lps(rtwdev); 2698 2699 if (tfc_changed) { 2700 rtw89_hci_recalc_int_mit(rtwdev); 2701 rtw89_btc_ntfy_wl_sta(rtwdev); 2702 } 2703 rtw89_mac_bf_monitor_track(rtwdev); 2704 rtw89_phy_stat_track(rtwdev); 2705 rtw89_phy_env_monitor_track(rtwdev); 2706 rtw89_phy_dig(rtwdev); 2707 rtw89_chip_rfk_track(rtwdev); 2708 rtw89_phy_ra_update(rtwdev); 2709 rtw89_phy_cfo_track(rtwdev); 2710 rtw89_phy_tx_path_div_track(rtwdev); 2711 rtw89_phy_antdiv_track(rtwdev); 2712 rtw89_phy_ul_tb_ctrl_track(rtwdev); 2713 rtw89_tas_track(rtwdev); 2714 2715 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2716 rtw89_enter_lps_track(rtwdev); 2717 2718 out: 2719 mutex_unlock(&rtwdev->mutex); 2720 } 2721 rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)2722 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2723 { 2724 unsigned long bit; 2725 2726 bit = find_first_zero_bit(addr, size); 2727 if (bit < size) 2728 set_bit(bit, addr); 2729 2730 return bit; 2731 } 2732 rtw89_core_release_bit_map(unsigned long * addr,u8 bit)2733 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2734 { 2735 clear_bit(bit, addr); 2736 } 2737 rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)2738 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2739 { 2740 bitmap_zero(addr, nbits); 2741 } 2742 rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2743 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2744 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2745 { 2746 const struct rtw89_chip_info *chip = rtwdev->chip; 2747 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2748 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2749 u8 idx; 2750 int i; 2751 2752 lockdep_assert_held(&rtwdev->mutex); 2753 2754 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2755 if (idx == chip->bacam_num) { 2756 /* allocate a static BA CAM to tid=0/5, so replace the existing 2757 * one if BA CAM is full. Hardware will process the original tid 2758 * automatically. 2759 */ 2760 if (tid != 0 && tid != 5) 2761 return -ENOSPC; 2762 2763 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2764 tmp = &cam_info->ba_cam_entry[i]; 2765 if (tmp->tid == 0 || tmp->tid == 5) 2766 continue; 2767 2768 idx = i; 2769 entry = tmp; 2770 list_del(&entry->list); 2771 break; 2772 } 2773 2774 if (!entry) 2775 return -ENOSPC; 2776 } else { 2777 entry = &cam_info->ba_cam_entry[idx]; 2778 } 2779 2780 entry->tid = tid; 2781 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2782 2783 *cam_idx = idx; 2784 2785 return 0; 2786 } 2787 rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2788 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2789 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2790 { 2791 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2792 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2793 u8 idx; 2794 2795 lockdep_assert_held(&rtwdev->mutex); 2796 2797 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2798 if (entry->tid != tid) 2799 continue; 2800 2801 idx = entry - cam_info->ba_cam_entry; 2802 list_del(&entry->list); 2803 2804 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2805 *cam_idx = idx; 2806 return 0; 2807 } 2808 2809 return -ENOENT; 2810 } 2811 2812 #define RTW89_TYPE_MAPPING(_type) \ 2813 case NL80211_IFTYPE_ ## _type: \ 2814 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2815 break rtw89_vif_type_mapping(struct ieee80211_vif * vif,bool assoc)2816 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2817 { 2818 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2819 2820 switch (vif->type) { 2821 case NL80211_IFTYPE_STATION: 2822 if (vif->p2p) 2823 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 2824 else 2825 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 2826 break; 2827 case NL80211_IFTYPE_AP: 2828 if (vif->p2p) 2829 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 2830 else 2831 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 2832 break; 2833 RTW89_TYPE_MAPPING(ADHOC); 2834 RTW89_TYPE_MAPPING(MONITOR); 2835 RTW89_TYPE_MAPPING(MESH_POINT); 2836 default: 2837 WARN_ON(1); 2838 break; 2839 } 2840 2841 switch (vif->type) { 2842 case NL80211_IFTYPE_AP: 2843 case NL80211_IFTYPE_MESH_POINT: 2844 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2845 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2846 break; 2847 case NL80211_IFTYPE_ADHOC: 2848 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2849 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2850 break; 2851 case NL80211_IFTYPE_STATION: 2852 if (assoc) { 2853 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2854 rtwvif->trigger = vif->bss_conf.he_support; 2855 } else { 2856 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2857 rtwvif->trigger = false; 2858 } 2859 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2860 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2861 break; 2862 case NL80211_IFTYPE_MONITOR: 2863 break; 2864 default: 2865 WARN_ON(1); 2866 break; 2867 } 2868 } 2869 rtw89_core_sta_add(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2870 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2871 struct ieee80211_vif *vif, 2872 struct ieee80211_sta *sta) 2873 { 2874 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2875 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2876 struct rtw89_hal *hal = &rtwdev->hal; 2877 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 2878 int i; 2879 int ret; 2880 2881 rtwsta->rtwdev = rtwdev; 2882 rtwsta->rtwvif = rtwvif; 2883 rtwsta->prev_rssi = 0; 2884 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2885 skb_queue_head_init(&rtwsta->roc_queue); 2886 2887 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2888 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2889 2890 ewma_rssi_init(&rtwsta->avg_rssi); 2891 ewma_snr_init(&rtwsta->avg_snr); 2892 for (i = 0; i < ant_num; i++) { 2893 ewma_rssi_init(&rtwsta->rssi[i]); 2894 ewma_evm_init(&rtwsta->evm_min[i]); 2895 ewma_evm_init(&rtwsta->evm_max[i]); 2896 } 2897 2898 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2899 /* for station mode, assign the mac_id from itself */ 2900 rtwsta->mac_id = rtwvif->mac_id; 2901 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */ 2902 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true); 2903 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2904 BTC_ROLE_MSTS_STA_CONN_START); 2905 rtw89_chip_rfk_channel(rtwdev); 2906 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2907 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2908 RTW89_MAX_MAC_ID_NUM); 2909 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 2910 return -ENOSPC; 2911 2912 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2913 if (ret) { 2914 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2915 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2916 return ret; 2917 } 2918 2919 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 2920 RTW89_ROLE_CREATE); 2921 if (ret) { 2922 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2923 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2924 return ret; 2925 } 2926 } 2927 2928 return 0; 2929 } 2930 rtw89_core_sta_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2931 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2932 struct ieee80211_vif *vif, 2933 struct ieee80211_sta *sta) 2934 { 2935 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2936 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2937 2938 if (vif->type == NL80211_IFTYPE_STATION) 2939 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 2940 2941 rtwdev->total_sta_assoc--; 2942 if (sta->tdls) 2943 rtwvif->tdls_peer--; 2944 rtwsta->disassoc = true; 2945 2946 return 0; 2947 } 2948 rtw89_core_sta_disconnect(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2949 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2950 struct ieee80211_vif *vif, 2951 struct ieee80211_sta *sta) 2952 { 2953 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2954 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2955 int ret; 2956 2957 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2958 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2959 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2960 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2961 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 2962 2963 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2964 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2965 if (sta->tdls) 2966 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2967 2968 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2969 rtw89_vif_type_mapping(vif, false); 2970 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 2971 } 2972 2973 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2974 if (ret) { 2975 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2976 return ret; 2977 } 2978 2979 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2980 if (ret) { 2981 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2982 return ret; 2983 } 2984 2985 /* update cam aid mac_id net_type */ 2986 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2987 if (ret) { 2988 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2989 return ret; 2990 } 2991 2992 return ret; 2993 } 2994 rtw89_core_sta_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2995 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2996 struct ieee80211_vif *vif, 2997 struct ieee80211_sta *sta) 2998 { 2999 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3000 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3001 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3002 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3003 rtwvif->sub_entity_idx); 3004 int ret; 3005 3006 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3007 if (sta->tdls) { 3008 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3009 if (ret) { 3010 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3011 return ret; 3012 } 3013 } 3014 3015 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3016 if (ret) { 3017 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3018 return ret; 3019 } 3020 } 3021 3022 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3023 if (ret) { 3024 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3025 return ret; 3026 } 3027 3028 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3029 if (ret) { 3030 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3031 return ret; 3032 } 3033 3034 /* update cam aid mac_id net_type */ 3035 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3036 if (ret) { 3037 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3038 return ret; 3039 } 3040 3041 rtwdev->total_sta_assoc++; 3042 if (sta->tdls) 3043 rtwvif->tdls_peer++; 3044 rtw89_phy_ra_assoc(rtwdev, sta); 3045 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3046 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3047 3048 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3049 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3050 3051 if (bss_conf->he_support && 3052 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3053 rtwsta->er_cap = true; 3054 3055 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3056 BTC_ROLE_MSTS_STA_CONN_END); 3057 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3058 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3059 3060 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3061 if (ret) { 3062 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3063 return ret; 3064 } 3065 } 3066 3067 return ret; 3068 } 3069 rtw89_core_sta_remove(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3070 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3071 struct ieee80211_vif *vif, 3072 struct ieee80211_sta *sta) 3073 { 3074 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3075 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3076 int ret; 3077 3078 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3079 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false); 3080 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3081 BTC_ROLE_MSTS_STA_DIS_CONN); 3082 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3083 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3084 3085 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3086 RTW89_ROLE_REMOVE); 3087 if (ret) { 3088 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3089 return ret; 3090 } 3091 } 3092 3093 return 0; 3094 } 3095 _rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3096 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3097 struct ieee80211_sta *sta, 3098 struct cfg80211_tid_cfg *tid_conf) 3099 { 3100 struct ieee80211_txq *txq; 3101 struct rtw89_txq *rtwtxq; 3102 u32 mask = tid_conf->mask; 3103 u8 tids = tid_conf->tids; 3104 int tids_nbit = BITS_PER_BYTE; 3105 int i; 3106 3107 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3108 if (!tids) 3109 break; 3110 3111 if (!(tids & BIT(0))) 3112 continue; 3113 3114 txq = sta->txq[i]; 3115 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3116 3117 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3118 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3119 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3120 } else { 3121 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3122 ieee80211_stop_tx_ba_session(sta, txq->tid); 3123 spin_lock_bh(&rtwdev->ba_lock); 3124 list_del_init(&rtwtxq->list); 3125 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3126 spin_unlock_bh(&rtwdev->ba_lock); 3127 } 3128 } 3129 3130 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3131 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3132 sta->max_amsdu_subframes = 0; 3133 else 3134 sta->max_amsdu_subframes = 1; 3135 } 3136 } 3137 } 3138 rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)3139 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3140 struct ieee80211_sta *sta, 3141 struct cfg80211_tid_config *tid_config) 3142 { 3143 int i; 3144 3145 for (i = 0; i < tid_config->n_tid_conf; i++) 3146 _rtw89_core_set_tid_config(rtwdev, sta, 3147 &tid_config->tid_conf[i]); 3148 } 3149 rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)3150 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3151 struct ieee80211_sta_ht_cap *ht_cap) 3152 { 3153 static const __le16 highest[RF_PATH_MAX] = { 3154 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3155 }; 3156 struct rtw89_hal *hal = &rtwdev->hal; 3157 u8 nss = hal->rx_nss; 3158 int i; 3159 3160 ht_cap->ht_supported = true; 3161 ht_cap->cap = 0; 3162 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3163 IEEE80211_HT_CAP_MAX_AMSDU | 3164 IEEE80211_HT_CAP_TX_STBC | 3165 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3166 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3167 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3168 IEEE80211_HT_CAP_DSSSCCK40 | 3169 IEEE80211_HT_CAP_SGI_40; 3170 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3171 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3172 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3173 for (i = 0; i < nss; i++) 3174 ht_cap->mcs.rx_mask[i] = 0xFF; 3175 ht_cap->mcs.rx_mask[4] = 0x01; 3176 ht_cap->mcs.rx_highest = highest[nss - 1]; 3177 } 3178 rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)3179 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3180 struct ieee80211_sta_vht_cap *vht_cap) 3181 { 3182 static const __le16 highest_bw80[RF_PATH_MAX] = { 3183 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3184 }; 3185 static const __le16 highest_bw160[RF_PATH_MAX] = { 3186 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3187 }; 3188 const struct rtw89_chip_info *chip = rtwdev->chip; 3189 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 3190 struct rtw89_hal *hal = &rtwdev->hal; 3191 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3192 u8 sts_cap = 3; 3193 int i; 3194 3195 for (i = 0; i < 8; i++) { 3196 if (i < hal->tx_nss) 3197 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3198 else 3199 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3200 if (i < hal->rx_nss) 3201 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3202 else 3203 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3204 } 3205 3206 vht_cap->vht_supported = true; 3207 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3208 IEEE80211_VHT_CAP_SHORT_GI_80 | 3209 IEEE80211_VHT_CAP_RXSTBC_1 | 3210 IEEE80211_VHT_CAP_HTC_VHT | 3211 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3212 0; 3213 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3214 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3215 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3216 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3217 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3218 if (chip->support_bw160) 3219 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3220 IEEE80211_VHT_CAP_SHORT_GI_160; 3221 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3222 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3223 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3224 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3225 } 3226 3227 #define RTW89_SBAND_IFTYPES_NR 2 3228 rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)3229 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3230 enum nl80211_band band, 3231 struct ieee80211_supported_band *sband) 3232 { 3233 const struct rtw89_chip_info *chip = rtwdev->chip; 3234 struct rtw89_hal *hal = &rtwdev->hal; 3235 struct ieee80211_sband_iftype_data *iftype_data; 3236 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3237 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3238 u16 mcs_map = 0; 3239 int i; 3240 int nss = hal->rx_nss; 3241 int idx = 0; 3242 3243 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3244 if (!iftype_data) 3245 return; 3246 3247 for (i = 0; i < 8; i++) { 3248 if (i < nss) 3249 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3250 else 3251 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3252 } 3253 3254 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 3255 struct ieee80211_sta_he_cap *he_cap; 3256 u8 *mac_cap_info; 3257 u8 *phy_cap_info; 3258 3259 switch (i) { 3260 case NL80211_IFTYPE_STATION: 3261 case NL80211_IFTYPE_AP: 3262 break; 3263 default: 3264 continue; 3265 } 3266 3267 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3268 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3269 break; 3270 } 3271 3272 iftype_data[idx].types_mask = BIT(i); 3273 he_cap = &iftype_data[idx].he_cap; 3274 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3275 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3276 3277 he_cap->has_he = true; 3278 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3279 if (i == NL80211_IFTYPE_STATION) 3280 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3281 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3282 IEEE80211_HE_MAC_CAP2_BSR; 3283 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3284 if (i == NL80211_IFTYPE_AP) 3285 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3286 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3287 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3288 if (i == NL80211_IFTYPE_STATION) 3289 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3290 if (band == NL80211_BAND_2GHZ) { 3291 phy_cap_info[0] = 3292 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3293 } else { 3294 phy_cap_info[0] = 3295 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3296 if (chip->support_bw160) 3297 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3298 } 3299 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3300 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3301 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3302 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3303 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3304 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3305 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3306 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3307 if (i == NL80211_IFTYPE_STATION) 3308 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3309 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3310 if (i == NL80211_IFTYPE_AP) 3311 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3312 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3313 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3314 if (chip->support_bw160) 3315 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3316 phy_cap_info[5] = no_ng16 ? 0 : 3317 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3318 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3319 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3320 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3321 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3322 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3323 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3324 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3325 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3326 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3327 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3328 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3329 if (chip->support_bw160) 3330 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3331 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3332 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3333 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3334 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3335 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3336 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3337 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3338 if (i == NL80211_IFTYPE_STATION) 3339 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3340 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3341 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3342 if (chip->support_bw160) { 3343 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3344 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3345 } 3346 3347 if (band == NL80211_BAND_6GHZ) { 3348 __le16 capa; 3349 3350 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3351 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3352 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3353 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3354 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3355 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3356 iftype_data[idx].he_6ghz_capa.capa = capa; 3357 } 3358 3359 idx++; 3360 } 3361 3362 sband->iftype_data = iftype_data; 3363 sband->n_iftype_data = idx; 3364 } 3365 rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)3366 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3367 { 3368 struct ieee80211_hw *hw = rtwdev->hw; 3369 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3370 struct ieee80211_supported_band *sband_6ghz = NULL; 3371 u32 size = sizeof(struct ieee80211_supported_band); 3372 u8 support_bands = rtwdev->chip->support_bands; 3373 3374 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3375 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3376 if (!sband_2ghz) 3377 goto err; 3378 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3379 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3380 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3381 } 3382 3383 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3384 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3385 if (!sband_5ghz) 3386 goto err; 3387 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3388 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3389 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3390 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3391 } 3392 3393 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3394 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3395 if (!sband_6ghz) 3396 goto err; 3397 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3398 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3399 } 3400 3401 return 0; 3402 3403 err: 3404 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3405 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3406 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3407 if (sband_2ghz) 3408 kfree(sband_2ghz->iftype_data); 3409 if (sband_5ghz) 3410 kfree(sband_5ghz->iftype_data); 3411 if (sband_6ghz) 3412 kfree(sband_6ghz->iftype_data); 3413 kfree(sband_2ghz); 3414 kfree(sband_5ghz); 3415 kfree(sband_6ghz); 3416 return -ENOMEM; 3417 } 3418 rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)3419 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 3420 { 3421 struct ieee80211_hw *hw = rtwdev->hw; 3422 3423 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 3424 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3425 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 3426 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3427 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3428 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3429 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3430 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3431 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3432 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3433 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3434 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3435 } 3436 rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)3437 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3438 { 3439 int i; 3440 3441 for (i = 0; i < RTW89_PHY_MAX; i++) 3442 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 3443 for (i = 0; i < RTW89_PHY_MAX; i++) 3444 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 3445 } 3446 rtw89_core_update_beacon_work(struct work_struct * work)3447 void rtw89_core_update_beacon_work(struct work_struct *work) 3448 { 3449 struct rtw89_dev *rtwdev; 3450 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3451 update_beacon_work); 3452 3453 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 3454 return; 3455 3456 rtwdev = rtwvif->rtwdev; 3457 mutex_lock(&rtwdev->mutex); 3458 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 3459 mutex_unlock(&rtwdev->mutex); 3460 } 3461 rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)3462 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 3463 { 3464 struct completion *cmpl = &wait->completion; 3465 unsigned long timeout; 3466 unsigned int cur; 3467 3468 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 3469 if (cur != RTW89_WAIT_COND_IDLE) 3470 return -EBUSY; 3471 3472 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 3473 if (timeout == 0) { 3474 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3475 return -ETIMEDOUT; 3476 } 3477 3478 if (wait->data.err) 3479 return -EFAULT; 3480 3481 return 0; 3482 } 3483 rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)3484 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 3485 const struct rtw89_completion_data *data) 3486 { 3487 unsigned int cur; 3488 3489 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 3490 if (cur != cond) 3491 return; 3492 3493 wait->data = *data; 3494 complete(&wait->completion); 3495 } 3496 rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)3497 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 3498 { 3499 u16 bt_req_len; 3500 3501 switch (event) { 3502 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 3503 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 3504 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3505 "coex updates BT req len to %d TU\n", bt_req_len); 3506 break; 3507 default: 3508 if (event < NUM_OF_RTW89_BTC_HMSG) 3509 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3510 "unhandled BTC HMSG event: %d\n", event); 3511 else 3512 rtw89_warn(rtwdev, 3513 "unrecognized BTC HMSG event: %d\n", event); 3514 break; 3515 } 3516 } 3517 rtw89_core_start(struct rtw89_dev * rtwdev)3518 int rtw89_core_start(struct rtw89_dev *rtwdev) 3519 { 3520 int ret; 3521 3522 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 3523 ret = rtw89_mac_init(rtwdev); 3524 if (ret) { 3525 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 3526 return ret; 3527 } 3528 3529 rtw89_btc_ntfy_poweron(rtwdev); 3530 3531 /* efuse process */ 3532 3533 /* pre-config BB/RF, BB reset/RFC reset */ 3534 ret = rtw89_chip_disable_bb_rf(rtwdev); 3535 if (ret) 3536 return ret; 3537 ret = rtw89_chip_enable_bb_rf(rtwdev); 3538 if (ret) 3539 return ret; 3540 3541 rtw89_phy_init_bb_reg(rtwdev); 3542 rtw89_phy_init_rf_reg(rtwdev, false); 3543 3544 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 3545 3546 rtw89_phy_dm_init(rtwdev); 3547 3548 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 3549 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 3550 3551 rtw89_tas_reset(rtwdev); 3552 3553 ret = rtw89_hci_start(rtwdev); 3554 if (ret) { 3555 rtw89_err(rtwdev, "failed to start hci\n"); 3556 return ret; 3557 } 3558 3559 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3560 RTW89_TRACK_WORK_PERIOD); 3561 3562 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3563 3564 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 3565 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 3566 rtw89_fw_h2c_init_ba_cam(rtwdev); 3567 3568 return 0; 3569 } 3570 rtw89_core_stop(struct rtw89_dev * rtwdev)3571 void rtw89_core_stop(struct rtw89_dev *rtwdev) 3572 { 3573 struct rtw89_btc *btc = &rtwdev->btc; 3574 3575 /* Prvent to stop twice; enter_ips and ops_stop */ 3576 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3577 return; 3578 3579 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 3580 3581 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3582 3583 mutex_unlock(&rtwdev->mutex); 3584 3585 cancel_work_sync(&rtwdev->c2h_work); 3586 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 3587 cancel_work_sync(&btc->eapol_notify_work); 3588 cancel_work_sync(&btc->arp_notify_work); 3589 cancel_work_sync(&btc->dhcp_notify_work); 3590 cancel_work_sync(&btc->icmp_notify_work); 3591 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 3592 cancel_delayed_work_sync(&rtwdev->track_work); 3593 cancel_delayed_work_sync(&rtwdev->chanctx_work); 3594 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 3595 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 3596 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 3597 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 3598 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 3599 cancel_delayed_work_sync(&rtwdev->antdiv_work); 3600 3601 mutex_lock(&rtwdev->mutex); 3602 3603 rtw89_btc_ntfy_poweroff(rtwdev); 3604 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3605 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3606 rtw89_hci_stop(rtwdev); 3607 rtw89_hci_deinit(rtwdev); 3608 rtw89_mac_pwr_off(rtwdev); 3609 rtw89_hci_reset(rtwdev); 3610 } 3611 rtw89_core_init(struct rtw89_dev * rtwdev)3612 int rtw89_core_init(struct rtw89_dev *rtwdev) 3613 { 3614 struct rtw89_btc *btc = &rtwdev->btc; 3615 u8 band; 3616 3617 INIT_LIST_HEAD(&rtwdev->ba_list); 3618 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 3619 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 3620 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 3621 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 3622 if (!(rtwdev->chip->support_bands & BIT(band))) 3623 continue; 3624 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 3625 } 3626 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 3627 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 3628 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 3629 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 3630 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 3631 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 3632 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 3633 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 3634 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 3635 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 3636 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 3637 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 3638 if (!rtwdev->txq_wq) 3639 return -ENOMEM; 3640 spin_lock_init(&rtwdev->ba_lock); 3641 spin_lock_init(&rtwdev->rpwm_lock); 3642 mutex_init(&rtwdev->mutex); 3643 mutex_init(&rtwdev->rf_mutex); 3644 rtwdev->total_sta_assoc = 0; 3645 3646 rtw89_init_wait(&rtwdev->mcc.wait); 3647 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 3648 3649 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 3650 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 3651 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 3652 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 3653 3654 skb_queue_head_init(&rtwdev->c2h_queue); 3655 rtw89_core_ppdu_sts_init(rtwdev); 3656 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 3657 3658 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 3659 3660 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 3661 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 3662 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 3663 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 3664 3665 init_completion(&rtwdev->fw.req.completion); 3666 3667 schedule_work(&rtwdev->load_firmware_work); 3668 3669 rtw89_ser_init(rtwdev); 3670 rtw89_entity_init(rtwdev); 3671 rtw89_tas_init(rtwdev); 3672 3673 return 0; 3674 } 3675 EXPORT_SYMBOL(rtw89_core_init); 3676 rtw89_core_deinit(struct rtw89_dev * rtwdev)3677 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3678 { 3679 rtw89_ser_deinit(rtwdev); 3680 rtw89_unload_firmware(rtwdev); 3681 rtw89_fw_free_all_early_h2c(rtwdev); 3682 3683 destroy_workqueue(rtwdev->txq_wq); 3684 mutex_destroy(&rtwdev->rf_mutex); 3685 mutex_destroy(&rtwdev->mutex); 3686 } 3687 EXPORT_SYMBOL(rtw89_core_deinit); 3688 rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,const u8 * mac_addr,bool hw_scan)3689 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3690 const u8 *mac_addr, bool hw_scan) 3691 { 3692 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3693 rtwvif->sub_entity_idx); 3694 3695 rtwdev->scanning = true; 3696 rtw89_leave_lps(rtwdev); 3697 if (hw_scan) 3698 rtw89_leave_ips_by_hwflags(rtwdev); 3699 3700 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3701 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3702 rtw89_chip_rfk_scan(rtwdev, true); 3703 rtw89_hci_recalc_int_mit(rtwdev); 3704 rtw89_phy_config_edcca(rtwdev, true); 3705 3706 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3707 } 3708 rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)3709 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3710 struct ieee80211_vif *vif, bool hw_scan) 3711 { 3712 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3713 3714 if (!rtwvif) 3715 return; 3716 3717 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3718 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3719 3720 rtw89_chip_rfk_scan(rtwdev, false); 3721 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3722 rtw89_phy_config_edcca(rtwdev, false); 3723 3724 rtwdev->scanning = false; 3725 rtwdev->dig.bypass_dig = true; 3726 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3727 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3728 } 3729 rtw89_read_chip_ver(struct rtw89_dev * rtwdev)3730 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3731 { 3732 const struct rtw89_chip_info *chip = rtwdev->chip; 3733 int ret; 3734 u8 val; 3735 u8 cv; 3736 3737 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3738 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3739 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3740 cv = CHIP_CAV; 3741 else 3742 cv = CHIP_CBV; 3743 } 3744 3745 rtwdev->hal.cv = cv; 3746 3747 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 3748 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 3749 if (ret) 3750 return; 3751 3752 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 3753 } 3754 } 3755 rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)3756 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3757 { 3758 rtwdev->hal.support_cckpd = 3759 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3760 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3761 rtwdev->hal.support_igi = 3762 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3763 } 3764 rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)3765 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 3766 { 3767 const struct rtw89_chip_info *chip = rtwdev->chip; 3768 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 3769 struct rtw89_efuse *efuse = &rtwdev->efuse; 3770 u8 rfe_type = efuse->rfe_type; 3771 3772 if (!conf) 3773 goto out; 3774 3775 while (conf->rfe_parms) { 3776 if (rfe_type == conf->rfe_type) { 3777 rtwdev->rfe_parms = conf->rfe_parms; 3778 return; 3779 } 3780 conf++; 3781 } 3782 3783 out: 3784 rtwdev->rfe_parms = chip->dflt_parms; 3785 } 3786 rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)3787 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3788 { 3789 int ret; 3790 3791 ret = rtw89_mac_partial_init(rtwdev); 3792 if (ret) 3793 return ret; 3794 3795 ret = rtw89_parse_efuse_map(rtwdev); 3796 if (ret) 3797 return ret; 3798 3799 ret = rtw89_parse_phycap_map(rtwdev); 3800 if (ret) 3801 return ret; 3802 3803 ret = rtw89_mac_setup_phycap(rtwdev); 3804 if (ret) 3805 return ret; 3806 3807 rtw89_core_setup_phycap(rtwdev); 3808 rtw89_core_setup_rfe_parms(rtwdev); 3809 3810 rtw89_mac_pwr_off(rtwdev); 3811 3812 return 0; 3813 } 3814 rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)3815 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3816 { 3817 rtw89_chip_fem_setup(rtwdev); 3818 3819 return 0; 3820 } 3821 rtw89_chip_info_setup(struct rtw89_dev * rtwdev)3822 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3823 { 3824 int ret; 3825 3826 rtw89_read_chip_ver(rtwdev); 3827 3828 ret = rtw89_wait_firmware_completion(rtwdev); 3829 if (ret) { 3830 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3831 return ret; 3832 } 3833 3834 ret = rtw89_fw_recognize(rtwdev); 3835 if (ret) { 3836 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3837 return ret; 3838 } 3839 3840 ret = rtw89_fw_recognize_elements(rtwdev); 3841 if (ret) { 3842 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 3843 return ret; 3844 } 3845 3846 ret = rtw89_chip_efuse_info_setup(rtwdev); 3847 if (ret) 3848 return ret; 3849 3850 ret = rtw89_chip_board_info_setup(rtwdev); 3851 if (ret) 3852 return ret; 3853 3854 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 3855 3856 return 0; 3857 } 3858 EXPORT_SYMBOL(rtw89_chip_info_setup); 3859 rtw89_core_register_hw(struct rtw89_dev * rtwdev)3860 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3861 { 3862 struct ieee80211_hw *hw = rtwdev->hw; 3863 struct rtw89_efuse *efuse = &rtwdev->efuse; 3864 struct rtw89_hal *hal = &rtwdev->hal; 3865 int ret; 3866 int tx_headroom = IEEE80211_HT_CTL_LEN; 3867 3868 hw->vif_data_size = sizeof(struct rtw89_vif); 3869 hw->sta_data_size = sizeof(struct rtw89_sta); 3870 hw->txq_data_size = sizeof(struct rtw89_txq); 3871 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3872 3873 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3874 3875 hw->extra_tx_headroom = tx_headroom; 3876 hw->queues = IEEE80211_NUM_ACS; 3877 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3878 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3879 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 3880 3881 ieee80211_hw_set(hw, SIGNAL_DBM); 3882 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3883 ieee80211_hw_set(hw, MFP_CAPABLE); 3884 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3885 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3886 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3887 ieee80211_hw_set(hw, TX_AMSDU); 3888 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3889 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3890 ieee80211_hw_set(hw, SUPPORTS_PS); 3891 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3892 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3893 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3894 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 3895 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 3896 ieee80211_hw_set(hw, CONNECTION_MONITOR); 3897 3898 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3899 BIT(NL80211_IFTYPE_AP) | 3900 BIT(NL80211_IFTYPE_P2P_CLIENT) | 3901 BIT(NL80211_IFTYPE_P2P_GO); 3902 3903 if (hal->ant_diversity) { 3904 hw->wiphy->available_antennas_tx = 0x3; 3905 hw->wiphy->available_antennas_rx = 0x3; 3906 } else { 3907 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3908 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3909 } 3910 3911 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3912 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 3913 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ; 3914 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3915 3916 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3917 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3918 3919 #ifdef CONFIG_PM 3920 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 3921 #endif 3922 3923 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3924 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3925 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3926 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3927 hw->wiphy->max_remain_on_channel_duration = 1000; 3928 3929 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3930 3931 ret = rtw89_core_set_supported_band(rtwdev); 3932 if (ret) { 3933 rtw89_err(rtwdev, "failed to set supported band\n"); 3934 return ret; 3935 } 3936 3937 ret = rtw89_regd_setup(rtwdev); 3938 if (ret) { 3939 rtw89_err(rtwdev, "failed to set up regd\n"); 3940 goto err_free_supported_band; 3941 } 3942 3943 hw->wiphy->sar_capa = &rtw89_sar_capa; 3944 3945 ret = ieee80211_register_hw(hw); 3946 if (ret) { 3947 rtw89_err(rtwdev, "failed to register hw\n"); 3948 goto err_free_supported_band; 3949 } 3950 3951 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3952 if (ret) { 3953 rtw89_err(rtwdev, "failed to init regd\n"); 3954 goto err_unregister_hw; 3955 } 3956 3957 return 0; 3958 3959 err_unregister_hw: 3960 ieee80211_unregister_hw(hw); 3961 err_free_supported_band: 3962 rtw89_core_clr_supported_band(rtwdev); 3963 3964 return ret; 3965 } 3966 rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)3967 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3968 { 3969 struct ieee80211_hw *hw = rtwdev->hw; 3970 3971 ieee80211_unregister_hw(hw); 3972 rtw89_core_clr_supported_band(rtwdev); 3973 } 3974 rtw89_core_register(struct rtw89_dev * rtwdev)3975 int rtw89_core_register(struct rtw89_dev *rtwdev) 3976 { 3977 int ret; 3978 3979 ret = rtw89_core_register_hw(rtwdev); 3980 if (ret) { 3981 rtw89_err(rtwdev, "failed to register core hw\n"); 3982 return ret; 3983 } 3984 3985 rtw89_debugfs_init(rtwdev); 3986 3987 return 0; 3988 } 3989 EXPORT_SYMBOL(rtw89_core_register); 3990 rtw89_core_unregister(struct rtw89_dev * rtwdev)3991 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3992 { 3993 rtw89_core_unregister_hw(rtwdev); 3994 } 3995 EXPORT_SYMBOL(rtw89_core_unregister); 3996 rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)3997 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3998 u32 bus_data_size, 3999 const struct rtw89_chip_info *chip) 4000 { 4001 struct rtw89_fw_info early_fw = {}; 4002 const struct firmware *firmware; 4003 struct ieee80211_hw *hw; 4004 struct rtw89_dev *rtwdev; 4005 struct ieee80211_ops *ops; 4006 u32 driver_data_size; 4007 int fw_format = -1; 4008 bool no_chanctx; 4009 4010 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4011 4012 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4013 if (!ops) 4014 goto err; 4015 4016 no_chanctx = chip->support_chanctx_num == 0 || 4017 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4018 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4019 4020 if (no_chanctx) { 4021 ops->add_chanctx = NULL; 4022 ops->remove_chanctx = NULL; 4023 ops->change_chanctx = NULL; 4024 ops->assign_vif_chanctx = NULL; 4025 ops->unassign_vif_chanctx = NULL; 4026 ops->remain_on_channel = NULL; 4027 ops->cancel_remain_on_channel = NULL; 4028 } 4029 4030 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4031 hw = ieee80211_alloc_hw(driver_data_size, ops); 4032 if (!hw) 4033 goto err; 4034 4035 hw->wiphy->iface_combinations = rtw89_iface_combs; 4036 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4037 4038 rtwdev = hw->priv; 4039 rtwdev->hw = hw; 4040 rtwdev->dev = device; 4041 rtwdev->ops = ops; 4042 rtwdev->chip = chip; 4043 rtwdev->fw.req.firmware = firmware; 4044 rtwdev->fw.fw_format = fw_format; 4045 4046 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4047 no_chanctx ? "without" : "with"); 4048 4049 return rtwdev; 4050 4051 err: 4052 kfree(ops); 4053 release_firmware(firmware); 4054 return NULL; 4055 } 4056 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4057 rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)4058 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4059 { 4060 kfree(rtwdev->ops); 4061 release_firmware(rtwdev->fw.req.firmware); 4062 ieee80211_free_hw(rtwdev->hw); 4063 } 4064 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4065 4066 MODULE_AUTHOR("Realtek Corporation"); 4067 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4068 MODULE_LICENSE("Dual BSD/GPL"); 4069