1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
19 #include "hw/misc/aspeed_scu.h"
20 #include "hw/adc/aspeed_adc.h"
21 #include "hw/misc/aspeed_gfx.h"
22 #include "hw/misc/aspeed_sdmc.h"
23 #include "hw/misc/aspeed_xdma.h"
24 #include "hw/timer/aspeed_timer.h"
25 #include "hw/rtc/aspeed_rtc.h"
26 #include "hw/misc/aspeed_ibt.h"
27 #include "hw/i2c/aspeed_i2c.h"
28 #include "hw/i3c/aspeed_i3c.h"
29 #include "hw/ssi/aspeed_smc.h"
30 #include "hw/misc/aspeed_hace.h"
31 #include "hw/misc/aspeed_sbc.h"
32 #include "hw/misc/aspeed_sli.h"
33 #include "hw/misc/aspeed_pwm.h"
34 #include "hw/watchdog/wdt_aspeed.h"
35 #include "hw/net/ftgmac100.h"
36 #include "target/arm/cpu.h"
37 #include "hw/gpio/aspeed_gpio.h"
38 #include "hw/gpio/aspeed_sgpio.h"
39 #include "hw/sd/aspeed_sdhci.h"
40 #include "hw/usb/hcd-ehci.h"
41 #include "qom/object.h"
42 #include "hw/misc/aspeed_lpc.h"
43 #include "hw/misc/unimp.h"
44 #include "hw/pci-host/aspeed_pcie.h"
45 #include "hw/misc/aspeed_peci.h"
46 #include "hw/fsi/aspeed_apb2opb.h"
47 #include "hw/char/serial-mm.h"
48 #include "hw/intc/arm_gicv3.h"
49 #include "hw/misc/aspeed_ltpi.h"
50 #include "hw/arm/aspeed_ast1700.h"
51
52 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
53
54 #define ASPEED_SPIS_NUM 3
55 #define ASPEED_SGPIO_NUM 2
56 #define ASPEED_EHCIS_NUM 4
57 #define ASPEED_WDTS_NUM 8
58 #define ASPEED_CPUS_NUM 4
59 #define ASPEED_MACS_NUM 4
60 #define ASPEED_UARTS_NUM 13
61 #define ASPEED_JTAG_NUM 2
62 #define ASPEED_PCIE_NUM 3
63 #define ASPEED_INTC_NUM 2
64 #define ASPEED_IOEXP_NUM 2
65
66 struct AspeedSoCState {
67 DeviceState parent;
68
69 MemoryRegion *memory;
70 MemoryRegion *dram_mr;
71 MemoryRegion dram_container;
72 MemoryRegion sram;
73 MemoryRegion spi_boot_container;
74 MemoryRegion spi_boot;
75 MemoryRegion vbootrom;
76 MemoryRegion pcie_mmio_alias[ASPEED_PCIE_NUM];
77 AddressSpace dram_as;
78 AspeedRtcState rtc;
79 AspeedTimerCtrlState timerctrl;
80 AspeedIBTState ibt;
81 AspeedI2CState i2c;
82 AspeedI3CState i3c;
83 AspeedSCUState scu;
84 AspeedSCUState scuio;
85 AspeedHACEState hace;
86 AspeedXDMAState xdma;
87 AspeedADCState adc;
88 AspeedSMCState fmc;
89 AspeedSMCState spi[ASPEED_SPIS_NUM];
90 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
91 AspeedSBCState sbc;
92 AspeedSLIState sli;
93 AspeedSLIState sliio;
94 MemoryRegion secsram;
95 UnimplementedDeviceState sbc_unimplemented;
96 AspeedSDMCState sdmc;
97 AspeedWDTState wdt[ASPEED_WDTS_NUM];
98 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
99 AspeedMiiState mii[ASPEED_MACS_NUM];
100 AspeedGPIOState gpio;
101 AspeedGPIOState gpio_1_8v;
102 AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM];
103 AspeedSDHCIState sdhci;
104 AspeedSDHCIState emmc;
105 AspeedLPCState lpc;
106 AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
107 AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
108 AspeedPECIState peci;
109 AspeedGFXState gfx;
110 SerialMM uart[ASPEED_UARTS_NUM];
111 Clock *sysclk;
112 UnimplementedDeviceState iomem;
113 UnimplementedDeviceState iomem0;
114 UnimplementedDeviceState iomem1;
115 UnimplementedDeviceState video;
116 UnimplementedDeviceState emmc_boot_controller;
117 UnimplementedDeviceState dpmcu;
118 AspeedPWMState pwm;
119 UnimplementedDeviceState espi;
120 UnimplementedDeviceState udc;
121 AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
122 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
123 AspeedAPB2OPBState fsi[2];
124 AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
125 };
126
127 #define TYPE_ASPEED_SOC "aspeed-soc"
128 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
129
130 struct Aspeed2400SoCState {
131 AspeedSoCState parent;
132
133 ARMCPU cpu[ASPEED_CPUS_NUM];
134 AspeedVICState vic;
135 };
136
137 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
138 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
139
140 struct Aspeed2600SoCState {
141 AspeedSoCState parent;
142
143 A15MPPrivState a7mpcore;
144 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
145 };
146
147 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
148 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
149
150 struct Aspeed27x0SoCState {
151 AspeedSoCState parent;
152
153 ARMCPU cpu[ASPEED_CPUS_NUM];
154 AspeedINTCState intc[ASPEED_INTC_NUM];
155 AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
156 GICv3State gic;
157 MemoryRegion dram_empty;
158 };
159
160 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
161 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
162
163 struct Aspeed10x0SoCState {
164 AspeedSoCState parent;
165
166 ARMv7MState armv7m;
167 };
168
169 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
170 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
171
172 struct AspeedSoCClass {
173 DeviceClass parent_class;
174
175 /** valid_cpu_types: NULL terminated array of a single CPU type. */
176 const char * const *valid_cpu_types;
177 uint32_t silicon_rev;
178 uint64_t sram_size;
179 uint64_t secsram_size;
180 int pcie_num;
181 int spis_num;
182 int sgpio_num;
183 int ehcis_num;
184 int wdts_num;
185 int macs_num;
186 int uarts_num;
187 int uarts_base;
188 int ioexp_num;
189 const int *irqmap;
190 const hwaddr *memmap;
191 uint32_t num_cpus;
192 bool (*boot_from_emmc)(AspeedSoCState *s);
193 };
194
195 enum {
196 ASPEED_DEV_VBOOTROM,
197 ASPEED_DEV_SPI_BOOT,
198 ASPEED_DEV_IOMEM,
199 ASPEED_DEV_IOMEM0,
200 ASPEED_DEV_IOMEM1,
201 ASPEED_DEV_UART0,
202 ASPEED_DEV_UART1,
203 ASPEED_DEV_UART2,
204 ASPEED_DEV_UART3,
205 ASPEED_DEV_UART4,
206 ASPEED_DEV_UART5,
207 ASPEED_DEV_UART6,
208 ASPEED_DEV_UART7,
209 ASPEED_DEV_UART8,
210 ASPEED_DEV_UART9,
211 ASPEED_DEV_UART10,
212 ASPEED_DEV_UART11,
213 ASPEED_DEV_UART12,
214 ASPEED_DEV_UART13,
215 ASPEED_DEV_VUART,
216 ASPEED_DEV_FMC,
217 ASPEED_DEV_SPI0,
218 ASPEED_DEV_SPI1,
219 ASPEED_DEV_SPI2,
220 ASPEED_DEV_EHCI1,
221 ASPEED_DEV_EHCI2,
222 ASPEED_DEV_EHCI3,
223 ASPEED_DEV_EHCI4,
224 ASPEED_DEV_VIC,
225 ASPEED_DEV_INTC,
226 ASPEED_DEV_INTCIO,
227 ASPEED_DEV_SDMC,
228 ASPEED_DEV_SCU,
229 ASPEED_DEV_ADC,
230 ASPEED_DEV_SBC,
231 ASPEED_DEV_SECSRAM,
232 ASPEED_DEV_EMMC_BC,
233 ASPEED_DEV_VIDEO,
234 ASPEED_DEV_SRAM,
235 ASPEED_DEV_SDHCI,
236 ASPEED_DEV_GPIO,
237 ASPEED_DEV_GPIO_1_8V,
238 ASPEED_DEV_SGPIOM0,
239 ASPEED_DEV_SGPIOM1,
240 ASPEED_DEV_RTC,
241 ASPEED_DEV_TIMER1,
242 ASPEED_DEV_TIMER2,
243 ASPEED_DEV_TIMER3,
244 ASPEED_DEV_TIMER4,
245 ASPEED_DEV_TIMER5,
246 ASPEED_DEV_TIMER6,
247 ASPEED_DEV_TIMER7,
248 ASPEED_DEV_TIMER8,
249 ASPEED_DEV_WDT,
250 ASPEED_DEV_PWM,
251 ASPEED_DEV_LPC,
252 ASPEED_DEV_IBT,
253 ASPEED_DEV_I2C,
254 ASPEED_DEV_PCIE0,
255 ASPEED_DEV_PCIE1,
256 ASPEED_DEV_PCIE2,
257 ASPEED_DEV_PCIE_PHY0,
258 ASPEED_DEV_PCIE_PHY1,
259 ASPEED_DEV_PCIE_PHY2,
260 ASPEED_DEV_PCIE_MMIO0,
261 ASPEED_DEV_PCIE_MMIO1,
262 ASPEED_DEV_PCIE_MMIO2,
263 ASPEED_DEV_PECI,
264 ASPEED_DEV_ETH1,
265 ASPEED_DEV_ETH2,
266 ASPEED_DEV_ETH3,
267 ASPEED_DEV_ETH4,
268 ASPEED_DEV_MII1,
269 ASPEED_DEV_MII2,
270 ASPEED_DEV_MII3,
271 ASPEED_DEV_MII4,
272 ASPEED_DEV_SDRAM,
273 ASPEED_DEV_XDMA,
274 ASPEED_DEV_EMMC,
275 ASPEED_DEV_KCS,
276 ASPEED_DEV_HACE,
277 ASPEED_DEV_GFX,
278 ASPEED_DEV_DPMCU,
279 ASPEED_DEV_DP,
280 ASPEED_DEV_I3C,
281 ASPEED_DEV_ESPI,
282 ASPEED_DEV_UDC,
283 ASPEED_DEV_JTAG0,
284 ASPEED_DEV_JTAG1,
285 ASPEED_DEV_FSI1,
286 ASPEED_DEV_FSI2,
287 ASPEED_DEV_SCUIO,
288 ASPEED_DEV_SLI,
289 ASPEED_DEV_SLIIO,
290 ASPEED_GIC_DIST,
291 ASPEED_GIC_REDIST,
292 ASPEED_DEV_IPC0,
293 ASPEED_DEV_IPC1,
294 ASPEED_DEV_LTPI_CTRL1,
295 ASPEED_DEV_LTPI_CTRL2,
296 ASPEED_DEV_LTPI_IO0,
297 ASPEED_DEV_LTPI_IO1,
298 ASPEED_DEV_IOEXP0_I2C,
299 ASPEED_DEV_IOEXP1_I2C,
300 ASPEED_DEV_IOEXP0_INTCIO,
301 ASPEED_DEV_IOEXP1_INTCIO,
302 ASPEED_DEV_IOEXP0_I3C,
303 ASPEED_DEV_IOEXP1_I3C,
304 };
305
306 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
307 bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
308 const hwaddr addr, Error **errp);
309 void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
310 int uarts_num, Chardev *chr);
311 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
312 void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
313 hwaddr addr);
314 void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
315 const char *name, hwaddr addr,
316 uint64_t size);
317 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
318 unsigned int count, int unit0);
319 void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
320 Error **errp);
321 void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
322 MemoryRegion *boot_rom, uint64_t rom_size);
323 void aspeed_load_vbootrom(AspeedSoCState *soc, const char *bios_name,
324 Error **errp);
325
aspeed_uart_index(int uart_dev)326 static inline int aspeed_uart_index(int uart_dev)
327 {
328 return uart_dev - ASPEED_DEV_UART0;
329 }
330
aspeed_uart_first(int uarts_base)331 static inline int aspeed_uart_first(int uarts_base)
332 {
333 return aspeed_uart_index(uarts_base);
334 }
335
aspeed_uart_last(int uarts_base,int uarts_num)336 static inline int aspeed_uart_last(int uarts_base, int uarts_num)
337 {
338 return aspeed_uart_first(uarts_base) + uarts_num - 1;
339 }
340
341 #endif /* ASPEED_SOC_H */
342