1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 i-cache-size = <32768>; 340 i-cache-line-size = <64>; 341 i-cache-sets = <256>; 342 d-cache-size = <32768>; 343 d-cache-line-size = <64>; 344 d-cache-sets = <128>; 345 next-level-cache = <&l2_0>; 346 #cooling-cells = <2>; 347 mediatek,cci = <&cci>; 348 }; 349 350 cpu1: cpu@1 { 351 device_type = "cpu"; 352 compatible = "arm,cortex-a53"; 353 reg = <0x001>; 354 enable-method = "psci"; 355 capacity-dmips-mhz = <741>; 356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 357 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 359 clock-names = "cpu", "intermediate"; 360 operating-points-v2 = <&cluster0_opp>; 361 dynamic-power-coefficient = <84>; 362 i-cache-size = <32768>; 363 i-cache-line-size = <64>; 364 i-cache-sets = <256>; 365 d-cache-size = <32768>; 366 d-cache-line-size = <64>; 367 d-cache-sets = <128>; 368 next-level-cache = <&l2_0>; 369 #cooling-cells = <2>; 370 mediatek,cci = <&cci>; 371 }; 372 373 cpu2: cpu@2 { 374 device_type = "cpu"; 375 compatible = "arm,cortex-a53"; 376 reg = <0x002>; 377 enable-method = "psci"; 378 capacity-dmips-mhz = <741>; 379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 380 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 382 clock-names = "cpu", "intermediate"; 383 operating-points-v2 = <&cluster0_opp>; 384 dynamic-power-coefficient = <84>; 385 i-cache-size = <32768>; 386 i-cache-line-size = <64>; 387 i-cache-sets = <256>; 388 d-cache-size = <32768>; 389 d-cache-line-size = <64>; 390 d-cache-sets = <128>; 391 next-level-cache = <&l2_0>; 392 #cooling-cells = <2>; 393 mediatek,cci = <&cci>; 394 }; 395 396 cpu3: cpu@3 { 397 device_type = "cpu"; 398 compatible = "arm,cortex-a53"; 399 reg = <0x003>; 400 enable-method = "psci"; 401 capacity-dmips-mhz = <741>; 402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 403 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 405 clock-names = "cpu", "intermediate"; 406 operating-points-v2 = <&cluster0_opp>; 407 dynamic-power-coefficient = <84>; 408 i-cache-size = <32768>; 409 i-cache-line-size = <64>; 410 i-cache-sets = <256>; 411 d-cache-size = <32768>; 412 d-cache-line-size = <64>; 413 d-cache-sets = <128>; 414 next-level-cache = <&l2_0>; 415 #cooling-cells = <2>; 416 mediatek,cci = <&cci>; 417 }; 418 419 cpu4: cpu@100 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a73"; 422 reg = <0x100>; 423 enable-method = "psci"; 424 capacity-dmips-mhz = <1024>; 425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 426 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 428 clock-names = "cpu", "intermediate"; 429 operating-points-v2 = <&cluster1_opp>; 430 dynamic-power-coefficient = <211>; 431 i-cache-size = <65536>; 432 i-cache-line-size = <64>; 433 i-cache-sets = <256>; 434 d-cache-size = <65536>; 435 d-cache-line-size = <64>; 436 d-cache-sets = <256>; 437 next-level-cache = <&l2_1>; 438 #cooling-cells = <2>; 439 mediatek,cci = <&cci>; 440 }; 441 442 cpu5: cpu@101 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a73"; 445 reg = <0x101>; 446 enable-method = "psci"; 447 capacity-dmips-mhz = <1024>; 448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 449 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 451 clock-names = "cpu", "intermediate"; 452 operating-points-v2 = <&cluster1_opp>; 453 dynamic-power-coefficient = <211>; 454 i-cache-size = <65536>; 455 i-cache-line-size = <64>; 456 i-cache-sets = <256>; 457 d-cache-size = <65536>; 458 d-cache-line-size = <64>; 459 d-cache-sets = <256>; 460 next-level-cache = <&l2_1>; 461 #cooling-cells = <2>; 462 mediatek,cci = <&cci>; 463 }; 464 465 cpu6: cpu@102 { 466 device_type = "cpu"; 467 compatible = "arm,cortex-a73"; 468 reg = <0x102>; 469 enable-method = "psci"; 470 capacity-dmips-mhz = <1024>; 471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 472 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 474 clock-names = "cpu", "intermediate"; 475 operating-points-v2 = <&cluster1_opp>; 476 dynamic-power-coefficient = <211>; 477 i-cache-size = <65536>; 478 i-cache-line-size = <64>; 479 i-cache-sets = <256>; 480 d-cache-size = <65536>; 481 d-cache-line-size = <64>; 482 d-cache-sets = <256>; 483 next-level-cache = <&l2_1>; 484 #cooling-cells = <2>; 485 mediatek,cci = <&cci>; 486 }; 487 488 cpu7: cpu@103 { 489 device_type = "cpu"; 490 compatible = "arm,cortex-a73"; 491 reg = <0x103>; 492 enable-method = "psci"; 493 capacity-dmips-mhz = <1024>; 494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 495 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 497 clock-names = "cpu", "intermediate"; 498 operating-points-v2 = <&cluster1_opp>; 499 dynamic-power-coefficient = <211>; 500 i-cache-size = <65536>; 501 i-cache-line-size = <64>; 502 i-cache-sets = <256>; 503 d-cache-size = <65536>; 504 d-cache-line-size = <64>; 505 d-cache-sets = <256>; 506 next-level-cache = <&l2_1>; 507 #cooling-cells = <2>; 508 mediatek,cci = <&cci>; 509 }; 510 511 idle-states { 512 entry-method = "psci"; 513 514 CPU_SLEEP: cpu-sleep { 515 compatible = "arm,idle-state"; 516 local-timer-stop; 517 arm,psci-suspend-param = <0x00010001>; 518 entry-latency-us = <200>; 519 exit-latency-us = <200>; 520 min-residency-us = <800>; 521 }; 522 523 CLUSTER_SLEEP0: cluster-sleep-0 { 524 compatible = "arm,idle-state"; 525 local-timer-stop; 526 arm,psci-suspend-param = <0x01010001>; 527 entry-latency-us = <250>; 528 exit-latency-us = <400>; 529 min-residency-us = <1000>; 530 }; 531 CLUSTER_SLEEP1: cluster-sleep-1 { 532 compatible = "arm,idle-state"; 533 local-timer-stop; 534 arm,psci-suspend-param = <0x01010001>; 535 entry-latency-us = <250>; 536 exit-latency-us = <400>; 537 min-residency-us = <1300>; 538 }; 539 }; 540 541 l2_0: l2-cache0 { 542 compatible = "cache"; 543 cache-level = <2>; 544 cache-size = <1048576>; 545 cache-line-size = <64>; 546 cache-sets = <1024>; 547 cache-unified; 548 }; 549 550 l2_1: l2-cache1 { 551 compatible = "cache"; 552 cache-level = <2>; 553 cache-size = <1048576>; 554 cache-line-size = <64>; 555 cache-sets = <1024>; 556 cache-unified; 557 }; 558 }; 559 560 gpu_opp_table: opp-table-0 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 opp-300000000 { 565 opp-hz = /bits/ 64 <300000000>; 566 opp-microvolt = <625000>; 567 }; 568 569 opp-320000000 { 570 opp-hz = /bits/ 64 <320000000>; 571 opp-microvolt = <631250>; 572 }; 573 574 opp-340000000 { 575 opp-hz = /bits/ 64 <340000000>; 576 opp-microvolt = <637500>; 577 }; 578 579 opp-360000000 { 580 opp-hz = /bits/ 64 <360000000>; 581 opp-microvolt = <643750>; 582 }; 583 584 opp-380000000 { 585 opp-hz = /bits/ 64 <380000000>; 586 opp-microvolt = <650000>; 587 }; 588 589 opp-400000000 { 590 opp-hz = /bits/ 64 <400000000>; 591 opp-microvolt = <656250>; 592 }; 593 594 opp-420000000 { 595 opp-hz = /bits/ 64 <420000000>; 596 opp-microvolt = <662500>; 597 }; 598 599 opp-460000000 { 600 opp-hz = /bits/ 64 <460000000>; 601 opp-microvolt = <675000>; 602 }; 603 604 opp-500000000 { 605 opp-hz = /bits/ 64 <500000000>; 606 opp-microvolt = <687500>; 607 }; 608 609 opp-540000000 { 610 opp-hz = /bits/ 64 <540000000>; 611 opp-microvolt = <700000>; 612 }; 613 614 opp-580000000 { 615 opp-hz = /bits/ 64 <580000000>; 616 opp-microvolt = <712500>; 617 }; 618 619 opp-620000000 { 620 opp-hz = /bits/ 64 <620000000>; 621 opp-microvolt = <725000>; 622 }; 623 624 opp-653000000 { 625 opp-hz = /bits/ 64 <653000000>; 626 opp-microvolt = <743750>; 627 }; 628 629 opp-698000000 { 630 opp-hz = /bits/ 64 <698000000>; 631 opp-microvolt = <768750>; 632 }; 633 634 opp-743000000 { 635 opp-hz = /bits/ 64 <743000000>; 636 opp-microvolt = <793750>; 637 }; 638 639 opp-800000000 { 640 opp-hz = /bits/ 64 <800000000>; 641 opp-microvolt = <825000>; 642 }; 643 }; 644 645 pmu-a53 { 646 compatible = "arm,cortex-a53-pmu"; 647 interrupt-parent = <&gic>; 648 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 649 }; 650 651 pmu-a73 { 652 compatible = "arm,cortex-a73-pmu"; 653 interrupt-parent = <&gic>; 654 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 655 }; 656 657 psci { 658 compatible = "arm,psci-1.0"; 659 method = "smc"; 660 }; 661 662 clk13m: fixed-factor-clock-13m { 663 compatible = "fixed-factor-clock"; 664 #clock-cells = <0>; 665 clocks = <&clk26m>; 666 clock-div = <2>; 667 clock-mult = <1>; 668 clock-output-names = "clk13m"; 669 }; 670 671 clk26m: oscillator { 672 compatible = "fixed-clock"; 673 #clock-cells = <0>; 674 clock-frequency = <26000000>; 675 clock-output-names = "clk26m"; 676 }; 677 678 timer { 679 compatible = "arm,armv8-timer"; 680 interrupt-parent = <&gic>; 681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 685 }; 686 687 soc { 688 #address-cells = <2>; 689 #size-cells = <2>; 690 compatible = "simple-bus"; 691 ranges; 692 693 soc_data: efuse@8000000 { 694 compatible = "mediatek,mt8183-efuse", 695 "mediatek,efuse"; 696 reg = <0 0x08000000 0 0x0010>; 697 #address-cells = <1>; 698 #size-cells = <1>; 699 status = "disabled"; 700 }; 701 702 gic: interrupt-controller@c000000 { 703 compatible = "arm,gic-v3"; 704 #interrupt-cells = <4>; 705 interrupt-parent = <&gic>; 706 interrupt-controller; 707 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 708 <0 0x0c100000 0 0x200000>, /* GICR */ 709 <0 0x0c400000 0 0x2000>, /* GICC */ 710 <0 0x0c410000 0 0x1000>, /* GICH */ 711 <0 0x0c420000 0 0x2000>; /* GICV */ 712 713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 714 ppi-partitions { 715 ppi_cluster0: interrupt-partition-0 { 716 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 717 }; 718 ppi_cluster1: interrupt-partition-1 { 719 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 720 }; 721 }; 722 }; 723 724 mcucfg: syscon@c530000 { 725 compatible = "mediatek,mt8183-mcucfg", "syscon"; 726 reg = <0 0x0c530000 0 0x1000>; 727 #clock-cells = <1>; 728 }; 729 730 sysirq: interrupt-controller@c530a80 { 731 compatible = "mediatek,mt8183-sysirq", 732 "mediatek,mt6577-sysirq"; 733 interrupt-controller; 734 #interrupt-cells = <3>; 735 interrupt-parent = <&gic>; 736 reg = <0 0x0c530a80 0 0x50>; 737 }; 738 739 cpu_debug0: cpu-debug@d410000 { 740 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 741 reg = <0x0 0xd410000 0x0 0x1000>; 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 743 clock-names = "apb_pclk"; 744 cpu = <&cpu0>; 745 }; 746 747 cpu_debug1: cpu-debug@d510000 { 748 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 749 reg = <0x0 0xd510000 0x0 0x1000>; 750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 751 clock-names = "apb_pclk"; 752 cpu = <&cpu1>; 753 }; 754 755 cpu_debug2: cpu-debug@d610000 { 756 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 757 reg = <0x0 0xd610000 0x0 0x1000>; 758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 759 clock-names = "apb_pclk"; 760 cpu = <&cpu2>; 761 }; 762 763 cpu_debug3: cpu-debug@d710000 { 764 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 765 reg = <0x0 0xd710000 0x0 0x1000>; 766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 767 clock-names = "apb_pclk"; 768 cpu = <&cpu3>; 769 }; 770 771 cpu_debug4: cpu-debug@d810000 { 772 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 773 reg = <0x0 0xd810000 0x0 0x1000>; 774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 775 clock-names = "apb_pclk"; 776 cpu = <&cpu4>; 777 }; 778 779 cpu_debug5: cpu-debug@d910000 { 780 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 781 reg = <0x0 0xd910000 0x0 0x1000>; 782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 783 clock-names = "apb_pclk"; 784 cpu = <&cpu5>; 785 }; 786 787 cpu_debug6: cpu-debug@da10000 { 788 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 789 reg = <0x0 0xda10000 0x0 0x1000>; 790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 791 clock-names = "apb_pclk"; 792 cpu = <&cpu6>; 793 }; 794 795 cpu_debug7: cpu-debug@db10000 { 796 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 797 reg = <0x0 0xdb10000 0x0 0x1000>; 798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 799 clock-names = "apb_pclk"; 800 cpu = <&cpu7>; 801 }; 802 803 topckgen: syscon@10000000 { 804 compatible = "mediatek,mt8183-topckgen", "syscon"; 805 reg = <0 0x10000000 0 0x1000>; 806 #clock-cells = <1>; 807 }; 808 809 infracfg: syscon@10001000 { 810 compatible = "mediatek,mt8183-infracfg", "syscon"; 811 reg = <0 0x10001000 0 0x1000>; 812 #clock-cells = <1>; 813 #reset-cells = <1>; 814 }; 815 816 pericfg: syscon@10003000 { 817 compatible = "mediatek,mt8183-pericfg", "syscon"; 818 reg = <0 0x10003000 0 0x1000>; 819 #clock-cells = <1>; 820 }; 821 822 pio: pinctrl@10005000 { 823 compatible = "mediatek,mt8183-pinctrl"; 824 reg = <0 0x10005000 0 0x1000>, 825 <0 0x11f20000 0 0x1000>, 826 <0 0x11e80000 0 0x1000>, 827 <0 0x11e70000 0 0x1000>, 828 <0 0x11e90000 0 0x1000>, 829 <0 0x11d30000 0 0x1000>, 830 <0 0x11d20000 0 0x1000>, 831 <0 0x11c50000 0 0x1000>, 832 <0 0x11f30000 0 0x1000>, 833 <0 0x1000b000 0 0x1000>; 834 reg-names = "iocfg0", "iocfg1", "iocfg2", 835 "iocfg3", "iocfg4", "iocfg5", 836 "iocfg6", "iocfg7", "iocfg8", 837 "eint"; 838 gpio-controller; 839 #gpio-cells = <2>; 840 gpio-ranges = <&pio 0 0 192>; 841 interrupt-controller; 842 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 843 #interrupt-cells = <2>; 844 }; 845 846 scpsys: syscon@10006000 { 847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; 848 reg = <0 0x10006000 0 0x1000>; 849 850 /* System Power Manager */ 851 spm: power-controller { 852 compatible = "mediatek,mt8183-power-controller"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 #power-domain-cells = <1>; 856 857 /* power domain of the SoC */ 858 power-domain@MT8183_POWER_DOMAIN_AUDIO { 859 reg = <MT8183_POWER_DOMAIN_AUDIO>; 860 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 861 <&infracfg CLK_INFRA_AUDIO>, 862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 863 clock-names = "audio", "audio1", "audio2"; 864 #power-domain-cells = <0>; 865 }; 866 867 power-domain@MT8183_POWER_DOMAIN_CONN { 868 reg = <MT8183_POWER_DOMAIN_CONN>; 869 mediatek,infracfg = <&infracfg>; 870 #power-domain-cells = <0>; 871 }; 872 873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 874 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 875 clocks = <&topckgen CLK_TOP_MUX_MFG>; 876 clock-names = "mfg"; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 #power-domain-cells = <1>; 880 881 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 882 reg = <MT8183_POWER_DOMAIN_MFG>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 #power-domain-cells = <1>; 886 887 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 888 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 889 #power-domain-cells = <0>; 890 }; 891 892 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 893 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 894 #power-domain-cells = <0>; 895 }; 896 897 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 898 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 899 mediatek,infracfg = <&infracfg>; 900 #power-domain-cells = <0>; 901 }; 902 }; 903 }; 904 905 power-domain@MT8183_POWER_DOMAIN_DISP { 906 reg = <MT8183_POWER_DOMAIN_DISP>; 907 clocks = <&topckgen CLK_TOP_MUX_MM>, 908 <&mmsys CLK_MM_SMI_COMMON>, 909 <&mmsys CLK_MM_SMI_LARB0>, 910 <&mmsys CLK_MM_SMI_LARB1>, 911 <&mmsys CLK_MM_GALS_COMM0>, 912 <&mmsys CLK_MM_GALS_COMM1>, 913 <&mmsys CLK_MM_GALS_CCU2MM>, 914 <&mmsys CLK_MM_GALS_IPU12MM>, 915 <&mmsys CLK_MM_GALS_IMG2MM>, 916 <&mmsys CLK_MM_GALS_CAM2MM>, 917 <&mmsys CLK_MM_GALS_IPU2MM>; 918 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 919 "mm-4", "mm-5", "mm-6", "mm-7", 920 "mm-8", "mm-9"; 921 mediatek,infracfg = <&infracfg>; 922 mediatek,smi = <&smi_common>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 #power-domain-cells = <1>; 926 927 power-domain@MT8183_POWER_DOMAIN_CAM { 928 reg = <MT8183_POWER_DOMAIN_CAM>; 929 clocks = <&topckgen CLK_TOP_MUX_CAM>, 930 <&camsys CLK_CAM_LARB6>, 931 <&camsys CLK_CAM_LARB3>, 932 <&camsys CLK_CAM_SENINF>, 933 <&camsys CLK_CAM_CAMSV0>, 934 <&camsys CLK_CAM_CAMSV1>, 935 <&camsys CLK_CAM_CAMSV2>, 936 <&camsys CLK_CAM_CCU>; 937 clock-names = "cam", "cam-0", "cam-1", 938 "cam-2", "cam-3", "cam-4", 939 "cam-5", "cam-6"; 940 mediatek,infracfg = <&infracfg>; 941 mediatek,smi = <&smi_common>; 942 #power-domain-cells = <0>; 943 }; 944 945 power-domain@MT8183_POWER_DOMAIN_ISP { 946 reg = <MT8183_POWER_DOMAIN_ISP>; 947 clocks = <&topckgen CLK_TOP_MUX_IMG>, 948 <&imgsys CLK_IMG_LARB5>, 949 <&imgsys CLK_IMG_LARB2>; 950 clock-names = "isp", "isp-0", "isp-1"; 951 mediatek,infracfg = <&infracfg>; 952 mediatek,smi = <&smi_common>; 953 #power-domain-cells = <0>; 954 }; 955 956 power-domain@MT8183_POWER_DOMAIN_VDEC { 957 reg = <MT8183_POWER_DOMAIN_VDEC>; 958 mediatek,smi = <&smi_common>; 959 #power-domain-cells = <0>; 960 }; 961 962 power-domain@MT8183_POWER_DOMAIN_VENC { 963 reg = <MT8183_POWER_DOMAIN_VENC>; 964 mediatek,smi = <&smi_common>; 965 #power-domain-cells = <0>; 966 }; 967 968 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 969 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 970 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 971 <&topckgen CLK_TOP_MUX_DSP>, 972 <&ipu_conn CLK_IPU_CONN_IPU>, 973 <&ipu_conn CLK_IPU_CONN_AHB>, 974 <&ipu_conn CLK_IPU_CONN_AXI>, 975 <&ipu_conn CLK_IPU_CONN_ISP>, 976 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 977 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 978 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 979 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 980 mediatek,infracfg = <&infracfg>; 981 mediatek,smi = <&smi_common>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 #power-domain-cells = <1>; 985 986 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 987 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 988 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 989 clock-names = "vpu2"; 990 mediatek,infracfg = <&infracfg>; 991 #power-domain-cells = <0>; 992 }; 993 994 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 995 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 996 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 997 clock-names = "vpu3"; 998 mediatek,infracfg = <&infracfg>; 999 #power-domain-cells = <0>; 1000 }; 1001 }; 1002 }; 1003 }; 1004 }; 1005 1006 watchdog: watchdog@10007000 { 1007 compatible = "mediatek,mt8183-wdt"; 1008 reg = <0 0x10007000 0 0x100>; 1009 #reset-cells = <1>; 1010 }; 1011 1012 apmixedsys: syscon@1000c000 { 1013 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 1014 reg = <0 0x1000c000 0 0x1000>; 1015 #clock-cells = <1>; 1016 }; 1017 1018 pwrap: pwrap@1000d000 { 1019 compatible = "mediatek,mt8183-pwrap"; 1020 reg = <0 0x1000d000 0 0x1000>; 1021 reg-names = "pwrap"; 1022 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 1024 <&infracfg CLK_INFRA_PMIC_AP>; 1025 clock-names = "spi", "wrap"; 1026 }; 1027 1028 keyboard: keyboard@10010000 { 1029 compatible = "mediatek,mt8183-keypad", 1030 "mediatek,mt6779-keypad"; 1031 reg = <0 0x10010000 0 0x1000>; 1032 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; 1033 clocks = <&clk26m>; 1034 clock-names = "kpd"; 1035 status = "disabled"; 1036 }; 1037 1038 scp: scp@10500000 { 1039 compatible = "mediatek,mt8183-scp"; 1040 reg = <0 0x10500000 0 0x80000>, 1041 <0 0x105c0000 0 0x19080>; 1042 reg-names = "sram", "cfg"; 1043 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&infracfg CLK_INFRA_SCPSYS>; 1045 clock-names = "main"; 1046 memory-region = <&scp_mem_reserved>; 1047 status = "disabled"; 1048 }; 1049 1050 systimer: timer@10017000 { 1051 compatible = "mediatek,mt8183-timer", 1052 "mediatek,mt6765-timer"; 1053 reg = <0 0x10017000 0 0x1000>; 1054 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&clk13m>; 1056 }; 1057 1058 iommu: iommu@10205000 { 1059 compatible = "mediatek,mt8183-m4u"; 1060 reg = <0 0x10205000 0 0x1000>; 1061 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 1062 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 1063 <&larb4>, <&larb5>, <&larb6>; 1064 #iommu-cells = <1>; 1065 }; 1066 1067 gce: mailbox@10238000 { 1068 compatible = "mediatek,mt8183-gce"; 1069 reg = <0 0x10238000 0 0x4000>; 1070 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 1071 #mbox-cells = <2>; 1072 clocks = <&infracfg CLK_INFRA_GCE>; 1073 clock-names = "gce"; 1074 }; 1075 1076 auxadc: auxadc@11001000 { 1077 compatible = "mediatek,mt8183-auxadc", 1078 "mediatek,mt8173-auxadc"; 1079 reg = <0 0x11001000 0 0x1000>; 1080 clocks = <&infracfg CLK_INFRA_AUXADC>; 1081 clock-names = "main"; 1082 #io-channel-cells = <1>; 1083 status = "disabled"; 1084 }; 1085 1086 uart0: serial@11002000 { 1087 compatible = "mediatek,mt8183-uart", 1088 "mediatek,mt6577-uart"; 1089 reg = <0 0x11002000 0 0x1000>; 1090 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 1091 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 1092 clock-names = "baud", "bus"; 1093 status = "disabled"; 1094 }; 1095 1096 uart1: serial@11003000 { 1097 compatible = "mediatek,mt8183-uart", 1098 "mediatek,mt6577-uart"; 1099 reg = <0 0x11003000 0 0x1000>; 1100 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1101 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1102 clock-names = "baud", "bus"; 1103 status = "disabled"; 1104 }; 1105 1106 uart2: serial@11004000 { 1107 compatible = "mediatek,mt8183-uart", 1108 "mediatek,mt6577-uart"; 1109 reg = <0 0x11004000 0 0x1000>; 1110 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1111 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1112 clock-names = "baud", "bus"; 1113 status = "disabled"; 1114 }; 1115 1116 i2c6: i2c@11005000 { 1117 compatible = "mediatek,mt8183-i2c"; 1118 reg = <0 0x11005000 0 0x1000>, 1119 <0 0x11000600 0 0x80>; 1120 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1121 clocks = <&infracfg CLK_INFRA_I2C6>, 1122 <&infracfg CLK_INFRA_AP_DMA>; 1123 clock-names = "main", "dma"; 1124 clock-div = <1>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c0: i2c@11007000 { 1131 compatible = "mediatek,mt8183-i2c"; 1132 reg = <0 0x11007000 0 0x1000>, 1133 <0 0x11000080 0 0x80>; 1134 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1135 clocks = <&infracfg CLK_INFRA_I2C0>, 1136 <&infracfg CLK_INFRA_AP_DMA>; 1137 clock-names = "main", "dma"; 1138 clock-div = <1>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 i2c4: i2c@11008000 { 1145 compatible = "mediatek,mt8183-i2c"; 1146 reg = <0 0x11008000 0 0x1000>, 1147 <0 0x11000100 0 0x80>; 1148 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1149 clocks = <&infracfg CLK_INFRA_I2C1>, 1150 <&infracfg CLK_INFRA_AP_DMA>, 1151 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1152 clock-names = "main", "dma","arb"; 1153 clock-div = <1>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c2: i2c@11009000 { 1160 compatible = "mediatek,mt8183-i2c"; 1161 reg = <0 0x11009000 0 0x1000>, 1162 <0 0x11000280 0 0x80>; 1163 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1164 clocks = <&infracfg CLK_INFRA_I2C2>, 1165 <&infracfg CLK_INFRA_AP_DMA>, 1166 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1167 clock-names = "main", "dma", "arb"; 1168 clock-div = <1>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 spi0: spi@1100a000 { 1175 compatible = "mediatek,mt8183-spi"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 reg = <0 0x1100a000 0 0x1000>; 1179 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1180 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1181 <&topckgen CLK_TOP_MUX_SPI>, 1182 <&infracfg CLK_INFRA_SPI0>; 1183 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1184 status = "disabled"; 1185 }; 1186 1187 svs: svs@1100b000 { 1188 compatible = "mediatek,mt8183-svs"; 1189 reg = <0 0x1100b000 0 0x1000>; 1190 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 1191 clocks = <&infracfg CLK_INFRA_THERM>; 1192 clock-names = "main"; 1193 nvmem-cells = <&svs_calibration>, 1194 <&thermal_calibration>; 1195 nvmem-cell-names = "svs-calibration-data", 1196 "t-calibration-data"; 1197 }; 1198 1199 thermal: thermal@1100b000 { 1200 #thermal-sensor-cells = <1>; 1201 compatible = "mediatek,mt8183-thermal"; 1202 reg = <0 0x1100b000 0 0x1000>; 1203 clocks = <&infracfg CLK_INFRA_THERM>, 1204 <&infracfg CLK_INFRA_AUXADC>; 1205 clock-names = "therm", "auxadc"; 1206 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1207 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1208 mediatek,auxadc = <&auxadc>; 1209 mediatek,apmixedsys = <&apmixedsys>; 1210 nvmem-cells = <&thermal_calibration>; 1211 nvmem-cell-names = "calibration-data"; 1212 }; 1213 1214 pwm0: pwm@1100e000 { 1215 compatible = "mediatek,mt8183-disp-pwm"; 1216 reg = <0 0x1100e000 0 0x1000>; 1217 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1218 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1219 #pwm-cells = <2>; 1220 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1221 <&infracfg CLK_INFRA_DISP_PWM>; 1222 clock-names = "main", "mm"; 1223 }; 1224 1225 pwm1: pwm@11006000 { 1226 compatible = "mediatek,mt8183-pwm"; 1227 reg = <0 0x11006000 0 0x1000>; 1228 #pwm-cells = <2>; 1229 clocks = <&infracfg CLK_INFRA_PWM>, 1230 <&infracfg CLK_INFRA_PWM_HCLK>, 1231 <&infracfg CLK_INFRA_PWM1>, 1232 <&infracfg CLK_INFRA_PWM2>, 1233 <&infracfg CLK_INFRA_PWM3>, 1234 <&infracfg CLK_INFRA_PWM4>; 1235 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1236 "pwm4"; 1237 }; 1238 1239 i2c3: i2c@1100f000 { 1240 compatible = "mediatek,mt8183-i2c"; 1241 reg = <0 0x1100f000 0 0x1000>, 1242 <0 0x11000400 0 0x80>; 1243 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1244 clocks = <&infracfg CLK_INFRA_I2C3>, 1245 <&infracfg CLK_INFRA_AP_DMA>; 1246 clock-names = "main", "dma"; 1247 clock-div = <1>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 spi1: spi@11010000 { 1254 compatible = "mediatek,mt8183-spi"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 reg = <0 0x11010000 0 0x1000>; 1258 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1259 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1260 <&topckgen CLK_TOP_MUX_SPI>, 1261 <&infracfg CLK_INFRA_SPI1>; 1262 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c1: i2c@11011000 { 1267 compatible = "mediatek,mt8183-i2c"; 1268 reg = <0 0x11011000 0 0x1000>, 1269 <0 0x11000480 0 0x80>; 1270 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1271 clocks = <&infracfg CLK_INFRA_I2C4>, 1272 <&infracfg CLK_INFRA_AP_DMA>; 1273 clock-names = "main", "dma"; 1274 clock-div = <1>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 spi2: spi@11012000 { 1281 compatible = "mediatek,mt8183-spi"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 reg = <0 0x11012000 0 0x1000>; 1285 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1286 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1287 <&topckgen CLK_TOP_MUX_SPI>, 1288 <&infracfg CLK_INFRA_SPI2>; 1289 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1290 status = "disabled"; 1291 }; 1292 1293 spi3: spi@11013000 { 1294 compatible = "mediatek,mt8183-spi"; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 reg = <0 0x11013000 0 0x1000>; 1298 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1299 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1300 <&topckgen CLK_TOP_MUX_SPI>, 1301 <&infracfg CLK_INFRA_SPI3>; 1302 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c9: i2c@11014000 { 1307 compatible = "mediatek,mt8183-i2c"; 1308 reg = <0 0x11014000 0 0x1000>, 1309 <0 0x11000180 0 0x80>; 1310 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1311 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1312 <&infracfg CLK_INFRA_AP_DMA>, 1313 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1314 clock-names = "main", "dma", "arb"; 1315 clock-div = <1>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 i2c10: i2c@11015000 { 1322 compatible = "mediatek,mt8183-i2c"; 1323 reg = <0 0x11015000 0 0x1000>, 1324 <0 0x11000300 0 0x80>; 1325 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1326 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1327 <&infracfg CLK_INFRA_AP_DMA>, 1328 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1329 clock-names = "main", "dma", "arb"; 1330 clock-div = <1>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 i2c5: i2c@11016000 { 1337 compatible = "mediatek,mt8183-i2c"; 1338 reg = <0 0x11016000 0 0x1000>, 1339 <0 0x11000500 0 0x80>; 1340 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1341 clocks = <&infracfg CLK_INFRA_I2C5>, 1342 <&infracfg CLK_INFRA_AP_DMA>, 1343 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1344 clock-names = "main", "dma", "arb"; 1345 clock-div = <1>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 i2c11: i2c@11017000 { 1352 compatible = "mediatek,mt8183-i2c"; 1353 reg = <0 0x11017000 0 0x1000>, 1354 <0 0x11000580 0 0x80>; 1355 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1356 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1357 <&infracfg CLK_INFRA_AP_DMA>, 1358 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1359 clock-names = "main", "dma", "arb"; 1360 clock-div = <1>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 spi4: spi@11018000 { 1367 compatible = "mediatek,mt8183-spi"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 reg = <0 0x11018000 0 0x1000>; 1371 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1372 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1373 <&topckgen CLK_TOP_MUX_SPI>, 1374 <&infracfg CLK_INFRA_SPI4>; 1375 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1376 status = "disabled"; 1377 }; 1378 1379 spi5: spi@11019000 { 1380 compatible = "mediatek,mt8183-spi"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 reg = <0 0x11019000 0 0x1000>; 1384 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1385 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1386 <&topckgen CLK_TOP_MUX_SPI>, 1387 <&infracfg CLK_INFRA_SPI5>; 1388 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1389 status = "disabled"; 1390 }; 1391 1392 i2c7: i2c@1101a000 { 1393 compatible = "mediatek,mt8183-i2c"; 1394 reg = <0 0x1101a000 0 0x1000>, 1395 <0 0x11000680 0 0x80>; 1396 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1397 clocks = <&infracfg CLK_INFRA_I2C7>, 1398 <&infracfg CLK_INFRA_AP_DMA>; 1399 clock-names = "main", "dma"; 1400 clock-div = <1>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 status = "disabled"; 1404 }; 1405 1406 i2c8: i2c@1101b000 { 1407 compatible = "mediatek,mt8183-i2c"; 1408 reg = <0 0x1101b000 0 0x1000>, 1409 <0 0x11000700 0 0x80>; 1410 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1411 clocks = <&infracfg CLK_INFRA_I2C8>, 1412 <&infracfg CLK_INFRA_AP_DMA>; 1413 clock-names = "main", "dma"; 1414 clock-div = <1>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 ssusb: usb@11201000 { 1421 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1422 reg = <0 0x11201000 0 0x2e00>, 1423 <0 0x11203e00 0 0x0100>; 1424 reg-names = "mac", "ippc"; 1425 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1426 phys = <&u2port0 PHY_TYPE_USB2>, 1427 <&u3port0 PHY_TYPE_USB3>; 1428 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1429 <&infracfg CLK_INFRA_USB>; 1430 clock-names = "sys_ck", "ref_ck"; 1431 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1432 #address-cells = <2>; 1433 #size-cells = <2>; 1434 ranges; 1435 status = "disabled"; 1436 1437 usb_host: usb@11200000 { 1438 compatible = "mediatek,mt8183-xhci", 1439 "mediatek,mtk-xhci"; 1440 reg = <0 0x11200000 0 0x1000>; 1441 reg-names = "mac"; 1442 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1443 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1444 <&infracfg CLK_INFRA_USB>; 1445 clock-names = "sys_ck", "ref_ck"; 1446 status = "disabled"; 1447 }; 1448 }; 1449 1450 audiosys: audio-controller@11220000 { 1451 compatible = "mediatek,mt8183-audiosys", "syscon"; 1452 reg = <0 0x11220000 0 0x1000>; 1453 #clock-cells = <1>; 1454 afe: mt8183-afe-pcm { 1455 compatible = "mediatek,mt8183-audio"; 1456 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1457 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1458 reset-names = "audiosys"; 1459 power-domains = 1460 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1461 clocks = <&audiosys CLK_AUDIO_AFE>, 1462 <&audiosys CLK_AUDIO_DAC>, 1463 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1464 <&audiosys CLK_AUDIO_ADC>, 1465 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1466 <&audiosys CLK_AUDIO_22M>, 1467 <&audiosys CLK_AUDIO_24M>, 1468 <&audiosys CLK_AUDIO_APLL_TUNER>, 1469 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1470 <&audiosys CLK_AUDIO_I2S1>, 1471 <&audiosys CLK_AUDIO_I2S2>, 1472 <&audiosys CLK_AUDIO_I2S3>, 1473 <&audiosys CLK_AUDIO_I2S4>, 1474 <&audiosys CLK_AUDIO_TDM>, 1475 <&audiosys CLK_AUDIO_TML>, 1476 <&infracfg CLK_INFRA_AUDIO>, 1477 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1478 <&topckgen CLK_TOP_MUX_AUDIO>, 1479 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1480 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1481 <&topckgen CLK_TOP_MUX_AUD_1>, 1482 <&topckgen CLK_TOP_APLL1_CK>, 1483 <&topckgen CLK_TOP_MUX_AUD_2>, 1484 <&topckgen CLK_TOP_APLL2_CK>, 1485 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1486 <&topckgen CLK_TOP_APLL1_D8>, 1487 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1488 <&topckgen CLK_TOP_APLL2_D8>, 1489 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1490 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1491 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1492 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1493 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1494 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1495 <&topckgen CLK_TOP_APLL12_DIV0>, 1496 <&topckgen CLK_TOP_APLL12_DIV1>, 1497 <&topckgen CLK_TOP_APLL12_DIV2>, 1498 <&topckgen CLK_TOP_APLL12_DIV3>, 1499 <&topckgen CLK_TOP_APLL12_DIV4>, 1500 <&topckgen CLK_TOP_APLL12_DIVB>, 1501 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1502 <&clk26m>; 1503 clock-names = "aud_afe_clk", 1504 "aud_dac_clk", 1505 "aud_dac_predis_clk", 1506 "aud_adc_clk", 1507 "aud_adc_adda6_clk", 1508 "aud_apll22m_clk", 1509 "aud_apll24m_clk", 1510 "aud_apll1_tuner_clk", 1511 "aud_apll2_tuner_clk", 1512 "aud_i2s1_bclk_sw", 1513 "aud_i2s2_bclk_sw", 1514 "aud_i2s3_bclk_sw", 1515 "aud_i2s4_bclk_sw", 1516 "aud_tdm_clk", 1517 "aud_tml_clk", 1518 "aud_infra_clk", 1519 "mtkaif_26m_clk", 1520 "top_mux_audio", 1521 "top_mux_aud_intbus", 1522 "top_syspll_d2_d4", 1523 "top_mux_aud_1", 1524 "top_apll1_ck", 1525 "top_mux_aud_2", 1526 "top_apll2_ck", 1527 "top_mux_aud_eng1", 1528 "top_apll1_d8", 1529 "top_mux_aud_eng2", 1530 "top_apll2_d8", 1531 "top_i2s0_m_sel", 1532 "top_i2s1_m_sel", 1533 "top_i2s2_m_sel", 1534 "top_i2s3_m_sel", 1535 "top_i2s4_m_sel", 1536 "top_i2s5_m_sel", 1537 "top_apll12_div0", 1538 "top_apll12_div1", 1539 "top_apll12_div2", 1540 "top_apll12_div3", 1541 "top_apll12_div4", 1542 "top_apll12_divb", 1543 /*"top_apll12_div5",*/ 1544 "top_clk26m_clk"; 1545 }; 1546 }; 1547 1548 mmc0: mmc@11230000 { 1549 compatible = "mediatek,mt8183-mmc"; 1550 reg = <0 0x11230000 0 0x1000>, 1551 <0 0x11f50000 0 0x1000>; 1552 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1553 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1554 <&infracfg CLK_INFRA_MSDC0>, 1555 <&infracfg CLK_INFRA_MSDC0_SCK>; 1556 clock-names = "source", "hclk", "source_cg"; 1557 status = "disabled"; 1558 }; 1559 1560 mmc1: mmc@11240000 { 1561 compatible = "mediatek,mt8183-mmc"; 1562 reg = <0 0x11240000 0 0x1000>, 1563 <0 0x11e10000 0 0x1000>; 1564 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1565 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1566 <&infracfg CLK_INFRA_MSDC1>, 1567 <&infracfg CLK_INFRA_MSDC1_SCK>; 1568 clock-names = "source", "hclk", "source_cg"; 1569 status = "disabled"; 1570 }; 1571 1572 mipi_tx0: dsi-phy@11e50000 { 1573 compatible = "mediatek,mt8183-mipi-tx"; 1574 reg = <0 0x11e50000 0 0x1000>; 1575 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1576 #clock-cells = <0>; 1577 #phy-cells = <0>; 1578 clock-output-names = "mipi_tx0_pll"; 1579 nvmem-cells = <&mipi_tx_calibration>; 1580 nvmem-cell-names = "calibration-data"; 1581 }; 1582 1583 efuse: efuse@11f10000 { 1584 compatible = "mediatek,mt8183-efuse", 1585 "mediatek,efuse"; 1586 reg = <0 0x11f10000 0 0x1000>; 1587 #address-cells = <1>; 1588 #size-cells = <1>; 1589 thermal_calibration: calib@180 { 1590 reg = <0x180 0xc>; 1591 }; 1592 1593 mipi_tx_calibration: calib@190 { 1594 reg = <0x190 0xc>; 1595 }; 1596 1597 svs_calibration: calib@580 { 1598 reg = <0x580 0x64>; 1599 }; 1600 }; 1601 1602 u3phy: t-phy@11f40000 { 1603 compatible = "mediatek,mt8183-tphy", 1604 "mediatek,generic-tphy-v2"; 1605 #address-cells = <1>; 1606 #size-cells = <1>; 1607 ranges = <0 0 0x11f40000 0x1000>; 1608 status = "okay"; 1609 1610 u2port0: usb-phy@0 { 1611 reg = <0x0 0x700>; 1612 clocks = <&clk26m>; 1613 clock-names = "ref"; 1614 #phy-cells = <1>; 1615 mediatek,discth = <15>; 1616 status = "okay"; 1617 }; 1618 1619 u3port0: usb-phy@700 { 1620 reg = <0x0700 0x900>; 1621 clocks = <&clk26m>; 1622 clock-names = "ref"; 1623 #phy-cells = <1>; 1624 status = "okay"; 1625 }; 1626 }; 1627 1628 mfgcfg: syscon@13000000 { 1629 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1630 reg = <0 0x13000000 0 0x1000>; 1631 #clock-cells = <1>; 1632 power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; 1633 }; 1634 1635 gpu: gpu@13040000 { 1636 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost"; 1637 reg = <0 0x13040000 0 0x4000>; 1638 interrupts = 1639 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1640 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1641 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1642 interrupt-names = "job", "mmu", "gpu"; 1643 1644 clocks = <&mfgcfg CLK_MFG_BG3D>; 1645 1646 power-domains = 1647 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1648 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1649 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1650 power-domain-names = "core0", "core1", "core2"; 1651 1652 operating-points-v2 = <&gpu_opp_table>; 1653 }; 1654 1655 mmsys: syscon@14000000 { 1656 compatible = "mediatek,mt8183-mmsys", "syscon"; 1657 reg = <0 0x14000000 0 0x1000>; 1658 #clock-cells = <1>; 1659 #reset-cells = <1>; 1660 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1661 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1662 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1663 }; 1664 1665 dma-controller0@14001000 { 1666 compatible = "mediatek,mt8183-mdp3-rdma"; 1667 reg = <0 0x14001000 0 0x1000>; 1668 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1669 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1670 <CMDQ_EVENT_MDP_RDMA0_EOF>; 1671 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1672 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1673 <&mmsys CLK_MM_MDP_RSZ1>; 1674 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1675 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, 1676 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; 1677 #dma-cells = <1>; 1678 }; 1679 1680 mdp3-rsz0@14003000 { 1681 compatible = "mediatek,mt8183-mdp3-rsz"; 1682 reg = <0 0x14003000 0 0x1000>; 1683 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 1684 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 1685 <CMDQ_EVENT_MDP_RSZ0_EOF>; 1686 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1687 }; 1688 1689 mdp3-rsz1@14004000 { 1690 compatible = "mediatek,mt8183-mdp3-rsz"; 1691 reg = <0 0x14004000 0 0x1000>; 1692 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 1693 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 1694 <CMDQ_EVENT_MDP_RSZ1_EOF>; 1695 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1696 }; 1697 1698 dma-controller@14005000 { 1699 compatible = "mediatek,mt8183-mdp3-wrot"; 1700 reg = <0 0x14005000 0 0x1000>; 1701 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1702 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 1703 <CMDQ_EVENT_MDP_WROT0_EOF>; 1704 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1705 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1706 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1707 #dma-cells = <1>; 1708 }; 1709 1710 mdp3-wdma@14006000 { 1711 compatible = "mediatek,mt8183-mdp3-wdma"; 1712 reg = <0 0x14006000 0 0x1000>; 1713 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1714 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, 1715 <CMDQ_EVENT_MDP_WDMA0_EOF>; 1716 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1717 clocks = <&mmsys CLK_MM_MDP_WDMA0>; 1718 iommus = <&iommu M4U_PORT_MDP_WDMA0>; 1719 }; 1720 1721 ovl0: ovl@14008000 { 1722 compatible = "mediatek,mt8183-disp-ovl"; 1723 reg = <0 0x14008000 0 0x1000>; 1724 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1725 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1726 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1727 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1728 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1729 }; 1730 1731 ovl_2l0: ovl@14009000 { 1732 compatible = "mediatek,mt8183-disp-ovl-2l"; 1733 reg = <0 0x14009000 0 0x1000>; 1734 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1735 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1736 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1737 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1738 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1739 }; 1740 1741 ovl_2l1: ovl@1400a000 { 1742 compatible = "mediatek,mt8183-disp-ovl-2l"; 1743 reg = <0 0x1400a000 0 0x1000>; 1744 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1745 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1746 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1747 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1748 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1749 }; 1750 1751 rdma0: rdma@1400b000 { 1752 compatible = "mediatek,mt8183-disp-rdma"; 1753 reg = <0 0x1400b000 0 0x1000>; 1754 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1755 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1756 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1757 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1758 mediatek,rdma-fifo-size = <5120>; 1759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1760 }; 1761 1762 rdma1: rdma@1400c000 { 1763 compatible = "mediatek,mt8183-disp-rdma"; 1764 reg = <0 0x1400c000 0 0x1000>; 1765 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1766 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1767 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1768 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1769 mediatek,rdma-fifo-size = <2048>; 1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1771 }; 1772 1773 color0: color@1400e000 { 1774 compatible = "mediatek,mt8183-disp-color", 1775 "mediatek,mt8173-disp-color"; 1776 reg = <0 0x1400e000 0 0x1000>; 1777 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1778 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1779 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1781 }; 1782 1783 ccorr0: ccorr@1400f000 { 1784 compatible = "mediatek,mt8183-disp-ccorr"; 1785 reg = <0 0x1400f000 0 0x1000>; 1786 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1787 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1788 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1789 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1790 }; 1791 1792 aal0: aal@14010000 { 1793 compatible = "mediatek,mt8183-disp-aal"; 1794 reg = <0 0x14010000 0 0x1000>; 1795 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1796 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1797 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1798 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1799 }; 1800 1801 gamma0: gamma@14011000 { 1802 compatible = "mediatek,mt8183-disp-gamma"; 1803 reg = <0 0x14011000 0 0x1000>; 1804 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1805 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1806 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1807 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1808 }; 1809 1810 dither0: dither@14012000 { 1811 compatible = "mediatek,mt8183-disp-dither"; 1812 reg = <0 0x14012000 0 0x1000>; 1813 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1814 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1815 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1816 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1817 }; 1818 1819 dsi0: dsi@14014000 { 1820 compatible = "mediatek,mt8183-dsi"; 1821 reg = <0 0x14014000 0 0x1000>; 1822 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1823 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1824 clocks = <&mmsys CLK_MM_DSI0_MM>, 1825 <&mmsys CLK_MM_DSI0_IF>, 1826 <&mipi_tx0>; 1827 clock-names = "engine", "digital", "hs"; 1828 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1829 phys = <&mipi_tx0>; 1830 phy-names = "dphy"; 1831 status = "disabled"; 1832 }; 1833 1834 mutex: mutex@14016000 { 1835 compatible = "mediatek,mt8183-disp-mutex"; 1836 reg = <0 0x14016000 0 0x1000>; 1837 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1838 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1839 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1840 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1841 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1842 }; 1843 1844 larb0: larb@14017000 { 1845 compatible = "mediatek,mt8183-smi-larb"; 1846 reg = <0 0x14017000 0 0x1000>; 1847 mediatek,smi = <&smi_common>; 1848 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1849 <&mmsys CLK_MM_SMI_LARB0>; 1850 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1851 clock-names = "apb", "smi"; 1852 }; 1853 1854 smi_common: smi@14019000 { 1855 compatible = "mediatek,mt8183-smi-common"; 1856 reg = <0 0x14019000 0 0x1000>; 1857 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1858 <&mmsys CLK_MM_SMI_COMMON>, 1859 <&mmsys CLK_MM_GALS_COMM0>, 1860 <&mmsys CLK_MM_GALS_COMM1>; 1861 clock-names = "apb", "smi", "gals0", "gals1"; 1862 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1863 }; 1864 1865 mdp3-ccorr@1401c000 { 1866 compatible = "mediatek,mt8183-mdp3-ccorr"; 1867 reg = <0 0x1401c000 0 0x1000>; 1868 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; 1869 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, 1870 <CMDQ_EVENT_MDP_CCORR_EOF>; 1871 clocks = <&mmsys CLK_MM_MDP_CCORR>; 1872 }; 1873 1874 imgsys: syscon@15020000 { 1875 compatible = "mediatek,mt8183-imgsys", "syscon"; 1876 reg = <0 0x15020000 0 0x1000>; 1877 #clock-cells = <1>; 1878 }; 1879 1880 larb5: larb@15021000 { 1881 compatible = "mediatek,mt8183-smi-larb"; 1882 reg = <0 0x15021000 0 0x1000>; 1883 mediatek,smi = <&smi_common>; 1884 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1885 <&mmsys CLK_MM_GALS_IMG2MM>; 1886 clock-names = "apb", "smi", "gals"; 1887 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1888 }; 1889 1890 larb2: larb@1502f000 { 1891 compatible = "mediatek,mt8183-smi-larb"; 1892 reg = <0 0x1502f000 0 0x1000>; 1893 mediatek,smi = <&smi_common>; 1894 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1895 <&mmsys CLK_MM_GALS_IPU2MM>; 1896 clock-names = "apb", "smi", "gals"; 1897 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1898 }; 1899 1900 vdecsys: syscon@16000000 { 1901 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1902 reg = <0 0x16000000 0 0x1000>; 1903 #clock-cells = <1>; 1904 }; 1905 1906 larb1: larb@16010000 { 1907 compatible = "mediatek,mt8183-smi-larb"; 1908 reg = <0 0x16010000 0 0x1000>; 1909 mediatek,smi = <&smi_common>; 1910 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1911 clock-names = "apb", "smi"; 1912 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1913 }; 1914 1915 vencsys: syscon@17000000 { 1916 compatible = "mediatek,mt8183-vencsys", "syscon"; 1917 reg = <0 0x17000000 0 0x1000>; 1918 #clock-cells = <1>; 1919 }; 1920 1921 larb4: larb@17010000 { 1922 compatible = "mediatek,mt8183-smi-larb"; 1923 reg = <0 0x17010000 0 0x1000>; 1924 mediatek,smi = <&smi_common>; 1925 clocks = <&vencsys CLK_VENC_LARB>, 1926 <&vencsys CLK_VENC_LARB>; 1927 clock-names = "apb", "smi"; 1928 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1929 }; 1930 1931 venc_jpg: venc_jpg@17030000 { 1932 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 1933 reg = <0 0x17030000 0 0x1000>; 1934 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 1935 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 1936 <&iommu M4U_PORT_JPGENC_BSDMA>; 1937 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1938 clocks = <&vencsys CLK_VENC_JPGENC>; 1939 clock-names = "jpgenc"; 1940 }; 1941 1942 ipu_conn: syscon@19000000 { 1943 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1944 reg = <0 0x19000000 0 0x1000>; 1945 #clock-cells = <1>; 1946 }; 1947 1948 ipu_adl: syscon@19010000 { 1949 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1950 reg = <0 0x19010000 0 0x1000>; 1951 #clock-cells = <1>; 1952 }; 1953 1954 ipu_core0: syscon@19180000 { 1955 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1956 reg = <0 0x19180000 0 0x1000>; 1957 #clock-cells = <1>; 1958 }; 1959 1960 ipu_core1: syscon@19280000 { 1961 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1962 reg = <0 0x19280000 0 0x1000>; 1963 #clock-cells = <1>; 1964 }; 1965 1966 camsys: syscon@1a000000 { 1967 compatible = "mediatek,mt8183-camsys", "syscon"; 1968 reg = <0 0x1a000000 0 0x1000>; 1969 #clock-cells = <1>; 1970 }; 1971 1972 larb6: larb@1a001000 { 1973 compatible = "mediatek,mt8183-smi-larb"; 1974 reg = <0 0x1a001000 0 0x1000>; 1975 mediatek,smi = <&smi_common>; 1976 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1977 <&mmsys CLK_MM_GALS_CAM2MM>; 1978 clock-names = "apb", "smi", "gals"; 1979 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1980 }; 1981 1982 larb3: larb@1a002000 { 1983 compatible = "mediatek,mt8183-smi-larb"; 1984 reg = <0 0x1a002000 0 0x1000>; 1985 mediatek,smi = <&smi_common>; 1986 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1987 <&mmsys CLK_MM_GALS_IPU12MM>; 1988 clock-names = "apb", "smi", "gals"; 1989 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1990 }; 1991 }; 1992 1993 thermal_zones: thermal-zones { 1994 cpu_thermal: cpu-thermal { 1995 polling-delay-passive = <100>; 1996 polling-delay = <500>; 1997 thermal-sensors = <&thermal 0>; 1998 sustainable-power = <5000>; 1999 2000 trips { 2001 threshold: trip-point0 { 2002 temperature = <68000>; 2003 hysteresis = <2000>; 2004 type = "passive"; 2005 }; 2006 2007 target: trip-point1 { 2008 temperature = <80000>; 2009 hysteresis = <2000>; 2010 type = "passive"; 2011 }; 2012 2013 cpu_crit: cpu-crit { 2014 temperature = <115000>; 2015 hysteresis = <2000>; 2016 type = "critical"; 2017 }; 2018 }; 2019 2020 cooling-maps { 2021 map0 { 2022 trip = <&target>; 2023 cooling-device = <&cpu0 2024 THERMAL_NO_LIMIT 2025 THERMAL_NO_LIMIT>, 2026 <&cpu1 2027 THERMAL_NO_LIMIT 2028 THERMAL_NO_LIMIT>, 2029 <&cpu2 2030 THERMAL_NO_LIMIT 2031 THERMAL_NO_LIMIT>, 2032 <&cpu3 2033 THERMAL_NO_LIMIT 2034 THERMAL_NO_LIMIT>; 2035 contribution = <3072>; 2036 }; 2037 map1 { 2038 trip = <&target>; 2039 cooling-device = <&cpu4 2040 THERMAL_NO_LIMIT 2041 THERMAL_NO_LIMIT>, 2042 <&cpu5 2043 THERMAL_NO_LIMIT 2044 THERMAL_NO_LIMIT>, 2045 <&cpu6 2046 THERMAL_NO_LIMIT 2047 THERMAL_NO_LIMIT>, 2048 <&cpu7 2049 THERMAL_NO_LIMIT 2050 THERMAL_NO_LIMIT>; 2051 contribution = <1024>; 2052 }; 2053 }; 2054 }; 2055 2056 /* The tzts1 ~ tzts6 don't need to polling */ 2057 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 2058 2059 tzts1: tzts1 { 2060 polling-delay-passive = <0>; 2061 polling-delay = <0>; 2062 thermal-sensors = <&thermal 1>; 2063 sustainable-power = <5000>; 2064 trips {}; 2065 cooling-maps {}; 2066 }; 2067 2068 tzts2: tzts2 { 2069 polling-delay-passive = <0>; 2070 polling-delay = <0>; 2071 thermal-sensors = <&thermal 2>; 2072 sustainable-power = <5000>; 2073 trips {}; 2074 cooling-maps {}; 2075 }; 2076 2077 tzts3: tzts3 { 2078 polling-delay-passive = <0>; 2079 polling-delay = <0>; 2080 thermal-sensors = <&thermal 3>; 2081 sustainable-power = <5000>; 2082 trips {}; 2083 cooling-maps {}; 2084 }; 2085 2086 tzts4: tzts4 { 2087 polling-delay-passive = <0>; 2088 polling-delay = <0>; 2089 thermal-sensors = <&thermal 4>; 2090 sustainable-power = <5000>; 2091 trips {}; 2092 cooling-maps {}; 2093 }; 2094 2095 tzts5: tzts5 { 2096 polling-delay-passive = <0>; 2097 polling-delay = <0>; 2098 thermal-sensors = <&thermal 5>; 2099 sustainable-power = <5000>; 2100 trips {}; 2101 cooling-maps {}; 2102 }; 2103 2104 tztsABB: tztsABB { 2105 polling-delay-passive = <0>; 2106 polling-delay = <0>; 2107 thermal-sensors = <&thermal 6>; 2108 sustainable-power = <5000>; 2109 trips {}; 2110 cooling-maps {}; 2111 }; 2112 }; 2113}; 2114