1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * Thanks to the following companies for their support:
7 *
8 * - JMicron (hardware and technical support)
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/string.h>
13 #include <linux/delay.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/scatterlist.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/gpio.h>
24 #include <linux/gpio/machine.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/pm_qos.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <linux/dmi.h>
30
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #ifdef CONFIG_X86
36 #include <asm/iosf_mbi.h>
37 #endif
38
39 #include "cqhci.h"
40
41 #include "sdhci.h"
42 #include "sdhci-cqhci.h"
43 #include "sdhci-pci.h"
44
45 static void sdhci_pci_hw_reset(struct sdhci_host *host);
46
47 #ifdef CONFIG_PM_SLEEP
sdhci_pci_init_wakeup(struct sdhci_pci_chip * chip)48 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
49 {
50 mmc_pm_flag_t pm_flags = 0;
51 bool cap_cd_wake = false;
52 int i;
53
54 for (i = 0; i < chip->num_slots; i++) {
55 struct sdhci_pci_slot *slot = chip->slots[i];
56
57 if (slot) {
58 pm_flags |= slot->host->mmc->pm_flags;
59 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
60 cap_cd_wake = true;
61 }
62 }
63
64 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
65 return device_wakeup_enable(&chip->pdev->dev);
66 else if (!cap_cd_wake)
67 return device_wakeup_disable(&chip->pdev->dev);
68
69 return 0;
70 }
71
sdhci_pci_suspend_host(struct sdhci_pci_chip * chip)72 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
73 {
74 int i, ret;
75
76 sdhci_pci_init_wakeup(chip);
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80 struct sdhci_host *host;
81
82 if (!slot)
83 continue;
84
85 host = slot->host;
86
87 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
88 mmc_retune_needed(host->mmc);
89
90 ret = sdhci_suspend_host(host);
91 if (ret)
92 goto err_pci_suspend;
93
94 if (device_may_wakeup(&chip->pdev->dev))
95 mmc_gpio_set_cd_wake(host->mmc, true);
96 }
97
98 return 0;
99
100 err_pci_suspend:
101 while (--i >= 0)
102 sdhci_resume_host(chip->slots[i]->host);
103 return ret;
104 }
105
sdhci_pci_resume_host(struct sdhci_pci_chip * chip)106 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
107 {
108 struct sdhci_pci_slot *slot;
109 int i, ret;
110
111 for (i = 0; i < chip->num_slots; i++) {
112 slot = chip->slots[i];
113 if (!slot)
114 continue;
115
116 ret = sdhci_resume_host(slot->host);
117 if (ret)
118 return ret;
119
120 mmc_gpio_set_cd_wake(slot->host->mmc, false);
121 }
122
123 return 0;
124 }
125
sdhci_cqhci_suspend(struct sdhci_pci_chip * chip)126 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
127 {
128 int ret;
129
130 ret = cqhci_suspend(chip->slots[0]->host->mmc);
131 if (ret)
132 return ret;
133
134 return sdhci_pci_suspend_host(chip);
135 }
136
sdhci_cqhci_resume(struct sdhci_pci_chip * chip)137 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
138 {
139 int ret;
140
141 ret = sdhci_pci_resume_host(chip);
142 if (ret)
143 return ret;
144
145 return cqhci_resume(chip->slots[0]->host->mmc);
146 }
147 #endif
148
149 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip * chip)150 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
151 {
152 struct sdhci_pci_slot *slot;
153 struct sdhci_host *host;
154 int i, ret;
155
156 for (i = 0; i < chip->num_slots; i++) {
157 slot = chip->slots[i];
158 if (!slot)
159 continue;
160
161 host = slot->host;
162
163 ret = sdhci_runtime_suspend_host(host);
164 if (ret)
165 goto err_pci_runtime_suspend;
166
167 if (chip->rpm_retune &&
168 host->tuning_mode != SDHCI_TUNING_MODE_3)
169 mmc_retune_needed(host->mmc);
170 }
171
172 return 0;
173
174 err_pci_runtime_suspend:
175 while (--i >= 0)
176 sdhci_runtime_resume_host(chip->slots[i]->host, 0);
177 return ret;
178 }
179
sdhci_pci_runtime_resume_host(struct sdhci_pci_chip * chip)180 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
181 {
182 struct sdhci_pci_slot *slot;
183 int i, ret;
184
185 for (i = 0; i < chip->num_slots; i++) {
186 slot = chip->slots[i];
187 if (!slot)
188 continue;
189
190 ret = sdhci_runtime_resume_host(slot->host, 0);
191 if (ret)
192 return ret;
193 }
194
195 return 0;
196 }
197
sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip * chip)198 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
199 {
200 int ret;
201
202 ret = cqhci_suspend(chip->slots[0]->host->mmc);
203 if (ret)
204 return ret;
205
206 return sdhci_pci_runtime_suspend_host(chip);
207 }
208
sdhci_cqhci_runtime_resume(struct sdhci_pci_chip * chip)209 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
210 {
211 int ret;
212
213 ret = sdhci_pci_runtime_resume_host(chip);
214 if (ret)
215 return ret;
216
217 return cqhci_resume(chip->slots[0]->host->mmc);
218 }
219 #endif
220
sdhci_cqhci_irq(struct sdhci_host * host,u32 intmask)221 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
222 {
223 int cmd_error = 0;
224 int data_error = 0;
225
226 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
227 return intmask;
228
229 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
230
231 return 0;
232 }
233
sdhci_pci_dumpregs(struct mmc_host * mmc)234 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
235 {
236 sdhci_dumpregs(mmc_priv(mmc));
237 }
238
239 /*****************************************************************************\
240 * *
241 * Hardware specific quirk handling *
242 * *
243 \*****************************************************************************/
244
ricoh_probe(struct sdhci_pci_chip * chip)245 static int ricoh_probe(struct sdhci_pci_chip *chip)
246 {
247 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
248 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
249 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
250 return 0;
251 }
252
ricoh_mmc_probe_slot(struct sdhci_pci_slot * slot)253 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
254 {
255 u32 caps =
256 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) |
257 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) |
258 SDHCI_TIMEOUT_CLK_UNIT |
259 SDHCI_CAN_VDD_330 |
260 SDHCI_CAN_DO_HISPD |
261 SDHCI_CAN_DO_SDMA;
262 u32 caps1 = 0;
263
264 __sdhci_read_caps(slot->host, NULL, &caps, &caps1);
265 return 0;
266 }
267
268 #ifdef CONFIG_PM_SLEEP
ricoh_mmc_resume(struct sdhci_pci_chip * chip)269 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
270 {
271 /* Apply a delay to allow controller to settle */
272 /* Otherwise it becomes confused if card state changed
273 during suspend */
274 msleep(500);
275 return sdhci_pci_resume_host(chip);
276 }
277 #endif
278
279 static const struct sdhci_pci_fixes sdhci_ricoh = {
280 .probe = ricoh_probe,
281 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
282 SDHCI_QUIRK_FORCE_DMA |
283 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
284 };
285
286 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
287 .probe_slot = ricoh_mmc_probe_slot,
288 #ifdef CONFIG_PM_SLEEP
289 .resume = ricoh_mmc_resume,
290 #endif
291 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
292 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
293 SDHCI_QUIRK_NO_CARD_NO_RESET,
294 };
295
ene_714_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)296 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
297 {
298 struct sdhci_host *host = mmc_priv(mmc);
299
300 sdhci_set_ios(mmc, ios);
301
302 /*
303 * Some (ENE) controllers misbehave on some ios operations,
304 * signalling timeout and CRC errors even on CMD0. Resetting
305 * it on each ios seems to solve the problem.
306 */
307 if (!(host->flags & SDHCI_DEVICE_DEAD))
308 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
309 }
310
ene_714_probe_slot(struct sdhci_pci_slot * slot)311 static int ene_714_probe_slot(struct sdhci_pci_slot *slot)
312 {
313 slot->host->mmc_host_ops.set_ios = ene_714_set_ios;
314 return 0;
315 }
316
317 static const struct sdhci_pci_fixes sdhci_ene_712 = {
318 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
319 SDHCI_QUIRK_BROKEN_DMA,
320 };
321
322 static const struct sdhci_pci_fixes sdhci_ene_714 = {
323 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
324 SDHCI_QUIRK_BROKEN_DMA,
325 .probe_slot = ene_714_probe_slot,
326 };
327
328 static const struct sdhci_pci_fixes sdhci_cafe = {
329 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
330 SDHCI_QUIRK_NO_BUSY_IRQ |
331 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
332 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
333 };
334
335 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
336 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
337 };
338
mrst_hc_probe_slot(struct sdhci_pci_slot * slot)339 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
340 {
341 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
342 return 0;
343 }
344
345 /*
346 * ADMA operation is disabled for Moorestown platform due to
347 * hardware bugs.
348 */
mrst_hc_probe(struct sdhci_pci_chip * chip)349 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
350 {
351 /*
352 * slots number is fixed here for MRST as SDIO3/5 are never used and
353 * have hardware bugs.
354 */
355 chip->num_slots = 1;
356 return 0;
357 }
358
pch_hc_probe_slot(struct sdhci_pci_slot * slot)359 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
360 {
361 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
362 return 0;
363 }
364
mfd_emmc_probe_slot(struct sdhci_pci_slot * slot)365 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
366 {
367 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
368 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
369 return 0;
370 }
371
mfd_sdio_probe_slot(struct sdhci_pci_slot * slot)372 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
373 {
374 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
375 return 0;
376 }
377
378 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
379 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
380 .probe_slot = mrst_hc_probe_slot,
381 };
382
383 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
384 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
385 .probe = mrst_hc_probe,
386 };
387
388 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
389 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 };
393
394 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
396 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
397 .allow_runtime_pm = true,
398 .probe_slot = mfd_sdio_probe_slot,
399 };
400
401 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
403 .allow_runtime_pm = true,
404 .probe_slot = mfd_emmc_probe_slot,
405 };
406
407 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
408 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
409 .probe_slot = pch_hc_probe_slot,
410 };
411
412 #ifdef CONFIG_X86
413
414 #define BYT_IOSF_SCCEP 0x63
415 #define BYT_IOSF_OCP_NETCTRL0 0x1078
416 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
417
byt_ocp_setting(struct pci_dev * pdev)418 static void byt_ocp_setting(struct pci_dev *pdev)
419 {
420 u32 val = 0;
421
422 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
423 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
424 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
425 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
426 return;
427
428 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
429 &val)) {
430 dev_err(&pdev->dev, "%s read error\n", __func__);
431 return;
432 }
433
434 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
435 return;
436
437 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
438
439 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
440 val)) {
441 dev_err(&pdev->dev, "%s write error\n", __func__);
442 return;
443 }
444
445 dev_dbg(&pdev->dev, "%s completed\n", __func__);
446 }
447
448 #else
449
byt_ocp_setting(struct pci_dev * pdev)450 static inline void byt_ocp_setting(struct pci_dev *pdev)
451 {
452 }
453
454 #endif
455
456 enum {
457 INTEL_DSM_FNS = 0,
458 INTEL_DSM_V18_SWITCH = 3,
459 INTEL_DSM_V33_SWITCH = 4,
460 INTEL_DSM_DRV_STRENGTH = 9,
461 INTEL_DSM_D3_RETUNE = 10,
462 };
463
464 struct intel_host {
465 u32 dsm_fns;
466 int drv_strength;
467 bool d3_retune;
468 bool rpm_retune_ok;
469 bool needs_pwr_off;
470 u32 glk_rx_ctrl1;
471 u32 glk_tun_val;
472 u32 active_ltr;
473 u32 idle_ltr;
474 };
475
476 static const guid_t intel_dsm_guid =
477 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
478 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
479
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)480 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
481 unsigned int fn, u32 *result)
482 {
483 union acpi_object *obj;
484 int err = 0;
485 size_t len;
486
487 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
488 if (!obj)
489 return -EOPNOTSUPP;
490
491 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
492 err = -EINVAL;
493 goto out;
494 }
495
496 len = min_t(size_t, obj->buffer.length, 4);
497
498 *result = 0;
499 memcpy(result, obj->buffer.pointer, len);
500 out:
501 ACPI_FREE(obj);
502
503 return err;
504 }
505
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)506 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
507 unsigned int fn, u32 *result)
508 {
509 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
510 return -EOPNOTSUPP;
511
512 return __intel_dsm(intel_host, dev, fn, result);
513 }
514
intel_dsm_init(struct intel_host * intel_host,struct device * dev,struct mmc_host * mmc)515 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
516 struct mmc_host *mmc)
517 {
518 int err;
519 u32 val;
520
521 intel_host->d3_retune = true;
522
523 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
524 if (err) {
525 pr_debug("%s: DSM not supported, error %d\n",
526 mmc_hostname(mmc), err);
527 return;
528 }
529
530 pr_debug("%s: DSM function mask %#x\n",
531 mmc_hostname(mmc), intel_host->dsm_fns);
532
533 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
534 intel_host->drv_strength = err ? 0 : val;
535
536 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
537 intel_host->d3_retune = err ? true : !!val;
538 }
539
sdhci_pci_int_hw_reset(struct sdhci_host * host)540 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
541 {
542 u8 reg;
543
544 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
545 reg |= 0x10;
546 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
547 /* For eMMC, minimum is 1us but give it 9us for good measure */
548 udelay(9);
549 reg &= ~0x10;
550 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
551 /* For eMMC, minimum is 200us but give it 300us for good measure */
552 usleep_range(300, 1000);
553 }
554
intel_select_drive_strength(struct mmc_card * card,unsigned int max_dtr,int host_drv,int card_drv,int * drv_type)555 static int intel_select_drive_strength(struct mmc_card *card,
556 unsigned int max_dtr, int host_drv,
557 int card_drv, int *drv_type)
558 {
559 struct sdhci_host *host = mmc_priv(card->host);
560 struct sdhci_pci_slot *slot = sdhci_priv(host);
561 struct intel_host *intel_host = sdhci_pci_priv(slot);
562
563 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
564 return 0;
565
566 return intel_host->drv_strength;
567 }
568
bxt_get_cd(struct mmc_host * mmc)569 static int bxt_get_cd(struct mmc_host *mmc)
570 {
571 int gpio_cd = mmc_gpio_get_cd(mmc);
572
573 if (!gpio_cd)
574 return 0;
575
576 return sdhci_get_cd_nogpio(mmc);
577 }
578
mrfld_get_cd(struct mmc_host * mmc)579 static int mrfld_get_cd(struct mmc_host *mmc)
580 {
581 return sdhci_get_cd_nogpio(mmc);
582 }
583
584 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
585 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
586
sdhci_intel_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)587 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
588 unsigned short vdd)
589 {
590 struct sdhci_pci_slot *slot = sdhci_priv(host);
591 struct intel_host *intel_host = sdhci_pci_priv(slot);
592 int cntr;
593 u8 reg;
594
595 /*
596 * Bus power may control card power, but a full reset still may not
597 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can.
598 * That might be needed to initialize correctly, if the card was left
599 * powered on previously.
600 */
601 if (intel_host->needs_pwr_off) {
602 intel_host->needs_pwr_off = false;
603 if (mode != MMC_POWER_OFF) {
604 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
605 usleep_range(10000, 12500);
606 }
607 }
608
609 sdhci_set_power(host, mode, vdd);
610
611 if (mode == MMC_POWER_OFF)
612 return;
613
614 /*
615 * Bus power might not enable after D3 -> D0 transition due to the
616 * present state not yet having propagated. Retry for up to 2ms.
617 */
618 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
619 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
620 if (reg & SDHCI_POWER_ON)
621 break;
622 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
623 reg |= SDHCI_POWER_ON;
624 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
625 }
626 }
627
sdhci_intel_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)628 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
629 unsigned int timing)
630 {
631 /* Set UHS timing to SDR25 for High Speed mode */
632 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
633 timing = MMC_TIMING_UHS_SDR25;
634 sdhci_set_uhs_signaling(host, timing);
635 }
636
637 #define INTEL_HS400_ES_REG 0x78
638 #define INTEL_HS400_ES_BIT BIT(0)
639
intel_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)640 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
641 struct mmc_ios *ios)
642 {
643 struct sdhci_host *host = mmc_priv(mmc);
644 u32 val;
645
646 val = sdhci_readl(host, INTEL_HS400_ES_REG);
647 if (ios->enhanced_strobe)
648 val |= INTEL_HS400_ES_BIT;
649 else
650 val &= ~INTEL_HS400_ES_BIT;
651 sdhci_writel(host, val, INTEL_HS400_ES_REG);
652 }
653
intel_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)654 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
655 struct mmc_ios *ios)
656 {
657 struct device *dev = mmc_dev(mmc);
658 struct sdhci_host *host = mmc_priv(mmc);
659 struct sdhci_pci_slot *slot = sdhci_priv(host);
660 struct intel_host *intel_host = sdhci_pci_priv(slot);
661 unsigned int fn;
662 u32 result = 0;
663 int err;
664
665 err = sdhci_start_signal_voltage_switch(mmc, ios);
666 if (err)
667 return err;
668
669 switch (ios->signal_voltage) {
670 case MMC_SIGNAL_VOLTAGE_330:
671 fn = INTEL_DSM_V33_SWITCH;
672 break;
673 case MMC_SIGNAL_VOLTAGE_180:
674 fn = INTEL_DSM_V18_SWITCH;
675 break;
676 default:
677 return 0;
678 }
679
680 err = intel_dsm(intel_host, dev, fn, &result);
681 pr_debug("%s: %s DSM fn %u error %d result %u\n",
682 mmc_hostname(mmc), __func__, fn, err, result);
683
684 return 0;
685 }
686
687 static const struct sdhci_ops sdhci_intel_byt_ops = {
688 .set_clock = sdhci_set_clock,
689 .set_power = sdhci_intel_set_power,
690 .enable_dma = sdhci_pci_enable_dma,
691 .set_bus_width = sdhci_set_bus_width,
692 .reset = sdhci_reset,
693 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
694 .hw_reset = sdhci_pci_hw_reset,
695 };
696
697 static const struct sdhci_ops sdhci_intel_glk_ops = {
698 .set_clock = sdhci_set_clock,
699 .set_power = sdhci_intel_set_power,
700 .enable_dma = sdhci_pci_enable_dma,
701 .set_bus_width = sdhci_set_bus_width,
702 .reset = sdhci_and_cqhci_reset,
703 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
704 .hw_reset = sdhci_pci_hw_reset,
705 .irq = sdhci_cqhci_irq,
706 };
707
byt_read_dsm(struct sdhci_pci_slot * slot)708 static void byt_read_dsm(struct sdhci_pci_slot *slot)
709 {
710 struct intel_host *intel_host = sdhci_pci_priv(slot);
711 struct device *dev = &slot->chip->pdev->dev;
712 struct mmc_host *mmc = slot->host->mmc;
713
714 intel_dsm_init(intel_host, dev, mmc);
715 slot->chip->rpm_retune = intel_host->d3_retune;
716 }
717
intel_execute_tuning(struct mmc_host * mmc,u32 opcode)718 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
719 {
720 int err = sdhci_execute_tuning(mmc, opcode);
721 struct sdhci_host *host = mmc_priv(mmc);
722
723 if (err)
724 return err;
725
726 /*
727 * Tuning can leave the IP in an active state (Buffer Read Enable bit
728 * set) which prevents the entry to low power states (i.e. S0i3). Data
729 * reset will clear it.
730 */
731 sdhci_reset(host, SDHCI_RESET_DATA);
732
733 return 0;
734 }
735
736 #define INTEL_ACTIVELTR 0x804
737 #define INTEL_IDLELTR 0x808
738
739 #define INTEL_LTR_REQ BIT(15)
740 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
741 #define INTEL_LTR_SCALE_1US (2 << 10)
742 #define INTEL_LTR_SCALE_32US (3 << 10)
743 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
744
intel_cache_ltr(struct sdhci_pci_slot * slot)745 static void intel_cache_ltr(struct sdhci_pci_slot *slot)
746 {
747 struct intel_host *intel_host = sdhci_pci_priv(slot);
748 struct sdhci_host *host = slot->host;
749
750 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
751 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR);
752 }
753
intel_ltr_set(struct device * dev,s32 val)754 static void intel_ltr_set(struct device *dev, s32 val)
755 {
756 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
757 struct sdhci_pci_slot *slot = chip->slots[0];
758 struct intel_host *intel_host = sdhci_pci_priv(slot);
759 struct sdhci_host *host = slot->host;
760 u32 ltr;
761
762 pm_runtime_get_sync(dev);
763
764 /*
765 * Program latency tolerance (LTR) accordingly what has been asked
766 * by the PM QoS layer or disable it in case we were passed
767 * negative value or PM_QOS_LATENCY_ANY.
768 */
769 ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
770
771 if (val == PM_QOS_LATENCY_ANY || val < 0) {
772 ltr &= ~INTEL_LTR_REQ;
773 } else {
774 ltr |= INTEL_LTR_REQ;
775 ltr &= ~INTEL_LTR_SCALE_MASK;
776 ltr &= ~INTEL_LTR_VALUE_MASK;
777
778 if (val > INTEL_LTR_VALUE_MASK) {
779 val >>= 5;
780 if (val > INTEL_LTR_VALUE_MASK)
781 val = INTEL_LTR_VALUE_MASK;
782 ltr |= INTEL_LTR_SCALE_32US | val;
783 } else {
784 ltr |= INTEL_LTR_SCALE_1US | val;
785 }
786 }
787
788 if (ltr == intel_host->active_ltr)
789 goto out;
790
791 writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
792 writel(ltr, host->ioaddr + INTEL_IDLELTR);
793
794 /* Cache the values into lpss structure */
795 intel_cache_ltr(slot);
796 out:
797 pm_runtime_put_autosuspend(dev);
798 }
799
intel_use_ltr(struct sdhci_pci_chip * chip)800 static bool intel_use_ltr(struct sdhci_pci_chip *chip)
801 {
802 switch (chip->pdev->device) {
803 case PCI_DEVICE_ID_INTEL_BYT_EMMC:
804 case PCI_DEVICE_ID_INTEL_BYT_EMMC2:
805 case PCI_DEVICE_ID_INTEL_BYT_SDIO:
806 case PCI_DEVICE_ID_INTEL_BYT_SD:
807 case PCI_DEVICE_ID_INTEL_BSW_EMMC:
808 case PCI_DEVICE_ID_INTEL_BSW_SDIO:
809 case PCI_DEVICE_ID_INTEL_BSW_SD:
810 return false;
811 default:
812 return true;
813 }
814 }
815
intel_ltr_expose(struct sdhci_pci_chip * chip)816 static void intel_ltr_expose(struct sdhci_pci_chip *chip)
817 {
818 struct device *dev = &chip->pdev->dev;
819
820 if (!intel_use_ltr(chip))
821 return;
822
823 dev->power.set_latency_tolerance = intel_ltr_set;
824 dev_pm_qos_expose_latency_tolerance(dev);
825 }
826
intel_ltr_hide(struct sdhci_pci_chip * chip)827 static void intel_ltr_hide(struct sdhci_pci_chip *chip)
828 {
829 struct device *dev = &chip->pdev->dev;
830
831 if (!intel_use_ltr(chip))
832 return;
833
834 dev_pm_qos_hide_latency_tolerance(dev);
835 dev->power.set_latency_tolerance = NULL;
836 }
837
byt_probe_slot(struct sdhci_pci_slot * slot)838 static void byt_probe_slot(struct sdhci_pci_slot *slot)
839 {
840 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
841 struct device *dev = &slot->chip->pdev->dev;
842 struct mmc_host *mmc = slot->host->mmc;
843
844 byt_read_dsm(slot);
845
846 byt_ocp_setting(slot->chip->pdev);
847
848 ops->execute_tuning = intel_execute_tuning;
849 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
850
851 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
852
853 if (!mmc->slotno) {
854 slot->chip->slots[mmc->slotno] = slot;
855 intel_ltr_expose(slot->chip);
856 }
857 }
858
byt_add_debugfs(struct sdhci_pci_slot * slot)859 static void byt_add_debugfs(struct sdhci_pci_slot *slot)
860 {
861 struct intel_host *intel_host = sdhci_pci_priv(slot);
862 struct mmc_host *mmc = slot->host->mmc;
863 struct dentry *dir = mmc->debugfs_root;
864
865 if (!intel_use_ltr(slot->chip))
866 return;
867
868 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr);
869 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr);
870
871 intel_cache_ltr(slot);
872 }
873
byt_add_host(struct sdhci_pci_slot * slot)874 static int byt_add_host(struct sdhci_pci_slot *slot)
875 {
876 int ret = sdhci_add_host(slot->host);
877
878 if (!ret)
879 byt_add_debugfs(slot);
880 return ret;
881 }
882
byt_remove_slot(struct sdhci_pci_slot * slot,int dead)883 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead)
884 {
885 struct mmc_host *mmc = slot->host->mmc;
886
887 if (!mmc->slotno)
888 intel_ltr_hide(slot->chip);
889 }
890
byt_emmc_probe_slot(struct sdhci_pci_slot * slot)891 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
892 {
893 byt_probe_slot(slot);
894 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
895 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
896 MMC_CAP_CMD_DURING_TFR |
897 MMC_CAP_WAIT_WHILE_BUSY;
898 slot->hw_reset = sdhci_pci_int_hw_reset;
899 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
900 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
901 slot->host->mmc_host_ops.select_drive_strength =
902 intel_select_drive_strength;
903 return 0;
904 }
905
glk_broken_cqhci(struct sdhci_pci_slot * slot)906 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
907 {
908 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
909 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
910 dmi_match(DMI_SYS_VENDOR, "IRBIS"));
911 }
912
jsl_broken_hs400es(struct sdhci_pci_slot * slot)913 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot)
914 {
915 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC &&
916 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC.");
917 }
918
glk_emmc_probe_slot(struct sdhci_pci_slot * slot)919 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
920 {
921 int ret = byt_emmc_probe_slot(slot);
922
923 if (!glk_broken_cqhci(slot))
924 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
925
926 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
927 if (!jsl_broken_hs400es(slot)) {
928 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
929 slot->host->mmc_host_ops.hs400_enhanced_strobe =
930 intel_hs400_enhanced_strobe;
931 }
932 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
933 }
934
935 return ret;
936 }
937
938 static const struct cqhci_host_ops glk_cqhci_ops = {
939 .enable = sdhci_cqe_enable,
940 .disable = sdhci_cqe_disable,
941 .dumpregs = sdhci_pci_dumpregs,
942 };
943
glk_emmc_add_host(struct sdhci_pci_slot * slot)944 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
945 {
946 struct device *dev = &slot->chip->pdev->dev;
947 struct sdhci_host *host = slot->host;
948 struct cqhci_host *cq_host;
949 bool dma64;
950 int ret;
951
952 ret = sdhci_setup_host(host);
953 if (ret)
954 return ret;
955
956 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
957 if (!cq_host) {
958 ret = -ENOMEM;
959 goto cleanup;
960 }
961
962 cq_host->mmio = host->ioaddr + 0x200;
963 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
964 cq_host->ops = &glk_cqhci_ops;
965
966 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
967 if (dma64)
968 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
969
970 ret = cqhci_init(cq_host, host->mmc, dma64);
971 if (ret)
972 goto cleanup;
973
974 ret = __sdhci_add_host(host);
975 if (ret)
976 goto cleanup;
977
978 byt_add_debugfs(slot);
979
980 return 0;
981
982 cleanup:
983 sdhci_cleanup_host(host);
984 return ret;
985 }
986
987 #ifdef CONFIG_PM
988 #define GLK_RX_CTRL1 0x834
989 #define GLK_TUN_VAL 0x840
990 #define GLK_PATH_PLL GENMASK(13, 8)
991 #define GLK_DLY GENMASK(6, 0)
992 /* Workaround firmware failing to restore the tuning value */
glk_rpm_retune_wa(struct sdhci_pci_chip * chip,bool susp)993 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
994 {
995 struct sdhci_pci_slot *slot = chip->slots[0];
996 struct intel_host *intel_host = sdhci_pci_priv(slot);
997 struct sdhci_host *host = slot->host;
998 u32 glk_rx_ctrl1;
999 u32 glk_tun_val;
1000 u32 dly;
1001
1002 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
1003 return;
1004
1005 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
1006 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
1007
1008 if (susp) {
1009 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
1010 intel_host->glk_tun_val = glk_tun_val;
1011 return;
1012 }
1013
1014 if (!intel_host->glk_tun_val)
1015 return;
1016
1017 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
1018 intel_host->rpm_retune_ok = true;
1019 return;
1020 }
1021
1022 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
1023 (intel_host->glk_tun_val << 1));
1024 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
1025 return;
1026
1027 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
1028 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
1029
1030 intel_host->rpm_retune_ok = true;
1031 chip->rpm_retune = true;
1032 mmc_retune_needed(host->mmc);
1033 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
1034 }
1035
glk_rpm_retune_chk(struct sdhci_pci_chip * chip,bool susp)1036 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
1037 {
1038 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
1039 !chip->rpm_retune)
1040 glk_rpm_retune_wa(chip, susp);
1041 }
1042
glk_runtime_suspend(struct sdhci_pci_chip * chip)1043 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
1044 {
1045 glk_rpm_retune_chk(chip, true);
1046
1047 return sdhci_cqhci_runtime_suspend(chip);
1048 }
1049
glk_runtime_resume(struct sdhci_pci_chip * chip)1050 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
1051 {
1052 glk_rpm_retune_chk(chip, false);
1053
1054 return sdhci_cqhci_runtime_resume(chip);
1055 }
1056 #endif
1057
1058 #ifdef CONFIG_ACPI
ni_set_max_freq(struct sdhci_pci_slot * slot)1059 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
1060 {
1061 acpi_status status;
1062 unsigned long long max_freq;
1063
1064 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
1065 "MXFQ", NULL, &max_freq);
1066 if (ACPI_FAILURE(status)) {
1067 dev_err(&slot->chip->pdev->dev,
1068 "MXFQ not found in acpi table\n");
1069 return -EINVAL;
1070 }
1071
1072 slot->host->mmc->f_max = max_freq * 1000000;
1073
1074 return 0;
1075 }
1076 #else
ni_set_max_freq(struct sdhci_pci_slot * slot)1077 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
1078 {
1079 return 0;
1080 }
1081 #endif
1082
ni_byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1083 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1084 {
1085 int err;
1086
1087 byt_probe_slot(slot);
1088
1089 err = ni_set_max_freq(slot);
1090 if (err)
1091 return err;
1092
1093 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1094 MMC_CAP_WAIT_WHILE_BUSY;
1095 return 0;
1096 }
1097
byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1098 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1099 {
1100 byt_probe_slot(slot);
1101 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1102 MMC_CAP_WAIT_WHILE_BUSY;
1103 return 0;
1104 }
1105
byt_needs_pwr_off(struct sdhci_pci_slot * slot)1106 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot)
1107 {
1108 struct intel_host *intel_host = sdhci_pci_priv(slot);
1109 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL);
1110
1111 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON;
1112 }
1113
byt_sd_probe_slot(struct sdhci_pci_slot * slot)1114 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
1115 {
1116 byt_probe_slot(slot);
1117 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
1118 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
1119 slot->cd_idx = 0;
1120 slot->cd_override_level = true;
1121 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
1122 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
1123 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
1124 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
1125 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
1126
1127 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
1128 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
1129 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
1130
1131 byt_needs_pwr_off(slot);
1132
1133 return 0;
1134 }
1135
1136 #ifdef CONFIG_PM_SLEEP
1137
byt_resume(struct sdhci_pci_chip * chip)1138 static int byt_resume(struct sdhci_pci_chip *chip)
1139 {
1140 byt_ocp_setting(chip->pdev);
1141
1142 return sdhci_pci_resume_host(chip);
1143 }
1144
1145 #endif
1146
1147 #ifdef CONFIG_PM
1148
byt_runtime_resume(struct sdhci_pci_chip * chip)1149 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1150 {
1151 byt_ocp_setting(chip->pdev);
1152
1153 return sdhci_pci_runtime_resume_host(chip);
1154 }
1155
1156 #endif
1157
1158 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1159 #ifdef CONFIG_PM_SLEEP
1160 .resume = byt_resume,
1161 #endif
1162 #ifdef CONFIG_PM
1163 .runtime_resume = byt_runtime_resume,
1164 #endif
1165 .allow_runtime_pm = true,
1166 .probe_slot = byt_emmc_probe_slot,
1167 .add_host = byt_add_host,
1168 .remove_slot = byt_remove_slot,
1169 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1170 SDHCI_QUIRK_NO_LED,
1171 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1172 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1173 SDHCI_QUIRK2_STOP_WITH_TC,
1174 .ops = &sdhci_intel_byt_ops,
1175 .priv_size = sizeof(struct intel_host),
1176 };
1177
1178 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1179 .allow_runtime_pm = true,
1180 .probe_slot = glk_emmc_probe_slot,
1181 .add_host = glk_emmc_add_host,
1182 .remove_slot = byt_remove_slot,
1183 #ifdef CONFIG_PM_SLEEP
1184 .suspend = sdhci_cqhci_suspend,
1185 .resume = sdhci_cqhci_resume,
1186 #endif
1187 #ifdef CONFIG_PM
1188 .runtime_suspend = glk_runtime_suspend,
1189 .runtime_resume = glk_runtime_resume,
1190 #endif
1191 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1192 SDHCI_QUIRK_NO_LED,
1193 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1194 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1195 SDHCI_QUIRK2_STOP_WITH_TC,
1196 .ops = &sdhci_intel_glk_ops,
1197 .priv_size = sizeof(struct intel_host),
1198 };
1199
1200 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1201 #ifdef CONFIG_PM_SLEEP
1202 .resume = byt_resume,
1203 #endif
1204 #ifdef CONFIG_PM
1205 .runtime_resume = byt_runtime_resume,
1206 #endif
1207 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1208 SDHCI_QUIRK_NO_LED,
1209 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1210 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1211 .allow_runtime_pm = true,
1212 .probe_slot = ni_byt_sdio_probe_slot,
1213 .add_host = byt_add_host,
1214 .remove_slot = byt_remove_slot,
1215 .ops = &sdhci_intel_byt_ops,
1216 .priv_size = sizeof(struct intel_host),
1217 };
1218
1219 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1220 #ifdef CONFIG_PM_SLEEP
1221 .resume = byt_resume,
1222 #endif
1223 #ifdef CONFIG_PM
1224 .runtime_resume = byt_runtime_resume,
1225 #endif
1226 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1227 SDHCI_QUIRK_NO_LED,
1228 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1229 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1230 .allow_runtime_pm = true,
1231 .probe_slot = byt_sdio_probe_slot,
1232 .add_host = byt_add_host,
1233 .remove_slot = byt_remove_slot,
1234 .ops = &sdhci_intel_byt_ops,
1235 .priv_size = sizeof(struct intel_host),
1236 };
1237
1238 /* DMI quirks for devices with missing or broken CD GPIO info */
1239 static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = {
1240 .dev_id = "0000:00:12.0",
1241 .table = {
1242 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH),
1243 { }
1244 },
1245 };
1246
1247 static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = {
1248 {
1249 /* Vexia Edu Atla 10 tablet 9V version */
1250 .matches = {
1251 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
1252 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
1253 /* Above strings are too generic, also match on BIOS date */
1254 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"),
1255 },
1256 .driver_data = (void *)&vexia_edu_atla10_cd_gpios,
1257 },
1258 { }
1259 };
1260
1261 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1262 #ifdef CONFIG_PM_SLEEP
1263 .resume = byt_resume,
1264 #endif
1265 #ifdef CONFIG_PM
1266 .runtime_resume = byt_runtime_resume,
1267 #endif
1268 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1269 SDHCI_QUIRK_NO_LED,
1270 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1271 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1272 SDHCI_QUIRK2_STOP_WITH_TC,
1273 .allow_runtime_pm = true,
1274 .own_cd_for_runtime_pm = true,
1275 .probe_slot = byt_sd_probe_slot,
1276 .add_host = byt_add_host,
1277 .remove_slot = byt_remove_slot,
1278 .ops = &sdhci_intel_byt_ops,
1279 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override,
1280 .priv_size = sizeof(struct intel_host),
1281 };
1282
1283 /* Define Host controllers for Intel Merrifield platform */
1284 #define INTEL_MRFLD_EMMC_0 0
1285 #define INTEL_MRFLD_EMMC_1 1
1286 #define INTEL_MRFLD_SD 2
1287 #define INTEL_MRFLD_SDIO 3
1288
1289 #ifdef CONFIG_ACPI
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1290 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1291 {
1292 struct acpi_device *device;
1293
1294 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1295 if (device)
1296 acpi_device_fix_up_power_extended(device);
1297 }
1298 #else
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1299 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1300 #endif
1301
intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot * slot)1302 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1303 {
1304 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1305
1306 switch (func) {
1307 case INTEL_MRFLD_EMMC_0:
1308 case INTEL_MRFLD_EMMC_1:
1309 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1310 MMC_CAP_8_BIT_DATA |
1311 MMC_CAP_1_8V_DDR;
1312 break;
1313 case INTEL_MRFLD_SD:
1314 slot->cd_idx = 0;
1315 slot->cd_override_level = true;
1316 /*
1317 * There are two PCB designs of SD card slot with the opposite
1318 * card detection sense. Quirk this out by ignoring GPIO state
1319 * completely in the custom ->get_cd() callback.
1320 */
1321 slot->host->mmc_host_ops.get_cd = mrfld_get_cd;
1322 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1323 break;
1324 case INTEL_MRFLD_SDIO:
1325 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1326 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1327 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1328 MMC_CAP_POWER_OFF_CARD;
1329 break;
1330 default:
1331 return -ENODEV;
1332 }
1333
1334 intel_mrfld_mmc_fix_up_power_slot(slot);
1335 return 0;
1336 }
1337
1338 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1339 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1340 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1341 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1342 .allow_runtime_pm = true,
1343 .probe_slot = intel_mrfld_mmc_probe_slot,
1344 };
1345
jmicron_pmos(struct sdhci_pci_chip * chip,int on)1346 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1347 {
1348 u8 scratch;
1349 int ret;
1350
1351 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1352 if (ret)
1353 goto fail;
1354
1355 /*
1356 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1357 * [bit 1:2] and enable over current debouncing [bit 6].
1358 */
1359 if (on)
1360 scratch |= 0x47;
1361 else
1362 scratch &= ~0x47;
1363
1364 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
1365
1366 fail:
1367 return pcibios_err_to_errno(ret);
1368 }
1369
jmicron_probe(struct sdhci_pci_chip * chip)1370 static int jmicron_probe(struct sdhci_pci_chip *chip)
1371 {
1372 int ret;
1373 u16 mmcdev = 0;
1374
1375 if (chip->pdev->revision == 0) {
1376 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1377 SDHCI_QUIRK_32BIT_DMA_SIZE |
1378 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1379 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1380 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1381 }
1382
1383 /*
1384 * JMicron chips can have two interfaces to the same hardware
1385 * in order to work around limitations in Microsoft's driver.
1386 * We need to make sure we only bind to one of them.
1387 *
1388 * This code assumes two things:
1389 *
1390 * 1. The PCI code adds subfunctions in order.
1391 *
1392 * 2. The MMC interface has a lower subfunction number
1393 * than the SD interface.
1394 */
1395 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1396 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1397 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1398 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1399
1400 if (mmcdev) {
1401 struct pci_dev *sd_dev;
1402
1403 sd_dev = NULL;
1404 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1405 mmcdev, sd_dev)) != NULL) {
1406 if ((PCI_SLOT(chip->pdev->devfn) ==
1407 PCI_SLOT(sd_dev->devfn)) &&
1408 (chip->pdev->bus == sd_dev->bus))
1409 break;
1410 }
1411
1412 if (sd_dev) {
1413 pci_dev_put(sd_dev);
1414 dev_info(&chip->pdev->dev, "Refusing to bind to "
1415 "secondary interface.\n");
1416 return -ENODEV;
1417 }
1418 }
1419
1420 /*
1421 * JMicron chips need a bit of a nudge to enable the power
1422 * output pins.
1423 */
1424 ret = jmicron_pmos(chip, 1);
1425 if (ret) {
1426 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1427 return ret;
1428 }
1429
1430 /* quirk for unsable RO-detection on JM388 chips */
1431 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1432 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1433 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1434
1435 return 0;
1436 }
1437
jmicron_enable_mmc(struct sdhci_host * host,int on)1438 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1439 {
1440 u8 scratch;
1441
1442 scratch = readb(host->ioaddr + 0xC0);
1443
1444 if (on)
1445 scratch |= 0x01;
1446 else
1447 scratch &= ~0x01;
1448
1449 writeb(scratch, host->ioaddr + 0xC0);
1450 }
1451
jmicron_probe_slot(struct sdhci_pci_slot * slot)1452 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1453 {
1454 if (slot->chip->pdev->revision == 0) {
1455 u16 version;
1456
1457 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1458 version = (version & SDHCI_VENDOR_VER_MASK) >>
1459 SDHCI_VENDOR_VER_SHIFT;
1460
1461 /*
1462 * Older versions of the chip have lots of nasty glitches
1463 * in the ADMA engine. It's best just to avoid it
1464 * completely.
1465 */
1466 if (version < 0xAC)
1467 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1468 }
1469
1470 /* JM388 MMC doesn't support 1.8V while SD supports it */
1471 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1472 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1473 MMC_VDD_29_30 | MMC_VDD_30_31 |
1474 MMC_VDD_165_195; /* allow 1.8V */
1475 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1476 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1477 }
1478
1479 /*
1480 * The secondary interface requires a bit set to get the
1481 * interrupts.
1482 */
1483 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1484 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1485 jmicron_enable_mmc(slot->host, 1);
1486
1487 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1488
1489 return 0;
1490 }
1491
jmicron_remove_slot(struct sdhci_pci_slot * slot,int dead)1492 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1493 {
1494 if (dead)
1495 return;
1496
1497 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1498 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1499 jmicron_enable_mmc(slot->host, 0);
1500 }
1501
1502 #ifdef CONFIG_PM_SLEEP
jmicron_suspend(struct sdhci_pci_chip * chip)1503 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1504 {
1505 int i, ret;
1506
1507 ret = sdhci_pci_suspend_host(chip);
1508 if (ret)
1509 return ret;
1510
1511 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1512 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1513 for (i = 0; i < chip->num_slots; i++)
1514 jmicron_enable_mmc(chip->slots[i]->host, 0);
1515 }
1516
1517 return 0;
1518 }
1519
jmicron_resume(struct sdhci_pci_chip * chip)1520 static int jmicron_resume(struct sdhci_pci_chip *chip)
1521 {
1522 int ret, i;
1523
1524 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1525 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1526 for (i = 0; i < chip->num_slots; i++)
1527 jmicron_enable_mmc(chip->slots[i]->host, 1);
1528 }
1529
1530 ret = jmicron_pmos(chip, 1);
1531 if (ret) {
1532 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1533 return ret;
1534 }
1535
1536 return sdhci_pci_resume_host(chip);
1537 }
1538 #endif
1539
1540 static const struct sdhci_pci_fixes sdhci_jmicron = {
1541 .probe = jmicron_probe,
1542
1543 .probe_slot = jmicron_probe_slot,
1544 .remove_slot = jmicron_remove_slot,
1545
1546 #ifdef CONFIG_PM_SLEEP
1547 .suspend = jmicron_suspend,
1548 .resume = jmicron_resume,
1549 #endif
1550 };
1551
1552 /* SysKonnect CardBus2SDIO extra registers */
1553 #define SYSKT_CTRL 0x200
1554 #define SYSKT_RDFIFO_STAT 0x204
1555 #define SYSKT_WRFIFO_STAT 0x208
1556 #define SYSKT_POWER_DATA 0x20c
1557 #define SYSKT_POWER_330 0xef
1558 #define SYSKT_POWER_300 0xf8
1559 #define SYSKT_POWER_184 0xcc
1560 #define SYSKT_POWER_CMD 0x20d
1561 #define SYSKT_POWER_START (1 << 7)
1562 #define SYSKT_POWER_STATUS 0x20e
1563 #define SYSKT_POWER_STATUS_OK (1 << 0)
1564 #define SYSKT_BOARD_REV 0x210
1565 #define SYSKT_CHIP_REV 0x211
1566 #define SYSKT_CONF_DATA 0x212
1567 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1568 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1569 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1570
syskt_probe(struct sdhci_pci_chip * chip)1571 static int syskt_probe(struct sdhci_pci_chip *chip)
1572 {
1573 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1574 chip->pdev->class &= ~0x0000FF;
1575 chip->pdev->class |= PCI_SDHCI_IFDMA;
1576 }
1577 return 0;
1578 }
1579
syskt_probe_slot(struct sdhci_pci_slot * slot)1580 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1581 {
1582 int tm, ps;
1583
1584 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1585 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1586 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1587 "board rev %d.%d, chip rev %d.%d\n",
1588 board_rev >> 4, board_rev & 0xf,
1589 chip_rev >> 4, chip_rev & 0xf);
1590 if (chip_rev >= 0x20)
1591 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1592
1593 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1594 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1595 udelay(50);
1596 tm = 10; /* Wait max 1 ms */
1597 do {
1598 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1599 if (ps & SYSKT_POWER_STATUS_OK)
1600 break;
1601 udelay(100);
1602 } while (--tm);
1603 if (!tm) {
1604 dev_err(&slot->chip->pdev->dev,
1605 "power regulator never stabilized");
1606 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1607 return -ENODEV;
1608 }
1609
1610 return 0;
1611 }
1612
1613 static const struct sdhci_pci_fixes sdhci_syskt = {
1614 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1615 .probe = syskt_probe,
1616 .probe_slot = syskt_probe_slot,
1617 };
1618
via_probe(struct sdhci_pci_chip * chip)1619 static int via_probe(struct sdhci_pci_chip *chip)
1620 {
1621 if (chip->pdev->revision == 0x10)
1622 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1623
1624 return 0;
1625 }
1626
1627 static const struct sdhci_pci_fixes sdhci_via = {
1628 .probe = via_probe,
1629 };
1630
rtsx_probe_slot(struct sdhci_pci_slot * slot)1631 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1632 {
1633 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1634 return 0;
1635 }
1636
1637 static const struct sdhci_pci_fixes sdhci_rtsx = {
1638 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1639 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1640 SDHCI_QUIRK2_BROKEN_DDR50,
1641 .probe_slot = rtsx_probe_slot,
1642 };
1643
1644 /*AMD chipset generation*/
1645 enum amd_chipset_gen {
1646 AMD_CHIPSET_BEFORE_ML,
1647 AMD_CHIPSET_CZ,
1648 AMD_CHIPSET_NL,
1649 AMD_CHIPSET_UNKNOWN,
1650 };
1651
1652 /* AMD registers */
1653 #define AMD_SD_AUTO_PATTERN 0xB8
1654 #define AMD_MSLEEP_DURATION 4
1655 #define AMD_SD_MISC_CONTROL 0xD0
1656 #define AMD_MAX_TUNE_VALUE 0x0B
1657 #define AMD_AUTO_TUNE_SEL 0x10800
1658 #define AMD_FIFO_PTR 0x30
1659 #define AMD_BIT_MASK 0x1F
1660
amd_tuning_reset(struct sdhci_host * host)1661 static void amd_tuning_reset(struct sdhci_host *host)
1662 {
1663 unsigned int val;
1664
1665 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1666 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1667 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1668
1669 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1670 val &= ~SDHCI_CTRL_EXEC_TUNING;
1671 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1672 }
1673
amd_config_tuning_phase(struct pci_dev * pdev,u8 phase)1674 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1675 {
1676 unsigned int val;
1677
1678 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1679 val &= ~AMD_BIT_MASK;
1680 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1681 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1682 }
1683
amd_enable_manual_tuning(struct pci_dev * pdev)1684 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1685 {
1686 unsigned int val;
1687
1688 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1689 val |= AMD_FIFO_PTR;
1690 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1691 }
1692
amd_execute_tuning_hs200(struct sdhci_host * host,u32 opcode)1693 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1694 {
1695 struct sdhci_pci_slot *slot = sdhci_priv(host);
1696 struct pci_dev *pdev = slot->chip->pdev;
1697 u8 valid_win = 0;
1698 u8 valid_win_max = 0;
1699 u8 valid_win_end = 0;
1700 u8 ctrl, tune_around;
1701
1702 amd_tuning_reset(host);
1703
1704 for (tune_around = 0; tune_around < 12; tune_around++) {
1705 amd_config_tuning_phase(pdev, tune_around);
1706
1707 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1708 valid_win = 0;
1709 msleep(AMD_MSLEEP_DURATION);
1710 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1711 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1712 } else if (++valid_win > valid_win_max) {
1713 valid_win_max = valid_win;
1714 valid_win_end = tune_around;
1715 }
1716 }
1717
1718 if (!valid_win_max) {
1719 dev_err(&pdev->dev, "no tuning point found\n");
1720 return -EIO;
1721 }
1722
1723 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1724
1725 amd_enable_manual_tuning(pdev);
1726
1727 host->mmc->retune_period = 0;
1728
1729 return 0;
1730 }
1731
amd_execute_tuning(struct mmc_host * mmc,u32 opcode)1732 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1733 {
1734 struct sdhci_host *host = mmc_priv(mmc);
1735
1736 /* AMD requires custom HS200 tuning */
1737 if (host->timing == MMC_TIMING_MMC_HS200)
1738 return amd_execute_tuning_hs200(host, opcode);
1739
1740 /* Otherwise perform standard SDHCI tuning */
1741 return sdhci_execute_tuning(mmc, opcode);
1742 }
1743
amd_probe_slot(struct sdhci_pci_slot * slot)1744 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1745 {
1746 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1747
1748 ops->execute_tuning = amd_execute_tuning;
1749
1750 return 0;
1751 }
1752
amd_probe(struct sdhci_pci_chip * chip)1753 static int amd_probe(struct sdhci_pci_chip *chip)
1754 {
1755 struct pci_dev *smbus_dev;
1756 enum amd_chipset_gen gen;
1757
1758 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1759 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1760 if (smbus_dev) {
1761 gen = AMD_CHIPSET_BEFORE_ML;
1762 } else {
1763 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1764 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1765 if (smbus_dev) {
1766 if (smbus_dev->revision < 0x51)
1767 gen = AMD_CHIPSET_CZ;
1768 else
1769 gen = AMD_CHIPSET_NL;
1770 } else {
1771 gen = AMD_CHIPSET_UNKNOWN;
1772 }
1773 }
1774
1775 pci_dev_put(smbus_dev);
1776
1777 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1778 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1779
1780 return 0;
1781 }
1782
sdhci_read_present_state(struct sdhci_host * host)1783 static u32 sdhci_read_present_state(struct sdhci_host *host)
1784 {
1785 return sdhci_readl(host, SDHCI_PRESENT_STATE);
1786 }
1787
amd_sdhci_reset(struct sdhci_host * host,u8 mask)1788 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1789 {
1790 struct sdhci_pci_slot *slot = sdhci_priv(host);
1791 struct pci_dev *pdev = slot->chip->pdev;
1792 u32 present_state;
1793
1794 /*
1795 * SDHC 0x7906 requires a hard reset to clear all internal state.
1796 * Otherwise it can get into a bad state where the DATA lines are always
1797 * read as zeros.
1798 */
1799 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1800 pci_clear_master(pdev);
1801
1802 pci_save_state(pdev);
1803
1804 pci_set_power_state(pdev, PCI_D3cold);
1805 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1806 pdev->current_state);
1807 pci_set_power_state(pdev, PCI_D0);
1808
1809 pci_restore_state(pdev);
1810
1811 /*
1812 * SDHCI_RESET_ALL says the card detect logic should not be
1813 * reset, but since we need to reset the entire controller
1814 * we should wait until the card detect logic has stabilized.
1815 *
1816 * This normally takes about 40ms.
1817 */
1818 readx_poll_timeout(
1819 sdhci_read_present_state,
1820 host,
1821 present_state,
1822 present_state & SDHCI_CD_STABLE,
1823 10000,
1824 100000
1825 );
1826 }
1827
1828 return sdhci_reset(host, mask);
1829 }
1830
1831 static const struct sdhci_ops amd_sdhci_pci_ops = {
1832 .set_clock = sdhci_set_clock,
1833 .enable_dma = sdhci_pci_enable_dma,
1834 .set_bus_width = sdhci_set_bus_width,
1835 .reset = amd_sdhci_reset,
1836 .set_uhs_signaling = sdhci_set_uhs_signaling,
1837 };
1838
1839 static const struct sdhci_pci_fixes sdhci_amd = {
1840 .probe = amd_probe,
1841 .ops = &amd_sdhci_pci_ops,
1842 .probe_slot = amd_probe_slot,
1843 };
1844
1845 static const struct pci_device_id pci_ids[] = {
1846 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1847 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1848 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1849 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1850 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1851 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1852 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1853 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1854 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1855 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1856 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1857 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1858 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1859 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1860 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1861 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1862 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1863 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1864 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1865 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1866 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1867 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1868 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1869 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1870 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1871 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1872 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1873 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1874 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1875 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1876 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1877 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1878 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1879 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1880 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1881 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1882 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1883 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1884 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1885 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1886 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1887 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1888 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1889 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1890 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1891 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1892 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1893 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1894 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1895 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1896 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1897 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1898 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1899 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1900 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1901 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1902 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1903 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1904 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1905 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1906 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1907 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1908 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1909 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc),
1910 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd),
1911 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1912 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1913 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
1914 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
1915 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1916 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc),
1917 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd),
1918 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc),
1919 SDHCI_PCI_DEVICE(O2, 8120, o2),
1920 SDHCI_PCI_DEVICE(O2, 8220, o2),
1921 SDHCI_PCI_DEVICE(O2, 8221, o2),
1922 SDHCI_PCI_DEVICE(O2, 8320, o2),
1923 SDHCI_PCI_DEVICE(O2, 8321, o2),
1924 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1925 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1926 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1927 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1928 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1929 SDHCI_PCI_DEVICE(O2, GG8_9860, o2),
1930 SDHCI_PCI_DEVICE(O2, GG8_9861, o2),
1931 SDHCI_PCI_DEVICE(O2, GG8_9862, o2),
1932 SDHCI_PCI_DEVICE(O2, GG8_9863, o2),
1933 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1934 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1935 SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1936 SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1937 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
1938 SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
1939 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1940 /* Generic SD host controller */
1941 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1942 { /* end: all zeroes */ },
1943 };
1944
1945 MODULE_DEVICE_TABLE(pci, pci_ids);
1946
1947 /*****************************************************************************\
1948 * *
1949 * SDHCI core callbacks *
1950 * *
1951 \*****************************************************************************/
1952
sdhci_pci_enable_dma(struct sdhci_host * host)1953 int sdhci_pci_enable_dma(struct sdhci_host *host)
1954 {
1955 struct sdhci_pci_slot *slot;
1956 struct pci_dev *pdev;
1957
1958 slot = sdhci_priv(host);
1959 pdev = slot->chip->pdev;
1960
1961 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1962 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1963 (host->flags & SDHCI_USE_SDMA)) {
1964 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1965 "doesn't fully claim to support it.\n");
1966 }
1967
1968 pci_set_master(pdev);
1969
1970 return 0;
1971 }
1972
sdhci_pci_hw_reset(struct sdhci_host * host)1973 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1974 {
1975 struct sdhci_pci_slot *slot = sdhci_priv(host);
1976
1977 if (slot->hw_reset)
1978 slot->hw_reset(host);
1979 }
1980
1981 static const struct sdhci_ops sdhci_pci_ops = {
1982 .set_clock = sdhci_set_clock,
1983 .enable_dma = sdhci_pci_enable_dma,
1984 .set_bus_width = sdhci_set_bus_width,
1985 .reset = sdhci_reset,
1986 .set_uhs_signaling = sdhci_set_uhs_signaling,
1987 .hw_reset = sdhci_pci_hw_reset,
1988 };
1989
1990 /*****************************************************************************\
1991 * *
1992 * Suspend/resume *
1993 * *
1994 \*****************************************************************************/
1995
1996 #ifdef CONFIG_PM_SLEEP
sdhci_pci_suspend(struct device * dev)1997 static int sdhci_pci_suspend(struct device *dev)
1998 {
1999 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2000
2001 if (!chip)
2002 return 0;
2003
2004 if (chip->fixes && chip->fixes->suspend)
2005 return chip->fixes->suspend(chip);
2006
2007 return sdhci_pci_suspend_host(chip);
2008 }
2009
sdhci_pci_resume(struct device * dev)2010 static int sdhci_pci_resume(struct device *dev)
2011 {
2012 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2013
2014 if (!chip)
2015 return 0;
2016
2017 if (chip->fixes && chip->fixes->resume)
2018 return chip->fixes->resume(chip);
2019
2020 return sdhci_pci_resume_host(chip);
2021 }
2022 #endif
2023
2024 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend(struct device * dev)2025 static int sdhci_pci_runtime_suspend(struct device *dev)
2026 {
2027 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2028
2029 if (!chip)
2030 return 0;
2031
2032 if (chip->fixes && chip->fixes->runtime_suspend)
2033 return chip->fixes->runtime_suspend(chip);
2034
2035 return sdhci_pci_runtime_suspend_host(chip);
2036 }
2037
sdhci_pci_runtime_resume(struct device * dev)2038 static int sdhci_pci_runtime_resume(struct device *dev)
2039 {
2040 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2041
2042 if (!chip)
2043 return 0;
2044
2045 if (chip->fixes && chip->fixes->runtime_resume)
2046 return chip->fixes->runtime_resume(chip);
2047
2048 return sdhci_pci_runtime_resume_host(chip);
2049 }
2050 #endif
2051
2052 static const struct dev_pm_ops sdhci_pci_pm_ops = {
2053 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
2054 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
2055 sdhci_pci_runtime_resume, NULL)
2056 };
2057
2058 /*****************************************************************************\
2059 * *
2060 * Device probing/removal *
2061 * *
2062 \*****************************************************************************/
2063
sdhci_pci_add_gpio_lookup_table(struct sdhci_pci_chip * chip)2064 static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table(
2065 struct sdhci_pci_chip *chip)
2066 {
2067 struct gpiod_lookup_table *cd_gpio_lookup_table;
2068 const struct dmi_system_id *dmi_id = NULL;
2069 size_t count;
2070
2071 if (chip->fixes && chip->fixes->cd_gpio_override)
2072 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override);
2073
2074 if (!dmi_id)
2075 return NULL;
2076
2077 cd_gpio_lookup_table = dmi_id->driver_data;
2078 for (count = 0; cd_gpio_lookup_table->table[count].key; count++)
2079 ;
2080
2081 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data,
2082 /* count + 1 terminating entry */
2083 struct_size(cd_gpio_lookup_table, table, count + 1),
2084 GFP_KERNEL);
2085 if (!cd_gpio_lookup_table)
2086 return ERR_PTR(-ENOMEM);
2087
2088 gpiod_add_lookup_table(cd_gpio_lookup_table);
2089 return cd_gpio_lookup_table;
2090 }
2091
sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table * lookup_table)2092 static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table)
2093 {
2094 if (lookup_table) {
2095 gpiod_remove_lookup_table(lookup_table);
2096 kfree(lookup_table);
2097 }
2098 }
2099
sdhci_pci_probe_slot(struct pci_dev * pdev,struct sdhci_pci_chip * chip,int first_bar,int slotno)2100 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
2101 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
2102 int slotno)
2103 {
2104 struct sdhci_pci_slot *slot;
2105 struct sdhci_host *host;
2106 int ret, bar = first_bar + slotno;
2107 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
2108
2109 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
2110 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
2111 return ERR_PTR(-ENODEV);
2112 }
2113
2114 if (pci_resource_len(pdev, bar) < 0x100) {
2115 dev_err(&pdev->dev, "Invalid iomem size. You may "
2116 "experience problems.\n");
2117 }
2118
2119 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
2120 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
2121 return ERR_PTR(-ENODEV);
2122 }
2123
2124 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
2125 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
2126 return ERR_PTR(-ENODEV);
2127 }
2128
2129 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
2130 if (IS_ERR(host)) {
2131 dev_err(&pdev->dev, "cannot allocate host\n");
2132 return ERR_CAST(host);
2133 }
2134
2135 slot = sdhci_priv(host);
2136
2137 slot->chip = chip;
2138 slot->host = host;
2139 slot->cd_idx = -1;
2140
2141 host->hw_name = "PCI";
2142 host->ops = chip->fixes && chip->fixes->ops ?
2143 chip->fixes->ops :
2144 &sdhci_pci_ops;
2145 host->quirks = chip->quirks;
2146 host->quirks2 = chip->quirks2;
2147
2148 host->irq = pdev->irq;
2149
2150 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
2151 if (ret) {
2152 dev_err(&pdev->dev, "cannot request region\n");
2153 goto cleanup;
2154 }
2155
2156 host->ioaddr = pcim_iomap_table(pdev)[bar];
2157
2158 if (chip->fixes && chip->fixes->probe_slot) {
2159 ret = chip->fixes->probe_slot(slot);
2160 if (ret)
2161 goto cleanup;
2162 }
2163
2164 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
2165 host->mmc->slotno = slotno;
2166 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2167
2168 if (device_can_wakeup(&pdev->dev))
2169 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2170
2171 if (host->mmc->caps & MMC_CAP_CD_WAKE)
2172 device_init_wakeup(&pdev->dev, true);
2173
2174 if (slot->cd_idx >= 0) {
2175 struct gpiod_lookup_table *cd_gpio_lookup_table;
2176
2177 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip);
2178 if (IS_ERR(cd_gpio_lookup_table)) {
2179 ret = PTR_ERR(cd_gpio_lookup_table);
2180 goto remove;
2181 }
2182
2183 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
2184 slot->cd_override_level, 0);
2185
2186 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table);
2187
2188 if (ret && ret != -EPROBE_DEFER)
2189 ret = mmc_gpiod_request_cd(host->mmc, NULL,
2190 slot->cd_idx,
2191 slot->cd_override_level,
2192 0);
2193 if (ret == -EPROBE_DEFER)
2194 goto remove;
2195
2196 if (ret) {
2197 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2198 slot->cd_idx = -1;
2199 }
2200 }
2201
2202 if (chip->fixes && chip->fixes->add_host)
2203 ret = chip->fixes->add_host(slot);
2204 else
2205 ret = sdhci_add_host(host);
2206 if (ret)
2207 goto remove;
2208
2209 /*
2210 * Check if the chip needs a separate GPIO for card detect to wake up
2211 * from runtime suspend. If it is not there, don't allow runtime PM.
2212 */
2213 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0)
2214 chip->allow_runtime_pm = false;
2215
2216 return slot;
2217
2218 remove:
2219 if (chip->fixes && chip->fixes->remove_slot)
2220 chip->fixes->remove_slot(slot, 0);
2221
2222 cleanup:
2223 sdhci_free_host(host);
2224
2225 return ERR_PTR(ret);
2226 }
2227
sdhci_pci_remove_slot(struct sdhci_pci_slot * slot)2228 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2229 {
2230 int dead;
2231 u32 scratch;
2232
2233 dead = 0;
2234 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2235 if (scratch == (u32)-1)
2236 dead = 1;
2237
2238 sdhci_remove_host(slot->host, dead);
2239
2240 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2241 slot->chip->fixes->remove_slot(slot, dead);
2242
2243 sdhci_free_host(slot->host);
2244 }
2245
sdhci_pci_runtime_pm_allow(struct device * dev)2246 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2247 {
2248 pm_suspend_ignore_children(dev, 1);
2249 pm_runtime_set_autosuspend_delay(dev, 50);
2250 pm_runtime_use_autosuspend(dev);
2251 pm_runtime_allow(dev);
2252 /* Stay active until mmc core scans for a card */
2253 pm_runtime_put_noidle(dev);
2254 }
2255
sdhci_pci_runtime_pm_forbid(struct device * dev)2256 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2257 {
2258 pm_runtime_forbid(dev);
2259 pm_runtime_get_noresume(dev);
2260 }
2261
sdhci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2262 static int sdhci_pci_probe(struct pci_dev *pdev,
2263 const struct pci_device_id *ent)
2264 {
2265 struct sdhci_pci_chip *chip;
2266 struct sdhci_pci_slot *slot;
2267
2268 u8 slots, first_bar;
2269 int ret, i;
2270
2271 BUG_ON(pdev == NULL);
2272 BUG_ON(ent == NULL);
2273
2274 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2275 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2276
2277 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2278 if (ret)
2279 return pcibios_err_to_errno(ret);
2280
2281 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2282 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2283
2284 BUG_ON(slots > MAX_SLOTS);
2285
2286 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2287 if (ret)
2288 return pcibios_err_to_errno(ret);
2289
2290 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2291
2292 if (first_bar > 5) {
2293 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2294 return -ENODEV;
2295 }
2296
2297 ret = pcim_enable_device(pdev);
2298 if (ret)
2299 return ret;
2300
2301 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2302 if (!chip)
2303 return -ENOMEM;
2304
2305 chip->pdev = pdev;
2306 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2307 if (chip->fixes) {
2308 chip->quirks = chip->fixes->quirks;
2309 chip->quirks2 = chip->fixes->quirks2;
2310 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2311 }
2312 chip->num_slots = slots;
2313 chip->pm_retune = true;
2314 chip->rpm_retune = true;
2315
2316 pci_set_drvdata(pdev, chip);
2317
2318 if (chip->fixes && chip->fixes->probe) {
2319 ret = chip->fixes->probe(chip);
2320 if (ret)
2321 return ret;
2322 }
2323
2324 slots = chip->num_slots; /* Quirk may have changed this */
2325
2326 for (i = 0; i < slots; i++) {
2327 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2328 if (IS_ERR(slot)) {
2329 for (i--; i >= 0; i--)
2330 sdhci_pci_remove_slot(chip->slots[i]);
2331 return PTR_ERR(slot);
2332 }
2333
2334 chip->slots[i] = slot;
2335 }
2336
2337 if (chip->allow_runtime_pm)
2338 sdhci_pci_runtime_pm_allow(&pdev->dev);
2339
2340 return 0;
2341 }
2342
sdhci_pci_remove(struct pci_dev * pdev)2343 static void sdhci_pci_remove(struct pci_dev *pdev)
2344 {
2345 int i;
2346 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2347
2348 if (chip->allow_runtime_pm)
2349 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2350
2351 for (i = 0; i < chip->num_slots; i++)
2352 sdhci_pci_remove_slot(chip->slots[i]);
2353 }
2354
2355 static struct pci_driver sdhci_driver = {
2356 .name = "sdhci-pci",
2357 .id_table = pci_ids,
2358 .probe = sdhci_pci_probe,
2359 .remove = sdhci_pci_remove,
2360 .driver = {
2361 .pm = &sdhci_pci_pm_ops,
2362 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2363 },
2364 };
2365
2366 module_pci_driver(sdhci_driver);
2367
2368 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2369 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2370 MODULE_LICENSE("GPL");
2371