xref: /openbmc/qemu/hw/timer/imx_epit.c (revision ba324b3f)
1 /*
2  * IMX EPIT Timer
3  *
4  * Copyright (c) 2008 OK Labs
5  * Copyright (c) 2011 NICTA Pty Ltd
6  * Originally written by Hans Jiang
7  * Updated by Peter Chubb
8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
9  * Updated by Axel Heider
10  *
11  * This code is licensed under GPL version 2 or later.  See
12  * the COPYING file in the top-level directory.
13  *
14  */
15 
16 #include "qemu/osdep.h"
17 #include "hw/timer/imx_epit.h"
18 #include "migration/vmstate.h"
19 #include "hw/irq.h"
20 #include "hw/misc/imx_ccm.h"
21 #include "qemu/module.h"
22 #include "qemu/log.h"
23 
24 #ifndef DEBUG_IMX_EPIT
25 #define DEBUG_IMX_EPIT 0
26 #endif
27 
28 #define DPRINTF(fmt, args...) \
29     do { \
30         if (DEBUG_IMX_EPIT) { \
31             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \
32                                              __func__, ##args); \
33         } \
34     } while (0)
35 
imx_epit_reg_name(uint32_t reg)36 static const char *imx_epit_reg_name(uint32_t reg)
37 {
38     switch (reg) {
39     case 0:
40         return "CR";
41     case 1:
42         return "SR";
43     case 2:
44         return "LR";
45     case 3:
46         return "CMP";
47     case 4:
48         return "CNT";
49     default:
50         return "[?]";
51     }
52 }
53 
54 /*
55  * Exact clock frequencies vary from board to board.
56  * These are typical.
57  */
58 static const IMXClk imx_epit_clocks[] =  {
59     CLK_NONE,      /* 00 disabled */
60     CLK_IPG,       /* 01 ipg_clk, ~532MHz */
61     CLK_IPG_HIGH,  /* 10 ipg_clk_highfreq */
62     CLK_32k,       /* 11 ipg_clk_32k -- ~32kHz */
63 };
64 
65 /*
66  * Update interrupt status
67  */
imx_epit_update_int(IMXEPITState * s)68 static void imx_epit_update_int(IMXEPITState *s)
69 {
70     if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
71         qemu_irq_raise(s->irq);
72     } else {
73         qemu_irq_lower(s->irq);
74     }
75 }
76 
imx_epit_get_freq(IMXEPITState * s)77 static uint32_t imx_epit_get_freq(IMXEPITState *s)
78 {
79     uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
80     uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
81     uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
82     uint32_t freq = f_in / prescaler;
83     DPRINTF("ptimer frequency is %u\n", freq);
84     return freq;
85 }
86 
87 /*
88  * This is called both on hardware (device) reset and software reset.
89  */
imx_epit_reset(IMXEPITState * s,bool is_hard_reset)90 static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
91 {
92     /* Soft reset doesn't touch some bits; hard reset clears them */
93     if (is_hard_reset) {
94         s->cr = 0;
95     } else {
96         s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
97     }
98     s->sr = 0;
99     s->lr = EPIT_TIMER_MAX;
100     s->cmp = 0;
101     ptimer_transaction_begin(s->timer_cmp);
102     ptimer_transaction_begin(s->timer_reload);
103 
104     /*
105      * The reset switches off the input clock, so even if the CR.EN is still
106      * set, the timers are no longer running.
107      */
108     assert(imx_epit_get_freq(s) == 0);
109     ptimer_stop(s->timer_cmp);
110     ptimer_stop(s->timer_reload);
111     /* init both timers to EPIT_TIMER_MAX */
112     ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
113     ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
114     ptimer_transaction_commit(s->timer_cmp);
115     ptimer_transaction_commit(s->timer_reload);
116 }
117 
imx_epit_read(void * opaque,hwaddr offset,unsigned size)118 static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
119 {
120     IMXEPITState *s = IMX_EPIT(opaque);
121     uint32_t reg_value = 0;
122 
123     switch (offset >> 2) {
124     case 0: /* Control Register */
125         reg_value = s->cr;
126         break;
127 
128     case 1: /* Status Register */
129         reg_value = s->sr;
130         break;
131 
132     case 2: /* LR - ticks*/
133         reg_value = s->lr;
134         break;
135 
136     case 3: /* CMP */
137         reg_value = s->cmp;
138         break;
139 
140     case 4: /* CNT */
141         reg_value = ptimer_get_count(s->timer_reload);
142         break;
143 
144     default:
145         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
146                       HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
147         break;
148     }
149 
150     DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value);
151 
152     return reg_value;
153 }
154 
155 /*
156  * Must be called from a ptimer_transaction_begin/commit block for
157  * s->timer_cmp, but outside of a transaction block of s->timer_reload,
158  * so the proper counter value is read.
159  */
imx_epit_update_compare_timer(IMXEPITState * s)160 static void imx_epit_update_compare_timer(IMXEPITState *s)
161 {
162     uint64_t counter = 0;
163     bool is_oneshot = false;
164     /*
165      * The compare timer only has to run if the timer peripheral is active
166      * and there is an input clock, Otherwise it can be switched off.
167      */
168     bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
169     if (is_active) {
170         /*
171          * Calculate next timeout for compare timer. Reading the reload
172          * counter returns proper results only if pending transactions
173          * on it are committed here. Otherwise stale values are be read.
174          */
175         counter = ptimer_get_count(s->timer_reload);
176         uint64_t limit = ptimer_get_limit(s->timer_cmp);
177         /*
178          * The compare timer is a periodic timer if the limit is at least
179          * the compare value. Otherwise it may fire at most once in the
180          * current round.
181          */
182         is_oneshot = (limit < s->cmp);
183         if (counter >= s->cmp) {
184             /* The compare timer fires in the current round. */
185             counter -= s->cmp;
186         } else if (!is_oneshot) {
187             /*
188              * The compare timer fires after a reload, as it is below the
189              * compare value already in this round. Note that the counter
190              * value calculated below can be above the 32-bit limit, which
191              * is legal here because the compare timer is an internal
192              * helper ptimer only.
193              */
194             counter += limit - s->cmp;
195         } else {
196             /*
197              * The compare timer won't fire in this round, and the limit is
198              * set to a value below the compare value. This practically means
199              * it will never fire, so it can be switched off.
200              */
201             is_active = false;
202         }
203     }
204 
205     /*
206      * Set the compare timer and let it run, or stop it. This is agnostic
207      * of CR.OCIEN bit, as this bit affects interrupt generation only. The
208      * compare timer needs to run even if no interrupts are to be generated,
209      * because the SR.OCIF bit must be updated also.
210      * Note that the timer might already be stopped or be running with
211      * counter values. However, finding out when an update is needed and
212      * when not is not trivial. It's much easier applying the setting again,
213      * as this does not harm either and the overhead is negligible.
214      */
215     if (is_active) {
216         ptimer_set_count(s->timer_cmp, counter);
217         ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
218     } else {
219         ptimer_stop(s->timer_cmp);
220     }
221 
222 }
223 
imx_epit_write_cr(IMXEPITState * s,uint32_t value)224 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
225 {
226     uint32_t oldcr = s->cr;
227 
228     s->cr = value & 0x03ffffff;
229 
230     if (s->cr & CR_SWR) {
231         /*
232          * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
233          * are still stopped because the input clock is disabled.
234          */
235         imx_epit_reset(s, false);
236     } else {
237         uint32_t freq;
238         uint32_t toggled_cr_bits = oldcr ^ s->cr;
239         /* re-initialize the limits if CR.RLD has changed */
240         bool set_limit = toggled_cr_bits & CR_RLD;
241         /* set the counter if the timer got just enabled and CR.ENMOD is set */
242         bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
243         bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
244 
245         ptimer_transaction_begin(s->timer_cmp);
246         ptimer_transaction_begin(s->timer_reload);
247         freq = imx_epit_get_freq(s);
248         if (freq) {
249             ptimer_set_freq(s->timer_reload, freq);
250             ptimer_set_freq(s->timer_cmp, freq);
251         }
252 
253         if (set_limit || set_counter) {
254             uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
255             ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
256             if (set_limit) {
257                 ptimer_set_limit(s->timer_cmp, limit, 0);
258             }
259         }
260         /*
261          * If there is an input clock and the peripheral is enabled, then
262          * ensure the wall clock timer is ticking. Otherwise stop the timers.
263          * The compare timer will be updated later.
264          */
265         if (freq && (s->cr & CR_EN)) {
266             ptimer_run(s->timer_reload, 0);
267         } else {
268             ptimer_stop(s->timer_reload);
269         }
270         /* Commit changes to reload timer, so they can propagate. */
271         ptimer_transaction_commit(s->timer_reload);
272         /* Update compare timer based on the committed reload timer value. */
273         imx_epit_update_compare_timer(s);
274         ptimer_transaction_commit(s->timer_cmp);
275     }
276 
277     /*
278      * The interrupt state can change due to:
279      * - reset clears both SR.OCIF and CR.OCIE
280      * - write to CR.EN or CR.OCIE
281      */
282     imx_epit_update_int(s);
283 }
284 
imx_epit_write_sr(IMXEPITState * s,uint32_t value)285 static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
286 {
287     /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
288     if (value & SR_OCIF) {
289         s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
290         imx_epit_update_int(s);
291     }
292 }
293 
imx_epit_write_lr(IMXEPITState * s,uint32_t value)294 static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
295 {
296     s->lr = value;
297 
298     ptimer_transaction_begin(s->timer_cmp);
299     ptimer_transaction_begin(s->timer_reload);
300     if (s->cr & CR_RLD) {
301         /* Also set the limit if the LRD bit is set */
302         /* If IOVW bit is set then set the timer value */
303         ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
304         ptimer_set_limit(s->timer_cmp, s->lr, 0);
305     } else if (s->cr & CR_IOVW) {
306         /* If IOVW bit is set then set the timer value */
307         ptimer_set_count(s->timer_reload, s->lr);
308     }
309     /* Commit the changes to s->timer_reload, so they can propagate. */
310     ptimer_transaction_commit(s->timer_reload);
311     /* Update the compare timer based on the committed reload timer value. */
312     imx_epit_update_compare_timer(s);
313     ptimer_transaction_commit(s->timer_cmp);
314 }
315 
imx_epit_write_cmp(IMXEPITState * s,uint32_t value)316 static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
317 {
318     s->cmp = value;
319 
320     /* Update the compare timer based on the committed reload timer value. */
321     ptimer_transaction_begin(s->timer_cmp);
322     imx_epit_update_compare_timer(s);
323     ptimer_transaction_commit(s->timer_cmp);
324 }
325 
imx_epit_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)326 static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
327                            unsigned size)
328 {
329     IMXEPITState *s = IMX_EPIT(opaque);
330 
331     DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
332             (uint32_t)value);
333 
334     switch (offset >> 2) {
335     case 0: /* CR */
336         imx_epit_write_cr(s, (uint32_t)value);
337         break;
338 
339     case 1: /* SR */
340         imx_epit_write_sr(s, (uint32_t)value);
341         break;
342 
343     case 2: /* LR */
344         imx_epit_write_lr(s, (uint32_t)value);
345         break;
346 
347     case 3: /* CMP */
348         imx_epit_write_cmp(s, (uint32_t)value);
349         break;
350 
351     default:
352         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
353                       HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
354         break;
355     }
356 }
357 
imx_epit_cmp(void * opaque)358 static void imx_epit_cmp(void *opaque)
359 {
360     IMXEPITState *s = IMX_EPIT(opaque);
361 
362     /* The cmp ptimer can't be running when the peripheral is disabled */
363     assert(s->cr & CR_EN);
364 
365     DPRINTF("sr was %d\n", s->sr);
366     /* Set interrupt status bit SR.OCIF and update the interrupt state */
367     s->sr |= SR_OCIF;
368     imx_epit_update_int(s);
369 }
370 
imx_epit_reload(void * opaque)371 static void imx_epit_reload(void *opaque)
372 {
373     /* No action required on rollover of timer_reload */
374 }
375 
376 static const MemoryRegionOps imx_epit_ops = {
377     .read = imx_epit_read,
378     .write = imx_epit_write,
379     .endianness = DEVICE_NATIVE_ENDIAN,
380 };
381 
382 static const VMStateDescription vmstate_imx_timer_epit = {
383     .name = TYPE_IMX_EPIT,
384     .version_id = 3,
385     .minimum_version_id = 3,
386     .fields = (const VMStateField[]) {
387         VMSTATE_UINT32(cr, IMXEPITState),
388         VMSTATE_UINT32(sr, IMXEPITState),
389         VMSTATE_UINT32(lr, IMXEPITState),
390         VMSTATE_UINT32(cmp, IMXEPITState),
391         VMSTATE_PTIMER(timer_reload, IMXEPITState),
392         VMSTATE_PTIMER(timer_cmp, IMXEPITState),
393         VMSTATE_END_OF_LIST()
394     }
395 };
396 
imx_epit_realize(DeviceState * dev,Error ** errp)397 static void imx_epit_realize(DeviceState *dev, Error **errp)
398 {
399     IMXEPITState *s = IMX_EPIT(dev);
400     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
401 
402     DPRINTF("\n");
403 
404     sysbus_init_irq(sbd, &s->irq);
405     memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
406                           0x00001000);
407     sysbus_init_mmio(sbd, &s->iomem);
408 
409     /*
410      * The reload timer keeps running when the peripheral is enabled. It is a
411      * kind of wall clock that does not generate any interrupts. The callback
412      * needs to be provided, but it does nothing as the ptimer already supports
413      * all necessary reloading functionality.
414      */
415     s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
416 
417     /*
418      * The compare timer is running only when the peripheral configuration is
419      * in a state that will generate compare interrupts.
420      */
421     s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
422 }
423 
imx_epit_dev_reset(DeviceState * dev)424 static void imx_epit_dev_reset(DeviceState *dev)
425 {
426     IMXEPITState *s = IMX_EPIT(dev);
427     imx_epit_reset(s, true);
428 }
429 
imx_epit_class_init(ObjectClass * klass,void * data)430 static void imx_epit_class_init(ObjectClass *klass, void *data)
431 {
432     DeviceClass *dc  = DEVICE_CLASS(klass);
433 
434     dc->realize = imx_epit_realize;
435     dc->reset = imx_epit_dev_reset;
436     dc->vmsd = &vmstate_imx_timer_epit;
437     dc->desc = "i.MX periodic timer";
438 }
439 
440 static const TypeInfo imx_epit_info = {
441     .name = TYPE_IMX_EPIT,
442     .parent = TYPE_SYS_BUS_DEVICE,
443     .instance_size = sizeof(IMXEPITState),
444     .class_init = imx_epit_class_init,
445 };
446 
imx_epit_register_types(void)447 static void imx_epit_register_types(void)
448 {
449     type_register_static(&imx_epit_info);
450 }
451 
452 type_init(imx_epit_register_types)
453