xref: /openbmc/linux/arch/sh/kernel/cpu/sh4a/setup-sh7724.c (revision c95baf12f5077419db01313ab61c2aac007d40cd)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * SH7724 Setup
4   *
5   * Copyright (C) 2009 Renesas Solutions Corp.
6   *
7   * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8   *
9   * Based on SH7723 Setup
10   * Copyright (C) 2008  Paul Mundt
11   */
12  #include <linux/platform_device.h>
13  #include <linux/init.h>
14  #include <linux/serial.h>
15  #include <linux/mm.h>
16  #include <linux/serial_sci.h>
17  #include <linux/uio_driver.h>
18  #include <linux/sh_dma.h>
19  #include <linux/sh_timer.h>
20  #include <linux/sh_intc.h>
21  #include <linux/io.h>
22  #include <linux/notifier.h>
23  
24  #include <asm/suspend.h>
25  #include <asm/clock.h>
26  #include <asm/mmzone.h>
27  #include <asm/platform_early.h>
28  
29  #include <cpu/dma-register.h>
30  #include <cpu/sh7724.h>
31  
32  /* DMA */
33  static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
34  	{
35  		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
36  		.addr		= 0xffe0000c,
37  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
38  		.mid_rid	= 0x21,
39  	}, {
40  		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
41  		.addr		= 0xffe00014,
42  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
43  		.mid_rid	= 0x22,
44  	}, {
45  		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
46  		.addr		= 0xffe1000c,
47  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
48  		.mid_rid	= 0x25,
49  	}, {
50  		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
51  		.addr		= 0xffe10014,
52  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
53  		.mid_rid	= 0x26,
54  	}, {
55  		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
56  		.addr		= 0xffe2000c,
57  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
58  		.mid_rid	= 0x29,
59  	}, {
60  		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
61  		.addr		= 0xffe20014,
62  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
63  		.mid_rid	= 0x2a,
64  	}, {
65  		.slave_id	= SHDMA_SLAVE_SCIF3_TX,
66  		.addr		= 0xa4e30020,
67  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
68  		.mid_rid	= 0x2d,
69  	}, {
70  		.slave_id	= SHDMA_SLAVE_SCIF3_RX,
71  		.addr		= 0xa4e30024,
72  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
73  		.mid_rid	= 0x2e,
74  	}, {
75  		.slave_id	= SHDMA_SLAVE_SCIF4_TX,
76  		.addr		= 0xa4e40020,
77  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
78  		.mid_rid	= 0x31,
79  	}, {
80  		.slave_id	= SHDMA_SLAVE_SCIF4_RX,
81  		.addr		= 0xa4e40024,
82  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
83  		.mid_rid	= 0x32,
84  	}, {
85  		.slave_id	= SHDMA_SLAVE_SCIF5_TX,
86  		.addr		= 0xa4e50020,
87  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
88  		.mid_rid	= 0x35,
89  	}, {
90  		.slave_id	= SHDMA_SLAVE_SCIF5_RX,
91  		.addr		= 0xa4e50024,
92  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
93  		.mid_rid	= 0x36,
94  	}, {
95  		.slave_id	= SHDMA_SLAVE_USB0D0_TX,
96  		.addr		= 0xA4D80100,
97  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
98  		.mid_rid	= 0x73,
99  	}, {
100  		.slave_id	= SHDMA_SLAVE_USB0D0_RX,
101  		.addr		= 0xA4D80100,
102  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
103  		.mid_rid	= 0x73,
104  	}, {
105  		.slave_id	= SHDMA_SLAVE_USB0D1_TX,
106  		.addr		= 0xA4D80120,
107  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
108  		.mid_rid	= 0x77,
109  	}, {
110  		.slave_id	= SHDMA_SLAVE_USB0D1_RX,
111  		.addr		= 0xA4D80120,
112  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
113  		.mid_rid	= 0x77,
114  	}, {
115  		.slave_id	= SHDMA_SLAVE_USB1D0_TX,
116  		.addr		= 0xA4D90100,
117  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
118  		.mid_rid	= 0xab,
119  	}, {
120  		.slave_id	= SHDMA_SLAVE_USB1D0_RX,
121  		.addr		= 0xA4D90100,
122  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
123  		.mid_rid	= 0xab,
124  	}, {
125  		.slave_id	= SHDMA_SLAVE_USB1D1_TX,
126  		.addr		= 0xA4D90120,
127  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
128  		.mid_rid	= 0xaf,
129  	}, {
130  		.slave_id	= SHDMA_SLAVE_USB1D1_RX,
131  		.addr		= 0xA4D90120,
132  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
133  		.mid_rid	= 0xaf,
134  	}, {
135  		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
136  		.addr		= 0x04ce0030,
137  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
138  		.mid_rid	= 0xc1,
139  	}, {
140  		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
141  		.addr		= 0x04ce0030,
142  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
143  		.mid_rid	= 0xc2,
144  	}, {
145  		.slave_id	= SHDMA_SLAVE_SDHI1_TX,
146  		.addr		= 0x04cf0030,
147  		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
148  		.mid_rid	= 0xc9,
149  	}, {
150  		.slave_id	= SHDMA_SLAVE_SDHI1_RX,
151  		.addr		= 0x04cf0030,
152  		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
153  		.mid_rid	= 0xca,
154  	},
155  };
156  
157  static const struct sh_dmae_channel sh7724_dmae_channels[] = {
158  	{
159  		.offset = 0,
160  		.dmars = 0,
161  		.dmars_bit = 0,
162  	}, {
163  		.offset = 0x10,
164  		.dmars = 0,
165  		.dmars_bit = 8,
166  	}, {
167  		.offset = 0x20,
168  		.dmars = 4,
169  		.dmars_bit = 0,
170  	}, {
171  		.offset = 0x30,
172  		.dmars = 4,
173  		.dmars_bit = 8,
174  	}, {
175  		.offset = 0x50,
176  		.dmars = 8,
177  		.dmars_bit = 0,
178  	}, {
179  		.offset = 0x60,
180  		.dmars = 8,
181  		.dmars_bit = 8,
182  	}
183  };
184  
185  static const unsigned int ts_shift[] = TS_SHIFT;
186  
187  static struct sh_dmae_pdata dma_platform_data = {
188  	.slave		= sh7724_dmae_slaves,
189  	.slave_num	= ARRAY_SIZE(sh7724_dmae_slaves),
190  	.channel	= sh7724_dmae_channels,
191  	.channel_num	= ARRAY_SIZE(sh7724_dmae_channels),
192  	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
193  	.ts_low_mask	= CHCR_TS_LOW_MASK,
194  	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
195  	.ts_high_mask	= CHCR_TS_HIGH_MASK,
196  	.ts_shift	= ts_shift,
197  	.ts_shift_num	= ARRAY_SIZE(ts_shift),
198  	.dmaor_init	= DMAOR_INIT,
199  };
200  
201  /* Resource order important! */
202  static struct resource sh7724_dmae0_resources[] = {
203  	{
204  		/* Channel registers and DMAOR */
205  		.start	= 0xfe008020,
206  		.end	= 0xfe00808f,
207  		.flags	= IORESOURCE_MEM,
208  	},
209  	{
210  		/* DMARSx */
211  		.start	= 0xfe009000,
212  		.end	= 0xfe00900b,
213  		.flags	= IORESOURCE_MEM,
214  	},
215  	{
216  		.name	= "error_irq",
217  		.start	= evt2irq(0xbc0),
218  		.end	= evt2irq(0xbc0),
219  		.flags	= IORESOURCE_IRQ,
220  	},
221  	{
222  		/* IRQ for channels 0-3 */
223  		.start	= evt2irq(0x800),
224  		.end	= evt2irq(0x860),
225  		.flags	= IORESOURCE_IRQ,
226  	},
227  	{
228  		/* IRQ for channels 4-5 */
229  		.start	= evt2irq(0xb80),
230  		.end	= evt2irq(0xba0),
231  		.flags	= IORESOURCE_IRQ,
232  	},
233  };
234  
235  /* Resource order important! */
236  static struct resource sh7724_dmae1_resources[] = {
237  	{
238  		/* Channel registers and DMAOR */
239  		.start	= 0xfdc08020,
240  		.end	= 0xfdc0808f,
241  		.flags	= IORESOURCE_MEM,
242  	},
243  	{
244  		/* DMARSx */
245  		.start	= 0xfdc09000,
246  		.end	= 0xfdc0900b,
247  		.flags	= IORESOURCE_MEM,
248  	},
249  	{
250  		.name	= "error_irq",
251  		.start	= evt2irq(0xb40),
252  		.end	= evt2irq(0xb40),
253  		.flags	= IORESOURCE_IRQ,
254  	},
255  	{
256  		/* IRQ for channels 0-3 */
257  		.start	= evt2irq(0x700),
258  		.end	= evt2irq(0x760),
259  		.flags	= IORESOURCE_IRQ,
260  	},
261  	{
262  		/* IRQ for channels 4-5 */
263  		.start	= evt2irq(0xb00),
264  		.end	= evt2irq(0xb20),
265  		.flags	= IORESOURCE_IRQ,
266  	},
267  };
268  
269  static struct platform_device dma0_device = {
270  	.name		= "sh-dma-engine",
271  	.id		= 0,
272  	.resource	= sh7724_dmae0_resources,
273  	.num_resources	= ARRAY_SIZE(sh7724_dmae0_resources),
274  	.dev		= {
275  		.platform_data	= &dma_platform_data,
276  	},
277  };
278  
279  static struct platform_device dma1_device = {
280  	.name		= "sh-dma-engine",
281  	.id		= 1,
282  	.resource	= sh7724_dmae1_resources,
283  	.num_resources	= ARRAY_SIZE(sh7724_dmae1_resources),
284  	.dev		= {
285  		.platform_data	= &dma_platform_data,
286  	},
287  };
288  
289  /* Serial */
290  static struct plat_sci_port scif0_platform_data = {
291  	.scscr		= SCSCR_REIE,
292  	.type           = PORT_SCIF,
293  	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
294  };
295  
296  static struct resource scif0_resources[] = {
297  	DEFINE_RES_MEM(0xffe00000, 0x100),
298  	DEFINE_RES_IRQ(evt2irq(0xc00)),
299  };
300  
301  static struct platform_device scif0_device = {
302  	.name		= "sh-sci",
303  	.id		= 0,
304  	.resource	= scif0_resources,
305  	.num_resources	= ARRAY_SIZE(scif0_resources),
306  	.dev		= {
307  		.platform_data	= &scif0_platform_data,
308  	},
309  };
310  
311  static struct plat_sci_port scif1_platform_data = {
312  	.scscr		= SCSCR_REIE,
313  	.type           = PORT_SCIF,
314  	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
315  };
316  
317  static struct resource scif1_resources[] = {
318  	DEFINE_RES_MEM(0xffe10000, 0x100),
319  	DEFINE_RES_IRQ(evt2irq(0xc20)),
320  };
321  
322  static struct platform_device scif1_device = {
323  	.name		= "sh-sci",
324  	.id		= 1,
325  	.resource	= scif1_resources,
326  	.num_resources	= ARRAY_SIZE(scif1_resources),
327  	.dev		= {
328  		.platform_data	= &scif1_platform_data,
329  	},
330  };
331  
332  static struct plat_sci_port scif2_platform_data = {
333  	.scscr		= SCSCR_REIE,
334  	.type           = PORT_SCIF,
335  	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
336  };
337  
338  static struct resource scif2_resources[] = {
339  	DEFINE_RES_MEM(0xffe20000, 0x100),
340  	DEFINE_RES_IRQ(evt2irq(0xc40)),
341  };
342  
343  static struct platform_device scif2_device = {
344  	.name		= "sh-sci",
345  	.id		= 2,
346  	.resource	= scif2_resources,
347  	.num_resources	= ARRAY_SIZE(scif2_resources),
348  	.dev		= {
349  		.platform_data	= &scif2_platform_data,
350  	},
351  };
352  
353  static struct plat_sci_port scif3_platform_data = {
354  	.sampling_rate	= 8,
355  	.type           = PORT_SCIFA,
356  };
357  
358  static struct resource scif3_resources[] = {
359  	DEFINE_RES_MEM(0xa4e30000, 0x100),
360  	DEFINE_RES_IRQ(evt2irq(0x900)),
361  };
362  
363  static struct platform_device scif3_device = {
364  	.name		= "sh-sci",
365  	.id		= 3,
366  	.resource	= scif3_resources,
367  	.num_resources	= ARRAY_SIZE(scif3_resources),
368  	.dev		= {
369  		.platform_data	= &scif3_platform_data,
370  	},
371  };
372  
373  static struct plat_sci_port scif4_platform_data = {
374  	.sampling_rate	= 8,
375  	.type           = PORT_SCIFA,
376  };
377  
378  static struct resource scif4_resources[] = {
379  	DEFINE_RES_MEM(0xa4e40000, 0x100),
380  	DEFINE_RES_IRQ(evt2irq(0xd00)),
381  };
382  
383  static struct platform_device scif4_device = {
384  	.name		= "sh-sci",
385  	.id		= 4,
386  	.resource	= scif4_resources,
387  	.num_resources	= ARRAY_SIZE(scif4_resources),
388  	.dev		= {
389  		.platform_data	= &scif4_platform_data,
390  	},
391  };
392  
393  static struct plat_sci_port scif5_platform_data = {
394  	.sampling_rate	= 8,
395  	.type           = PORT_SCIFA,
396  };
397  
398  static struct resource scif5_resources[] = {
399  	DEFINE_RES_MEM(0xa4e50000, 0x100),
400  	DEFINE_RES_IRQ(evt2irq(0xfa0)),
401  };
402  
403  static struct platform_device scif5_device = {
404  	.name		= "sh-sci",
405  	.id		= 5,
406  	.resource	= scif5_resources,
407  	.num_resources	= ARRAY_SIZE(scif5_resources),
408  	.dev		= {
409  		.platform_data	= &scif5_platform_data,
410  	},
411  };
412  
413  /* RTC */
414  static struct resource rtc_resources[] = {
415  	[0] = {
416  		.start	= 0xa465fec0,
417  		.end	= 0xa465fec0 + 0x58 - 1,
418  		.flags	= IORESOURCE_IO,
419  	},
420  	[1] = {
421  		/* Period IRQ */
422  		.start	= evt2irq(0xaa0),
423  		.flags	= IORESOURCE_IRQ,
424  	},
425  	[2] = {
426  		/* Carry IRQ */
427  		.start	= evt2irq(0xac0),
428  		.flags	= IORESOURCE_IRQ,
429  	},
430  	[3] = {
431  		/* Alarm IRQ */
432  		.start	= evt2irq(0xa80),
433  		.flags	= IORESOURCE_IRQ,
434  	},
435  };
436  
437  static struct platform_device rtc_device = {
438  	.name		= "sh-rtc",
439  	.id		= -1,
440  	.num_resources	= ARRAY_SIZE(rtc_resources),
441  	.resource	= rtc_resources,
442  };
443  
444  /* I2C0 */
445  static struct resource iic0_resources[] = {
446  	[0] = {
447  		.name	= "IIC0",
448  		.start  = 0x04470000,
449  		.end    = 0x04470018 - 1,
450  		.flags  = IORESOURCE_MEM,
451  	},
452  	[1] = {
453  		.start  = evt2irq(0xe00),
454  		.end    = evt2irq(0xe60),
455  		.flags  = IORESOURCE_IRQ,
456  	},
457  };
458  
459  static struct platform_device iic0_device = {
460  	.name           = "i2c-sh_mobile",
461  	.id             = 0, /* "i2c0" clock */
462  	.num_resources  = ARRAY_SIZE(iic0_resources),
463  	.resource       = iic0_resources,
464  };
465  
466  /* I2C1 */
467  static struct resource iic1_resources[] = {
468  	[0] = {
469  		.name	= "IIC1",
470  		.start  = 0x04750000,
471  		.end    = 0x04750018 - 1,
472  		.flags  = IORESOURCE_MEM,
473  	},
474  	[1] = {
475  		.start  = evt2irq(0xd80),
476  		.end    = evt2irq(0xde0),
477  		.flags  = IORESOURCE_IRQ,
478  	},
479  };
480  
481  static struct platform_device iic1_device = {
482  	.name           = "i2c-sh_mobile",
483  	.id             = 1, /* "i2c1" clock */
484  	.num_resources  = ARRAY_SIZE(iic1_resources),
485  	.resource       = iic1_resources,
486  };
487  
488  /* VPU */
489  static struct uio_info vpu_platform_data = {
490  	.name = "VPU5F",
491  	.version = "0",
492  	.irq = evt2irq(0x980),
493  };
494  
495  static struct resource vpu_resources[] = {
496  	[0] = {
497  		.name	= "VPU",
498  		.start	= 0xfe900000,
499  		.end	= 0xfe902807,
500  		.flags	= IORESOURCE_MEM,
501  	},
502  	[1] = {
503  		/* place holder for contiguous memory */
504  	},
505  };
506  
507  static struct platform_device vpu_device = {
508  	.name		= "uio_pdrv_genirq",
509  	.id		= 0,
510  	.dev = {
511  		.platform_data	= &vpu_platform_data,
512  	},
513  	.resource	= vpu_resources,
514  	.num_resources	= ARRAY_SIZE(vpu_resources),
515  };
516  
517  /* VEU0 */
518  static struct uio_info veu0_platform_data = {
519  	.name = "VEU3F0",
520  	.version = "0",
521  	.irq = evt2irq(0xc60),
522  };
523  
524  static struct resource veu0_resources[] = {
525  	[0] = {
526  		.name	= "VEU3F0",
527  		.start	= 0xfe920000,
528  		.end	= 0xfe9200cb,
529  		.flags	= IORESOURCE_MEM,
530  	},
531  	[1] = {
532  		/* place holder for contiguous memory */
533  	},
534  };
535  
536  static struct platform_device veu0_device = {
537  	.name		= "uio_pdrv_genirq",
538  	.id		= 1,
539  	.dev = {
540  		.platform_data	= &veu0_platform_data,
541  	},
542  	.resource	= veu0_resources,
543  	.num_resources	= ARRAY_SIZE(veu0_resources),
544  };
545  
546  /* VEU1 */
547  static struct uio_info veu1_platform_data = {
548  	.name = "VEU3F1",
549  	.version = "0",
550  	.irq = evt2irq(0x8c0),
551  };
552  
553  static struct resource veu1_resources[] = {
554  	[0] = {
555  		.name	= "VEU3F1",
556  		.start	= 0xfe924000,
557  		.end	= 0xfe9240cb,
558  		.flags	= IORESOURCE_MEM,
559  	},
560  	[1] = {
561  		/* place holder for contiguous memory */
562  	},
563  };
564  
565  static struct platform_device veu1_device = {
566  	.name		= "uio_pdrv_genirq",
567  	.id		= 2,
568  	.dev = {
569  		.platform_data	= &veu1_platform_data,
570  	},
571  	.resource	= veu1_resources,
572  	.num_resources	= ARRAY_SIZE(veu1_resources),
573  };
574  
575  /* BEU0 */
576  static struct uio_info beu0_platform_data = {
577  	.name = "BEU0",
578  	.version = "0",
579  	.irq = evt2irq(0x8A0),
580  };
581  
582  static struct resource beu0_resources[] = {
583  	[0] = {
584  		.name	= "BEU0",
585  		.start	= 0xfe930000,
586  		.end	= 0xfe933400,
587  		.flags	= IORESOURCE_MEM,
588  	},
589  	[1] = {
590  		/* place holder for contiguous memory */
591  	},
592  };
593  
594  static struct platform_device beu0_device = {
595  	.name		= "uio_pdrv_genirq",
596  	.id		= 6,
597  	.dev = {
598  		.platform_data	= &beu0_platform_data,
599  	},
600  	.resource	= beu0_resources,
601  	.num_resources	= ARRAY_SIZE(beu0_resources),
602  };
603  
604  /* BEU1 */
605  static struct uio_info beu1_platform_data = {
606  	.name = "BEU1",
607  	.version = "0",
608  	.irq = evt2irq(0xA00),
609  };
610  
611  static struct resource beu1_resources[] = {
612  	[0] = {
613  		.name	= "BEU1",
614  		.start	= 0xfe940000,
615  		.end	= 0xfe943400,
616  		.flags	= IORESOURCE_MEM,
617  	},
618  	[1] = {
619  		/* place holder for contiguous memory */
620  	},
621  };
622  
623  static struct platform_device beu1_device = {
624  	.name		= "uio_pdrv_genirq",
625  	.id		= 7,
626  	.dev = {
627  		.platform_data	= &beu1_platform_data,
628  	},
629  	.resource	= beu1_resources,
630  	.num_resources	= ARRAY_SIZE(beu1_resources),
631  };
632  
633  static struct sh_timer_config cmt_platform_data = {
634  	.channels_mask = 0x20,
635  };
636  
637  static struct resource cmt_resources[] = {
638  	DEFINE_RES_MEM(0x044a0000, 0x70),
639  	DEFINE_RES_IRQ(evt2irq(0xf00)),
640  };
641  
642  static struct platform_device cmt_device = {
643  	.name		= "sh-cmt-32",
644  	.id		= 0,
645  	.dev = {
646  		.platform_data	= &cmt_platform_data,
647  	},
648  	.resource	= cmt_resources,
649  	.num_resources	= ARRAY_SIZE(cmt_resources),
650  };
651  
652  static struct sh_timer_config tmu0_platform_data = {
653  	.channels_mask = 7,
654  };
655  
656  static struct resource tmu0_resources[] = {
657  	DEFINE_RES_MEM(0xffd80000, 0x2c),
658  	DEFINE_RES_IRQ(evt2irq(0x400)),
659  	DEFINE_RES_IRQ(evt2irq(0x420)),
660  	DEFINE_RES_IRQ(evt2irq(0x440)),
661  };
662  
663  static struct platform_device tmu0_device = {
664  	.name		= "sh-tmu",
665  	.id		= 0,
666  	.dev = {
667  		.platform_data	= &tmu0_platform_data,
668  	},
669  	.resource	= tmu0_resources,
670  	.num_resources	= ARRAY_SIZE(tmu0_resources),
671  };
672  
673  static struct sh_timer_config tmu1_platform_data = {
674  	.channels_mask = 7,
675  };
676  
677  static struct resource tmu1_resources[] = {
678  	DEFINE_RES_MEM(0xffd90000, 0x2c),
679  	DEFINE_RES_IRQ(evt2irq(0x920)),
680  	DEFINE_RES_IRQ(evt2irq(0x940)),
681  	DEFINE_RES_IRQ(evt2irq(0x960)),
682  };
683  
684  static struct platform_device tmu1_device = {
685  	.name		= "sh-tmu",
686  	.id		= 1,
687  	.dev = {
688  		.platform_data	= &tmu1_platform_data,
689  	},
690  	.resource	= tmu1_resources,
691  	.num_resources	= ARRAY_SIZE(tmu1_resources),
692  };
693  
694  /* JPU */
695  static struct uio_info jpu_platform_data = {
696  	.name = "JPU",
697  	.version = "0",
698  	.irq = evt2irq(0x560),
699  };
700  
701  static struct resource jpu_resources[] = {
702  	[0] = {
703  		.name	= "JPU",
704  		.start	= 0xfe980000,
705  		.end	= 0xfe9902d3,
706  		.flags	= IORESOURCE_MEM,
707  	},
708  	[1] = {
709  		/* place holder for contiguous memory */
710  	},
711  };
712  
713  static struct platform_device jpu_device = {
714  	.name		= "uio_pdrv_genirq",
715  	.id		= 3,
716  	.dev = {
717  		.platform_data	= &jpu_platform_data,
718  	},
719  	.resource	= jpu_resources,
720  	.num_resources	= ARRAY_SIZE(jpu_resources),
721  };
722  
723  /* SPU2DSP0 */
724  static struct uio_info spu0_platform_data = {
725  	.name = "SPU2DSP0",
726  	.version = "0",
727  	.irq = evt2irq(0xcc0),
728  };
729  
730  static struct resource spu0_resources[] = {
731  	[0] = {
732  		.name	= "SPU2DSP0",
733  		.start	= 0xFE200000,
734  		.end	= 0xFE2FFFFF,
735  		.flags	= IORESOURCE_MEM,
736  	},
737  	[1] = {
738  		/* place holder for contiguous memory */
739  	},
740  };
741  
742  static struct platform_device spu0_device = {
743  	.name		= "uio_pdrv_genirq",
744  	.id		= 4,
745  	.dev = {
746  		.platform_data	= &spu0_platform_data,
747  	},
748  	.resource	= spu0_resources,
749  	.num_resources	= ARRAY_SIZE(spu0_resources),
750  };
751  
752  /* SPU2DSP1 */
753  static struct uio_info spu1_platform_data = {
754  	.name = "SPU2DSP1",
755  	.version = "0",
756  	.irq = evt2irq(0xce0),
757  };
758  
759  static struct resource spu1_resources[] = {
760  	[0] = {
761  		.name	= "SPU2DSP1",
762  		.start	= 0xFE300000,
763  		.end	= 0xFE3FFFFF,
764  		.flags	= IORESOURCE_MEM,
765  	},
766  	[1] = {
767  		/* place holder for contiguous memory */
768  	},
769  };
770  
771  static struct platform_device spu1_device = {
772  	.name		= "uio_pdrv_genirq",
773  	.id		= 5,
774  	.dev = {
775  		.platform_data	= &spu1_platform_data,
776  	},
777  	.resource	= spu1_resources,
778  	.num_resources	= ARRAY_SIZE(spu1_resources),
779  };
780  
781  static struct platform_device *sh7724_devices[] __initdata = {
782  	&scif0_device,
783  	&scif1_device,
784  	&scif2_device,
785  	&scif3_device,
786  	&scif4_device,
787  	&scif5_device,
788  	&cmt_device,
789  	&tmu0_device,
790  	&tmu1_device,
791  	&dma0_device,
792  	&dma1_device,
793  	&rtc_device,
794  	&iic0_device,
795  	&iic1_device,
796  	&vpu_device,
797  	&veu0_device,
798  	&veu1_device,
799  	&beu0_device,
800  	&beu1_device,
801  	&jpu_device,
802  	&spu0_device,
803  	&spu1_device,
804  };
805  
sh7724_devices_setup(void)806  static int __init sh7724_devices_setup(void)
807  {
808  	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
809  	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
810  	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
811  	platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
812  	platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
813  	platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
814  
815  	return platform_add_devices(sh7724_devices,
816  				    ARRAY_SIZE(sh7724_devices));
817  }
818  arch_initcall(sh7724_devices_setup);
819  
820  static struct platform_device *sh7724_early_devices[] __initdata = {
821  	&scif0_device,
822  	&scif1_device,
823  	&scif2_device,
824  	&scif3_device,
825  	&scif4_device,
826  	&scif5_device,
827  	&cmt_device,
828  	&tmu0_device,
829  	&tmu1_device,
830  };
831  
plat_early_device_setup(void)832  void __init plat_early_device_setup(void)
833  {
834  	sh_early_platform_add_devices(sh7724_early_devices,
835  				   ARRAY_SIZE(sh7724_early_devices));
836  }
837  
838  #define RAMCR_CACHE_L2FC	0x0002
839  #define RAMCR_CACHE_L2E		0x0001
840  #define L2_CACHE_ENABLE		(RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
841  
l2_cache_init(void)842  void l2_cache_init(void)
843  {
844  	/* Enable L2 cache */
845  	__raw_writel(L2_CACHE_ENABLE, RAMCR);
846  }
847  
848  enum {
849  	UNUSED = 0,
850  	ENABLED,
851  	DISABLED,
852  
853  	/* interrupt sources */
854  	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
855  	HUDI,
856  	DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
857  	_2DG_TRI, _2DG_INI, _2DG_CEI,
858  	DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
859  	VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
860  	SCIFA3,
861  	VPU,
862  	TPU,
863  	CEU1,
864  	BEU1,
865  	USB0, USB1,
866  	ATAPI,
867  	RTC_ATI, RTC_PRI, RTC_CUI,
868  	DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
869  	DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
870  	KEYSC,
871  	SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
872  	VEU0,
873  	MSIOF_MSIOFI0, MSIOF_MSIOFI1,
874  	SPU_SPUI0, SPU_SPUI1,
875  	SCIFA4,
876  	ICB,
877  	ETHI,
878  	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
879  	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
880  	CMT,
881  	TSIF,
882  	FSI,
883  	SCIFA5,
884  	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
885  	IRDA,
886  	JPU,
887  	_2DDMAC,
888  	MMC_MMC2I, MMC_MMC3I,
889  	LCDC,
890  	TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
891  
892  	/* interrupt groups */
893  	DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
894  	DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
895  };
896  
897  static struct intc_vect vectors[] __initdata = {
898  	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
899  	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
900  	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
901  	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
902  
903  	INTC_VECT(DMAC1A_DEI0, 0x700),
904  	INTC_VECT(DMAC1A_DEI1, 0x720),
905  	INTC_VECT(DMAC1A_DEI2, 0x740),
906  	INTC_VECT(DMAC1A_DEI3, 0x760),
907  
908  	INTC_VECT(_2DG_TRI, 0x780),
909  	INTC_VECT(_2DG_INI, 0x7A0),
910  	INTC_VECT(_2DG_CEI, 0x7C0),
911  
912  	INTC_VECT(DMAC0A_DEI0, 0x800),
913  	INTC_VECT(DMAC0A_DEI1, 0x820),
914  	INTC_VECT(DMAC0A_DEI2, 0x840),
915  	INTC_VECT(DMAC0A_DEI3, 0x860),
916  
917  	INTC_VECT(VIO_CEU0, 0x880),
918  	INTC_VECT(VIO_BEU0, 0x8A0),
919  	INTC_VECT(VIO_VEU1, 0x8C0),
920  	INTC_VECT(VIO_VOU,  0x8E0),
921  
922  	INTC_VECT(SCIFA3, 0x900),
923  	INTC_VECT(VPU,    0x980),
924  	INTC_VECT(TPU,    0x9A0),
925  	INTC_VECT(CEU1,   0x9E0),
926  	INTC_VECT(BEU1,   0xA00),
927  	INTC_VECT(USB0,   0xA20),
928  	INTC_VECT(USB1,   0xA40),
929  	INTC_VECT(ATAPI,  0xA60),
930  
931  	INTC_VECT(RTC_ATI, 0xA80),
932  	INTC_VECT(RTC_PRI, 0xAA0),
933  	INTC_VECT(RTC_CUI, 0xAC0),
934  
935  	INTC_VECT(DMAC1B_DEI4, 0xB00),
936  	INTC_VECT(DMAC1B_DEI5, 0xB20),
937  	INTC_VECT(DMAC1B_DADERR, 0xB40),
938  
939  	INTC_VECT(DMAC0B_DEI4, 0xB80),
940  	INTC_VECT(DMAC0B_DEI5, 0xBA0),
941  	INTC_VECT(DMAC0B_DADERR, 0xBC0),
942  
943  	INTC_VECT(KEYSC,      0xBE0),
944  	INTC_VECT(SCIF_SCIF0, 0xC00),
945  	INTC_VECT(SCIF_SCIF1, 0xC20),
946  	INTC_VECT(SCIF_SCIF2, 0xC40),
947  	INTC_VECT(VEU0,       0xC60),
948  	INTC_VECT(MSIOF_MSIOFI0, 0xC80),
949  	INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
950  	INTC_VECT(SPU_SPUI0, 0xCC0),
951  	INTC_VECT(SPU_SPUI1, 0xCE0),
952  	INTC_VECT(SCIFA4,    0xD00),
953  
954  	INTC_VECT(ICB,  0xD20),
955  	INTC_VECT(ETHI, 0xD60),
956  
957  	INTC_VECT(I2C1_ALI, 0xD80),
958  	INTC_VECT(I2C1_TACKI, 0xDA0),
959  	INTC_VECT(I2C1_WAITI, 0xDC0),
960  	INTC_VECT(I2C1_DTEI, 0xDE0),
961  
962  	INTC_VECT(I2C0_ALI, 0xE00),
963  	INTC_VECT(I2C0_TACKI, 0xE20),
964  	INTC_VECT(I2C0_WAITI, 0xE40),
965  	INTC_VECT(I2C0_DTEI, 0xE60),
966  
967  	INTC_VECT(SDHI0, 0xE80),
968  	INTC_VECT(SDHI0, 0xEA0),
969  	INTC_VECT(SDHI0, 0xEC0),
970  	INTC_VECT(SDHI0, 0xEE0),
971  
972  	INTC_VECT(CMT,    0xF00),
973  	INTC_VECT(TSIF,   0xF20),
974  	INTC_VECT(FSI,    0xF80),
975  	INTC_VECT(SCIFA5, 0xFA0),
976  
977  	INTC_VECT(TMU0_TUNI0, 0x400),
978  	INTC_VECT(TMU0_TUNI1, 0x420),
979  	INTC_VECT(TMU0_TUNI2, 0x440),
980  
981  	INTC_VECT(IRDA,    0x480),
982  
983  	INTC_VECT(SDHI1, 0x4E0),
984  	INTC_VECT(SDHI1, 0x500),
985  	INTC_VECT(SDHI1, 0x520),
986  
987  	INTC_VECT(JPU, 0x560),
988  	INTC_VECT(_2DDMAC, 0x4A0),
989  
990  	INTC_VECT(MMC_MMC2I, 0x5A0),
991  	INTC_VECT(MMC_MMC3I, 0x5C0),
992  
993  	INTC_VECT(LCDC, 0xF40),
994  
995  	INTC_VECT(TMU1_TUNI0, 0x920),
996  	INTC_VECT(TMU1_TUNI1, 0x940),
997  	INTC_VECT(TMU1_TUNI2, 0x960),
998  };
999  
1000  static struct intc_group groups[] __initdata = {
1001  	INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1002  	INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1003  	INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1004  	INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1005  	INTC_GROUP(USB, USB0, USB1),
1006  	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1007  	INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1008  	INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1009  	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1010  	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1011  	INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1012  	INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1013  };
1014  
1015  static struct intc_mask_reg mask_registers[] __initdata = {
1016  	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1017  	  { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1018  	    0, ENABLED, ENABLED, ENABLED } },
1019  	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1020  	  { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1021  	    DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1022  	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1023  	  { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1024  	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1025  	  { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1026  	    SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1027  	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1028  	  { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1029  	    JPU, 0, 0, LCDC } },
1030  	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1031  	  { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1032  	    VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1033  	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1034  	  { 0, 0, ICB, SCIFA4,
1035  	    CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1036  	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1037  	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1038  	    I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1039  	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1040  	  { DISABLED, ENABLED, ENABLED, ENABLED,
1041  	    0, 0, SCIFA5, FSI } },
1042  	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1043  	  { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1044  	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1045  	  { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1046  	    0, RTC_CUI, RTC_PRI, RTC_ATI } },
1047  	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1048  	  { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1049  	    0, TPU, 0, TSIF } },
1050  	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1051  	  { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1052  	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1053  	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1054  };
1055  
1056  static struct intc_prio_reg prio_registers[] __initdata = {
1057  	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1058  					     TMU0_TUNI2, IRDA } },
1059  	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1060  	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1061  					     TMU1_TUNI2, SPU } },
1062  	{ 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1063  	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1064  	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1065  	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1066  					     SCIF_SCIF2, VEU0 } },
1067  	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1068  					     I2C1, I2C0 } },
1069  	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1070  	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1071  	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1072  	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1073  	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
1074  	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1075  };
1076  
1077  static struct intc_sense_reg sense_registers[] __initdata = {
1078  	{ 0xa414001c, 16, 2, /* ICR1 */
1079  	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1080  };
1081  
1082  static struct intc_mask_reg ack_registers[] __initdata = {
1083  	{ 0xa4140024, 0, 8, /* INTREQ00 */
1084  	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1085  };
1086  
1087  static struct intc_desc intc_desc __initdata = {
1088  	.name = "sh7724",
1089  	.force_enable = ENABLED,
1090  	.force_disable = DISABLED,
1091  	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
1092  			   prio_registers, sense_registers, ack_registers),
1093  };
1094  
plat_irq_setup(void)1095  void __init plat_irq_setup(void)
1096  {
1097  	register_intc_controller(&intc_desc);
1098  }
1099  
1100  static struct {
1101  	/* BSC */
1102  	unsigned long mmselr;
1103  	unsigned long cs0bcr;
1104  	unsigned long cs4bcr;
1105  	unsigned long cs5abcr;
1106  	unsigned long cs5bbcr;
1107  	unsigned long cs6abcr;
1108  	unsigned long cs6bbcr;
1109  	unsigned long cs4wcr;
1110  	unsigned long cs5awcr;
1111  	unsigned long cs5bwcr;
1112  	unsigned long cs6awcr;
1113  	unsigned long cs6bwcr;
1114  	/* INTC */
1115  	unsigned short ipra;
1116  	unsigned short iprb;
1117  	unsigned short iprc;
1118  	unsigned short iprd;
1119  	unsigned short ipre;
1120  	unsigned short iprf;
1121  	unsigned short iprg;
1122  	unsigned short iprh;
1123  	unsigned short ipri;
1124  	unsigned short iprj;
1125  	unsigned short iprk;
1126  	unsigned short iprl;
1127  	unsigned char imr0;
1128  	unsigned char imr1;
1129  	unsigned char imr2;
1130  	unsigned char imr3;
1131  	unsigned char imr4;
1132  	unsigned char imr5;
1133  	unsigned char imr6;
1134  	unsigned char imr7;
1135  	unsigned char imr8;
1136  	unsigned char imr9;
1137  	unsigned char imr10;
1138  	unsigned char imr11;
1139  	unsigned char imr12;
1140  	/* RWDT */
1141  	unsigned short rwtcnt;
1142  	unsigned short rwtcsr;
1143  	/* CPG */
1144  	unsigned long irdaclk;
1145  	unsigned long spuclk;
1146  } sh7724_rstandby_state;
1147  
sh7724_pre_sleep_notifier_call(struct notifier_block * nb,unsigned long flags,void * unused)1148  static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1149  					  unsigned long flags, void *unused)
1150  {
1151  	if (!(flags & SUSP_SH_RSTANDBY))
1152  		return NOTIFY_DONE;
1153  
1154  	/* BCR */
1155  	sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1156  	sh7724_rstandby_state.mmselr |= 0xa5a50000;
1157  	sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1158  	sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1159  	sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1160  	sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1161  	sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1162  	sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1163  	sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1164  	sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1165  	sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1166  	sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1167  	sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1168  
1169  	/* INTC */
1170  	sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1171  	sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1172  	sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1173  	sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1174  	sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1175  	sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1176  	sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1177  	sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1178  	sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1179  	sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1180  	sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1181  	sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1182  	sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1183  	sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1184  	sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1185  	sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1186  	sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1187  	sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1188  	sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1189  	sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1190  	sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1191  	sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1192  	sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1193  	sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1194  	sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1195  
1196  	/* RWDT */
1197  	sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1198  	sh7724_rstandby_state.rwtcnt |= 0x5a00;
1199  	sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1200  	sh7724_rstandby_state.rwtcsr |= 0xa500;
1201  	__raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1202  
1203  	/* CPG */
1204  	sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1205  	sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1206  
1207  	return NOTIFY_DONE;
1208  }
1209  
sh7724_post_sleep_notifier_call(struct notifier_block * nb,unsigned long flags,void * unused)1210  static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1211  					   unsigned long flags, void *unused)
1212  {
1213  	if (!(flags & SUSP_SH_RSTANDBY))
1214  		return NOTIFY_DONE;
1215  
1216  	/* BCR */
1217  	__raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1218  	__raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1219  	__raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1220  	__raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1221  	__raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1222  	__raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1223  	__raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1224  	__raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1225  	__raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1226  	__raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1227  	__raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1228  	__raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1229  
1230  	/* INTC */
1231  	__raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1232  	__raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1233  	__raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1234  	__raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1235  	__raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1236  	__raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1237  	__raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1238  	__raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1239  	__raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1240  	__raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1241  	__raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1242  	__raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1243  	__raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1244  	__raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1245  	__raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1246  	__raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1247  	__raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1248  	__raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1249  	__raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1250  	__raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1251  	__raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1252  	__raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1253  	__raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1254  	__raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1255  	__raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1256  
1257  	/* RWDT */
1258  	__raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1259  	__raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1260  
1261  	/* CPG */
1262  	__raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1263  	__raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1264  
1265  	return NOTIFY_DONE;
1266  }
1267  
1268  static struct notifier_block sh7724_pre_sleep_notifier = {
1269  	.notifier_call = sh7724_pre_sleep_notifier_call,
1270  	.priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1271  };
1272  
1273  static struct notifier_block sh7724_post_sleep_notifier = {
1274  	.notifier_call = sh7724_post_sleep_notifier_call,
1275  	.priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1276  };
1277  
sh7724_sleep_setup(void)1278  static int __init sh7724_sleep_setup(void)
1279  {
1280  	atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1281  				       &sh7724_pre_sleep_notifier);
1282  
1283  	atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1284  				       &sh7724_post_sleep_notifier);
1285  	return 0;
1286  }
1287  arch_initcall(sh7724_sleep_setup);
1288  
1289