1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
6 */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/mxc_hdmi.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/sata.h>
18 #include <asm/mach-imx/spi.h>
19 #include <asm/mach-imx/video.h>
20 #include <asm/io.h>
21 #include <asm/setup.h>
22 #include <dm.h>
23 #include <dm/platform_data/serial_mxc.h>
24 #include <environment.h>
25 #include <hwconfig.h>
26 #include <i2c.h>
27 #include <fdt_support.h>
28 #include <fsl_esdhc.h>
29 #include <jffs2/load_kernel.h>
30 #include <linux/ctype.h>
31 #include <miiphy.h>
32 #include <mtd_node.h>
33 #include <netdev.h>
34 #include <pci.h>
35 #include <power/pmic.h>
36 #include <power/ltc3676_pmic.h>
37 #include <power/pfuze100_pmic.h>
38 #include <fdt_support.h>
39 #include <jffs2/load_kernel.h>
40 #include <spi_flash.h>
41
42 #include "gsc.h"
43 #include "common.h"
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47
48 /*
49 * EEPROM board info struct populated by read_eeprom so that we only have to
50 * read it once.
51 */
52 struct ventana_board_info ventana_info;
53
54 static int board_type;
55
56 /* ENET */
57 static iomux_v3_cfg_t const enet_pads[] = {
58 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
59 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
61 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
63 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
66 MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
68 MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
75 MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 /* PHY nRST */
77 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
78 };
79
80 #ifdef CONFIG_CMD_NAND
81 static iomux_v3_cfg_t const nfc_pads[] = {
82 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
83 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
86 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 };
98
setup_gpmi_nand(void)99 static void setup_gpmi_nand(void)
100 {
101 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
102
103 /* config gpmi nand iomux */
104 SETUP_IOMUX_PADS(nfc_pads);
105
106 /* config gpmi and bch clock to 100 MHz */
107 clrsetbits_le32(&mxc_ccm->cs2cdr,
108 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
109 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
110 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
111 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
112 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
113 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
114
115 /* enable gpmi and bch clock gating */
116 setbits_le32(&mxc_ccm->CCGR4,
117 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
118 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
119 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
120 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
121 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
122
123 /* enable apbh clock gating */
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
125 }
126 #endif
127
setup_iomux_enet(int gpio)128 static void setup_iomux_enet(int gpio)
129 {
130 SETUP_IOMUX_PADS(enet_pads);
131
132 /* toggle PHY_RST# */
133 gpio_request(gpio, "phy_rst#");
134 gpio_direction_output(gpio, 0);
135 mdelay(10);
136 gpio_set_value(gpio, 1);
137 mdelay(100);
138 }
139
140 #ifdef CONFIG_USB_EHCI_MX6
141 static iomux_v3_cfg_t const usb_pads[] = {
142 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
143 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
144 /* OTG PWR */
145 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
146 };
147
board_ehci_hcd_init(int port)148 int board_ehci_hcd_init(int port)
149 {
150 int gpio;
151
152 SETUP_IOMUX_PADS(usb_pads);
153
154 /* Reset USB HUB */
155 switch (board_type) {
156 case GW53xx:
157 case GW552x:
158 case GW5906:
159 gpio = (IMX_GPIO_NR(1, 9));
160 break;
161 case GW54proto:
162 case GW54xx:
163 gpio = (IMX_GPIO_NR(1, 16));
164 break;
165 default:
166 return 0;
167 }
168
169 /* request and toggle hub rst */
170 gpio_request(gpio, "usb_hub_rst#");
171 gpio_direction_output(gpio, 0);
172 mdelay(2);
173 gpio_set_value(gpio, 1);
174
175 return 0;
176 }
177
board_ehci_power(int port,int on)178 int board_ehci_power(int port, int on)
179 {
180 /* enable OTG VBUS */
181 if (!port && board_type < GW_UNKNOWN) {
182 if (gpio_cfg[board_type].otgpwr_en)
183 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
184 }
185 return 0;
186 }
187 #endif /* CONFIG_USB_EHCI_MX6 */
188
189 #ifdef CONFIG_MXC_SPI
190 iomux_v3_cfg_t const ecspi1_pads[] = {
191 /* SS1 */
192 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
195 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
196 };
197
board_spi_cs_gpio(unsigned bus,unsigned cs)198 int board_spi_cs_gpio(unsigned bus, unsigned cs)
199 {
200 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
201 }
202
setup_spi(void)203 static void setup_spi(void)
204 {
205 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
206 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
207 SETUP_IOMUX_PADS(ecspi1_pads);
208 }
209 #endif
210
211 /* configure eth0 PHY board-specific LED behavior */
board_phy_config(struct phy_device * phydev)212 int board_phy_config(struct phy_device *phydev)
213 {
214 unsigned short val;
215
216 /* Marvel 88E1510 */
217 if (phydev->phy_id == 0x1410dd1) {
218 /*
219 * Page 3, Register 16: LED[2:0] Function Control Register
220 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
221 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
222 */
223 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
224 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
225 val &= 0xff00;
226 val |= 0x0017;
227 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
228 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
229 }
230
231 /* TI DP83867 */
232 else if (phydev->phy_id == 0x2000a231) {
233 /* configure register 0x170 for ref CLKOUT */
234 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
235 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
236 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
237 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
238 val &= ~0x1f00;
239 val |= 0x0b00; /* chD tx clock*/
240 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
241 }
242
243 if (phydev->drv->config)
244 phydev->drv->config(phydev);
245
246 return 0;
247 }
248
249 #ifdef CONFIG_MV88E61XX_SWITCH
mv88e61xx_hw_reset(struct phy_device * phydev)250 int mv88e61xx_hw_reset(struct phy_device *phydev)
251 {
252 struct mii_dev *bus = phydev->bus;
253
254 /* GPIO[0] output, CLK125 */
255 debug("enabling RGMII_REFCLK\n");
256 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
257 0x1a /*MV_SCRATCH_MISC*/,
258 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
259 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
260 0x1a /*MV_SCRATCH_MISC*/,
261 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
262
263 /* RGMII delay - Physical Control register bit[15:14] */
264 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
265 /* forced 1000mbps full-duplex link */
266 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
267 phydev->autoneg = AUTONEG_DISABLE;
268 phydev->speed = SPEED_1000;
269 phydev->duplex = DUPLEX_FULL;
270
271 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
272 bus->write(bus, 0x10, 0, 0x16, 0x8088);
273 bus->write(bus, 0x11, 0, 0x16, 0x8088);
274 bus->write(bus, 0x12, 0, 0x16, 0x8088);
275 bus->write(bus, 0x13, 0, 0x16, 0x8088);
276
277 return 0;
278 }
279 #endif // CONFIG_MV88E61XX_SWITCH
280
board_eth_init(bd_t * bis)281 int board_eth_init(bd_t *bis)
282 {
283 #ifdef CONFIG_FEC_MXC
284 struct ventana_board_info *info = &ventana_info;
285
286 if (test_bit(EECONFIG_ETH0, info->config)) {
287 setup_iomux_enet(GP_PHY_RST);
288 cpu_eth_init(bis);
289 }
290 #endif
291
292 #ifdef CONFIG_E1000
293 e1000_initialize(bis);
294 #endif
295
296 #ifdef CONFIG_CI_UDC
297 /* For otg ethernet*/
298 usb_eth_initialize(bis);
299 #endif
300
301 /* default to the first detected enet dev */
302 if (!env_get("ethprime")) {
303 struct eth_device *dev = eth_get_dev_by_index(0);
304 if (dev) {
305 env_set("ethprime", dev->name);
306 printf("set ethprime to %s\n", env_get("ethprime"));
307 }
308 }
309
310 return 0;
311 }
312
313 #if defined(CONFIG_VIDEO_IPUV3)
314
enable_hdmi(struct display_info_t const * dev)315 static void enable_hdmi(struct display_info_t const *dev)
316 {
317 imx_enable_hdmi_phy();
318 }
319
detect_i2c(struct display_info_t const * dev)320 static int detect_i2c(struct display_info_t const *dev)
321 {
322 return i2c_set_bus_num(dev->bus) == 0 &&
323 i2c_probe(dev->addr) == 0;
324 }
325
enable_lvds(struct display_info_t const * dev)326 static void enable_lvds(struct display_info_t const *dev)
327 {
328 struct iomuxc *iomux = (struct iomuxc *)
329 IOMUXC_BASE_ADDR;
330
331 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
332 u32 reg = readl(&iomux->gpr[2]);
333 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
334 writel(reg, &iomux->gpr[2]);
335
336 /* Enable Backlight */
337 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
338 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
339 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
340 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
341 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
342 }
343
344 struct display_info_t const displays[] = {{
345 /* HDMI Output */
346 .bus = -1,
347 .addr = 0,
348 .pixfmt = IPU_PIX_FMT_RGB24,
349 .detect = detect_hdmi,
350 .enable = enable_hdmi,
351 .mode = {
352 .name = "HDMI",
353 .refresh = 60,
354 .xres = 1024,
355 .yres = 768,
356 .pixclock = 15385,
357 .left_margin = 220,
358 .right_margin = 40,
359 .upper_margin = 21,
360 .lower_margin = 7,
361 .hsync_len = 60,
362 .vsync_len = 10,
363 .sync = FB_SYNC_EXT,
364 .vmode = FB_VMODE_NONINTERLACED
365 } }, {
366 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
367 .bus = 2,
368 .addr = 0x4,
369 .pixfmt = IPU_PIX_FMT_LVDS666,
370 .detect = detect_i2c,
371 .enable = enable_lvds,
372 .mode = {
373 .name = "Hannstar-XGA",
374 .refresh = 60,
375 .xres = 1024,
376 .yres = 768,
377 .pixclock = 15385,
378 .left_margin = 220,
379 .right_margin = 40,
380 .upper_margin = 21,
381 .lower_margin = 7,
382 .hsync_len = 60,
383 .vsync_len = 10,
384 .sync = FB_SYNC_EXT,
385 .vmode = FB_VMODE_NONINTERLACED
386 } }, {
387 /* DLC700JMG-T-4 */
388 .bus = 2,
389 .addr = 0x38,
390 .detect = NULL,
391 .enable = enable_lvds,
392 .pixfmt = IPU_PIX_FMT_LVDS666,
393 .mode = {
394 .name = "DLC700JMGT4",
395 .refresh = 60,
396 .xres = 1024, /* 1024x600active pixels */
397 .yres = 600,
398 .pixclock = 15385, /* 64MHz */
399 .left_margin = 220,
400 .right_margin = 40,
401 .upper_margin = 21,
402 .lower_margin = 7,
403 .hsync_len = 60,
404 .vsync_len = 10,
405 .sync = FB_SYNC_EXT,
406 .vmode = FB_VMODE_NONINTERLACED
407 } }, {
408 /* DLC800FIG-T-3 */
409 .bus = 2,
410 .addr = 0x14,
411 .detect = NULL,
412 .enable = enable_lvds,
413 .pixfmt = IPU_PIX_FMT_LVDS666,
414 .mode = {
415 .name = "DLC800FIGT3",
416 .refresh = 60,
417 .xres = 1024, /* 1024x768 active pixels */
418 .yres = 768,
419 .pixclock = 15385, /* 64MHz */
420 .left_margin = 220,
421 .right_margin = 40,
422 .upper_margin = 21,
423 .lower_margin = 7,
424 .hsync_len = 60,
425 .vsync_len = 10,
426 .sync = FB_SYNC_EXT,
427 .vmode = FB_VMODE_NONINTERLACED
428 } }, {
429 .bus = 2,
430 .addr = 0x5d,
431 .detect = detect_i2c,
432 .enable = enable_lvds,
433 .pixfmt = IPU_PIX_FMT_LVDS666,
434 .mode = {
435 .name = "Z101WX01",
436 .refresh = 60,
437 .xres = 1280,
438 .yres = 800,
439 .pixclock = 15385, /* 64MHz */
440 .left_margin = 220,
441 .right_margin = 40,
442 .upper_margin = 21,
443 .lower_margin = 7,
444 .hsync_len = 60,
445 .vsync_len = 10,
446 .sync = FB_SYNC_EXT,
447 .vmode = FB_VMODE_NONINTERLACED
448 }
449 },
450 };
451 size_t display_count = ARRAY_SIZE(displays);
452
setup_display(void)453 static void setup_display(void)
454 {
455 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
456 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
457 int reg;
458
459 enable_ipu_clock();
460 imx_setup_hdmi();
461 /* Turn on LDB0,IPU,IPU DI0 clocks */
462 reg = __raw_readl(&mxc_ccm->CCGR3);
463 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
464 writel(reg, &mxc_ccm->CCGR3);
465
466 /* set LDB0, LDB1 clk select to 011/011 */
467 reg = readl(&mxc_ccm->cs2cdr);
468 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
469 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
470 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
471 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
472 writel(reg, &mxc_ccm->cs2cdr);
473
474 reg = readl(&mxc_ccm->cscmr2);
475 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
476 writel(reg, &mxc_ccm->cscmr2);
477
478 reg = readl(&mxc_ccm->chsccdr);
479 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
480 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
481 writel(reg, &mxc_ccm->chsccdr);
482
483 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
484 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
485 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
486 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
487 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
488 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
489 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
490 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
491 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
492 writel(reg, &iomux->gpr[2]);
493
494 reg = readl(&iomux->gpr[3]);
495 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
496 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
497 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
498 writel(reg, &iomux->gpr[3]);
499
500 /* LVDS Backlight GPIO on LVDS connector - output low */
501 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
502 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
503 }
504 #endif /* CONFIG_VIDEO_IPUV3 */
505
506 /* setup board specific PMIC */
power_init_board(void)507 int power_init_board(void)
508 {
509 setup_pmic();
510 return 0;
511 }
512
513 #if defined(CONFIG_CMD_PCI)
imx6_pcie_toggle_reset(void)514 int imx6_pcie_toggle_reset(void)
515 {
516 if (board_type < GW_UNKNOWN) {
517 uint pin = gpio_cfg[board_type].pcie_rst;
518 gpio_request(pin, "pci_rst#");
519 gpio_direction_output(pin, 0);
520 mdelay(50);
521 gpio_direction_output(pin, 1);
522 }
523 return 0;
524 }
525
526 /*
527 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
528 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
529 * properly and assert reset for 100ms.
530 */
531 #define MAX_PCI_DEVS 32
532 struct pci_dev {
533 pci_dev_t devfn;
534 unsigned short vendor;
535 unsigned short device;
536 unsigned short class;
537 unsigned short busno; /* subbordinate busno */
538 struct pci_dev *ppar;
539 };
540 struct pci_dev pci_devs[MAX_PCI_DEVS];
541 int pci_devno;
542 int pci_bridgeno;
543
board_pci_fixup_dev(struct pci_controller * hose,pci_dev_t dev,unsigned short vendor,unsigned short device,unsigned short class)544 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
545 unsigned short vendor, unsigned short device,
546 unsigned short class)
547 {
548 int i;
549 u32 dw;
550 struct pci_dev *pdev = &pci_devs[pci_devno++];
551
552 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
553 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
554
555 /* store array of devs for later use in device-tree fixup */
556 pdev->devfn = dev;
557 pdev->vendor = vendor;
558 pdev->device = device;
559 pdev->class = class;
560 pdev->ppar = NULL;
561 if (class == PCI_CLASS_BRIDGE_PCI)
562 pdev->busno = ++pci_bridgeno;
563 else
564 pdev->busno = 0;
565
566 /* fixup RC - it should be 00:00.0 not 00:01.0 */
567 if (PCI_BUS(dev) == 0)
568 pdev->devfn = 0;
569
570 /* find dev's parent */
571 for (i = 0; i < pci_devno; i++) {
572 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
573 pdev->ppar = &pci_devs[i];
574 break;
575 }
576 }
577
578 /* assert downstream PERST# */
579 if (vendor == PCI_VENDOR_ID_PLX &&
580 (device & 0xfff0) == 0x8600 &&
581 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
582 debug("configuring PLX 860X downstream PERST#\n");
583 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
584 dw |= 0xaaa8; /* GPIO1-7 outputs */
585 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
586
587 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
588 dw |= 0xfe; /* GPIO1-7 output high */
589 pci_hose_write_config_dword(hose, dev, 0x644, dw);
590
591 mdelay(100);
592 }
593 }
594 #endif /* CONFIG_CMD_PCI */
595
596 #ifdef CONFIG_SERIAL_TAG
597 /*
598 * called when setting up ATAGS before booting kernel
599 * populate serialnum from the following (in order of priority):
600 * serial# env var
601 * eeprom
602 */
get_board_serial(struct tag_serialnr * serialnr)603 void get_board_serial(struct tag_serialnr *serialnr)
604 {
605 char *serial = env_get("serial#");
606
607 if (serial) {
608 serialnr->high = 0;
609 serialnr->low = simple_strtoul(serial, NULL, 10);
610 } else if (ventana_info.model[0]) {
611 serialnr->high = 0;
612 serialnr->low = ventana_info.serial;
613 } else {
614 serialnr->high = 0;
615 serialnr->low = 0;
616 }
617 }
618 #endif
619
620 /*
621 * Board Support
622 */
623
board_early_init_f(void)624 int board_early_init_f(void)
625 {
626 setup_iomux_uart();
627
628 #if defined(CONFIG_VIDEO_IPUV3)
629 setup_display();
630 #endif
631 return 0;
632 }
633
dram_init(void)634 int dram_init(void)
635 {
636 gd->ram_size = imx_ddr_size();
637 return 0;
638 }
639
board_init(void)640 int board_init(void)
641 {
642 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
643
644 clrsetbits_le32(&iomuxc_regs->gpr[1],
645 IOMUXC_GPR1_OTG_ID_MASK,
646 IOMUXC_GPR1_OTG_ID_GPIO1);
647
648 /* address of linux boot parameters */
649 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
650
651 /* read Gateworks EEPROM into global struct (used later) */
652 setup_ventana_i2c(0);
653 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
654
655 #ifdef CONFIG_CMD_NAND
656 if (gpio_cfg[board_type].nand)
657 setup_gpmi_nand();
658 #endif
659 #ifdef CONFIG_MXC_SPI
660 setup_spi();
661 #endif
662 setup_ventana_i2c(1);
663 setup_ventana_i2c(2);
664
665 #ifdef CONFIG_SATA
666 setup_sata();
667 #endif
668
669 setup_iomux_gpio(board_type, &ventana_info);
670
671 return 0;
672 }
673
674 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
675 /*
676 * called during late init (after relocation and after board_init())
677 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
678 * EEPROM read.
679 */
checkboard(void)680 int checkboard(void)
681 {
682 struct ventana_board_info *info = &ventana_info;
683 unsigned char buf[4];
684 const char *p;
685 int quiet; /* Quiet or minimal output mode */
686
687 quiet = 0;
688 p = env_get("quiet");
689 if (p)
690 quiet = simple_strtol(p, NULL, 10);
691 else
692 env_set("quiet", "0");
693
694 puts("\nGateworks Corporation Copyright 2014\n");
695 if (info->model[0]) {
696 printf("Model: %s\n", info->model);
697 printf("MFGDate: %02x-%02x-%02x%02x\n",
698 info->mfgdate[0], info->mfgdate[1],
699 info->mfgdate[2], info->mfgdate[3]);
700 printf("Serial:%d\n", info->serial);
701 } else {
702 puts("Invalid EEPROM - board will not function fully\n");
703 }
704 if (quiet)
705 return 0;
706
707 /* Display GSC firmware revision/CRC/status */
708 gsc_info(0);
709
710 /* Display RTC */
711 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
712 printf("RTC: %d\n",
713 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
714 }
715
716 return 0;
717 }
718 #endif
719
720 #ifdef CONFIG_CMD_BMODE
721 /*
722 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
723 * see Table 8-11 and Table 5-9
724 * BOOT_CFG1[7] = 1 (boot from NAND)
725 * BOOT_CFG1[5] = 0 - raw NAND
726 * BOOT_CFG1[4] = 0 - default pad settings
727 * BOOT_CFG1[3:2] = 00 - devices = 1
728 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
729 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
730 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
731 * BOOT_CFG2[0] = 0 - Reset time 12ms
732 */
733 static const struct boot_mode board_boot_modes[] = {
734 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
735 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
736 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
737 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
738 { NULL, 0 },
739 };
740 #endif
741
742 /* late init */
misc_init_r(void)743 int misc_init_r(void)
744 {
745 struct ventana_board_info *info = &ventana_info;
746 char buf[256];
747 int i;
748
749 /* set env vars based on EEPROM data */
750 if (ventana_info.model[0]) {
751 char str[16], fdt[36];
752 char *p;
753 const char *cputype = "";
754
755 /*
756 * FDT name will be prefixed with CPU type. Three versions
757 * will be created each increasingly generic and bootloader
758 * env scripts will try loading each from most specific to
759 * least.
760 */
761 if (is_cpu_type(MXC_CPU_MX6Q) ||
762 is_cpu_type(MXC_CPU_MX6D))
763 cputype = "imx6q";
764 else if (is_cpu_type(MXC_CPU_MX6DL) ||
765 is_cpu_type(MXC_CPU_MX6SOLO))
766 cputype = "imx6dl";
767 env_set("soctype", cputype);
768 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
769 env_set("flash_layout", "large");
770 else
771 env_set("flash_layout", "normal");
772 memset(str, 0, sizeof(str));
773 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
774 str[i] = tolower(info->model[i]);
775 env_set("model", str);
776 if (!env_get("fdt_file")) {
777 sprintf(fdt, "%s-%s.dtb", cputype, str);
778 env_set("fdt_file", fdt);
779 }
780 p = strchr(str, '-');
781 if (p) {
782 *p++ = 0;
783
784 env_set("model_base", str);
785 sprintf(fdt, "%s-%s.dtb", cputype, str);
786 env_set("fdt_file1", fdt);
787 if (board_type != GW551x &&
788 board_type != GW552x &&
789 board_type != GW553x &&
790 board_type != GW560x)
791 str[4] = 'x';
792 str[5] = 'x';
793 str[6] = 0;
794 sprintf(fdt, "%s-%s.dtb", cputype, str);
795 env_set("fdt_file2", fdt);
796 }
797
798 /* initialize env from EEPROM */
799 if (test_bit(EECONFIG_ETH0, info->config) &&
800 !env_get("ethaddr")) {
801 eth_env_set_enetaddr("ethaddr", info->mac0);
802 }
803 if (test_bit(EECONFIG_ETH1, info->config) &&
804 !env_get("eth1addr")) {
805 eth_env_set_enetaddr("eth1addr", info->mac1);
806 }
807
808 /* board serial-number */
809 sprintf(str, "%6d", info->serial);
810 env_set("serial#", str);
811
812 /* memory MB */
813 sprintf(str, "%d", (int) (gd->ram_size >> 20));
814 env_set("mem_mb", str);
815 }
816
817 /* Set a non-initialized hwconfig based on board configuration */
818 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
819 buf[0] = 0;
820 if (gpio_cfg[board_type].rs232_en)
821 strcat(buf, "rs232;");
822 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
823 char buf1[32];
824 sprintf(buf1, "dio%d:mode=gpio;", i);
825 if (strlen(buf) + strlen(buf1) < sizeof(buf))
826 strcat(buf, buf1);
827 }
828 env_set("hwconfig", buf);
829 }
830
831 /* setup baseboard specific GPIO based on board and env */
832 setup_board_gpio(board_type, info);
833
834 #ifdef CONFIG_CMD_BMODE
835 add_board_boot_modes(board_boot_modes);
836 #endif
837
838 /* disable boot watchdog */
839 gsc_boot_wd_disable();
840
841 return 0;
842 }
843
844 #ifdef CONFIG_OF_BOARD_SETUP
845
ft_sethdmiinfmt(void * blob,char * mode)846 static int ft_sethdmiinfmt(void *blob, char *mode)
847 {
848 int off;
849
850 if (!mode)
851 return -EINVAL;
852
853 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
854 if (off < 0)
855 return off;
856
857 if (0 == strcasecmp(mode, "yuv422bt656")) {
858 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
859 0x00, 0x00, 0x00 };
860 mode = "422_ccir";
861 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
862 fdt_setprop_u32(blob, off, "vidout_trc", 1);
863 fdt_setprop_u32(blob, off, "vidout_blc", 1);
864 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
865 printf(" set HDMI input mode to %s\n", mode);
866 } else if (0 == strcasecmp(mode, "yuv422smp")) {
867 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
868 0x82, 0x81, 0x00 };
869 mode = "422_smp";
870 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
871 fdt_setprop_u32(blob, off, "vidout_trc", 0);
872 fdt_setprop_u32(blob, off, "vidout_blc", 0);
873 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
874 printf(" set HDMI input mode to %s\n", mode);
875 } else {
876 return -EINVAL;
877 }
878
879 return 0;
880 }
881
882 #if defined(CONFIG_CMD_PCI)
883 #define PCI_ID(x) ( \
884 (PCI_BUS(x->devfn)<<16)| \
885 (PCI_DEV(x->devfn)<<11)| \
886 (PCI_FUNC(x->devfn)<<8) \
887 )
fdt_add_pci_node(void * blob,int par,struct pci_dev * dev)888 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
889 {
890 uint32_t reg[5];
891 char node[32];
892 int np;
893
894 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
895 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
896
897 np = fdt_subnode_offset(blob, par, node);
898 if (np >= 0)
899 return np;
900 np = fdt_add_subnode(blob, par, node);
901 if (np < 0) {
902 printf(" %s failed: no space\n", __func__);
903 return np;
904 }
905
906 memset(reg, 0, sizeof(reg));
907 reg[0] = cpu_to_fdt32(PCI_ID(dev));
908 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
909
910 return np;
911 }
912
913 /* build a path of nested PCI devs for all bridges passed through */
fdt_add_pci_path(void * blob,struct pci_dev * dev)914 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
915 {
916 struct pci_dev *bridges[MAX_PCI_DEVS];
917 int k, np;
918
919 /* build list of parents */
920 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
921 if (np < 0)
922 return np;
923
924 k = 0;
925 while (dev) {
926 bridges[k++] = dev;
927 dev = dev->ppar;
928 };
929
930 /* now add them the to DT in reverse order */
931 while (k--) {
932 np = fdt_add_pci_node(blob, np, bridges[k]);
933 if (np < 0)
934 break;
935 }
936
937 return np;
938 }
939
940 /*
941 * The GW16082 has a hardware errata errata such that it's
942 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
943 * of this normal PCI interrupt swizzling will not work so we will
944 * provide an irq-map via device-tree.
945 */
fdt_fixup_gw16082(void * blob,int np,struct pci_dev * dev)946 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
947 {
948 int len;
949 int host;
950 uint32_t imap_new[8*4*4];
951 const uint32_t *imap;
952 uint32_t irq[4];
953 uint32_t reg[4];
954 int i;
955
956 /* build irq-map based on host controllers map */
957 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
958 if (host < 0) {
959 printf(" %s failed: missing host\n", __func__);
960 return host;
961 }
962
963 /* use interrupt data from root complex's node */
964 imap = fdt_getprop(blob, host, "interrupt-map", &len);
965 if (!imap || len != 128) {
966 printf(" %s failed: invalid interrupt-map\n",
967 __func__);
968 return -FDT_ERR_NOTFOUND;
969 }
970
971 /* obtain irq's of host controller in pin order */
972 for (i = 0; i < 4; i++)
973 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
974
975 /*
976 * determine number of swizzles necessary:
977 * For each bridge we pass through we need to swizzle
978 * the number of the slot we are on.
979 */
980 struct pci_dev *d;
981 int b;
982 b = 0;
983 d = dev->ppar;
984 while(d && d->ppar) {
985 b += PCI_DEV(d->devfn);
986 d = d->ppar;
987 }
988
989 /* create new irq mappings for slots12-15
990 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
991 * J3 AD28 12 INTD INTA
992 * J4 AD29 13 INTC INTD
993 * J5 AD30 14 INTB INTC
994 * J2 AD31 15 INTA INTB
995 */
996 for (i = 0; i < 4; i++) {
997 /* addr matches bus:dev:func */
998 u32 addr = dev->busno << 16 | (12+i) << 11;
999
1000 /* default cells from root complex */
1001 memcpy(&imap_new[i*32], imap, 128);
1002 /* first cell is PCI device address (BDF) */
1003 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1004 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1005 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1006 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1007 /* third cell is pin */
1008 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1009 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1010 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1011 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1012 /* sixth cell is relative interrupt */
1013 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1014 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1015 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1016 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1017 }
1018 fdt_setprop(blob, np, "interrupt-map", imap_new,
1019 sizeof(imap_new));
1020 reg[0] = cpu_to_fdt32(0xfff00);
1021 reg[1] = 0;
1022 reg[2] = 0;
1023 reg[3] = cpu_to_fdt32(0x7);
1024 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1025 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1026 fdt_setprop_string(blob, np, "device_type", "pci");
1027 fdt_setprop_cell(blob, np, "#address-cells", 3);
1028 fdt_setprop_cell(blob, np, "#size-cells", 2);
1029 printf(" Added custom interrupt-map for GW16082\n");
1030
1031 return 0;
1032 }
1033
1034 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
fdt_fixup_sky2(void * blob,int np,struct pci_dev * dev)1035 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1036 {
1037 char *tmp, *end;
1038 char mac[16];
1039 unsigned char mac_addr[6];
1040 int j;
1041
1042 sprintf(mac, "eth1addr");
1043 tmp = env_get(mac);
1044 if (tmp) {
1045 for (j = 0; j < 6; j++) {
1046 mac_addr[j] = tmp ?
1047 simple_strtoul(tmp, &end,16) : 0;
1048 if (tmp)
1049 tmp = (*end) ? end+1 : end;
1050 }
1051 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1052 sizeof(mac_addr));
1053 printf(" Added mac addr for eth1\n");
1054 return 0;
1055 }
1056
1057 return -1;
1058 }
1059
1060 /*
1061 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1062 * we will walk the PCI bus and add bridge nodes up to the device receiving
1063 * the fixup.
1064 */
ft_board_pci_fixup(void * blob,bd_t * bd)1065 void ft_board_pci_fixup(void *blob, bd_t *bd)
1066 {
1067 int i, np;
1068 struct pci_dev *dev;
1069
1070 for (i = 0; i < pci_devno; i++) {
1071 dev = &pci_devs[i];
1072
1073 /*
1074 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1075 * an EEPROM at i2c1-0x50.
1076 */
1077 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1078 (dev->device == 0x8240) &&
1079 (i2c_set_bus_num(1) == 0) &&
1080 (i2c_probe(0x50) == 0))
1081 {
1082 np = fdt_add_pci_path(blob, dev);
1083 if (np > 0)
1084 fdt_fixup_gw16082(blob, np, dev);
1085 }
1086
1087 /* ethernet1 mac address */
1088 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1089 (dev->device == 0x4380))
1090 {
1091 np = fdt_add_pci_path(blob, dev);
1092 if (np > 0)
1093 fdt_fixup_sky2(blob, np, dev);
1094 }
1095 }
1096 }
1097 #endif /* if defined(CONFIG_CMD_PCI) */
1098
ft_board_wdog_fixup(void * blob,phys_addr_t addr)1099 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1100 {
1101 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1102
1103 if (off) {
1104 fdt_delprop(blob, off, "ext-reset-output");
1105 fdt_delprop(blob, off, "fsl,ext-reset-output");
1106 }
1107 }
1108
1109 /*
1110 * called prior to booting kernel or by 'fdt boardsetup' command
1111 *
1112 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1113 * - mtd partitions based on mtdparts/mtdids env
1114 * - system-serial (board serial num from EEPROM)
1115 * - board (full model from EEPROM)
1116 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1117 */
1118 #define WDOG1_ADDR 0x20bc000
1119 #define WDOG2_ADDR 0x20c0000
1120 #define GPIO3_ADDR 0x20a4000
1121 #define USDHC3_ADDR 0x2198000
1122 #define PWM0_ADDR 0x2080000
ft_board_setup(void * blob,bd_t * bd)1123 int ft_board_setup(void *blob, bd_t *bd)
1124 {
1125 struct ventana_board_info *info = &ventana_info;
1126 struct ventana_eeprom_config *cfg;
1127 static const struct node_info nodes[] = {
1128 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1129 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1130 };
1131 const char *model = env_get("model");
1132 const char *display = env_get("display");
1133 int i;
1134 char rev = 0;
1135
1136 /* determine board revision */
1137 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1138 if (ventana_info.model[i] >= 'A') {
1139 rev = ventana_info.model[i];
1140 break;
1141 }
1142 }
1143
1144 if (env_get("fdt_noauto")) {
1145 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1146 return 0;
1147 }
1148
1149 if (test_bit(EECONFIG_NAND, info->config)) {
1150 /* Update partition nodes using info from mtdparts env var */
1151 puts(" Updating MTD partitions...\n");
1152 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1153 }
1154
1155 /* Update display timings from display env var */
1156 if (display) {
1157 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1158 display) >= 0)
1159 printf(" Set display timings for %s...\n", display);
1160 }
1161
1162 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1163
1164 /* board serial number */
1165 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1166 strlen(env_get("serial#")) + 1);
1167
1168 /* board (model contains model from device-tree) */
1169 fdt_setprop(blob, 0, "board", info->model,
1170 strlen((const char *)info->model) + 1);
1171
1172 /* set desired digital video capture format */
1173 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1174
1175 /*
1176 * Board model specific fixups
1177 */
1178 switch (board_type) {
1179 case GW51xx:
1180 /*
1181 * disable wdog node for GW51xx-A/B to work around
1182 * errata causing wdog timer to be unreliable.
1183 */
1184 if (rev >= 'A' && rev < 'C') {
1185 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1186 WDOG1_ADDR);
1187 if (i)
1188 fdt_status_disabled(blob, i);
1189 }
1190
1191 /* GW51xx-E adds WDOG1_B external reset */
1192 if (rev < 'E')
1193 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1194 break;
1195
1196 case GW52xx:
1197 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1198 if (info->model[4] == '2') {
1199 u32 handle = 0;
1200 u32 *range = NULL;
1201
1202 i = fdt_node_offset_by_compatible(blob, -1,
1203 "fsl,imx6q-pcie");
1204 if (i)
1205 range = (u32 *)fdt_getprop(blob, i,
1206 "reset-gpio", NULL);
1207
1208 if (range) {
1209 i = fdt_node_offset_by_compat_reg(blob,
1210 "fsl,imx6q-gpio", GPIO3_ADDR);
1211 if (i)
1212 handle = fdt_get_phandle(blob, i);
1213 if (handle) {
1214 range[0] = cpu_to_fdt32(handle);
1215 range[1] = cpu_to_fdt32(23);
1216 }
1217 }
1218
1219 /* these have broken usd_vsel */
1220 if (strstr((const char *)info->model, "SP318-B") ||
1221 strstr((const char *)info->model, "SP331-B"))
1222 gpio_cfg[board_type].usd_vsel = 0;
1223
1224 /* GW522x-B adds WDOG1_B external reset */
1225 if (rev < 'B')
1226 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1227 }
1228
1229 /* GW520x-E adds WDOG1_B external reset */
1230 else if (info->model[4] == '0' && rev < 'E')
1231 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1232 break;
1233
1234 case GW53xx:
1235 /* GW53xx-E adds WDOG1_B external reset */
1236 if (rev < 'E')
1237 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1238 break;
1239
1240 case GW54xx:
1241 /*
1242 * disable serial2 node for GW54xx for compatibility with older
1243 * 3.10.x kernel that improperly had this node enabled in the DT
1244 */
1245 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1246 0);
1247
1248 /* GW54xx-E adds WDOG2_B external reset */
1249 if (rev < 'E')
1250 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1251 break;
1252
1253 case GW551x:
1254 /*
1255 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1256 * causing non functional digital video in (it is not hooked up)
1257 */
1258 if (rev == 'A') {
1259 u32 *range = NULL;
1260 int len;
1261 const u32 *handle = NULL;
1262
1263 i = fdt_node_offset_by_compatible(blob, -1,
1264 "fsl,imx-tda1997x-video");
1265 if (i)
1266 handle = fdt_getprop(blob, i, "pinctrl-0",
1267 NULL);
1268 if (handle)
1269 i = fdt_node_offset_by_phandle(blob,
1270 fdt32_to_cpu(*handle));
1271 if (i)
1272 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1273 &len);
1274 if (range) {
1275 len /= sizeof(u32);
1276 for (i = 0; i < len; i += 6) {
1277 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1278 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1279 /* mux PAD_CSI0_DATA_EN to GPIO */
1280 if (is_cpu_type(MXC_CPU_MX6Q) &&
1281 mux_reg == 0x260 &&
1282 conf_reg == 0x630)
1283 range[i+3] = cpu_to_fdt32(0x5);
1284 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1285 mux_reg == 0x08c &&
1286 conf_reg == 0x3a0)
1287 range[i+3] = cpu_to_fdt32(0x5);
1288 }
1289 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1290 len);
1291 }
1292
1293 /* set BT656 video format */
1294 ft_sethdmiinfmt(blob, "yuv422bt656");
1295 }
1296
1297 /* GW551x-C adds WDOG1_B external reset */
1298 if (rev < 'C')
1299 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1300 break;
1301 case GW5901:
1302 case GW5902:
1303 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1304 if (rev < 'B')
1305 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1306 break;
1307 }
1308
1309 /* Configure DIO */
1310 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1311 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1312 char arg[10];
1313
1314 sprintf(arg, "dio%d", i);
1315 if (!hwconfig(arg))
1316 continue;
1317 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1318 {
1319 phys_addr_t addr;
1320 int off;
1321
1322 printf(" Enabling pwm%d for DIO%d\n",
1323 cfg->pwm_param, i);
1324 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1325 off = fdt_node_offset_by_compat_reg(blob,
1326 "fsl,imx6q-pwm",
1327 addr);
1328 if (off)
1329 fdt_status_okay(blob, off);
1330 }
1331 }
1332
1333 /* remove no-1-8-v if UHS-I support is present */
1334 if (gpio_cfg[board_type].usd_vsel) {
1335 debug("Enabling UHS-I support\n");
1336 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1337 USDHC3_ADDR);
1338 if (i)
1339 fdt_delprop(blob, i, "no-1-8-v");
1340 }
1341
1342 #if defined(CONFIG_CMD_PCI)
1343 if (!env_get("nopcifixup"))
1344 ft_board_pci_fixup(blob, bd);
1345 #endif
1346
1347 /*
1348 * Peripheral Config:
1349 * remove nodes by alias path if EEPROM config tells us the
1350 * peripheral is not loaded on the board.
1351 */
1352 if (env_get("fdt_noconfig")) {
1353 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1354 return 0;
1355 }
1356 cfg = econfig;
1357 while (cfg->name) {
1358 if (!test_bit(cfg->bit, info->config)) {
1359 fdt_del_node_and_alias(blob, cfg->dtalias ?
1360 cfg->dtalias : cfg->name);
1361 }
1362 cfg++;
1363 }
1364
1365 return 0;
1366 }
1367 #endif /* CONFIG_OF_BOARD_SETUP */
1368
1369 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1370 .reg = (struct mxc_uart *)UART2_BASE,
1371 };
1372
1373 U_BOOT_DEVICE(ventana_serial) = {
1374 .name = "serial_mxc",
1375 .platdata = &ventana_mxc_serial_plat,
1376 };
1377