1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #include <linux/module.h>
5 #include <linux/types.h>
6 #include <linux/if_vlan.h>
7 #include <linux/tcp.h>
8 #include <linux/udp.h>
9 #include <linux/ip.h>
10 #include <linux/pm_runtime.h>
11 #include <net/pkt_sched.h>
12 #include <linux/bpf_trace.h>
13 #include <net/xdp_sock_drv.h>
14 #include <linux/pci.h>
15
16 #include <net/ipv6.h>
17
18 #include "igc.h"
19 #include "igc_hw.h"
20 #include "igc_tsn.h"
21 #include "igc_xdp.h"
22
23 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver"
24
25 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
26
27 #define IGC_XDP_PASS 0
28 #define IGC_XDP_CONSUMED BIT(0)
29 #define IGC_XDP_TX BIT(1)
30 #define IGC_XDP_REDIRECT BIT(2)
31
32 static int debug = -1;
33
34 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
35 MODULE_DESCRIPTION(DRV_SUMMARY);
36 MODULE_LICENSE("GPL v2");
37 module_param(debug, int, 0);
38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40 char igc_driver_name[] = "igc";
41 static const char igc_driver_string[] = DRV_SUMMARY;
42 static const char igc_copyright[] =
43 "Copyright(c) 2018 Intel Corporation.";
44
45 static const struct igc_info *igc_info_tbl[] = {
46 [board_base] = &igc_base_info,
47 };
48
49 static const struct pci_device_id igc_pci_tbl[] = {
50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },
53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },
54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },
55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },
56 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base },
57 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },
58 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base },
59 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },
60 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },
61 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },
62 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },
63 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },
64 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },
65 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },
66 /* required last entry */
67 {0, }
68 };
69
70 MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
71
72 enum latency_range {
73 lowest_latency = 0,
74 low_latency = 1,
75 bulk_latency = 2,
76 latency_invalid = 255
77 };
78
igc_reset(struct igc_adapter * adapter)79 void igc_reset(struct igc_adapter *adapter)
80 {
81 struct net_device *dev = adapter->netdev;
82 struct igc_hw *hw = &adapter->hw;
83 struct igc_fc_info *fc = &hw->fc;
84 u32 pba, hwm;
85
86 /* Repartition PBA for greater than 9k MTU if required */
87 pba = IGC_PBA_34K;
88
89 /* flow control settings
90 * The high water mark must be low enough to fit one full frame
91 * after transmitting the pause frame. As such we must have enough
92 * space to allow for us to complete our current transmit and then
93 * receive the frame that is in progress from the link partner.
94 * Set it to:
95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
96 */
97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
98
99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
100 fc->low_water = fc->high_water - 16;
101 fc->pause_time = 0xFFFF;
102 fc->send_xon = 1;
103 fc->current_mode = fc->requested_mode;
104
105 hw->mac.ops.reset_hw(hw);
106
107 if (hw->mac.ops.init_hw(hw))
108 netdev_err(dev, "Error on hardware initialization\n");
109
110 /* Re-establish EEE setting */
111 igc_set_eee_i225(hw, true, true, true);
112
113 if (!netif_running(adapter->netdev))
114 igc_power_down_phy_copper_base(&adapter->hw);
115
116 /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */
117 wr32(IGC_VET, ETH_P_8021Q);
118
119 /* Re-enable PTP, where applicable. */
120 igc_ptp_reset(adapter);
121
122 /* Re-enable TSN offloading, where applicable. */
123 igc_tsn_reset(adapter);
124
125 igc_get_phy_info(hw);
126 }
127
128 /**
129 * igc_power_up_link - Power up the phy link
130 * @adapter: address of board private structure
131 */
igc_power_up_link(struct igc_adapter * adapter)132 static void igc_power_up_link(struct igc_adapter *adapter)
133 {
134 igc_reset_phy(&adapter->hw);
135
136 igc_power_up_phy_copper(&adapter->hw);
137
138 igc_setup_link(&adapter->hw);
139 }
140
141 /**
142 * igc_release_hw_control - release control of the h/w to f/w
143 * @adapter: address of board private structure
144 *
145 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
146 * For ASF and Pass Through versions of f/w this means that the
147 * driver is no longer loaded.
148 */
igc_release_hw_control(struct igc_adapter * adapter)149 static void igc_release_hw_control(struct igc_adapter *adapter)
150 {
151 struct igc_hw *hw = &adapter->hw;
152 u32 ctrl_ext;
153
154 if (!pci_device_is_present(adapter->pdev))
155 return;
156
157 /* Let firmware take over control of h/w */
158 ctrl_ext = rd32(IGC_CTRL_EXT);
159 wr32(IGC_CTRL_EXT,
160 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
161 }
162
163 /**
164 * igc_get_hw_control - get control of the h/w from f/w
165 * @adapter: address of board private structure
166 *
167 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
168 * For ASF and Pass Through versions of f/w this means that
169 * the driver is loaded.
170 */
igc_get_hw_control(struct igc_adapter * adapter)171 static void igc_get_hw_control(struct igc_adapter *adapter)
172 {
173 struct igc_hw *hw = &adapter->hw;
174 u32 ctrl_ext;
175
176 /* Let firmware know the driver has taken over */
177 ctrl_ext = rd32(IGC_CTRL_EXT);
178 wr32(IGC_CTRL_EXT,
179 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
180 }
181
igc_unmap_tx_buffer(struct device * dev,struct igc_tx_buffer * buf)182 static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf)
183 {
184 dma_unmap_single(dev, dma_unmap_addr(buf, dma),
185 dma_unmap_len(buf, len), DMA_TO_DEVICE);
186
187 dma_unmap_len_set(buf, len, 0);
188 }
189
190 /**
191 * igc_clean_tx_ring - Free Tx Buffers
192 * @tx_ring: ring to be cleaned
193 */
igc_clean_tx_ring(struct igc_ring * tx_ring)194 static void igc_clean_tx_ring(struct igc_ring *tx_ring)
195 {
196 u16 i = tx_ring->next_to_clean;
197 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
198 u32 xsk_frames = 0;
199
200 while (i != tx_ring->next_to_use) {
201 union igc_adv_tx_desc *eop_desc, *tx_desc;
202
203 switch (tx_buffer->type) {
204 case IGC_TX_BUFFER_TYPE_XSK:
205 xsk_frames++;
206 break;
207 case IGC_TX_BUFFER_TYPE_XDP:
208 xdp_return_frame(tx_buffer->xdpf);
209 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
210 break;
211 case IGC_TX_BUFFER_TYPE_SKB:
212 dev_kfree_skb_any(tx_buffer->skb);
213 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
214 break;
215 default:
216 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");
217 break;
218 }
219
220 /* check for eop_desc to determine the end of the packet */
221 eop_desc = tx_buffer->next_to_watch;
222 tx_desc = IGC_TX_DESC(tx_ring, i);
223
224 /* unmap remaining buffers */
225 while (tx_desc != eop_desc) {
226 tx_buffer++;
227 tx_desc++;
228 i++;
229 if (unlikely(i == tx_ring->count)) {
230 i = 0;
231 tx_buffer = tx_ring->tx_buffer_info;
232 tx_desc = IGC_TX_DESC(tx_ring, 0);
233 }
234
235 /* unmap any remaining paged data */
236 if (dma_unmap_len(tx_buffer, len))
237 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
238 }
239
240 tx_buffer->next_to_watch = NULL;
241
242 /* move us one more past the eop_desc for start of next pkt */
243 tx_buffer++;
244 i++;
245 if (unlikely(i == tx_ring->count)) {
246 i = 0;
247 tx_buffer = tx_ring->tx_buffer_info;
248 }
249 }
250
251 if (tx_ring->xsk_pool && xsk_frames)
252 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);
253
254 /* reset BQL for queue */
255 netdev_tx_reset_queue(txring_txq(tx_ring));
256
257 /* Zero out the buffer ring */
258 memset(tx_ring->tx_buffer_info, 0,
259 sizeof(*tx_ring->tx_buffer_info) * tx_ring->count);
260
261 /* Zero out the descriptor ring */
262 memset(tx_ring->desc, 0, tx_ring->size);
263
264 /* reset next_to_use and next_to_clean */
265 tx_ring->next_to_use = 0;
266 tx_ring->next_to_clean = 0;
267 }
268
269 /**
270 * igc_free_tx_resources - Free Tx Resources per Queue
271 * @tx_ring: Tx descriptor ring for a specific queue
272 *
273 * Free all transmit software resources
274 */
igc_free_tx_resources(struct igc_ring * tx_ring)275 void igc_free_tx_resources(struct igc_ring *tx_ring)
276 {
277 igc_disable_tx_ring(tx_ring);
278
279 vfree(tx_ring->tx_buffer_info);
280 tx_ring->tx_buffer_info = NULL;
281
282 /* if not set, then don't free */
283 if (!tx_ring->desc)
284 return;
285
286 dma_free_coherent(tx_ring->dev, tx_ring->size,
287 tx_ring->desc, tx_ring->dma);
288
289 tx_ring->desc = NULL;
290 }
291
292 /**
293 * igc_free_all_tx_resources - Free Tx Resources for All Queues
294 * @adapter: board private structure
295 *
296 * Free all transmit software resources
297 */
igc_free_all_tx_resources(struct igc_adapter * adapter)298 static void igc_free_all_tx_resources(struct igc_adapter *adapter)
299 {
300 int i;
301
302 for (i = 0; i < adapter->num_tx_queues; i++)
303 igc_free_tx_resources(adapter->tx_ring[i]);
304 }
305
306 /**
307 * igc_clean_all_tx_rings - Free Tx Buffers for all queues
308 * @adapter: board private structure
309 */
igc_clean_all_tx_rings(struct igc_adapter * adapter)310 static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
311 {
312 int i;
313
314 for (i = 0; i < adapter->num_tx_queues; i++)
315 if (adapter->tx_ring[i])
316 igc_clean_tx_ring(adapter->tx_ring[i]);
317 }
318
igc_disable_tx_ring_hw(struct igc_ring * ring)319 static void igc_disable_tx_ring_hw(struct igc_ring *ring)
320 {
321 struct igc_hw *hw = &ring->q_vector->adapter->hw;
322 u8 idx = ring->reg_idx;
323 u32 txdctl;
324
325 txdctl = rd32(IGC_TXDCTL(idx));
326 txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE;
327 txdctl |= IGC_TXDCTL_SWFLUSH;
328 wr32(IGC_TXDCTL(idx), txdctl);
329 }
330
331 /**
332 * igc_disable_all_tx_rings_hw - Disable all transmit queue operation
333 * @adapter: board private structure
334 */
igc_disable_all_tx_rings_hw(struct igc_adapter * adapter)335 static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter)
336 {
337 int i;
338
339 for (i = 0; i < adapter->num_tx_queues; i++) {
340 struct igc_ring *tx_ring = adapter->tx_ring[i];
341
342 igc_disable_tx_ring_hw(tx_ring);
343 }
344 }
345
346 /**
347 * igc_setup_tx_resources - allocate Tx resources (Descriptors)
348 * @tx_ring: tx descriptor ring (for a specific queue) to setup
349 *
350 * Return 0 on success, negative on failure
351 */
igc_setup_tx_resources(struct igc_ring * tx_ring)352 int igc_setup_tx_resources(struct igc_ring *tx_ring)
353 {
354 struct net_device *ndev = tx_ring->netdev;
355 struct device *dev = tx_ring->dev;
356 int size = 0;
357
358 size = sizeof(struct igc_tx_buffer) * tx_ring->count;
359 tx_ring->tx_buffer_info = vzalloc(size);
360 if (!tx_ring->tx_buffer_info)
361 goto err;
362
363 /* round up to nearest 4K */
364 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
365 tx_ring->size = ALIGN(tx_ring->size, 4096);
366
367 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
368 &tx_ring->dma, GFP_KERNEL);
369
370 if (!tx_ring->desc)
371 goto err;
372
373 tx_ring->next_to_use = 0;
374 tx_ring->next_to_clean = 0;
375
376 return 0;
377
378 err:
379 vfree(tx_ring->tx_buffer_info);
380 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");
381 return -ENOMEM;
382 }
383
384 /**
385 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
386 * @adapter: board private structure
387 *
388 * Return 0 on success, negative on failure
389 */
igc_setup_all_tx_resources(struct igc_adapter * adapter)390 static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
391 {
392 struct net_device *dev = adapter->netdev;
393 int i, err = 0;
394
395 for (i = 0; i < adapter->num_tx_queues; i++) {
396 err = igc_setup_tx_resources(adapter->tx_ring[i]);
397 if (err) {
398 netdev_err(dev, "Error on Tx queue %u setup\n", i);
399 for (i--; i >= 0; i--)
400 igc_free_tx_resources(adapter->tx_ring[i]);
401 break;
402 }
403 }
404
405 return err;
406 }
407
igc_clean_rx_ring_page_shared(struct igc_ring * rx_ring)408 static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring)
409 {
410 u16 i = rx_ring->next_to_clean;
411
412 dev_kfree_skb(rx_ring->skb);
413 rx_ring->skb = NULL;
414
415 /* Free all the Rx ring sk_buffs */
416 while (i != rx_ring->next_to_alloc) {
417 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
418
419 /* Invalidate cache lines that may have been written to by
420 * device so that we avoid corrupting memory.
421 */
422 dma_sync_single_range_for_cpu(rx_ring->dev,
423 buffer_info->dma,
424 buffer_info->page_offset,
425 igc_rx_bufsz(rx_ring),
426 DMA_FROM_DEVICE);
427
428 /* free resources associated with mapping */
429 dma_unmap_page_attrs(rx_ring->dev,
430 buffer_info->dma,
431 igc_rx_pg_size(rx_ring),
432 DMA_FROM_DEVICE,
433 IGC_RX_DMA_ATTR);
434 __page_frag_cache_drain(buffer_info->page,
435 buffer_info->pagecnt_bias);
436
437 i++;
438 if (i == rx_ring->count)
439 i = 0;
440 }
441 }
442
igc_clean_rx_ring_xsk_pool(struct igc_ring * ring)443 static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring)
444 {
445 struct igc_rx_buffer *bi;
446 u16 i;
447
448 for (i = 0; i < ring->count; i++) {
449 bi = &ring->rx_buffer_info[i];
450 if (!bi->xdp)
451 continue;
452
453 xsk_buff_free(bi->xdp);
454 bi->xdp = NULL;
455 }
456 }
457
458 /**
459 * igc_clean_rx_ring - Free Rx Buffers per Queue
460 * @ring: ring to free buffers from
461 */
igc_clean_rx_ring(struct igc_ring * ring)462 static void igc_clean_rx_ring(struct igc_ring *ring)
463 {
464 if (ring->xsk_pool)
465 igc_clean_rx_ring_xsk_pool(ring);
466 else
467 igc_clean_rx_ring_page_shared(ring);
468
469 clear_ring_uses_large_buffer(ring);
470
471 ring->next_to_alloc = 0;
472 ring->next_to_clean = 0;
473 ring->next_to_use = 0;
474 }
475
476 /**
477 * igc_clean_all_rx_rings - Free Rx Buffers for all queues
478 * @adapter: board private structure
479 */
igc_clean_all_rx_rings(struct igc_adapter * adapter)480 static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
481 {
482 int i;
483
484 for (i = 0; i < adapter->num_rx_queues; i++)
485 if (adapter->rx_ring[i])
486 igc_clean_rx_ring(adapter->rx_ring[i]);
487 }
488
489 /**
490 * igc_free_rx_resources - Free Rx Resources
491 * @rx_ring: ring to clean the resources from
492 *
493 * Free all receive software resources
494 */
igc_free_rx_resources(struct igc_ring * rx_ring)495 void igc_free_rx_resources(struct igc_ring *rx_ring)
496 {
497 igc_clean_rx_ring(rx_ring);
498
499 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
500
501 vfree(rx_ring->rx_buffer_info);
502 rx_ring->rx_buffer_info = NULL;
503
504 /* if not set, then don't free */
505 if (!rx_ring->desc)
506 return;
507
508 dma_free_coherent(rx_ring->dev, rx_ring->size,
509 rx_ring->desc, rx_ring->dma);
510
511 rx_ring->desc = NULL;
512 }
513
514 /**
515 * igc_free_all_rx_resources - Free Rx Resources for All Queues
516 * @adapter: board private structure
517 *
518 * Free all receive software resources
519 */
igc_free_all_rx_resources(struct igc_adapter * adapter)520 static void igc_free_all_rx_resources(struct igc_adapter *adapter)
521 {
522 int i;
523
524 for (i = 0; i < adapter->num_rx_queues; i++)
525 igc_free_rx_resources(adapter->rx_ring[i]);
526 }
527
528 /**
529 * igc_setup_rx_resources - allocate Rx resources (Descriptors)
530 * @rx_ring: rx descriptor ring (for a specific queue) to setup
531 *
532 * Returns 0 on success, negative on failure
533 */
igc_setup_rx_resources(struct igc_ring * rx_ring)534 int igc_setup_rx_resources(struct igc_ring *rx_ring)
535 {
536 struct net_device *ndev = rx_ring->netdev;
537 struct device *dev = rx_ring->dev;
538 u8 index = rx_ring->queue_index;
539 int size, desc_len, res;
540
541 /* XDP RX-queue info */
542 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
543 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
544 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index,
545 rx_ring->q_vector->napi.napi_id);
546 if (res < 0) {
547 netdev_err(ndev, "Failed to register xdp_rxq index %u\n",
548 index);
549 return res;
550 }
551
552 size = sizeof(struct igc_rx_buffer) * rx_ring->count;
553 rx_ring->rx_buffer_info = vzalloc(size);
554 if (!rx_ring->rx_buffer_info)
555 goto err;
556
557 desc_len = sizeof(union igc_adv_rx_desc);
558
559 /* Round up to nearest 4K */
560 rx_ring->size = rx_ring->count * desc_len;
561 rx_ring->size = ALIGN(rx_ring->size, 4096);
562
563 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
564 &rx_ring->dma, GFP_KERNEL);
565
566 if (!rx_ring->desc)
567 goto err;
568
569 rx_ring->next_to_alloc = 0;
570 rx_ring->next_to_clean = 0;
571 rx_ring->next_to_use = 0;
572
573 return 0;
574
575 err:
576 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
577 vfree(rx_ring->rx_buffer_info);
578 rx_ring->rx_buffer_info = NULL;
579 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");
580 return -ENOMEM;
581 }
582
583 /**
584 * igc_setup_all_rx_resources - wrapper to allocate Rx resources
585 * (Descriptors) for all queues
586 * @adapter: board private structure
587 *
588 * Return 0 on success, negative on failure
589 */
igc_setup_all_rx_resources(struct igc_adapter * adapter)590 static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
591 {
592 struct net_device *dev = adapter->netdev;
593 int i, err = 0;
594
595 for (i = 0; i < adapter->num_rx_queues; i++) {
596 err = igc_setup_rx_resources(adapter->rx_ring[i]);
597 if (err) {
598 netdev_err(dev, "Error on Rx queue %u setup\n", i);
599 for (i--; i >= 0; i--)
600 igc_free_rx_resources(adapter->rx_ring[i]);
601 break;
602 }
603 }
604
605 return err;
606 }
607
igc_get_xsk_pool(struct igc_adapter * adapter,struct igc_ring * ring)608 static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter,
609 struct igc_ring *ring)
610 {
611 if (!igc_xdp_is_enabled(adapter) ||
612 !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags))
613 return NULL;
614
615 return xsk_get_pool_from_qid(ring->netdev, ring->queue_index);
616 }
617
618 /**
619 * igc_configure_rx_ring - Configure a receive ring after Reset
620 * @adapter: board private structure
621 * @ring: receive ring to be configured
622 *
623 * Configure the Rx unit of the MAC after a reset.
624 */
igc_configure_rx_ring(struct igc_adapter * adapter,struct igc_ring * ring)625 static void igc_configure_rx_ring(struct igc_adapter *adapter,
626 struct igc_ring *ring)
627 {
628 struct igc_hw *hw = &adapter->hw;
629 union igc_adv_rx_desc *rx_desc;
630 int reg_idx = ring->reg_idx;
631 u32 srrctl = 0, rxdctl = 0;
632 u64 rdba = ring->dma;
633 u32 buf_size;
634
635 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
636 ring->xsk_pool = igc_get_xsk_pool(adapter, ring);
637 if (ring->xsk_pool) {
638 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
639 MEM_TYPE_XSK_BUFF_POOL,
640 NULL));
641 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
642 } else {
643 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
644 MEM_TYPE_PAGE_SHARED,
645 NULL));
646 }
647
648 if (igc_xdp_is_enabled(adapter))
649 set_ring_uses_large_buffer(ring);
650
651 /* disable the queue */
652 wr32(IGC_RXDCTL(reg_idx), 0);
653
654 /* Set DMA base address registers */
655 wr32(IGC_RDBAL(reg_idx),
656 rdba & 0x00000000ffffffffULL);
657 wr32(IGC_RDBAH(reg_idx), rdba >> 32);
658 wr32(IGC_RDLEN(reg_idx),
659 ring->count * sizeof(union igc_adv_rx_desc));
660
661 /* initialize head and tail */
662 ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
663 wr32(IGC_RDH(reg_idx), 0);
664 writel(0, ring->tail);
665
666 /* reset next-to- use/clean to place SW in sync with hardware */
667 ring->next_to_clean = 0;
668 ring->next_to_use = 0;
669
670 if (ring->xsk_pool)
671 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool);
672 else if (ring_uses_large_buffer(ring))
673 buf_size = IGC_RXBUFFER_3072;
674 else
675 buf_size = IGC_RXBUFFER_2048;
676
677 srrctl = rd32(IGC_SRRCTL(reg_idx));
678 srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK |
679 IGC_SRRCTL_DESCTYPE_MASK);
680 srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN);
681 srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size);
682 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
683
684 wr32(IGC_SRRCTL(reg_idx), srrctl);
685
686 rxdctl |= IGC_RX_PTHRESH;
687 rxdctl |= IGC_RX_HTHRESH << 8;
688 rxdctl |= IGC_RX_WTHRESH << 16;
689
690 /* initialize rx_buffer_info */
691 memset(ring->rx_buffer_info, 0,
692 sizeof(struct igc_rx_buffer) * ring->count);
693
694 /* initialize Rx descriptor 0 */
695 rx_desc = IGC_RX_DESC(ring, 0);
696 rx_desc->wb.upper.length = 0;
697
698 /* enable receive descriptor fetching */
699 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
700
701 wr32(IGC_RXDCTL(reg_idx), rxdctl);
702 }
703
704 /**
705 * igc_configure_rx - Configure receive Unit after Reset
706 * @adapter: board private structure
707 *
708 * Configure the Rx unit of the MAC after a reset.
709 */
igc_configure_rx(struct igc_adapter * adapter)710 static void igc_configure_rx(struct igc_adapter *adapter)
711 {
712 int i;
713
714 /* Setup the HW Rx Head and Tail Descriptor Pointers and
715 * the Base and Length of the Rx Descriptor Ring
716 */
717 for (i = 0; i < adapter->num_rx_queues; i++)
718 igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
719 }
720
721 /**
722 * igc_configure_tx_ring - Configure transmit ring after Reset
723 * @adapter: board private structure
724 * @ring: tx ring to configure
725 *
726 * Configure a transmit ring after a reset.
727 */
igc_configure_tx_ring(struct igc_adapter * adapter,struct igc_ring * ring)728 static void igc_configure_tx_ring(struct igc_adapter *adapter,
729 struct igc_ring *ring)
730 {
731 struct igc_hw *hw = &adapter->hw;
732 int reg_idx = ring->reg_idx;
733 u64 tdba = ring->dma;
734 u32 txdctl = 0;
735
736 ring->xsk_pool = igc_get_xsk_pool(adapter, ring);
737
738 /* disable the queue */
739 wr32(IGC_TXDCTL(reg_idx), 0);
740 wrfl();
741
742 wr32(IGC_TDLEN(reg_idx),
743 ring->count * sizeof(union igc_adv_tx_desc));
744 wr32(IGC_TDBAL(reg_idx),
745 tdba & 0x00000000ffffffffULL);
746 wr32(IGC_TDBAH(reg_idx), tdba >> 32);
747
748 ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
749 wr32(IGC_TDH(reg_idx), 0);
750 writel(0, ring->tail);
751
752 txdctl |= IGC_TX_PTHRESH;
753 txdctl |= IGC_TX_HTHRESH << 8;
754 txdctl |= IGC_TX_WTHRESH << 16;
755
756 txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
757 wr32(IGC_TXDCTL(reg_idx), txdctl);
758 }
759
760 /**
761 * igc_configure_tx - Configure transmit Unit after Reset
762 * @adapter: board private structure
763 *
764 * Configure the Tx unit of the MAC after a reset.
765 */
igc_configure_tx(struct igc_adapter * adapter)766 static void igc_configure_tx(struct igc_adapter *adapter)
767 {
768 int i;
769
770 for (i = 0; i < adapter->num_tx_queues; i++)
771 igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
772 }
773
774 /**
775 * igc_setup_mrqc - configure the multiple receive queue control registers
776 * @adapter: Board private structure
777 */
igc_setup_mrqc(struct igc_adapter * adapter)778 static void igc_setup_mrqc(struct igc_adapter *adapter)
779 {
780 struct igc_hw *hw = &adapter->hw;
781 u32 j, num_rx_queues;
782 u32 mrqc, rxcsum;
783 u32 rss_key[10];
784
785 netdev_rss_key_fill(rss_key, sizeof(rss_key));
786 for (j = 0; j < 10; j++)
787 wr32(IGC_RSSRK(j), rss_key[j]);
788
789 num_rx_queues = adapter->rss_queues;
790
791 if (adapter->rss_indir_tbl_init != num_rx_queues) {
792 for (j = 0; j < IGC_RETA_SIZE; j++)
793 adapter->rss_indir_tbl[j] =
794 (j * num_rx_queues) / IGC_RETA_SIZE;
795 adapter->rss_indir_tbl_init = num_rx_queues;
796 }
797 igc_write_rss_indir_tbl(adapter);
798
799 /* Disable raw packet checksumming so that RSS hash is placed in
800 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
801 * offloads as they are enabled by default
802 */
803 rxcsum = rd32(IGC_RXCSUM);
804 rxcsum |= IGC_RXCSUM_PCSD;
805
806 /* Enable Receive Checksum Offload for SCTP */
807 rxcsum |= IGC_RXCSUM_CRCOFL;
808
809 /* Don't need to set TUOFL or IPOFL, they default to 1 */
810 wr32(IGC_RXCSUM, rxcsum);
811
812 /* Generate RSS hash based on packet types, TCP/UDP
813 * port numbers and/or IPv4/v6 src and dst addresses
814 */
815 mrqc = IGC_MRQC_RSS_FIELD_IPV4 |
816 IGC_MRQC_RSS_FIELD_IPV4_TCP |
817 IGC_MRQC_RSS_FIELD_IPV6 |
818 IGC_MRQC_RSS_FIELD_IPV6_TCP |
819 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;
820
821 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)
822 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;
823 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)
824 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;
825
826 mrqc |= IGC_MRQC_ENABLE_RSS_MQ;
827
828 wr32(IGC_MRQC, mrqc);
829 }
830
831 /**
832 * igc_setup_rctl - configure the receive control registers
833 * @adapter: Board private structure
834 */
igc_setup_rctl(struct igc_adapter * adapter)835 static void igc_setup_rctl(struct igc_adapter *adapter)
836 {
837 struct igc_hw *hw = &adapter->hw;
838 u32 rctl;
839
840 rctl = rd32(IGC_RCTL);
841
842 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
843 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);
844
845 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
846 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
847
848 /* enable stripping of CRC. Newer features require
849 * that the HW strips the CRC.
850 */
851 rctl |= IGC_RCTL_SECRC;
852
853 /* disable store bad packets and clear size bits. */
854 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);
855
856 /* enable LPE to allow for reception of jumbo frames */
857 rctl |= IGC_RCTL_LPE;
858
859 /* disable queue 0 to prevent tail write w/o re-config */
860 wr32(IGC_RXDCTL(0), 0);
861
862 /* This is useful for sniffing bad packets. */
863 if (adapter->netdev->features & NETIF_F_RXALL) {
864 /* UPE and MPE will be handled by normal PROMISC logic
865 * in set_rx_mode
866 */
867 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
868 IGC_RCTL_BAM | /* RX All Bcast Pkts */
869 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
870
871 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
872 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
873 }
874
875 wr32(IGC_RCTL, rctl);
876 }
877
878 /**
879 * igc_setup_tctl - configure the transmit control registers
880 * @adapter: Board private structure
881 */
igc_setup_tctl(struct igc_adapter * adapter)882 static void igc_setup_tctl(struct igc_adapter *adapter)
883 {
884 struct igc_hw *hw = &adapter->hw;
885 u32 tctl;
886
887 /* disable queue 0 which icould be enabled by default */
888 wr32(IGC_TXDCTL(0), 0);
889
890 /* Program the Transmit Control Register */
891 tctl = rd32(IGC_TCTL);
892 tctl &= ~IGC_TCTL_CT;
893 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
894 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);
895
896 /* Enable transmits */
897 tctl |= IGC_TCTL_EN;
898
899 wr32(IGC_TCTL, tctl);
900 }
901
902 /**
903 * igc_set_mac_filter_hw() - Set MAC address filter in hardware
904 * @adapter: Pointer to adapter where the filter should be set
905 * @index: Filter index
906 * @type: MAC address filter type (source or destination)
907 * @addr: MAC address
908 * @queue: If non-negative, queue assignment feature is enabled and frames
909 * matching the filter are enqueued onto 'queue'. Otherwise, queue
910 * assignment is disabled.
911 */
igc_set_mac_filter_hw(struct igc_adapter * adapter,int index,enum igc_mac_filter_type type,const u8 * addr,int queue)912 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,
913 enum igc_mac_filter_type type,
914 const u8 *addr, int queue)
915 {
916 struct net_device *dev = adapter->netdev;
917 struct igc_hw *hw = &adapter->hw;
918 u32 ral, rah;
919
920 if (WARN_ON(index >= hw->mac.rar_entry_count))
921 return;
922
923 ral = le32_to_cpup((__le32 *)(addr));
924 rah = le16_to_cpup((__le16 *)(addr + 4));
925
926 if (type == IGC_MAC_FILTER_TYPE_SRC) {
927 rah &= ~IGC_RAH_ASEL_MASK;
928 rah |= IGC_RAH_ASEL_SRC_ADDR;
929 }
930
931 if (queue >= 0) {
932 rah &= ~IGC_RAH_QSEL_MASK;
933 rah |= (queue << IGC_RAH_QSEL_SHIFT);
934 rah |= IGC_RAH_QSEL_ENABLE;
935 }
936
937 rah |= IGC_RAH_AV;
938
939 wr32(IGC_RAL(index), ral);
940 wr32(IGC_RAH(index), rah);
941
942 netdev_dbg(dev, "MAC address filter set in HW: index %d", index);
943 }
944
945 /**
946 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware
947 * @adapter: Pointer to adapter where the filter should be cleared
948 * @index: Filter index
949 */
igc_clear_mac_filter_hw(struct igc_adapter * adapter,int index)950 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)
951 {
952 struct net_device *dev = adapter->netdev;
953 struct igc_hw *hw = &adapter->hw;
954
955 if (WARN_ON(index >= hw->mac.rar_entry_count))
956 return;
957
958 wr32(IGC_RAL(index), 0);
959 wr32(IGC_RAH(index), 0);
960
961 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);
962 }
963
964 /* Set default MAC address for the PF in the first RAR entry */
igc_set_default_mac_filter(struct igc_adapter * adapter)965 static void igc_set_default_mac_filter(struct igc_adapter *adapter)
966 {
967 struct net_device *dev = adapter->netdev;
968 u8 *addr = adapter->hw.mac.addr;
969
970 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);
971
972 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);
973 }
974
975 /**
976 * igc_set_mac - Change the Ethernet Address of the NIC
977 * @netdev: network interface device structure
978 * @p: pointer to an address structure
979 *
980 * Returns 0 on success, negative on failure
981 */
igc_set_mac(struct net_device * netdev,void * p)982 static int igc_set_mac(struct net_device *netdev, void *p)
983 {
984 struct igc_adapter *adapter = netdev_priv(netdev);
985 struct igc_hw *hw = &adapter->hw;
986 struct sockaddr *addr = p;
987
988 if (!is_valid_ether_addr(addr->sa_data))
989 return -EADDRNOTAVAIL;
990
991 eth_hw_addr_set(netdev, addr->sa_data);
992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
993
994 /* set the correct pool for the new PF MAC address in entry 0 */
995 igc_set_default_mac_filter(adapter);
996
997 return 0;
998 }
999
1000 /**
1001 * igc_write_mc_addr_list - write multicast addresses to MTA
1002 * @netdev: network interface device structure
1003 *
1004 * Writes multicast address list to the MTA hash table.
1005 * Returns: -ENOMEM on failure
1006 * 0 on no addresses written
1007 * X on writing X addresses to MTA
1008 **/
igc_write_mc_addr_list(struct net_device * netdev)1009 static int igc_write_mc_addr_list(struct net_device *netdev)
1010 {
1011 struct igc_adapter *adapter = netdev_priv(netdev);
1012 struct igc_hw *hw = &adapter->hw;
1013 struct netdev_hw_addr *ha;
1014 u8 *mta_list;
1015 int i;
1016
1017 if (netdev_mc_empty(netdev)) {
1018 /* nothing to program, so clear mc list */
1019 igc_update_mc_addr_list(hw, NULL, 0);
1020 return 0;
1021 }
1022
1023 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
1024 if (!mta_list)
1025 return -ENOMEM;
1026
1027 /* The shared function expects a packed array of only addresses. */
1028 i = 0;
1029 netdev_for_each_mc_addr(ha, netdev)
1030 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
1031
1032 igc_update_mc_addr_list(hw, mta_list, i);
1033 kfree(mta_list);
1034
1035 return netdev_mc_count(netdev);
1036 }
1037
igc_tx_launchtime(struct igc_ring * ring,ktime_t txtime,bool * first_flag,bool * insert_empty)1038 static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime,
1039 bool *first_flag, bool *insert_empty)
1040 {
1041 struct igc_adapter *adapter = netdev_priv(ring->netdev);
1042 ktime_t cycle_time = adapter->cycle_time;
1043 ktime_t base_time = adapter->base_time;
1044 ktime_t now = ktime_get_clocktai();
1045 ktime_t baset_est, end_of_cycle;
1046 s32 launchtime;
1047 s64 n;
1048
1049 n = div64_s64(ktime_sub_ns(now, base_time), cycle_time);
1050
1051 baset_est = ktime_add_ns(base_time, cycle_time * (n));
1052 end_of_cycle = ktime_add_ns(baset_est, cycle_time);
1053
1054 if (ktime_compare(txtime, end_of_cycle) >= 0) {
1055 if (baset_est != ring->last_ff_cycle) {
1056 *first_flag = true;
1057 ring->last_ff_cycle = baset_est;
1058
1059 if (ktime_compare(end_of_cycle, ring->last_tx_cycle) > 0)
1060 *insert_empty = true;
1061 }
1062 }
1063
1064 /* Introducing a window at end of cycle on which packets
1065 * potentially not honor launchtime. Window of 5us chosen
1066 * considering software update the tail pointer and packets
1067 * are dma'ed to packet buffer.
1068 */
1069 if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC))
1070 netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n",
1071 txtime);
1072
1073 ring->last_tx_cycle = end_of_cycle;
1074
1075 launchtime = ktime_sub_ns(txtime, baset_est);
1076 if (launchtime > 0)
1077 div_s64_rem(launchtime, cycle_time, &launchtime);
1078 else
1079 launchtime = 0;
1080
1081 return cpu_to_le32(launchtime);
1082 }
1083
igc_init_empty_frame(struct igc_ring * ring,struct igc_tx_buffer * buffer,struct sk_buff * skb)1084 static int igc_init_empty_frame(struct igc_ring *ring,
1085 struct igc_tx_buffer *buffer,
1086 struct sk_buff *skb)
1087 {
1088 unsigned int size;
1089 dma_addr_t dma;
1090
1091 size = skb_headlen(skb);
1092
1093 dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE);
1094 if (dma_mapping_error(ring->dev, dma)) {
1095 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
1096 return -ENOMEM;
1097 }
1098
1099 buffer->type = IGC_TX_BUFFER_TYPE_SKB;
1100 buffer->skb = skb;
1101 buffer->protocol = 0;
1102 buffer->bytecount = skb->len;
1103 buffer->gso_segs = 1;
1104 buffer->time_stamp = jiffies;
1105 dma_unmap_len_set(buffer, len, skb->len);
1106 dma_unmap_addr_set(buffer, dma, dma);
1107
1108 return 0;
1109 }
1110
igc_init_tx_empty_descriptor(struct igc_ring * ring,struct sk_buff * skb,struct igc_tx_buffer * first)1111 static int igc_init_tx_empty_descriptor(struct igc_ring *ring,
1112 struct sk_buff *skb,
1113 struct igc_tx_buffer *first)
1114 {
1115 union igc_adv_tx_desc *desc;
1116 u32 cmd_type, olinfo_status;
1117 int err;
1118
1119 if (!igc_desc_unused(ring))
1120 return -EBUSY;
1121
1122 err = igc_init_empty_frame(ring, first, skb);
1123 if (err)
1124 return err;
1125
1126 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
1127 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
1128 first->bytecount;
1129 olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
1130
1131 desc = IGC_TX_DESC(ring, ring->next_to_use);
1132 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1133 desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1134 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma));
1135
1136 netdev_tx_sent_queue(txring_txq(ring), skb->len);
1137
1138 first->next_to_watch = desc;
1139
1140 ring->next_to_use++;
1141 if (ring->next_to_use == ring->count)
1142 ring->next_to_use = 0;
1143
1144 return 0;
1145 }
1146
1147 #define IGC_EMPTY_FRAME_SIZE 60
1148
igc_tx_ctxtdesc(struct igc_ring * tx_ring,__le32 launch_time,bool first_flag,u32 vlan_macip_lens,u32 type_tucmd,u32 mss_l4len_idx)1149 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
1150 __le32 launch_time, bool first_flag,
1151 u32 vlan_macip_lens, u32 type_tucmd,
1152 u32 mss_l4len_idx)
1153 {
1154 struct igc_adv_tx_context_desc *context_desc;
1155 u16 i = tx_ring->next_to_use;
1156
1157 context_desc = IGC_TX_CTXTDESC(tx_ring, i);
1158
1159 i++;
1160 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1161
1162 /* set bits to identify this as an advanced context descriptor */
1163 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
1164
1165 /* For i225, context index must be unique per ring. */
1166 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
1167 mss_l4len_idx |= tx_ring->reg_idx << 4;
1168
1169 if (first_flag)
1170 mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST;
1171
1172 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1173 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1174 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
1175 context_desc->launch_time = launch_time;
1176 }
1177
igc_tx_csum(struct igc_ring * tx_ring,struct igc_tx_buffer * first,__le32 launch_time,bool first_flag)1178 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first,
1179 __le32 launch_time, bool first_flag)
1180 {
1181 struct sk_buff *skb = first->skb;
1182 u32 vlan_macip_lens = 0;
1183 u32 type_tucmd = 0;
1184
1185 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1186 csum_failed:
1187 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&
1188 !tx_ring->launchtime_enable)
1189 return;
1190 goto no_csum;
1191 }
1192
1193 switch (skb->csum_offset) {
1194 case offsetof(struct tcphdr, check):
1195 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1196 fallthrough;
1197 case offsetof(struct udphdr, check):
1198 break;
1199 case offsetof(struct sctphdr, checksum):
1200 /* validate that this is actually an SCTP request */
1201 if (skb_csum_is_sctp(skb)) {
1202 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;
1203 break;
1204 }
1205 fallthrough;
1206 default:
1207 skb_checksum_help(skb);
1208 goto csum_failed;
1209 }
1210
1211 /* update TX checksum flag */
1212 first->tx_flags |= IGC_TX_FLAGS_CSUM;
1213 vlan_macip_lens = skb_checksum_start_offset(skb) -
1214 skb_network_offset(skb);
1215 no_csum:
1216 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
1217 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1218
1219 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
1220 vlan_macip_lens, type_tucmd, 0);
1221 }
1222
__igc_maybe_stop_tx(struct igc_ring * tx_ring,const u16 size)1223 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1224 {
1225 struct net_device *netdev = tx_ring->netdev;
1226
1227 netif_stop_subqueue(netdev, tx_ring->queue_index);
1228
1229 /* memory barriier comment */
1230 smp_mb();
1231
1232 /* We need to check again in a case another CPU has just
1233 * made room available.
1234 */
1235 if (igc_desc_unused(tx_ring) < size)
1236 return -EBUSY;
1237
1238 /* A reprieve! */
1239 netif_wake_subqueue(netdev, tx_ring->queue_index);
1240
1241 u64_stats_update_begin(&tx_ring->tx_syncp2);
1242 tx_ring->tx_stats.restart_queue2++;
1243 u64_stats_update_end(&tx_ring->tx_syncp2);
1244
1245 return 0;
1246 }
1247
igc_maybe_stop_tx(struct igc_ring * tx_ring,const u16 size)1248 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1249 {
1250 if (igc_desc_unused(tx_ring) >= size)
1251 return 0;
1252 return __igc_maybe_stop_tx(tx_ring, size);
1253 }
1254
1255 #define IGC_SET_FLAG(_input, _flag, _result) \
1256 (((_flag) <= (_result)) ? \
1257 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1258 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1259
igc_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)1260 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
1261 {
1262 /* set type for advanced descriptor with frame checksum insertion */
1263 u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
1264 IGC_ADVTXD_DCMD_DEXT |
1265 IGC_ADVTXD_DCMD_IFCS;
1266
1267 /* set HW vlan bit if vlan is present */
1268 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN,
1269 IGC_ADVTXD_DCMD_VLE);
1270
1271 /* set segmentation bits for TSO */
1272 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,
1273 (IGC_ADVTXD_DCMD_TSE));
1274
1275 /* set timestamp bit if present, will select the register set
1276 * based on the _TSTAMP(_X) bit.
1277 */
1278 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,
1279 (IGC_ADVTXD_MAC_TSTAMP));
1280
1281 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_1,
1282 (IGC_ADVTXD_TSTAMP_REG_1));
1283
1284 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_2,
1285 (IGC_ADVTXD_TSTAMP_REG_2));
1286
1287 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_3,
1288 (IGC_ADVTXD_TSTAMP_REG_3));
1289
1290 /* insert frame checksum */
1291 cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS);
1292
1293 return cmd_type;
1294 }
1295
igc_tx_olinfo_status(struct igc_ring * tx_ring,union igc_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)1296 static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
1297 union igc_adv_tx_desc *tx_desc,
1298 u32 tx_flags, unsigned int paylen)
1299 {
1300 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;
1301
1302 /* insert L4 checksum */
1303 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) *
1304 ((IGC_TXD_POPTS_TXSM << 8) /
1305 IGC_TX_FLAGS_CSUM);
1306
1307 /* insert IPv4 checksum */
1308 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) *
1309 (((IGC_TXD_POPTS_IXSM << 8)) /
1310 IGC_TX_FLAGS_IPV4);
1311
1312 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1313 }
1314
igc_tx_map(struct igc_ring * tx_ring,struct igc_tx_buffer * first,const u8 hdr_len)1315 static int igc_tx_map(struct igc_ring *tx_ring,
1316 struct igc_tx_buffer *first,
1317 const u8 hdr_len)
1318 {
1319 struct sk_buff *skb = first->skb;
1320 struct igc_tx_buffer *tx_buffer;
1321 union igc_adv_tx_desc *tx_desc;
1322 u32 tx_flags = first->tx_flags;
1323 skb_frag_t *frag;
1324 u16 i = tx_ring->next_to_use;
1325 unsigned int data_len, size;
1326 dma_addr_t dma;
1327 u32 cmd_type;
1328
1329 cmd_type = igc_tx_cmd_type(skb, tx_flags);
1330 tx_desc = IGC_TX_DESC(tx_ring, i);
1331
1332 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
1333
1334 size = skb_headlen(skb);
1335 data_len = skb->data_len;
1336
1337 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1338
1339 tx_buffer = first;
1340
1341 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1342 if (dma_mapping_error(tx_ring->dev, dma))
1343 goto dma_error;
1344
1345 /* record length, and DMA address */
1346 dma_unmap_len_set(tx_buffer, len, size);
1347 dma_unmap_addr_set(tx_buffer, dma, dma);
1348
1349 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1350
1351 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
1352 tx_desc->read.cmd_type_len =
1353 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);
1354
1355 i++;
1356 tx_desc++;
1357 if (i == tx_ring->count) {
1358 tx_desc = IGC_TX_DESC(tx_ring, 0);
1359 i = 0;
1360 }
1361 tx_desc->read.olinfo_status = 0;
1362
1363 dma += IGC_MAX_DATA_PER_TXD;
1364 size -= IGC_MAX_DATA_PER_TXD;
1365
1366 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1367 }
1368
1369 if (likely(!data_len))
1370 break;
1371
1372 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1373
1374 i++;
1375 tx_desc++;
1376 if (i == tx_ring->count) {
1377 tx_desc = IGC_TX_DESC(tx_ring, 0);
1378 i = 0;
1379 }
1380 tx_desc->read.olinfo_status = 0;
1381
1382 size = skb_frag_size(frag);
1383 data_len -= size;
1384
1385 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
1386 size, DMA_TO_DEVICE);
1387
1388 tx_buffer = &tx_ring->tx_buffer_info[i];
1389 }
1390
1391 /* write last descriptor with RS and EOP bits */
1392 cmd_type |= size | IGC_TXD_DCMD;
1393 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1394
1395 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1396
1397 /* set the timestamp */
1398 first->time_stamp = jiffies;
1399
1400 skb_tx_timestamp(skb);
1401
1402 /* Force memory writes to complete before letting h/w know there
1403 * are new descriptors to fetch. (Only applicable for weak-ordered
1404 * memory model archs, such as IA-64).
1405 *
1406 * We also need this memory barrier to make certain all of the
1407 * status bits have been updated before next_to_watch is written.
1408 */
1409 wmb();
1410
1411 /* set next_to_watch value indicating a packet is present */
1412 first->next_to_watch = tx_desc;
1413
1414 i++;
1415 if (i == tx_ring->count)
1416 i = 0;
1417
1418 tx_ring->next_to_use = i;
1419
1420 /* Make sure there is space in the ring for the next send. */
1421 igc_maybe_stop_tx(tx_ring, DESC_NEEDED);
1422
1423 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
1424 writel(i, tx_ring->tail);
1425 }
1426
1427 return 0;
1428 dma_error:
1429 netdev_err(tx_ring->netdev, "TX DMA map failed\n");
1430 tx_buffer = &tx_ring->tx_buffer_info[i];
1431
1432 /* clear dma mappings for failed tx_buffer_info map */
1433 while (tx_buffer != first) {
1434 if (dma_unmap_len(tx_buffer, len))
1435 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
1436
1437 if (i-- == 0)
1438 i += tx_ring->count;
1439 tx_buffer = &tx_ring->tx_buffer_info[i];
1440 }
1441
1442 if (dma_unmap_len(tx_buffer, len))
1443 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
1444
1445 dev_kfree_skb_any(tx_buffer->skb);
1446 tx_buffer->skb = NULL;
1447
1448 tx_ring->next_to_use = i;
1449
1450 return -1;
1451 }
1452
igc_tso(struct igc_ring * tx_ring,struct igc_tx_buffer * first,__le32 launch_time,bool first_flag,u8 * hdr_len)1453 static int igc_tso(struct igc_ring *tx_ring,
1454 struct igc_tx_buffer *first,
1455 __le32 launch_time, bool first_flag,
1456 u8 *hdr_len)
1457 {
1458 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1459 struct sk_buff *skb = first->skb;
1460 union {
1461 struct iphdr *v4;
1462 struct ipv6hdr *v6;
1463 unsigned char *hdr;
1464 } ip;
1465 union {
1466 struct tcphdr *tcp;
1467 struct udphdr *udp;
1468 unsigned char *hdr;
1469 } l4;
1470 u32 paylen, l4_offset;
1471 int err;
1472
1473 if (skb->ip_summed != CHECKSUM_PARTIAL)
1474 return 0;
1475
1476 if (!skb_is_gso(skb))
1477 return 0;
1478
1479 err = skb_cow_head(skb, 0);
1480 if (err < 0)
1481 return err;
1482
1483 ip.hdr = skb_network_header(skb);
1484 l4.hdr = skb_checksum_start(skb);
1485
1486 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
1487 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1488
1489 /* initialize outer IP header fields */
1490 if (ip.v4->version == 4) {
1491 unsigned char *csum_start = skb_checksum_start(skb);
1492 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
1493
1494 /* IP header will have to cancel out any data that
1495 * is not a part of the outer IP header
1496 */
1497 ip.v4->check = csum_fold(csum_partial(trans_start,
1498 csum_start - trans_start,
1499 0));
1500 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;
1501
1502 ip.v4->tot_len = 0;
1503 first->tx_flags |= IGC_TX_FLAGS_TSO |
1504 IGC_TX_FLAGS_CSUM |
1505 IGC_TX_FLAGS_IPV4;
1506 } else {
1507 ip.v6->payload_len = 0;
1508 first->tx_flags |= IGC_TX_FLAGS_TSO |
1509 IGC_TX_FLAGS_CSUM;
1510 }
1511
1512 /* determine offset of inner transport header */
1513 l4_offset = l4.hdr - skb->data;
1514
1515 /* remove payload length from inner checksum */
1516 paylen = skb->len - l4_offset;
1517 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {
1518 /* compute length of segmentation header */
1519 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1520 csum_replace_by_diff(&l4.tcp->check,
1521 (__force __wsum)htonl(paylen));
1522 } else {
1523 /* compute length of segmentation header */
1524 *hdr_len = sizeof(*l4.udp) + l4_offset;
1525 csum_replace_by_diff(&l4.udp->check,
1526 (__force __wsum)htonl(paylen));
1527 }
1528
1529 /* update gso size and bytecount with header size */
1530 first->gso_segs = skb_shinfo(skb)->gso_segs;
1531 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1532
1533 /* MSS L4LEN IDX */
1534 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;
1535 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;
1536
1537 /* VLAN MACLEN IPLEN */
1538 vlan_macip_lens = l4.hdr - ip.hdr;
1539 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
1540 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1541
1542 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
1543 vlan_macip_lens, type_tucmd, mss_l4len_idx);
1544
1545 return 1;
1546 }
1547
igc_request_tx_tstamp(struct igc_adapter * adapter,struct sk_buff * skb,u32 * flags)1548 static bool igc_request_tx_tstamp(struct igc_adapter *adapter, struct sk_buff *skb, u32 *flags)
1549 {
1550 int i;
1551
1552 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
1553 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
1554
1555 if (tstamp->skb)
1556 continue;
1557
1558 tstamp->skb = skb_get(skb);
1559 tstamp->start = jiffies;
1560 *flags = tstamp->flags;
1561
1562 return true;
1563 }
1564
1565 return false;
1566 }
1567
igc_xmit_frame_ring(struct sk_buff * skb,struct igc_ring * tx_ring)1568 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
1569 struct igc_ring *tx_ring)
1570 {
1571 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
1572 bool first_flag = false, insert_empty = false;
1573 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1574 __be16 protocol = vlan_get_protocol(skb);
1575 struct igc_tx_buffer *first;
1576 __le32 launch_time = 0;
1577 u32 tx_flags = 0;
1578 unsigned short f;
1579 ktime_t txtime;
1580 u8 hdr_len = 0;
1581 int tso = 0;
1582
1583 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
1584 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
1585 * + 2 desc gap to keep tail from touching head,
1586 * + 1 desc for context descriptor,
1587 * otherwise try next time
1588 */
1589 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1590 count += TXD_USE_COUNT(skb_frag_size(
1591 &skb_shinfo(skb)->frags[f]));
1592
1593 if (igc_maybe_stop_tx(tx_ring, count + 5)) {
1594 /* this is a hard error */
1595 return NETDEV_TX_BUSY;
1596 }
1597
1598 if (!tx_ring->launchtime_enable)
1599 goto done;
1600
1601 txtime = skb->tstamp;
1602 skb->tstamp = ktime_set(0, 0);
1603 launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty);
1604
1605 if (insert_empty) {
1606 struct igc_tx_buffer *empty_info;
1607 struct sk_buff *empty;
1608 void *data;
1609
1610 empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1611 empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC);
1612 if (!empty)
1613 goto done;
1614
1615 data = skb_put(empty, IGC_EMPTY_FRAME_SIZE);
1616 memset(data, 0, IGC_EMPTY_FRAME_SIZE);
1617
1618 igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0);
1619
1620 if (igc_init_tx_empty_descriptor(tx_ring,
1621 empty,
1622 empty_info) < 0)
1623 dev_kfree_skb_any(empty);
1624 }
1625
1626 done:
1627 /* record the location of the first descriptor for this packet */
1628 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1629 first->type = IGC_TX_BUFFER_TYPE_SKB;
1630 first->skb = skb;
1631 first->bytecount = skb->len;
1632 first->gso_segs = 1;
1633
1634 if (adapter->qbv_transition || tx_ring->oper_gate_closed)
1635 goto out_drop;
1636
1637 if (tx_ring->max_sdu > 0 && first->bytecount > tx_ring->max_sdu) {
1638 adapter->stats.txdrop++;
1639 goto out_drop;
1640 }
1641
1642 if (unlikely(test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags) &&
1643 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
1644 unsigned long flags;
1645 u32 tstamp_flags;
1646
1647 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
1648 if (igc_request_tx_tstamp(adapter, skb, &tstamp_flags)) {
1649 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1650 tx_flags |= IGC_TX_FLAGS_TSTAMP | tstamp_flags;
1651 } else {
1652 adapter->tx_hwtstamp_skipped++;
1653 }
1654
1655 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
1656 }
1657
1658 if (skb_vlan_tag_present(skb)) {
1659 tx_flags |= IGC_TX_FLAGS_VLAN;
1660 tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT);
1661 }
1662
1663 /* record initial flags and protocol */
1664 first->tx_flags = tx_flags;
1665 first->protocol = protocol;
1666
1667 tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len);
1668 if (tso < 0)
1669 goto out_drop;
1670 else if (!tso)
1671 igc_tx_csum(tx_ring, first, launch_time, first_flag);
1672
1673 igc_tx_map(tx_ring, first, hdr_len);
1674
1675 return NETDEV_TX_OK;
1676
1677 out_drop:
1678 dev_kfree_skb_any(first->skb);
1679 first->skb = NULL;
1680
1681 return NETDEV_TX_OK;
1682 }
1683
igc_tx_queue_mapping(struct igc_adapter * adapter,struct sk_buff * skb)1684 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
1685 struct sk_buff *skb)
1686 {
1687 unsigned int r_idx = skb->queue_mapping;
1688
1689 if (r_idx >= adapter->num_tx_queues)
1690 r_idx = r_idx % adapter->num_tx_queues;
1691
1692 return adapter->tx_ring[r_idx];
1693 }
1694
igc_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1695 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
1696 struct net_device *netdev)
1697 {
1698 struct igc_adapter *adapter = netdev_priv(netdev);
1699
1700 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1701 * in order to meet this minimum size requirement.
1702 */
1703 if (skb->len < 17) {
1704 if (skb_padto(skb, 17))
1705 return NETDEV_TX_OK;
1706 skb->len = 17;
1707 }
1708
1709 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
1710 }
1711
igc_rx_checksum(struct igc_ring * ring,union igc_adv_rx_desc * rx_desc,struct sk_buff * skb)1712 static void igc_rx_checksum(struct igc_ring *ring,
1713 union igc_adv_rx_desc *rx_desc,
1714 struct sk_buff *skb)
1715 {
1716 skb_checksum_none_assert(skb);
1717
1718 /* Ignore Checksum bit is set */
1719 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))
1720 return;
1721
1722 /* Rx checksum disabled via ethtool */
1723 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1724 return;
1725
1726 /* TCP/UDP checksum error bit is set */
1727 if (igc_test_staterr(rx_desc,
1728 IGC_RXDEXT_STATERR_L4E |
1729 IGC_RXDEXT_STATERR_IPE)) {
1730 /* work around errata with sctp packets where the TCPE aka
1731 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
1732 * packets (aka let the stack check the crc32c)
1733 */
1734 if (!(skb->len == 60 &&
1735 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
1736 u64_stats_update_begin(&ring->rx_syncp);
1737 ring->rx_stats.csum_err++;
1738 u64_stats_update_end(&ring->rx_syncp);
1739 }
1740 /* let the stack verify checksum errors */
1741 return;
1742 }
1743 /* It must be a TCP or UDP packet with a valid checksum */
1744 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |
1745 IGC_RXD_STAT_UDPCS))
1746 skb->ip_summed = CHECKSUM_UNNECESSARY;
1747
1748 netdev_dbg(ring->netdev, "cksum success: bits %08X\n",
1749 le32_to_cpu(rx_desc->wb.upper.status_error));
1750 }
1751
1752 /* Mapping HW RSS Type to enum pkt_hash_types */
1753 static const enum pkt_hash_types igc_rss_type_table[IGC_RSS_TYPE_MAX_TABLE] = {
1754 [IGC_RSS_TYPE_NO_HASH] = PKT_HASH_TYPE_L2,
1755 [IGC_RSS_TYPE_HASH_TCP_IPV4] = PKT_HASH_TYPE_L4,
1756 [IGC_RSS_TYPE_HASH_IPV4] = PKT_HASH_TYPE_L3,
1757 [IGC_RSS_TYPE_HASH_TCP_IPV6] = PKT_HASH_TYPE_L4,
1758 [IGC_RSS_TYPE_HASH_IPV6_EX] = PKT_HASH_TYPE_L3,
1759 [IGC_RSS_TYPE_HASH_IPV6] = PKT_HASH_TYPE_L3,
1760 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = PKT_HASH_TYPE_L4,
1761 [IGC_RSS_TYPE_HASH_UDP_IPV4] = PKT_HASH_TYPE_L4,
1762 [IGC_RSS_TYPE_HASH_UDP_IPV6] = PKT_HASH_TYPE_L4,
1763 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = PKT_HASH_TYPE_L4,
1764 [10] = PKT_HASH_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */
1765 [11] = PKT_HASH_TYPE_NONE, /* keep array sized for SW bit-mask */
1766 [12] = PKT_HASH_TYPE_NONE, /* to handle future HW revisons */
1767 [13] = PKT_HASH_TYPE_NONE,
1768 [14] = PKT_HASH_TYPE_NONE,
1769 [15] = PKT_HASH_TYPE_NONE,
1770 };
1771
igc_rx_hash(struct igc_ring * ring,union igc_adv_rx_desc * rx_desc,struct sk_buff * skb)1772 static inline void igc_rx_hash(struct igc_ring *ring,
1773 union igc_adv_rx_desc *rx_desc,
1774 struct sk_buff *skb)
1775 {
1776 if (ring->netdev->features & NETIF_F_RXHASH) {
1777 u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1778 u32 rss_type = igc_rss_type(rx_desc);
1779
1780 skb_set_hash(skb, rss_hash, igc_rss_type_table[rss_type]);
1781 }
1782 }
1783
igc_rx_vlan(struct igc_ring * rx_ring,union igc_adv_rx_desc * rx_desc,struct sk_buff * skb)1784 static void igc_rx_vlan(struct igc_ring *rx_ring,
1785 union igc_adv_rx_desc *rx_desc,
1786 struct sk_buff *skb)
1787 {
1788 struct net_device *dev = rx_ring->netdev;
1789 u16 vid;
1790
1791 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1792 igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) {
1793 if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) &&
1794 test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
1795 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
1796 else
1797 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1798
1799 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1800 }
1801 }
1802
1803 /**
1804 * igc_process_skb_fields - Populate skb header fields from Rx descriptor
1805 * @rx_ring: rx descriptor ring packet is being transacted on
1806 * @rx_desc: pointer to the EOP Rx descriptor
1807 * @skb: pointer to current skb being populated
1808 *
1809 * This function checks the ring, descriptor, and packet information in order
1810 * to populate the hash, checksum, VLAN, protocol, and other fields within the
1811 * skb.
1812 */
igc_process_skb_fields(struct igc_ring * rx_ring,union igc_adv_rx_desc * rx_desc,struct sk_buff * skb)1813 static void igc_process_skb_fields(struct igc_ring *rx_ring,
1814 union igc_adv_rx_desc *rx_desc,
1815 struct sk_buff *skb)
1816 {
1817 igc_rx_hash(rx_ring, rx_desc, skb);
1818
1819 igc_rx_checksum(rx_ring, rx_desc, skb);
1820
1821 igc_rx_vlan(rx_ring, rx_desc, skb);
1822
1823 skb_record_rx_queue(skb, rx_ring->queue_index);
1824
1825 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1826 }
1827
igc_vlan_mode(struct net_device * netdev,netdev_features_t features)1828 static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features)
1829 {
1830 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1831 struct igc_adapter *adapter = netdev_priv(netdev);
1832 struct igc_hw *hw = &adapter->hw;
1833 u32 ctrl;
1834
1835 ctrl = rd32(IGC_CTRL);
1836
1837 if (enable) {
1838 /* enable VLAN tag insert/strip */
1839 ctrl |= IGC_CTRL_VME;
1840 } else {
1841 /* disable VLAN tag insert/strip */
1842 ctrl &= ~IGC_CTRL_VME;
1843 }
1844 wr32(IGC_CTRL, ctrl);
1845 }
1846
igc_restore_vlan(struct igc_adapter * adapter)1847 static void igc_restore_vlan(struct igc_adapter *adapter)
1848 {
1849 igc_vlan_mode(adapter->netdev, adapter->netdev->features);
1850 }
1851
igc_get_rx_buffer(struct igc_ring * rx_ring,const unsigned int size,int * rx_buffer_pgcnt)1852 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
1853 const unsigned int size,
1854 int *rx_buffer_pgcnt)
1855 {
1856 struct igc_rx_buffer *rx_buffer;
1857
1858 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1859 *rx_buffer_pgcnt =
1860 #if (PAGE_SIZE < 8192)
1861 page_count(rx_buffer->page);
1862 #else
1863 0;
1864 #endif
1865 prefetchw(rx_buffer->page);
1866
1867 /* we are reusing so sync this buffer for CPU use */
1868 dma_sync_single_range_for_cpu(rx_ring->dev,
1869 rx_buffer->dma,
1870 rx_buffer->page_offset,
1871 size,
1872 DMA_FROM_DEVICE);
1873
1874 rx_buffer->pagecnt_bias--;
1875
1876 return rx_buffer;
1877 }
1878
igc_rx_buffer_flip(struct igc_rx_buffer * buffer,unsigned int truesize)1879 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer,
1880 unsigned int truesize)
1881 {
1882 #if (PAGE_SIZE < 8192)
1883 buffer->page_offset ^= truesize;
1884 #else
1885 buffer->page_offset += truesize;
1886 #endif
1887 }
1888
igc_get_rx_frame_truesize(struct igc_ring * ring,unsigned int size)1889 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring,
1890 unsigned int size)
1891 {
1892 unsigned int truesize;
1893
1894 #if (PAGE_SIZE < 8192)
1895 truesize = igc_rx_pg_size(ring) / 2;
1896 #else
1897 truesize = ring_uses_build_skb(ring) ?
1898 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1899 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1900 SKB_DATA_ALIGN(size);
1901 #endif
1902 return truesize;
1903 }
1904
1905 /**
1906 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
1907 * @rx_ring: rx descriptor ring to transact packets on
1908 * @rx_buffer: buffer containing page to add
1909 * @skb: sk_buff to place the data into
1910 * @size: size of buffer to be added
1911 *
1912 * This function will add the data contained in rx_buffer->page to the skb.
1913 */
igc_add_rx_frag(struct igc_ring * rx_ring,struct igc_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)1914 static void igc_add_rx_frag(struct igc_ring *rx_ring,
1915 struct igc_rx_buffer *rx_buffer,
1916 struct sk_buff *skb,
1917 unsigned int size)
1918 {
1919 unsigned int truesize;
1920
1921 #if (PAGE_SIZE < 8192)
1922 truesize = igc_rx_pg_size(rx_ring) / 2;
1923 #else
1924 truesize = ring_uses_build_skb(rx_ring) ?
1925 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1926 SKB_DATA_ALIGN(size);
1927 #endif
1928 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1929 rx_buffer->page_offset, size, truesize);
1930
1931 igc_rx_buffer_flip(rx_buffer, truesize);
1932 }
1933
igc_build_skb(struct igc_ring * rx_ring,struct igc_rx_buffer * rx_buffer,struct xdp_buff * xdp)1934 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
1935 struct igc_rx_buffer *rx_buffer,
1936 struct xdp_buff *xdp)
1937 {
1938 unsigned int size = xdp->data_end - xdp->data;
1939 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1940 unsigned int metasize = xdp->data - xdp->data_meta;
1941 struct sk_buff *skb;
1942
1943 /* prefetch first cache line of first page */
1944 net_prefetch(xdp->data_meta);
1945
1946 /* build an skb around the page buffer */
1947 skb = napi_build_skb(xdp->data_hard_start, truesize);
1948 if (unlikely(!skb))
1949 return NULL;
1950
1951 /* update pointers within the skb to store the data */
1952 skb_reserve(skb, xdp->data - xdp->data_hard_start);
1953 __skb_put(skb, size);
1954 if (metasize)
1955 skb_metadata_set(skb, metasize);
1956
1957 igc_rx_buffer_flip(rx_buffer, truesize);
1958 return skb;
1959 }
1960
igc_construct_skb(struct igc_ring * rx_ring,struct igc_rx_buffer * rx_buffer,struct xdp_buff * xdp,ktime_t timestamp)1961 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
1962 struct igc_rx_buffer *rx_buffer,
1963 struct xdp_buff *xdp,
1964 ktime_t timestamp)
1965 {
1966 unsigned int metasize = xdp->data - xdp->data_meta;
1967 unsigned int size = xdp->data_end - xdp->data;
1968 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1969 void *va = xdp->data;
1970 unsigned int headlen;
1971 struct sk_buff *skb;
1972
1973 /* prefetch first cache line of first page */
1974 net_prefetch(xdp->data_meta);
1975
1976 /* allocate a skb to store the frags */
1977 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1978 IGC_RX_HDR_LEN + metasize);
1979 if (unlikely(!skb))
1980 return NULL;
1981
1982 if (timestamp)
1983 skb_hwtstamps(skb)->hwtstamp = timestamp;
1984
1985 /* Determine available headroom for copy */
1986 headlen = size;
1987 if (headlen > IGC_RX_HDR_LEN)
1988 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);
1989
1990 /* align pull length to size of long to optimize memcpy performance */
1991 memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta,
1992 ALIGN(headlen + metasize, sizeof(long)));
1993
1994 if (metasize) {
1995 skb_metadata_set(skb, metasize);
1996 __skb_pull(skb, metasize);
1997 }
1998
1999 /* update all of the pointers */
2000 size -= headlen;
2001 if (size) {
2002 skb_add_rx_frag(skb, 0, rx_buffer->page,
2003 (va + headlen) - page_address(rx_buffer->page),
2004 size, truesize);
2005 igc_rx_buffer_flip(rx_buffer, truesize);
2006 } else {
2007 rx_buffer->pagecnt_bias++;
2008 }
2009
2010 return skb;
2011 }
2012
2013 /**
2014 * igc_reuse_rx_page - page flip buffer and store it back on the ring
2015 * @rx_ring: rx descriptor ring to store buffers on
2016 * @old_buff: donor buffer to have page reused
2017 *
2018 * Synchronizes page for reuse by the adapter
2019 */
igc_reuse_rx_page(struct igc_ring * rx_ring,struct igc_rx_buffer * old_buff)2020 static void igc_reuse_rx_page(struct igc_ring *rx_ring,
2021 struct igc_rx_buffer *old_buff)
2022 {
2023 u16 nta = rx_ring->next_to_alloc;
2024 struct igc_rx_buffer *new_buff;
2025
2026 new_buff = &rx_ring->rx_buffer_info[nta];
2027
2028 /* update, and store next to alloc */
2029 nta++;
2030 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
2031
2032 /* Transfer page from old buffer to new buffer.
2033 * Move each member individually to avoid possible store
2034 * forwarding stalls.
2035 */
2036 new_buff->dma = old_buff->dma;
2037 new_buff->page = old_buff->page;
2038 new_buff->page_offset = old_buff->page_offset;
2039 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
2040 }
2041
igc_can_reuse_rx_page(struct igc_rx_buffer * rx_buffer,int rx_buffer_pgcnt)2042 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer,
2043 int rx_buffer_pgcnt)
2044 {
2045 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
2046 struct page *page = rx_buffer->page;
2047
2048 /* avoid re-using remote and pfmemalloc pages */
2049 if (!dev_page_is_reusable(page))
2050 return false;
2051
2052 #if (PAGE_SIZE < 8192)
2053 /* if we are only owner of page we can reuse it */
2054 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
2055 return false;
2056 #else
2057 #define IGC_LAST_OFFSET \
2058 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)
2059
2060 if (rx_buffer->page_offset > IGC_LAST_OFFSET)
2061 return false;
2062 #endif
2063
2064 /* If we have drained the page fragment pool we need to update
2065 * the pagecnt_bias and page count so that we fully restock the
2066 * number of references the driver holds.
2067 */
2068 if (unlikely(pagecnt_bias == 1)) {
2069 page_ref_add(page, USHRT_MAX - 1);
2070 rx_buffer->pagecnt_bias = USHRT_MAX;
2071 }
2072
2073 return true;
2074 }
2075
2076 /**
2077 * igc_is_non_eop - process handling of non-EOP buffers
2078 * @rx_ring: Rx ring being processed
2079 * @rx_desc: Rx descriptor for current buffer
2080 *
2081 * This function updates next to clean. If the buffer is an EOP buffer
2082 * this function exits returning false, otherwise it will place the
2083 * sk_buff in the next buffer to be chained and return true indicating
2084 * that this is in fact a non-EOP buffer.
2085 */
igc_is_non_eop(struct igc_ring * rx_ring,union igc_adv_rx_desc * rx_desc)2086 static bool igc_is_non_eop(struct igc_ring *rx_ring,
2087 union igc_adv_rx_desc *rx_desc)
2088 {
2089 u32 ntc = rx_ring->next_to_clean + 1;
2090
2091 /* fetch, update, and store next to clean */
2092 ntc = (ntc < rx_ring->count) ? ntc : 0;
2093 rx_ring->next_to_clean = ntc;
2094
2095 prefetch(IGC_RX_DESC(rx_ring, ntc));
2096
2097 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
2098 return false;
2099
2100 return true;
2101 }
2102
2103 /**
2104 * igc_cleanup_headers - Correct corrupted or empty headers
2105 * @rx_ring: rx descriptor ring packet is being transacted on
2106 * @rx_desc: pointer to the EOP Rx descriptor
2107 * @skb: pointer to current skb being fixed
2108 *
2109 * Address the case where we are pulling data in on pages only
2110 * and as such no data is present in the skb header.
2111 *
2112 * In addition if skb is not at least 60 bytes we need to pad it so that
2113 * it is large enough to qualify as a valid Ethernet frame.
2114 *
2115 * Returns true if an error was encountered and skb was freed.
2116 */
igc_cleanup_headers(struct igc_ring * rx_ring,union igc_adv_rx_desc * rx_desc,struct sk_buff * skb)2117 static bool igc_cleanup_headers(struct igc_ring *rx_ring,
2118 union igc_adv_rx_desc *rx_desc,
2119 struct sk_buff *skb)
2120 {
2121 /* XDP packets use error pointer so abort at this point */
2122 if (IS_ERR(skb))
2123 return true;
2124
2125 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {
2126 struct net_device *netdev = rx_ring->netdev;
2127
2128 if (!(netdev->features & NETIF_F_RXALL)) {
2129 dev_kfree_skb_any(skb);
2130 return true;
2131 }
2132 }
2133
2134 /* if eth_skb_pad returns an error the skb was freed */
2135 if (eth_skb_pad(skb))
2136 return true;
2137
2138 return false;
2139 }
2140
igc_put_rx_buffer(struct igc_ring * rx_ring,struct igc_rx_buffer * rx_buffer,int rx_buffer_pgcnt)2141 static void igc_put_rx_buffer(struct igc_ring *rx_ring,
2142 struct igc_rx_buffer *rx_buffer,
2143 int rx_buffer_pgcnt)
2144 {
2145 if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2146 /* hand second half of page back to the ring */
2147 igc_reuse_rx_page(rx_ring, rx_buffer);
2148 } else {
2149 /* We are not reusing the buffer so unmap it and free
2150 * any references we are holding to it
2151 */
2152 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2153 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
2154 IGC_RX_DMA_ATTR);
2155 __page_frag_cache_drain(rx_buffer->page,
2156 rx_buffer->pagecnt_bias);
2157 }
2158
2159 /* clear contents of rx_buffer */
2160 rx_buffer->page = NULL;
2161 }
2162
igc_rx_offset(struct igc_ring * rx_ring)2163 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
2164 {
2165 struct igc_adapter *adapter = rx_ring->q_vector->adapter;
2166
2167 if (ring_uses_build_skb(rx_ring))
2168 return IGC_SKB_PAD;
2169 if (igc_xdp_is_enabled(adapter))
2170 return XDP_PACKET_HEADROOM;
2171
2172 return 0;
2173 }
2174
igc_alloc_mapped_page(struct igc_ring * rx_ring,struct igc_rx_buffer * bi)2175 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
2176 struct igc_rx_buffer *bi)
2177 {
2178 struct page *page = bi->page;
2179 dma_addr_t dma;
2180
2181 /* since we are recycling buffers we should seldom need to alloc */
2182 if (likely(page))
2183 return true;
2184
2185 /* alloc new page for storage */
2186 page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
2187 if (unlikely(!page)) {
2188 rx_ring->rx_stats.alloc_failed++;
2189 return false;
2190 }
2191
2192 /* map page for use */
2193 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
2194 igc_rx_pg_size(rx_ring),
2195 DMA_FROM_DEVICE,
2196 IGC_RX_DMA_ATTR);
2197
2198 /* if mapping failed free memory back to system since
2199 * there isn't much point in holding memory we can't use
2200 */
2201 if (dma_mapping_error(rx_ring->dev, dma)) {
2202 __free_page(page);
2203
2204 rx_ring->rx_stats.alloc_failed++;
2205 return false;
2206 }
2207
2208 bi->dma = dma;
2209 bi->page = page;
2210 bi->page_offset = igc_rx_offset(rx_ring);
2211 page_ref_add(page, USHRT_MAX - 1);
2212 bi->pagecnt_bias = USHRT_MAX;
2213
2214 return true;
2215 }
2216
2217 /**
2218 * igc_alloc_rx_buffers - Replace used receive buffers; packet split
2219 * @rx_ring: rx descriptor ring
2220 * @cleaned_count: number of buffers to clean
2221 */
igc_alloc_rx_buffers(struct igc_ring * rx_ring,u16 cleaned_count)2222 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
2223 {
2224 union igc_adv_rx_desc *rx_desc;
2225 u16 i = rx_ring->next_to_use;
2226 struct igc_rx_buffer *bi;
2227 u16 bufsz;
2228
2229 /* nothing to do */
2230 if (!cleaned_count)
2231 return;
2232
2233 rx_desc = IGC_RX_DESC(rx_ring, i);
2234 bi = &rx_ring->rx_buffer_info[i];
2235 i -= rx_ring->count;
2236
2237 bufsz = igc_rx_bufsz(rx_ring);
2238
2239 do {
2240 if (!igc_alloc_mapped_page(rx_ring, bi))
2241 break;
2242
2243 /* sync the buffer for use by the device */
2244 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
2245 bi->page_offset, bufsz,
2246 DMA_FROM_DEVICE);
2247
2248 /* Refresh the desc even if buffer_addrs didn't change
2249 * because each write-back erases this info.
2250 */
2251 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
2252
2253 rx_desc++;
2254 bi++;
2255 i++;
2256 if (unlikely(!i)) {
2257 rx_desc = IGC_RX_DESC(rx_ring, 0);
2258 bi = rx_ring->rx_buffer_info;
2259 i -= rx_ring->count;
2260 }
2261
2262 /* clear the length for the next_to_use descriptor */
2263 rx_desc->wb.upper.length = 0;
2264
2265 cleaned_count--;
2266 } while (cleaned_count);
2267
2268 i += rx_ring->count;
2269
2270 if (rx_ring->next_to_use != i) {
2271 /* record the next descriptor to use */
2272 rx_ring->next_to_use = i;
2273
2274 /* update next to alloc since we have filled the ring */
2275 rx_ring->next_to_alloc = i;
2276
2277 /* Force memory writes to complete before letting h/w
2278 * know there are new descriptors to fetch. (Only
2279 * applicable for weak-ordered memory model archs,
2280 * such as IA-64).
2281 */
2282 wmb();
2283 writel(i, rx_ring->tail);
2284 }
2285 }
2286
igc_alloc_rx_buffers_zc(struct igc_ring * ring,u16 count)2287 static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count)
2288 {
2289 union igc_adv_rx_desc *desc;
2290 u16 i = ring->next_to_use;
2291 struct igc_rx_buffer *bi;
2292 dma_addr_t dma;
2293 bool ok = true;
2294
2295 if (!count)
2296 return ok;
2297
2298 XSK_CHECK_PRIV_TYPE(struct igc_xdp_buff);
2299
2300 desc = IGC_RX_DESC(ring, i);
2301 bi = &ring->rx_buffer_info[i];
2302 i -= ring->count;
2303
2304 do {
2305 bi->xdp = xsk_buff_alloc(ring->xsk_pool);
2306 if (!bi->xdp) {
2307 ok = false;
2308 break;
2309 }
2310
2311 dma = xsk_buff_xdp_get_dma(bi->xdp);
2312 desc->read.pkt_addr = cpu_to_le64(dma);
2313
2314 desc++;
2315 bi++;
2316 i++;
2317 if (unlikely(!i)) {
2318 desc = IGC_RX_DESC(ring, 0);
2319 bi = ring->rx_buffer_info;
2320 i -= ring->count;
2321 }
2322
2323 /* Clear the length for the next_to_use descriptor. */
2324 desc->wb.upper.length = 0;
2325
2326 count--;
2327 } while (count);
2328
2329 i += ring->count;
2330
2331 if (ring->next_to_use != i) {
2332 ring->next_to_use = i;
2333
2334 /* Force memory writes to complete before letting h/w
2335 * know there are new descriptors to fetch. (Only
2336 * applicable for weak-ordered memory model archs,
2337 * such as IA-64).
2338 */
2339 wmb();
2340 writel(i, ring->tail);
2341 }
2342
2343 return ok;
2344 }
2345
2346 /* This function requires __netif_tx_lock is held by the caller. */
igc_xdp_init_tx_descriptor(struct igc_ring * ring,struct xdp_frame * xdpf)2347 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring,
2348 struct xdp_frame *xdpf)
2349 {
2350 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
2351 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
2352 u16 count, index = ring->next_to_use;
2353 struct igc_tx_buffer *head = &ring->tx_buffer_info[index];
2354 struct igc_tx_buffer *buffer = head;
2355 union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index);
2356 u32 olinfo_status, len = xdpf->len, cmd_type;
2357 void *data = xdpf->data;
2358 u16 i;
2359
2360 count = TXD_USE_COUNT(len);
2361 for (i = 0; i < nr_frags; i++)
2362 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
2363
2364 if (igc_maybe_stop_tx(ring, count + 3)) {
2365 /* this is a hard error */
2366 return -EBUSY;
2367 }
2368
2369 i = 0;
2370 head->bytecount = xdp_get_frame_len(xdpf);
2371 head->type = IGC_TX_BUFFER_TYPE_XDP;
2372 head->gso_segs = 1;
2373 head->xdpf = xdpf;
2374
2375 olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
2376 desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2377
2378 for (;;) {
2379 dma_addr_t dma;
2380
2381 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE);
2382 if (dma_mapping_error(ring->dev, dma)) {
2383 netdev_err_once(ring->netdev,
2384 "Failed to map DMA for TX\n");
2385 goto unmap;
2386 }
2387
2388 dma_unmap_len_set(buffer, len, len);
2389 dma_unmap_addr_set(buffer, dma, dma);
2390
2391 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
2392 IGC_ADVTXD_DCMD_IFCS | len;
2393
2394 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
2395 desc->read.buffer_addr = cpu_to_le64(dma);
2396
2397 buffer->protocol = 0;
2398
2399 if (++index == ring->count)
2400 index = 0;
2401
2402 if (i == nr_frags)
2403 break;
2404
2405 buffer = &ring->tx_buffer_info[index];
2406 desc = IGC_TX_DESC(ring, index);
2407 desc->read.olinfo_status = 0;
2408
2409 data = skb_frag_address(&sinfo->frags[i]);
2410 len = skb_frag_size(&sinfo->frags[i]);
2411 i++;
2412 }
2413 desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD);
2414
2415 netdev_tx_sent_queue(txring_txq(ring), head->bytecount);
2416 /* set the timestamp */
2417 head->time_stamp = jiffies;
2418 /* set next_to_watch value indicating a packet is present */
2419 head->next_to_watch = desc;
2420 ring->next_to_use = index;
2421
2422 return 0;
2423
2424 unmap:
2425 for (;;) {
2426 buffer = &ring->tx_buffer_info[index];
2427 if (dma_unmap_len(buffer, len))
2428 dma_unmap_page(ring->dev,
2429 dma_unmap_addr(buffer, dma),
2430 dma_unmap_len(buffer, len),
2431 DMA_TO_DEVICE);
2432 dma_unmap_len_set(buffer, len, 0);
2433 if (buffer == head)
2434 break;
2435
2436 if (!index)
2437 index += ring->count;
2438 index--;
2439 }
2440
2441 return -ENOMEM;
2442 }
2443
igc_xdp_get_tx_ring(struct igc_adapter * adapter,int cpu)2444 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter,
2445 int cpu)
2446 {
2447 int index = cpu;
2448
2449 if (unlikely(index < 0))
2450 index = 0;
2451
2452 while (index >= adapter->num_tx_queues)
2453 index -= adapter->num_tx_queues;
2454
2455 return adapter->tx_ring[index];
2456 }
2457
igc_xdp_xmit_back(struct igc_adapter * adapter,struct xdp_buff * xdp)2458 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp)
2459 {
2460 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2461 int cpu = smp_processor_id();
2462 struct netdev_queue *nq;
2463 struct igc_ring *ring;
2464 int res;
2465
2466 if (unlikely(!xdpf))
2467 return -EFAULT;
2468
2469 ring = igc_xdp_get_tx_ring(adapter, cpu);
2470 nq = txring_txq(ring);
2471
2472 __netif_tx_lock(nq, cpu);
2473 /* Avoid transmit queue timeout since we share it with the slow path */
2474 txq_trans_cond_update(nq);
2475 res = igc_xdp_init_tx_descriptor(ring, xdpf);
2476 __netif_tx_unlock(nq);
2477 return res;
2478 }
2479
2480 /* This function assumes rcu_read_lock() is held by the caller. */
__igc_xdp_run_prog(struct igc_adapter * adapter,struct bpf_prog * prog,struct xdp_buff * xdp)2481 static int __igc_xdp_run_prog(struct igc_adapter *adapter,
2482 struct bpf_prog *prog,
2483 struct xdp_buff *xdp)
2484 {
2485 u32 act = bpf_prog_run_xdp(prog, xdp);
2486
2487 switch (act) {
2488 case XDP_PASS:
2489 return IGC_XDP_PASS;
2490 case XDP_TX:
2491 if (igc_xdp_xmit_back(adapter, xdp) < 0)
2492 goto out_failure;
2493 return IGC_XDP_TX;
2494 case XDP_REDIRECT:
2495 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0)
2496 goto out_failure;
2497 return IGC_XDP_REDIRECT;
2498 break;
2499 default:
2500 bpf_warn_invalid_xdp_action(adapter->netdev, prog, act);
2501 fallthrough;
2502 case XDP_ABORTED:
2503 out_failure:
2504 trace_xdp_exception(adapter->netdev, prog, act);
2505 fallthrough;
2506 case XDP_DROP:
2507 return IGC_XDP_CONSUMED;
2508 }
2509 }
2510
igc_xdp_run_prog(struct igc_adapter * adapter,struct xdp_buff * xdp)2511 static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter,
2512 struct xdp_buff *xdp)
2513 {
2514 struct bpf_prog *prog;
2515 int res;
2516
2517 prog = READ_ONCE(adapter->xdp_prog);
2518 if (!prog) {
2519 res = IGC_XDP_PASS;
2520 goto out;
2521 }
2522
2523 res = __igc_xdp_run_prog(adapter, prog, xdp);
2524
2525 out:
2526 return ERR_PTR(-res);
2527 }
2528
2529 /* This function assumes __netif_tx_lock is held by the caller. */
igc_flush_tx_descriptors(struct igc_ring * ring)2530 static void igc_flush_tx_descriptors(struct igc_ring *ring)
2531 {
2532 /* Once tail pointer is updated, hardware can fetch the descriptors
2533 * any time so we issue a write membar here to ensure all memory
2534 * writes are complete before the tail pointer is updated.
2535 */
2536 wmb();
2537 writel(ring->next_to_use, ring->tail);
2538 }
2539
igc_finalize_xdp(struct igc_adapter * adapter,int status)2540 static void igc_finalize_xdp(struct igc_adapter *adapter, int status)
2541 {
2542 int cpu = smp_processor_id();
2543 struct netdev_queue *nq;
2544 struct igc_ring *ring;
2545
2546 if (status & IGC_XDP_TX) {
2547 ring = igc_xdp_get_tx_ring(adapter, cpu);
2548 nq = txring_txq(ring);
2549
2550 __netif_tx_lock(nq, cpu);
2551 igc_flush_tx_descriptors(ring);
2552 __netif_tx_unlock(nq);
2553 }
2554
2555 if (status & IGC_XDP_REDIRECT)
2556 xdp_do_flush();
2557 }
2558
igc_update_rx_stats(struct igc_q_vector * q_vector,unsigned int packets,unsigned int bytes)2559 static void igc_update_rx_stats(struct igc_q_vector *q_vector,
2560 unsigned int packets, unsigned int bytes)
2561 {
2562 struct igc_ring *ring = q_vector->rx.ring;
2563
2564 u64_stats_update_begin(&ring->rx_syncp);
2565 ring->rx_stats.packets += packets;
2566 ring->rx_stats.bytes += bytes;
2567 u64_stats_update_end(&ring->rx_syncp);
2568
2569 q_vector->rx.total_packets += packets;
2570 q_vector->rx.total_bytes += bytes;
2571 }
2572
igc_clean_rx_irq(struct igc_q_vector * q_vector,const int budget)2573 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)
2574 {
2575 unsigned int total_bytes = 0, total_packets = 0;
2576 struct igc_adapter *adapter = q_vector->adapter;
2577 struct igc_ring *rx_ring = q_vector->rx.ring;
2578 struct sk_buff *skb = rx_ring->skb;
2579 u16 cleaned_count = igc_desc_unused(rx_ring);
2580 int xdp_status = 0, rx_buffer_pgcnt;
2581
2582 while (likely(total_packets < budget)) {
2583 union igc_adv_rx_desc *rx_desc;
2584 struct igc_rx_buffer *rx_buffer;
2585 unsigned int size, truesize;
2586 struct igc_xdp_buff ctx;
2587 ktime_t timestamp = 0;
2588 int pkt_offset = 0;
2589 void *pktbuf;
2590
2591 /* return some buffers to hardware, one at a time is too slow */
2592 if (cleaned_count >= IGC_RX_BUFFER_WRITE) {
2593 igc_alloc_rx_buffers(rx_ring, cleaned_count);
2594 cleaned_count = 0;
2595 }
2596
2597 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);
2598 size = le16_to_cpu(rx_desc->wb.upper.length);
2599 if (!size)
2600 break;
2601
2602 /* This memory barrier is needed to keep us from reading
2603 * any other fields out of the rx_desc until we know the
2604 * descriptor has been written back
2605 */
2606 dma_rmb();
2607
2608 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2609 truesize = igc_get_rx_frame_truesize(rx_ring, size);
2610
2611 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
2612
2613 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) {
2614 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter,
2615 pktbuf);
2616 ctx.rx_ts = timestamp;
2617 pkt_offset = IGC_TS_HDR_LEN;
2618 size -= IGC_TS_HDR_LEN;
2619 }
2620
2621 if (!skb) {
2622 xdp_init_buff(&ctx.xdp, truesize, &rx_ring->xdp_rxq);
2623 xdp_prepare_buff(&ctx.xdp, pktbuf - igc_rx_offset(rx_ring),
2624 igc_rx_offset(rx_ring) + pkt_offset,
2625 size, true);
2626 xdp_buff_clear_frags_flag(&ctx.xdp);
2627 ctx.rx_desc = rx_desc;
2628
2629 skb = igc_xdp_run_prog(adapter, &ctx.xdp);
2630 }
2631
2632 if (IS_ERR(skb)) {
2633 unsigned int xdp_res = -PTR_ERR(skb);
2634
2635 switch (xdp_res) {
2636 case IGC_XDP_CONSUMED:
2637 rx_buffer->pagecnt_bias++;
2638 break;
2639 case IGC_XDP_TX:
2640 case IGC_XDP_REDIRECT:
2641 igc_rx_buffer_flip(rx_buffer, truesize);
2642 xdp_status |= xdp_res;
2643 break;
2644 }
2645
2646 total_packets++;
2647 total_bytes += size;
2648 } else if (skb)
2649 igc_add_rx_frag(rx_ring, rx_buffer, skb, size);
2650 else if (ring_uses_build_skb(rx_ring))
2651 skb = igc_build_skb(rx_ring, rx_buffer, &ctx.xdp);
2652 else
2653 skb = igc_construct_skb(rx_ring, rx_buffer, &ctx.xdp,
2654 timestamp);
2655
2656 /* exit if we failed to retrieve a buffer */
2657 if (!skb) {
2658 rx_ring->rx_stats.alloc_failed++;
2659 rx_buffer->pagecnt_bias++;
2660 break;
2661 }
2662
2663 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2664 cleaned_count++;
2665
2666 /* fetch next buffer in frame if non-eop */
2667 if (igc_is_non_eop(rx_ring, rx_desc))
2668 continue;
2669
2670 /* verify the packet layout is correct */
2671 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {
2672 skb = NULL;
2673 continue;
2674 }
2675
2676 /* probably a little skewed due to removing CRC */
2677 total_bytes += skb->len;
2678
2679 /* populate checksum, VLAN, and protocol */
2680 igc_process_skb_fields(rx_ring, rx_desc, skb);
2681
2682 napi_gro_receive(&q_vector->napi, skb);
2683
2684 /* reset skb pointer */
2685 skb = NULL;
2686
2687 /* update budget accounting */
2688 total_packets++;
2689 }
2690
2691 if (xdp_status)
2692 igc_finalize_xdp(adapter, xdp_status);
2693
2694 /* place incomplete frames back on ring for completion */
2695 rx_ring->skb = skb;
2696
2697 igc_update_rx_stats(q_vector, total_packets, total_bytes);
2698
2699 if (cleaned_count)
2700 igc_alloc_rx_buffers(rx_ring, cleaned_count);
2701
2702 return total_packets;
2703 }
2704
igc_construct_skb_zc(struct igc_ring * ring,struct xdp_buff * xdp)2705 static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring,
2706 struct xdp_buff *xdp)
2707 {
2708 unsigned int totalsize = xdp->data_end - xdp->data_meta;
2709 unsigned int metasize = xdp->data - xdp->data_meta;
2710 struct sk_buff *skb;
2711
2712 net_prefetch(xdp->data_meta);
2713
2714 skb = __napi_alloc_skb(&ring->q_vector->napi, totalsize,
2715 GFP_ATOMIC | __GFP_NOWARN);
2716 if (unlikely(!skb))
2717 return NULL;
2718
2719 memcpy(__skb_put(skb, totalsize), xdp->data_meta,
2720 ALIGN(totalsize, sizeof(long)));
2721
2722 if (metasize) {
2723 skb_metadata_set(skb, metasize);
2724 __skb_pull(skb, metasize);
2725 }
2726
2727 return skb;
2728 }
2729
igc_dispatch_skb_zc(struct igc_q_vector * q_vector,union igc_adv_rx_desc * desc,struct xdp_buff * xdp,ktime_t timestamp)2730 static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector,
2731 union igc_adv_rx_desc *desc,
2732 struct xdp_buff *xdp,
2733 ktime_t timestamp)
2734 {
2735 struct igc_ring *ring = q_vector->rx.ring;
2736 struct sk_buff *skb;
2737
2738 skb = igc_construct_skb_zc(ring, xdp);
2739 if (!skb) {
2740 ring->rx_stats.alloc_failed++;
2741 return;
2742 }
2743
2744 if (timestamp)
2745 skb_hwtstamps(skb)->hwtstamp = timestamp;
2746
2747 if (igc_cleanup_headers(ring, desc, skb))
2748 return;
2749
2750 igc_process_skb_fields(ring, desc, skb);
2751 napi_gro_receive(&q_vector->napi, skb);
2752 }
2753
xsk_buff_to_igc_ctx(struct xdp_buff * xdp)2754 static struct igc_xdp_buff *xsk_buff_to_igc_ctx(struct xdp_buff *xdp)
2755 {
2756 /* xdp_buff pointer used by ZC code path is alloc as xdp_buff_xsk. The
2757 * igc_xdp_buff shares its layout with xdp_buff_xsk and private
2758 * igc_xdp_buff fields fall into xdp_buff_xsk->cb
2759 */
2760 return (struct igc_xdp_buff *)xdp;
2761 }
2762
igc_clean_rx_irq_zc(struct igc_q_vector * q_vector,const int budget)2763 static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget)
2764 {
2765 struct igc_adapter *adapter = q_vector->adapter;
2766 struct igc_ring *ring = q_vector->rx.ring;
2767 u16 cleaned_count = igc_desc_unused(ring);
2768 int total_bytes = 0, total_packets = 0;
2769 u16 ntc = ring->next_to_clean;
2770 struct bpf_prog *prog;
2771 bool failure = false;
2772 int xdp_status = 0;
2773
2774 rcu_read_lock();
2775
2776 prog = READ_ONCE(adapter->xdp_prog);
2777
2778 while (likely(total_packets < budget)) {
2779 union igc_adv_rx_desc *desc;
2780 struct igc_rx_buffer *bi;
2781 struct igc_xdp_buff *ctx;
2782 ktime_t timestamp = 0;
2783 unsigned int size;
2784 int res;
2785
2786 desc = IGC_RX_DESC(ring, ntc);
2787 size = le16_to_cpu(desc->wb.upper.length);
2788 if (!size)
2789 break;
2790
2791 /* This memory barrier is needed to keep us from reading
2792 * any other fields out of the rx_desc until we know the
2793 * descriptor has been written back
2794 */
2795 dma_rmb();
2796
2797 bi = &ring->rx_buffer_info[ntc];
2798
2799 ctx = xsk_buff_to_igc_ctx(bi->xdp);
2800 ctx->rx_desc = desc;
2801
2802 if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) {
2803 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter,
2804 bi->xdp->data);
2805 ctx->rx_ts = timestamp;
2806
2807 bi->xdp->data += IGC_TS_HDR_LEN;
2808
2809 /* HW timestamp has been copied into local variable. Metadata
2810 * length when XDP program is called should be 0.
2811 */
2812 bi->xdp->data_meta += IGC_TS_HDR_LEN;
2813 size -= IGC_TS_HDR_LEN;
2814 }
2815
2816 bi->xdp->data_end = bi->xdp->data + size;
2817 xsk_buff_dma_sync_for_cpu(bi->xdp, ring->xsk_pool);
2818
2819 res = __igc_xdp_run_prog(adapter, prog, bi->xdp);
2820 switch (res) {
2821 case IGC_XDP_PASS:
2822 igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp);
2823 fallthrough;
2824 case IGC_XDP_CONSUMED:
2825 xsk_buff_free(bi->xdp);
2826 break;
2827 case IGC_XDP_TX:
2828 case IGC_XDP_REDIRECT:
2829 xdp_status |= res;
2830 break;
2831 }
2832
2833 bi->xdp = NULL;
2834 total_bytes += size;
2835 total_packets++;
2836 cleaned_count++;
2837 ntc++;
2838 if (ntc == ring->count)
2839 ntc = 0;
2840 }
2841
2842 ring->next_to_clean = ntc;
2843 rcu_read_unlock();
2844
2845 if (cleaned_count >= IGC_RX_BUFFER_WRITE)
2846 failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count);
2847
2848 if (xdp_status)
2849 igc_finalize_xdp(adapter, xdp_status);
2850
2851 igc_update_rx_stats(q_vector, total_packets, total_bytes);
2852
2853 if (xsk_uses_need_wakeup(ring->xsk_pool)) {
2854 if (failure || ring->next_to_clean == ring->next_to_use)
2855 xsk_set_rx_need_wakeup(ring->xsk_pool);
2856 else
2857 xsk_clear_rx_need_wakeup(ring->xsk_pool);
2858 return total_packets;
2859 }
2860
2861 return failure ? budget : total_packets;
2862 }
2863
igc_update_tx_stats(struct igc_q_vector * q_vector,unsigned int packets,unsigned int bytes)2864 static void igc_update_tx_stats(struct igc_q_vector *q_vector,
2865 unsigned int packets, unsigned int bytes)
2866 {
2867 struct igc_ring *ring = q_vector->tx.ring;
2868
2869 u64_stats_update_begin(&ring->tx_syncp);
2870 ring->tx_stats.bytes += bytes;
2871 ring->tx_stats.packets += packets;
2872 u64_stats_update_end(&ring->tx_syncp);
2873
2874 q_vector->tx.total_bytes += bytes;
2875 q_vector->tx.total_packets += packets;
2876 }
2877
igc_xdp_xmit_zc(struct igc_ring * ring)2878 static void igc_xdp_xmit_zc(struct igc_ring *ring)
2879 {
2880 struct xsk_buff_pool *pool = ring->xsk_pool;
2881 struct netdev_queue *nq = txring_txq(ring);
2882 union igc_adv_tx_desc *tx_desc = NULL;
2883 int cpu = smp_processor_id();
2884 struct xdp_desc xdp_desc;
2885 u16 budget, ntu;
2886
2887 if (!netif_carrier_ok(ring->netdev))
2888 return;
2889
2890 __netif_tx_lock(nq, cpu);
2891
2892 /* Avoid transmit queue timeout since we share it with the slow path */
2893 txq_trans_cond_update(nq);
2894
2895 ntu = ring->next_to_use;
2896 budget = igc_desc_unused(ring);
2897
2898 while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) {
2899 u32 cmd_type, olinfo_status;
2900 struct igc_tx_buffer *bi;
2901 dma_addr_t dma;
2902
2903 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
2904 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
2905 xdp_desc.len;
2906 olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT;
2907
2908 dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2909 xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len);
2910
2911 tx_desc = IGC_TX_DESC(ring, ntu);
2912 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
2913 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2914 tx_desc->read.buffer_addr = cpu_to_le64(dma);
2915
2916 bi = &ring->tx_buffer_info[ntu];
2917 bi->type = IGC_TX_BUFFER_TYPE_XSK;
2918 bi->protocol = 0;
2919 bi->bytecount = xdp_desc.len;
2920 bi->gso_segs = 1;
2921 bi->time_stamp = jiffies;
2922 bi->next_to_watch = tx_desc;
2923
2924 netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len);
2925
2926 ntu++;
2927 if (ntu == ring->count)
2928 ntu = 0;
2929 }
2930
2931 ring->next_to_use = ntu;
2932 if (tx_desc) {
2933 igc_flush_tx_descriptors(ring);
2934 xsk_tx_release(pool);
2935 }
2936
2937 __netif_tx_unlock(nq);
2938 }
2939
2940 /**
2941 * igc_clean_tx_irq - Reclaim resources after transmit completes
2942 * @q_vector: pointer to q_vector containing needed info
2943 * @napi_budget: Used to determine if we are in netpoll
2944 *
2945 * returns true if ring is completely cleaned
2946 */
igc_clean_tx_irq(struct igc_q_vector * q_vector,int napi_budget)2947 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)
2948 {
2949 struct igc_adapter *adapter = q_vector->adapter;
2950 unsigned int total_bytes = 0, total_packets = 0;
2951 unsigned int budget = q_vector->tx.work_limit;
2952 struct igc_ring *tx_ring = q_vector->tx.ring;
2953 unsigned int i = tx_ring->next_to_clean;
2954 struct igc_tx_buffer *tx_buffer;
2955 union igc_adv_tx_desc *tx_desc;
2956 u32 xsk_frames = 0;
2957
2958 if (test_bit(__IGC_DOWN, &adapter->state))
2959 return true;
2960
2961 tx_buffer = &tx_ring->tx_buffer_info[i];
2962 tx_desc = IGC_TX_DESC(tx_ring, i);
2963 i -= tx_ring->count;
2964
2965 do {
2966 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
2967
2968 /* if next_to_watch is not set then there is no work pending */
2969 if (!eop_desc)
2970 break;
2971
2972 /* prevent any other reads prior to eop_desc */
2973 smp_rmb();
2974
2975 /* if DD is not set pending work has not been completed */
2976 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))
2977 break;
2978
2979 /* clear next_to_watch to prevent false hangs */
2980 tx_buffer->next_to_watch = NULL;
2981
2982 /* update the statistics for this packet */
2983 total_bytes += tx_buffer->bytecount;
2984 total_packets += tx_buffer->gso_segs;
2985
2986 switch (tx_buffer->type) {
2987 case IGC_TX_BUFFER_TYPE_XSK:
2988 xsk_frames++;
2989 break;
2990 case IGC_TX_BUFFER_TYPE_XDP:
2991 xdp_return_frame(tx_buffer->xdpf);
2992 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
2993 break;
2994 case IGC_TX_BUFFER_TYPE_SKB:
2995 napi_consume_skb(tx_buffer->skb, napi_budget);
2996 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
2997 break;
2998 default:
2999 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");
3000 break;
3001 }
3002
3003 /* clear last DMA location and unmap remaining buffers */
3004 while (tx_desc != eop_desc) {
3005 tx_buffer++;
3006 tx_desc++;
3007 i++;
3008 if (unlikely(!i)) {
3009 i -= tx_ring->count;
3010 tx_buffer = tx_ring->tx_buffer_info;
3011 tx_desc = IGC_TX_DESC(tx_ring, 0);
3012 }
3013
3014 /* unmap any remaining paged data */
3015 if (dma_unmap_len(tx_buffer, len))
3016 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
3017 }
3018
3019 /* move us one more past the eop_desc for start of next pkt */
3020 tx_buffer++;
3021 tx_desc++;
3022 i++;
3023 if (unlikely(!i)) {
3024 i -= tx_ring->count;
3025 tx_buffer = tx_ring->tx_buffer_info;
3026 tx_desc = IGC_TX_DESC(tx_ring, 0);
3027 }
3028
3029 /* issue prefetch for next Tx descriptor */
3030 prefetch(tx_desc);
3031
3032 /* update budget accounting */
3033 budget--;
3034 } while (likely(budget));
3035
3036 netdev_tx_completed_queue(txring_txq(tx_ring),
3037 total_packets, total_bytes);
3038
3039 i += tx_ring->count;
3040 tx_ring->next_to_clean = i;
3041
3042 igc_update_tx_stats(q_vector, total_packets, total_bytes);
3043
3044 if (tx_ring->xsk_pool) {
3045 if (xsk_frames)
3046 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);
3047 if (xsk_uses_need_wakeup(tx_ring->xsk_pool))
3048 xsk_set_tx_need_wakeup(tx_ring->xsk_pool);
3049 igc_xdp_xmit_zc(tx_ring);
3050 }
3051
3052 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
3053 struct igc_hw *hw = &adapter->hw;
3054
3055 /* Detect a transmit hang in hardware, this serializes the
3056 * check with the clearing of time_stamp and movement of i
3057 */
3058 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3059 if (tx_buffer->next_to_watch &&
3060 time_after(jiffies, tx_buffer->time_stamp +
3061 (adapter->tx_timeout_factor * HZ)) &&
3062 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) &&
3063 (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) &&
3064 !tx_ring->oper_gate_closed) {
3065 /* detected Tx unit hang */
3066 netdev_err(tx_ring->netdev,
3067 "Detected Tx Unit Hang\n"
3068 " Tx Queue <%d>\n"
3069 " TDH <%x>\n"
3070 " TDT <%x>\n"
3071 " next_to_use <%x>\n"
3072 " next_to_clean <%x>\n"
3073 "buffer_info[next_to_clean]\n"
3074 " time_stamp <%lx>\n"
3075 " next_to_watch <%p>\n"
3076 " jiffies <%lx>\n"
3077 " desc.status <%x>\n",
3078 tx_ring->queue_index,
3079 rd32(IGC_TDH(tx_ring->reg_idx)),
3080 readl(tx_ring->tail),
3081 tx_ring->next_to_use,
3082 tx_ring->next_to_clean,
3083 tx_buffer->time_stamp,
3084 tx_buffer->next_to_watch,
3085 jiffies,
3086 tx_buffer->next_to_watch->wb.status);
3087 netif_stop_subqueue(tx_ring->netdev,
3088 tx_ring->queue_index);
3089
3090 /* we are about to reset, no point in enabling stuff */
3091 return true;
3092 }
3093 }
3094
3095 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
3096 if (unlikely(total_packets &&
3097 netif_carrier_ok(tx_ring->netdev) &&
3098 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
3099 /* Make sure that anybody stopping the queue after this
3100 * sees the new next_to_clean.
3101 */
3102 smp_mb();
3103 if (__netif_subqueue_stopped(tx_ring->netdev,
3104 tx_ring->queue_index) &&
3105 !(test_bit(__IGC_DOWN, &adapter->state))) {
3106 netif_wake_subqueue(tx_ring->netdev,
3107 tx_ring->queue_index);
3108
3109 u64_stats_update_begin(&tx_ring->tx_syncp);
3110 tx_ring->tx_stats.restart_queue++;
3111 u64_stats_update_end(&tx_ring->tx_syncp);
3112 }
3113 }
3114
3115 return !!budget;
3116 }
3117
igc_find_mac_filter(struct igc_adapter * adapter,enum igc_mac_filter_type type,const u8 * addr)3118 static int igc_find_mac_filter(struct igc_adapter *adapter,
3119 enum igc_mac_filter_type type, const u8 *addr)
3120 {
3121 struct igc_hw *hw = &adapter->hw;
3122 int max_entries = hw->mac.rar_entry_count;
3123 u32 ral, rah;
3124 int i;
3125
3126 for (i = 0; i < max_entries; i++) {
3127 ral = rd32(IGC_RAL(i));
3128 rah = rd32(IGC_RAH(i));
3129
3130 if (!(rah & IGC_RAH_AV))
3131 continue;
3132 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type)
3133 continue;
3134 if ((rah & IGC_RAH_RAH_MASK) !=
3135 le16_to_cpup((__le16 *)(addr + 4)))
3136 continue;
3137 if (ral != le32_to_cpup((__le32 *)(addr)))
3138 continue;
3139
3140 return i;
3141 }
3142
3143 return -1;
3144 }
3145
igc_get_avail_mac_filter_slot(struct igc_adapter * adapter)3146 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter)
3147 {
3148 struct igc_hw *hw = &adapter->hw;
3149 int max_entries = hw->mac.rar_entry_count;
3150 u32 rah;
3151 int i;
3152
3153 for (i = 0; i < max_entries; i++) {
3154 rah = rd32(IGC_RAH(i));
3155
3156 if (!(rah & IGC_RAH_AV))
3157 return i;
3158 }
3159
3160 return -1;
3161 }
3162
3163 /**
3164 * igc_add_mac_filter() - Add MAC address filter
3165 * @adapter: Pointer to adapter where the filter should be added
3166 * @type: MAC address filter type (source or destination)
3167 * @addr: MAC address
3168 * @queue: If non-negative, queue assignment feature is enabled and frames
3169 * matching the filter are enqueued onto 'queue'. Otherwise, queue
3170 * assignment is disabled.
3171 *
3172 * Return: 0 in case of success, negative errno code otherwise.
3173 */
igc_add_mac_filter(struct igc_adapter * adapter,enum igc_mac_filter_type type,const u8 * addr,int queue)3174 static int igc_add_mac_filter(struct igc_adapter *adapter,
3175 enum igc_mac_filter_type type, const u8 *addr,
3176 int queue)
3177 {
3178 struct net_device *dev = adapter->netdev;
3179 int index;
3180
3181 index = igc_find_mac_filter(adapter, type, addr);
3182 if (index >= 0)
3183 goto update_filter;
3184
3185 index = igc_get_avail_mac_filter_slot(adapter);
3186 if (index < 0)
3187 return -ENOSPC;
3188
3189 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n",
3190 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
3191 addr, queue);
3192
3193 update_filter:
3194 igc_set_mac_filter_hw(adapter, index, type, addr, queue);
3195 return 0;
3196 }
3197
3198 /**
3199 * igc_del_mac_filter() - Delete MAC address filter
3200 * @adapter: Pointer to adapter where the filter should be deleted from
3201 * @type: MAC address filter type (source or destination)
3202 * @addr: MAC address
3203 */
igc_del_mac_filter(struct igc_adapter * adapter,enum igc_mac_filter_type type,const u8 * addr)3204 static void igc_del_mac_filter(struct igc_adapter *adapter,
3205 enum igc_mac_filter_type type, const u8 *addr)
3206 {
3207 struct net_device *dev = adapter->netdev;
3208 int index;
3209
3210 index = igc_find_mac_filter(adapter, type, addr);
3211 if (index < 0)
3212 return;
3213
3214 if (index == 0) {
3215 /* If this is the default filter, we don't actually delete it.
3216 * We just reset to its default value i.e. disable queue
3217 * assignment.
3218 */
3219 netdev_dbg(dev, "Disable default MAC filter queue assignment");
3220
3221 igc_set_mac_filter_hw(adapter, 0, type, addr, -1);
3222 } else {
3223 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n",
3224 index,
3225 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
3226 addr);
3227
3228 igc_clear_mac_filter_hw(adapter, index);
3229 }
3230 }
3231
3232 /**
3233 * igc_add_vlan_prio_filter() - Add VLAN priority filter
3234 * @adapter: Pointer to adapter where the filter should be added
3235 * @prio: VLAN priority value
3236 * @queue: Queue number which matching frames are assigned to
3237 *
3238 * Return: 0 in case of success, negative errno code otherwise.
3239 */
igc_add_vlan_prio_filter(struct igc_adapter * adapter,int prio,int queue)3240 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,
3241 int queue)
3242 {
3243 struct net_device *dev = adapter->netdev;
3244 struct igc_hw *hw = &adapter->hw;
3245 u32 vlanpqf;
3246
3247 vlanpqf = rd32(IGC_VLANPQF);
3248
3249 if (vlanpqf & IGC_VLANPQF_VALID(prio)) {
3250 netdev_dbg(dev, "VLAN priority filter already in use\n");
3251 return -EEXIST;
3252 }
3253
3254 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);
3255 vlanpqf |= IGC_VLANPQF_VALID(prio);
3256
3257 wr32(IGC_VLANPQF, vlanpqf);
3258
3259 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",
3260 prio, queue);
3261 return 0;
3262 }
3263
3264 /**
3265 * igc_del_vlan_prio_filter() - Delete VLAN priority filter
3266 * @adapter: Pointer to adapter where the filter should be deleted from
3267 * @prio: VLAN priority value
3268 */
igc_del_vlan_prio_filter(struct igc_adapter * adapter,int prio)3269 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)
3270 {
3271 struct igc_hw *hw = &adapter->hw;
3272 u32 vlanpqf;
3273
3274 vlanpqf = rd32(IGC_VLANPQF);
3275
3276 vlanpqf &= ~IGC_VLANPQF_VALID(prio);
3277 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);
3278
3279 wr32(IGC_VLANPQF, vlanpqf);
3280
3281 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",
3282 prio);
3283 }
3284
igc_get_avail_etype_filter_slot(struct igc_adapter * adapter)3285 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)
3286 {
3287 struct igc_hw *hw = &adapter->hw;
3288 int i;
3289
3290 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
3291 u32 etqf = rd32(IGC_ETQF(i));
3292
3293 if (!(etqf & IGC_ETQF_FILTER_ENABLE))
3294 return i;
3295 }
3296
3297 return -1;
3298 }
3299
3300 /**
3301 * igc_add_etype_filter() - Add ethertype filter
3302 * @adapter: Pointer to adapter where the filter should be added
3303 * @etype: Ethertype value
3304 * @queue: If non-negative, queue assignment feature is enabled and frames
3305 * matching the filter are enqueued onto 'queue'. Otherwise, queue
3306 * assignment is disabled.
3307 *
3308 * Return: 0 in case of success, negative errno code otherwise.
3309 */
igc_add_etype_filter(struct igc_adapter * adapter,u16 etype,int queue)3310 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype,
3311 int queue)
3312 {
3313 struct igc_hw *hw = &adapter->hw;
3314 int index;
3315 u32 etqf;
3316
3317 index = igc_get_avail_etype_filter_slot(adapter);
3318 if (index < 0)
3319 return -ENOSPC;
3320
3321 etqf = rd32(IGC_ETQF(index));
3322
3323 etqf &= ~IGC_ETQF_ETYPE_MASK;
3324 etqf |= etype;
3325
3326 if (queue >= 0) {
3327 etqf &= ~IGC_ETQF_QUEUE_MASK;
3328 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);
3329 etqf |= IGC_ETQF_QUEUE_ENABLE;
3330 }
3331
3332 etqf |= IGC_ETQF_FILTER_ENABLE;
3333
3334 wr32(IGC_ETQF(index), etqf);
3335
3336 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",
3337 etype, queue);
3338 return 0;
3339 }
3340
igc_find_etype_filter(struct igc_adapter * adapter,u16 etype)3341 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)
3342 {
3343 struct igc_hw *hw = &adapter->hw;
3344 int i;
3345
3346 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
3347 u32 etqf = rd32(IGC_ETQF(i));
3348
3349 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)
3350 return i;
3351 }
3352
3353 return -1;
3354 }
3355
3356 /**
3357 * igc_del_etype_filter() - Delete ethertype filter
3358 * @adapter: Pointer to adapter where the filter should be deleted from
3359 * @etype: Ethertype value
3360 */
igc_del_etype_filter(struct igc_adapter * adapter,u16 etype)3361 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
3362 {
3363 struct igc_hw *hw = &adapter->hw;
3364 int index;
3365
3366 index = igc_find_etype_filter(adapter, etype);
3367 if (index < 0)
3368 return;
3369
3370 wr32(IGC_ETQF(index), 0);
3371
3372 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",
3373 etype);
3374 }
3375
igc_flex_filter_select(struct igc_adapter * adapter,struct igc_flex_filter * input,u32 * fhft)3376 static int igc_flex_filter_select(struct igc_adapter *adapter,
3377 struct igc_flex_filter *input,
3378 u32 *fhft)
3379 {
3380 struct igc_hw *hw = &adapter->hw;
3381 u8 fhft_index;
3382 u32 fhftsl;
3383
3384 if (input->index >= MAX_FLEX_FILTER) {
3385 dev_err(&adapter->pdev->dev, "Wrong Flex Filter index selected!\n");
3386 return -EINVAL;
3387 }
3388
3389 /* Indirect table select register */
3390 fhftsl = rd32(IGC_FHFTSL);
3391 fhftsl &= ~IGC_FHFTSL_FTSL_MASK;
3392 switch (input->index) {
3393 case 0 ... 7:
3394 fhftsl |= 0x00;
3395 break;
3396 case 8 ... 15:
3397 fhftsl |= 0x01;
3398 break;
3399 case 16 ... 23:
3400 fhftsl |= 0x02;
3401 break;
3402 case 24 ... 31:
3403 fhftsl |= 0x03;
3404 break;
3405 }
3406 wr32(IGC_FHFTSL, fhftsl);
3407
3408 /* Normalize index down to host table register */
3409 fhft_index = input->index % 8;
3410
3411 *fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) :
3412 IGC_FHFT_EXT(fhft_index - 4);
3413
3414 return 0;
3415 }
3416
igc_write_flex_filter_ll(struct igc_adapter * adapter,struct igc_flex_filter * input)3417 static int igc_write_flex_filter_ll(struct igc_adapter *adapter,
3418 struct igc_flex_filter *input)
3419 {
3420 struct device *dev = &adapter->pdev->dev;
3421 struct igc_hw *hw = &adapter->hw;
3422 u8 *data = input->data;
3423 u8 *mask = input->mask;
3424 u32 queuing;
3425 u32 fhft;
3426 u32 wufc;
3427 int ret;
3428 int i;
3429
3430 /* Length has to be aligned to 8. Otherwise the filter will fail. Bail
3431 * out early to avoid surprises later.
3432 */
3433 if (input->length % 8 != 0) {
3434 dev_err(dev, "The length of a flex filter has to be 8 byte aligned!\n");
3435 return -EINVAL;
3436 }
3437
3438 /* Select corresponding flex filter register and get base for host table. */
3439 ret = igc_flex_filter_select(adapter, input, &fhft);
3440 if (ret)
3441 return ret;
3442
3443 /* When adding a filter globally disable flex filter feature. That is
3444 * recommended within the datasheet.
3445 */
3446 wufc = rd32(IGC_WUFC);
3447 wufc &= ~IGC_WUFC_FLEX_HQ;
3448 wr32(IGC_WUFC, wufc);
3449
3450 /* Configure filter */
3451 queuing = input->length & IGC_FHFT_LENGTH_MASK;
3452 queuing |= (input->rx_queue << IGC_FHFT_QUEUE_SHIFT) & IGC_FHFT_QUEUE_MASK;
3453 queuing |= (input->prio << IGC_FHFT_PRIO_SHIFT) & IGC_FHFT_PRIO_MASK;
3454
3455 if (input->immediate_irq)
3456 queuing |= IGC_FHFT_IMM_INT;
3457
3458 if (input->drop)
3459 queuing |= IGC_FHFT_DROP;
3460
3461 wr32(fhft + 0xFC, queuing);
3462
3463 /* Write data (128 byte) and mask (128 bit) */
3464 for (i = 0; i < 16; ++i) {
3465 const size_t data_idx = i * 8;
3466 const size_t row_idx = i * 16;
3467 u32 dw0 =
3468 (data[data_idx + 0] << 0) |
3469 (data[data_idx + 1] << 8) |
3470 (data[data_idx + 2] << 16) |
3471 (data[data_idx + 3] << 24);
3472 u32 dw1 =
3473 (data[data_idx + 4] << 0) |
3474 (data[data_idx + 5] << 8) |
3475 (data[data_idx + 6] << 16) |
3476 (data[data_idx + 7] << 24);
3477 u32 tmp;
3478
3479 /* Write row: dw0, dw1 and mask */
3480 wr32(fhft + row_idx, dw0);
3481 wr32(fhft + row_idx + 4, dw1);
3482
3483 /* mask is only valid for MASK(7, 0) */
3484 tmp = rd32(fhft + row_idx + 8);
3485 tmp &= ~GENMASK(7, 0);
3486 tmp |= mask[i];
3487 wr32(fhft + row_idx + 8, tmp);
3488 }
3489
3490 /* Enable filter. */
3491 wufc |= IGC_WUFC_FLEX_HQ;
3492 if (input->index > 8) {
3493 /* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */
3494 u32 wufc_ext = rd32(IGC_WUFC_EXT);
3495
3496 wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8));
3497
3498 wr32(IGC_WUFC_EXT, wufc_ext);
3499 } else {
3500 wufc |= (IGC_WUFC_FLX0 << input->index);
3501 }
3502 wr32(IGC_WUFC, wufc);
3503
3504 dev_dbg(&adapter->pdev->dev, "Added flex filter %u to HW.\n",
3505 input->index);
3506
3507 return 0;
3508 }
3509
igc_flex_filter_add_field(struct igc_flex_filter * flex,const void * src,unsigned int offset,size_t len,const void * mask)3510 static void igc_flex_filter_add_field(struct igc_flex_filter *flex,
3511 const void *src, unsigned int offset,
3512 size_t len, const void *mask)
3513 {
3514 int i;
3515
3516 /* data */
3517 memcpy(&flex->data[offset], src, len);
3518
3519 /* mask */
3520 for (i = 0; i < len; ++i) {
3521 const unsigned int idx = i + offset;
3522 const u8 *ptr = mask;
3523
3524 if (mask) {
3525 if (ptr[i] & 0xff)
3526 flex->mask[idx / 8] |= BIT(idx % 8);
3527
3528 continue;
3529 }
3530
3531 flex->mask[idx / 8] |= BIT(idx % 8);
3532 }
3533 }
3534
igc_find_avail_flex_filter_slot(struct igc_adapter * adapter)3535 static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter)
3536 {
3537 struct igc_hw *hw = &adapter->hw;
3538 u32 wufc, wufc_ext;
3539 int i;
3540
3541 wufc = rd32(IGC_WUFC);
3542 wufc_ext = rd32(IGC_WUFC_EXT);
3543
3544 for (i = 0; i < MAX_FLEX_FILTER; i++) {
3545 if (i < 8) {
3546 if (!(wufc & (IGC_WUFC_FLX0 << i)))
3547 return i;
3548 } else {
3549 if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8))))
3550 return i;
3551 }
3552 }
3553
3554 return -ENOSPC;
3555 }
3556
igc_flex_filter_in_use(struct igc_adapter * adapter)3557 static bool igc_flex_filter_in_use(struct igc_adapter *adapter)
3558 {
3559 struct igc_hw *hw = &adapter->hw;
3560 u32 wufc, wufc_ext;
3561
3562 wufc = rd32(IGC_WUFC);
3563 wufc_ext = rd32(IGC_WUFC_EXT);
3564
3565 if (wufc & IGC_WUFC_FILTER_MASK)
3566 return true;
3567
3568 if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK)
3569 return true;
3570
3571 return false;
3572 }
3573
igc_add_flex_filter(struct igc_adapter * adapter,struct igc_nfc_rule * rule)3574 static int igc_add_flex_filter(struct igc_adapter *adapter,
3575 struct igc_nfc_rule *rule)
3576 {
3577 struct igc_flex_filter flex = { };
3578 struct igc_nfc_filter *filter = &rule->filter;
3579 unsigned int eth_offset, user_offset;
3580 int ret, index;
3581 bool vlan;
3582
3583 index = igc_find_avail_flex_filter_slot(adapter);
3584 if (index < 0)
3585 return -ENOSPC;
3586
3587 /* Construct the flex filter:
3588 * -> dest_mac [6]
3589 * -> src_mac [6]
3590 * -> tpid [2]
3591 * -> vlan tci [2]
3592 * -> ether type [2]
3593 * -> user data [8]
3594 * -> = 26 bytes => 32 length
3595 */
3596 flex.index = index;
3597 flex.length = 32;
3598 flex.rx_queue = rule->action;
3599
3600 vlan = rule->filter.vlan_tci || rule->filter.vlan_etype;
3601 eth_offset = vlan ? 16 : 12;
3602 user_offset = vlan ? 18 : 14;
3603
3604 /* Add destination MAC */
3605 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
3606 igc_flex_filter_add_field(&flex, &filter->dst_addr, 0,
3607 ETH_ALEN, NULL);
3608
3609 /* Add source MAC */
3610 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
3611 igc_flex_filter_add_field(&flex, &filter->src_addr, 6,
3612 ETH_ALEN, NULL);
3613
3614 /* Add VLAN etype */
3615 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE)
3616 igc_flex_filter_add_field(&flex, &filter->vlan_etype, 12,
3617 sizeof(filter->vlan_etype),
3618 NULL);
3619
3620 /* Add VLAN TCI */
3621 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)
3622 igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14,
3623 sizeof(filter->vlan_tci), NULL);
3624
3625 /* Add Ether type */
3626 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
3627 __be16 etype = cpu_to_be16(filter->etype);
3628
3629 igc_flex_filter_add_field(&flex, &etype, eth_offset,
3630 sizeof(etype), NULL);
3631 }
3632
3633 /* Add user data */
3634 if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA)
3635 igc_flex_filter_add_field(&flex, &filter->user_data,
3636 user_offset,
3637 sizeof(filter->user_data),
3638 filter->user_mask);
3639
3640 /* Add it down to the hardware and enable it. */
3641 ret = igc_write_flex_filter_ll(adapter, &flex);
3642 if (ret)
3643 return ret;
3644
3645 filter->flex_index = index;
3646
3647 return 0;
3648 }
3649
igc_del_flex_filter(struct igc_adapter * adapter,u16 reg_index)3650 static void igc_del_flex_filter(struct igc_adapter *adapter,
3651 u16 reg_index)
3652 {
3653 struct igc_hw *hw = &adapter->hw;
3654 u32 wufc;
3655
3656 /* Just disable the filter. The filter table itself is kept
3657 * intact. Another flex_filter_add() should override the "old" data
3658 * then.
3659 */
3660 if (reg_index > 8) {
3661 u32 wufc_ext = rd32(IGC_WUFC_EXT);
3662
3663 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8));
3664 wr32(IGC_WUFC_EXT, wufc_ext);
3665 } else {
3666 wufc = rd32(IGC_WUFC);
3667
3668 wufc &= ~(IGC_WUFC_FLX0 << reg_index);
3669 wr32(IGC_WUFC, wufc);
3670 }
3671
3672 if (igc_flex_filter_in_use(adapter))
3673 return;
3674
3675 /* No filters are in use, we may disable flex filters */
3676 wufc = rd32(IGC_WUFC);
3677 wufc &= ~IGC_WUFC_FLEX_HQ;
3678 wr32(IGC_WUFC, wufc);
3679 }
3680
igc_enable_nfc_rule(struct igc_adapter * adapter,struct igc_nfc_rule * rule)3681 static int igc_enable_nfc_rule(struct igc_adapter *adapter,
3682 struct igc_nfc_rule *rule)
3683 {
3684 int err;
3685
3686 if (rule->flex) {
3687 return igc_add_flex_filter(adapter, rule);
3688 }
3689
3690 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
3691 err = igc_add_etype_filter(adapter, rule->filter.etype,
3692 rule->action);
3693 if (err)
3694 return err;
3695 }
3696
3697 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) {
3698 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
3699 rule->filter.src_addr, rule->action);
3700 if (err)
3701 return err;
3702 }
3703
3704 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) {
3705 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
3706 rule->filter.dst_addr, rule->action);
3707 if (err)
3708 return err;
3709 }
3710
3711 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
3712 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);
3713
3714 err = igc_add_vlan_prio_filter(adapter, prio, rule->action);
3715 if (err)
3716 return err;
3717 }
3718
3719 return 0;
3720 }
3721
igc_disable_nfc_rule(struct igc_adapter * adapter,const struct igc_nfc_rule * rule)3722 static void igc_disable_nfc_rule(struct igc_adapter *adapter,
3723 const struct igc_nfc_rule *rule)
3724 {
3725 if (rule->flex) {
3726 igc_del_flex_filter(adapter, rule->filter.flex_index);
3727 return;
3728 }
3729
3730 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
3731 igc_del_etype_filter(adapter, rule->filter.etype);
3732
3733 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
3734 int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci);
3735
3736 igc_del_vlan_prio_filter(adapter, prio);
3737 }
3738
3739 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
3740 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
3741 rule->filter.src_addr);
3742
3743 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
3744 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
3745 rule->filter.dst_addr);
3746 }
3747
3748 /**
3749 * igc_get_nfc_rule() - Get NFC rule
3750 * @adapter: Pointer to adapter
3751 * @location: Rule location
3752 *
3753 * Context: Expects adapter->nfc_rule_lock to be held by caller.
3754 *
3755 * Return: Pointer to NFC rule at @location. If not found, NULL.
3756 */
igc_get_nfc_rule(struct igc_adapter * adapter,u32 location)3757 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
3758 u32 location)
3759 {
3760 struct igc_nfc_rule *rule;
3761
3762 list_for_each_entry(rule, &adapter->nfc_rule_list, list) {
3763 if (rule->location == location)
3764 return rule;
3765 if (rule->location > location)
3766 break;
3767 }
3768
3769 return NULL;
3770 }
3771
3772 /**
3773 * igc_del_nfc_rule() - Delete NFC rule
3774 * @adapter: Pointer to adapter
3775 * @rule: Pointer to rule to be deleted
3776 *
3777 * Disable NFC rule in hardware and delete it from adapter.
3778 *
3779 * Context: Expects adapter->nfc_rule_lock to be held by caller.
3780 */
igc_del_nfc_rule(struct igc_adapter * adapter,struct igc_nfc_rule * rule)3781 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
3782 {
3783 igc_disable_nfc_rule(adapter, rule);
3784
3785 list_del(&rule->list);
3786 adapter->nfc_rule_count--;
3787
3788 kfree(rule);
3789 }
3790
igc_flush_nfc_rules(struct igc_adapter * adapter)3791 static void igc_flush_nfc_rules(struct igc_adapter *adapter)
3792 {
3793 struct igc_nfc_rule *rule, *tmp;
3794
3795 mutex_lock(&adapter->nfc_rule_lock);
3796
3797 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list)
3798 igc_del_nfc_rule(adapter, rule);
3799
3800 mutex_unlock(&adapter->nfc_rule_lock);
3801 }
3802
3803 /**
3804 * igc_add_nfc_rule() - Add NFC rule
3805 * @adapter: Pointer to adapter
3806 * @rule: Pointer to rule to be added
3807 *
3808 * Enable NFC rule in hardware and add it to adapter.
3809 *
3810 * Context: Expects adapter->nfc_rule_lock to be held by caller.
3811 *
3812 * Return: 0 on success, negative errno on failure.
3813 */
igc_add_nfc_rule(struct igc_adapter * adapter,struct igc_nfc_rule * rule)3814 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
3815 {
3816 struct igc_nfc_rule *pred, *cur;
3817 int err;
3818
3819 err = igc_enable_nfc_rule(adapter, rule);
3820 if (err)
3821 return err;
3822
3823 pred = NULL;
3824 list_for_each_entry(cur, &adapter->nfc_rule_list, list) {
3825 if (cur->location >= rule->location)
3826 break;
3827 pred = cur;
3828 }
3829
3830 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list);
3831 adapter->nfc_rule_count++;
3832 return 0;
3833 }
3834
igc_restore_nfc_rules(struct igc_adapter * adapter)3835 static void igc_restore_nfc_rules(struct igc_adapter *adapter)
3836 {
3837 struct igc_nfc_rule *rule;
3838
3839 mutex_lock(&adapter->nfc_rule_lock);
3840
3841 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list)
3842 igc_enable_nfc_rule(adapter, rule);
3843
3844 mutex_unlock(&adapter->nfc_rule_lock);
3845 }
3846
igc_uc_sync(struct net_device * netdev,const unsigned char * addr)3847 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)
3848 {
3849 struct igc_adapter *adapter = netdev_priv(netdev);
3850
3851 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1);
3852 }
3853
igc_uc_unsync(struct net_device * netdev,const unsigned char * addr)3854 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr)
3855 {
3856 struct igc_adapter *adapter = netdev_priv(netdev);
3857
3858 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr);
3859 return 0;
3860 }
3861
3862 /**
3863 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3864 * @netdev: network interface device structure
3865 *
3866 * The set_rx_mode entry point is called whenever the unicast or multicast
3867 * address lists or the network interface flags are updated. This routine is
3868 * responsible for configuring the hardware for proper unicast, multicast,
3869 * promiscuous mode, and all-multi behavior.
3870 */
igc_set_rx_mode(struct net_device * netdev)3871 static void igc_set_rx_mode(struct net_device *netdev)
3872 {
3873 struct igc_adapter *adapter = netdev_priv(netdev);
3874 struct igc_hw *hw = &adapter->hw;
3875 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
3876 int count;
3877
3878 /* Check for Promiscuous and All Multicast modes */
3879 if (netdev->flags & IFF_PROMISC) {
3880 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE;
3881 } else {
3882 if (netdev->flags & IFF_ALLMULTI) {
3883 rctl |= IGC_RCTL_MPE;
3884 } else {
3885 /* Write addresses to the MTA, if the attempt fails
3886 * then we should just turn on promiscuous mode so
3887 * that we can at least receive multicast traffic
3888 */
3889 count = igc_write_mc_addr_list(netdev);
3890 if (count < 0)
3891 rctl |= IGC_RCTL_MPE;
3892 }
3893 }
3894
3895 /* Write addresses to available RAR registers, if there is not
3896 * sufficient space to store all the addresses then enable
3897 * unicast promiscuous mode
3898 */
3899 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync))
3900 rctl |= IGC_RCTL_UPE;
3901
3902 /* update state of unicast and multicast */
3903 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
3904 wr32(IGC_RCTL, rctl);
3905
3906 #if (PAGE_SIZE < 8192)
3907 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB)
3908 rlpml = IGC_MAX_FRAME_BUILD_SKB;
3909 #endif
3910 wr32(IGC_RLPML, rlpml);
3911 }
3912
3913 /**
3914 * igc_configure - configure the hardware for RX and TX
3915 * @adapter: private board structure
3916 */
igc_configure(struct igc_adapter * adapter)3917 static void igc_configure(struct igc_adapter *adapter)
3918 {
3919 struct net_device *netdev = adapter->netdev;
3920 int i = 0;
3921
3922 igc_get_hw_control(adapter);
3923 igc_set_rx_mode(netdev);
3924
3925 igc_restore_vlan(adapter);
3926
3927 igc_setup_tctl(adapter);
3928 igc_setup_mrqc(adapter);
3929 igc_setup_rctl(adapter);
3930
3931 igc_set_default_mac_filter(adapter);
3932 igc_restore_nfc_rules(adapter);
3933
3934 igc_configure_tx(adapter);
3935 igc_configure_rx(adapter);
3936
3937 igc_rx_fifo_flush_base(&adapter->hw);
3938
3939 /* call igc_desc_unused which always leaves
3940 * at least 1 descriptor unused to make sure
3941 * next_to_use != next_to_clean
3942 */
3943 for (i = 0; i < adapter->num_rx_queues; i++) {
3944 struct igc_ring *ring = adapter->rx_ring[i];
3945
3946 if (ring->xsk_pool)
3947 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));
3948 else
3949 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
3950 }
3951 }
3952
3953 /**
3954 * igc_write_ivar - configure ivar for given MSI-X vector
3955 * @hw: pointer to the HW structure
3956 * @msix_vector: vector number we are allocating to a given ring
3957 * @index: row index of IVAR register to write within IVAR table
3958 * @offset: column offset of in IVAR, should be multiple of 8
3959 *
3960 * The IVAR table consists of 2 columns,
3961 * each containing an cause allocation for an Rx and Tx ring, and a
3962 * variable number of rows depending on the number of queues supported.
3963 */
igc_write_ivar(struct igc_hw * hw,int msix_vector,int index,int offset)3964 static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
3965 int index, int offset)
3966 {
3967 u32 ivar = array_rd32(IGC_IVAR0, index);
3968
3969 /* clear any bits that are currently set */
3970 ivar &= ~((u32)0xFF << offset);
3971
3972 /* write vector and valid bit */
3973 ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
3974
3975 array_wr32(IGC_IVAR0, index, ivar);
3976 }
3977
igc_assign_vector(struct igc_q_vector * q_vector,int msix_vector)3978 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
3979 {
3980 struct igc_adapter *adapter = q_vector->adapter;
3981 struct igc_hw *hw = &adapter->hw;
3982 int rx_queue = IGC_N0_QUEUE;
3983 int tx_queue = IGC_N0_QUEUE;
3984
3985 if (q_vector->rx.ring)
3986 rx_queue = q_vector->rx.ring->reg_idx;
3987 if (q_vector->tx.ring)
3988 tx_queue = q_vector->tx.ring->reg_idx;
3989
3990 switch (hw->mac.type) {
3991 case igc_i225:
3992 if (rx_queue > IGC_N0_QUEUE)
3993 igc_write_ivar(hw, msix_vector,
3994 rx_queue >> 1,
3995 (rx_queue & 0x1) << 4);
3996 if (tx_queue > IGC_N0_QUEUE)
3997 igc_write_ivar(hw, msix_vector,
3998 tx_queue >> 1,
3999 ((tx_queue & 0x1) << 4) + 8);
4000 q_vector->eims_value = BIT(msix_vector);
4001 break;
4002 default:
4003 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
4004 break;
4005 }
4006
4007 /* add q_vector eims value to global eims_enable_mask */
4008 adapter->eims_enable_mask |= q_vector->eims_value;
4009
4010 /* configure q_vector to set itr on first interrupt */
4011 q_vector->set_itr = 1;
4012 }
4013
4014 /**
4015 * igc_configure_msix - Configure MSI-X hardware
4016 * @adapter: Pointer to adapter structure
4017 *
4018 * igc_configure_msix sets up the hardware to properly
4019 * generate MSI-X interrupts.
4020 */
igc_configure_msix(struct igc_adapter * adapter)4021 static void igc_configure_msix(struct igc_adapter *adapter)
4022 {
4023 struct igc_hw *hw = &adapter->hw;
4024 int i, vector = 0;
4025 u32 tmp;
4026
4027 adapter->eims_enable_mask = 0;
4028
4029 /* set vector for other causes, i.e. link changes */
4030 switch (hw->mac.type) {
4031 case igc_i225:
4032 /* Turn on MSI-X capability first, or our settings
4033 * won't stick. And it will take days to debug.
4034 */
4035 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |
4036 IGC_GPIE_PBA | IGC_GPIE_EIAME |
4037 IGC_GPIE_NSICR);
4038
4039 /* enable msix_other interrupt */
4040 adapter->eims_other = BIT(vector);
4041 tmp = (vector++ | IGC_IVAR_VALID) << 8;
4042
4043 wr32(IGC_IVAR_MISC, tmp);
4044 break;
4045 default:
4046 /* do nothing, since nothing else supports MSI-X */
4047 break;
4048 } /* switch (hw->mac.type) */
4049
4050 adapter->eims_enable_mask |= adapter->eims_other;
4051
4052 for (i = 0; i < adapter->num_q_vectors; i++)
4053 igc_assign_vector(adapter->q_vector[i], vector++);
4054
4055 wrfl();
4056 }
4057
4058 /**
4059 * igc_irq_enable - Enable default interrupt generation settings
4060 * @adapter: board private structure
4061 */
igc_irq_enable(struct igc_adapter * adapter)4062 static void igc_irq_enable(struct igc_adapter *adapter)
4063 {
4064 struct igc_hw *hw = &adapter->hw;
4065
4066 if (adapter->msix_entries) {
4067 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;
4068 u32 regval = rd32(IGC_EIAC);
4069
4070 wr32(IGC_EIAC, regval | adapter->eims_enable_mask);
4071 regval = rd32(IGC_EIAM);
4072 wr32(IGC_EIAM, regval | adapter->eims_enable_mask);
4073 wr32(IGC_EIMS, adapter->eims_enable_mask);
4074 wr32(IGC_IMS, ims);
4075 } else {
4076 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
4077 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
4078 }
4079 }
4080
4081 /**
4082 * igc_irq_disable - Mask off interrupt generation on the NIC
4083 * @adapter: board private structure
4084 */
igc_irq_disable(struct igc_adapter * adapter)4085 static void igc_irq_disable(struct igc_adapter *adapter)
4086 {
4087 struct igc_hw *hw = &adapter->hw;
4088
4089 if (adapter->msix_entries) {
4090 u32 regval = rd32(IGC_EIAM);
4091
4092 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);
4093 wr32(IGC_EIMC, adapter->eims_enable_mask);
4094 regval = rd32(IGC_EIAC);
4095 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);
4096 }
4097
4098 wr32(IGC_IAM, 0);
4099 wr32(IGC_IMC, ~0);
4100 wrfl();
4101
4102 if (adapter->msix_entries) {
4103 int vector = 0, i;
4104
4105 synchronize_irq(adapter->msix_entries[vector++].vector);
4106
4107 for (i = 0; i < adapter->num_q_vectors; i++)
4108 synchronize_irq(adapter->msix_entries[vector++].vector);
4109 } else {
4110 synchronize_irq(adapter->pdev->irq);
4111 }
4112 }
4113
igc_set_flag_queue_pairs(struct igc_adapter * adapter,const u32 max_rss_queues)4114 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
4115 const u32 max_rss_queues)
4116 {
4117 /* Determine if we need to pair queues. */
4118 /* If rss_queues > half of max_rss_queues, pair the queues in
4119 * order to conserve interrupts due to limited supply.
4120 */
4121 if (adapter->rss_queues > (max_rss_queues / 2))
4122 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
4123 else
4124 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;
4125 }
4126
igc_get_max_rss_queues(struct igc_adapter * adapter)4127 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)
4128 {
4129 return IGC_MAX_RX_QUEUES;
4130 }
4131
igc_init_queue_configuration(struct igc_adapter * adapter)4132 static void igc_init_queue_configuration(struct igc_adapter *adapter)
4133 {
4134 u32 max_rss_queues;
4135
4136 max_rss_queues = igc_get_max_rss_queues(adapter);
4137 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
4138
4139 igc_set_flag_queue_pairs(adapter, max_rss_queues);
4140 }
4141
4142 /**
4143 * igc_reset_q_vector - Reset config for interrupt vector
4144 * @adapter: board private structure to initialize
4145 * @v_idx: Index of vector to be reset
4146 *
4147 * If NAPI is enabled it will delete any references to the
4148 * NAPI struct. This is preparation for igc_free_q_vector.
4149 */
igc_reset_q_vector(struct igc_adapter * adapter,int v_idx)4150 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)
4151 {
4152 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
4153
4154 /* if we're coming from igc_set_interrupt_capability, the vectors are
4155 * not yet allocated
4156 */
4157 if (!q_vector)
4158 return;
4159
4160 if (q_vector->tx.ring)
4161 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
4162
4163 if (q_vector->rx.ring)
4164 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
4165
4166 netif_napi_del(&q_vector->napi);
4167 }
4168
4169 /**
4170 * igc_free_q_vector - Free memory allocated for specific interrupt vector
4171 * @adapter: board private structure to initialize
4172 * @v_idx: Index of vector to be freed
4173 *
4174 * This function frees the memory allocated to the q_vector.
4175 */
igc_free_q_vector(struct igc_adapter * adapter,int v_idx)4176 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)
4177 {
4178 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
4179
4180 adapter->q_vector[v_idx] = NULL;
4181
4182 /* igc_get_stats64() might access the rings on this vector,
4183 * we must wait a grace period before freeing it.
4184 */
4185 if (q_vector)
4186 kfree_rcu(q_vector, rcu);
4187 }
4188
4189 /**
4190 * igc_free_q_vectors - Free memory allocated for interrupt vectors
4191 * @adapter: board private structure to initialize
4192 *
4193 * This function frees the memory allocated to the q_vectors. In addition if
4194 * NAPI is enabled it will delete any references to the NAPI struct prior
4195 * to freeing the q_vector.
4196 */
igc_free_q_vectors(struct igc_adapter * adapter)4197 static void igc_free_q_vectors(struct igc_adapter *adapter)
4198 {
4199 int v_idx = adapter->num_q_vectors;
4200
4201 adapter->num_tx_queues = 0;
4202 adapter->num_rx_queues = 0;
4203 adapter->num_q_vectors = 0;
4204
4205 while (v_idx--) {
4206 igc_reset_q_vector(adapter, v_idx);
4207 igc_free_q_vector(adapter, v_idx);
4208 }
4209 }
4210
4211 /**
4212 * igc_update_itr - update the dynamic ITR value based on statistics
4213 * @q_vector: pointer to q_vector
4214 * @ring_container: ring info to update the itr for
4215 *
4216 * Stores a new ITR value based on packets and byte
4217 * counts during the last interrupt. The advantage of per interrupt
4218 * computation is faster updates and more accurate ITR for the current
4219 * traffic pattern. Constants in this function were computed
4220 * based on theoretical maximum wire speed and thresholds were set based
4221 * on testing data as well as attempting to minimize response time
4222 * while increasing bulk throughput.
4223 * NOTE: These calculations are only valid when operating in a single-
4224 * queue environment.
4225 */
igc_update_itr(struct igc_q_vector * q_vector,struct igc_ring_container * ring_container)4226 static void igc_update_itr(struct igc_q_vector *q_vector,
4227 struct igc_ring_container *ring_container)
4228 {
4229 unsigned int packets = ring_container->total_packets;
4230 unsigned int bytes = ring_container->total_bytes;
4231 u8 itrval = ring_container->itr;
4232
4233 /* no packets, exit with status unchanged */
4234 if (packets == 0)
4235 return;
4236
4237 switch (itrval) {
4238 case lowest_latency:
4239 /* handle TSO and jumbo frames */
4240 if (bytes / packets > 8000)
4241 itrval = bulk_latency;
4242 else if ((packets < 5) && (bytes > 512))
4243 itrval = low_latency;
4244 break;
4245 case low_latency: /* 50 usec aka 20000 ints/s */
4246 if (bytes > 10000) {
4247 /* this if handles the TSO accounting */
4248 if (bytes / packets > 8000)
4249 itrval = bulk_latency;
4250 else if ((packets < 10) || ((bytes / packets) > 1200))
4251 itrval = bulk_latency;
4252 else if ((packets > 35))
4253 itrval = lowest_latency;
4254 } else if (bytes / packets > 2000) {
4255 itrval = bulk_latency;
4256 } else if (packets <= 2 && bytes < 512) {
4257 itrval = lowest_latency;
4258 }
4259 break;
4260 case bulk_latency: /* 250 usec aka 4000 ints/s */
4261 if (bytes > 25000) {
4262 if (packets > 35)
4263 itrval = low_latency;
4264 } else if (bytes < 1500) {
4265 itrval = low_latency;
4266 }
4267 break;
4268 }
4269
4270 /* clear work counters since we have the values we need */
4271 ring_container->total_bytes = 0;
4272 ring_container->total_packets = 0;
4273
4274 /* write updated itr to ring container */
4275 ring_container->itr = itrval;
4276 }
4277
igc_set_itr(struct igc_q_vector * q_vector)4278 static void igc_set_itr(struct igc_q_vector *q_vector)
4279 {
4280 struct igc_adapter *adapter = q_vector->adapter;
4281 u32 new_itr = q_vector->itr_val;
4282 u8 current_itr = 0;
4283
4284 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4285 switch (adapter->link_speed) {
4286 case SPEED_10:
4287 case SPEED_100:
4288 current_itr = 0;
4289 new_itr = IGC_4K_ITR;
4290 goto set_itr_now;
4291 default:
4292 break;
4293 }
4294
4295 igc_update_itr(q_vector, &q_vector->tx);
4296 igc_update_itr(q_vector, &q_vector->rx);
4297
4298 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4299
4300 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4301 if (current_itr == lowest_latency &&
4302 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4303 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4304 current_itr = low_latency;
4305
4306 switch (current_itr) {
4307 /* counts and packets in update_itr are dependent on these numbers */
4308 case lowest_latency:
4309 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */
4310 break;
4311 case low_latency:
4312 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */
4313 break;
4314 case bulk_latency:
4315 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */
4316 break;
4317 default:
4318 break;
4319 }
4320
4321 set_itr_now:
4322 if (new_itr != q_vector->itr_val) {
4323 /* this attempts to bias the interrupt rate towards Bulk
4324 * by adding intermediate steps when interrupt rate is
4325 * increasing
4326 */
4327 new_itr = new_itr > q_vector->itr_val ?
4328 max((new_itr * q_vector->itr_val) /
4329 (new_itr + (q_vector->itr_val >> 2)),
4330 new_itr) : new_itr;
4331 /* Don't write the value here; it resets the adapter's
4332 * internal timer, and causes us to delay far longer than
4333 * we should between interrupts. Instead, we write the ITR
4334 * value at the beginning of the next interrupt so the timing
4335 * ends up being correct.
4336 */
4337 q_vector->itr_val = new_itr;
4338 q_vector->set_itr = 1;
4339 }
4340 }
4341
igc_reset_interrupt_capability(struct igc_adapter * adapter)4342 static void igc_reset_interrupt_capability(struct igc_adapter *adapter)
4343 {
4344 int v_idx = adapter->num_q_vectors;
4345
4346 if (adapter->msix_entries) {
4347 pci_disable_msix(adapter->pdev);
4348 kfree(adapter->msix_entries);
4349 adapter->msix_entries = NULL;
4350 } else if (adapter->flags & IGC_FLAG_HAS_MSI) {
4351 pci_disable_msi(adapter->pdev);
4352 }
4353
4354 while (v_idx--)
4355 igc_reset_q_vector(adapter, v_idx);
4356 }
4357
4358 /**
4359 * igc_set_interrupt_capability - set MSI or MSI-X if supported
4360 * @adapter: Pointer to adapter structure
4361 * @msix: boolean value for MSI-X capability
4362 *
4363 * Attempt to configure interrupts using the best available
4364 * capabilities of the hardware and kernel.
4365 */
igc_set_interrupt_capability(struct igc_adapter * adapter,bool msix)4366 static void igc_set_interrupt_capability(struct igc_adapter *adapter,
4367 bool msix)
4368 {
4369 int numvecs, i;
4370 int err;
4371
4372 if (!msix)
4373 goto msi_only;
4374 adapter->flags |= IGC_FLAG_HAS_MSIX;
4375
4376 /* Number of supported queues. */
4377 adapter->num_rx_queues = adapter->rss_queues;
4378
4379 adapter->num_tx_queues = adapter->rss_queues;
4380
4381 /* start with one vector for every Rx queue */
4382 numvecs = adapter->num_rx_queues;
4383
4384 /* if Tx handler is separate add 1 for every Tx queue */
4385 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))
4386 numvecs += adapter->num_tx_queues;
4387
4388 /* store the number of vectors reserved for queues */
4389 adapter->num_q_vectors = numvecs;
4390
4391 /* add 1 vector for link status interrupts */
4392 numvecs++;
4393
4394 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
4395 GFP_KERNEL);
4396
4397 if (!adapter->msix_entries)
4398 return;
4399
4400 /* populate entry values */
4401 for (i = 0; i < numvecs; i++)
4402 adapter->msix_entries[i].entry = i;
4403
4404 err = pci_enable_msix_range(adapter->pdev,
4405 adapter->msix_entries,
4406 numvecs,
4407 numvecs);
4408 if (err > 0)
4409 return;
4410
4411 kfree(adapter->msix_entries);
4412 adapter->msix_entries = NULL;
4413
4414 igc_reset_interrupt_capability(adapter);
4415
4416 msi_only:
4417 adapter->flags &= ~IGC_FLAG_HAS_MSIX;
4418
4419 adapter->rss_queues = 1;
4420 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
4421 adapter->num_rx_queues = 1;
4422 adapter->num_tx_queues = 1;
4423 adapter->num_q_vectors = 1;
4424 if (!pci_enable_msi(adapter->pdev))
4425 adapter->flags |= IGC_FLAG_HAS_MSI;
4426 }
4427
4428 /**
4429 * igc_update_ring_itr - update the dynamic ITR value based on packet size
4430 * @q_vector: pointer to q_vector
4431 *
4432 * Stores a new ITR value based on strictly on packet size. This
4433 * algorithm is less sophisticated than that used in igc_update_itr,
4434 * due to the difficulty of synchronizing statistics across multiple
4435 * receive rings. The divisors and thresholds used by this function
4436 * were determined based on theoretical maximum wire speed and testing
4437 * data, in order to minimize response time while increasing bulk
4438 * throughput.
4439 * NOTE: This function is called only when operating in a multiqueue
4440 * receive environment.
4441 */
igc_update_ring_itr(struct igc_q_vector * q_vector)4442 static void igc_update_ring_itr(struct igc_q_vector *q_vector)
4443 {
4444 struct igc_adapter *adapter = q_vector->adapter;
4445 int new_val = q_vector->itr_val;
4446 int avg_wire_size = 0;
4447 unsigned int packets;
4448
4449 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4450 * ints/sec - ITR timer value of 120 ticks.
4451 */
4452 switch (adapter->link_speed) {
4453 case SPEED_10:
4454 case SPEED_100:
4455 new_val = IGC_4K_ITR;
4456 goto set_itr_val;
4457 default:
4458 break;
4459 }
4460
4461 packets = q_vector->rx.total_packets;
4462 if (packets)
4463 avg_wire_size = q_vector->rx.total_bytes / packets;
4464
4465 packets = q_vector->tx.total_packets;
4466 if (packets)
4467 avg_wire_size = max_t(u32, avg_wire_size,
4468 q_vector->tx.total_bytes / packets);
4469
4470 /* if avg_wire_size isn't set no work was done */
4471 if (!avg_wire_size)
4472 goto clear_counts;
4473
4474 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4475 avg_wire_size += 24;
4476
4477 /* Don't starve jumbo frames */
4478 avg_wire_size = min(avg_wire_size, 3000);
4479
4480 /* Give a little boost to mid-size frames */
4481 if (avg_wire_size > 300 && avg_wire_size < 1200)
4482 new_val = avg_wire_size / 3;
4483 else
4484 new_val = avg_wire_size / 2;
4485
4486 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4487 if (new_val < IGC_20K_ITR &&
4488 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4489 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4490 new_val = IGC_20K_ITR;
4491
4492 set_itr_val:
4493 if (new_val != q_vector->itr_val) {
4494 q_vector->itr_val = new_val;
4495 q_vector->set_itr = 1;
4496 }
4497 clear_counts:
4498 q_vector->rx.total_bytes = 0;
4499 q_vector->rx.total_packets = 0;
4500 q_vector->tx.total_bytes = 0;
4501 q_vector->tx.total_packets = 0;
4502 }
4503
igc_ring_irq_enable(struct igc_q_vector * q_vector)4504 static void igc_ring_irq_enable(struct igc_q_vector *q_vector)
4505 {
4506 struct igc_adapter *adapter = q_vector->adapter;
4507 struct igc_hw *hw = &adapter->hw;
4508
4509 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
4510 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
4511 if (adapter->num_q_vectors == 1)
4512 igc_set_itr(q_vector);
4513 else
4514 igc_update_ring_itr(q_vector);
4515 }
4516
4517 if (!test_bit(__IGC_DOWN, &adapter->state)) {
4518 if (adapter->msix_entries)
4519 wr32(IGC_EIMS, q_vector->eims_value);
4520 else
4521 igc_irq_enable(adapter);
4522 }
4523 }
4524
igc_add_ring(struct igc_ring * ring,struct igc_ring_container * head)4525 static void igc_add_ring(struct igc_ring *ring,
4526 struct igc_ring_container *head)
4527 {
4528 head->ring = ring;
4529 head->count++;
4530 }
4531
4532 /**
4533 * igc_cache_ring_register - Descriptor ring to register mapping
4534 * @adapter: board private structure to initialize
4535 *
4536 * Once we know the feature-set enabled for the device, we'll cache
4537 * the register offset the descriptor ring is assigned to.
4538 */
igc_cache_ring_register(struct igc_adapter * adapter)4539 static void igc_cache_ring_register(struct igc_adapter *adapter)
4540 {
4541 int i = 0, j = 0;
4542
4543 switch (adapter->hw.mac.type) {
4544 case igc_i225:
4545 default:
4546 for (; i < adapter->num_rx_queues; i++)
4547 adapter->rx_ring[i]->reg_idx = i;
4548 for (; j < adapter->num_tx_queues; j++)
4549 adapter->tx_ring[j]->reg_idx = j;
4550 break;
4551 }
4552 }
4553
4554 /**
4555 * igc_poll - NAPI Rx polling callback
4556 * @napi: napi polling structure
4557 * @budget: count of how many packets we should handle
4558 */
igc_poll(struct napi_struct * napi,int budget)4559 static int igc_poll(struct napi_struct *napi, int budget)
4560 {
4561 struct igc_q_vector *q_vector = container_of(napi,
4562 struct igc_q_vector,
4563 napi);
4564 struct igc_ring *rx_ring = q_vector->rx.ring;
4565 bool clean_complete = true;
4566 int work_done = 0;
4567
4568 if (q_vector->tx.ring)
4569 clean_complete = igc_clean_tx_irq(q_vector, budget);
4570
4571 if (rx_ring) {
4572 int cleaned = rx_ring->xsk_pool ?
4573 igc_clean_rx_irq_zc(q_vector, budget) :
4574 igc_clean_rx_irq(q_vector, budget);
4575
4576 work_done += cleaned;
4577 if (cleaned >= budget)
4578 clean_complete = false;
4579 }
4580
4581 /* If all work not completed, return budget and keep polling */
4582 if (!clean_complete)
4583 return budget;
4584
4585 /* Exit the polling mode, but don't re-enable interrupts if stack might
4586 * poll us due to busy-polling
4587 */
4588 if (likely(napi_complete_done(napi, work_done)))
4589 igc_ring_irq_enable(q_vector);
4590
4591 return min(work_done, budget - 1);
4592 }
4593
4594 /**
4595 * igc_alloc_q_vector - Allocate memory for a single interrupt vector
4596 * @adapter: board private structure to initialize
4597 * @v_count: q_vectors allocated on adapter, used for ring interleaving
4598 * @v_idx: index of vector in adapter struct
4599 * @txr_count: total number of Tx rings to allocate
4600 * @txr_idx: index of first Tx ring to allocate
4601 * @rxr_count: total number of Rx rings to allocate
4602 * @rxr_idx: index of first Rx ring to allocate
4603 *
4604 * We allocate one q_vector. If allocation fails we return -ENOMEM.
4605 */
igc_alloc_q_vector(struct igc_adapter * adapter,unsigned int v_count,unsigned int v_idx,unsigned int txr_count,unsigned int txr_idx,unsigned int rxr_count,unsigned int rxr_idx)4606 static int igc_alloc_q_vector(struct igc_adapter *adapter,
4607 unsigned int v_count, unsigned int v_idx,
4608 unsigned int txr_count, unsigned int txr_idx,
4609 unsigned int rxr_count, unsigned int rxr_idx)
4610 {
4611 struct igc_q_vector *q_vector;
4612 struct igc_ring *ring;
4613 int ring_count;
4614
4615 /* igc only supports 1 Tx and/or 1 Rx queue per vector */
4616 if (txr_count > 1 || rxr_count > 1)
4617 return -ENOMEM;
4618
4619 ring_count = txr_count + rxr_count;
4620
4621 /* allocate q_vector and rings */
4622 q_vector = adapter->q_vector[v_idx];
4623 if (!q_vector)
4624 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
4625 GFP_KERNEL);
4626 else
4627 memset(q_vector, 0, struct_size(q_vector, ring, ring_count));
4628 if (!q_vector)
4629 return -ENOMEM;
4630
4631 /* initialize NAPI */
4632 netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll);
4633
4634 /* tie q_vector and adapter together */
4635 adapter->q_vector[v_idx] = q_vector;
4636 q_vector->adapter = adapter;
4637
4638 /* initialize work limits */
4639 q_vector->tx.work_limit = adapter->tx_work_limit;
4640
4641 /* initialize ITR configuration */
4642 q_vector->itr_register = adapter->io_addr + IGC_EITR(0);
4643 q_vector->itr_val = IGC_START_ITR;
4644
4645 /* initialize pointer to rings */
4646 ring = q_vector->ring;
4647
4648 /* initialize ITR */
4649 if (rxr_count) {
4650 /* rx or rx/tx vector */
4651 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
4652 q_vector->itr_val = adapter->rx_itr_setting;
4653 } else {
4654 /* tx only vector */
4655 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
4656 q_vector->itr_val = adapter->tx_itr_setting;
4657 }
4658
4659 if (txr_count) {
4660 /* assign generic ring traits */
4661 ring->dev = &adapter->pdev->dev;
4662 ring->netdev = adapter->netdev;
4663
4664 /* configure backlink on ring */
4665 ring->q_vector = q_vector;
4666
4667 /* update q_vector Tx values */
4668 igc_add_ring(ring, &q_vector->tx);
4669
4670 /* apply Tx specific ring traits */
4671 ring->count = adapter->tx_ring_count;
4672 ring->queue_index = txr_idx;
4673
4674 /* assign ring to adapter */
4675 adapter->tx_ring[txr_idx] = ring;
4676
4677 /* push pointer to next ring */
4678 ring++;
4679 }
4680
4681 if (rxr_count) {
4682 /* assign generic ring traits */
4683 ring->dev = &adapter->pdev->dev;
4684 ring->netdev = adapter->netdev;
4685
4686 /* configure backlink on ring */
4687 ring->q_vector = q_vector;
4688
4689 /* update q_vector Rx values */
4690 igc_add_ring(ring, &q_vector->rx);
4691
4692 /* apply Rx specific ring traits */
4693 ring->count = adapter->rx_ring_count;
4694 ring->queue_index = rxr_idx;
4695
4696 /* assign ring to adapter */
4697 adapter->rx_ring[rxr_idx] = ring;
4698 }
4699
4700 return 0;
4701 }
4702
4703 /**
4704 * igc_alloc_q_vectors - Allocate memory for interrupt vectors
4705 * @adapter: board private structure to initialize
4706 *
4707 * We allocate one q_vector per queue interrupt. If allocation fails we
4708 * return -ENOMEM.
4709 */
igc_alloc_q_vectors(struct igc_adapter * adapter)4710 static int igc_alloc_q_vectors(struct igc_adapter *adapter)
4711 {
4712 int rxr_remaining = adapter->num_rx_queues;
4713 int txr_remaining = adapter->num_tx_queues;
4714 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
4715 int q_vectors = adapter->num_q_vectors;
4716 int err;
4717
4718 if (q_vectors >= (rxr_remaining + txr_remaining)) {
4719 for (; rxr_remaining; v_idx++) {
4720 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
4721 0, 0, 1, rxr_idx);
4722
4723 if (err)
4724 goto err_out;
4725
4726 /* update counts and index */
4727 rxr_remaining--;
4728 rxr_idx++;
4729 }
4730 }
4731
4732 for (; v_idx < q_vectors; v_idx++) {
4733 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
4734 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
4735
4736 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
4737 tqpv, txr_idx, rqpv, rxr_idx);
4738
4739 if (err)
4740 goto err_out;
4741
4742 /* update counts and index */
4743 rxr_remaining -= rqpv;
4744 txr_remaining -= tqpv;
4745 rxr_idx++;
4746 txr_idx++;
4747 }
4748
4749 return 0;
4750
4751 err_out:
4752 adapter->num_tx_queues = 0;
4753 adapter->num_rx_queues = 0;
4754 adapter->num_q_vectors = 0;
4755
4756 while (v_idx--)
4757 igc_free_q_vector(adapter, v_idx);
4758
4759 return -ENOMEM;
4760 }
4761
4762 /**
4763 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
4764 * @adapter: Pointer to adapter structure
4765 * @msix: boolean for MSI-X capability
4766 *
4767 * This function initializes the interrupts and allocates all of the queues.
4768 */
igc_init_interrupt_scheme(struct igc_adapter * adapter,bool msix)4769 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)
4770 {
4771 struct net_device *dev = adapter->netdev;
4772 int err = 0;
4773
4774 igc_set_interrupt_capability(adapter, msix);
4775
4776 err = igc_alloc_q_vectors(adapter);
4777 if (err) {
4778 netdev_err(dev, "Unable to allocate memory for vectors\n");
4779 goto err_alloc_q_vectors;
4780 }
4781
4782 igc_cache_ring_register(adapter);
4783
4784 return 0;
4785
4786 err_alloc_q_vectors:
4787 igc_reset_interrupt_capability(adapter);
4788 return err;
4789 }
4790
4791 /**
4792 * igc_sw_init - Initialize general software structures (struct igc_adapter)
4793 * @adapter: board private structure to initialize
4794 *
4795 * igc_sw_init initializes the Adapter private data structure.
4796 * Fields are initialized based on PCI device information and
4797 * OS network device settings (MTU size).
4798 */
igc_sw_init(struct igc_adapter * adapter)4799 static int igc_sw_init(struct igc_adapter *adapter)
4800 {
4801 struct net_device *netdev = adapter->netdev;
4802 struct pci_dev *pdev = adapter->pdev;
4803 struct igc_hw *hw = &adapter->hw;
4804
4805 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
4806
4807 /* set default ring sizes */
4808 adapter->tx_ring_count = IGC_DEFAULT_TXD;
4809 adapter->rx_ring_count = IGC_DEFAULT_RXD;
4810
4811 /* set default ITR values */
4812 adapter->rx_itr_setting = IGC_DEFAULT_ITR;
4813 adapter->tx_itr_setting = IGC_DEFAULT_ITR;
4814
4815 /* set default work limits */
4816 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;
4817
4818 /* adjust max frame to be at least the size of a standard frame */
4819 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
4820 VLAN_HLEN;
4821 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4822
4823 mutex_init(&adapter->nfc_rule_lock);
4824 INIT_LIST_HEAD(&adapter->nfc_rule_list);
4825 adapter->nfc_rule_count = 0;
4826
4827 spin_lock_init(&adapter->stats64_lock);
4828 spin_lock_init(&adapter->qbv_tx_lock);
4829 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
4830 adapter->flags |= IGC_FLAG_HAS_MSIX;
4831
4832 igc_init_queue_configuration(adapter);
4833
4834 /* This call may decrease the number of queues */
4835 if (igc_init_interrupt_scheme(adapter, true)) {
4836 netdev_err(netdev, "Unable to allocate memory for queues\n");
4837 return -ENOMEM;
4838 }
4839
4840 /* Explicitly disable IRQ since the NIC can be in any state. */
4841 igc_irq_disable(adapter);
4842
4843 set_bit(__IGC_DOWN, &adapter->state);
4844
4845 return 0;
4846 }
4847
4848 /**
4849 * igc_up - Open the interface and prepare it to handle traffic
4850 * @adapter: board private structure
4851 */
igc_up(struct igc_adapter * adapter)4852 void igc_up(struct igc_adapter *adapter)
4853 {
4854 struct igc_hw *hw = &adapter->hw;
4855 int i = 0;
4856
4857 /* hardware has been reset, we need to reload some things */
4858 igc_configure(adapter);
4859
4860 clear_bit(__IGC_DOWN, &adapter->state);
4861
4862 for (i = 0; i < adapter->num_q_vectors; i++)
4863 napi_enable(&adapter->q_vector[i]->napi);
4864
4865 if (adapter->msix_entries)
4866 igc_configure_msix(adapter);
4867 else
4868 igc_assign_vector(adapter->q_vector[0], 0);
4869
4870 /* Clear any pending interrupts. */
4871 rd32(IGC_ICR);
4872 igc_irq_enable(adapter);
4873
4874 netif_tx_start_all_queues(adapter->netdev);
4875
4876 /* start the watchdog. */
4877 hw->mac.get_link_status = true;
4878 schedule_work(&adapter->watchdog_task);
4879 }
4880
4881 /**
4882 * igc_update_stats - Update the board statistics counters
4883 * @adapter: board private structure
4884 */
igc_update_stats(struct igc_adapter * adapter)4885 void igc_update_stats(struct igc_adapter *adapter)
4886 {
4887 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
4888 struct pci_dev *pdev = adapter->pdev;
4889 struct igc_hw *hw = &adapter->hw;
4890 u64 _bytes, _packets;
4891 u64 bytes, packets;
4892 unsigned int start;
4893 u32 mpc;
4894 int i;
4895
4896 /* Prevent stats update while adapter is being reset, or if the pci
4897 * connection is down.
4898 */
4899 if (adapter->link_speed == 0)
4900 return;
4901 if (pci_channel_offline(pdev))
4902 return;
4903
4904 packets = 0;
4905 bytes = 0;
4906
4907 rcu_read_lock();
4908 for (i = 0; i < adapter->num_rx_queues; i++) {
4909 struct igc_ring *ring = adapter->rx_ring[i];
4910 u32 rqdpc = rd32(IGC_RQDPC(i));
4911
4912 if (hw->mac.type >= igc_i225)
4913 wr32(IGC_RQDPC(i), 0);
4914
4915 if (rqdpc) {
4916 ring->rx_stats.drops += rqdpc;
4917 net_stats->rx_fifo_errors += rqdpc;
4918 }
4919
4920 do {
4921 start = u64_stats_fetch_begin(&ring->rx_syncp);
4922 _bytes = ring->rx_stats.bytes;
4923 _packets = ring->rx_stats.packets;
4924 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));
4925 bytes += _bytes;
4926 packets += _packets;
4927 }
4928
4929 net_stats->rx_bytes = bytes;
4930 net_stats->rx_packets = packets;
4931
4932 packets = 0;
4933 bytes = 0;
4934 for (i = 0; i < adapter->num_tx_queues; i++) {
4935 struct igc_ring *ring = adapter->tx_ring[i];
4936
4937 do {
4938 start = u64_stats_fetch_begin(&ring->tx_syncp);
4939 _bytes = ring->tx_stats.bytes;
4940 _packets = ring->tx_stats.packets;
4941 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));
4942 bytes += _bytes;
4943 packets += _packets;
4944 }
4945 net_stats->tx_bytes = bytes;
4946 net_stats->tx_packets = packets;
4947 rcu_read_unlock();
4948
4949 /* read stats registers */
4950 adapter->stats.crcerrs += rd32(IGC_CRCERRS);
4951 adapter->stats.gprc += rd32(IGC_GPRC);
4952 adapter->stats.gorc += rd32(IGC_GORCL);
4953 rd32(IGC_GORCH); /* clear GORCL */
4954 adapter->stats.bprc += rd32(IGC_BPRC);
4955 adapter->stats.mprc += rd32(IGC_MPRC);
4956 adapter->stats.roc += rd32(IGC_ROC);
4957
4958 adapter->stats.prc64 += rd32(IGC_PRC64);
4959 adapter->stats.prc127 += rd32(IGC_PRC127);
4960 adapter->stats.prc255 += rd32(IGC_PRC255);
4961 adapter->stats.prc511 += rd32(IGC_PRC511);
4962 adapter->stats.prc1023 += rd32(IGC_PRC1023);
4963 adapter->stats.prc1522 += rd32(IGC_PRC1522);
4964 adapter->stats.tlpic += rd32(IGC_TLPIC);
4965 adapter->stats.rlpic += rd32(IGC_RLPIC);
4966 adapter->stats.hgptc += rd32(IGC_HGPTC);
4967
4968 mpc = rd32(IGC_MPC);
4969 adapter->stats.mpc += mpc;
4970 net_stats->rx_fifo_errors += mpc;
4971 adapter->stats.scc += rd32(IGC_SCC);
4972 adapter->stats.ecol += rd32(IGC_ECOL);
4973 adapter->stats.mcc += rd32(IGC_MCC);
4974 adapter->stats.latecol += rd32(IGC_LATECOL);
4975 adapter->stats.dc += rd32(IGC_DC);
4976 adapter->stats.rlec += rd32(IGC_RLEC);
4977 adapter->stats.xonrxc += rd32(IGC_XONRXC);
4978 adapter->stats.xontxc += rd32(IGC_XONTXC);
4979 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC);
4980 adapter->stats.xofftxc += rd32(IGC_XOFFTXC);
4981 adapter->stats.fcruc += rd32(IGC_FCRUC);
4982 adapter->stats.gptc += rd32(IGC_GPTC);
4983 adapter->stats.gotc += rd32(IGC_GOTCL);
4984 rd32(IGC_GOTCH); /* clear GOTCL */
4985 adapter->stats.rnbc += rd32(IGC_RNBC);
4986 adapter->stats.ruc += rd32(IGC_RUC);
4987 adapter->stats.rfc += rd32(IGC_RFC);
4988 adapter->stats.rjc += rd32(IGC_RJC);
4989 adapter->stats.tor += rd32(IGC_TORH);
4990 adapter->stats.tot += rd32(IGC_TOTH);
4991 adapter->stats.tpr += rd32(IGC_TPR);
4992
4993 adapter->stats.ptc64 += rd32(IGC_PTC64);
4994 adapter->stats.ptc127 += rd32(IGC_PTC127);
4995 adapter->stats.ptc255 += rd32(IGC_PTC255);
4996 adapter->stats.ptc511 += rd32(IGC_PTC511);
4997 adapter->stats.ptc1023 += rd32(IGC_PTC1023);
4998 adapter->stats.ptc1522 += rd32(IGC_PTC1522);
4999
5000 adapter->stats.mptc += rd32(IGC_MPTC);
5001 adapter->stats.bptc += rd32(IGC_BPTC);
5002
5003 adapter->stats.tpt += rd32(IGC_TPT);
5004 adapter->stats.colc += rd32(IGC_COLC);
5005 adapter->stats.colc += rd32(IGC_RERC);
5006
5007 adapter->stats.algnerrc += rd32(IGC_ALGNERRC);
5008
5009 adapter->stats.tsctc += rd32(IGC_TSCTC);
5010
5011 adapter->stats.iac += rd32(IGC_IAC);
5012
5013 /* Fill out the OS statistics structure */
5014 net_stats->multicast = adapter->stats.mprc;
5015 net_stats->collisions = adapter->stats.colc;
5016
5017 /* Rx Errors */
5018
5019 /* RLEC on some newer hardware can be incorrect so build
5020 * our own version based on RUC and ROC
5021 */
5022 net_stats->rx_errors = adapter->stats.rxerrc +
5023 adapter->stats.crcerrs + adapter->stats.algnerrc +
5024 adapter->stats.ruc + adapter->stats.roc +
5025 adapter->stats.cexterr;
5026 net_stats->rx_length_errors = adapter->stats.ruc +
5027 adapter->stats.roc;
5028 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5029 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5030 net_stats->rx_missed_errors = adapter->stats.mpc;
5031
5032 /* Tx Errors */
5033 net_stats->tx_errors = adapter->stats.ecol +
5034 adapter->stats.latecol;
5035 net_stats->tx_aborted_errors = adapter->stats.ecol;
5036 net_stats->tx_window_errors = adapter->stats.latecol;
5037 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5038
5039 /* Tx Dropped */
5040 net_stats->tx_dropped = adapter->stats.txdrop;
5041
5042 /* Management Stats */
5043 adapter->stats.mgptc += rd32(IGC_MGTPTC);
5044 adapter->stats.mgprc += rd32(IGC_MGTPRC);
5045 adapter->stats.mgpdc += rd32(IGC_MGTPDC);
5046 }
5047
5048 /**
5049 * igc_down - Close the interface
5050 * @adapter: board private structure
5051 */
igc_down(struct igc_adapter * adapter)5052 void igc_down(struct igc_adapter *adapter)
5053 {
5054 struct net_device *netdev = adapter->netdev;
5055 struct igc_hw *hw = &adapter->hw;
5056 u32 tctl, rctl;
5057 int i = 0;
5058
5059 set_bit(__IGC_DOWN, &adapter->state);
5060
5061 igc_ptp_suspend(adapter);
5062
5063 if (pci_device_is_present(adapter->pdev)) {
5064 /* disable receives in the hardware */
5065 rctl = rd32(IGC_RCTL);
5066 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);
5067 /* flush and sleep below */
5068 }
5069 /* set trans_start so we don't get spurious watchdogs during reset */
5070 netif_trans_update(netdev);
5071
5072 netif_carrier_off(netdev);
5073 netif_tx_stop_all_queues(netdev);
5074
5075 if (pci_device_is_present(adapter->pdev)) {
5076 /* disable transmits in the hardware */
5077 tctl = rd32(IGC_TCTL);
5078 tctl &= ~IGC_TCTL_EN;
5079 wr32(IGC_TCTL, tctl);
5080 /* flush both disables and wait for them to finish */
5081 wrfl();
5082 usleep_range(10000, 20000);
5083
5084 igc_irq_disable(adapter);
5085 }
5086
5087 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5088
5089 for (i = 0; i < adapter->num_q_vectors; i++) {
5090 if (adapter->q_vector[i]) {
5091 napi_synchronize(&adapter->q_vector[i]->napi);
5092 napi_disable(&adapter->q_vector[i]->napi);
5093 }
5094 }
5095
5096 del_timer_sync(&adapter->watchdog_timer);
5097 del_timer_sync(&adapter->phy_info_timer);
5098
5099 /* record the stats before reset*/
5100 spin_lock(&adapter->stats64_lock);
5101 igc_update_stats(adapter);
5102 spin_unlock(&adapter->stats64_lock);
5103
5104 adapter->link_speed = 0;
5105 adapter->link_duplex = 0;
5106
5107 if (!pci_channel_offline(adapter->pdev))
5108 igc_reset(adapter);
5109
5110 /* clear VLAN promisc flag so VFTA will be updated if necessary */
5111 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;
5112
5113 igc_disable_all_tx_rings_hw(adapter);
5114 igc_clean_all_tx_rings(adapter);
5115 igc_clean_all_rx_rings(adapter);
5116 }
5117
igc_reinit_locked(struct igc_adapter * adapter)5118 void igc_reinit_locked(struct igc_adapter *adapter)
5119 {
5120 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
5121 usleep_range(1000, 2000);
5122 igc_down(adapter);
5123 igc_up(adapter);
5124 clear_bit(__IGC_RESETTING, &adapter->state);
5125 }
5126
igc_reset_task(struct work_struct * work)5127 static void igc_reset_task(struct work_struct *work)
5128 {
5129 struct igc_adapter *adapter;
5130
5131 adapter = container_of(work, struct igc_adapter, reset_task);
5132
5133 rtnl_lock();
5134 /* If we're already down or resetting, just bail */
5135 if (test_bit(__IGC_DOWN, &adapter->state) ||
5136 test_bit(__IGC_RESETTING, &adapter->state)) {
5137 rtnl_unlock();
5138 return;
5139 }
5140
5141 igc_rings_dump(adapter);
5142 igc_regs_dump(adapter);
5143 netdev_err(adapter->netdev, "Reset adapter\n");
5144 igc_reinit_locked(adapter);
5145 rtnl_unlock();
5146 }
5147
5148 /**
5149 * igc_change_mtu - Change the Maximum Transfer Unit
5150 * @netdev: network interface device structure
5151 * @new_mtu: new value for maximum frame size
5152 *
5153 * Returns 0 on success, negative on failure
5154 */
igc_change_mtu(struct net_device * netdev,int new_mtu)5155 static int igc_change_mtu(struct net_device *netdev, int new_mtu)
5156 {
5157 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5158 struct igc_adapter *adapter = netdev_priv(netdev);
5159
5160 if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) {
5161 netdev_dbg(netdev, "Jumbo frames not supported with XDP");
5162 return -EINVAL;
5163 }
5164
5165 /* adjust max frame to be at least the size of a standard frame */
5166 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5167 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5168
5169 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
5170 usleep_range(1000, 2000);
5171
5172 /* igc_down has a dependency on max_frame_size */
5173 adapter->max_frame_size = max_frame;
5174
5175 if (netif_running(netdev))
5176 igc_down(adapter);
5177
5178 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5179 netdev->mtu = new_mtu;
5180
5181 if (netif_running(netdev))
5182 igc_up(adapter);
5183 else
5184 igc_reset(adapter);
5185
5186 clear_bit(__IGC_RESETTING, &adapter->state);
5187
5188 return 0;
5189 }
5190
5191 /**
5192 * igc_tx_timeout - Respond to a Tx Hang
5193 * @netdev: network interface device structure
5194 * @txqueue: queue number that timed out
5195 **/
igc_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)5196 static void igc_tx_timeout(struct net_device *netdev,
5197 unsigned int __always_unused txqueue)
5198 {
5199 struct igc_adapter *adapter = netdev_priv(netdev);
5200 struct igc_hw *hw = &adapter->hw;
5201
5202 /* Do the reset outside of interrupt context */
5203 adapter->tx_timeout_count++;
5204 schedule_work(&adapter->reset_task);
5205 wr32(IGC_EICS,
5206 (adapter->eims_enable_mask & ~adapter->eims_other));
5207 }
5208
5209 /**
5210 * igc_get_stats64 - Get System Network Statistics
5211 * @netdev: network interface device structure
5212 * @stats: rtnl_link_stats64 pointer
5213 *
5214 * Returns the address of the device statistics structure.
5215 * The statistics are updated here and also from the timer callback.
5216 */
igc_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)5217 static void igc_get_stats64(struct net_device *netdev,
5218 struct rtnl_link_stats64 *stats)
5219 {
5220 struct igc_adapter *adapter = netdev_priv(netdev);
5221
5222 spin_lock(&adapter->stats64_lock);
5223 if (!test_bit(__IGC_RESETTING, &adapter->state))
5224 igc_update_stats(adapter);
5225 memcpy(stats, &adapter->stats64, sizeof(*stats));
5226 spin_unlock(&adapter->stats64_lock);
5227 }
5228
igc_fix_features(struct net_device * netdev,netdev_features_t features)5229 static netdev_features_t igc_fix_features(struct net_device *netdev,
5230 netdev_features_t features)
5231 {
5232 /* Since there is no support for separate Rx/Tx vlan accel
5233 * enable/disable make sure Tx flag is always in same state as Rx.
5234 */
5235 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5236 features |= NETIF_F_HW_VLAN_CTAG_TX;
5237 else
5238 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
5239
5240 return features;
5241 }
5242
igc_set_features(struct net_device * netdev,netdev_features_t features)5243 static int igc_set_features(struct net_device *netdev,
5244 netdev_features_t features)
5245 {
5246 netdev_features_t changed = netdev->features ^ features;
5247 struct igc_adapter *adapter = netdev_priv(netdev);
5248
5249 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
5250 igc_vlan_mode(netdev, features);
5251
5252 /* Add VLAN support */
5253 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
5254 return 0;
5255
5256 if (!(features & NETIF_F_NTUPLE))
5257 igc_flush_nfc_rules(adapter);
5258
5259 netdev->features = features;
5260
5261 if (netif_running(netdev))
5262 igc_reinit_locked(adapter);
5263 else
5264 igc_reset(adapter);
5265
5266 return 1;
5267 }
5268
5269 static netdev_features_t
igc_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)5270 igc_features_check(struct sk_buff *skb, struct net_device *dev,
5271 netdev_features_t features)
5272 {
5273 unsigned int network_hdr_len, mac_hdr_len;
5274
5275 /* Make certain the headers can be described by a context descriptor */
5276 mac_hdr_len = skb_network_header(skb) - skb->data;
5277 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN))
5278 return features & ~(NETIF_F_HW_CSUM |
5279 NETIF_F_SCTP_CRC |
5280 NETIF_F_HW_VLAN_CTAG_TX |
5281 NETIF_F_TSO |
5282 NETIF_F_TSO6);
5283
5284 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
5285 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN))
5286 return features & ~(NETIF_F_HW_CSUM |
5287 NETIF_F_SCTP_CRC |
5288 NETIF_F_TSO |
5289 NETIF_F_TSO6);
5290
5291 /* We can only support IPv4 TSO in tunnels if we can mangle the
5292 * inner IP ID field, so strip TSO if MANGLEID is not supported.
5293 */
5294 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
5295 features &= ~NETIF_F_TSO;
5296
5297 return features;
5298 }
5299
igc_tsync_interrupt(struct igc_adapter * adapter)5300 static void igc_tsync_interrupt(struct igc_adapter *adapter)
5301 {
5302 struct igc_hw *hw = &adapter->hw;
5303 u32 tsauxc, sec, nsec, tsicr;
5304 struct ptp_clock_event event;
5305 struct timespec64 ts;
5306
5307 tsicr = rd32(IGC_TSICR);
5308
5309 if (tsicr & IGC_TSICR_SYS_WRAP) {
5310 event.type = PTP_CLOCK_PPS;
5311 if (adapter->ptp_caps.pps)
5312 ptp_clock_event(adapter->ptp_clock, &event);
5313 }
5314
5315 if (tsicr & IGC_TSICR_TXTS) {
5316 /* retrieve hardware timestamp */
5317 igc_ptp_tx_tstamp_event(adapter);
5318 }
5319
5320 if (tsicr & IGC_TSICR_TT0) {
5321 spin_lock(&adapter->tmreg_lock);
5322 ts = timespec64_add(adapter->perout[0].start,
5323 adapter->perout[0].period);
5324 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
5325 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec);
5326 tsauxc = rd32(IGC_TSAUXC);
5327 tsauxc |= IGC_TSAUXC_EN_TT0;
5328 wr32(IGC_TSAUXC, tsauxc);
5329 adapter->perout[0].start = ts;
5330 spin_unlock(&adapter->tmreg_lock);
5331 }
5332
5333 if (tsicr & IGC_TSICR_TT1) {
5334 spin_lock(&adapter->tmreg_lock);
5335 ts = timespec64_add(adapter->perout[1].start,
5336 adapter->perout[1].period);
5337 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
5338 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec);
5339 tsauxc = rd32(IGC_TSAUXC);
5340 tsauxc |= IGC_TSAUXC_EN_TT1;
5341 wr32(IGC_TSAUXC, tsauxc);
5342 adapter->perout[1].start = ts;
5343 spin_unlock(&adapter->tmreg_lock);
5344 }
5345
5346 if (tsicr & IGC_TSICR_AUTT0) {
5347 nsec = rd32(IGC_AUXSTMPL0);
5348 sec = rd32(IGC_AUXSTMPH0);
5349 event.type = PTP_CLOCK_EXTTS;
5350 event.index = 0;
5351 event.timestamp = sec * NSEC_PER_SEC + nsec;
5352 ptp_clock_event(adapter->ptp_clock, &event);
5353 }
5354
5355 if (tsicr & IGC_TSICR_AUTT1) {
5356 nsec = rd32(IGC_AUXSTMPL1);
5357 sec = rd32(IGC_AUXSTMPH1);
5358 event.type = PTP_CLOCK_EXTTS;
5359 event.index = 1;
5360 event.timestamp = sec * NSEC_PER_SEC + nsec;
5361 ptp_clock_event(adapter->ptp_clock, &event);
5362 }
5363 }
5364
5365 /**
5366 * igc_msix_other - msix other interrupt handler
5367 * @irq: interrupt number
5368 * @data: pointer to a q_vector
5369 */
igc_msix_other(int irq,void * data)5370 static irqreturn_t igc_msix_other(int irq, void *data)
5371 {
5372 struct igc_adapter *adapter = data;
5373 struct igc_hw *hw = &adapter->hw;
5374 u32 icr = rd32(IGC_ICR);
5375
5376 /* reading ICR causes bit 31 of EICR to be cleared */
5377 if (icr & IGC_ICR_DRSTA)
5378 schedule_work(&adapter->reset_task);
5379
5380 if (icr & IGC_ICR_DOUTSYNC) {
5381 /* HW is reporting DMA is out of sync */
5382 adapter->stats.doosync++;
5383 }
5384
5385 if (icr & IGC_ICR_LSC) {
5386 hw->mac.get_link_status = true;
5387 /* guard against interrupt when we're going down */
5388 if (!test_bit(__IGC_DOWN, &adapter->state))
5389 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5390 }
5391
5392 if (icr & IGC_ICR_TS)
5393 igc_tsync_interrupt(adapter);
5394
5395 wr32(IGC_EIMS, adapter->eims_other);
5396
5397 return IRQ_HANDLED;
5398 }
5399
igc_write_itr(struct igc_q_vector * q_vector)5400 static void igc_write_itr(struct igc_q_vector *q_vector)
5401 {
5402 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;
5403
5404 if (!q_vector->set_itr)
5405 return;
5406
5407 if (!itr_val)
5408 itr_val = IGC_ITR_VAL_MASK;
5409
5410 itr_val |= IGC_EITR_CNT_IGNR;
5411
5412 writel(itr_val, q_vector->itr_register);
5413 q_vector->set_itr = 0;
5414 }
5415
igc_msix_ring(int irq,void * data)5416 static irqreturn_t igc_msix_ring(int irq, void *data)
5417 {
5418 struct igc_q_vector *q_vector = data;
5419
5420 /* Write the ITR value calculated from the previous interrupt. */
5421 igc_write_itr(q_vector);
5422
5423 napi_schedule(&q_vector->napi);
5424
5425 return IRQ_HANDLED;
5426 }
5427
5428 /**
5429 * igc_request_msix - Initialize MSI-X interrupts
5430 * @adapter: Pointer to adapter structure
5431 *
5432 * igc_request_msix allocates MSI-X vectors and requests interrupts from the
5433 * kernel.
5434 */
igc_request_msix(struct igc_adapter * adapter)5435 static int igc_request_msix(struct igc_adapter *adapter)
5436 {
5437 unsigned int num_q_vectors = adapter->num_q_vectors;
5438 int i = 0, err = 0, vector = 0, free_vector = 0;
5439 struct net_device *netdev = adapter->netdev;
5440
5441 err = request_irq(adapter->msix_entries[vector].vector,
5442 &igc_msix_other, 0, netdev->name, adapter);
5443 if (err)
5444 goto err_out;
5445
5446 if (num_q_vectors > MAX_Q_VECTORS) {
5447 num_q_vectors = MAX_Q_VECTORS;
5448 dev_warn(&adapter->pdev->dev,
5449 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
5450 adapter->num_q_vectors, MAX_Q_VECTORS);
5451 }
5452 for (i = 0; i < num_q_vectors; i++) {
5453 struct igc_q_vector *q_vector = adapter->q_vector[i];
5454
5455 vector++;
5456
5457 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
5458
5459 if (q_vector->rx.ring && q_vector->tx.ring)
5460 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
5461 q_vector->rx.ring->queue_index);
5462 else if (q_vector->tx.ring)
5463 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
5464 q_vector->tx.ring->queue_index);
5465 else if (q_vector->rx.ring)
5466 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
5467 q_vector->rx.ring->queue_index);
5468 else
5469 sprintf(q_vector->name, "%s-unused", netdev->name);
5470
5471 err = request_irq(adapter->msix_entries[vector].vector,
5472 igc_msix_ring, 0, q_vector->name,
5473 q_vector);
5474 if (err)
5475 goto err_free;
5476 }
5477
5478 igc_configure_msix(adapter);
5479 return 0;
5480
5481 err_free:
5482 /* free already assigned IRQs */
5483 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
5484
5485 vector--;
5486 for (i = 0; i < vector; i++) {
5487 free_irq(adapter->msix_entries[free_vector++].vector,
5488 adapter->q_vector[i]);
5489 }
5490 err_out:
5491 return err;
5492 }
5493
5494 /**
5495 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts
5496 * @adapter: Pointer to adapter structure
5497 *
5498 * This function resets the device so that it has 0 rx queues, tx queues, and
5499 * MSI-X interrupts allocated.
5500 */
igc_clear_interrupt_scheme(struct igc_adapter * adapter)5501 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)
5502 {
5503 igc_free_q_vectors(adapter);
5504 igc_reset_interrupt_capability(adapter);
5505 }
5506
5507 /* Need to wait a few seconds after link up to get diagnostic information from
5508 * the phy
5509 */
igc_update_phy_info(struct timer_list * t)5510 static void igc_update_phy_info(struct timer_list *t)
5511 {
5512 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5513
5514 igc_get_phy_info(&adapter->hw);
5515 }
5516
5517 /**
5518 * igc_has_link - check shared code for link and determine up/down
5519 * @adapter: pointer to driver private info
5520 */
igc_has_link(struct igc_adapter * adapter)5521 bool igc_has_link(struct igc_adapter *adapter)
5522 {
5523 struct igc_hw *hw = &adapter->hw;
5524 bool link_active = false;
5525
5526 /* get_link_status is set on LSC (link status) interrupt or
5527 * rx sequence error interrupt. get_link_status will stay
5528 * false until the igc_check_for_link establishes link
5529 * for copper adapters ONLY
5530 */
5531 if (!hw->mac.get_link_status)
5532 return true;
5533 hw->mac.ops.check_for_link(hw);
5534 link_active = !hw->mac.get_link_status;
5535
5536 if (hw->mac.type == igc_i225) {
5537 if (!netif_carrier_ok(adapter->netdev)) {
5538 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5539 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {
5540 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;
5541 adapter->link_check_timeout = jiffies;
5542 }
5543 }
5544
5545 return link_active;
5546 }
5547
5548 /**
5549 * igc_watchdog - Timer Call-back
5550 * @t: timer for the watchdog
5551 */
igc_watchdog(struct timer_list * t)5552 static void igc_watchdog(struct timer_list *t)
5553 {
5554 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5555 /* Do the rest outside of interrupt context */
5556 schedule_work(&adapter->watchdog_task);
5557 }
5558
igc_watchdog_task(struct work_struct * work)5559 static void igc_watchdog_task(struct work_struct *work)
5560 {
5561 struct igc_adapter *adapter = container_of(work,
5562 struct igc_adapter,
5563 watchdog_task);
5564 struct net_device *netdev = adapter->netdev;
5565 struct igc_hw *hw = &adapter->hw;
5566 struct igc_phy_info *phy = &hw->phy;
5567 u16 phy_data, retry_count = 20;
5568 u32 link;
5569 int i;
5570
5571 link = igc_has_link(adapter);
5572
5573 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {
5574 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5575 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
5576 else
5577 link = false;
5578 }
5579
5580 if (link) {
5581 /* Cancel scheduled suspend requests. */
5582 pm_runtime_resume(netdev->dev.parent);
5583
5584 if (!netif_carrier_ok(netdev)) {
5585 u32 ctrl;
5586
5587 hw->mac.ops.get_speed_and_duplex(hw,
5588 &adapter->link_speed,
5589 &adapter->link_duplex);
5590
5591 ctrl = rd32(IGC_CTRL);
5592 /* Link status message must follow this format */
5593 netdev_info(netdev,
5594 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5595 adapter->link_speed,
5596 adapter->link_duplex == FULL_DUPLEX ?
5597 "Full" : "Half",
5598 (ctrl & IGC_CTRL_TFCE) &&
5599 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :
5600 (ctrl & IGC_CTRL_RFCE) ? "RX" :
5601 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None");
5602
5603 /* disable EEE if enabled */
5604 if ((adapter->flags & IGC_FLAG_EEE) &&
5605 adapter->link_duplex == HALF_DUPLEX) {
5606 netdev_info(netdev,
5607 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n");
5608 adapter->hw.dev_spec._base.eee_enable = false;
5609 adapter->flags &= ~IGC_FLAG_EEE;
5610 }
5611
5612 /* check if SmartSpeed worked */
5613 igc_check_downshift(hw);
5614 if (phy->speed_downgraded)
5615 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5616
5617 /* adjust timeout factor according to speed/duplex */
5618 adapter->tx_timeout_factor = 1;
5619 switch (adapter->link_speed) {
5620 case SPEED_10:
5621 adapter->tx_timeout_factor = 14;
5622 break;
5623 case SPEED_100:
5624 case SPEED_1000:
5625 case SPEED_2500:
5626 adapter->tx_timeout_factor = 1;
5627 break;
5628 }
5629
5630 /* Once the launch time has been set on the wire, there
5631 * is a delay before the link speed can be determined
5632 * based on link-up activity. Write into the register
5633 * as soon as we know the correct link speed.
5634 */
5635 igc_tsn_adjust_txtime_offset(adapter);
5636
5637 if (adapter->link_speed != SPEED_1000)
5638 goto no_wait;
5639
5640 /* wait for Remote receiver status OK */
5641 retry_read_status:
5642 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,
5643 &phy_data)) {
5644 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5645 retry_count) {
5646 msleep(100);
5647 retry_count--;
5648 goto retry_read_status;
5649 } else if (!retry_count) {
5650 netdev_err(netdev, "exceed max 2 second\n");
5651 }
5652 } else {
5653 netdev_err(netdev, "read 1000Base-T Status Reg\n");
5654 }
5655 no_wait:
5656 netif_carrier_on(netdev);
5657
5658 /* link state has changed, schedule phy info update */
5659 if (!test_bit(__IGC_DOWN, &adapter->state))
5660 mod_timer(&adapter->phy_info_timer,
5661 round_jiffies(jiffies + 2 * HZ));
5662 }
5663 } else {
5664 if (netif_carrier_ok(netdev)) {
5665 adapter->link_speed = 0;
5666 adapter->link_duplex = 0;
5667
5668 /* Links status message must follow this format */
5669 netdev_info(netdev, "NIC Link is Down\n");
5670 netif_carrier_off(netdev);
5671
5672 /* link state has changed, schedule phy info update */
5673 if (!test_bit(__IGC_DOWN, &adapter->state))
5674 mod_timer(&adapter->phy_info_timer,
5675 round_jiffies(jiffies + 2 * HZ));
5676
5677 pm_schedule_suspend(netdev->dev.parent,
5678 MSEC_PER_SEC * 5);
5679 }
5680 }
5681
5682 spin_lock(&adapter->stats64_lock);
5683 igc_update_stats(adapter);
5684 spin_unlock(&adapter->stats64_lock);
5685
5686 for (i = 0; i < adapter->num_tx_queues; i++) {
5687 struct igc_ring *tx_ring = adapter->tx_ring[i];
5688
5689 if (!netif_carrier_ok(netdev)) {
5690 /* We've lost link, so the controller stops DMA,
5691 * but we've got queued Tx work that's never going
5692 * to get done, so reset controller to flush Tx.
5693 * (Do the reset outside of interrupt context).
5694 */
5695 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {
5696 adapter->tx_timeout_count++;
5697 schedule_work(&adapter->reset_task);
5698 /* return immediately since reset is imminent */
5699 return;
5700 }
5701 }
5702
5703 /* Force detection of hung controller every watchdog period */
5704 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5705 }
5706
5707 /* Cause software interrupt to ensure Rx ring is cleaned */
5708 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
5709 u32 eics = 0;
5710
5711 for (i = 0; i < adapter->num_q_vectors; i++)
5712 eics |= adapter->q_vector[i]->eims_value;
5713 wr32(IGC_EICS, eics);
5714 } else {
5715 wr32(IGC_ICS, IGC_ICS_RXDMT0);
5716 }
5717
5718 igc_ptp_tx_hang(adapter);
5719
5720 /* Reset the timer */
5721 if (!test_bit(__IGC_DOWN, &adapter->state)) {
5722 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)
5723 mod_timer(&adapter->watchdog_timer,
5724 round_jiffies(jiffies + HZ));
5725 else
5726 mod_timer(&adapter->watchdog_timer,
5727 round_jiffies(jiffies + 2 * HZ));
5728 }
5729 }
5730
5731 /**
5732 * igc_intr_msi - Interrupt Handler
5733 * @irq: interrupt number
5734 * @data: pointer to a network interface device structure
5735 */
igc_intr_msi(int irq,void * data)5736 static irqreturn_t igc_intr_msi(int irq, void *data)
5737 {
5738 struct igc_adapter *adapter = data;
5739 struct igc_q_vector *q_vector = adapter->q_vector[0];
5740 struct igc_hw *hw = &adapter->hw;
5741 /* read ICR disables interrupts using IAM */
5742 u32 icr = rd32(IGC_ICR);
5743
5744 igc_write_itr(q_vector);
5745
5746 if (icr & IGC_ICR_DRSTA)
5747 schedule_work(&adapter->reset_task);
5748
5749 if (icr & IGC_ICR_DOUTSYNC) {
5750 /* HW is reporting DMA is out of sync */
5751 adapter->stats.doosync++;
5752 }
5753
5754 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
5755 hw->mac.get_link_status = true;
5756 if (!test_bit(__IGC_DOWN, &adapter->state))
5757 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5758 }
5759
5760 if (icr & IGC_ICR_TS)
5761 igc_tsync_interrupt(adapter);
5762
5763 napi_schedule(&q_vector->napi);
5764
5765 return IRQ_HANDLED;
5766 }
5767
5768 /**
5769 * igc_intr - Legacy Interrupt Handler
5770 * @irq: interrupt number
5771 * @data: pointer to a network interface device structure
5772 */
igc_intr(int irq,void * data)5773 static irqreturn_t igc_intr(int irq, void *data)
5774 {
5775 struct igc_adapter *adapter = data;
5776 struct igc_q_vector *q_vector = adapter->q_vector[0];
5777 struct igc_hw *hw = &adapter->hw;
5778 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5779 * need for the IMC write
5780 */
5781 u32 icr = rd32(IGC_ICR);
5782
5783 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5784 * not set, then the adapter didn't send an interrupt
5785 */
5786 if (!(icr & IGC_ICR_INT_ASSERTED))
5787 return IRQ_NONE;
5788
5789 igc_write_itr(q_vector);
5790
5791 if (icr & IGC_ICR_DRSTA)
5792 schedule_work(&adapter->reset_task);
5793
5794 if (icr & IGC_ICR_DOUTSYNC) {
5795 /* HW is reporting DMA is out of sync */
5796 adapter->stats.doosync++;
5797 }
5798
5799 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
5800 hw->mac.get_link_status = true;
5801 /* guard against interrupt when we're going down */
5802 if (!test_bit(__IGC_DOWN, &adapter->state))
5803 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5804 }
5805
5806 if (icr & IGC_ICR_TS)
5807 igc_tsync_interrupt(adapter);
5808
5809 napi_schedule(&q_vector->napi);
5810
5811 return IRQ_HANDLED;
5812 }
5813
igc_free_irq(struct igc_adapter * adapter)5814 static void igc_free_irq(struct igc_adapter *adapter)
5815 {
5816 if (adapter->msix_entries) {
5817 int vector = 0, i;
5818
5819 free_irq(adapter->msix_entries[vector++].vector, adapter);
5820
5821 for (i = 0; i < adapter->num_q_vectors; i++)
5822 free_irq(adapter->msix_entries[vector++].vector,
5823 adapter->q_vector[i]);
5824 } else {
5825 free_irq(adapter->pdev->irq, adapter);
5826 }
5827 }
5828
5829 /**
5830 * igc_request_irq - initialize interrupts
5831 * @adapter: Pointer to adapter structure
5832 *
5833 * Attempts to configure interrupts using the best available
5834 * capabilities of the hardware and kernel.
5835 */
igc_request_irq(struct igc_adapter * adapter)5836 static int igc_request_irq(struct igc_adapter *adapter)
5837 {
5838 struct net_device *netdev = adapter->netdev;
5839 struct pci_dev *pdev = adapter->pdev;
5840 int err = 0;
5841
5842 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
5843 err = igc_request_msix(adapter);
5844 if (!err)
5845 goto request_done;
5846 /* fall back to MSI */
5847 igc_free_all_tx_resources(adapter);
5848 igc_free_all_rx_resources(adapter);
5849
5850 igc_clear_interrupt_scheme(adapter);
5851 err = igc_init_interrupt_scheme(adapter, false);
5852 if (err)
5853 goto request_done;
5854 igc_setup_all_tx_resources(adapter);
5855 igc_setup_all_rx_resources(adapter);
5856 igc_configure(adapter);
5857 }
5858
5859 igc_assign_vector(adapter->q_vector[0], 0);
5860
5861 if (adapter->flags & IGC_FLAG_HAS_MSI) {
5862 err = request_irq(pdev->irq, &igc_intr_msi, 0,
5863 netdev->name, adapter);
5864 if (!err)
5865 goto request_done;
5866
5867 /* fall back to legacy interrupts */
5868 igc_reset_interrupt_capability(adapter);
5869 adapter->flags &= ~IGC_FLAG_HAS_MSI;
5870 }
5871
5872 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,
5873 netdev->name, adapter);
5874
5875 if (err)
5876 netdev_err(netdev, "Error %d getting interrupt\n", err);
5877
5878 request_done:
5879 return err;
5880 }
5881
5882 /**
5883 * __igc_open - Called when a network interface is made active
5884 * @netdev: network interface device structure
5885 * @resuming: boolean indicating if the device is resuming
5886 *
5887 * Returns 0 on success, negative value on failure
5888 *
5889 * The open entry point is called when a network interface is made
5890 * active by the system (IFF_UP). At this point all resources needed
5891 * for transmit and receive operations are allocated, the interrupt
5892 * handler is registered with the OS, the watchdog timer is started,
5893 * and the stack is notified that the interface is ready.
5894 */
__igc_open(struct net_device * netdev,bool resuming)5895 static int __igc_open(struct net_device *netdev, bool resuming)
5896 {
5897 struct igc_adapter *adapter = netdev_priv(netdev);
5898 struct pci_dev *pdev = adapter->pdev;
5899 struct igc_hw *hw = &adapter->hw;
5900 int err = 0;
5901 int i = 0;
5902
5903 /* disallow open during test */
5904
5905 if (test_bit(__IGC_TESTING, &adapter->state)) {
5906 WARN_ON(resuming);
5907 return -EBUSY;
5908 }
5909
5910 if (!resuming)
5911 pm_runtime_get_sync(&pdev->dev);
5912
5913 netif_carrier_off(netdev);
5914
5915 /* allocate transmit descriptors */
5916 err = igc_setup_all_tx_resources(adapter);
5917 if (err)
5918 goto err_setup_tx;
5919
5920 /* allocate receive descriptors */
5921 err = igc_setup_all_rx_resources(adapter);
5922 if (err)
5923 goto err_setup_rx;
5924
5925 igc_power_up_link(adapter);
5926
5927 igc_configure(adapter);
5928
5929 err = igc_request_irq(adapter);
5930 if (err)
5931 goto err_req_irq;
5932
5933 /* Notify the stack of the actual queue counts. */
5934 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
5935 if (err)
5936 goto err_set_queues;
5937
5938 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
5939 if (err)
5940 goto err_set_queues;
5941
5942 clear_bit(__IGC_DOWN, &adapter->state);
5943
5944 for (i = 0; i < adapter->num_q_vectors; i++)
5945 napi_enable(&adapter->q_vector[i]->napi);
5946
5947 /* Clear any pending interrupts. */
5948 rd32(IGC_ICR);
5949 igc_irq_enable(adapter);
5950
5951 if (!resuming)
5952 pm_runtime_put(&pdev->dev);
5953
5954 netif_tx_start_all_queues(netdev);
5955
5956 /* start the watchdog. */
5957 hw->mac.get_link_status = true;
5958 schedule_work(&adapter->watchdog_task);
5959
5960 return IGC_SUCCESS;
5961
5962 err_set_queues:
5963 igc_free_irq(adapter);
5964 err_req_irq:
5965 igc_release_hw_control(adapter);
5966 igc_power_down_phy_copper_base(&adapter->hw);
5967 igc_free_all_rx_resources(adapter);
5968 err_setup_rx:
5969 igc_free_all_tx_resources(adapter);
5970 err_setup_tx:
5971 igc_reset(adapter);
5972 if (!resuming)
5973 pm_runtime_put(&pdev->dev);
5974
5975 return err;
5976 }
5977
igc_open(struct net_device * netdev)5978 int igc_open(struct net_device *netdev)
5979 {
5980 return __igc_open(netdev, false);
5981 }
5982
5983 /**
5984 * __igc_close - Disables a network interface
5985 * @netdev: network interface device structure
5986 * @suspending: boolean indicating the device is suspending
5987 *
5988 * Returns 0, this is not allowed to fail
5989 *
5990 * The close entry point is called when an interface is de-activated
5991 * by the OS. The hardware is still under the driver's control, but
5992 * needs to be disabled. A global MAC reset is issued to stop the
5993 * hardware, and all transmit and receive resources are freed.
5994 */
__igc_close(struct net_device * netdev,bool suspending)5995 static int __igc_close(struct net_device *netdev, bool suspending)
5996 {
5997 struct igc_adapter *adapter = netdev_priv(netdev);
5998 struct pci_dev *pdev = adapter->pdev;
5999
6000 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));
6001
6002 if (!suspending)
6003 pm_runtime_get_sync(&pdev->dev);
6004
6005 igc_down(adapter);
6006
6007 igc_release_hw_control(adapter);
6008
6009 igc_free_irq(adapter);
6010
6011 igc_free_all_tx_resources(adapter);
6012 igc_free_all_rx_resources(adapter);
6013
6014 if (!suspending)
6015 pm_runtime_put_sync(&pdev->dev);
6016
6017 return 0;
6018 }
6019
igc_close(struct net_device * netdev)6020 int igc_close(struct net_device *netdev)
6021 {
6022 if (netif_device_present(netdev) || netdev->dismantle)
6023 return __igc_close(netdev, false);
6024 return 0;
6025 }
6026
6027 /**
6028 * igc_ioctl - Access the hwtstamp interface
6029 * @netdev: network interface device structure
6030 * @ifr: interface request data
6031 * @cmd: ioctl command
6032 **/
igc_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)6033 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6034 {
6035 switch (cmd) {
6036 case SIOCGHWTSTAMP:
6037 return igc_ptp_get_ts_config(netdev, ifr);
6038 case SIOCSHWTSTAMP:
6039 return igc_ptp_set_ts_config(netdev, ifr);
6040 default:
6041 return -EOPNOTSUPP;
6042 }
6043 }
6044
igc_save_launchtime_params(struct igc_adapter * adapter,int queue,bool enable)6045 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue,
6046 bool enable)
6047 {
6048 struct igc_ring *ring;
6049
6050 if (queue < 0 || queue >= adapter->num_tx_queues)
6051 return -EINVAL;
6052
6053 ring = adapter->tx_ring[queue];
6054 ring->launchtime_enable = enable;
6055
6056 return 0;
6057 }
6058
is_base_time_past(ktime_t base_time,const struct timespec64 * now)6059 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
6060 {
6061 struct timespec64 b;
6062
6063 b = ktime_to_timespec64(base_time);
6064
6065 return timespec64_compare(now, &b) > 0;
6066 }
6067
validate_schedule(struct igc_adapter * adapter,const struct tc_taprio_qopt_offload * qopt)6068 static bool validate_schedule(struct igc_adapter *adapter,
6069 const struct tc_taprio_qopt_offload *qopt)
6070 {
6071 int queue_uses[IGC_MAX_TX_QUEUES] = { };
6072 struct igc_hw *hw = &adapter->hw;
6073 struct timespec64 now;
6074 size_t n;
6075
6076 if (qopt->cycle_time_extension)
6077 return false;
6078
6079 igc_ptp_read(adapter, &now);
6080
6081 /* If we program the controller's BASET registers with a time
6082 * in the future, it will hold all the packets until that
6083 * time, causing a lot of TX Hangs, so to avoid that, we
6084 * reject schedules that would start in the future.
6085 * Note: Limitation above is no longer in i226.
6086 */
6087 if (!is_base_time_past(qopt->base_time, &now) &&
6088 igc_is_device_id_i225(hw))
6089 return false;
6090
6091 for (n = 0; n < qopt->num_entries; n++) {
6092 const struct tc_taprio_sched_entry *e, *prev;
6093 int i;
6094
6095 prev = n ? &qopt->entries[n - 1] : NULL;
6096 e = &qopt->entries[n];
6097
6098 /* i225 only supports "global" frame preemption
6099 * settings.
6100 */
6101 if (e->command != TC_TAPRIO_CMD_SET_GATES)
6102 return false;
6103
6104 for (i = 0; i < adapter->num_tx_queues; i++)
6105 if (e->gate_mask & BIT(i)) {
6106 queue_uses[i]++;
6107
6108 /* There are limitations: A single queue cannot
6109 * be opened and closed multiple times per cycle
6110 * unless the gate stays open. Check for it.
6111 */
6112 if (queue_uses[i] > 1 &&
6113 !(prev->gate_mask & BIT(i)))
6114 return false;
6115 }
6116 }
6117
6118 return true;
6119 }
6120
igc_tsn_enable_launchtime(struct igc_adapter * adapter,struct tc_etf_qopt_offload * qopt)6121 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter,
6122 struct tc_etf_qopt_offload *qopt)
6123 {
6124 struct igc_hw *hw = &adapter->hw;
6125 int err;
6126
6127 if (hw->mac.type != igc_i225)
6128 return -EOPNOTSUPP;
6129
6130 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable);
6131 if (err)
6132 return err;
6133
6134 return igc_tsn_offload_apply(adapter);
6135 }
6136
igc_qbv_clear_schedule(struct igc_adapter * adapter)6137 static int igc_qbv_clear_schedule(struct igc_adapter *adapter)
6138 {
6139 unsigned long flags;
6140 int i;
6141
6142 adapter->base_time = 0;
6143 adapter->cycle_time = NSEC_PER_SEC;
6144 adapter->taprio_offload_enable = false;
6145 adapter->qbv_config_change_errors = 0;
6146 adapter->qbv_count = 0;
6147
6148 for (i = 0; i < adapter->num_tx_queues; i++) {
6149 struct igc_ring *ring = adapter->tx_ring[i];
6150
6151 ring->start_time = 0;
6152 ring->end_time = NSEC_PER_SEC;
6153 ring->max_sdu = 0;
6154 }
6155
6156 spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6157
6158 adapter->qbv_transition = false;
6159
6160 for (i = 0; i < adapter->num_tx_queues; i++) {
6161 struct igc_ring *ring = adapter->tx_ring[i];
6162
6163 ring->oper_gate_closed = false;
6164 ring->admin_gate_closed = false;
6165 }
6166
6167 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6168
6169 return 0;
6170 }
6171
igc_tsn_clear_schedule(struct igc_adapter * adapter)6172 static int igc_tsn_clear_schedule(struct igc_adapter *adapter)
6173 {
6174 igc_qbv_clear_schedule(adapter);
6175
6176 return 0;
6177 }
6178
igc_taprio_stats(struct net_device * dev,struct tc_taprio_qopt_stats * stats)6179 static void igc_taprio_stats(struct net_device *dev,
6180 struct tc_taprio_qopt_stats *stats)
6181 {
6182 /* When Strict_End is enabled, the tx_overruns counter
6183 * will always be zero.
6184 */
6185 stats->tx_overruns = 0;
6186 }
6187
igc_taprio_queue_stats(struct net_device * dev,struct tc_taprio_qopt_queue_stats * queue_stats)6188 static void igc_taprio_queue_stats(struct net_device *dev,
6189 struct tc_taprio_qopt_queue_stats *queue_stats)
6190 {
6191 struct tc_taprio_qopt_stats *stats = &queue_stats->stats;
6192
6193 /* When Strict_End is enabled, the tx_overruns counter
6194 * will always be zero.
6195 */
6196 stats->tx_overruns = 0;
6197 }
6198
igc_save_qbv_schedule(struct igc_adapter * adapter,struct tc_taprio_qopt_offload * qopt)6199 static int igc_save_qbv_schedule(struct igc_adapter *adapter,
6200 struct tc_taprio_qopt_offload *qopt)
6201 {
6202 bool queue_configured[IGC_MAX_TX_QUEUES] = { };
6203 struct igc_hw *hw = &adapter->hw;
6204 u32 start_time = 0, end_time = 0;
6205 struct timespec64 now;
6206 unsigned long flags;
6207 size_t n;
6208 int i;
6209
6210 if (qopt->base_time < 0)
6211 return -ERANGE;
6212
6213 if (igc_is_device_id_i225(hw) && adapter->taprio_offload_enable)
6214 return -EALREADY;
6215
6216 if (!validate_schedule(adapter, qopt))
6217 return -EINVAL;
6218
6219 igc_ptp_read(adapter, &now);
6220
6221 if (igc_tsn_is_taprio_activated_by_user(adapter) &&
6222 is_base_time_past(qopt->base_time, &now))
6223 adapter->qbv_config_change_errors++;
6224
6225 adapter->cycle_time = qopt->cycle_time;
6226 adapter->base_time = qopt->base_time;
6227 adapter->taprio_offload_enable = true;
6228
6229 for (n = 0; n < qopt->num_entries; n++) {
6230 struct tc_taprio_sched_entry *e = &qopt->entries[n];
6231
6232 end_time += e->interval;
6233
6234 /* If any of the conditions below are true, we need to manually
6235 * control the end time of the cycle.
6236 * 1. Qbv users can specify a cycle time that is not equal
6237 * to the total GCL intervals. Hence, recalculation is
6238 * necessary here to exclude the time interval that
6239 * exceeds the cycle time.
6240 * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2,
6241 * once the end of the list is reached, it will switch
6242 * to the END_OF_CYCLE state and leave the gates in the
6243 * same state until the next cycle is started.
6244 */
6245 if (end_time > adapter->cycle_time ||
6246 n + 1 == qopt->num_entries)
6247 end_time = adapter->cycle_time;
6248
6249 for (i = 0; i < adapter->num_tx_queues; i++) {
6250 struct igc_ring *ring = adapter->tx_ring[i];
6251
6252 if (!(e->gate_mask & BIT(i)))
6253 continue;
6254
6255 /* Check whether a queue stays open for more than one
6256 * entry. If so, keep the start and advance the end
6257 * time.
6258 */
6259 if (!queue_configured[i])
6260 ring->start_time = start_time;
6261 ring->end_time = end_time;
6262
6263 if (ring->start_time >= adapter->cycle_time)
6264 queue_configured[i] = false;
6265 else
6266 queue_configured[i] = true;
6267 }
6268
6269 start_time += e->interval;
6270 }
6271
6272 spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6273
6274 /* Check whether a queue gets configured.
6275 * If not, set the start and end time to be end time.
6276 */
6277 for (i = 0; i < adapter->num_tx_queues; i++) {
6278 struct igc_ring *ring = adapter->tx_ring[i];
6279
6280 if (!is_base_time_past(qopt->base_time, &now)) {
6281 ring->admin_gate_closed = false;
6282 } else {
6283 ring->oper_gate_closed = false;
6284 ring->admin_gate_closed = false;
6285 }
6286
6287 if (!queue_configured[i]) {
6288 if (!is_base_time_past(qopt->base_time, &now))
6289 ring->admin_gate_closed = true;
6290 else
6291 ring->oper_gate_closed = true;
6292
6293 ring->start_time = end_time;
6294 ring->end_time = end_time;
6295 }
6296 }
6297
6298 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6299
6300 for (i = 0; i < adapter->num_tx_queues; i++) {
6301 struct igc_ring *ring = adapter->tx_ring[i];
6302 struct net_device *dev = adapter->netdev;
6303
6304 if (qopt->max_sdu[i])
6305 ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len - ETH_TLEN;
6306 else
6307 ring->max_sdu = 0;
6308 }
6309
6310 return 0;
6311 }
6312
igc_tsn_enable_qbv_scheduling(struct igc_adapter * adapter,struct tc_taprio_qopt_offload * qopt)6313 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,
6314 struct tc_taprio_qopt_offload *qopt)
6315 {
6316 struct igc_hw *hw = &adapter->hw;
6317 int err;
6318
6319 if (hw->mac.type != igc_i225)
6320 return -EOPNOTSUPP;
6321
6322 switch (qopt->cmd) {
6323 case TAPRIO_CMD_REPLACE:
6324 err = igc_save_qbv_schedule(adapter, qopt);
6325 break;
6326 case TAPRIO_CMD_DESTROY:
6327 err = igc_tsn_clear_schedule(adapter);
6328 break;
6329 case TAPRIO_CMD_STATS:
6330 igc_taprio_stats(adapter->netdev, &qopt->stats);
6331 return 0;
6332 case TAPRIO_CMD_QUEUE_STATS:
6333 igc_taprio_queue_stats(adapter->netdev, &qopt->queue_stats);
6334 return 0;
6335 default:
6336 return -EOPNOTSUPP;
6337 }
6338
6339 if (err)
6340 return err;
6341
6342 return igc_tsn_offload_apply(adapter);
6343 }
6344
igc_save_cbs_params(struct igc_adapter * adapter,int queue,bool enable,int idleslope,int sendslope,int hicredit,int locredit)6345 static int igc_save_cbs_params(struct igc_adapter *adapter, int queue,
6346 bool enable, int idleslope, int sendslope,
6347 int hicredit, int locredit)
6348 {
6349 bool cbs_status[IGC_MAX_SR_QUEUES] = { false };
6350 struct net_device *netdev = adapter->netdev;
6351 struct igc_ring *ring;
6352 int i;
6353
6354 /* i225 has two sets of credit-based shaper logic.
6355 * Supporting it only on the top two priority queues
6356 */
6357 if (queue < 0 || queue > 1)
6358 return -EINVAL;
6359
6360 ring = adapter->tx_ring[queue];
6361
6362 for (i = 0; i < IGC_MAX_SR_QUEUES; i++)
6363 if (adapter->tx_ring[i])
6364 cbs_status[i] = adapter->tx_ring[i]->cbs_enable;
6365
6366 /* CBS should be enabled on the highest priority queue first in order
6367 * for the CBS algorithm to operate as intended.
6368 */
6369 if (enable) {
6370 if (queue == 1 && !cbs_status[0]) {
6371 netdev_err(netdev,
6372 "Enabling CBS on queue1 before queue0\n");
6373 return -EINVAL;
6374 }
6375 } else {
6376 if (queue == 0 && cbs_status[1]) {
6377 netdev_err(netdev,
6378 "Disabling CBS on queue0 before queue1\n");
6379 return -EINVAL;
6380 }
6381 }
6382
6383 ring->cbs_enable = enable;
6384 ring->idleslope = idleslope;
6385 ring->sendslope = sendslope;
6386 ring->hicredit = hicredit;
6387 ring->locredit = locredit;
6388
6389 return 0;
6390 }
6391
igc_tsn_enable_cbs(struct igc_adapter * adapter,struct tc_cbs_qopt_offload * qopt)6392 static int igc_tsn_enable_cbs(struct igc_adapter *adapter,
6393 struct tc_cbs_qopt_offload *qopt)
6394 {
6395 struct igc_hw *hw = &adapter->hw;
6396 int err;
6397
6398 if (hw->mac.type != igc_i225)
6399 return -EOPNOTSUPP;
6400
6401 if (qopt->queue < 0 || qopt->queue > 1)
6402 return -EINVAL;
6403
6404 err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable,
6405 qopt->idleslope, qopt->sendslope,
6406 qopt->hicredit, qopt->locredit);
6407 if (err)
6408 return err;
6409
6410 return igc_tsn_offload_apply(adapter);
6411 }
6412
igc_tc_query_caps(struct igc_adapter * adapter,struct tc_query_caps_base * base)6413 static int igc_tc_query_caps(struct igc_adapter *adapter,
6414 struct tc_query_caps_base *base)
6415 {
6416 struct igc_hw *hw = &adapter->hw;
6417
6418 switch (base->type) {
6419 case TC_SETUP_QDISC_TAPRIO: {
6420 struct tc_taprio_caps *caps = base->caps;
6421
6422 caps->broken_mqprio = true;
6423
6424 if (hw->mac.type == igc_i225) {
6425 caps->supports_queue_max_sdu = true;
6426 caps->gate_mask_per_txq = true;
6427 }
6428
6429 return 0;
6430 }
6431 default:
6432 return -EOPNOTSUPP;
6433 }
6434 }
6435
igc_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)6436 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type,
6437 void *type_data)
6438 {
6439 struct igc_adapter *adapter = netdev_priv(dev);
6440
6441 adapter->tc_setup_type = type;
6442
6443 switch (type) {
6444 case TC_QUERY_CAPS:
6445 return igc_tc_query_caps(adapter, type_data);
6446 case TC_SETUP_QDISC_TAPRIO:
6447 return igc_tsn_enable_qbv_scheduling(adapter, type_data);
6448
6449 case TC_SETUP_QDISC_ETF:
6450 return igc_tsn_enable_launchtime(adapter, type_data);
6451
6452 case TC_SETUP_QDISC_CBS:
6453 return igc_tsn_enable_cbs(adapter, type_data);
6454
6455 default:
6456 return -EOPNOTSUPP;
6457 }
6458 }
6459
igc_bpf(struct net_device * dev,struct netdev_bpf * bpf)6460 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6461 {
6462 struct igc_adapter *adapter = netdev_priv(dev);
6463
6464 switch (bpf->command) {
6465 case XDP_SETUP_PROG:
6466 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack);
6467 case XDP_SETUP_XSK_POOL:
6468 return igc_xdp_setup_pool(adapter, bpf->xsk.pool,
6469 bpf->xsk.queue_id);
6470 default:
6471 return -EOPNOTSUPP;
6472 }
6473 }
6474
igc_xdp_xmit(struct net_device * dev,int num_frames,struct xdp_frame ** frames,u32 flags)6475 static int igc_xdp_xmit(struct net_device *dev, int num_frames,
6476 struct xdp_frame **frames, u32 flags)
6477 {
6478 struct igc_adapter *adapter = netdev_priv(dev);
6479 int cpu = smp_processor_id();
6480 struct netdev_queue *nq;
6481 struct igc_ring *ring;
6482 int i, nxmit;
6483
6484 if (unlikely(!netif_carrier_ok(dev)))
6485 return -ENETDOWN;
6486
6487 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6488 return -EINVAL;
6489
6490 ring = igc_xdp_get_tx_ring(adapter, cpu);
6491 nq = txring_txq(ring);
6492
6493 __netif_tx_lock(nq, cpu);
6494
6495 /* Avoid transmit queue timeout since we share it with the slow path */
6496 txq_trans_cond_update(nq);
6497
6498 nxmit = 0;
6499 for (i = 0; i < num_frames; i++) {
6500 int err;
6501 struct xdp_frame *xdpf = frames[i];
6502
6503 err = igc_xdp_init_tx_descriptor(ring, xdpf);
6504 if (err)
6505 break;
6506 nxmit++;
6507 }
6508
6509 if (flags & XDP_XMIT_FLUSH)
6510 igc_flush_tx_descriptors(ring);
6511
6512 __netif_tx_unlock(nq);
6513
6514 return nxmit;
6515 }
6516
igc_trigger_rxtxq_interrupt(struct igc_adapter * adapter,struct igc_q_vector * q_vector)6517 static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter,
6518 struct igc_q_vector *q_vector)
6519 {
6520 struct igc_hw *hw = &adapter->hw;
6521 u32 eics = 0;
6522
6523 eics |= q_vector->eims_value;
6524 wr32(IGC_EICS, eics);
6525 }
6526
igc_xsk_wakeup(struct net_device * dev,u32 queue_id,u32 flags)6527 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags)
6528 {
6529 struct igc_adapter *adapter = netdev_priv(dev);
6530 struct igc_q_vector *q_vector;
6531 struct igc_ring *ring;
6532
6533 if (test_bit(__IGC_DOWN, &adapter->state))
6534 return -ENETDOWN;
6535
6536 if (!igc_xdp_is_enabled(adapter))
6537 return -ENXIO;
6538
6539 if (queue_id >= adapter->num_rx_queues)
6540 return -EINVAL;
6541
6542 ring = adapter->rx_ring[queue_id];
6543
6544 if (!ring->xsk_pool)
6545 return -ENXIO;
6546
6547 q_vector = adapter->q_vector[queue_id];
6548 if (!napi_if_scheduled_mark_missed(&q_vector->napi))
6549 igc_trigger_rxtxq_interrupt(adapter, q_vector);
6550
6551 return 0;
6552 }
6553
6554 static const struct net_device_ops igc_netdev_ops = {
6555 .ndo_open = igc_open,
6556 .ndo_stop = igc_close,
6557 .ndo_start_xmit = igc_xmit_frame,
6558 .ndo_set_rx_mode = igc_set_rx_mode,
6559 .ndo_set_mac_address = igc_set_mac,
6560 .ndo_change_mtu = igc_change_mtu,
6561 .ndo_tx_timeout = igc_tx_timeout,
6562 .ndo_get_stats64 = igc_get_stats64,
6563 .ndo_fix_features = igc_fix_features,
6564 .ndo_set_features = igc_set_features,
6565 .ndo_features_check = igc_features_check,
6566 .ndo_eth_ioctl = igc_ioctl,
6567 .ndo_setup_tc = igc_setup_tc,
6568 .ndo_bpf = igc_bpf,
6569 .ndo_xdp_xmit = igc_xdp_xmit,
6570 .ndo_xsk_wakeup = igc_xsk_wakeup,
6571 };
6572
6573 /* PCIe configuration access */
igc_read_pci_cfg(struct igc_hw * hw,u32 reg,u16 * value)6574 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
6575 {
6576 struct igc_adapter *adapter = hw->back;
6577
6578 pci_read_config_word(adapter->pdev, reg, value);
6579 }
6580
igc_write_pci_cfg(struct igc_hw * hw,u32 reg,u16 * value)6581 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
6582 {
6583 struct igc_adapter *adapter = hw->back;
6584
6585 pci_write_config_word(adapter->pdev, reg, *value);
6586 }
6587
igc_read_pcie_cap_reg(struct igc_hw * hw,u32 reg,u16 * value)6588 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
6589 {
6590 struct igc_adapter *adapter = hw->back;
6591
6592 if (!pci_is_pcie(adapter->pdev))
6593 return -IGC_ERR_CONFIG;
6594
6595 pcie_capability_read_word(adapter->pdev, reg, value);
6596
6597 return IGC_SUCCESS;
6598 }
6599
igc_write_pcie_cap_reg(struct igc_hw * hw,u32 reg,u16 * value)6600 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
6601 {
6602 struct igc_adapter *adapter = hw->back;
6603
6604 if (!pci_is_pcie(adapter->pdev))
6605 return -IGC_ERR_CONFIG;
6606
6607 pcie_capability_write_word(adapter->pdev, reg, *value);
6608
6609 return IGC_SUCCESS;
6610 }
6611
igc_rd32(struct igc_hw * hw,u32 reg)6612 u32 igc_rd32(struct igc_hw *hw, u32 reg)
6613 {
6614 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);
6615 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
6616 u32 value = 0;
6617
6618 if (IGC_REMOVED(hw_addr))
6619 return ~value;
6620
6621 value = readl(&hw_addr[reg]);
6622
6623 /* reads should not return all F's */
6624 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
6625 struct net_device *netdev = igc->netdev;
6626
6627 hw->hw_addr = NULL;
6628 netif_device_detach(netdev);
6629 netdev_err(netdev, "PCIe link lost, device now detached\n");
6630 WARN(pci_device_is_present(igc->pdev),
6631 "igc: Failed to read reg 0x%x!\n", reg);
6632 }
6633
6634 return value;
6635 }
6636
6637 /* Mapping HW RSS Type to enum xdp_rss_hash_type */
6638 static enum xdp_rss_hash_type igc_xdp_rss_type[IGC_RSS_TYPE_MAX_TABLE] = {
6639 [IGC_RSS_TYPE_NO_HASH] = XDP_RSS_TYPE_L2,
6640 [IGC_RSS_TYPE_HASH_TCP_IPV4] = XDP_RSS_TYPE_L4_IPV4_TCP,
6641 [IGC_RSS_TYPE_HASH_IPV4] = XDP_RSS_TYPE_L3_IPV4,
6642 [IGC_RSS_TYPE_HASH_TCP_IPV6] = XDP_RSS_TYPE_L4_IPV6_TCP,
6643 [IGC_RSS_TYPE_HASH_IPV6_EX] = XDP_RSS_TYPE_L3_IPV6_EX,
6644 [IGC_RSS_TYPE_HASH_IPV6] = XDP_RSS_TYPE_L3_IPV6,
6645 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_TCP_EX,
6646 [IGC_RSS_TYPE_HASH_UDP_IPV4] = XDP_RSS_TYPE_L4_IPV4_UDP,
6647 [IGC_RSS_TYPE_HASH_UDP_IPV6] = XDP_RSS_TYPE_L4_IPV6_UDP,
6648 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_UDP_EX,
6649 [10] = XDP_RSS_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */
6650 [11] = XDP_RSS_TYPE_NONE, /* keep array sized for SW bit-mask */
6651 [12] = XDP_RSS_TYPE_NONE, /* to handle future HW revisons */
6652 [13] = XDP_RSS_TYPE_NONE,
6653 [14] = XDP_RSS_TYPE_NONE,
6654 [15] = XDP_RSS_TYPE_NONE,
6655 };
6656
igc_xdp_rx_hash(const struct xdp_md * _ctx,u32 * hash,enum xdp_rss_hash_type * rss_type)6657 static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash,
6658 enum xdp_rss_hash_type *rss_type)
6659 {
6660 const struct igc_xdp_buff *ctx = (void *)_ctx;
6661
6662 if (!(ctx->xdp.rxq->dev->features & NETIF_F_RXHASH))
6663 return -ENODATA;
6664
6665 *hash = le32_to_cpu(ctx->rx_desc->wb.lower.hi_dword.rss);
6666 *rss_type = igc_xdp_rss_type[igc_rss_type(ctx->rx_desc)];
6667
6668 return 0;
6669 }
6670
igc_xdp_rx_timestamp(const struct xdp_md * _ctx,u64 * timestamp)6671 static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)
6672 {
6673 const struct igc_xdp_buff *ctx = (void *)_ctx;
6674
6675 if (igc_test_staterr(ctx->rx_desc, IGC_RXDADV_STAT_TSIP)) {
6676 *timestamp = ctx->rx_ts;
6677
6678 return 0;
6679 }
6680
6681 return -ENODATA;
6682 }
6683
6684 static const struct xdp_metadata_ops igc_xdp_metadata_ops = {
6685 .xmo_rx_hash = igc_xdp_rx_hash,
6686 .xmo_rx_timestamp = igc_xdp_rx_timestamp,
6687 };
6688
igc_qbv_scheduling_timer(struct hrtimer * timer)6689 static enum hrtimer_restart igc_qbv_scheduling_timer(struct hrtimer *timer)
6690 {
6691 struct igc_adapter *adapter = container_of(timer, struct igc_adapter,
6692 hrtimer);
6693 unsigned long flags;
6694 unsigned int i;
6695
6696 spin_lock_irqsave(&adapter->qbv_tx_lock, flags);
6697
6698 adapter->qbv_transition = true;
6699 for (i = 0; i < adapter->num_tx_queues; i++) {
6700 struct igc_ring *tx_ring = adapter->tx_ring[i];
6701
6702 if (tx_ring->admin_gate_closed) {
6703 tx_ring->admin_gate_closed = false;
6704 tx_ring->oper_gate_closed = true;
6705 } else {
6706 tx_ring->oper_gate_closed = false;
6707 }
6708 }
6709 adapter->qbv_transition = false;
6710
6711 spin_unlock_irqrestore(&adapter->qbv_tx_lock, flags);
6712
6713 return HRTIMER_NORESTART;
6714 }
6715
6716 /**
6717 * igc_probe - Device Initialization Routine
6718 * @pdev: PCI device information struct
6719 * @ent: entry in igc_pci_tbl
6720 *
6721 * Returns 0 on success, negative on failure
6722 *
6723 * igc_probe initializes an adapter identified by a pci_dev structure.
6724 * The OS initialization, configuring the adapter private structure,
6725 * and a hardware reset occur.
6726 */
igc_probe(struct pci_dev * pdev,const struct pci_device_id * ent)6727 static int igc_probe(struct pci_dev *pdev,
6728 const struct pci_device_id *ent)
6729 {
6730 struct igc_adapter *adapter;
6731 struct net_device *netdev;
6732 struct igc_hw *hw;
6733 const struct igc_info *ei = igc_info_tbl[ent->driver_data];
6734 int err;
6735
6736 err = pci_enable_device_mem(pdev);
6737 if (err)
6738 return err;
6739
6740 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6741 if (err) {
6742 dev_err(&pdev->dev,
6743 "No usable DMA configuration, aborting\n");
6744 goto err_dma;
6745 }
6746
6747 err = pci_request_mem_regions(pdev, igc_driver_name);
6748 if (err)
6749 goto err_pci_reg;
6750
6751 err = pci_enable_ptm(pdev, NULL);
6752 if (err < 0)
6753 dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n");
6754
6755 pci_set_master(pdev);
6756
6757 err = -ENOMEM;
6758 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),
6759 IGC_MAX_TX_QUEUES);
6760
6761 if (!netdev)
6762 goto err_alloc_etherdev;
6763
6764 SET_NETDEV_DEV(netdev, &pdev->dev);
6765
6766 pci_set_drvdata(pdev, netdev);
6767 adapter = netdev_priv(netdev);
6768 adapter->netdev = netdev;
6769 adapter->pdev = pdev;
6770 hw = &adapter->hw;
6771 hw->back = adapter;
6772 adapter->port_num = hw->bus.func;
6773 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6774
6775 err = pci_save_state(pdev);
6776 if (err)
6777 goto err_ioremap;
6778
6779 err = -EIO;
6780 adapter->io_addr = ioremap(pci_resource_start(pdev, 0),
6781 pci_resource_len(pdev, 0));
6782 if (!adapter->io_addr)
6783 goto err_ioremap;
6784
6785 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */
6786 hw->hw_addr = adapter->io_addr;
6787
6788 netdev->netdev_ops = &igc_netdev_ops;
6789 netdev->xdp_metadata_ops = &igc_xdp_metadata_ops;
6790 igc_ethtool_set_ops(netdev);
6791 netdev->watchdog_timeo = 5 * HZ;
6792
6793 netdev->mem_start = pci_resource_start(pdev, 0);
6794 netdev->mem_end = pci_resource_end(pdev, 0);
6795
6796 /* PCI config space info */
6797 hw->vendor_id = pdev->vendor;
6798 hw->device_id = pdev->device;
6799 hw->revision_id = pdev->revision;
6800 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6801 hw->subsystem_device_id = pdev->subsystem_device;
6802
6803 /* Copy the default MAC and PHY function pointers */
6804 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6805 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6806
6807 /* Initialize skew-specific constants */
6808 err = ei->get_invariants(hw);
6809 if (err)
6810 goto err_sw_init;
6811
6812 /* Add supported features to the features list*/
6813 netdev->features |= NETIF_F_SG;
6814 netdev->features |= NETIF_F_TSO;
6815 netdev->features |= NETIF_F_TSO6;
6816 netdev->features |= NETIF_F_TSO_ECN;
6817 netdev->features |= NETIF_F_RXHASH;
6818 netdev->features |= NETIF_F_RXCSUM;
6819 netdev->features |= NETIF_F_HW_CSUM;
6820 netdev->features |= NETIF_F_SCTP_CRC;
6821 netdev->features |= NETIF_F_HW_TC;
6822
6823 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
6824 NETIF_F_GSO_GRE_CSUM | \
6825 NETIF_F_GSO_IPXIP4 | \
6826 NETIF_F_GSO_IPXIP6 | \
6827 NETIF_F_GSO_UDP_TUNNEL | \
6828 NETIF_F_GSO_UDP_TUNNEL_CSUM)
6829
6830 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES;
6831 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES;
6832
6833 /* setup the private structure */
6834 err = igc_sw_init(adapter);
6835 if (err)
6836 goto err_sw_init;
6837
6838 /* copy netdev features into list of user selectable features */
6839 netdev->hw_features |= NETIF_F_NTUPLE;
6840 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
6841 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
6842 netdev->hw_features |= netdev->features;
6843
6844 netdev->features |= NETIF_F_HIGHDMA;
6845
6846 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
6847 netdev->mpls_features |= NETIF_F_HW_CSUM;
6848 netdev->hw_enc_features |= netdev->vlan_features;
6849
6850 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
6851 NETDEV_XDP_ACT_XSK_ZEROCOPY;
6852
6853 /* MTU range: 68 - 9216 */
6854 netdev->min_mtu = ETH_MIN_MTU;
6855 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
6856
6857 /* before reading the NVM, reset the controller to put the device in a
6858 * known good starting state
6859 */
6860 hw->mac.ops.reset_hw(hw);
6861
6862 if (igc_get_flash_presence_i225(hw)) {
6863 if (hw->nvm.ops.validate(hw) < 0) {
6864 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
6865 err = -EIO;
6866 goto err_eeprom;
6867 }
6868 }
6869
6870 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
6871 /* copy the MAC address out of the NVM */
6872 if (hw->mac.ops.read_mac_addr(hw))
6873 dev_err(&pdev->dev, "NVM Read Error\n");
6874 }
6875
6876 eth_hw_addr_set(netdev, hw->mac.addr);
6877
6878 if (!is_valid_ether_addr(netdev->dev_addr)) {
6879 dev_err(&pdev->dev, "Invalid MAC Address\n");
6880 err = -EIO;
6881 goto err_eeprom;
6882 }
6883
6884 /* configure RXPBSIZE and TXPBSIZE */
6885 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);
6886 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
6887
6888 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);
6889 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);
6890
6891 INIT_WORK(&adapter->reset_task, igc_reset_task);
6892 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);
6893
6894 hrtimer_init(&adapter->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6895 adapter->hrtimer.function = &igc_qbv_scheduling_timer;
6896
6897 /* Initialize link properties that are user-changeable */
6898 adapter->fc_autoneg = true;
6899 hw->mac.autoneg = true;
6900 hw->phy.autoneg_advertised = 0xaf;
6901
6902 hw->fc.requested_mode = igc_fc_default;
6903 hw->fc.current_mode = igc_fc_default;
6904
6905 /* By default, support wake on port A */
6906 adapter->flags |= IGC_FLAG_WOL_SUPPORTED;
6907
6908 /* initialize the wol settings based on the eeprom settings */
6909 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED)
6910 adapter->wol |= IGC_WUFC_MAG;
6911
6912 device_set_wakeup_enable(&adapter->pdev->dev,
6913 adapter->flags & IGC_FLAG_WOL_SUPPORTED);
6914
6915 igc_ptp_init(adapter);
6916
6917 igc_tsn_clear_schedule(adapter);
6918
6919 /* reset the hardware with the new settings */
6920 igc_reset(adapter);
6921
6922 /* let the f/w know that the h/w is now under the control of the
6923 * driver.
6924 */
6925 igc_get_hw_control(adapter);
6926
6927 strncpy(netdev->name, "eth%d", IFNAMSIZ);
6928 err = register_netdev(netdev);
6929 if (err)
6930 goto err_register;
6931
6932 /* carrier off reporting is important to ethtool even BEFORE open */
6933 netif_carrier_off(netdev);
6934
6935 /* Check if Media Autosense is enabled */
6936 adapter->ei = *ei;
6937
6938 /* print pcie link status and MAC address */
6939 pcie_print_link_status(pdev);
6940 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);
6941
6942 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
6943 /* Disable EEE for internal PHY devices */
6944 hw->dev_spec._base.eee_enable = false;
6945 adapter->flags &= ~IGC_FLAG_EEE;
6946 igc_set_eee_i225(hw, false, false, false);
6947
6948 pm_runtime_put_noidle(&pdev->dev);
6949
6950 return 0;
6951
6952 err_register:
6953 igc_release_hw_control(adapter);
6954 err_eeprom:
6955 if (!igc_check_reset_block(hw))
6956 igc_reset_phy(hw);
6957 err_sw_init:
6958 igc_clear_interrupt_scheme(adapter);
6959 iounmap(adapter->io_addr);
6960 err_ioremap:
6961 free_netdev(netdev);
6962 err_alloc_etherdev:
6963 pci_release_mem_regions(pdev);
6964 err_pci_reg:
6965 err_dma:
6966 pci_disable_device(pdev);
6967 return err;
6968 }
6969
6970 /**
6971 * igc_remove - Device Removal Routine
6972 * @pdev: PCI device information struct
6973 *
6974 * igc_remove is called by the PCI subsystem to alert the driver
6975 * that it should release a PCI device. This could be caused by a
6976 * Hot-Plug event, or because the driver is going to be removed from
6977 * memory.
6978 */
igc_remove(struct pci_dev * pdev)6979 static void igc_remove(struct pci_dev *pdev)
6980 {
6981 struct net_device *netdev = pci_get_drvdata(pdev);
6982 struct igc_adapter *adapter = netdev_priv(netdev);
6983
6984 pm_runtime_get_noresume(&pdev->dev);
6985
6986 igc_flush_nfc_rules(adapter);
6987
6988 igc_ptp_stop(adapter);
6989
6990 pci_disable_ptm(pdev);
6991 pci_clear_master(pdev);
6992
6993 set_bit(__IGC_DOWN, &adapter->state);
6994
6995 del_timer_sync(&adapter->watchdog_timer);
6996 del_timer_sync(&adapter->phy_info_timer);
6997
6998 cancel_work_sync(&adapter->reset_task);
6999 cancel_work_sync(&adapter->watchdog_task);
7000 hrtimer_cancel(&adapter->hrtimer);
7001
7002 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7003 * would have already happened in close and is redundant.
7004 */
7005 igc_release_hw_control(adapter);
7006 unregister_netdev(netdev);
7007
7008 igc_clear_interrupt_scheme(adapter);
7009 pci_iounmap(pdev, adapter->io_addr);
7010 pci_release_mem_regions(pdev);
7011
7012 free_netdev(netdev);
7013
7014 pci_disable_device(pdev);
7015 }
7016
__igc_shutdown(struct pci_dev * pdev,bool * enable_wake,bool runtime)7017 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake,
7018 bool runtime)
7019 {
7020 struct net_device *netdev = pci_get_drvdata(pdev);
7021 struct igc_adapter *adapter = netdev_priv(netdev);
7022 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol;
7023 struct igc_hw *hw = &adapter->hw;
7024 u32 ctrl, rctl, status;
7025 bool wake;
7026
7027 rtnl_lock();
7028 netif_device_detach(netdev);
7029
7030 if (netif_running(netdev))
7031 __igc_close(netdev, true);
7032
7033 igc_ptp_suspend(adapter);
7034
7035 igc_clear_interrupt_scheme(adapter);
7036 rtnl_unlock();
7037
7038 status = rd32(IGC_STATUS);
7039 if (status & IGC_STATUS_LU)
7040 wufc &= ~IGC_WUFC_LNKC;
7041
7042 if (wufc) {
7043 igc_setup_rctl(adapter);
7044 igc_set_rx_mode(netdev);
7045
7046 /* turn on all-multi mode if wake on multicast is enabled */
7047 if (wufc & IGC_WUFC_MC) {
7048 rctl = rd32(IGC_RCTL);
7049 rctl |= IGC_RCTL_MPE;
7050 wr32(IGC_RCTL, rctl);
7051 }
7052
7053 ctrl = rd32(IGC_CTRL);
7054 ctrl |= IGC_CTRL_ADVD3WUC;
7055 wr32(IGC_CTRL, ctrl);
7056
7057 /* Allow time for pending master requests to run */
7058 igc_disable_pcie_master(hw);
7059
7060 wr32(IGC_WUC, IGC_WUC_PME_EN);
7061 wr32(IGC_WUFC, wufc);
7062 } else {
7063 wr32(IGC_WUC, 0);
7064 wr32(IGC_WUFC, 0);
7065 }
7066
7067 wake = wufc || adapter->en_mng_pt;
7068 if (!wake)
7069 igc_power_down_phy_copper_base(&adapter->hw);
7070 else
7071 igc_power_up_link(adapter);
7072
7073 if (enable_wake)
7074 *enable_wake = wake;
7075
7076 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7077 * would have already happened in close and is redundant.
7078 */
7079 igc_release_hw_control(adapter);
7080
7081 pci_disable_device(pdev);
7082
7083 return 0;
7084 }
7085
7086 #ifdef CONFIG_PM
igc_runtime_suspend(struct device * dev)7087 static int __maybe_unused igc_runtime_suspend(struct device *dev)
7088 {
7089 return __igc_shutdown(to_pci_dev(dev), NULL, 1);
7090 }
7091
igc_deliver_wake_packet(struct net_device * netdev)7092 static void igc_deliver_wake_packet(struct net_device *netdev)
7093 {
7094 struct igc_adapter *adapter = netdev_priv(netdev);
7095 struct igc_hw *hw = &adapter->hw;
7096 struct sk_buff *skb;
7097 u32 wupl;
7098
7099 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK;
7100
7101 /* WUPM stores only the first 128 bytes of the wake packet.
7102 * Read the packet only if we have the whole thing.
7103 */
7104 if (wupl == 0 || wupl > IGC_WUPM_BYTES)
7105 return;
7106
7107 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES);
7108 if (!skb)
7109 return;
7110
7111 skb_put(skb, wupl);
7112
7113 /* Ensure reads are 32-bit aligned */
7114 wupl = roundup(wupl, 4);
7115
7116 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl);
7117
7118 skb->protocol = eth_type_trans(skb, netdev);
7119 netif_rx(skb);
7120 }
7121
igc_resume(struct device * dev)7122 static int __maybe_unused igc_resume(struct device *dev)
7123 {
7124 struct pci_dev *pdev = to_pci_dev(dev);
7125 struct net_device *netdev = pci_get_drvdata(pdev);
7126 struct igc_adapter *adapter = netdev_priv(netdev);
7127 struct igc_hw *hw = &adapter->hw;
7128 u32 err, val;
7129
7130 pci_set_power_state(pdev, PCI_D0);
7131 pci_restore_state(pdev);
7132 pci_save_state(pdev);
7133
7134 if (!pci_device_is_present(pdev))
7135 return -ENODEV;
7136 err = pci_enable_device_mem(pdev);
7137 if (err) {
7138 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
7139 return err;
7140 }
7141 pci_set_master(pdev);
7142
7143 pci_enable_wake(pdev, PCI_D3hot, 0);
7144 pci_enable_wake(pdev, PCI_D3cold, 0);
7145
7146 if (igc_init_interrupt_scheme(adapter, true)) {
7147 netdev_err(netdev, "Unable to allocate memory for queues\n");
7148 return -ENOMEM;
7149 }
7150
7151 igc_reset(adapter);
7152
7153 /* let the f/w know that the h/w is now under the control of the
7154 * driver.
7155 */
7156 igc_get_hw_control(adapter);
7157
7158 val = rd32(IGC_WUS);
7159 if (val & WAKE_PKT_WUS)
7160 igc_deliver_wake_packet(netdev);
7161
7162 wr32(IGC_WUS, ~0);
7163
7164 rtnl_lock();
7165 if (!err && netif_running(netdev))
7166 err = __igc_open(netdev, true);
7167
7168 if (!err)
7169 netif_device_attach(netdev);
7170 rtnl_unlock();
7171
7172 return err;
7173 }
7174
igc_runtime_resume(struct device * dev)7175 static int __maybe_unused igc_runtime_resume(struct device *dev)
7176 {
7177 return igc_resume(dev);
7178 }
7179
igc_suspend(struct device * dev)7180 static int __maybe_unused igc_suspend(struct device *dev)
7181 {
7182 return __igc_shutdown(to_pci_dev(dev), NULL, 0);
7183 }
7184
igc_runtime_idle(struct device * dev)7185 static int __maybe_unused igc_runtime_idle(struct device *dev)
7186 {
7187 struct net_device *netdev = dev_get_drvdata(dev);
7188 struct igc_adapter *adapter = netdev_priv(netdev);
7189
7190 if (!igc_has_link(adapter))
7191 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7192
7193 return -EBUSY;
7194 }
7195 #endif /* CONFIG_PM */
7196
igc_shutdown(struct pci_dev * pdev)7197 static void igc_shutdown(struct pci_dev *pdev)
7198 {
7199 bool wake;
7200
7201 __igc_shutdown(pdev, &wake, 0);
7202
7203 if (system_state == SYSTEM_POWER_OFF) {
7204 pci_wake_from_d3(pdev, wake);
7205 pci_set_power_state(pdev, PCI_D3hot);
7206 }
7207 }
7208
7209 /**
7210 * igc_io_error_detected - called when PCI error is detected
7211 * @pdev: Pointer to PCI device
7212 * @state: The current PCI connection state
7213 *
7214 * This function is called after a PCI bus error affecting
7215 * this device has been detected.
7216 **/
igc_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7217 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev,
7218 pci_channel_state_t state)
7219 {
7220 struct net_device *netdev = pci_get_drvdata(pdev);
7221 struct igc_adapter *adapter = netdev_priv(netdev);
7222
7223 netif_device_detach(netdev);
7224
7225 if (state == pci_channel_io_perm_failure)
7226 return PCI_ERS_RESULT_DISCONNECT;
7227
7228 if (netif_running(netdev))
7229 igc_down(adapter);
7230 pci_disable_device(pdev);
7231
7232 /* Request a slot reset. */
7233 return PCI_ERS_RESULT_NEED_RESET;
7234 }
7235
7236 /**
7237 * igc_io_slot_reset - called after the PCI bus has been reset.
7238 * @pdev: Pointer to PCI device
7239 *
7240 * Restart the card from scratch, as if from a cold-boot. Implementation
7241 * resembles the first-half of the igc_resume routine.
7242 **/
igc_io_slot_reset(struct pci_dev * pdev)7243 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev)
7244 {
7245 struct net_device *netdev = pci_get_drvdata(pdev);
7246 struct igc_adapter *adapter = netdev_priv(netdev);
7247 struct igc_hw *hw = &adapter->hw;
7248 pci_ers_result_t result;
7249
7250 if (pci_enable_device_mem(pdev)) {
7251 netdev_err(netdev, "Could not re-enable PCI device after reset\n");
7252 result = PCI_ERS_RESULT_DISCONNECT;
7253 } else {
7254 pci_set_master(pdev);
7255 pci_restore_state(pdev);
7256 pci_save_state(pdev);
7257
7258 pci_enable_wake(pdev, PCI_D3hot, 0);
7259 pci_enable_wake(pdev, PCI_D3cold, 0);
7260
7261 /* In case of PCI error, adapter loses its HW address
7262 * so we should re-assign it here.
7263 */
7264 hw->hw_addr = adapter->io_addr;
7265
7266 igc_reset(adapter);
7267 wr32(IGC_WUS, ~0);
7268 result = PCI_ERS_RESULT_RECOVERED;
7269 }
7270
7271 return result;
7272 }
7273
7274 /**
7275 * igc_io_resume - called when traffic can start to flow again.
7276 * @pdev: Pointer to PCI device
7277 *
7278 * This callback is called when the error recovery driver tells us that
7279 * its OK to resume normal operation. Implementation resembles the
7280 * second-half of the igc_resume routine.
7281 */
igc_io_resume(struct pci_dev * pdev)7282 static void igc_io_resume(struct pci_dev *pdev)
7283 {
7284 struct net_device *netdev = pci_get_drvdata(pdev);
7285 struct igc_adapter *adapter = netdev_priv(netdev);
7286
7287 rtnl_lock();
7288 if (netif_running(netdev)) {
7289 if (igc_open(netdev)) {
7290 rtnl_unlock();
7291 netdev_err(netdev, "igc_open failed after reset\n");
7292 return;
7293 }
7294 }
7295
7296 netif_device_attach(netdev);
7297
7298 /* let the f/w know that the h/w is now under the control of the
7299 * driver.
7300 */
7301 igc_get_hw_control(adapter);
7302 rtnl_unlock();
7303 }
7304
7305 static const struct pci_error_handlers igc_err_handler = {
7306 .error_detected = igc_io_error_detected,
7307 .slot_reset = igc_io_slot_reset,
7308 .resume = igc_io_resume,
7309 };
7310
7311 #ifdef CONFIG_PM
7312 static const struct dev_pm_ops igc_pm_ops = {
7313 SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume)
7314 SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume,
7315 igc_runtime_idle)
7316 };
7317 #endif
7318
7319 static struct pci_driver igc_driver = {
7320 .name = igc_driver_name,
7321 .id_table = igc_pci_tbl,
7322 .probe = igc_probe,
7323 .remove = igc_remove,
7324 #ifdef CONFIG_PM
7325 .driver.pm = &igc_pm_ops,
7326 #endif
7327 .shutdown = igc_shutdown,
7328 .err_handler = &igc_err_handler,
7329 };
7330
7331 /**
7332 * igc_reinit_queues - return error
7333 * @adapter: pointer to adapter structure
7334 */
igc_reinit_queues(struct igc_adapter * adapter)7335 int igc_reinit_queues(struct igc_adapter *adapter)
7336 {
7337 struct net_device *netdev = adapter->netdev;
7338 int err = 0;
7339
7340 if (netif_running(netdev))
7341 igc_close(netdev);
7342
7343 igc_reset_interrupt_capability(adapter);
7344
7345 if (igc_init_interrupt_scheme(adapter, true)) {
7346 netdev_err(netdev, "Unable to allocate memory for queues\n");
7347 return -ENOMEM;
7348 }
7349
7350 if (netif_running(netdev))
7351 err = igc_open(netdev);
7352
7353 return err;
7354 }
7355
7356 /**
7357 * igc_get_hw_dev - return device
7358 * @hw: pointer to hardware structure
7359 *
7360 * used by hardware layer to print debugging information
7361 */
igc_get_hw_dev(struct igc_hw * hw)7362 struct net_device *igc_get_hw_dev(struct igc_hw *hw)
7363 {
7364 struct igc_adapter *adapter = hw->back;
7365
7366 return adapter->netdev;
7367 }
7368
igc_disable_rx_ring_hw(struct igc_ring * ring)7369 static void igc_disable_rx_ring_hw(struct igc_ring *ring)
7370 {
7371 struct igc_hw *hw = &ring->q_vector->adapter->hw;
7372 u8 idx = ring->reg_idx;
7373 u32 rxdctl;
7374
7375 rxdctl = rd32(IGC_RXDCTL(idx));
7376 rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE;
7377 rxdctl |= IGC_RXDCTL_SWFLUSH;
7378 wr32(IGC_RXDCTL(idx), rxdctl);
7379 }
7380
igc_disable_rx_ring(struct igc_ring * ring)7381 void igc_disable_rx_ring(struct igc_ring *ring)
7382 {
7383 igc_disable_rx_ring_hw(ring);
7384 igc_clean_rx_ring(ring);
7385 }
7386
igc_enable_rx_ring(struct igc_ring * ring)7387 void igc_enable_rx_ring(struct igc_ring *ring)
7388 {
7389 struct igc_adapter *adapter = ring->q_vector->adapter;
7390
7391 igc_configure_rx_ring(adapter, ring);
7392
7393 if (ring->xsk_pool)
7394 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring));
7395 else
7396 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
7397 }
7398
igc_disable_tx_ring(struct igc_ring * ring)7399 void igc_disable_tx_ring(struct igc_ring *ring)
7400 {
7401 igc_disable_tx_ring_hw(ring);
7402 igc_clean_tx_ring(ring);
7403 }
7404
igc_enable_tx_ring(struct igc_ring * ring)7405 void igc_enable_tx_ring(struct igc_ring *ring)
7406 {
7407 struct igc_adapter *adapter = ring->q_vector->adapter;
7408
7409 igc_configure_tx_ring(adapter, ring);
7410 }
7411
7412 /**
7413 * igc_init_module - Driver Registration Routine
7414 *
7415 * igc_init_module is the first routine called when the driver is
7416 * loaded. All it does is register with the PCI subsystem.
7417 */
igc_init_module(void)7418 static int __init igc_init_module(void)
7419 {
7420 int ret;
7421
7422 pr_info("%s\n", igc_driver_string);
7423 pr_info("%s\n", igc_copyright);
7424
7425 ret = pci_register_driver(&igc_driver);
7426 return ret;
7427 }
7428
7429 module_init(igc_init_module);
7430
7431 /**
7432 * igc_exit_module - Driver Exit Cleanup Routine
7433 *
7434 * igc_exit_module is called just before the driver is removed
7435 * from memory.
7436 */
igc_exit_module(void)7437 static void __exit igc_exit_module(void)
7438 {
7439 pci_unregister_driver(&igc_driver);
7440 }
7441
7442 module_exit(igc_exit_module);
7443 /* igc_main.c */
7444