1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/prefetch.h>
32 #include <linux/bpf.h>
33 #include <linux/bpf_trace.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/etherdevice.h>
36 #ifdef CONFIG_IGB_DCA
37 #include <linux/dca.h>
38 #endif
39 #include <linux/i2c.h>
40 #include "igb.h"
41
42 enum queue_mode {
43 QUEUE_MODE_STRICT_PRIORITY,
44 QUEUE_MODE_STREAM_RESERVATION,
45 };
46
47 enum tx_queue_prio {
48 TX_QUEUE_PRIO_HIGH,
49 TX_QUEUE_PRIO_LOW,
50 };
51
52 char igb_driver_name[] = "igb";
53 static const char igb_driver_string[] =
54 "Intel(R) Gigabit Ethernet Network Driver";
55 static const char igb_copyright[] =
56 "Copyright (c) 2007-2014 Intel Corporation.";
57
58 static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60 };
61
62 static const struct pci_device_id igb_pci_tbl[] = {
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
98 /* required last entry */
99 {0, }
100 };
101
102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
103
104 static int igb_setup_all_tx_resources(struct igb_adapter *);
105 static int igb_setup_all_rx_resources(struct igb_adapter *);
106 static void igb_free_all_tx_resources(struct igb_adapter *);
107 static void igb_free_all_rx_resources(struct igb_adapter *);
108 static void igb_setup_mrqc(struct igb_adapter *);
109 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
110 static void igb_remove(struct pci_dev *pdev);
111 static void igb_init_queue_configuration(struct igb_adapter *adapter);
112 static int igb_sw_init(struct igb_adapter *);
113 int igb_open(struct net_device *);
114 int igb_close(struct net_device *);
115 static void igb_configure(struct igb_adapter *);
116 static void igb_configure_tx(struct igb_adapter *);
117 static void igb_configure_rx(struct igb_adapter *);
118 static void igb_clean_all_tx_rings(struct igb_adapter *);
119 static void igb_clean_all_rx_rings(struct igb_adapter *);
120 static void igb_clean_tx_ring(struct igb_ring *);
121 static void igb_clean_rx_ring(struct igb_ring *);
122 static void igb_set_rx_mode(struct net_device *);
123 static void igb_update_phy_info(struct timer_list *);
124 static void igb_watchdog(struct timer_list *);
125 static void igb_watchdog_task(struct work_struct *);
126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127 static void igb_get_stats64(struct net_device *dev,
128 struct rtnl_link_stats64 *stats);
129 static int igb_change_mtu(struct net_device *, int);
130 static int igb_set_mac(struct net_device *, void *);
131 static void igb_set_uta(struct igb_adapter *adapter, bool set);
132 static irqreturn_t igb_intr(int irq, void *);
133 static irqreturn_t igb_intr_msi(int irq, void *);
134 static irqreturn_t igb_msix_other(int irq, void *);
135 static irqreturn_t igb_msix_ring(int irq, void *);
136 #ifdef CONFIG_IGB_DCA
137 static void igb_update_dca(struct igb_q_vector *);
138 static void igb_setup_dca(struct igb_adapter *);
139 #endif /* CONFIG_IGB_DCA */
140 static int igb_poll(struct napi_struct *, int);
141 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142 static int igb_clean_rx_irq(struct igb_q_vector *, int);
143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145 static void igb_reset_task(struct work_struct *);
146 static void igb_vlan_mode(struct net_device *netdev,
147 netdev_features_t features);
148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150 static void igb_restore_vlan(struct igb_adapter *);
151 static void igb_rar_set_index(struct igb_adapter *, u32);
152 static void igb_ping_all_vfs(struct igb_adapter *);
153 static void igb_msg_task(struct igb_adapter *);
154 static void igb_vmm_control(struct igb_adapter *);
155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156 static void igb_flush_mac_table(struct igb_adapter *);
157 static int igb_available_rars(struct igb_adapter *, u8);
158 static void igb_set_default_mac_filter(struct igb_adapter *);
159 static int igb_uc_sync(struct net_device *, const unsigned char *);
160 static int igb_uc_unsync(struct net_device *, const unsigned char *);
161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 bool setting);
168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 bool setting);
170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
172 static void igb_check_vf_rate_limit(struct igb_adapter *);
173 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static int igb_disable_sriov(struct pci_dev *dev, bool reinit);
179 #endif
180
181 static int igb_suspend(struct device *);
182 static int igb_resume(struct device *);
183 static int igb_runtime_suspend(struct device *dev);
184 static int igb_runtime_resume(struct device *dev);
185 static int igb_runtime_idle(struct device *dev);
186 #ifdef CONFIG_PM
187 static const struct dev_pm_ops igb_pm_ops = {
188 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
189 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
190 igb_runtime_idle)
191 };
192 #endif
193 static void igb_shutdown(struct pci_dev *);
194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201 };
202 #endif
203 #ifdef CONFIG_PCI_IOV
204 static unsigned int max_vfs;
205 module_param(max_vfs, uint, 0);
206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207 #endif /* CONFIG_PCI_IOV */
208
209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 pci_channel_state_t);
211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212 static void igb_io_resume(struct pci_dev *);
213
214 static const struct pci_error_handlers igb_err_handler = {
215 .error_detected = igb_io_error_detected,
216 .slot_reset = igb_io_slot_reset,
217 .resume = igb_io_resume,
218 };
219
220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221
222 static struct pci_driver igb_driver = {
223 .name = igb_driver_name,
224 .id_table = igb_pci_tbl,
225 .probe = igb_probe,
226 .remove = igb_remove,
227 #ifdef CONFIG_PM
228 .driver.pm = &igb_pm_ops,
229 #endif
230 .shutdown = igb_shutdown,
231 .sriov_configure = igb_pci_sriov_configure,
232 .err_handler = &igb_err_handler
233 };
234
235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237 MODULE_LICENSE("GPL v2");
238
239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240 static int debug = -1;
241 module_param(debug, int, 0);
242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243
244 struct igb_reg_info {
245 u32 ofs;
246 char *name;
247 };
248
249 static const struct igb_reg_info igb_reg_info_tbl[] = {
250
251 /* General Registers */
252 {E1000_CTRL, "CTRL"},
253 {E1000_STATUS, "STATUS"},
254 {E1000_CTRL_EXT, "CTRL_EXT"},
255
256 /* Interrupt Registers */
257 {E1000_ICR, "ICR"},
258
259 /* RX Registers */
260 {E1000_RCTL, "RCTL"},
261 {E1000_RDLEN(0), "RDLEN"},
262 {E1000_RDH(0), "RDH"},
263 {E1000_RDT(0), "RDT"},
264 {E1000_RXDCTL(0), "RXDCTL"},
265 {E1000_RDBAL(0), "RDBAL"},
266 {E1000_RDBAH(0), "RDBAH"},
267
268 /* TX Registers */
269 {E1000_TCTL, "TCTL"},
270 {E1000_TDBAL(0), "TDBAL"},
271 {E1000_TDBAH(0), "TDBAH"},
272 {E1000_TDLEN(0), "TDLEN"},
273 {E1000_TDH(0), "TDH"},
274 {E1000_TDT(0), "TDT"},
275 {E1000_TXDCTL(0), "TXDCTL"},
276 {E1000_TDFH, "TDFH"},
277 {E1000_TDFT, "TDFT"},
278 {E1000_TDFHS, "TDFHS"},
279 {E1000_TDFPC, "TDFPC"},
280
281 /* List Terminator */
282 {}
283 };
284
285 /* igb_regdump - register printout routine */
igb_regdump(struct e1000_hw * hw,struct igb_reg_info * reginfo)286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287 {
288 int n = 0;
289 char rname[16];
290 u32 regs[8];
291
292 switch (reginfo->ofs) {
293 case E1000_RDLEN(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDLEN(n));
296 break;
297 case E1000_RDH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDH(n));
300 break;
301 case E1000_RDT(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDT(n));
304 break;
305 case E1000_RXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RXDCTL(n));
308 break;
309 case E1000_RDBAL(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDBAL(n));
312 break;
313 case E1000_RDBAH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDBAH(n));
316 break;
317 case E1000_TDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDBAL(n));
320 break;
321 case E1000_TDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDBAH(n));
324 break;
325 case E1000_TDLEN(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TDLEN(n));
328 break;
329 case E1000_TDH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDH(n));
332 break;
333 case E1000_TDT(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDT(n));
336 break;
337 case E1000_TXDCTL(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TXDCTL(n));
340 break;
341 default:
342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 return;
344 }
345
346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 regs[2], regs[3]);
349 }
350
351 /* igb_dump - Print registers, Tx-rings and Rx-rings */
igb_dump(struct igb_adapter * adapter)352 static void igb_dump(struct igb_adapter *adapter)
353 {
354 struct net_device *netdev = adapter->netdev;
355 struct e1000_hw *hw = &adapter->hw;
356 struct igb_reg_info *reginfo;
357 struct igb_ring *tx_ring;
358 union e1000_adv_tx_desc *tx_desc;
359 struct my_u0 { __le64 a; __le64 b; } *u0;
360 struct igb_ring *rx_ring;
361 union e1000_adv_rx_desc *rx_desc;
362 u32 staterr;
363 u16 i, n;
364
365 if (!netif_msg_hw(adapter))
366 return;
367
368 /* Print netdevice Info */
369 if (netdev) {
370 dev_info(&adapter->pdev->dev, "Net device Info\n");
371 pr_info("Device Name state trans_start\n");
372 pr_info("%-15s %016lX %016lX\n", netdev->name,
373 netdev->state, dev_trans_start(netdev));
374 }
375
376 /* Print Registers */
377 dev_info(&adapter->pdev->dev, "Register Dump\n");
378 pr_info(" Register Name Value\n");
379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 reginfo->name; reginfo++) {
381 igb_regdump(hw, reginfo);
382 }
383
384 /* Print TX Ring Summary */
385 if (!netdev || !netif_running(netdev))
386 goto exit;
387
388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 struct igb_tx_buffer *buffer_info;
392 tx_ring = adapter->tx_ring[n];
393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 (u64)dma_unmap_addr(buffer_info, dma),
397 dma_unmap_len(buffer_info, len),
398 buffer_info->next_to_watch,
399 (u64)buffer_info->time_stamp);
400 }
401
402 /* Print TX Rings */
403 if (!netif_msg_tx_done(adapter))
404 goto rx_ring_summary;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407
408 /* Transmit Descriptor Formats
409 *
410 * Advanced Transmit Descriptor
411 * +--------------------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +--------------------------------------------------------------+
414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
415 * +--------------------------------------------------------------+
416 * 63 46 45 40 39 38 36 35 32 31 24 15 0
417 */
418
419 for (n = 0; n < adapter->num_tx_queues; n++) {
420 tx_ring = adapter->tx_ring[n];
421 pr_info("------------------------------------\n");
422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 pr_info("------------------------------------\n");
424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
425
426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 const char *next_desc;
428 struct igb_tx_buffer *buffer_info;
429 tx_desc = IGB_TX_DESC(tx_ring, i);
430 buffer_info = &tx_ring->tx_buffer_info[i];
431 u0 = (struct my_u0 *)tx_desc;
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 next_desc = " NTC/U";
435 else if (i == tx_ring->next_to_use)
436 next_desc = " NTU";
437 else if (i == tx_ring->next_to_clean)
438 next_desc = " NTC";
439 else
440 next_desc = "";
441
442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
443 i, le64_to_cpu(u0->a),
444 le64_to_cpu(u0->b),
445 (u64)dma_unmap_addr(buffer_info, dma),
446 dma_unmap_len(buffer_info, len),
447 buffer_info->next_to_watch,
448 (u64)buffer_info->time_stamp,
449 buffer_info->skb, next_desc);
450
451 if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 print_hex_dump(KERN_INFO, "",
453 DUMP_PREFIX_ADDRESS,
454 16, 1, buffer_info->skb->data,
455 dma_unmap_len(buffer_info, len),
456 true);
457 }
458 }
459
460 /* Print RX Rings Summary */
461 rx_ring_summary:
462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 pr_info("Queue [NTU] [NTC]\n");
464 for (n = 0; n < adapter->num_rx_queues; n++) {
465 rx_ring = adapter->rx_ring[n];
466 pr_info(" %5d %5X %5X\n",
467 n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 }
469
470 /* Print RX Rings */
471 if (!netif_msg_rx_status(adapter))
472 goto exit;
473
474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475
476 /* Advanced Receive Descriptor (Read) Format
477 * 63 1 0
478 * +-----------------------------------------------------+
479 * 0 | Packet Buffer Address [63:1] |A0/NSE|
480 * +----------------------------------------------+------+
481 * 8 | Header Buffer Address [63:1] | DD |
482 * +-----------------------------------------------------+
483 *
484 *
485 * Advanced Receive Descriptor (Write-Back) Format
486 *
487 * 63 48 47 32 31 30 21 20 17 16 4 3 0
488 * +------------------------------------------------------+
489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
490 * | Checksum Ident | | | | Type | Type |
491 * +------------------------------------------------------+
492 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 * +------------------------------------------------------+
494 * 63 48 47 32 31 20 19 0
495 */
496
497 for (n = 0; n < adapter->num_rx_queues; n++) {
498 rx_ring = adapter->rx_ring[n];
499 pr_info("------------------------------------\n");
500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 pr_info("------------------------------------\n");
502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504
505 for (i = 0; i < rx_ring->count; i++) {
506 const char *next_desc;
507 struct igb_rx_buffer *buffer_info;
508 buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IGB_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512
513 if (i == rx_ring->next_to_use)
514 next_desc = " NTU";
515 else if (i == rx_ring->next_to_clean)
516 next_desc = " NTC";
517 else
518 next_desc = "";
519
520 if (staterr & E1000_RXD_STAT_DD) {
521 /* Descriptor Done */
522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
523 "RWB", i,
524 le64_to_cpu(u0->a),
525 le64_to_cpu(u0->b),
526 next_desc);
527 } else {
528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
529 "R ", i,
530 le64_to_cpu(u0->a),
531 le64_to_cpu(u0->b),
532 (u64)buffer_info->dma,
533 next_desc);
534
535 if (netif_msg_pktdata(adapter) &&
536 buffer_info->dma && buffer_info->page) {
537 print_hex_dump(KERN_INFO, "",
538 DUMP_PREFIX_ADDRESS,
539 16, 1,
540 page_address(buffer_info->page) +
541 buffer_info->page_offset,
542 igb_rx_bufsz(rx_ring), true);
543 }
544 }
545 }
546 }
547
548 exit:
549 return;
550 }
551
552 /**
553 * igb_get_i2c_data - Reads the I2C SDA data bit
554 * @data: opaque pointer to adapter struct
555 *
556 * Returns the I2C data bit value
557 **/
igb_get_i2c_data(void * data)558 static int igb_get_i2c_data(void *data)
559 {
560 struct igb_adapter *adapter = (struct igb_adapter *)data;
561 struct e1000_hw *hw = &adapter->hw;
562 s32 i2cctl = rd32(E1000_I2CPARAMS);
563
564 return !!(i2cctl & E1000_I2C_DATA_IN);
565 }
566
567 /**
568 * igb_set_i2c_data - Sets the I2C data bit
569 * @data: pointer to hardware structure
570 * @state: I2C data value (0 or 1) to set
571 *
572 * Sets the I2C data bit
573 **/
igb_set_i2c_data(void * data,int state)574 static void igb_set_i2c_data(void *data, int state)
575 {
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
579
580 if (state) {
581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
582 } else {
583 i2cctl &= ~E1000_I2C_DATA_OE_N;
584 i2cctl &= ~E1000_I2C_DATA_OUT;
585 }
586
587 wr32(E1000_I2CPARAMS, i2cctl);
588 wrfl();
589 }
590
591 /**
592 * igb_set_i2c_clk - Sets the I2C SCL clock
593 * @data: pointer to hardware structure
594 * @state: state to set clock
595 *
596 * Sets the I2C clock line to state
597 **/
igb_set_i2c_clk(void * data,int state)598 static void igb_set_i2c_clk(void *data, int state)
599 {
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state) {
605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N;
606 } else {
607 i2cctl &= ~E1000_I2C_CLK_OUT;
608 i2cctl &= ~E1000_I2C_CLK_OE_N;
609 }
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612 }
613
614 /**
615 * igb_get_i2c_clk - Gets the I2C SCL clock state
616 * @data: pointer to hardware structure
617 *
618 * Gets the I2C clock state
619 **/
igb_get_i2c_clk(void * data)620 static int igb_get_i2c_clk(void *data)
621 {
622 struct igb_adapter *adapter = (struct igb_adapter *)data;
623 struct e1000_hw *hw = &adapter->hw;
624 s32 i2cctl = rd32(E1000_I2CPARAMS);
625
626 return !!(i2cctl & E1000_I2C_CLK_IN);
627 }
628
629 static const struct i2c_algo_bit_data igb_i2c_algo = {
630 .setsda = igb_set_i2c_data,
631 .setscl = igb_set_i2c_clk,
632 .getsda = igb_get_i2c_data,
633 .getscl = igb_get_i2c_clk,
634 .udelay = 5,
635 .timeout = 20,
636 };
637
638 /**
639 * igb_get_hw_dev - return device
640 * @hw: pointer to hardware structure
641 *
642 * used by hardware layer to print debugging information
643 **/
igb_get_hw_dev(struct e1000_hw * hw)644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
645 {
646 struct igb_adapter *adapter = hw->back;
647 return adapter->netdev;
648 }
649
650 /**
651 * igb_init_module - Driver Registration Routine
652 *
653 * igb_init_module is the first routine called when the driver is
654 * loaded. All it does is register with the PCI subsystem.
655 **/
igb_init_module(void)656 static int __init igb_init_module(void)
657 {
658 int ret;
659
660 pr_info("%s\n", igb_driver_string);
661 pr_info("%s\n", igb_copyright);
662
663 #ifdef CONFIG_IGB_DCA
664 dca_register_notify(&dca_notifier);
665 #endif
666 ret = pci_register_driver(&igb_driver);
667 return ret;
668 }
669
670 module_init(igb_init_module);
671
672 /**
673 * igb_exit_module - Driver Exit Cleanup Routine
674 *
675 * igb_exit_module is called just before the driver is removed
676 * from memory.
677 **/
igb_exit_module(void)678 static void __exit igb_exit_module(void)
679 {
680 #ifdef CONFIG_IGB_DCA
681 dca_unregister_notify(&dca_notifier);
682 #endif
683 pci_unregister_driver(&igb_driver);
684 }
685
686 module_exit(igb_exit_module);
687
688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
689 /**
690 * igb_cache_ring_register - Descriptor ring to register mapping
691 * @adapter: board private structure to initialize
692 *
693 * Once we know the feature-set enabled for the device, we'll cache
694 * the register offset the descriptor ring is assigned to.
695 **/
igb_cache_ring_register(struct igb_adapter * adapter)696 static void igb_cache_ring_register(struct igb_adapter *adapter)
697 {
698 int i = 0, j = 0;
699 u32 rbase_offset = adapter->vfs_allocated_count;
700
701 switch (adapter->hw.mac.type) {
702 case e1000_82576:
703 /* The queues are allocated for virtualization such that VF 0
704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
705 * In order to avoid collision we start at the first free queue
706 * and continue consuming queues in the same sequence
707 */
708 if (adapter->vfs_allocated_count) {
709 for (; i < adapter->rss_queues; i++)
710 adapter->rx_ring[i]->reg_idx = rbase_offset +
711 Q_IDX_82576(i);
712 }
713 fallthrough;
714 case e1000_82575:
715 case e1000_82580:
716 case e1000_i350:
717 case e1000_i354:
718 case e1000_i210:
719 case e1000_i211:
720 default:
721 for (; i < adapter->num_rx_queues; i++)
722 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
723 for (; j < adapter->num_tx_queues; j++)
724 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
725 break;
726 }
727 }
728
igb_rd32(struct e1000_hw * hw,u32 reg)729 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
730 {
731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
733 u32 value = 0;
734
735 if (E1000_REMOVED(hw_addr))
736 return ~value;
737
738 value = readl(&hw_addr[reg]);
739
740 /* reads should not return all F's */
741 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
742 struct net_device *netdev = igb->netdev;
743 hw->hw_addr = NULL;
744 netdev_err(netdev, "PCIe link lost\n");
745 WARN(pci_device_is_present(igb->pdev),
746 "igb: Failed to read reg 0x%x!\n", reg);
747 }
748
749 return value;
750 }
751
752 /**
753 * igb_write_ivar - configure ivar for given MSI-X vector
754 * @hw: pointer to the HW structure
755 * @msix_vector: vector number we are allocating to a given ring
756 * @index: row index of IVAR register to write within IVAR table
757 * @offset: column offset of in IVAR, should be multiple of 8
758 *
759 * This function is intended to handle the writing of the IVAR register
760 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
761 * each containing an cause allocation for an Rx and Tx ring, and a
762 * variable number of rows depending on the number of queues supported.
763 **/
igb_write_ivar(struct e1000_hw * hw,int msix_vector,int index,int offset)764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 int index, int offset)
766 {
767 u32 ivar = array_rd32(E1000_IVAR0, index);
768
769 /* clear any bits that are currently set */
770 ivar &= ~((u32)0xFF << offset);
771
772 /* write vector and valid bit */
773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774
775 array_wr32(E1000_IVAR0, index, ivar);
776 }
777
778 #define IGB_N0_QUEUE -1
igb_assign_vector(struct igb_q_vector * q_vector,int msix_vector)779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
780 {
781 struct igb_adapter *adapter = q_vector->adapter;
782 struct e1000_hw *hw = &adapter->hw;
783 int rx_queue = IGB_N0_QUEUE;
784 int tx_queue = IGB_N0_QUEUE;
785 u32 msixbm = 0;
786
787 if (q_vector->rx.ring)
788 rx_queue = q_vector->rx.ring->reg_idx;
789 if (q_vector->tx.ring)
790 tx_queue = q_vector->tx.ring->reg_idx;
791
792 switch (hw->mac.type) {
793 case e1000_82575:
794 /* The 82575 assigns vectors using a bitmask, which matches the
795 * bitmask for the EICR/EIMS/EIMC registers. To assign one
796 * or more queues to a vector, we write the appropriate bits
797 * into the MSIXBM register for that vector.
798 */
799 if (rx_queue > IGB_N0_QUEUE)
800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
801 if (tx_queue > IGB_N0_QUEUE)
802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
804 msixbm |= E1000_EIMS_OTHER;
805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
806 q_vector->eims_value = msixbm;
807 break;
808 case e1000_82576:
809 /* 82576 uses a table that essentially consists of 2 columns
810 * with 8 rows. The ordering is column-major so we use the
811 * lower 3 bits as the row index, and the 4th bit as the
812 * column offset.
813 */
814 if (rx_queue > IGB_N0_QUEUE)
815 igb_write_ivar(hw, msix_vector,
816 rx_queue & 0x7,
817 (rx_queue & 0x8) << 1);
818 if (tx_queue > IGB_N0_QUEUE)
819 igb_write_ivar(hw, msix_vector,
820 tx_queue & 0x7,
821 ((tx_queue & 0x8) << 1) + 8);
822 q_vector->eims_value = BIT(msix_vector);
823 break;
824 case e1000_82580:
825 case e1000_i350:
826 case e1000_i354:
827 case e1000_i210:
828 case e1000_i211:
829 /* On 82580 and newer adapters the scheme is similar to 82576
830 * however instead of ordering column-major we have things
831 * ordered row-major. So we traverse the table by using
832 * bit 0 as the column offset, and the remaining bits as the
833 * row index.
834 */
835 if (rx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 rx_queue >> 1,
838 (rx_queue & 0x1) << 4);
839 if (tx_queue > IGB_N0_QUEUE)
840 igb_write_ivar(hw, msix_vector,
841 tx_queue >> 1,
842 ((tx_queue & 0x1) << 4) + 8);
843 q_vector->eims_value = BIT(msix_vector);
844 break;
845 default:
846 BUG();
847 break;
848 }
849
850 /* add q_vector eims value to global eims_enable_mask */
851 adapter->eims_enable_mask |= q_vector->eims_value;
852
853 /* configure q_vector to set itr on first interrupt */
854 q_vector->set_itr = 1;
855 }
856
857 /**
858 * igb_configure_msix - Configure MSI-X hardware
859 * @adapter: board private structure to initialize
860 *
861 * igb_configure_msix sets up the hardware to properly
862 * generate MSI-X interrupts.
863 **/
igb_configure_msix(struct igb_adapter * adapter)864 static void igb_configure_msix(struct igb_adapter *adapter)
865 {
866 u32 tmp;
867 int i, vector = 0;
868 struct e1000_hw *hw = &adapter->hw;
869
870 adapter->eims_enable_mask = 0;
871
872 /* set vector for other causes, i.e. link changes */
873 switch (hw->mac.type) {
874 case e1000_82575:
875 tmp = rd32(E1000_CTRL_EXT);
876 /* enable MSI-X PBA support*/
877 tmp |= E1000_CTRL_EXT_PBA_CLR;
878
879 /* Auto-Mask interrupts upon ICR read. */
880 tmp |= E1000_CTRL_EXT_EIAME;
881 tmp |= E1000_CTRL_EXT_IRCA;
882
883 wr32(E1000_CTRL_EXT, tmp);
884
885 /* enable msix_other interrupt */
886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
887 adapter->eims_other = E1000_EIMS_OTHER;
888
889 break;
890
891 case e1000_82576:
892 case e1000_82580:
893 case e1000_i350:
894 case e1000_i354:
895 case e1000_i210:
896 case e1000_i211:
897 /* Turn on MSI-X capability first, or our settings
898 * won't stick. And it will take days to debug.
899 */
900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
901 E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 E1000_GPIE_NSICR);
903
904 /* enable msix_other interrupt */
905 adapter->eims_other = BIT(vector);
906 tmp = (vector++ | E1000_IVAR_VALID) << 8;
907
908 wr32(E1000_IVAR_MISC, tmp);
909 break;
910 default:
911 /* do nothing, since nothing else supports MSI-X */
912 break;
913 } /* switch (hw->mac.type) */
914
915 adapter->eims_enable_mask |= adapter->eims_other;
916
917 for (i = 0; i < adapter->num_q_vectors; i++)
918 igb_assign_vector(adapter->q_vector[i], vector++);
919
920 wrfl();
921 }
922
923 /**
924 * igb_request_msix - Initialize MSI-X interrupts
925 * @adapter: board private structure to initialize
926 *
927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
928 * kernel.
929 **/
igb_request_msix(struct igb_adapter * adapter)930 static int igb_request_msix(struct igb_adapter *adapter)
931 {
932 unsigned int num_q_vectors = adapter->num_q_vectors;
933 struct net_device *netdev = adapter->netdev;
934 int i, err = 0, vector = 0, free_vector = 0;
935
936 err = request_irq(adapter->msix_entries[vector].vector,
937 igb_msix_other, 0, netdev->name, adapter);
938 if (err)
939 goto err_out;
940
941 if (num_q_vectors > MAX_Q_VECTORS) {
942 num_q_vectors = MAX_Q_VECTORS;
943 dev_warn(&adapter->pdev->dev,
944 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
945 adapter->num_q_vectors, MAX_Q_VECTORS);
946 }
947 for (i = 0; i < num_q_vectors; i++) {
948 struct igb_q_vector *q_vector = adapter->q_vector[i];
949
950 vector++;
951
952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
953
954 if (q_vector->rx.ring && q_vector->tx.ring)
955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
956 q_vector->rx.ring->queue_index);
957 else if (q_vector->tx.ring)
958 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
959 q_vector->tx.ring->queue_index);
960 else if (q_vector->rx.ring)
961 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
962 q_vector->rx.ring->queue_index);
963 else
964 sprintf(q_vector->name, "%s-unused", netdev->name);
965
966 err = request_irq(adapter->msix_entries[vector].vector,
967 igb_msix_ring, 0, q_vector->name,
968 q_vector);
969 if (err)
970 goto err_free;
971 }
972
973 igb_configure_msix(adapter);
974 return 0;
975
976 err_free:
977 /* free already assigned IRQs */
978 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
979
980 vector--;
981 for (i = 0; i < vector; i++) {
982 free_irq(adapter->msix_entries[free_vector++].vector,
983 adapter->q_vector[i]);
984 }
985 err_out:
986 return err;
987 }
988
989 /**
990 * igb_free_q_vector - Free memory allocated for specific interrupt vector
991 * @adapter: board private structure to initialize
992 * @v_idx: Index of vector to be freed
993 *
994 * This function frees the memory allocated to the q_vector.
995 **/
igb_free_q_vector(struct igb_adapter * adapter,int v_idx)996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
997 {
998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
999
1000 adapter->q_vector[v_idx] = NULL;
1001
1002 /* igb_get_stats64() might access the rings on this vector,
1003 * we must wait a grace period before freeing it.
1004 */
1005 if (q_vector)
1006 kfree_rcu(q_vector, rcu);
1007 }
1008
1009 /**
1010 * igb_reset_q_vector - Reset config for interrupt vector
1011 * @adapter: board private structure to initialize
1012 * @v_idx: Index of vector to be reset
1013 *
1014 * If NAPI is enabled it will delete any references to the
1015 * NAPI struct. This is preparation for igb_free_q_vector.
1016 **/
igb_reset_q_vector(struct igb_adapter * adapter,int v_idx)1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1018 {
1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1020
1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1022 * allocated. So, q_vector is NULL so we should stop here.
1023 */
1024 if (!q_vector)
1025 return;
1026
1027 if (q_vector->tx.ring)
1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1029
1030 if (q_vector->rx.ring)
1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1032
1033 netif_napi_del(&q_vector->napi);
1034
1035 }
1036
igb_reset_interrupt_capability(struct igb_adapter * adapter)1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1038 {
1039 int v_idx = adapter->num_q_vectors;
1040
1041 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1042 pci_disable_msix(adapter->pdev);
1043 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1044 pci_disable_msi(adapter->pdev);
1045
1046 while (v_idx--)
1047 igb_reset_q_vector(adapter, v_idx);
1048 }
1049
1050 /**
1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1052 * @adapter: board private structure to initialize
1053 *
1054 * This function frees the memory allocated to the q_vectors. In addition if
1055 * NAPI is enabled it will delete any references to the NAPI struct prior
1056 * to freeing the q_vector.
1057 **/
igb_free_q_vectors(struct igb_adapter * adapter)1058 static void igb_free_q_vectors(struct igb_adapter *adapter)
1059 {
1060 int v_idx = adapter->num_q_vectors;
1061
1062 adapter->num_tx_queues = 0;
1063 adapter->num_rx_queues = 0;
1064 adapter->num_q_vectors = 0;
1065
1066 while (v_idx--) {
1067 igb_reset_q_vector(adapter, v_idx);
1068 igb_free_q_vector(adapter, v_idx);
1069 }
1070 }
1071
1072 /**
1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1074 * @adapter: board private structure to initialize
1075 *
1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1077 * MSI-X interrupts allocated.
1078 */
igb_clear_interrupt_scheme(struct igb_adapter * adapter)1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1080 {
1081 igb_free_q_vectors(adapter);
1082 igb_reset_interrupt_capability(adapter);
1083 }
1084
1085 /**
1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1087 * @adapter: board private structure to initialize
1088 * @msix: boolean value of MSIX capability
1089 *
1090 * Attempt to configure interrupts using the best available
1091 * capabilities of the hardware and kernel.
1092 **/
igb_set_interrupt_capability(struct igb_adapter * adapter,bool msix)1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1094 {
1095 int err;
1096 int numvecs, i;
1097
1098 if (!msix)
1099 goto msi_only;
1100 adapter->flags |= IGB_FLAG_HAS_MSIX;
1101
1102 /* Number of supported queues. */
1103 adapter->num_rx_queues = adapter->rss_queues;
1104 if (adapter->vfs_allocated_count)
1105 adapter->num_tx_queues = 1;
1106 else
1107 adapter->num_tx_queues = adapter->rss_queues;
1108
1109 /* start with one vector for every Rx queue */
1110 numvecs = adapter->num_rx_queues;
1111
1112 /* if Tx handler is separate add 1 for every Tx queue */
1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1114 numvecs += adapter->num_tx_queues;
1115
1116 /* store the number of vectors reserved for queues */
1117 adapter->num_q_vectors = numvecs;
1118
1119 /* add 1 vector for link status interrupts */
1120 numvecs++;
1121 for (i = 0; i < numvecs; i++)
1122 adapter->msix_entries[i].entry = i;
1123
1124 err = pci_enable_msix_range(adapter->pdev,
1125 adapter->msix_entries,
1126 numvecs,
1127 numvecs);
1128 if (err > 0)
1129 return;
1130
1131 igb_reset_interrupt_capability(adapter);
1132
1133 /* If we can't do MSI-X, try MSI */
1134 msi_only:
1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1136 #ifdef CONFIG_PCI_IOV
1137 /* disable SR-IOV for non MSI-X configurations */
1138 if (adapter->vf_data) {
1139 struct e1000_hw *hw = &adapter->hw;
1140 /* disable iov and allow time for transactions to clear */
1141 pci_disable_sriov(adapter->pdev);
1142 msleep(500);
1143
1144 kfree(adapter->vf_mac_list);
1145 adapter->vf_mac_list = NULL;
1146 kfree(adapter->vf_data);
1147 adapter->vf_data = NULL;
1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1149 wrfl();
1150 msleep(100);
1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1152 }
1153 #endif
1154 adapter->vfs_allocated_count = 0;
1155 adapter->rss_queues = 1;
1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1157 adapter->num_rx_queues = 1;
1158 adapter->num_tx_queues = 1;
1159 adapter->num_q_vectors = 1;
1160 if (!pci_enable_msi(adapter->pdev))
1161 adapter->flags |= IGB_FLAG_HAS_MSI;
1162 }
1163
igb_add_ring(struct igb_ring * ring,struct igb_ring_container * head)1164 static void igb_add_ring(struct igb_ring *ring,
1165 struct igb_ring_container *head)
1166 {
1167 head->ring = ring;
1168 head->count++;
1169 }
1170
1171 /**
1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1173 * @adapter: board private structure to initialize
1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1175 * @v_idx: index of vector in adapter struct
1176 * @txr_count: total number of Tx rings to allocate
1177 * @txr_idx: index of first Tx ring to allocate
1178 * @rxr_count: total number of Rx rings to allocate
1179 * @rxr_idx: index of first Rx ring to allocate
1180 *
1181 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1182 **/
igb_alloc_q_vector(struct igb_adapter * adapter,int v_count,int v_idx,int txr_count,int txr_idx,int rxr_count,int rxr_idx)1183 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1184 int v_count, int v_idx,
1185 int txr_count, int txr_idx,
1186 int rxr_count, int rxr_idx)
1187 {
1188 struct igb_q_vector *q_vector;
1189 struct igb_ring *ring;
1190 int ring_count;
1191 size_t size;
1192
1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1194 if (txr_count > 1 || rxr_count > 1)
1195 return -ENOMEM;
1196
1197 ring_count = txr_count + rxr_count;
1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count));
1199
1200 /* allocate q_vector and rings */
1201 q_vector = adapter->q_vector[v_idx];
1202 if (!q_vector) {
1203 q_vector = kzalloc(size, GFP_KERNEL);
1204 } else if (size > ksize(q_vector)) {
1205 struct igb_q_vector *new_q_vector;
1206
1207 new_q_vector = kzalloc(size, GFP_KERNEL);
1208 if (new_q_vector)
1209 kfree_rcu(q_vector, rcu);
1210 q_vector = new_q_vector;
1211 } else {
1212 memset(q_vector, 0, size);
1213 }
1214 if (!q_vector)
1215 return -ENOMEM;
1216
1217 /* initialize NAPI */
1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll);
1219
1220 /* tie q_vector and adapter together */
1221 adapter->q_vector[v_idx] = q_vector;
1222 q_vector->adapter = adapter;
1223
1224 /* initialize work limits */
1225 q_vector->tx.work_limit = adapter->tx_work_limit;
1226
1227 /* initialize ITR configuration */
1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1229 q_vector->itr_val = IGB_START_ITR;
1230
1231 /* initialize pointer to rings */
1232 ring = q_vector->ring;
1233
1234 /* intialize ITR */
1235 if (rxr_count) {
1236 /* rx or rx/tx vector */
1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1238 q_vector->itr_val = adapter->rx_itr_setting;
1239 } else {
1240 /* tx only vector */
1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1242 q_vector->itr_val = adapter->tx_itr_setting;
1243 }
1244
1245 if (txr_count) {
1246 /* assign generic ring traits */
1247 ring->dev = &adapter->pdev->dev;
1248 ring->netdev = adapter->netdev;
1249
1250 /* configure backlink on ring */
1251 ring->q_vector = q_vector;
1252
1253 /* update q_vector Tx values */
1254 igb_add_ring(ring, &q_vector->tx);
1255
1256 /* For 82575, context index must be unique per ring. */
1257 if (adapter->hw.mac.type == e1000_82575)
1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1259
1260 /* apply Tx specific ring traits */
1261 ring->count = adapter->tx_ring_count;
1262 ring->queue_index = txr_idx;
1263
1264 ring->cbs_enable = false;
1265 ring->idleslope = 0;
1266 ring->sendslope = 0;
1267 ring->hicredit = 0;
1268 ring->locredit = 0;
1269
1270 u64_stats_init(&ring->tx_syncp);
1271 u64_stats_init(&ring->tx_syncp2);
1272
1273 /* assign ring to adapter */
1274 adapter->tx_ring[txr_idx] = ring;
1275
1276 /* push pointer to next ring */
1277 ring++;
1278 }
1279
1280 if (rxr_count) {
1281 /* assign generic ring traits */
1282 ring->dev = &adapter->pdev->dev;
1283 ring->netdev = adapter->netdev;
1284
1285 /* configure backlink on ring */
1286 ring->q_vector = q_vector;
1287
1288 /* update q_vector Rx values */
1289 igb_add_ring(ring, &q_vector->rx);
1290
1291 /* set flag indicating ring supports SCTP checksum offload */
1292 if (adapter->hw.mac.type >= e1000_82576)
1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1294
1295 /* On i350, i354, i210, and i211, loopback VLAN packets
1296 * have the tag byte-swapped.
1297 */
1298 if (adapter->hw.mac.type >= e1000_i350)
1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1300
1301 /* apply Rx specific ring traits */
1302 ring->count = adapter->rx_ring_count;
1303 ring->queue_index = rxr_idx;
1304
1305 u64_stats_init(&ring->rx_syncp);
1306
1307 /* assign ring to adapter */
1308 adapter->rx_ring[rxr_idx] = ring;
1309 }
1310
1311 return 0;
1312 }
1313
1314
1315 /**
1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1317 * @adapter: board private structure to initialize
1318 *
1319 * We allocate one q_vector per queue interrupt. If allocation fails we
1320 * return -ENOMEM.
1321 **/
igb_alloc_q_vectors(struct igb_adapter * adapter)1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1323 {
1324 int q_vectors = adapter->num_q_vectors;
1325 int rxr_remaining = adapter->num_rx_queues;
1326 int txr_remaining = adapter->num_tx_queues;
1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1328 int err;
1329
1330 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1331 for (; rxr_remaining; v_idx++) {
1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1333 0, 0, 1, rxr_idx);
1334
1335 if (err)
1336 goto err_out;
1337
1338 /* update counts and index */
1339 rxr_remaining--;
1340 rxr_idx++;
1341 }
1342 }
1343
1344 for (; v_idx < q_vectors; v_idx++) {
1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347
1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1349 tqpv, txr_idx, rqpv, rxr_idx);
1350
1351 if (err)
1352 goto err_out;
1353
1354 /* update counts and index */
1355 rxr_remaining -= rqpv;
1356 txr_remaining -= tqpv;
1357 rxr_idx++;
1358 txr_idx++;
1359 }
1360
1361 return 0;
1362
1363 err_out:
1364 adapter->num_tx_queues = 0;
1365 adapter->num_rx_queues = 0;
1366 adapter->num_q_vectors = 0;
1367
1368 while (v_idx--)
1369 igb_free_q_vector(adapter, v_idx);
1370
1371 return -ENOMEM;
1372 }
1373
1374 /**
1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1376 * @adapter: board private structure to initialize
1377 * @msix: boolean value of MSIX capability
1378 *
1379 * This function initializes the interrupts and allocates all of the queues.
1380 **/
igb_init_interrupt_scheme(struct igb_adapter * adapter,bool msix)1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1382 {
1383 struct pci_dev *pdev = adapter->pdev;
1384 int err;
1385
1386 igb_set_interrupt_capability(adapter, msix);
1387
1388 err = igb_alloc_q_vectors(adapter);
1389 if (err) {
1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1391 goto err_alloc_q_vectors;
1392 }
1393
1394 igb_cache_ring_register(adapter);
1395
1396 return 0;
1397
1398 err_alloc_q_vectors:
1399 igb_reset_interrupt_capability(adapter);
1400 return err;
1401 }
1402
1403 /**
1404 * igb_request_irq - initialize interrupts
1405 * @adapter: board private structure to initialize
1406 *
1407 * Attempts to configure interrupts using the best available
1408 * capabilities of the hardware and kernel.
1409 **/
igb_request_irq(struct igb_adapter * adapter)1410 static int igb_request_irq(struct igb_adapter *adapter)
1411 {
1412 struct net_device *netdev = adapter->netdev;
1413 struct pci_dev *pdev = adapter->pdev;
1414 int err = 0;
1415
1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1417 err = igb_request_msix(adapter);
1418 if (!err)
1419 goto request_done;
1420 /* fall back to MSI */
1421 igb_free_all_tx_resources(adapter);
1422 igb_free_all_rx_resources(adapter);
1423
1424 igb_clear_interrupt_scheme(adapter);
1425 err = igb_init_interrupt_scheme(adapter, false);
1426 if (err)
1427 goto request_done;
1428
1429 igb_setup_all_tx_resources(adapter);
1430 igb_setup_all_rx_resources(adapter);
1431 igb_configure(adapter);
1432 }
1433
1434 igb_assign_vector(adapter->q_vector[0], 0);
1435
1436 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1437 err = request_irq(pdev->irq, igb_intr_msi, 0,
1438 netdev->name, adapter);
1439 if (!err)
1440 goto request_done;
1441
1442 /* fall back to legacy interrupts */
1443 igb_reset_interrupt_capability(adapter);
1444 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1445 }
1446
1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1448 netdev->name, adapter);
1449
1450 if (err)
1451 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1452 err);
1453
1454 request_done:
1455 return err;
1456 }
1457
igb_free_irq(struct igb_adapter * adapter)1458 static void igb_free_irq(struct igb_adapter *adapter)
1459 {
1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1461 int vector = 0, i;
1462
1463 free_irq(adapter->msix_entries[vector++].vector, adapter);
1464
1465 for (i = 0; i < adapter->num_q_vectors; i++)
1466 free_irq(adapter->msix_entries[vector++].vector,
1467 adapter->q_vector[i]);
1468 } else {
1469 free_irq(adapter->pdev->irq, adapter);
1470 }
1471 }
1472
1473 /**
1474 * igb_irq_disable - Mask off interrupt generation on the NIC
1475 * @adapter: board private structure
1476 **/
igb_irq_disable(struct igb_adapter * adapter)1477 static void igb_irq_disable(struct igb_adapter *adapter)
1478 {
1479 struct e1000_hw *hw = &adapter->hw;
1480
1481 /* we need to be careful when disabling interrupts. The VFs are also
1482 * mapped into these registers and so clearing the bits can cause
1483 * issues on the VF drivers so we only need to clear what we set
1484 */
1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1486 u32 regval = rd32(E1000_EIAM);
1487
1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1489 wr32(E1000_EIMC, adapter->eims_enable_mask);
1490 regval = rd32(E1000_EIAC);
1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1492 }
1493
1494 wr32(E1000_IAM, 0);
1495 wr32(E1000_IMC, ~0);
1496 wrfl();
1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1498 int i;
1499
1500 for (i = 0; i < adapter->num_q_vectors; i++)
1501 synchronize_irq(adapter->msix_entries[i].vector);
1502 } else {
1503 synchronize_irq(adapter->pdev->irq);
1504 }
1505 }
1506
1507 /**
1508 * igb_irq_enable - Enable default interrupt generation settings
1509 * @adapter: board private structure
1510 **/
igb_irq_enable(struct igb_adapter * adapter)1511 static void igb_irq_enable(struct igb_adapter *adapter)
1512 {
1513 struct e1000_hw *hw = &adapter->hw;
1514
1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1517 u32 regval = rd32(E1000_EIAC);
1518
1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1520 regval = rd32(E1000_EIAM);
1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1522 wr32(E1000_EIMS, adapter->eims_enable_mask);
1523 if (adapter->vfs_allocated_count) {
1524 wr32(E1000_MBVFIMR, 0xFF);
1525 ims |= E1000_IMS_VMMB;
1526 }
1527 wr32(E1000_IMS, ims);
1528 } else {
1529 wr32(E1000_IMS, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
1531 wr32(E1000_IAM, IMS_ENABLE_MASK |
1532 E1000_IMS_DRSTA);
1533 }
1534 }
1535
igb_update_mng_vlan(struct igb_adapter * adapter)1536 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1537 {
1538 struct e1000_hw *hw = &adapter->hw;
1539 u16 pf_id = adapter->vfs_allocated_count;
1540 u16 vid = adapter->hw.mng_cookie.vlan_id;
1541 u16 old_vid = adapter->mng_vlan_id;
1542
1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1544 /* add VID to filter table */
1545 igb_vfta_set(hw, vid, pf_id, true, true);
1546 adapter->mng_vlan_id = vid;
1547 } else {
1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1549 }
1550
1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1552 (vid != old_vid) &&
1553 !test_bit(old_vid, adapter->active_vlans)) {
1554 /* remove VID from filter table */
1555 igb_vfta_set(hw, vid, pf_id, false, true);
1556 }
1557 }
1558
1559 /**
1560 * igb_release_hw_control - release control of the h/w to f/w
1561 * @adapter: address of board private structure
1562 *
1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1564 * For ASF and Pass Through versions of f/w this means that the
1565 * driver is no longer loaded.
1566 **/
igb_release_hw_control(struct igb_adapter * adapter)1567 static void igb_release_hw_control(struct igb_adapter *adapter)
1568 {
1569 struct e1000_hw *hw = &adapter->hw;
1570 u32 ctrl_ext;
1571
1572 /* Let firmware take over control of h/w */
1573 ctrl_ext = rd32(E1000_CTRL_EXT);
1574 wr32(E1000_CTRL_EXT,
1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1576 }
1577
1578 /**
1579 * igb_get_hw_control - get control of the h/w from f/w
1580 * @adapter: address of board private structure
1581 *
1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1583 * For ASF and Pass Through versions of f/w this means that
1584 * the driver is loaded.
1585 **/
igb_get_hw_control(struct igb_adapter * adapter)1586 static void igb_get_hw_control(struct igb_adapter *adapter)
1587 {
1588 struct e1000_hw *hw = &adapter->hw;
1589 u32 ctrl_ext;
1590
1591 /* Let firmware know the driver has taken over */
1592 ctrl_ext = rd32(E1000_CTRL_EXT);
1593 wr32(E1000_CTRL_EXT,
1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1595 }
1596
enable_fqtss(struct igb_adapter * adapter,bool enable)1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1598 {
1599 struct net_device *netdev = adapter->netdev;
1600 struct e1000_hw *hw = &adapter->hw;
1601
1602 WARN_ON(hw->mac.type != e1000_i210);
1603
1604 if (enable)
1605 adapter->flags |= IGB_FLAG_FQTSS;
1606 else
1607 adapter->flags &= ~IGB_FLAG_FQTSS;
1608
1609 if (netif_running(netdev))
1610 schedule_work(&adapter->reset_task);
1611 }
1612
is_fqtss_enabled(struct igb_adapter * adapter)1613 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1614 {
1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1616 }
1617
set_tx_desc_fetch_prio(struct e1000_hw * hw,int queue,enum tx_queue_prio prio)1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1619 enum tx_queue_prio prio)
1620 {
1621 u32 val;
1622
1623 WARN_ON(hw->mac.type != e1000_i210);
1624 WARN_ON(queue < 0 || queue > 4);
1625
1626 val = rd32(E1000_I210_TXDCTL(queue));
1627
1628 if (prio == TX_QUEUE_PRIO_HIGH)
1629 val |= E1000_TXDCTL_PRIORITY;
1630 else
1631 val &= ~E1000_TXDCTL_PRIORITY;
1632
1633 wr32(E1000_I210_TXDCTL(queue), val);
1634 }
1635
set_queue_mode(struct e1000_hw * hw,int queue,enum queue_mode mode)1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1637 {
1638 u32 val;
1639
1640 WARN_ON(hw->mac.type != e1000_i210);
1641 WARN_ON(queue < 0 || queue > 1);
1642
1643 val = rd32(E1000_I210_TQAVCC(queue));
1644
1645 if (mode == QUEUE_MODE_STREAM_RESERVATION)
1646 val |= E1000_TQAVCC_QUEUEMODE;
1647 else
1648 val &= ~E1000_TQAVCC_QUEUEMODE;
1649
1650 wr32(E1000_I210_TQAVCC(queue), val);
1651 }
1652
is_any_cbs_enabled(struct igb_adapter * adapter)1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1654 {
1655 int i;
1656
1657 for (i = 0; i < adapter->num_tx_queues; i++) {
1658 if (adapter->tx_ring[i]->cbs_enable)
1659 return true;
1660 }
1661
1662 return false;
1663 }
1664
is_any_txtime_enabled(struct igb_adapter * adapter)1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1666 {
1667 int i;
1668
1669 for (i = 0; i < adapter->num_tx_queues; i++) {
1670 if (adapter->tx_ring[i]->launchtime_enable)
1671 return true;
1672 }
1673
1674 return false;
1675 }
1676
1677 /**
1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1679 * @adapter: pointer to adapter struct
1680 * @queue: queue number
1681 *
1682 * Configure CBS and Launchtime for a given hardware queue.
1683 * Parameters are retrieved from the correct Tx ring, so
1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1685 * for setting those correctly prior to this function being called.
1686 **/
igb_config_tx_modes(struct igb_adapter * adapter,int queue)1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1688 {
1689 struct net_device *netdev = adapter->netdev;
1690 struct e1000_hw *hw = &adapter->hw;
1691 struct igb_ring *ring;
1692 u32 tqavcc, tqavctrl;
1693 u16 value;
1694
1695 WARN_ON(hw->mac.type != e1000_i210);
1696 WARN_ON(queue < 0 || queue > 1);
1697 ring = adapter->tx_ring[queue];
1698
1699 /* If any of the Qav features is enabled, configure queues as SR and
1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1701 * as SP.
1702 */
1703 if (ring->cbs_enable || ring->launchtime_enable) {
1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1706 } else {
1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1709 }
1710
1711 /* If CBS is enabled, set DataTranARB and config its parameters. */
1712 if (ring->cbs_enable || queue == 0) {
1713 /* i210 does not allow the queue 0 to be in the Strict
1714 * Priority mode while the Qav mode is enabled, so,
1715 * instead of disabling strict priority mode, we give
1716 * queue 0 the maximum of credits possible.
1717 *
1718 * See section 8.12.19 of the i210 datasheet, "Note:
1719 * Queue0 QueueMode must be set to 1b when
1720 * TransmitMode is set to Qav."
1721 */
1722 if (queue == 0 && !ring->cbs_enable) {
1723 /* max "linkspeed" idleslope in kbps */
1724 ring->idleslope = 1000000;
1725 ring->hicredit = ETH_FRAME_LEN;
1726 }
1727
1728 /* Always set data transfer arbitration to credit-based
1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1730 * the queues.
1731 */
1732 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1734 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1735
1736 /* According to i210 datasheet section 7.2.7.7, we should set
1737 * the 'idleSlope' field from TQAVCC register following the
1738 * equation:
1739 *
1740 * For 100 Mbps link speed:
1741 *
1742 * value = BW * 0x7735 * 0.2 (E1)
1743 *
1744 * For 1000Mbps link speed:
1745 *
1746 * value = BW * 0x7735 * 2 (E2)
1747 *
1748 * E1 and E2 can be merged into one equation as shown below.
1749 * Note that 'link-speed' is in Mbps.
1750 *
1751 * value = BW * 0x7735 * 2 * link-speed
1752 * -------------- (E3)
1753 * 1000
1754 *
1755 * 'BW' is the percentage bandwidth out of full link speed
1756 * which can be found with the following equation. Note that
1757 * idleSlope here is the parameter from this function which
1758 * is in kbps.
1759 *
1760 * BW = idleSlope
1761 * ----------------- (E4)
1762 * link-speed * 1000
1763 *
1764 * That said, we can come up with a generic equation to
1765 * calculate the value we should set it TQAVCC register by
1766 * replacing 'BW' in E3 by E4. The resulting equation is:
1767 *
1768 * value = idleSlope * 0x7735 * 2 * link-speed
1769 * ----------------- -------------- (E5)
1770 * link-speed * 1000 1000
1771 *
1772 * 'link-speed' is present in both sides of the fraction so
1773 * it is canceled out. The final equation is the following:
1774 *
1775 * value = idleSlope * 61034
1776 * ----------------- (E6)
1777 * 1000000
1778 *
1779 * NOTE: For i210, given the above, we can see that idleslope
1780 * is represented in 16.38431 kbps units by the value at
1781 * the TQAVCC register (1Gbps / 61034), which reduces
1782 * the granularity for idleslope increments.
1783 * For instance, if you want to configure a 2576kbps
1784 * idleslope, the value to be written on the register
1785 * would have to be 157.23. If rounded down, you end
1786 * up with less bandwidth available than originally
1787 * required (~2572 kbps). If rounded up, you end up
1788 * with a higher bandwidth (~2589 kbps). Below the
1789 * approach we take is to always round up the
1790 * calculated value, so the resulting bandwidth might
1791 * be slightly higher for some configurations.
1792 */
1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1794
1795 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1797 tqavcc |= value;
1798 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1799
1800 wr32(E1000_I210_TQAVHC(queue),
1801 0x80000000 + ring->hicredit * 0x7735);
1802 } else {
1803
1804 /* Set idleSlope to zero. */
1805 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1807 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1808
1809 /* Set hiCredit to zero. */
1810 wr32(E1000_I210_TQAVHC(queue), 0);
1811
1812 /* If CBS is not enabled for any queues anymore, then return to
1813 * the default state of Data Transmission Arbitration on
1814 * TQAVCTRL.
1815 */
1816 if (!is_any_cbs_enabled(adapter)) {
1817 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1819 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1820 }
1821 }
1822
1823 /* If LaunchTime is enabled, set DataTranTIM. */
1824 if (ring->launchtime_enable) {
1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1826 * for any of the SR queues, and configure fetchtime delta.
1827 * XXX NOTE:
1828 * - LaunchTime will be enabled for all SR queues.
1829 * - A fixed offset can be added relative to the launch
1830 * time of all packets if configured at reg LAUNCH_OS0.
1831 * We are keeping it as 0 for now (default value).
1832 */
1833 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1835 E1000_TQAVCTRL_FETCHTIME_DELTA;
1836 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1837 } else {
1838 /* If Launchtime is not enabled for any SR queues anymore,
1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1840 * effectively disabling Launchtime.
1841 */
1842 if (!is_any_txtime_enabled(adapter)) {
1843 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1846 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1847 }
1848 }
1849
1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1851 * CBS are not configurable by software so we don't do any 'controller
1852 * configuration' in respect to these parameters.
1853 */
1854
1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1856 ring->cbs_enable ? "enabled" : "disabled",
1857 ring->launchtime_enable ? "enabled" : "disabled",
1858 queue,
1859 ring->idleslope, ring->sendslope,
1860 ring->hicredit, ring->locredit);
1861 }
1862
igb_save_txtime_params(struct igb_adapter * adapter,int queue,bool enable)1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1864 bool enable)
1865 {
1866 struct igb_ring *ring;
1867
1868 if (queue < 0 || queue > adapter->num_tx_queues)
1869 return -EINVAL;
1870
1871 ring = adapter->tx_ring[queue];
1872 ring->launchtime_enable = enable;
1873
1874 return 0;
1875 }
1876
igb_save_cbs_params(struct igb_adapter * adapter,int queue,bool enable,int idleslope,int sendslope,int hicredit,int locredit)1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1878 bool enable, int idleslope, int sendslope,
1879 int hicredit, int locredit)
1880 {
1881 struct igb_ring *ring;
1882
1883 if (queue < 0 || queue > adapter->num_tx_queues)
1884 return -EINVAL;
1885
1886 ring = adapter->tx_ring[queue];
1887
1888 ring->cbs_enable = enable;
1889 ring->idleslope = idleslope;
1890 ring->sendslope = sendslope;
1891 ring->hicredit = hicredit;
1892 ring->locredit = locredit;
1893
1894 return 0;
1895 }
1896
1897 /**
1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1899 * @adapter: pointer to adapter struct
1900 *
1901 * Configure TQAVCTRL register switching the controller's Tx mode
1902 * if FQTSS mode is enabled or disabled. Additionally, will issue
1903 * a call to igb_config_tx_modes() per queue so any previously saved
1904 * Tx parameters are applied.
1905 **/
igb_setup_tx_mode(struct igb_adapter * adapter)1906 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1907 {
1908 struct net_device *netdev = adapter->netdev;
1909 struct e1000_hw *hw = &adapter->hw;
1910 u32 val;
1911
1912 /* Only i210 controller supports changing the transmission mode. */
1913 if (hw->mac.type != e1000_i210)
1914 return;
1915
1916 if (is_fqtss_enabled(adapter)) {
1917 int i, max_queue;
1918
1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1921 * so SP queues wait for SR ones.
1922 */
1923 val = rd32(E1000_I210_TQAVCTRL);
1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1926 wr32(E1000_I210_TQAVCTRL, val);
1927
1928 /* Configure Tx and Rx packet buffers sizes as described in
1929 * i210 datasheet section 7.2.7.7.
1930 */
1931 val = rd32(E1000_TXPBS);
1932 val &= ~I210_TXPBSIZE_MASK;
1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1935 wr32(E1000_TXPBS, val);
1936
1937 val = rd32(E1000_RXPBS);
1938 val &= ~I210_RXPBSIZE_MASK;
1939 val |= I210_RXPBSIZE_PB_30KB;
1940 wr32(E1000_RXPBS, val);
1941
1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1943 * register should not exceed the buffer size programmed in
1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1945 * so according to the datasheet we should set MAX_TPKT_SIZE to
1946 * 4kB / 64.
1947 *
1948 * However, when we do so, no frame from queue 2 and 3 are
1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great
1950 * or _equal_ to the buffer size programmed in TXPBS. For this
1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1952 */
1953 val = (4096 - 1) / 64;
1954 wr32(E1000_I210_DTXMXPKTSZ, val);
1955
1956 /* Since FQTSS mode is enabled, apply any CBS configuration
1957 * previously set. If no previous CBS configuration has been
1958 * done, then the initial configuration is applied, which means
1959 * CBS is disabled.
1960 */
1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1963
1964 for (i = 0; i < max_queue; i++) {
1965 igb_config_tx_modes(adapter, i);
1966 }
1967 } else {
1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1971
1972 val = rd32(E1000_I210_TQAVCTRL);
1973 /* According to Section 8.12.21, the other flags we've set when
1974 * enabling FQTSS are not relevant when disabling FQTSS so we
1975 * don't set they here.
1976 */
1977 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1978 wr32(E1000_I210_TQAVCTRL, val);
1979 }
1980
1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1982 "enabled" : "disabled");
1983 }
1984
1985 /**
1986 * igb_configure - configure the hardware for RX and TX
1987 * @adapter: private board structure
1988 **/
igb_configure(struct igb_adapter * adapter)1989 static void igb_configure(struct igb_adapter *adapter)
1990 {
1991 struct net_device *netdev = adapter->netdev;
1992 int i;
1993
1994 igb_get_hw_control(adapter);
1995 igb_set_rx_mode(netdev);
1996 igb_setup_tx_mode(adapter);
1997
1998 igb_restore_vlan(adapter);
1999
2000 igb_setup_tctl(adapter);
2001 igb_setup_mrqc(adapter);
2002 igb_setup_rctl(adapter);
2003
2004 igb_nfc_filter_restore(adapter);
2005 igb_configure_tx(adapter);
2006 igb_configure_rx(adapter);
2007
2008 igb_rx_fifo_flush_82575(&adapter->hw);
2009
2010 /* call igb_desc_unused which always leaves
2011 * at least 1 descriptor unused to make sure
2012 * next_to_use != next_to_clean
2013 */
2014 for (i = 0; i < adapter->num_rx_queues; i++) {
2015 struct igb_ring *ring = adapter->rx_ring[i];
2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2017 }
2018 }
2019
2020 /**
2021 * igb_power_up_link - Power up the phy/serdes link
2022 * @adapter: address of board private structure
2023 **/
igb_power_up_link(struct igb_adapter * adapter)2024 void igb_power_up_link(struct igb_adapter *adapter)
2025 {
2026 igb_reset_phy(&adapter->hw);
2027
2028 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2029 igb_power_up_phy_copper(&adapter->hw);
2030 else
2031 igb_power_up_serdes_link_82575(&adapter->hw);
2032
2033 igb_setup_link(&adapter->hw);
2034 }
2035
2036 /**
2037 * igb_power_down_link - Power down the phy/serdes link
2038 * @adapter: address of board private structure
2039 */
igb_power_down_link(struct igb_adapter * adapter)2040 static void igb_power_down_link(struct igb_adapter *adapter)
2041 {
2042 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2043 igb_power_down_phy_copper_82575(&adapter->hw);
2044 else
2045 igb_shutdown_serdes_link_82575(&adapter->hw);
2046 }
2047
2048 /**
2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense
2050 * @adapter: address of the board private structure
2051 **/
igb_check_swap_media(struct igb_adapter * adapter)2052 static void igb_check_swap_media(struct igb_adapter *adapter)
2053 {
2054 struct e1000_hw *hw = &adapter->hw;
2055 u32 ctrl_ext, connsw;
2056 bool swap_now = false;
2057
2058 ctrl_ext = rd32(E1000_CTRL_EXT);
2059 connsw = rd32(E1000_CONNSW);
2060
2061 /* need to live swap if current media is copper and we have fiber/serdes
2062 * to go to.
2063 */
2064
2065 if ((hw->phy.media_type == e1000_media_type_copper) &&
2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2067 swap_now = true;
2068 } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2069 !(connsw & E1000_CONNSW_SERDESD)) {
2070 /* copper signal takes time to appear */
2071 if (adapter->copper_tries < 4) {
2072 adapter->copper_tries++;
2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2074 wr32(E1000_CONNSW, connsw);
2075 return;
2076 } else {
2077 adapter->copper_tries = 0;
2078 if ((connsw & E1000_CONNSW_PHYSD) &&
2079 (!(connsw & E1000_CONNSW_PHY_PDN))) {
2080 swap_now = true;
2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2082 wr32(E1000_CONNSW, connsw);
2083 }
2084 }
2085 }
2086
2087 if (!swap_now)
2088 return;
2089
2090 switch (hw->phy.media_type) {
2091 case e1000_media_type_copper:
2092 netdev_info(adapter->netdev,
2093 "MAS: changing media to fiber/serdes\n");
2094 ctrl_ext |=
2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2096 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2097 adapter->copper_tries = 0;
2098 break;
2099 case e1000_media_type_internal_serdes:
2100 case e1000_media_type_fiber:
2101 netdev_info(adapter->netdev,
2102 "MAS: changing media to copper\n");
2103 ctrl_ext &=
2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2105 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2106 break;
2107 default:
2108 /* shouldn't get here during regular operation */
2109 netdev_err(adapter->netdev,
2110 "AMS: Invalid media type found, returning\n");
2111 break;
2112 }
2113 wr32(E1000_CTRL_EXT, ctrl_ext);
2114 }
2115
2116 /**
2117 * igb_up - Open the interface and prepare it to handle traffic
2118 * @adapter: board private structure
2119 **/
igb_up(struct igb_adapter * adapter)2120 int igb_up(struct igb_adapter *adapter)
2121 {
2122 struct e1000_hw *hw = &adapter->hw;
2123 int i;
2124
2125 /* hardware has been reset, we need to reload some things */
2126 igb_configure(adapter);
2127
2128 clear_bit(__IGB_DOWN, &adapter->state);
2129
2130 for (i = 0; i < adapter->num_q_vectors; i++)
2131 napi_enable(&(adapter->q_vector[i]->napi));
2132
2133 if (adapter->flags & IGB_FLAG_HAS_MSIX)
2134 igb_configure_msix(adapter);
2135 else
2136 igb_assign_vector(adapter->q_vector[0], 0);
2137
2138 /* Clear any pending interrupts. */
2139 rd32(E1000_TSICR);
2140 rd32(E1000_ICR);
2141 igb_irq_enable(adapter);
2142
2143 /* notify VFs that reset has been completed */
2144 if (adapter->vfs_allocated_count) {
2145 u32 reg_data = rd32(E1000_CTRL_EXT);
2146
2147 reg_data |= E1000_CTRL_EXT_PFRSTD;
2148 wr32(E1000_CTRL_EXT, reg_data);
2149 }
2150
2151 netif_tx_start_all_queues(adapter->netdev);
2152
2153 /* start the watchdog. */
2154 hw->mac.get_link_status = 1;
2155 schedule_work(&adapter->watchdog_task);
2156
2157 if ((adapter->flags & IGB_FLAG_EEE) &&
2158 (!hw->dev_spec._82575.eee_disable))
2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2160
2161 return 0;
2162 }
2163
igb_down(struct igb_adapter * adapter)2164 void igb_down(struct igb_adapter *adapter)
2165 {
2166 struct net_device *netdev = adapter->netdev;
2167 struct e1000_hw *hw = &adapter->hw;
2168 u32 tctl, rctl;
2169 int i;
2170
2171 /* signal that we're down so the interrupt handler does not
2172 * reschedule our watchdog timer
2173 */
2174 set_bit(__IGB_DOWN, &adapter->state);
2175
2176 /* disable receives in the hardware */
2177 rctl = rd32(E1000_RCTL);
2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2179 /* flush and sleep below */
2180
2181 igb_nfc_filter_exit(adapter);
2182
2183 netif_carrier_off(netdev);
2184 netif_tx_stop_all_queues(netdev);
2185
2186 /* disable transmits in the hardware */
2187 tctl = rd32(E1000_TCTL);
2188 tctl &= ~E1000_TCTL_EN;
2189 wr32(E1000_TCTL, tctl);
2190 /* flush both disables and wait for them to finish */
2191 wrfl();
2192 usleep_range(10000, 11000);
2193
2194 igb_irq_disable(adapter);
2195
2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2197
2198 for (i = 0; i < adapter->num_q_vectors; i++) {
2199 if (adapter->q_vector[i]) {
2200 napi_synchronize(&adapter->q_vector[i]->napi);
2201 napi_disable(&adapter->q_vector[i]->napi);
2202 }
2203 }
2204
2205 del_timer_sync(&adapter->watchdog_timer);
2206 del_timer_sync(&adapter->phy_info_timer);
2207
2208 /* record the stats before reset*/
2209 spin_lock(&adapter->stats64_lock);
2210 igb_update_stats(adapter);
2211 spin_unlock(&adapter->stats64_lock);
2212
2213 adapter->link_speed = 0;
2214 adapter->link_duplex = 0;
2215
2216 if (!pci_channel_offline(adapter->pdev))
2217 igb_reset(adapter);
2218
2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */
2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2221
2222 igb_clean_all_tx_rings(adapter);
2223 igb_clean_all_rx_rings(adapter);
2224 #ifdef CONFIG_IGB_DCA
2225
2226 /* since we reset the hardware DCA settings were cleared */
2227 igb_setup_dca(adapter);
2228 #endif
2229 }
2230
igb_reinit_locked(struct igb_adapter * adapter)2231 void igb_reinit_locked(struct igb_adapter *adapter)
2232 {
2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2234 usleep_range(1000, 2000);
2235 igb_down(adapter);
2236 igb_up(adapter);
2237 clear_bit(__IGB_RESETTING, &adapter->state);
2238 }
2239
2240 /** igb_enable_mas - Media Autosense re-enable after swap
2241 *
2242 * @adapter: adapter struct
2243 **/
igb_enable_mas(struct igb_adapter * adapter)2244 static void igb_enable_mas(struct igb_adapter *adapter)
2245 {
2246 struct e1000_hw *hw = &adapter->hw;
2247 u32 connsw = rd32(E1000_CONNSW);
2248
2249 /* configure for SerDes media detect */
2250 if ((hw->phy.media_type == e1000_media_type_copper) &&
2251 (!(connsw & E1000_CONNSW_SERDESD))) {
2252 connsw |= E1000_CONNSW_ENRGSRC;
2253 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2254 wr32(E1000_CONNSW, connsw);
2255 wrfl();
2256 }
2257 }
2258
2259 #ifdef CONFIG_IGB_HWMON
2260 /**
2261 * igb_set_i2c_bb - Init I2C interface
2262 * @hw: pointer to hardware structure
2263 **/
igb_set_i2c_bb(struct e1000_hw * hw)2264 static void igb_set_i2c_bb(struct e1000_hw *hw)
2265 {
2266 u32 ctrl_ext;
2267 s32 i2cctl;
2268
2269 ctrl_ext = rd32(E1000_CTRL_EXT);
2270 ctrl_ext |= E1000_CTRL_I2C_ENA;
2271 wr32(E1000_CTRL_EXT, ctrl_ext);
2272 wrfl();
2273
2274 i2cctl = rd32(E1000_I2CPARAMS);
2275 i2cctl |= E1000_I2CBB_EN
2276 | E1000_I2C_CLK_OE_N
2277 | E1000_I2C_DATA_OE_N;
2278 wr32(E1000_I2CPARAMS, i2cctl);
2279 wrfl();
2280 }
2281 #endif
2282
igb_reset(struct igb_adapter * adapter)2283 void igb_reset(struct igb_adapter *adapter)
2284 {
2285 struct pci_dev *pdev = adapter->pdev;
2286 struct e1000_hw *hw = &adapter->hw;
2287 struct e1000_mac_info *mac = &hw->mac;
2288 struct e1000_fc_info *fc = &hw->fc;
2289 u32 pba, hwm;
2290
2291 /* Repartition Pba for greater than 9k mtu
2292 * To take effect CTRL.RST is required.
2293 */
2294 switch (mac->type) {
2295 case e1000_i350:
2296 case e1000_i354:
2297 case e1000_82580:
2298 pba = rd32(E1000_RXPBS);
2299 pba = igb_rxpbs_adjust_82580(pba);
2300 break;
2301 case e1000_82576:
2302 pba = rd32(E1000_RXPBS);
2303 pba &= E1000_RXPBS_SIZE_MASK_82576;
2304 break;
2305 case e1000_82575:
2306 case e1000_i210:
2307 case e1000_i211:
2308 default:
2309 pba = E1000_PBA_34K;
2310 break;
2311 }
2312
2313 if (mac->type == e1000_82575) {
2314 u32 min_rx_space, min_tx_space, needed_tx_space;
2315
2316 /* write Rx PBA so that hardware can report correct Tx PBA */
2317 wr32(E1000_PBA, pba);
2318
2319 /* To maintain wire speed transmits, the Tx FIFO should be
2320 * large enough to accommodate two full transmit packets,
2321 * rounded up to the next 1KB and expressed in KB. Likewise,
2322 * the Rx FIFO should be large enough to accommodate at least
2323 * one full receive packet and is similarly rounded up and
2324 * expressed in KB.
2325 */
2326 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2327
2328 /* The Tx FIFO also stores 16 bytes of information about the Tx
2329 * but don't include Ethernet FCS because hardware appends it.
2330 * We only need to round down to the nearest 512 byte block
2331 * count since the value we care about is 2 frames, not 1.
2332 */
2333 min_tx_space = adapter->max_frame_size;
2334 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2335 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2336
2337 /* upper 16 bits has Tx packet buffer allocation size in KB */
2338 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2339
2340 /* If current Tx allocation is less than the min Tx FIFO size,
2341 * and the min Tx FIFO size is less than the current Rx FIFO
2342 * allocation, take space away from current Rx allocation.
2343 */
2344 if (needed_tx_space < pba) {
2345 pba -= needed_tx_space;
2346
2347 /* if short on Rx space, Rx wins and must trump Tx
2348 * adjustment
2349 */
2350 if (pba < min_rx_space)
2351 pba = min_rx_space;
2352 }
2353
2354 /* adjust PBA for jumbo frames */
2355 wr32(E1000_PBA, pba);
2356 }
2357
2358 /* flow control settings
2359 * The high water mark must be low enough to fit one full frame
2360 * after transmitting the pause frame. As such we must have enough
2361 * space to allow for us to complete our current transmit and then
2362 * receive the frame that is in progress from the link partner.
2363 * Set it to:
2364 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2365 */
2366 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2367
2368 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
2369 fc->low_water = fc->high_water - 16;
2370 fc->pause_time = 0xFFFF;
2371 fc->send_xon = 1;
2372 fc->current_mode = fc->requested_mode;
2373
2374 /* disable receive for all VFs and wait one second */
2375 if (adapter->vfs_allocated_count) {
2376 int i;
2377
2378 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2379 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2380
2381 /* ping all the active vfs to let them know we are going down */
2382 igb_ping_all_vfs(adapter);
2383
2384 /* disable transmits and receives */
2385 wr32(E1000_VFRE, 0);
2386 wr32(E1000_VFTE, 0);
2387 }
2388
2389 /* Allow time for pending master requests to run */
2390 hw->mac.ops.reset_hw(hw);
2391 wr32(E1000_WUC, 0);
2392
2393 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2394 /* need to resetup here after media swap */
2395 adapter->ei.get_invariants(hw);
2396 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2397 }
2398 if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2399 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2400 igb_enable_mas(adapter);
2401 }
2402 if (hw->mac.ops.init_hw(hw))
2403 dev_err(&pdev->dev, "Hardware Error\n");
2404
2405 /* RAR registers were cleared during init_hw, clear mac table */
2406 igb_flush_mac_table(adapter);
2407 __dev_uc_unsync(adapter->netdev, NULL);
2408
2409 /* Recover default RAR entry */
2410 igb_set_default_mac_filter(adapter);
2411
2412 /* Flow control settings reset on hardware reset, so guarantee flow
2413 * control is off when forcing speed.
2414 */
2415 if (!hw->mac.autoneg)
2416 igb_force_mac_fc(hw);
2417
2418 igb_init_dmac(adapter, pba);
2419 #ifdef CONFIG_IGB_HWMON
2420 /* Re-initialize the thermal sensor on i350 devices. */
2421 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2422 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2423 /* If present, re-initialize the external thermal sensor
2424 * interface.
2425 */
2426 if (adapter->ets)
2427 igb_set_i2c_bb(hw);
2428 mac->ops.init_thermal_sensor_thresh(hw);
2429 }
2430 }
2431 #endif
2432 /* Re-establish EEE setting */
2433 if (hw->phy.media_type == e1000_media_type_copper) {
2434 switch (mac->type) {
2435 case e1000_i350:
2436 case e1000_i210:
2437 case e1000_i211:
2438 igb_set_eee_i350(hw, true, true);
2439 break;
2440 case e1000_i354:
2441 igb_set_eee_i354(hw, true, true);
2442 break;
2443 default:
2444 break;
2445 }
2446 }
2447 if (!netif_running(adapter->netdev))
2448 igb_power_down_link(adapter);
2449
2450 igb_update_mng_vlan(adapter);
2451
2452 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2453 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2454
2455 /* Re-enable PTP, where applicable. */
2456 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2457 igb_ptp_reset(adapter);
2458
2459 igb_get_phy_info(hw);
2460 }
2461
igb_fix_features(struct net_device * netdev,netdev_features_t features)2462 static netdev_features_t igb_fix_features(struct net_device *netdev,
2463 netdev_features_t features)
2464 {
2465 /* Since there is no support for separate Rx/Tx vlan accel
2466 * enable/disable make sure Tx flag is always in same state as Rx.
2467 */
2468 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2469 features |= NETIF_F_HW_VLAN_CTAG_TX;
2470 else
2471 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2472
2473 return features;
2474 }
2475
igb_set_features(struct net_device * netdev,netdev_features_t features)2476 static int igb_set_features(struct net_device *netdev,
2477 netdev_features_t features)
2478 {
2479 netdev_features_t changed = netdev->features ^ features;
2480 struct igb_adapter *adapter = netdev_priv(netdev);
2481
2482 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2483 igb_vlan_mode(netdev, features);
2484
2485 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2486 return 0;
2487
2488 if (!(features & NETIF_F_NTUPLE)) {
2489 struct hlist_node *node2;
2490 struct igb_nfc_filter *rule;
2491
2492 spin_lock(&adapter->nfc_lock);
2493 hlist_for_each_entry_safe(rule, node2,
2494 &adapter->nfc_filter_list, nfc_node) {
2495 igb_erase_filter(adapter, rule);
2496 hlist_del(&rule->nfc_node);
2497 kfree(rule);
2498 }
2499 spin_unlock(&adapter->nfc_lock);
2500 adapter->nfc_filter_count = 0;
2501 }
2502
2503 netdev->features = features;
2504
2505 if (netif_running(netdev))
2506 igb_reinit_locked(adapter);
2507 else
2508 igb_reset(adapter);
2509
2510 return 1;
2511 }
2512
igb_ndo_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags,struct netlink_ext_ack * extack)2513 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2514 struct net_device *dev,
2515 const unsigned char *addr, u16 vid,
2516 u16 flags,
2517 struct netlink_ext_ack *extack)
2518 {
2519 /* guarantee we can provide a unique filter for the unicast address */
2520 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2521 struct igb_adapter *adapter = netdev_priv(dev);
2522 int vfn = adapter->vfs_allocated_count;
2523
2524 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2525 return -ENOMEM;
2526 }
2527
2528 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2529 }
2530
2531 #define IGB_MAX_MAC_HDR_LEN 127
2532 #define IGB_MAX_NETWORK_HDR_LEN 511
2533
2534 static netdev_features_t
igb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2535 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2536 netdev_features_t features)
2537 {
2538 unsigned int network_hdr_len, mac_hdr_len;
2539
2540 /* Make certain the headers can be described by a context descriptor */
2541 mac_hdr_len = skb_network_header(skb) - skb->data;
2542 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2543 return features & ~(NETIF_F_HW_CSUM |
2544 NETIF_F_SCTP_CRC |
2545 NETIF_F_GSO_UDP_L4 |
2546 NETIF_F_HW_VLAN_CTAG_TX |
2547 NETIF_F_TSO |
2548 NETIF_F_TSO6);
2549
2550 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2551 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2552 return features & ~(NETIF_F_HW_CSUM |
2553 NETIF_F_SCTP_CRC |
2554 NETIF_F_GSO_UDP_L4 |
2555 NETIF_F_TSO |
2556 NETIF_F_TSO6);
2557
2558 /* We can only support IPV4 TSO in tunnels if we can mangle the
2559 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2560 */
2561 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2562 features &= ~NETIF_F_TSO;
2563
2564 return features;
2565 }
2566
igb_offload_apply(struct igb_adapter * adapter,s32 queue)2567 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2568 {
2569 if (!is_fqtss_enabled(adapter)) {
2570 enable_fqtss(adapter, true);
2571 return;
2572 }
2573
2574 igb_config_tx_modes(adapter, queue);
2575
2576 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2577 enable_fqtss(adapter, false);
2578 }
2579
igb_offload_cbs(struct igb_adapter * adapter,struct tc_cbs_qopt_offload * qopt)2580 static int igb_offload_cbs(struct igb_adapter *adapter,
2581 struct tc_cbs_qopt_offload *qopt)
2582 {
2583 struct e1000_hw *hw = &adapter->hw;
2584 int err;
2585
2586 /* CBS offloading is only supported by i210 controller. */
2587 if (hw->mac.type != e1000_i210)
2588 return -EOPNOTSUPP;
2589
2590 /* CBS offloading is only supported by queue 0 and queue 1. */
2591 if (qopt->queue < 0 || qopt->queue > 1)
2592 return -EINVAL;
2593
2594 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2595 qopt->idleslope, qopt->sendslope,
2596 qopt->hicredit, qopt->locredit);
2597 if (err)
2598 return err;
2599
2600 igb_offload_apply(adapter, qopt->queue);
2601
2602 return 0;
2603 }
2604
2605 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2606 #define VLAN_PRIO_FULL_MASK (0x07)
2607
igb_parse_cls_flower(struct igb_adapter * adapter,struct flow_cls_offload * f,int traffic_class,struct igb_nfc_filter * input)2608 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2609 struct flow_cls_offload *f,
2610 int traffic_class,
2611 struct igb_nfc_filter *input)
2612 {
2613 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2614 struct flow_dissector *dissector = rule->match.dissector;
2615 struct netlink_ext_ack *extack = f->common.extack;
2616
2617 if (dissector->used_keys &
2618 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2619 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2620 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2621 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
2622 NL_SET_ERR_MSG_MOD(extack,
2623 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2624 return -EOPNOTSUPP;
2625 }
2626
2627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2628 struct flow_match_eth_addrs match;
2629
2630 flow_rule_match_eth_addrs(rule, &match);
2631 if (!is_zero_ether_addr(match.mask->dst)) {
2632 if (!is_broadcast_ether_addr(match.mask->dst)) {
2633 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2634 return -EINVAL;
2635 }
2636
2637 input->filter.match_flags |=
2638 IGB_FILTER_FLAG_DST_MAC_ADDR;
2639 ether_addr_copy(input->filter.dst_addr, match.key->dst);
2640 }
2641
2642 if (!is_zero_ether_addr(match.mask->src)) {
2643 if (!is_broadcast_ether_addr(match.mask->src)) {
2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2645 return -EINVAL;
2646 }
2647
2648 input->filter.match_flags |=
2649 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2650 ether_addr_copy(input->filter.src_addr, match.key->src);
2651 }
2652 }
2653
2654 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2655 struct flow_match_basic match;
2656
2657 flow_rule_match_basic(rule, &match);
2658 if (match.mask->n_proto) {
2659 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2660 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2661 return -EINVAL;
2662 }
2663
2664 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2665 input->filter.etype = match.key->n_proto;
2666 }
2667 }
2668
2669 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2670 struct flow_match_vlan match;
2671
2672 flow_rule_match_vlan(rule, &match);
2673 if (match.mask->vlan_priority) {
2674 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2675 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2676 return -EINVAL;
2677 }
2678
2679 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2680 input->filter.vlan_tci =
2681 (__force __be16)match.key->vlan_priority;
2682 }
2683 }
2684
2685 input->action = traffic_class;
2686 input->cookie = f->cookie;
2687
2688 return 0;
2689 }
2690
igb_configure_clsflower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2691 static int igb_configure_clsflower(struct igb_adapter *adapter,
2692 struct flow_cls_offload *cls_flower)
2693 {
2694 struct netlink_ext_ack *extack = cls_flower->common.extack;
2695 struct igb_nfc_filter *filter, *f;
2696 int err, tc;
2697
2698 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2699 if (tc < 0) {
2700 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2701 return -EINVAL;
2702 }
2703
2704 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2705 if (!filter)
2706 return -ENOMEM;
2707
2708 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2709 if (err < 0)
2710 goto err_parse;
2711
2712 spin_lock(&adapter->nfc_lock);
2713
2714 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2715 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2716 err = -EEXIST;
2717 NL_SET_ERR_MSG_MOD(extack,
2718 "This filter is already set in ethtool");
2719 goto err_locked;
2720 }
2721 }
2722
2723 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2724 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2725 err = -EEXIST;
2726 NL_SET_ERR_MSG_MOD(extack,
2727 "This filter is already set in cls_flower");
2728 goto err_locked;
2729 }
2730 }
2731
2732 err = igb_add_filter(adapter, filter);
2733 if (err < 0) {
2734 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2735 goto err_locked;
2736 }
2737
2738 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2739
2740 spin_unlock(&adapter->nfc_lock);
2741
2742 return 0;
2743
2744 err_locked:
2745 spin_unlock(&adapter->nfc_lock);
2746
2747 err_parse:
2748 kfree(filter);
2749
2750 return err;
2751 }
2752
igb_delete_clsflower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2753 static int igb_delete_clsflower(struct igb_adapter *adapter,
2754 struct flow_cls_offload *cls_flower)
2755 {
2756 struct igb_nfc_filter *filter;
2757 int err;
2758
2759 spin_lock(&adapter->nfc_lock);
2760
2761 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2762 if (filter->cookie == cls_flower->cookie)
2763 break;
2764
2765 if (!filter) {
2766 err = -ENOENT;
2767 goto out;
2768 }
2769
2770 err = igb_erase_filter(adapter, filter);
2771 if (err < 0)
2772 goto out;
2773
2774 hlist_del(&filter->nfc_node);
2775 kfree(filter);
2776
2777 out:
2778 spin_unlock(&adapter->nfc_lock);
2779
2780 return err;
2781 }
2782
igb_setup_tc_cls_flower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2783 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2784 struct flow_cls_offload *cls_flower)
2785 {
2786 switch (cls_flower->command) {
2787 case FLOW_CLS_REPLACE:
2788 return igb_configure_clsflower(adapter, cls_flower);
2789 case FLOW_CLS_DESTROY:
2790 return igb_delete_clsflower(adapter, cls_flower);
2791 case FLOW_CLS_STATS:
2792 return -EOPNOTSUPP;
2793 default:
2794 return -EOPNOTSUPP;
2795 }
2796 }
2797
igb_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2798 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2799 void *cb_priv)
2800 {
2801 struct igb_adapter *adapter = cb_priv;
2802
2803 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2804 return -EOPNOTSUPP;
2805
2806 switch (type) {
2807 case TC_SETUP_CLSFLOWER:
2808 return igb_setup_tc_cls_flower(adapter, type_data);
2809
2810 default:
2811 return -EOPNOTSUPP;
2812 }
2813 }
2814
igb_offload_txtime(struct igb_adapter * adapter,struct tc_etf_qopt_offload * qopt)2815 static int igb_offload_txtime(struct igb_adapter *adapter,
2816 struct tc_etf_qopt_offload *qopt)
2817 {
2818 struct e1000_hw *hw = &adapter->hw;
2819 int err;
2820
2821 /* Launchtime offloading is only supported by i210 controller. */
2822 if (hw->mac.type != e1000_i210)
2823 return -EOPNOTSUPP;
2824
2825 /* Launchtime offloading is only supported by queues 0 and 1. */
2826 if (qopt->queue < 0 || qopt->queue > 1)
2827 return -EINVAL;
2828
2829 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2830 if (err)
2831 return err;
2832
2833 igb_offload_apply(adapter, qopt->queue);
2834
2835 return 0;
2836 }
2837
igb_tc_query_caps(struct igb_adapter * adapter,struct tc_query_caps_base * base)2838 static int igb_tc_query_caps(struct igb_adapter *adapter,
2839 struct tc_query_caps_base *base)
2840 {
2841 switch (base->type) {
2842 case TC_SETUP_QDISC_TAPRIO: {
2843 struct tc_taprio_caps *caps = base->caps;
2844
2845 caps->broken_mqprio = true;
2846
2847 return 0;
2848 }
2849 default:
2850 return -EOPNOTSUPP;
2851 }
2852 }
2853
2854 static LIST_HEAD(igb_block_cb_list);
2855
igb_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2856 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2857 void *type_data)
2858 {
2859 struct igb_adapter *adapter = netdev_priv(dev);
2860
2861 switch (type) {
2862 case TC_QUERY_CAPS:
2863 return igb_tc_query_caps(adapter, type_data);
2864 case TC_SETUP_QDISC_CBS:
2865 return igb_offload_cbs(adapter, type_data);
2866 case TC_SETUP_BLOCK:
2867 return flow_block_cb_setup_simple(type_data,
2868 &igb_block_cb_list,
2869 igb_setup_tc_block_cb,
2870 adapter, adapter, true);
2871
2872 case TC_SETUP_QDISC_ETF:
2873 return igb_offload_txtime(adapter, type_data);
2874
2875 default:
2876 return -EOPNOTSUPP;
2877 }
2878 }
2879
igb_xdp_setup(struct net_device * dev,struct netdev_bpf * bpf)2880 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2881 {
2882 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2883 struct igb_adapter *adapter = netdev_priv(dev);
2884 struct bpf_prog *prog = bpf->prog, *old_prog;
2885 bool running = netif_running(dev);
2886 bool need_reset;
2887
2888 /* verify igb ring attributes are sufficient for XDP */
2889 for (i = 0; i < adapter->num_rx_queues; i++) {
2890 struct igb_ring *ring = adapter->rx_ring[i];
2891
2892 if (frame_size > igb_rx_bufsz(ring)) {
2893 NL_SET_ERR_MSG_MOD(bpf->extack,
2894 "The RX buffer size is too small for the frame size");
2895 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2896 igb_rx_bufsz(ring), frame_size);
2897 return -EINVAL;
2898 }
2899 }
2900
2901 old_prog = xchg(&adapter->xdp_prog, prog);
2902 need_reset = (!!prog != !!old_prog);
2903
2904 /* device is up and bpf is added/removed, must setup the RX queues */
2905 if (need_reset && running) {
2906 igb_close(dev);
2907 } else {
2908 for (i = 0; i < adapter->num_rx_queues; i++)
2909 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2910 adapter->xdp_prog);
2911 }
2912
2913 if (old_prog)
2914 bpf_prog_put(old_prog);
2915
2916 /* bpf is just replaced, RXQ and MTU are already setup */
2917 if (!need_reset) {
2918 return 0;
2919 } else {
2920 if (prog)
2921 xdp_features_set_redirect_target(dev, true);
2922 else
2923 xdp_features_clear_redirect_target(dev);
2924 }
2925
2926 if (running)
2927 igb_open(dev);
2928
2929 return 0;
2930 }
2931
igb_xdp(struct net_device * dev,struct netdev_bpf * xdp)2932 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2933 {
2934 switch (xdp->command) {
2935 case XDP_SETUP_PROG:
2936 return igb_xdp_setup(dev, xdp);
2937 default:
2938 return -EINVAL;
2939 }
2940 }
2941
igb_xdp_ring_update_tail(struct igb_ring * ring)2942 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2943 {
2944 /* Force memory writes to complete before letting h/w know there
2945 * are new descriptors to fetch.
2946 */
2947 wmb();
2948 writel(ring->next_to_use, ring->tail);
2949 }
2950
igb_xdp_tx_queue_mapping(struct igb_adapter * adapter)2951 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2952 {
2953 unsigned int r_idx = smp_processor_id();
2954
2955 if (r_idx >= adapter->num_tx_queues)
2956 r_idx = r_idx % adapter->num_tx_queues;
2957
2958 return adapter->tx_ring[r_idx];
2959 }
2960
igb_xdp_xmit_back(struct igb_adapter * adapter,struct xdp_buff * xdp)2961 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2962 {
2963 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2964 int cpu = smp_processor_id();
2965 struct igb_ring *tx_ring;
2966 struct netdev_queue *nq;
2967 u32 ret;
2968
2969 if (unlikely(!xdpf))
2970 return IGB_XDP_CONSUMED;
2971
2972 /* During program transitions its possible adapter->xdp_prog is assigned
2973 * but ring has not been configured yet. In this case simply abort xmit.
2974 */
2975 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2976 if (unlikely(!tx_ring))
2977 return IGB_XDP_CONSUMED;
2978
2979 nq = txring_txq(tx_ring);
2980 __netif_tx_lock(nq, cpu);
2981 /* Avoid transmit queue timeout since we share it with the slow path */
2982 txq_trans_cond_update(nq);
2983 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2984 __netif_tx_unlock(nq);
2985
2986 return ret;
2987 }
2988
igb_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)2989 static int igb_xdp_xmit(struct net_device *dev, int n,
2990 struct xdp_frame **frames, u32 flags)
2991 {
2992 struct igb_adapter *adapter = netdev_priv(dev);
2993 int cpu = smp_processor_id();
2994 struct igb_ring *tx_ring;
2995 struct netdev_queue *nq;
2996 int nxmit = 0;
2997 int i;
2998
2999 if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
3000 return -ENETDOWN;
3001
3002 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3003 return -EINVAL;
3004
3005 /* During program transitions its possible adapter->xdp_prog is assigned
3006 * but ring has not been configured yet. In this case simply abort xmit.
3007 */
3008 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
3009 if (unlikely(!tx_ring))
3010 return -ENXIO;
3011
3012 nq = txring_txq(tx_ring);
3013 __netif_tx_lock(nq, cpu);
3014
3015 /* Avoid transmit queue timeout since we share it with the slow path */
3016 txq_trans_cond_update(nq);
3017
3018 for (i = 0; i < n; i++) {
3019 struct xdp_frame *xdpf = frames[i];
3020 int err;
3021
3022 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
3023 if (err != IGB_XDP_TX)
3024 break;
3025 nxmit++;
3026 }
3027
3028 __netif_tx_unlock(nq);
3029
3030 if (unlikely(flags & XDP_XMIT_FLUSH))
3031 igb_xdp_ring_update_tail(tx_ring);
3032
3033 return nxmit;
3034 }
3035
3036 static const struct net_device_ops igb_netdev_ops = {
3037 .ndo_open = igb_open,
3038 .ndo_stop = igb_close,
3039 .ndo_start_xmit = igb_xmit_frame,
3040 .ndo_get_stats64 = igb_get_stats64,
3041 .ndo_set_rx_mode = igb_set_rx_mode,
3042 .ndo_set_mac_address = igb_set_mac,
3043 .ndo_change_mtu = igb_change_mtu,
3044 .ndo_eth_ioctl = igb_ioctl,
3045 .ndo_tx_timeout = igb_tx_timeout,
3046 .ndo_validate_addr = eth_validate_addr,
3047 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
3048 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
3049 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
3050 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
3051 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
3052 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
3053 .ndo_set_vf_trust = igb_ndo_set_vf_trust,
3054 .ndo_get_vf_config = igb_ndo_get_vf_config,
3055 .ndo_fix_features = igb_fix_features,
3056 .ndo_set_features = igb_set_features,
3057 .ndo_fdb_add = igb_ndo_fdb_add,
3058 .ndo_features_check = igb_features_check,
3059 .ndo_setup_tc = igb_setup_tc,
3060 .ndo_bpf = igb_xdp,
3061 .ndo_xdp_xmit = igb_xdp_xmit,
3062 };
3063
3064 /**
3065 * igb_set_fw_version - Configure version string for ethtool
3066 * @adapter: adapter struct
3067 **/
igb_set_fw_version(struct igb_adapter * adapter)3068 void igb_set_fw_version(struct igb_adapter *adapter)
3069 {
3070 struct e1000_hw *hw = &adapter->hw;
3071 struct e1000_fw_version fw;
3072
3073 igb_get_fw_version(hw, &fw);
3074
3075 switch (hw->mac.type) {
3076 case e1000_i210:
3077 case e1000_i211:
3078 if (!(igb_get_flash_presence_i210(hw))) {
3079 snprintf(adapter->fw_version,
3080 sizeof(adapter->fw_version),
3081 "%2d.%2d-%d",
3082 fw.invm_major, fw.invm_minor,
3083 fw.invm_img_type);
3084 break;
3085 }
3086 fallthrough;
3087 default:
3088 /* if option is rom valid, display its version too */
3089 if (fw.or_valid) {
3090 snprintf(adapter->fw_version,
3091 sizeof(adapter->fw_version),
3092 "%d.%d, 0x%08x, %d.%d.%d",
3093 fw.eep_major, fw.eep_minor, fw.etrack_id,
3094 fw.or_major, fw.or_build, fw.or_patch);
3095 /* no option rom */
3096 } else if (fw.etrack_id != 0X0000) {
3097 snprintf(adapter->fw_version,
3098 sizeof(adapter->fw_version),
3099 "%d.%d, 0x%08x",
3100 fw.eep_major, fw.eep_minor, fw.etrack_id);
3101 } else {
3102 snprintf(adapter->fw_version,
3103 sizeof(adapter->fw_version),
3104 "%d.%d.%d",
3105 fw.eep_major, fw.eep_minor, fw.eep_build);
3106 }
3107 break;
3108 }
3109 }
3110
3111 /**
3112 * igb_init_mas - init Media Autosense feature if enabled in the NVM
3113 *
3114 * @adapter: adapter struct
3115 **/
igb_init_mas(struct igb_adapter * adapter)3116 static void igb_init_mas(struct igb_adapter *adapter)
3117 {
3118 struct e1000_hw *hw = &adapter->hw;
3119 u16 eeprom_data;
3120
3121 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3122 switch (hw->bus.func) {
3123 case E1000_FUNC_0:
3124 if (eeprom_data & IGB_MAS_ENABLE_0) {
3125 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3126 netdev_info(adapter->netdev,
3127 "MAS: Enabling Media Autosense for port %d\n",
3128 hw->bus.func);
3129 }
3130 break;
3131 case E1000_FUNC_1:
3132 if (eeprom_data & IGB_MAS_ENABLE_1) {
3133 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3134 netdev_info(adapter->netdev,
3135 "MAS: Enabling Media Autosense for port %d\n",
3136 hw->bus.func);
3137 }
3138 break;
3139 case E1000_FUNC_2:
3140 if (eeprom_data & IGB_MAS_ENABLE_2) {
3141 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3142 netdev_info(adapter->netdev,
3143 "MAS: Enabling Media Autosense for port %d\n",
3144 hw->bus.func);
3145 }
3146 break;
3147 case E1000_FUNC_3:
3148 if (eeprom_data & IGB_MAS_ENABLE_3) {
3149 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3150 netdev_info(adapter->netdev,
3151 "MAS: Enabling Media Autosense for port %d\n",
3152 hw->bus.func);
3153 }
3154 break;
3155 default:
3156 /* Shouldn't get here */
3157 netdev_err(adapter->netdev,
3158 "MAS: Invalid port configuration, returning\n");
3159 break;
3160 }
3161 }
3162
3163 /**
3164 * igb_init_i2c - Init I2C interface
3165 * @adapter: pointer to adapter structure
3166 **/
igb_init_i2c(struct igb_adapter * adapter)3167 static s32 igb_init_i2c(struct igb_adapter *adapter)
3168 {
3169 s32 status = 0;
3170
3171 /* I2C interface supported on i350 devices */
3172 if (adapter->hw.mac.type != e1000_i350)
3173 return 0;
3174
3175 /* Initialize the i2c bus which is controlled by the registers.
3176 * This bus will use the i2c_algo_bit structure that implements
3177 * the protocol through toggling of the 4 bits in the register.
3178 */
3179 adapter->i2c_adap.owner = THIS_MODULE;
3180 adapter->i2c_algo = igb_i2c_algo;
3181 adapter->i2c_algo.data = adapter;
3182 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3183 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3184 strscpy(adapter->i2c_adap.name, "igb BB",
3185 sizeof(adapter->i2c_adap.name));
3186 status = i2c_bit_add_bus(&adapter->i2c_adap);
3187 return status;
3188 }
3189
3190 /**
3191 * igb_probe - Device Initialization Routine
3192 * @pdev: PCI device information struct
3193 * @ent: entry in igb_pci_tbl
3194 *
3195 * Returns 0 on success, negative on failure
3196 *
3197 * igb_probe initializes an adapter identified by a pci_dev structure.
3198 * The OS initialization, configuring of the adapter private structure,
3199 * and a hardware reset occur.
3200 **/
igb_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3201 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3202 {
3203 struct net_device *netdev;
3204 struct igb_adapter *adapter;
3205 struct e1000_hw *hw;
3206 u16 eeprom_data = 0;
3207 s32 ret_val;
3208 static int global_quad_port_a; /* global quad port a indication */
3209 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3210 u8 part_str[E1000_PBANUM_LENGTH];
3211 int err;
3212
3213 /* Catch broken hardware that put the wrong VF device ID in
3214 * the PCIe SR-IOV capability.
3215 */
3216 if (pdev->is_virtfn) {
3217 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3218 pci_name(pdev), pdev->vendor, pdev->device);
3219 return -EINVAL;
3220 }
3221
3222 err = pci_enable_device_mem(pdev);
3223 if (err)
3224 return err;
3225
3226 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3227 if (err) {
3228 dev_err(&pdev->dev,
3229 "No usable DMA configuration, aborting\n");
3230 goto err_dma;
3231 }
3232
3233 err = pci_request_mem_regions(pdev, igb_driver_name);
3234 if (err)
3235 goto err_pci_reg;
3236
3237 pci_set_master(pdev);
3238 pci_save_state(pdev);
3239
3240 err = -ENOMEM;
3241 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3242 IGB_MAX_TX_QUEUES);
3243 if (!netdev)
3244 goto err_alloc_etherdev;
3245
3246 SET_NETDEV_DEV(netdev, &pdev->dev);
3247
3248 pci_set_drvdata(pdev, netdev);
3249 adapter = netdev_priv(netdev);
3250 adapter->netdev = netdev;
3251 adapter->pdev = pdev;
3252 hw = &adapter->hw;
3253 hw->back = adapter;
3254 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3255
3256 err = -EIO;
3257 adapter->io_addr = pci_iomap(pdev, 0, 0);
3258 if (!adapter->io_addr)
3259 goto err_ioremap;
3260 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3261 hw->hw_addr = adapter->io_addr;
3262
3263 netdev->netdev_ops = &igb_netdev_ops;
3264 igb_set_ethtool_ops(netdev);
3265 netdev->watchdog_timeo = 5 * HZ;
3266
3267 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3268
3269 netdev->mem_start = pci_resource_start(pdev, 0);
3270 netdev->mem_end = pci_resource_end(pdev, 0);
3271
3272 /* PCI config space info */
3273 hw->vendor_id = pdev->vendor;
3274 hw->device_id = pdev->device;
3275 hw->revision_id = pdev->revision;
3276 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3277 hw->subsystem_device_id = pdev->subsystem_device;
3278
3279 /* Copy the default MAC, PHY and NVM function pointers */
3280 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3281 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3282 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3283 /* Initialize skew-specific constants */
3284 err = ei->get_invariants(hw);
3285 if (err)
3286 goto err_sw_init;
3287
3288 /* setup the private structure */
3289 err = igb_sw_init(adapter);
3290 if (err)
3291 goto err_sw_init;
3292
3293 igb_get_bus_info_pcie(hw);
3294
3295 hw->phy.autoneg_wait_to_complete = false;
3296
3297 /* Copper options */
3298 if (hw->phy.media_type == e1000_media_type_copper) {
3299 hw->phy.mdix = AUTO_ALL_MODES;
3300 hw->phy.disable_polarity_correction = false;
3301 hw->phy.ms_type = e1000_ms_hw_default;
3302 }
3303
3304 if (igb_check_reset_block(hw))
3305 dev_info(&pdev->dev,
3306 "PHY reset is blocked due to SOL/IDER session.\n");
3307
3308 /* features is initialized to 0 in allocation, it might have bits
3309 * set by igb_sw_init so we should use an or instead of an
3310 * assignment.
3311 */
3312 netdev->features |= NETIF_F_SG |
3313 NETIF_F_TSO |
3314 NETIF_F_TSO6 |
3315 NETIF_F_RXHASH |
3316 NETIF_F_RXCSUM |
3317 NETIF_F_HW_CSUM;
3318
3319 if (hw->mac.type >= e1000_82576)
3320 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3321
3322 if (hw->mac.type >= e1000_i350)
3323 netdev->features |= NETIF_F_HW_TC;
3324
3325 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3326 NETIF_F_GSO_GRE_CSUM | \
3327 NETIF_F_GSO_IPXIP4 | \
3328 NETIF_F_GSO_IPXIP6 | \
3329 NETIF_F_GSO_UDP_TUNNEL | \
3330 NETIF_F_GSO_UDP_TUNNEL_CSUM)
3331
3332 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3333 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3334
3335 /* copy netdev features into list of user selectable features */
3336 netdev->hw_features |= netdev->features |
3337 NETIF_F_HW_VLAN_CTAG_RX |
3338 NETIF_F_HW_VLAN_CTAG_TX |
3339 NETIF_F_RXALL;
3340
3341 if (hw->mac.type >= e1000_i350)
3342 netdev->hw_features |= NETIF_F_NTUPLE;
3343
3344 netdev->features |= NETIF_F_HIGHDMA;
3345
3346 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3347 netdev->mpls_features |= NETIF_F_HW_CSUM;
3348 netdev->hw_enc_features |= netdev->vlan_features;
3349
3350 /* set this bit last since it cannot be part of vlan_features */
3351 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3352 NETIF_F_HW_VLAN_CTAG_RX |
3353 NETIF_F_HW_VLAN_CTAG_TX;
3354
3355 netdev->priv_flags |= IFF_SUPP_NOFCS;
3356
3357 netdev->priv_flags |= IFF_UNICAST_FLT;
3358 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT;
3359
3360 /* MTU range: 68 - 9216 */
3361 netdev->min_mtu = ETH_MIN_MTU;
3362 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3363
3364 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3365
3366 /* before reading the NVM, reset the controller to put the device in a
3367 * known good starting state
3368 */
3369 hw->mac.ops.reset_hw(hw);
3370
3371 /* make sure the NVM is good , i211/i210 parts can have special NVM
3372 * that doesn't contain a checksum
3373 */
3374 switch (hw->mac.type) {
3375 case e1000_i210:
3376 case e1000_i211:
3377 if (igb_get_flash_presence_i210(hw)) {
3378 if (hw->nvm.ops.validate(hw) < 0) {
3379 dev_err(&pdev->dev,
3380 "The NVM Checksum Is Not Valid\n");
3381 err = -EIO;
3382 goto err_eeprom;
3383 }
3384 }
3385 break;
3386 default:
3387 if (hw->nvm.ops.validate(hw) < 0) {
3388 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3389 err = -EIO;
3390 goto err_eeprom;
3391 }
3392 break;
3393 }
3394
3395 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3396 /* copy the MAC address out of the NVM */
3397 if (hw->mac.ops.read_mac_addr(hw))
3398 dev_err(&pdev->dev, "NVM Read Error\n");
3399 }
3400
3401 eth_hw_addr_set(netdev, hw->mac.addr);
3402
3403 if (!is_valid_ether_addr(netdev->dev_addr)) {
3404 dev_err(&pdev->dev, "Invalid MAC Address\n");
3405 err = -EIO;
3406 goto err_eeprom;
3407 }
3408
3409 igb_set_default_mac_filter(adapter);
3410
3411 /* get firmware version for ethtool -i */
3412 igb_set_fw_version(adapter);
3413
3414 /* configure RXPBSIZE and TXPBSIZE */
3415 if (hw->mac.type == e1000_i210) {
3416 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3417 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3418 }
3419
3420 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3421 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3422
3423 INIT_WORK(&adapter->reset_task, igb_reset_task);
3424 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3425
3426 /* Initialize link properties that are user-changeable */
3427 adapter->fc_autoneg = true;
3428 hw->mac.autoneg = true;
3429 hw->phy.autoneg_advertised = 0x2f;
3430
3431 hw->fc.requested_mode = e1000_fc_default;
3432 hw->fc.current_mode = e1000_fc_default;
3433
3434 igb_validate_mdi_setting(hw);
3435
3436 /* By default, support wake on port A */
3437 if (hw->bus.func == 0)
3438 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3439
3440 /* Check the NVM for wake support on non-port A ports */
3441 if (hw->mac.type >= e1000_82580)
3442 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3443 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3444 &eeprom_data);
3445 else if (hw->bus.func == 1)
3446 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3447
3448 if (eeprom_data & IGB_EEPROM_APME)
3449 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3450
3451 /* now that we have the eeprom settings, apply the special cases where
3452 * the eeprom may be wrong or the board simply won't support wake on
3453 * lan on a particular port
3454 */
3455 switch (pdev->device) {
3456 case E1000_DEV_ID_82575GB_QUAD_COPPER:
3457 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3458 break;
3459 case E1000_DEV_ID_82575EB_FIBER_SERDES:
3460 case E1000_DEV_ID_82576_FIBER:
3461 case E1000_DEV_ID_82576_SERDES:
3462 /* Wake events only supported on port A for dual fiber
3463 * regardless of eeprom setting
3464 */
3465 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3466 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3467 break;
3468 case E1000_DEV_ID_82576_QUAD_COPPER:
3469 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3470 /* if quad port adapter, disable WoL on all but port A */
3471 if (global_quad_port_a != 0)
3472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3473 else
3474 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3475 /* Reset for multiple quad port adapters */
3476 if (++global_quad_port_a == 4)
3477 global_quad_port_a = 0;
3478 break;
3479 default:
3480 /* If the device can't wake, don't set software support */
3481 if (!device_can_wakeup(&adapter->pdev->dev))
3482 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3483 }
3484
3485 /* initialize the wol settings based on the eeprom settings */
3486 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3487 adapter->wol |= E1000_WUFC_MAG;
3488
3489 /* Some vendors want WoL disabled by default, but still supported */
3490 if ((hw->mac.type == e1000_i350) &&
3491 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3492 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3493 adapter->wol = 0;
3494 }
3495
3496 /* Some vendors want the ability to Use the EEPROM setting as
3497 * enable/disable only, and not for capability
3498 */
3499 if (((hw->mac.type == e1000_i350) ||
3500 (hw->mac.type == e1000_i354)) &&
3501 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3502 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3503 adapter->wol = 0;
3504 }
3505 if (hw->mac.type == e1000_i350) {
3506 if (((pdev->subsystem_device == 0x5001) ||
3507 (pdev->subsystem_device == 0x5002)) &&
3508 (hw->bus.func == 0)) {
3509 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3510 adapter->wol = 0;
3511 }
3512 if (pdev->subsystem_device == 0x1F52)
3513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3514 }
3515
3516 device_set_wakeup_enable(&adapter->pdev->dev,
3517 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3518
3519 /* reset the hardware with the new settings */
3520 igb_reset(adapter);
3521
3522 /* Init the I2C interface */
3523 err = igb_init_i2c(adapter);
3524 if (err) {
3525 dev_err(&pdev->dev, "failed to init i2c interface\n");
3526 goto err_eeprom;
3527 }
3528
3529 /* let the f/w know that the h/w is now under the control of the
3530 * driver.
3531 */
3532 igb_get_hw_control(adapter);
3533
3534 strcpy(netdev->name, "eth%d");
3535 err = register_netdev(netdev);
3536 if (err)
3537 goto err_register;
3538
3539 /* carrier off reporting is important to ethtool even BEFORE open */
3540 netif_carrier_off(netdev);
3541
3542 #ifdef CONFIG_IGB_DCA
3543 if (dca_add_requester(&pdev->dev) == 0) {
3544 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3545 dev_info(&pdev->dev, "DCA enabled\n");
3546 igb_setup_dca(adapter);
3547 }
3548
3549 #endif
3550 #ifdef CONFIG_IGB_HWMON
3551 /* Initialize the thermal sensor on i350 devices. */
3552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3553 u16 ets_word;
3554
3555 /* Read the NVM to determine if this i350 device supports an
3556 * external thermal sensor.
3557 */
3558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3559 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3560 adapter->ets = true;
3561 else
3562 adapter->ets = false;
3563 /* Only enable I2C bit banging if an external thermal
3564 * sensor is supported.
3565 */
3566 if (adapter->ets)
3567 igb_set_i2c_bb(hw);
3568 hw->mac.ops.init_thermal_sensor_thresh(hw);
3569 if (igb_sysfs_init(adapter))
3570 dev_err(&pdev->dev,
3571 "failed to allocate sysfs resources\n");
3572 } else {
3573 adapter->ets = false;
3574 }
3575 #endif
3576 /* Check if Media Autosense is enabled */
3577 adapter->ei = *ei;
3578 if (hw->dev_spec._82575.mas_capable)
3579 igb_init_mas(adapter);
3580
3581 /* do hw tstamp init after resetting */
3582 igb_ptp_init(adapter);
3583
3584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3585 /* print bus type/speed/width info, not applicable to i354 */
3586 if (hw->mac.type != e1000_i354) {
3587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3588 netdev->name,
3589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3591 "unknown"),
3592 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3593 "Width x4" :
3594 (hw->bus.width == e1000_bus_width_pcie_x2) ?
3595 "Width x2" :
3596 (hw->bus.width == e1000_bus_width_pcie_x1) ?
3597 "Width x1" : "unknown"), netdev->dev_addr);
3598 }
3599
3600 if ((hw->mac.type == e1000_82576 &&
3601 rd32(E1000_EECD) & E1000_EECD_PRES) ||
3602 (hw->mac.type >= e1000_i210 ||
3603 igb_get_flash_presence_i210(hw))) {
3604 ret_val = igb_read_part_string(hw, part_str,
3605 E1000_PBANUM_LENGTH);
3606 } else {
3607 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3608 }
3609
3610 if (ret_val)
3611 strcpy(part_str, "Unknown");
3612 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3613 dev_info(&pdev->dev,
3614 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3615 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3616 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3617 adapter->num_rx_queues, adapter->num_tx_queues);
3618 if (hw->phy.media_type == e1000_media_type_copper) {
3619 switch (hw->mac.type) {
3620 case e1000_i350:
3621 case e1000_i210:
3622 case e1000_i211:
3623 /* Enable EEE for internal copper PHY devices */
3624 err = igb_set_eee_i350(hw, true, true);
3625 if ((!err) &&
3626 (!hw->dev_spec._82575.eee_disable)) {
3627 adapter->eee_advert =
3628 MDIO_EEE_100TX | MDIO_EEE_1000T;
3629 adapter->flags |= IGB_FLAG_EEE;
3630 }
3631 break;
3632 case e1000_i354:
3633 if ((rd32(E1000_CTRL_EXT) &
3634 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3635 err = igb_set_eee_i354(hw, true, true);
3636 if ((!err) &&
3637 (!hw->dev_spec._82575.eee_disable)) {
3638 adapter->eee_advert =
3639 MDIO_EEE_100TX | MDIO_EEE_1000T;
3640 adapter->flags |= IGB_FLAG_EEE;
3641 }
3642 }
3643 break;
3644 default:
3645 break;
3646 }
3647 }
3648
3649 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3650
3651 pm_runtime_put_noidle(&pdev->dev);
3652 return 0;
3653
3654 err_register:
3655 igb_release_hw_control(adapter);
3656 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3657 err_eeprom:
3658 if (!igb_check_reset_block(hw))
3659 igb_reset_phy(hw);
3660
3661 if (hw->flash_address)
3662 iounmap(hw->flash_address);
3663 err_sw_init:
3664 kfree(adapter->mac_table);
3665 kfree(adapter->shadow_vfta);
3666 igb_clear_interrupt_scheme(adapter);
3667 #ifdef CONFIG_PCI_IOV
3668 igb_disable_sriov(pdev, false);
3669 #endif
3670 pci_iounmap(pdev, adapter->io_addr);
3671 err_ioremap:
3672 free_netdev(netdev);
3673 err_alloc_etherdev:
3674 pci_release_mem_regions(pdev);
3675 err_pci_reg:
3676 err_dma:
3677 pci_disable_device(pdev);
3678 return err;
3679 }
3680
3681 #ifdef CONFIG_PCI_IOV
igb_sriov_reinit(struct pci_dev * dev)3682 static int igb_sriov_reinit(struct pci_dev *dev)
3683 {
3684 struct net_device *netdev = pci_get_drvdata(dev);
3685 struct igb_adapter *adapter = netdev_priv(netdev);
3686 struct pci_dev *pdev = adapter->pdev;
3687
3688 rtnl_lock();
3689
3690 if (netif_running(netdev))
3691 igb_close(netdev);
3692 else
3693 igb_reset(adapter);
3694
3695 igb_clear_interrupt_scheme(adapter);
3696
3697 igb_init_queue_configuration(adapter);
3698
3699 if (igb_init_interrupt_scheme(adapter, true)) {
3700 rtnl_unlock();
3701 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3702 return -ENOMEM;
3703 }
3704
3705 if (netif_running(netdev))
3706 igb_open(netdev);
3707
3708 rtnl_unlock();
3709
3710 return 0;
3711 }
3712
igb_disable_sriov(struct pci_dev * pdev,bool reinit)3713 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit)
3714 {
3715 struct net_device *netdev = pci_get_drvdata(pdev);
3716 struct igb_adapter *adapter = netdev_priv(netdev);
3717 struct e1000_hw *hw = &adapter->hw;
3718 unsigned long flags;
3719
3720 /* reclaim resources allocated to VFs */
3721 if (adapter->vf_data) {
3722 /* disable iov and allow time for transactions to clear */
3723 if (pci_vfs_assigned(pdev)) {
3724 dev_warn(&pdev->dev,
3725 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3726 return -EPERM;
3727 } else {
3728 pci_disable_sriov(pdev);
3729 msleep(500);
3730 }
3731 spin_lock_irqsave(&adapter->vfs_lock, flags);
3732 kfree(adapter->vf_mac_list);
3733 adapter->vf_mac_list = NULL;
3734 kfree(adapter->vf_data);
3735 adapter->vf_data = NULL;
3736 adapter->vfs_allocated_count = 0;
3737 spin_unlock_irqrestore(&adapter->vfs_lock, flags);
3738 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3739 wrfl();
3740 msleep(100);
3741 dev_info(&pdev->dev, "IOV Disabled\n");
3742
3743 /* Re-enable DMA Coalescing flag since IOV is turned off */
3744 adapter->flags |= IGB_FLAG_DMAC;
3745 }
3746
3747 return reinit ? igb_sriov_reinit(pdev) : 0;
3748 }
3749
igb_enable_sriov(struct pci_dev * pdev,int num_vfs,bool reinit)3750 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit)
3751 {
3752 struct net_device *netdev = pci_get_drvdata(pdev);
3753 struct igb_adapter *adapter = netdev_priv(netdev);
3754 int old_vfs = pci_num_vf(pdev);
3755 struct vf_mac_filter *mac_list;
3756 int err = 0;
3757 int num_vf_mac_filters, i;
3758
3759 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3760 err = -EPERM;
3761 goto out;
3762 }
3763 if (!num_vfs)
3764 goto out;
3765
3766 if (old_vfs) {
3767 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3768 old_vfs, max_vfs);
3769 adapter->vfs_allocated_count = old_vfs;
3770 } else
3771 adapter->vfs_allocated_count = num_vfs;
3772
3773 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3774 sizeof(struct vf_data_storage), GFP_KERNEL);
3775
3776 /* if allocation failed then we do not support SR-IOV */
3777 if (!adapter->vf_data) {
3778 adapter->vfs_allocated_count = 0;
3779 err = -ENOMEM;
3780 goto out;
3781 }
3782
3783 /* Due to the limited number of RAR entries calculate potential
3784 * number of MAC filters available for the VFs. Reserve entries
3785 * for PF default MAC, PF MAC filters and at least one RAR entry
3786 * for each VF for VF MAC.
3787 */
3788 num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3789 (1 + IGB_PF_MAC_FILTERS_RESERVED +
3790 adapter->vfs_allocated_count);
3791
3792 adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3793 sizeof(struct vf_mac_filter),
3794 GFP_KERNEL);
3795
3796 mac_list = adapter->vf_mac_list;
3797 INIT_LIST_HEAD(&adapter->vf_macs.l);
3798
3799 if (adapter->vf_mac_list) {
3800 /* Initialize list of VF MAC filters */
3801 for (i = 0; i < num_vf_mac_filters; i++) {
3802 mac_list->vf = -1;
3803 mac_list->free = true;
3804 list_add(&mac_list->l, &adapter->vf_macs.l);
3805 mac_list++;
3806 }
3807 } else {
3808 /* If we could not allocate memory for the VF MAC filters
3809 * we can continue without this feature but warn user.
3810 */
3811 dev_err(&pdev->dev,
3812 "Unable to allocate memory for VF MAC filter list\n");
3813 }
3814
3815 dev_info(&pdev->dev, "%d VFs allocated\n",
3816 adapter->vfs_allocated_count);
3817 for (i = 0; i < adapter->vfs_allocated_count; i++)
3818 igb_vf_configure(adapter, i);
3819
3820 /* DMA Coalescing is not supported in IOV mode. */
3821 adapter->flags &= ~IGB_FLAG_DMAC;
3822
3823 if (reinit) {
3824 err = igb_sriov_reinit(pdev);
3825 if (err)
3826 goto err_out;
3827 }
3828
3829 /* only call pci_enable_sriov() if no VFs are allocated already */
3830 if (!old_vfs) {
3831 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3832 if (err)
3833 goto err_out;
3834 }
3835
3836 goto out;
3837
3838 err_out:
3839 kfree(adapter->vf_mac_list);
3840 adapter->vf_mac_list = NULL;
3841 kfree(adapter->vf_data);
3842 adapter->vf_data = NULL;
3843 adapter->vfs_allocated_count = 0;
3844 out:
3845 return err;
3846 }
3847
3848 #endif
3849 /**
3850 * igb_remove_i2c - Cleanup I2C interface
3851 * @adapter: pointer to adapter structure
3852 **/
igb_remove_i2c(struct igb_adapter * adapter)3853 static void igb_remove_i2c(struct igb_adapter *adapter)
3854 {
3855 /* free the adapter bus structure */
3856 i2c_del_adapter(&adapter->i2c_adap);
3857 }
3858
3859 /**
3860 * igb_remove - Device Removal Routine
3861 * @pdev: PCI device information struct
3862 *
3863 * igb_remove is called by the PCI subsystem to alert the driver
3864 * that it should release a PCI device. The could be caused by a
3865 * Hot-Plug event, or because the driver is going to be removed from
3866 * memory.
3867 **/
igb_remove(struct pci_dev * pdev)3868 static void igb_remove(struct pci_dev *pdev)
3869 {
3870 struct net_device *netdev = pci_get_drvdata(pdev);
3871 struct igb_adapter *adapter = netdev_priv(netdev);
3872 struct e1000_hw *hw = &adapter->hw;
3873
3874 pm_runtime_get_noresume(&pdev->dev);
3875 #ifdef CONFIG_IGB_HWMON
3876 igb_sysfs_exit(adapter);
3877 #endif
3878 igb_remove_i2c(adapter);
3879 igb_ptp_stop(adapter);
3880 /* The watchdog timer may be rescheduled, so explicitly
3881 * disable watchdog from being rescheduled.
3882 */
3883 set_bit(__IGB_DOWN, &adapter->state);
3884 del_timer_sync(&adapter->watchdog_timer);
3885 del_timer_sync(&adapter->phy_info_timer);
3886
3887 cancel_work_sync(&adapter->reset_task);
3888 cancel_work_sync(&adapter->watchdog_task);
3889
3890 #ifdef CONFIG_IGB_DCA
3891 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3892 dev_info(&pdev->dev, "DCA disabled\n");
3893 dca_remove_requester(&pdev->dev);
3894 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3895 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3896 }
3897 #endif
3898
3899 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3900 * would have already happened in close and is redundant.
3901 */
3902 igb_release_hw_control(adapter);
3903
3904 #ifdef CONFIG_PCI_IOV
3905 igb_disable_sriov(pdev, false);
3906 #endif
3907
3908 unregister_netdev(netdev);
3909
3910 igb_clear_interrupt_scheme(adapter);
3911
3912 pci_iounmap(pdev, adapter->io_addr);
3913 if (hw->flash_address)
3914 iounmap(hw->flash_address);
3915 pci_release_mem_regions(pdev);
3916
3917 kfree(adapter->mac_table);
3918 kfree(adapter->shadow_vfta);
3919 free_netdev(netdev);
3920
3921 pci_disable_device(pdev);
3922 }
3923
3924 /**
3925 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3926 * @adapter: board private structure to initialize
3927 *
3928 * This function initializes the vf specific data storage and then attempts to
3929 * allocate the VFs. The reason for ordering it this way is because it is much
3930 * mor expensive time wise to disable SR-IOV than it is to allocate and free
3931 * the memory for the VFs.
3932 **/
igb_probe_vfs(struct igb_adapter * adapter)3933 static void igb_probe_vfs(struct igb_adapter *adapter)
3934 {
3935 #ifdef CONFIG_PCI_IOV
3936 struct pci_dev *pdev = adapter->pdev;
3937 struct e1000_hw *hw = &adapter->hw;
3938
3939 /* Virtualization features not supported on i210 and 82580 family. */
3940 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) ||
3941 (hw->mac.type == e1000_82580))
3942 return;
3943
3944 /* Of the below we really only want the effect of getting
3945 * IGB_FLAG_HAS_MSIX set (if available), without which
3946 * igb_enable_sriov() has no effect.
3947 */
3948 igb_set_interrupt_capability(adapter, true);
3949 igb_reset_interrupt_capability(adapter);
3950
3951 pci_sriov_set_totalvfs(pdev, 7);
3952 igb_enable_sriov(pdev, max_vfs, false);
3953
3954 #endif /* CONFIG_PCI_IOV */
3955 }
3956
igb_get_max_rss_queues(struct igb_adapter * adapter)3957 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3958 {
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int max_rss_queues;
3961
3962 /* Determine the maximum number of RSS queues supported. */
3963 switch (hw->mac.type) {
3964 case e1000_i211:
3965 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3966 break;
3967 case e1000_82575:
3968 case e1000_i210:
3969 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3970 break;
3971 case e1000_i350:
3972 /* I350 cannot do RSS and SR-IOV at the same time */
3973 if (!!adapter->vfs_allocated_count) {
3974 max_rss_queues = 1;
3975 break;
3976 }
3977 fallthrough;
3978 case e1000_82576:
3979 if (!!adapter->vfs_allocated_count) {
3980 max_rss_queues = 2;
3981 break;
3982 }
3983 fallthrough;
3984 case e1000_82580:
3985 case e1000_i354:
3986 default:
3987 max_rss_queues = IGB_MAX_RX_QUEUES;
3988 break;
3989 }
3990
3991 return max_rss_queues;
3992 }
3993
igb_init_queue_configuration(struct igb_adapter * adapter)3994 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3995 {
3996 u32 max_rss_queues;
3997
3998 max_rss_queues = igb_get_max_rss_queues(adapter);
3999 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
4000
4001 igb_set_flag_queue_pairs(adapter, max_rss_queues);
4002 }
4003
igb_set_flag_queue_pairs(struct igb_adapter * adapter,const u32 max_rss_queues)4004 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
4005 const u32 max_rss_queues)
4006 {
4007 struct e1000_hw *hw = &adapter->hw;
4008
4009 /* Determine if we need to pair queues. */
4010 switch (hw->mac.type) {
4011 case e1000_82575:
4012 case e1000_i211:
4013 /* Device supports enough interrupts without queue pairing. */
4014 break;
4015 case e1000_82576:
4016 case e1000_82580:
4017 case e1000_i350:
4018 case e1000_i354:
4019 case e1000_i210:
4020 default:
4021 /* If rss_queues > half of max_rss_queues, pair the queues in
4022 * order to conserve interrupts due to limited supply.
4023 */
4024 if (adapter->rss_queues > (max_rss_queues / 2))
4025 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
4026 else
4027 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
4028 break;
4029 }
4030 }
4031
4032 /**
4033 * igb_sw_init - Initialize general software structures (struct igb_adapter)
4034 * @adapter: board private structure to initialize
4035 *
4036 * igb_sw_init initializes the Adapter private data structure.
4037 * Fields are initialized based on PCI device information and
4038 * OS network device settings (MTU size).
4039 **/
igb_sw_init(struct igb_adapter * adapter)4040 static int igb_sw_init(struct igb_adapter *adapter)
4041 {
4042 struct e1000_hw *hw = &adapter->hw;
4043 struct net_device *netdev = adapter->netdev;
4044 struct pci_dev *pdev = adapter->pdev;
4045
4046 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
4047
4048 /* set default ring sizes */
4049 adapter->tx_ring_count = IGB_DEFAULT_TXD;
4050 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4051
4052 /* set default ITR values */
4053 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
4054 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
4055
4056 /* set default work limits */
4057 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
4058
4059 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
4060 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4061
4062 spin_lock_init(&adapter->nfc_lock);
4063 spin_lock_init(&adapter->stats64_lock);
4064
4065 /* init spinlock to avoid concurrency of VF resources */
4066 spin_lock_init(&adapter->vfs_lock);
4067 #ifdef CONFIG_PCI_IOV
4068 switch (hw->mac.type) {
4069 case e1000_82576:
4070 case e1000_i350:
4071 if (max_vfs > 7) {
4072 dev_warn(&pdev->dev,
4073 "Maximum of 7 VFs per PF, using max\n");
4074 max_vfs = adapter->vfs_allocated_count = 7;
4075 } else
4076 adapter->vfs_allocated_count = max_vfs;
4077 if (adapter->vfs_allocated_count)
4078 dev_warn(&pdev->dev,
4079 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
4080 break;
4081 default:
4082 break;
4083 }
4084 #endif /* CONFIG_PCI_IOV */
4085
4086 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
4087 adapter->flags |= IGB_FLAG_HAS_MSIX;
4088
4089 adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4090 sizeof(struct igb_mac_addr),
4091 GFP_KERNEL);
4092 if (!adapter->mac_table)
4093 return -ENOMEM;
4094
4095 igb_probe_vfs(adapter);
4096
4097 igb_init_queue_configuration(adapter);
4098
4099 /* Setup and initialize a copy of the hw vlan table array */
4100 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4101 GFP_KERNEL);
4102 if (!adapter->shadow_vfta)
4103 return -ENOMEM;
4104
4105 /* This call may decrease the number of queues */
4106 if (igb_init_interrupt_scheme(adapter, true)) {
4107 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4108 return -ENOMEM;
4109 }
4110
4111 /* Explicitly disable IRQ since the NIC can be in any state. */
4112 igb_irq_disable(adapter);
4113
4114 if (hw->mac.type >= e1000_i350)
4115 adapter->flags &= ~IGB_FLAG_DMAC;
4116
4117 set_bit(__IGB_DOWN, &adapter->state);
4118 return 0;
4119 }
4120
4121 /**
4122 * __igb_open - Called when a network interface is made active
4123 * @netdev: network interface device structure
4124 * @resuming: indicates whether we are in a resume call
4125 *
4126 * Returns 0 on success, negative value on failure
4127 *
4128 * The open entry point is called when a network interface is made
4129 * active by the system (IFF_UP). At this point all resources needed
4130 * for transmit and receive operations are allocated, the interrupt
4131 * handler is registered with the OS, the watchdog timer is started,
4132 * and the stack is notified that the interface is ready.
4133 **/
__igb_open(struct net_device * netdev,bool resuming)4134 static int __igb_open(struct net_device *netdev, bool resuming)
4135 {
4136 struct igb_adapter *adapter = netdev_priv(netdev);
4137 struct e1000_hw *hw = &adapter->hw;
4138 struct pci_dev *pdev = adapter->pdev;
4139 int err;
4140 int i;
4141
4142 /* disallow open during test */
4143 if (test_bit(__IGB_TESTING, &adapter->state)) {
4144 WARN_ON(resuming);
4145 return -EBUSY;
4146 }
4147
4148 if (!resuming)
4149 pm_runtime_get_sync(&pdev->dev);
4150
4151 netif_carrier_off(netdev);
4152
4153 /* allocate transmit descriptors */
4154 err = igb_setup_all_tx_resources(adapter);
4155 if (err)
4156 goto err_setup_tx;
4157
4158 /* allocate receive descriptors */
4159 err = igb_setup_all_rx_resources(adapter);
4160 if (err)
4161 goto err_setup_rx;
4162
4163 igb_power_up_link(adapter);
4164
4165 /* before we allocate an interrupt, we must be ready to handle it.
4166 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4167 * as soon as we call pci_request_irq, so we have to setup our
4168 * clean_rx handler before we do so.
4169 */
4170 igb_configure(adapter);
4171
4172 err = igb_request_irq(adapter);
4173 if (err)
4174 goto err_req_irq;
4175
4176 /* Notify the stack of the actual queue counts. */
4177 err = netif_set_real_num_tx_queues(adapter->netdev,
4178 adapter->num_tx_queues);
4179 if (err)
4180 goto err_set_queues;
4181
4182 err = netif_set_real_num_rx_queues(adapter->netdev,
4183 adapter->num_rx_queues);
4184 if (err)
4185 goto err_set_queues;
4186
4187 /* From here on the code is the same as igb_up() */
4188 clear_bit(__IGB_DOWN, &adapter->state);
4189
4190 for (i = 0; i < adapter->num_q_vectors; i++)
4191 napi_enable(&(adapter->q_vector[i]->napi));
4192
4193 /* Clear any pending interrupts. */
4194 rd32(E1000_TSICR);
4195 rd32(E1000_ICR);
4196
4197 igb_irq_enable(adapter);
4198
4199 /* notify VFs that reset has been completed */
4200 if (adapter->vfs_allocated_count) {
4201 u32 reg_data = rd32(E1000_CTRL_EXT);
4202
4203 reg_data |= E1000_CTRL_EXT_PFRSTD;
4204 wr32(E1000_CTRL_EXT, reg_data);
4205 }
4206
4207 netif_tx_start_all_queues(netdev);
4208
4209 if (!resuming)
4210 pm_runtime_put(&pdev->dev);
4211
4212 /* start the watchdog. */
4213 hw->mac.get_link_status = 1;
4214 schedule_work(&adapter->watchdog_task);
4215
4216 return 0;
4217
4218 err_set_queues:
4219 igb_free_irq(adapter);
4220 err_req_irq:
4221 igb_release_hw_control(adapter);
4222 igb_power_down_link(adapter);
4223 igb_free_all_rx_resources(adapter);
4224 err_setup_rx:
4225 igb_free_all_tx_resources(adapter);
4226 err_setup_tx:
4227 igb_reset(adapter);
4228 if (!resuming)
4229 pm_runtime_put(&pdev->dev);
4230
4231 return err;
4232 }
4233
igb_open(struct net_device * netdev)4234 int igb_open(struct net_device *netdev)
4235 {
4236 return __igb_open(netdev, false);
4237 }
4238
4239 /**
4240 * __igb_close - Disables a network interface
4241 * @netdev: network interface device structure
4242 * @suspending: indicates we are in a suspend call
4243 *
4244 * Returns 0, this is not allowed to fail
4245 *
4246 * The close entry point is called when an interface is de-activated
4247 * by the OS. The hardware is still under the driver's control, but
4248 * needs to be disabled. A global MAC reset is issued to stop the
4249 * hardware, and all transmit and receive resources are freed.
4250 **/
__igb_close(struct net_device * netdev,bool suspending)4251 static int __igb_close(struct net_device *netdev, bool suspending)
4252 {
4253 struct igb_adapter *adapter = netdev_priv(netdev);
4254 struct pci_dev *pdev = adapter->pdev;
4255
4256 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4257
4258 if (!suspending)
4259 pm_runtime_get_sync(&pdev->dev);
4260
4261 igb_down(adapter);
4262 igb_free_irq(adapter);
4263
4264 igb_free_all_tx_resources(adapter);
4265 igb_free_all_rx_resources(adapter);
4266
4267 if (!suspending)
4268 pm_runtime_put_sync(&pdev->dev);
4269 return 0;
4270 }
4271
igb_close(struct net_device * netdev)4272 int igb_close(struct net_device *netdev)
4273 {
4274 if (netif_device_present(netdev) || netdev->dismantle)
4275 return __igb_close(netdev, false);
4276 return 0;
4277 }
4278
4279 /**
4280 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
4281 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4282 *
4283 * Return 0 on success, negative on failure
4284 **/
igb_setup_tx_resources(struct igb_ring * tx_ring)4285 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4286 {
4287 struct device *dev = tx_ring->dev;
4288 int size;
4289
4290 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4291
4292 tx_ring->tx_buffer_info = vmalloc(size);
4293 if (!tx_ring->tx_buffer_info)
4294 goto err;
4295
4296 /* round up to nearest 4K */
4297 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4298 tx_ring->size = ALIGN(tx_ring->size, 4096);
4299
4300 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4301 &tx_ring->dma, GFP_KERNEL);
4302 if (!tx_ring->desc)
4303 goto err;
4304
4305 tx_ring->next_to_use = 0;
4306 tx_ring->next_to_clean = 0;
4307
4308 return 0;
4309
4310 err:
4311 vfree(tx_ring->tx_buffer_info);
4312 tx_ring->tx_buffer_info = NULL;
4313 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4314 return -ENOMEM;
4315 }
4316
4317 /**
4318 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
4319 * (Descriptors) for all queues
4320 * @adapter: board private structure
4321 *
4322 * Return 0 on success, negative on failure
4323 **/
igb_setup_all_tx_resources(struct igb_adapter * adapter)4324 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4325 {
4326 struct pci_dev *pdev = adapter->pdev;
4327 int i, err = 0;
4328
4329 for (i = 0; i < adapter->num_tx_queues; i++) {
4330 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4331 if (err) {
4332 dev_err(&pdev->dev,
4333 "Allocation for Tx Queue %u failed\n", i);
4334 for (i--; i >= 0; i--)
4335 igb_free_tx_resources(adapter->tx_ring[i]);
4336 break;
4337 }
4338 }
4339
4340 return err;
4341 }
4342
4343 /**
4344 * igb_setup_tctl - configure the transmit control registers
4345 * @adapter: Board private structure
4346 **/
igb_setup_tctl(struct igb_adapter * adapter)4347 void igb_setup_tctl(struct igb_adapter *adapter)
4348 {
4349 struct e1000_hw *hw = &adapter->hw;
4350 u32 tctl;
4351
4352 /* disable queue 0 which is enabled by default on 82575 and 82576 */
4353 wr32(E1000_TXDCTL(0), 0);
4354
4355 /* Program the Transmit Control Register */
4356 tctl = rd32(E1000_TCTL);
4357 tctl &= ~E1000_TCTL_CT;
4358 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4359 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4360
4361 igb_config_collision_dist(hw);
4362
4363 /* Enable transmits */
4364 tctl |= E1000_TCTL_EN;
4365
4366 wr32(E1000_TCTL, tctl);
4367 }
4368
4369 /**
4370 * igb_configure_tx_ring - Configure transmit ring after Reset
4371 * @adapter: board private structure
4372 * @ring: tx ring to configure
4373 *
4374 * Configure a transmit ring after a reset.
4375 **/
igb_configure_tx_ring(struct igb_adapter * adapter,struct igb_ring * ring)4376 void igb_configure_tx_ring(struct igb_adapter *adapter,
4377 struct igb_ring *ring)
4378 {
4379 struct e1000_hw *hw = &adapter->hw;
4380 u32 txdctl = 0;
4381 u64 tdba = ring->dma;
4382 int reg_idx = ring->reg_idx;
4383
4384 wr32(E1000_TDLEN(reg_idx),
4385 ring->count * sizeof(union e1000_adv_tx_desc));
4386 wr32(E1000_TDBAL(reg_idx),
4387 tdba & 0x00000000ffffffffULL);
4388 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4389
4390 ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4391 wr32(E1000_TDH(reg_idx), 0);
4392 writel(0, ring->tail);
4393
4394 txdctl |= IGB_TX_PTHRESH;
4395 txdctl |= IGB_TX_HTHRESH << 8;
4396 txdctl |= IGB_TX_WTHRESH << 16;
4397
4398 /* reinitialize tx_buffer_info */
4399 memset(ring->tx_buffer_info, 0,
4400 sizeof(struct igb_tx_buffer) * ring->count);
4401
4402 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4403 wr32(E1000_TXDCTL(reg_idx), txdctl);
4404 }
4405
4406 /**
4407 * igb_configure_tx - Configure transmit Unit after Reset
4408 * @adapter: board private structure
4409 *
4410 * Configure the Tx unit of the MAC after a reset.
4411 **/
igb_configure_tx(struct igb_adapter * adapter)4412 static void igb_configure_tx(struct igb_adapter *adapter)
4413 {
4414 struct e1000_hw *hw = &adapter->hw;
4415 int i;
4416
4417 /* disable the queues */
4418 for (i = 0; i < adapter->num_tx_queues; i++)
4419 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4420
4421 wrfl();
4422 usleep_range(10000, 20000);
4423
4424 for (i = 0; i < adapter->num_tx_queues; i++)
4425 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4426 }
4427
4428 /**
4429 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
4430 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
4431 *
4432 * Returns 0 on success, negative on failure
4433 **/
igb_setup_rx_resources(struct igb_ring * rx_ring)4434 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4435 {
4436 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4437 struct device *dev = rx_ring->dev;
4438 int size, res;
4439
4440 /* XDP RX-queue info */
4441 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
4442 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4443 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4444 rx_ring->queue_index, 0);
4445 if (res < 0) {
4446 dev_err(dev, "Failed to register xdp_rxq index %u\n",
4447 rx_ring->queue_index);
4448 return res;
4449 }
4450
4451 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4452
4453 rx_ring->rx_buffer_info = vmalloc(size);
4454 if (!rx_ring->rx_buffer_info)
4455 goto err;
4456
4457 /* Round up to nearest 4K */
4458 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4459 rx_ring->size = ALIGN(rx_ring->size, 4096);
4460
4461 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4462 &rx_ring->dma, GFP_KERNEL);
4463 if (!rx_ring->desc)
4464 goto err;
4465
4466 rx_ring->next_to_alloc = 0;
4467 rx_ring->next_to_clean = 0;
4468 rx_ring->next_to_use = 0;
4469
4470 rx_ring->xdp_prog = adapter->xdp_prog;
4471
4472 return 0;
4473
4474 err:
4475 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4476 vfree(rx_ring->rx_buffer_info);
4477 rx_ring->rx_buffer_info = NULL;
4478 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4479 return -ENOMEM;
4480 }
4481
4482 /**
4483 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
4484 * (Descriptors) for all queues
4485 * @adapter: board private structure
4486 *
4487 * Return 0 on success, negative on failure
4488 **/
igb_setup_all_rx_resources(struct igb_adapter * adapter)4489 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4490 {
4491 struct pci_dev *pdev = adapter->pdev;
4492 int i, err = 0;
4493
4494 for (i = 0; i < adapter->num_rx_queues; i++) {
4495 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4496 if (err) {
4497 dev_err(&pdev->dev,
4498 "Allocation for Rx Queue %u failed\n", i);
4499 for (i--; i >= 0; i--)
4500 igb_free_rx_resources(adapter->rx_ring[i]);
4501 break;
4502 }
4503 }
4504
4505 return err;
4506 }
4507
4508 /**
4509 * igb_setup_mrqc - configure the multiple receive queue control registers
4510 * @adapter: Board private structure
4511 **/
igb_setup_mrqc(struct igb_adapter * adapter)4512 static void igb_setup_mrqc(struct igb_adapter *adapter)
4513 {
4514 struct e1000_hw *hw = &adapter->hw;
4515 u32 mrqc, rxcsum;
4516 u32 j, num_rx_queues;
4517 u32 rss_key[10];
4518
4519 netdev_rss_key_fill(rss_key, sizeof(rss_key));
4520 for (j = 0; j < 10; j++)
4521 wr32(E1000_RSSRK(j), rss_key[j]);
4522
4523 num_rx_queues = adapter->rss_queues;
4524
4525 switch (hw->mac.type) {
4526 case e1000_82576:
4527 /* 82576 supports 2 RSS queues for SR-IOV */
4528 if (adapter->vfs_allocated_count)
4529 num_rx_queues = 2;
4530 break;
4531 default:
4532 break;
4533 }
4534
4535 if (adapter->rss_indir_tbl_init != num_rx_queues) {
4536 for (j = 0; j < IGB_RETA_SIZE; j++)
4537 adapter->rss_indir_tbl[j] =
4538 (j * num_rx_queues) / IGB_RETA_SIZE;
4539 adapter->rss_indir_tbl_init = num_rx_queues;
4540 }
4541 igb_write_rss_indir_tbl(adapter);
4542
4543 /* Disable raw packet checksumming so that RSS hash is placed in
4544 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
4545 * offloads as they are enabled by default
4546 */
4547 rxcsum = rd32(E1000_RXCSUM);
4548 rxcsum |= E1000_RXCSUM_PCSD;
4549
4550 if (adapter->hw.mac.type >= e1000_82576)
4551 /* Enable Receive Checksum Offload for SCTP */
4552 rxcsum |= E1000_RXCSUM_CRCOFL;
4553
4554 /* Don't need to set TUOFL or IPOFL, they default to 1 */
4555 wr32(E1000_RXCSUM, rxcsum);
4556
4557 /* Generate RSS hash based on packet types, TCP/UDP
4558 * port numbers and/or IPv4/v6 src and dst addresses
4559 */
4560 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4561 E1000_MRQC_RSS_FIELD_IPV4_TCP |
4562 E1000_MRQC_RSS_FIELD_IPV6 |
4563 E1000_MRQC_RSS_FIELD_IPV6_TCP |
4564 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4565
4566 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4567 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4568 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4569 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4570
4571 /* If VMDq is enabled then we set the appropriate mode for that, else
4572 * we default to RSS so that an RSS hash is calculated per packet even
4573 * if we are only using one queue
4574 */
4575 if (adapter->vfs_allocated_count) {
4576 if (hw->mac.type > e1000_82575) {
4577 /* Set the default pool for the PF's first queue */
4578 u32 vtctl = rd32(E1000_VT_CTL);
4579
4580 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4581 E1000_VT_CTL_DISABLE_DEF_POOL);
4582 vtctl |= adapter->vfs_allocated_count <<
4583 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4584 wr32(E1000_VT_CTL, vtctl);
4585 }
4586 if (adapter->rss_queues > 1)
4587 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4588 else
4589 mrqc |= E1000_MRQC_ENABLE_VMDQ;
4590 } else {
4591 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4592 }
4593 igb_vmm_control(adapter);
4594
4595 wr32(E1000_MRQC, mrqc);
4596 }
4597
4598 /**
4599 * igb_setup_rctl - configure the receive control registers
4600 * @adapter: Board private structure
4601 **/
igb_setup_rctl(struct igb_adapter * adapter)4602 void igb_setup_rctl(struct igb_adapter *adapter)
4603 {
4604 struct e1000_hw *hw = &adapter->hw;
4605 u32 rctl;
4606
4607 rctl = rd32(E1000_RCTL);
4608
4609 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4610 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4611
4612 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4613 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4614
4615 /* enable stripping of CRC. It's unlikely this will break BMC
4616 * redirection as it did with e1000. Newer features require
4617 * that the HW strips the CRC.
4618 */
4619 rctl |= E1000_RCTL_SECRC;
4620
4621 /* disable store bad packets and clear size bits. */
4622 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4623
4624 /* enable LPE to allow for reception of jumbo frames */
4625 rctl |= E1000_RCTL_LPE;
4626
4627 /* disable queue 0 to prevent tail write w/o re-config */
4628 wr32(E1000_RXDCTL(0), 0);
4629
4630 /* Attention!!! For SR-IOV PF driver operations you must enable
4631 * queue drop for all VF and PF queues to prevent head of line blocking
4632 * if an un-trusted VF does not provide descriptors to hardware.
4633 */
4634 if (adapter->vfs_allocated_count) {
4635 /* set all queue drop enable bits */
4636 wr32(E1000_QDE, ALL_QUEUES);
4637 }
4638
4639 /* This is useful for sniffing bad packets. */
4640 if (adapter->netdev->features & NETIF_F_RXALL) {
4641 /* UPE and MPE will be handled by normal PROMISC logic
4642 * in e1000e_set_rx_mode
4643 */
4644 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4645 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4646 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4647
4648 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4649 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4650 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4651 * and that breaks VLANs.
4652 */
4653 }
4654
4655 wr32(E1000_RCTL, rctl);
4656 }
4657
igb_set_vf_rlpml(struct igb_adapter * adapter,int size,int vfn)4658 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4659 int vfn)
4660 {
4661 struct e1000_hw *hw = &adapter->hw;
4662 u32 vmolr;
4663
4664 if (size > MAX_JUMBO_FRAME_SIZE)
4665 size = MAX_JUMBO_FRAME_SIZE;
4666
4667 vmolr = rd32(E1000_VMOLR(vfn));
4668 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4669 vmolr |= size | E1000_VMOLR_LPE;
4670 wr32(E1000_VMOLR(vfn), vmolr);
4671
4672 return 0;
4673 }
4674
igb_set_vf_vlan_strip(struct igb_adapter * adapter,int vfn,bool enable)4675 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4676 int vfn, bool enable)
4677 {
4678 struct e1000_hw *hw = &adapter->hw;
4679 u32 val, reg;
4680
4681 if (hw->mac.type < e1000_82576)
4682 return;
4683
4684 if (hw->mac.type == e1000_i350)
4685 reg = E1000_DVMOLR(vfn);
4686 else
4687 reg = E1000_VMOLR(vfn);
4688
4689 val = rd32(reg);
4690 if (enable)
4691 val |= E1000_VMOLR_STRVLAN;
4692 else
4693 val &= ~(E1000_VMOLR_STRVLAN);
4694 wr32(reg, val);
4695 }
4696
igb_set_vmolr(struct igb_adapter * adapter,int vfn,bool aupe)4697 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4698 int vfn, bool aupe)
4699 {
4700 struct e1000_hw *hw = &adapter->hw;
4701 u32 vmolr;
4702
4703 /* This register exists only on 82576 and newer so if we are older then
4704 * we should exit and do nothing
4705 */
4706 if (hw->mac.type < e1000_82576)
4707 return;
4708
4709 vmolr = rd32(E1000_VMOLR(vfn));
4710 if (aupe)
4711 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4712 else
4713 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4714
4715 /* clear all bits that might not be set */
4716 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4717
4718 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4719 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4720 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4721 * multicast packets
4722 */
4723 if (vfn <= adapter->vfs_allocated_count)
4724 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4725
4726 wr32(E1000_VMOLR(vfn), vmolr);
4727 }
4728
4729 /**
4730 * igb_setup_srrctl - configure the split and replication receive control
4731 * registers
4732 * @adapter: Board private structure
4733 * @ring: receive ring to be configured
4734 **/
igb_setup_srrctl(struct igb_adapter * adapter,struct igb_ring * ring)4735 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4736 {
4737 struct e1000_hw *hw = &adapter->hw;
4738 int reg_idx = ring->reg_idx;
4739 u32 srrctl = 0;
4740
4741 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4742 if (ring_uses_large_buffer(ring))
4743 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4744 else
4745 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4746 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4747 if (hw->mac.type >= e1000_82580)
4748 srrctl |= E1000_SRRCTL_TIMESTAMP;
4749 /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4750 * queues and rx flow control is disabled
4751 */
4752 if (adapter->vfs_allocated_count ||
4753 (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4754 adapter->num_rx_queues > 1))
4755 srrctl |= E1000_SRRCTL_DROP_EN;
4756
4757 wr32(E1000_SRRCTL(reg_idx), srrctl);
4758 }
4759
4760 /**
4761 * igb_configure_rx_ring - Configure a receive ring after Reset
4762 * @adapter: board private structure
4763 * @ring: receive ring to be configured
4764 *
4765 * Configure the Rx unit of the MAC after a reset.
4766 **/
igb_configure_rx_ring(struct igb_adapter * adapter,struct igb_ring * ring)4767 void igb_configure_rx_ring(struct igb_adapter *adapter,
4768 struct igb_ring *ring)
4769 {
4770 struct e1000_hw *hw = &adapter->hw;
4771 union e1000_adv_rx_desc *rx_desc;
4772 u64 rdba = ring->dma;
4773 int reg_idx = ring->reg_idx;
4774 u32 rxdctl = 0;
4775
4776 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4777 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4778 MEM_TYPE_PAGE_SHARED, NULL));
4779
4780 /* disable the queue */
4781 wr32(E1000_RXDCTL(reg_idx), 0);
4782
4783 /* Set DMA base address registers */
4784 wr32(E1000_RDBAL(reg_idx),
4785 rdba & 0x00000000ffffffffULL);
4786 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4787 wr32(E1000_RDLEN(reg_idx),
4788 ring->count * sizeof(union e1000_adv_rx_desc));
4789
4790 /* initialize head and tail */
4791 ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4792 wr32(E1000_RDH(reg_idx), 0);
4793 writel(0, ring->tail);
4794
4795 /* set descriptor configuration */
4796 igb_setup_srrctl(adapter, ring);
4797
4798 /* set filtering for VMDQ pools */
4799 igb_set_vmolr(adapter, reg_idx & 0x7, true);
4800
4801 rxdctl |= IGB_RX_PTHRESH;
4802 rxdctl |= IGB_RX_HTHRESH << 8;
4803 rxdctl |= IGB_RX_WTHRESH << 16;
4804
4805 /* initialize rx_buffer_info */
4806 memset(ring->rx_buffer_info, 0,
4807 sizeof(struct igb_rx_buffer) * ring->count);
4808
4809 /* initialize Rx descriptor 0 */
4810 rx_desc = IGB_RX_DESC(ring, 0);
4811 rx_desc->wb.upper.length = 0;
4812
4813 /* enable receive descriptor fetching */
4814 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4815 wr32(E1000_RXDCTL(reg_idx), rxdctl);
4816 }
4817
igb_set_rx_buffer_len(struct igb_adapter * adapter,struct igb_ring * rx_ring)4818 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4819 struct igb_ring *rx_ring)
4820 {
4821 #if (PAGE_SIZE < 8192)
4822 struct e1000_hw *hw = &adapter->hw;
4823 #endif
4824
4825 /* set build_skb and buffer size flags */
4826 clear_ring_build_skb_enabled(rx_ring);
4827 clear_ring_uses_large_buffer(rx_ring);
4828
4829 if (adapter->flags & IGB_FLAG_RX_LEGACY)
4830 return;
4831
4832 set_ring_build_skb_enabled(rx_ring);
4833
4834 #if (PAGE_SIZE < 8192)
4835 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB ||
4836 IGB_2K_TOO_SMALL_WITH_PADDING ||
4837 rd32(E1000_RCTL) & E1000_RCTL_SBP)
4838 set_ring_uses_large_buffer(rx_ring);
4839 #endif
4840 }
4841
4842 /**
4843 * igb_configure_rx - Configure receive Unit after Reset
4844 * @adapter: board private structure
4845 *
4846 * Configure the Rx unit of the MAC after a reset.
4847 **/
igb_configure_rx(struct igb_adapter * adapter)4848 static void igb_configure_rx(struct igb_adapter *adapter)
4849 {
4850 int i;
4851
4852 /* set the correct pool for the PF default MAC address in entry 0 */
4853 igb_set_default_mac_filter(adapter);
4854
4855 /* Setup the HW Rx Head and Tail Descriptor Pointers and
4856 * the Base and Length of the Rx Descriptor Ring
4857 */
4858 for (i = 0; i < adapter->num_rx_queues; i++) {
4859 struct igb_ring *rx_ring = adapter->rx_ring[i];
4860
4861 igb_set_rx_buffer_len(adapter, rx_ring);
4862 igb_configure_rx_ring(adapter, rx_ring);
4863 }
4864 }
4865
4866 /**
4867 * igb_free_tx_resources - Free Tx Resources per Queue
4868 * @tx_ring: Tx descriptor ring for a specific queue
4869 *
4870 * Free all transmit software resources
4871 **/
igb_free_tx_resources(struct igb_ring * tx_ring)4872 void igb_free_tx_resources(struct igb_ring *tx_ring)
4873 {
4874 igb_clean_tx_ring(tx_ring);
4875
4876 vfree(tx_ring->tx_buffer_info);
4877 tx_ring->tx_buffer_info = NULL;
4878
4879 /* if not set, then don't free */
4880 if (!tx_ring->desc)
4881 return;
4882
4883 dma_free_coherent(tx_ring->dev, tx_ring->size,
4884 tx_ring->desc, tx_ring->dma);
4885
4886 tx_ring->desc = NULL;
4887 }
4888
4889 /**
4890 * igb_free_all_tx_resources - Free Tx Resources for All Queues
4891 * @adapter: board private structure
4892 *
4893 * Free all transmit software resources
4894 **/
igb_free_all_tx_resources(struct igb_adapter * adapter)4895 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4896 {
4897 int i;
4898
4899 for (i = 0; i < adapter->num_tx_queues; i++)
4900 if (adapter->tx_ring[i])
4901 igb_free_tx_resources(adapter->tx_ring[i]);
4902 }
4903
4904 /**
4905 * igb_clean_tx_ring - Free Tx Buffers
4906 * @tx_ring: ring to be cleaned
4907 **/
igb_clean_tx_ring(struct igb_ring * tx_ring)4908 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4909 {
4910 u16 i = tx_ring->next_to_clean;
4911 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4912
4913 while (i != tx_ring->next_to_use) {
4914 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4915
4916 /* Free all the Tx ring sk_buffs or xdp frames */
4917 if (tx_buffer->type == IGB_TYPE_SKB)
4918 dev_kfree_skb_any(tx_buffer->skb);
4919 else
4920 xdp_return_frame(tx_buffer->xdpf);
4921
4922 /* unmap skb header data */
4923 dma_unmap_single(tx_ring->dev,
4924 dma_unmap_addr(tx_buffer, dma),
4925 dma_unmap_len(tx_buffer, len),
4926 DMA_TO_DEVICE);
4927
4928 /* check for eop_desc to determine the end of the packet */
4929 eop_desc = tx_buffer->next_to_watch;
4930 tx_desc = IGB_TX_DESC(tx_ring, i);
4931
4932 /* unmap remaining buffers */
4933 while (tx_desc != eop_desc) {
4934 tx_buffer++;
4935 tx_desc++;
4936 i++;
4937 if (unlikely(i == tx_ring->count)) {
4938 i = 0;
4939 tx_buffer = tx_ring->tx_buffer_info;
4940 tx_desc = IGB_TX_DESC(tx_ring, 0);
4941 }
4942
4943 /* unmap any remaining paged data */
4944 if (dma_unmap_len(tx_buffer, len))
4945 dma_unmap_page(tx_ring->dev,
4946 dma_unmap_addr(tx_buffer, dma),
4947 dma_unmap_len(tx_buffer, len),
4948 DMA_TO_DEVICE);
4949 }
4950
4951 tx_buffer->next_to_watch = NULL;
4952
4953 /* move us one more past the eop_desc for start of next pkt */
4954 tx_buffer++;
4955 i++;
4956 if (unlikely(i == tx_ring->count)) {
4957 i = 0;
4958 tx_buffer = tx_ring->tx_buffer_info;
4959 }
4960 }
4961
4962 /* reset BQL for queue */
4963 netdev_tx_reset_queue(txring_txq(tx_ring));
4964
4965 /* reset next_to_use and next_to_clean */
4966 tx_ring->next_to_use = 0;
4967 tx_ring->next_to_clean = 0;
4968 }
4969
4970 /**
4971 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
4972 * @adapter: board private structure
4973 **/
igb_clean_all_tx_rings(struct igb_adapter * adapter)4974 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4975 {
4976 int i;
4977
4978 for (i = 0; i < adapter->num_tx_queues; i++)
4979 if (adapter->tx_ring[i])
4980 igb_clean_tx_ring(adapter->tx_ring[i]);
4981 }
4982
4983 /**
4984 * igb_free_rx_resources - Free Rx Resources
4985 * @rx_ring: ring to clean the resources from
4986 *
4987 * Free all receive software resources
4988 **/
igb_free_rx_resources(struct igb_ring * rx_ring)4989 void igb_free_rx_resources(struct igb_ring *rx_ring)
4990 {
4991 igb_clean_rx_ring(rx_ring);
4992
4993 rx_ring->xdp_prog = NULL;
4994 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4995 vfree(rx_ring->rx_buffer_info);
4996 rx_ring->rx_buffer_info = NULL;
4997
4998 /* if not set, then don't free */
4999 if (!rx_ring->desc)
5000 return;
5001
5002 dma_free_coherent(rx_ring->dev, rx_ring->size,
5003 rx_ring->desc, rx_ring->dma);
5004
5005 rx_ring->desc = NULL;
5006 }
5007
5008 /**
5009 * igb_free_all_rx_resources - Free Rx Resources for All Queues
5010 * @adapter: board private structure
5011 *
5012 * Free all receive software resources
5013 **/
igb_free_all_rx_resources(struct igb_adapter * adapter)5014 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
5015 {
5016 int i;
5017
5018 for (i = 0; i < adapter->num_rx_queues; i++)
5019 if (adapter->rx_ring[i])
5020 igb_free_rx_resources(adapter->rx_ring[i]);
5021 }
5022
5023 /**
5024 * igb_clean_rx_ring - Free Rx Buffers per Queue
5025 * @rx_ring: ring to free buffers from
5026 **/
igb_clean_rx_ring(struct igb_ring * rx_ring)5027 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
5028 {
5029 u16 i = rx_ring->next_to_clean;
5030
5031 dev_kfree_skb(rx_ring->skb);
5032 rx_ring->skb = NULL;
5033
5034 /* Free all the Rx ring sk_buffs */
5035 while (i != rx_ring->next_to_alloc) {
5036 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5037
5038 /* Invalidate cache lines that may have been written to by
5039 * device so that we avoid corrupting memory.
5040 */
5041 dma_sync_single_range_for_cpu(rx_ring->dev,
5042 buffer_info->dma,
5043 buffer_info->page_offset,
5044 igb_rx_bufsz(rx_ring),
5045 DMA_FROM_DEVICE);
5046
5047 /* free resources associated with mapping */
5048 dma_unmap_page_attrs(rx_ring->dev,
5049 buffer_info->dma,
5050 igb_rx_pg_size(rx_ring),
5051 DMA_FROM_DEVICE,
5052 IGB_RX_DMA_ATTR);
5053 __page_frag_cache_drain(buffer_info->page,
5054 buffer_info->pagecnt_bias);
5055
5056 i++;
5057 if (i == rx_ring->count)
5058 i = 0;
5059 }
5060
5061 rx_ring->next_to_alloc = 0;
5062 rx_ring->next_to_clean = 0;
5063 rx_ring->next_to_use = 0;
5064 }
5065
5066 /**
5067 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
5068 * @adapter: board private structure
5069 **/
igb_clean_all_rx_rings(struct igb_adapter * adapter)5070 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
5071 {
5072 int i;
5073
5074 for (i = 0; i < adapter->num_rx_queues; i++)
5075 if (adapter->rx_ring[i])
5076 igb_clean_rx_ring(adapter->rx_ring[i]);
5077 }
5078
5079 /**
5080 * igb_set_mac - Change the Ethernet Address of the NIC
5081 * @netdev: network interface device structure
5082 * @p: pointer to an address structure
5083 *
5084 * Returns 0 on success, negative on failure
5085 **/
igb_set_mac(struct net_device * netdev,void * p)5086 static int igb_set_mac(struct net_device *netdev, void *p)
5087 {
5088 struct igb_adapter *adapter = netdev_priv(netdev);
5089 struct e1000_hw *hw = &adapter->hw;
5090 struct sockaddr *addr = p;
5091
5092 if (!is_valid_ether_addr(addr->sa_data))
5093 return -EADDRNOTAVAIL;
5094
5095 eth_hw_addr_set(netdev, addr->sa_data);
5096 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5097
5098 /* set the correct pool for the new PF MAC address in entry 0 */
5099 igb_set_default_mac_filter(adapter);
5100
5101 return 0;
5102 }
5103
5104 /**
5105 * igb_write_mc_addr_list - write multicast addresses to MTA
5106 * @netdev: network interface device structure
5107 *
5108 * Writes multicast address list to the MTA hash table.
5109 * Returns: -ENOMEM on failure
5110 * 0 on no addresses written
5111 * X on writing X addresses to MTA
5112 **/
igb_write_mc_addr_list(struct net_device * netdev)5113 static int igb_write_mc_addr_list(struct net_device *netdev)
5114 {
5115 struct igb_adapter *adapter = netdev_priv(netdev);
5116 struct e1000_hw *hw = &adapter->hw;
5117 struct netdev_hw_addr *ha;
5118 u8 *mta_list;
5119 int i;
5120
5121 if (netdev_mc_empty(netdev)) {
5122 /* nothing to program, so clear mc list */
5123 igb_update_mc_addr_list(hw, NULL, 0);
5124 igb_restore_vf_multicasts(adapter);
5125 return 0;
5126 }
5127
5128 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5129 if (!mta_list)
5130 return -ENOMEM;
5131
5132 /* The shared function expects a packed array of only addresses. */
5133 i = 0;
5134 netdev_for_each_mc_addr(ha, netdev)
5135 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5136
5137 igb_update_mc_addr_list(hw, mta_list, i);
5138 kfree(mta_list);
5139
5140 return netdev_mc_count(netdev);
5141 }
5142
igb_vlan_promisc_enable(struct igb_adapter * adapter)5143 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5144 {
5145 struct e1000_hw *hw = &adapter->hw;
5146 u32 i, pf_id;
5147
5148 switch (hw->mac.type) {
5149 case e1000_i210:
5150 case e1000_i211:
5151 case e1000_i350:
5152 /* VLAN filtering needed for VLAN prio filter */
5153 if (adapter->netdev->features & NETIF_F_NTUPLE)
5154 break;
5155 fallthrough;
5156 case e1000_82576:
5157 case e1000_82580:
5158 case e1000_i354:
5159 /* VLAN filtering needed for pool filtering */
5160 if (adapter->vfs_allocated_count)
5161 break;
5162 fallthrough;
5163 default:
5164 return 1;
5165 }
5166
5167 /* We are already in VLAN promisc, nothing to do */
5168 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5169 return 0;
5170
5171 if (!adapter->vfs_allocated_count)
5172 goto set_vfta;
5173
5174 /* Add PF to all active pools */
5175 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5176
5177 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5178 u32 vlvf = rd32(E1000_VLVF(i));
5179
5180 vlvf |= BIT(pf_id);
5181 wr32(E1000_VLVF(i), vlvf);
5182 }
5183
5184 set_vfta:
5185 /* Set all bits in the VLAN filter table array */
5186 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5187 hw->mac.ops.write_vfta(hw, i, ~0U);
5188
5189 /* Set flag so we don't redo unnecessary work */
5190 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5191
5192 return 0;
5193 }
5194
5195 #define VFTA_BLOCK_SIZE 8
igb_scrub_vfta(struct igb_adapter * adapter,u32 vfta_offset)5196 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5197 {
5198 struct e1000_hw *hw = &adapter->hw;
5199 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5200 u32 vid_start = vfta_offset * 32;
5201 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5202 u32 i, vid, word, bits, pf_id;
5203
5204 /* guarantee that we don't scrub out management VLAN */
5205 vid = adapter->mng_vlan_id;
5206 if (vid >= vid_start && vid < vid_end)
5207 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5208
5209 if (!adapter->vfs_allocated_count)
5210 goto set_vfta;
5211
5212 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5213
5214 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5215 u32 vlvf = rd32(E1000_VLVF(i));
5216
5217 /* pull VLAN ID from VLVF */
5218 vid = vlvf & VLAN_VID_MASK;
5219
5220 /* only concern ourselves with a certain range */
5221 if (vid < vid_start || vid >= vid_end)
5222 continue;
5223
5224 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5225 /* record VLAN ID in VFTA */
5226 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5227
5228 /* if PF is part of this then continue */
5229 if (test_bit(vid, adapter->active_vlans))
5230 continue;
5231 }
5232
5233 /* remove PF from the pool */
5234 bits = ~BIT(pf_id);
5235 bits &= rd32(E1000_VLVF(i));
5236 wr32(E1000_VLVF(i), bits);
5237 }
5238
5239 set_vfta:
5240 /* extract values from active_vlans and write back to VFTA */
5241 for (i = VFTA_BLOCK_SIZE; i--;) {
5242 vid = (vfta_offset + i) * 32;
5243 word = vid / BITS_PER_LONG;
5244 bits = vid % BITS_PER_LONG;
5245
5246 vfta[i] |= adapter->active_vlans[word] >> bits;
5247
5248 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5249 }
5250 }
5251
igb_vlan_promisc_disable(struct igb_adapter * adapter)5252 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5253 {
5254 u32 i;
5255
5256 /* We are not in VLAN promisc, nothing to do */
5257 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5258 return;
5259
5260 /* Set flag so we don't redo unnecessary work */
5261 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5262
5263 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5264 igb_scrub_vfta(adapter, i);
5265 }
5266
5267 /**
5268 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5269 * @netdev: network interface device structure
5270 *
5271 * The set_rx_mode entry point is called whenever the unicast or multicast
5272 * address lists or the network interface flags are updated. This routine is
5273 * responsible for configuring the hardware for proper unicast, multicast,
5274 * promiscuous mode, and all-multi behavior.
5275 **/
igb_set_rx_mode(struct net_device * netdev)5276 static void igb_set_rx_mode(struct net_device *netdev)
5277 {
5278 struct igb_adapter *adapter = netdev_priv(netdev);
5279 struct e1000_hw *hw = &adapter->hw;
5280 unsigned int vfn = adapter->vfs_allocated_count;
5281 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5282 int count;
5283
5284 /* Check for Promiscuous and All Multicast modes */
5285 if (netdev->flags & IFF_PROMISC) {
5286 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5287 vmolr |= E1000_VMOLR_MPME;
5288
5289 /* enable use of UTA filter to force packets to default pool */
5290 if (hw->mac.type == e1000_82576)
5291 vmolr |= E1000_VMOLR_ROPE;
5292 } else {
5293 if (netdev->flags & IFF_ALLMULTI) {
5294 rctl |= E1000_RCTL_MPE;
5295 vmolr |= E1000_VMOLR_MPME;
5296 } else {
5297 /* Write addresses to the MTA, if the attempt fails
5298 * then we should just turn on promiscuous mode so
5299 * that we can at least receive multicast traffic
5300 */
5301 count = igb_write_mc_addr_list(netdev);
5302 if (count < 0) {
5303 rctl |= E1000_RCTL_MPE;
5304 vmolr |= E1000_VMOLR_MPME;
5305 } else if (count) {
5306 vmolr |= E1000_VMOLR_ROMPE;
5307 }
5308 }
5309 }
5310
5311 /* Write addresses to available RAR registers, if there is not
5312 * sufficient space to store all the addresses then enable
5313 * unicast promiscuous mode
5314 */
5315 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5316 rctl |= E1000_RCTL_UPE;
5317 vmolr |= E1000_VMOLR_ROPE;
5318 }
5319
5320 /* enable VLAN filtering by default */
5321 rctl |= E1000_RCTL_VFE;
5322
5323 /* disable VLAN filtering for modes that require it */
5324 if ((netdev->flags & IFF_PROMISC) ||
5325 (netdev->features & NETIF_F_RXALL)) {
5326 /* if we fail to set all rules then just clear VFE */
5327 if (igb_vlan_promisc_enable(adapter))
5328 rctl &= ~E1000_RCTL_VFE;
5329 } else {
5330 igb_vlan_promisc_disable(adapter);
5331 }
5332
5333 /* update state of unicast, multicast, and VLAN filtering modes */
5334 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5335 E1000_RCTL_VFE);
5336 wr32(E1000_RCTL, rctl);
5337
5338 #if (PAGE_SIZE < 8192)
5339 if (!adapter->vfs_allocated_count) {
5340 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5341 rlpml = IGB_MAX_FRAME_BUILD_SKB;
5342 }
5343 #endif
5344 wr32(E1000_RLPML, rlpml);
5345
5346 /* In order to support SR-IOV and eventually VMDq it is necessary to set
5347 * the VMOLR to enable the appropriate modes. Without this workaround
5348 * we will have issues with VLAN tag stripping not being done for frames
5349 * that are only arriving because we are the default pool
5350 */
5351 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5352 return;
5353
5354 /* set UTA to appropriate mode */
5355 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5356
5357 vmolr |= rd32(E1000_VMOLR(vfn)) &
5358 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5359
5360 /* enable Rx jumbo frames, restrict as needed to support build_skb */
5361 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5362 #if (PAGE_SIZE < 8192)
5363 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5364 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5365 else
5366 #endif
5367 vmolr |= MAX_JUMBO_FRAME_SIZE;
5368 vmolr |= E1000_VMOLR_LPE;
5369
5370 wr32(E1000_VMOLR(vfn), vmolr);
5371
5372 igb_restore_vf_multicasts(adapter);
5373 }
5374
igb_check_wvbr(struct igb_adapter * adapter)5375 static void igb_check_wvbr(struct igb_adapter *adapter)
5376 {
5377 struct e1000_hw *hw = &adapter->hw;
5378 u32 wvbr = 0;
5379
5380 switch (hw->mac.type) {
5381 case e1000_82576:
5382 case e1000_i350:
5383 wvbr = rd32(E1000_WVBR);
5384 if (!wvbr)
5385 return;
5386 break;
5387 default:
5388 break;
5389 }
5390
5391 adapter->wvbr |= wvbr;
5392 }
5393
5394 #define IGB_STAGGERED_QUEUE_OFFSET 8
5395
igb_spoof_check(struct igb_adapter * adapter)5396 static void igb_spoof_check(struct igb_adapter *adapter)
5397 {
5398 int j;
5399
5400 if (!adapter->wvbr)
5401 return;
5402
5403 for (j = 0; j < adapter->vfs_allocated_count; j++) {
5404 if (adapter->wvbr & BIT(j) ||
5405 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5406 dev_warn(&adapter->pdev->dev,
5407 "Spoof event(s) detected on VF %d\n", j);
5408 adapter->wvbr &=
5409 ~(BIT(j) |
5410 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5411 }
5412 }
5413 }
5414
5415 /* Need to wait a few seconds after link up to get diagnostic information from
5416 * the phy
5417 */
igb_update_phy_info(struct timer_list * t)5418 static void igb_update_phy_info(struct timer_list *t)
5419 {
5420 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5421 igb_get_phy_info(&adapter->hw);
5422 }
5423
5424 /**
5425 * igb_has_link - check shared code for link and determine up/down
5426 * @adapter: pointer to driver private info
5427 **/
igb_has_link(struct igb_adapter * adapter)5428 bool igb_has_link(struct igb_adapter *adapter)
5429 {
5430 struct e1000_hw *hw = &adapter->hw;
5431 bool link_active = false;
5432
5433 /* get_link_status is set on LSC (link status) interrupt or
5434 * rx sequence error interrupt. get_link_status will stay
5435 * false until the e1000_check_for_link establishes link
5436 * for copper adapters ONLY
5437 */
5438 switch (hw->phy.media_type) {
5439 case e1000_media_type_copper:
5440 if (!hw->mac.get_link_status)
5441 return true;
5442 fallthrough;
5443 case e1000_media_type_internal_serdes:
5444 hw->mac.ops.check_for_link(hw);
5445 link_active = !hw->mac.get_link_status;
5446 break;
5447 default:
5448 case e1000_media_type_unknown:
5449 break;
5450 }
5451
5452 if (((hw->mac.type == e1000_i210) ||
5453 (hw->mac.type == e1000_i211)) &&
5454 (hw->phy.id == I210_I_PHY_ID)) {
5455 if (!netif_carrier_ok(adapter->netdev)) {
5456 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5457 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5458 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5459 adapter->link_check_timeout = jiffies;
5460 }
5461 }
5462
5463 return link_active;
5464 }
5465
igb_thermal_sensor_event(struct e1000_hw * hw,u32 event)5466 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5467 {
5468 bool ret = false;
5469 u32 ctrl_ext, thstat;
5470
5471 /* check for thermal sensor event on i350 copper only */
5472 if (hw->mac.type == e1000_i350) {
5473 thstat = rd32(E1000_THSTAT);
5474 ctrl_ext = rd32(E1000_CTRL_EXT);
5475
5476 if ((hw->phy.media_type == e1000_media_type_copper) &&
5477 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5478 ret = !!(thstat & event);
5479 }
5480
5481 return ret;
5482 }
5483
5484 /**
5485 * igb_check_lvmmc - check for malformed packets received
5486 * and indicated in LVMMC register
5487 * @adapter: pointer to adapter
5488 **/
igb_check_lvmmc(struct igb_adapter * adapter)5489 static void igb_check_lvmmc(struct igb_adapter *adapter)
5490 {
5491 struct e1000_hw *hw = &adapter->hw;
5492 u32 lvmmc;
5493
5494 lvmmc = rd32(E1000_LVMMC);
5495 if (lvmmc) {
5496 if (unlikely(net_ratelimit())) {
5497 netdev_warn(adapter->netdev,
5498 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5499 lvmmc);
5500 }
5501 }
5502 }
5503
5504 /**
5505 * igb_watchdog - Timer Call-back
5506 * @t: pointer to timer_list containing our private info pointer
5507 **/
igb_watchdog(struct timer_list * t)5508 static void igb_watchdog(struct timer_list *t)
5509 {
5510 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5511 /* Do the rest outside of interrupt context */
5512 schedule_work(&adapter->watchdog_task);
5513 }
5514
igb_watchdog_task(struct work_struct * work)5515 static void igb_watchdog_task(struct work_struct *work)
5516 {
5517 struct igb_adapter *adapter = container_of(work,
5518 struct igb_adapter,
5519 watchdog_task);
5520 struct e1000_hw *hw = &adapter->hw;
5521 struct e1000_phy_info *phy = &hw->phy;
5522 struct net_device *netdev = adapter->netdev;
5523 u32 link;
5524 int i;
5525 u32 connsw;
5526 u16 phy_data, retry_count = 20;
5527
5528 link = igb_has_link(adapter);
5529
5530 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5531 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5532 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5533 else
5534 link = false;
5535 }
5536
5537 /* Force link down if we have fiber to swap to */
5538 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5539 if (hw->phy.media_type == e1000_media_type_copper) {
5540 connsw = rd32(E1000_CONNSW);
5541 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5542 link = 0;
5543 }
5544 }
5545 if (link) {
5546 /* Perform a reset if the media type changed. */
5547 if (hw->dev_spec._82575.media_changed) {
5548 hw->dev_spec._82575.media_changed = false;
5549 adapter->flags |= IGB_FLAG_MEDIA_RESET;
5550 igb_reset(adapter);
5551 }
5552 /* Cancel scheduled suspend requests. */
5553 pm_runtime_resume(netdev->dev.parent);
5554
5555 if (!netif_carrier_ok(netdev)) {
5556 u32 ctrl;
5557
5558 hw->mac.ops.get_speed_and_duplex(hw,
5559 &adapter->link_speed,
5560 &adapter->link_duplex);
5561
5562 ctrl = rd32(E1000_CTRL);
5563 /* Links status message must follow this format */
5564 netdev_info(netdev,
5565 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5566 netdev->name,
5567 adapter->link_speed,
5568 adapter->link_duplex == FULL_DUPLEX ?
5569 "Full" : "Half",
5570 (ctrl & E1000_CTRL_TFCE) &&
5571 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5572 (ctrl & E1000_CTRL_RFCE) ? "RX" :
5573 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
5574
5575 /* disable EEE if enabled */
5576 if ((adapter->flags & IGB_FLAG_EEE) &&
5577 (adapter->link_duplex == HALF_DUPLEX)) {
5578 dev_info(&adapter->pdev->dev,
5579 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5580 adapter->hw.dev_spec._82575.eee_disable = true;
5581 adapter->flags &= ~IGB_FLAG_EEE;
5582 }
5583
5584 /* check if SmartSpeed worked */
5585 igb_check_downshift(hw);
5586 if (phy->speed_downgraded)
5587 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5588
5589 /* check for thermal sensor event */
5590 if (igb_thermal_sensor_event(hw,
5591 E1000_THSTAT_LINK_THROTTLE))
5592 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5593
5594 /* adjust timeout factor according to speed/duplex */
5595 adapter->tx_timeout_factor = 1;
5596 switch (adapter->link_speed) {
5597 case SPEED_10:
5598 adapter->tx_timeout_factor = 14;
5599 break;
5600 case SPEED_100:
5601 /* maybe add some timeout factor ? */
5602 break;
5603 }
5604
5605 if (adapter->link_speed != SPEED_1000 ||
5606 !hw->phy.ops.read_reg)
5607 goto no_wait;
5608
5609 /* wait for Remote receiver status OK */
5610 retry_read_status:
5611 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5612 &phy_data)) {
5613 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5614 retry_count) {
5615 msleep(100);
5616 retry_count--;
5617 goto retry_read_status;
5618 } else if (!retry_count) {
5619 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5620 }
5621 } else {
5622 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5623 }
5624 no_wait:
5625 netif_carrier_on(netdev);
5626
5627 igb_ping_all_vfs(adapter);
5628 igb_check_vf_rate_limit(adapter);
5629
5630 /* link state has changed, schedule phy info update */
5631 if (!test_bit(__IGB_DOWN, &adapter->state))
5632 mod_timer(&adapter->phy_info_timer,
5633 round_jiffies(jiffies + 2 * HZ));
5634 }
5635 } else {
5636 if (netif_carrier_ok(netdev)) {
5637 adapter->link_speed = 0;
5638 adapter->link_duplex = 0;
5639
5640 /* check for thermal sensor event */
5641 if (igb_thermal_sensor_event(hw,
5642 E1000_THSTAT_PWR_DOWN)) {
5643 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5644 }
5645
5646 /* Links status message must follow this format */
5647 netdev_info(netdev, "igb: %s NIC Link is Down\n",
5648 netdev->name);
5649 netif_carrier_off(netdev);
5650
5651 igb_ping_all_vfs(adapter);
5652
5653 /* link state has changed, schedule phy info update */
5654 if (!test_bit(__IGB_DOWN, &adapter->state))
5655 mod_timer(&adapter->phy_info_timer,
5656 round_jiffies(jiffies + 2 * HZ));
5657
5658 /* link is down, time to check for alternate media */
5659 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5660 igb_check_swap_media(adapter);
5661 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5662 schedule_work(&adapter->reset_task);
5663 /* return immediately */
5664 return;
5665 }
5666 }
5667 pm_schedule_suspend(netdev->dev.parent,
5668 MSEC_PER_SEC * 5);
5669
5670 /* also check for alternate media here */
5671 } else if (!netif_carrier_ok(netdev) &&
5672 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5673 igb_check_swap_media(adapter);
5674 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5675 schedule_work(&adapter->reset_task);
5676 /* return immediately */
5677 return;
5678 }
5679 }
5680 }
5681
5682 spin_lock(&adapter->stats64_lock);
5683 igb_update_stats(adapter);
5684 spin_unlock(&adapter->stats64_lock);
5685
5686 for (i = 0; i < adapter->num_tx_queues; i++) {
5687 struct igb_ring *tx_ring = adapter->tx_ring[i];
5688 if (!netif_carrier_ok(netdev)) {
5689 /* We've lost link, so the controller stops DMA,
5690 * but we've got queued Tx work that's never going
5691 * to get done, so reset controller to flush Tx.
5692 * (Do the reset outside of interrupt context).
5693 */
5694 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5695 adapter->tx_timeout_count++;
5696 schedule_work(&adapter->reset_task);
5697 /* return immediately since reset is imminent */
5698 return;
5699 }
5700 }
5701
5702 /* Force detection of hung controller every watchdog period */
5703 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5704 }
5705
5706 /* Cause software interrupt to ensure Rx ring is cleaned */
5707 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5708 u32 eics = 0;
5709
5710 for (i = 0; i < adapter->num_q_vectors; i++)
5711 eics |= adapter->q_vector[i]->eims_value;
5712 wr32(E1000_EICS, eics);
5713 } else {
5714 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5715 }
5716
5717 igb_spoof_check(adapter);
5718 igb_ptp_rx_hang(adapter);
5719 igb_ptp_tx_hang(adapter);
5720
5721 /* Check LVMMC register on i350/i354 only */
5722 if ((adapter->hw.mac.type == e1000_i350) ||
5723 (adapter->hw.mac.type == e1000_i354))
5724 igb_check_lvmmc(adapter);
5725
5726 /* Reset the timer */
5727 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5728 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5729 mod_timer(&adapter->watchdog_timer,
5730 round_jiffies(jiffies + HZ));
5731 else
5732 mod_timer(&adapter->watchdog_timer,
5733 round_jiffies(jiffies + 2 * HZ));
5734 }
5735 }
5736
5737 enum latency_range {
5738 lowest_latency = 0,
5739 low_latency = 1,
5740 bulk_latency = 2,
5741 latency_invalid = 255
5742 };
5743
5744 /**
5745 * igb_update_ring_itr - update the dynamic ITR value based on packet size
5746 * @q_vector: pointer to q_vector
5747 *
5748 * Stores a new ITR value based on strictly on packet size. This
5749 * algorithm is less sophisticated than that used in igb_update_itr,
5750 * due to the difficulty of synchronizing statistics across multiple
5751 * receive rings. The divisors and thresholds used by this function
5752 * were determined based on theoretical maximum wire speed and testing
5753 * data, in order to minimize response time while increasing bulk
5754 * throughput.
5755 * This functionality is controlled by ethtool's coalescing settings.
5756 * NOTE: This function is called only when operating in a multiqueue
5757 * receive environment.
5758 **/
igb_update_ring_itr(struct igb_q_vector * q_vector)5759 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5760 {
5761 int new_val = q_vector->itr_val;
5762 int avg_wire_size = 0;
5763 struct igb_adapter *adapter = q_vector->adapter;
5764 unsigned int packets;
5765
5766 /* For non-gigabit speeds, just fix the interrupt rate at 4000
5767 * ints/sec - ITR timer value of 120 ticks.
5768 */
5769 if (adapter->link_speed != SPEED_1000) {
5770 new_val = IGB_4K_ITR;
5771 goto set_itr_val;
5772 }
5773
5774 packets = q_vector->rx.total_packets;
5775 if (packets)
5776 avg_wire_size = q_vector->rx.total_bytes / packets;
5777
5778 packets = q_vector->tx.total_packets;
5779 if (packets)
5780 avg_wire_size = max_t(u32, avg_wire_size,
5781 q_vector->tx.total_bytes / packets);
5782
5783 /* if avg_wire_size isn't set no work was done */
5784 if (!avg_wire_size)
5785 goto clear_counts;
5786
5787 /* Add 24 bytes to size to account for CRC, preamble, and gap */
5788 avg_wire_size += 24;
5789
5790 /* Don't starve jumbo frames */
5791 avg_wire_size = min(avg_wire_size, 3000);
5792
5793 /* Give a little boost to mid-size frames */
5794 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5795 new_val = avg_wire_size / 3;
5796 else
5797 new_val = avg_wire_size / 2;
5798
5799 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5800 if (new_val < IGB_20K_ITR &&
5801 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5802 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5803 new_val = IGB_20K_ITR;
5804
5805 set_itr_val:
5806 if (new_val != q_vector->itr_val) {
5807 q_vector->itr_val = new_val;
5808 q_vector->set_itr = 1;
5809 }
5810 clear_counts:
5811 q_vector->rx.total_bytes = 0;
5812 q_vector->rx.total_packets = 0;
5813 q_vector->tx.total_bytes = 0;
5814 q_vector->tx.total_packets = 0;
5815 }
5816
5817 /**
5818 * igb_update_itr - update the dynamic ITR value based on statistics
5819 * @q_vector: pointer to q_vector
5820 * @ring_container: ring info to update the itr for
5821 *
5822 * Stores a new ITR value based on packets and byte
5823 * counts during the last interrupt. The advantage of per interrupt
5824 * computation is faster updates and more accurate ITR for the current
5825 * traffic pattern. Constants in this function were computed
5826 * based on theoretical maximum wire speed and thresholds were set based
5827 * on testing data as well as attempting to minimize response time
5828 * while increasing bulk throughput.
5829 * This functionality is controlled by ethtool's coalescing settings.
5830 * NOTE: These calculations are only valid when operating in a single-
5831 * queue environment.
5832 **/
igb_update_itr(struct igb_q_vector * q_vector,struct igb_ring_container * ring_container)5833 static void igb_update_itr(struct igb_q_vector *q_vector,
5834 struct igb_ring_container *ring_container)
5835 {
5836 unsigned int packets = ring_container->total_packets;
5837 unsigned int bytes = ring_container->total_bytes;
5838 u8 itrval = ring_container->itr;
5839
5840 /* no packets, exit with status unchanged */
5841 if (packets == 0)
5842 return;
5843
5844 switch (itrval) {
5845 case lowest_latency:
5846 /* handle TSO and jumbo frames */
5847 if (bytes/packets > 8000)
5848 itrval = bulk_latency;
5849 else if ((packets < 5) && (bytes > 512))
5850 itrval = low_latency;
5851 break;
5852 case low_latency: /* 50 usec aka 20000 ints/s */
5853 if (bytes > 10000) {
5854 /* this if handles the TSO accounting */
5855 if (bytes/packets > 8000)
5856 itrval = bulk_latency;
5857 else if ((packets < 10) || ((bytes/packets) > 1200))
5858 itrval = bulk_latency;
5859 else if ((packets > 35))
5860 itrval = lowest_latency;
5861 } else if (bytes/packets > 2000) {
5862 itrval = bulk_latency;
5863 } else if (packets <= 2 && bytes < 512) {
5864 itrval = lowest_latency;
5865 }
5866 break;
5867 case bulk_latency: /* 250 usec aka 4000 ints/s */
5868 if (bytes > 25000) {
5869 if (packets > 35)
5870 itrval = low_latency;
5871 } else if (bytes < 1500) {
5872 itrval = low_latency;
5873 }
5874 break;
5875 }
5876
5877 /* clear work counters since we have the values we need */
5878 ring_container->total_bytes = 0;
5879 ring_container->total_packets = 0;
5880
5881 /* write updated itr to ring container */
5882 ring_container->itr = itrval;
5883 }
5884
igb_set_itr(struct igb_q_vector * q_vector)5885 static void igb_set_itr(struct igb_q_vector *q_vector)
5886 {
5887 struct igb_adapter *adapter = q_vector->adapter;
5888 u32 new_itr = q_vector->itr_val;
5889 u8 current_itr = 0;
5890
5891 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5892 if (adapter->link_speed != SPEED_1000) {
5893 current_itr = 0;
5894 new_itr = IGB_4K_ITR;
5895 goto set_itr_now;
5896 }
5897
5898 igb_update_itr(q_vector, &q_vector->tx);
5899 igb_update_itr(q_vector, &q_vector->rx);
5900
5901 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5902
5903 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5904 if (current_itr == lowest_latency &&
5905 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5906 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5907 current_itr = low_latency;
5908
5909 switch (current_itr) {
5910 /* counts and packets in update_itr are dependent on these numbers */
5911 case lowest_latency:
5912 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5913 break;
5914 case low_latency:
5915 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5916 break;
5917 case bulk_latency:
5918 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
5919 break;
5920 default:
5921 break;
5922 }
5923
5924 set_itr_now:
5925 if (new_itr != q_vector->itr_val) {
5926 /* this attempts to bias the interrupt rate towards Bulk
5927 * by adding intermediate steps when interrupt rate is
5928 * increasing
5929 */
5930 new_itr = new_itr > q_vector->itr_val ?
5931 max((new_itr * q_vector->itr_val) /
5932 (new_itr + (q_vector->itr_val >> 2)),
5933 new_itr) : new_itr;
5934 /* Don't write the value here; it resets the adapter's
5935 * internal timer, and causes us to delay far longer than
5936 * we should between interrupts. Instead, we write the ITR
5937 * value at the beginning of the next interrupt so the timing
5938 * ends up being correct.
5939 */
5940 q_vector->itr_val = new_itr;
5941 q_vector->set_itr = 1;
5942 }
5943 }
5944
igb_tx_ctxtdesc(struct igb_ring * tx_ring,struct igb_tx_buffer * first,u32 vlan_macip_lens,u32 type_tucmd,u32 mss_l4len_idx)5945 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5946 struct igb_tx_buffer *first,
5947 u32 vlan_macip_lens, u32 type_tucmd,
5948 u32 mss_l4len_idx)
5949 {
5950 struct e1000_adv_tx_context_desc *context_desc;
5951 u16 i = tx_ring->next_to_use;
5952 struct timespec64 ts;
5953
5954 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5955
5956 i++;
5957 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5958
5959 /* set bits to identify this as an advanced context descriptor */
5960 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5961
5962 /* For 82575, context index must be unique per ring. */
5963 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5964 mss_l4len_idx |= tx_ring->reg_idx << 4;
5965
5966 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5967 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5968 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5969
5970 /* We assume there is always a valid tx time available. Invalid times
5971 * should have been handled by the upper layers.
5972 */
5973 if (tx_ring->launchtime_enable) {
5974 ts = ktime_to_timespec64(first->skb->tstamp);
5975 skb_txtime_consumed(first->skb);
5976 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5977 } else {
5978 context_desc->seqnum_seed = 0;
5979 }
5980 }
5981
igb_tso(struct igb_ring * tx_ring,struct igb_tx_buffer * first,u8 * hdr_len)5982 static int igb_tso(struct igb_ring *tx_ring,
5983 struct igb_tx_buffer *first,
5984 u8 *hdr_len)
5985 {
5986 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5987 struct sk_buff *skb = first->skb;
5988 union {
5989 struct iphdr *v4;
5990 struct ipv6hdr *v6;
5991 unsigned char *hdr;
5992 } ip;
5993 union {
5994 struct tcphdr *tcp;
5995 struct udphdr *udp;
5996 unsigned char *hdr;
5997 } l4;
5998 u32 paylen, l4_offset;
5999 int err;
6000
6001 if (skb->ip_summed != CHECKSUM_PARTIAL)
6002 return 0;
6003
6004 if (!skb_is_gso(skb))
6005 return 0;
6006
6007 err = skb_cow_head(skb, 0);
6008 if (err < 0)
6009 return err;
6010
6011 ip.hdr = skb_network_header(skb);
6012 l4.hdr = skb_checksum_start(skb);
6013
6014 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6015 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
6016 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
6017
6018 /* initialize outer IP header fields */
6019 if (ip.v4->version == 4) {
6020 unsigned char *csum_start = skb_checksum_start(skb);
6021 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
6022
6023 /* IP header will have to cancel out any data that
6024 * is not a part of the outer IP header
6025 */
6026 ip.v4->check = csum_fold(csum_partial(trans_start,
6027 csum_start - trans_start,
6028 0));
6029 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
6030
6031 ip.v4->tot_len = 0;
6032 first->tx_flags |= IGB_TX_FLAGS_TSO |
6033 IGB_TX_FLAGS_CSUM |
6034 IGB_TX_FLAGS_IPV4;
6035 } else {
6036 ip.v6->payload_len = 0;
6037 first->tx_flags |= IGB_TX_FLAGS_TSO |
6038 IGB_TX_FLAGS_CSUM;
6039 }
6040
6041 /* determine offset of inner transport header */
6042 l4_offset = l4.hdr - skb->data;
6043
6044 /* remove payload length from inner checksum */
6045 paylen = skb->len - l4_offset;
6046 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
6047 /* compute length of segmentation header */
6048 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
6049 csum_replace_by_diff(&l4.tcp->check,
6050 (__force __wsum)htonl(paylen));
6051 } else {
6052 /* compute length of segmentation header */
6053 *hdr_len = sizeof(*l4.udp) + l4_offset;
6054 csum_replace_by_diff(&l4.udp->check,
6055 (__force __wsum)htonl(paylen));
6056 }
6057
6058 /* update gso size and bytecount with header size */
6059 first->gso_segs = skb_shinfo(skb)->gso_segs;
6060 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6061
6062 /* MSS L4LEN IDX */
6063 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
6064 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
6065
6066 /* VLAN MACLEN IPLEN */
6067 vlan_macip_lens = l4.hdr - ip.hdr;
6068 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
6069 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6070
6071 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
6072 type_tucmd, mss_l4len_idx);
6073
6074 return 1;
6075 }
6076
igb_tx_csum(struct igb_ring * tx_ring,struct igb_tx_buffer * first)6077 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
6078 {
6079 struct sk_buff *skb = first->skb;
6080 u32 vlan_macip_lens = 0;
6081 u32 type_tucmd = 0;
6082
6083 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6084 csum_failed:
6085 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
6086 !tx_ring->launchtime_enable)
6087 return;
6088 goto no_csum;
6089 }
6090
6091 switch (skb->csum_offset) {
6092 case offsetof(struct tcphdr, check):
6093 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
6094 fallthrough;
6095 case offsetof(struct udphdr, check):
6096 break;
6097 case offsetof(struct sctphdr, checksum):
6098 /* validate that this is actually an SCTP request */
6099 if (skb_csum_is_sctp(skb)) {
6100 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6101 break;
6102 }
6103 fallthrough;
6104 default:
6105 skb_checksum_help(skb);
6106 goto csum_failed;
6107 }
6108
6109 /* update TX checksum flag */
6110 first->tx_flags |= IGB_TX_FLAGS_CSUM;
6111 vlan_macip_lens = skb_checksum_start_offset(skb) -
6112 skb_network_offset(skb);
6113 no_csum:
6114 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6115 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6116
6117 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6118 }
6119
6120 #define IGB_SET_FLAG(_input, _flag, _result) \
6121 ((_flag <= _result) ? \
6122 ((u32)(_input & _flag) * (_result / _flag)) : \
6123 ((u32)(_input & _flag) / (_flag / _result)))
6124
igb_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)6125 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6126 {
6127 /* set type for advanced descriptor with frame checksum insertion */
6128 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6129 E1000_ADVTXD_DCMD_DEXT |
6130 E1000_ADVTXD_DCMD_IFCS;
6131
6132 /* set HW vlan bit if vlan is present */
6133 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6134 (E1000_ADVTXD_DCMD_VLE));
6135
6136 /* set segmentation bits for TSO */
6137 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6138 (E1000_ADVTXD_DCMD_TSE));
6139
6140 /* set timestamp bit if present */
6141 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6142 (E1000_ADVTXD_MAC_TSTAMP));
6143
6144 /* insert frame checksum */
6145 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6146
6147 return cmd_type;
6148 }
6149
igb_tx_olinfo_status(struct igb_ring * tx_ring,union e1000_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)6150 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6151 union e1000_adv_tx_desc *tx_desc,
6152 u32 tx_flags, unsigned int paylen)
6153 {
6154 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6155
6156 /* 82575 requires a unique index per ring */
6157 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6158 olinfo_status |= tx_ring->reg_idx << 4;
6159
6160 /* insert L4 checksum */
6161 olinfo_status |= IGB_SET_FLAG(tx_flags,
6162 IGB_TX_FLAGS_CSUM,
6163 (E1000_TXD_POPTS_TXSM << 8));
6164
6165 /* insert IPv4 checksum */
6166 olinfo_status |= IGB_SET_FLAG(tx_flags,
6167 IGB_TX_FLAGS_IPV4,
6168 (E1000_TXD_POPTS_IXSM << 8));
6169
6170 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6171 }
6172
__igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)6173 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6174 {
6175 struct net_device *netdev = tx_ring->netdev;
6176
6177 netif_stop_subqueue(netdev, tx_ring->queue_index);
6178
6179 /* Herbert's original patch had:
6180 * smp_mb__after_netif_stop_queue();
6181 * but since that doesn't exist yet, just open code it.
6182 */
6183 smp_mb();
6184
6185 /* We need to check again in a case another CPU has just
6186 * made room available.
6187 */
6188 if (igb_desc_unused(tx_ring) < size)
6189 return -EBUSY;
6190
6191 /* A reprieve! */
6192 netif_wake_subqueue(netdev, tx_ring->queue_index);
6193
6194 u64_stats_update_begin(&tx_ring->tx_syncp2);
6195 tx_ring->tx_stats.restart_queue2++;
6196 u64_stats_update_end(&tx_ring->tx_syncp2);
6197
6198 return 0;
6199 }
6200
igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)6201 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6202 {
6203 if (igb_desc_unused(tx_ring) >= size)
6204 return 0;
6205 return __igb_maybe_stop_tx(tx_ring, size);
6206 }
6207
igb_tx_map(struct igb_ring * tx_ring,struct igb_tx_buffer * first,const u8 hdr_len)6208 static int igb_tx_map(struct igb_ring *tx_ring,
6209 struct igb_tx_buffer *first,
6210 const u8 hdr_len)
6211 {
6212 struct sk_buff *skb = first->skb;
6213 struct igb_tx_buffer *tx_buffer;
6214 union e1000_adv_tx_desc *tx_desc;
6215 skb_frag_t *frag;
6216 dma_addr_t dma;
6217 unsigned int data_len, size;
6218 u32 tx_flags = first->tx_flags;
6219 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6220 u16 i = tx_ring->next_to_use;
6221
6222 tx_desc = IGB_TX_DESC(tx_ring, i);
6223
6224 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6225
6226 size = skb_headlen(skb);
6227 data_len = skb->data_len;
6228
6229 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6230
6231 tx_buffer = first;
6232
6233 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6234 if (dma_mapping_error(tx_ring->dev, dma))
6235 goto dma_error;
6236
6237 /* record length, and DMA address */
6238 dma_unmap_len_set(tx_buffer, len, size);
6239 dma_unmap_addr_set(tx_buffer, dma, dma);
6240
6241 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6242
6243 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6244 tx_desc->read.cmd_type_len =
6245 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6246
6247 i++;
6248 tx_desc++;
6249 if (i == tx_ring->count) {
6250 tx_desc = IGB_TX_DESC(tx_ring, 0);
6251 i = 0;
6252 }
6253 tx_desc->read.olinfo_status = 0;
6254
6255 dma += IGB_MAX_DATA_PER_TXD;
6256 size -= IGB_MAX_DATA_PER_TXD;
6257
6258 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6259 }
6260
6261 if (likely(!data_len))
6262 break;
6263
6264 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6265
6266 i++;
6267 tx_desc++;
6268 if (i == tx_ring->count) {
6269 tx_desc = IGB_TX_DESC(tx_ring, 0);
6270 i = 0;
6271 }
6272 tx_desc->read.olinfo_status = 0;
6273
6274 size = skb_frag_size(frag);
6275 data_len -= size;
6276
6277 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6278 size, DMA_TO_DEVICE);
6279
6280 tx_buffer = &tx_ring->tx_buffer_info[i];
6281 }
6282
6283 /* write last descriptor with RS and EOP bits */
6284 cmd_type |= size | IGB_TXD_DCMD;
6285 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6286
6287 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6288
6289 /* set the timestamp */
6290 first->time_stamp = jiffies;
6291
6292 skb_tx_timestamp(skb);
6293
6294 /* Force memory writes to complete before letting h/w know there
6295 * are new descriptors to fetch. (Only applicable for weak-ordered
6296 * memory model archs, such as IA-64).
6297 *
6298 * We also need this memory barrier to make certain all of the
6299 * status bits have been updated before next_to_watch is written.
6300 */
6301 dma_wmb();
6302
6303 /* set next_to_watch value indicating a packet is present */
6304 first->next_to_watch = tx_desc;
6305
6306 i++;
6307 if (i == tx_ring->count)
6308 i = 0;
6309
6310 tx_ring->next_to_use = i;
6311
6312 /* Make sure there is space in the ring for the next send. */
6313 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6314
6315 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6316 writel(i, tx_ring->tail);
6317 }
6318 return 0;
6319
6320 dma_error:
6321 dev_err(tx_ring->dev, "TX DMA map failed\n");
6322 tx_buffer = &tx_ring->tx_buffer_info[i];
6323
6324 /* clear dma mappings for failed tx_buffer_info map */
6325 while (tx_buffer != first) {
6326 if (dma_unmap_len(tx_buffer, len))
6327 dma_unmap_page(tx_ring->dev,
6328 dma_unmap_addr(tx_buffer, dma),
6329 dma_unmap_len(tx_buffer, len),
6330 DMA_TO_DEVICE);
6331 dma_unmap_len_set(tx_buffer, len, 0);
6332
6333 if (i-- == 0)
6334 i += tx_ring->count;
6335 tx_buffer = &tx_ring->tx_buffer_info[i];
6336 }
6337
6338 if (dma_unmap_len(tx_buffer, len))
6339 dma_unmap_single(tx_ring->dev,
6340 dma_unmap_addr(tx_buffer, dma),
6341 dma_unmap_len(tx_buffer, len),
6342 DMA_TO_DEVICE);
6343 dma_unmap_len_set(tx_buffer, len, 0);
6344
6345 dev_kfree_skb_any(tx_buffer->skb);
6346 tx_buffer->skb = NULL;
6347
6348 tx_ring->next_to_use = i;
6349
6350 return -1;
6351 }
6352
igb_xmit_xdp_ring(struct igb_adapter * adapter,struct igb_ring * tx_ring,struct xdp_frame * xdpf)6353 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6354 struct igb_ring *tx_ring,
6355 struct xdp_frame *xdpf)
6356 {
6357 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
6358 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
6359 u16 count, i, index = tx_ring->next_to_use;
6360 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index];
6361 struct igb_tx_buffer *tx_buffer = tx_head;
6362 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index);
6363 u32 len = xdpf->len, cmd_type, olinfo_status;
6364 void *data = xdpf->data;
6365
6366 count = TXD_USE_COUNT(len);
6367 for (i = 0; i < nr_frags; i++)
6368 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
6369
6370 if (igb_maybe_stop_tx(tx_ring, count + 3))
6371 return IGB_XDP_CONSUMED;
6372
6373 i = 0;
6374 /* record the location of the first descriptor for this packet */
6375 tx_head->bytecount = xdp_get_frame_len(xdpf);
6376 tx_head->type = IGB_TYPE_XDP;
6377 tx_head->gso_segs = 1;
6378 tx_head->xdpf = xdpf;
6379
6380 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT;
6381 /* 82575 requires a unique index per ring */
6382 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6383 olinfo_status |= tx_ring->reg_idx << 4;
6384 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6385
6386 for (;;) {
6387 dma_addr_t dma;
6388
6389 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
6390 if (dma_mapping_error(tx_ring->dev, dma))
6391 goto unmap;
6392
6393 /* record length, and DMA address */
6394 dma_unmap_len_set(tx_buffer, len, len);
6395 dma_unmap_addr_set(tx_buffer, dma, dma);
6396
6397 /* put descriptor type bits */
6398 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT |
6399 E1000_ADVTXD_DCMD_IFCS | len;
6400
6401 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6402 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6403
6404 tx_buffer->protocol = 0;
6405
6406 if (++index == tx_ring->count)
6407 index = 0;
6408
6409 if (i == nr_frags)
6410 break;
6411
6412 tx_buffer = &tx_ring->tx_buffer_info[index];
6413 tx_desc = IGB_TX_DESC(tx_ring, index);
6414 tx_desc->read.olinfo_status = 0;
6415
6416 data = skb_frag_address(&sinfo->frags[i]);
6417 len = skb_frag_size(&sinfo->frags[i]);
6418 i++;
6419 }
6420 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
6421
6422 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount);
6423 /* set the timestamp */
6424 tx_head->time_stamp = jiffies;
6425
6426 /* Avoid any potential race with xdp_xmit and cleanup */
6427 smp_wmb();
6428
6429 /* set next_to_watch value indicating a packet is present */
6430 tx_head->next_to_watch = tx_desc;
6431 tx_ring->next_to_use = index;
6432
6433 /* Make sure there is space in the ring for the next send. */
6434 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6435
6436 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6437 writel(index, tx_ring->tail);
6438
6439 return IGB_XDP_TX;
6440
6441 unmap:
6442 for (;;) {
6443 tx_buffer = &tx_ring->tx_buffer_info[index];
6444 if (dma_unmap_len(tx_buffer, len))
6445 dma_unmap_page(tx_ring->dev,
6446 dma_unmap_addr(tx_buffer, dma),
6447 dma_unmap_len(tx_buffer, len),
6448 DMA_TO_DEVICE);
6449 dma_unmap_len_set(tx_buffer, len, 0);
6450 if (tx_buffer == tx_head)
6451 break;
6452
6453 if (!index)
6454 index += tx_ring->count;
6455 index--;
6456 }
6457
6458 return IGB_XDP_CONSUMED;
6459 }
6460
igb_xmit_frame_ring(struct sk_buff * skb,struct igb_ring * tx_ring)6461 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6462 struct igb_ring *tx_ring)
6463 {
6464 struct igb_tx_buffer *first;
6465 int tso;
6466 u32 tx_flags = 0;
6467 unsigned short f;
6468 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6469 __be16 protocol = vlan_get_protocol(skb);
6470 u8 hdr_len = 0;
6471
6472 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6473 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6474 * + 2 desc gap to keep tail from touching head,
6475 * + 1 desc for context descriptor,
6476 * otherwise try next time
6477 */
6478 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6479 count += TXD_USE_COUNT(skb_frag_size(
6480 &skb_shinfo(skb)->frags[f]));
6481
6482 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6483 /* this is a hard error */
6484 return NETDEV_TX_BUSY;
6485 }
6486
6487 /* record the location of the first descriptor for this packet */
6488 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6489 first->type = IGB_TYPE_SKB;
6490 first->skb = skb;
6491 first->bytecount = skb->len;
6492 first->gso_segs = 1;
6493
6494 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6495 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6496
6497 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6498 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6499 &adapter->state)) {
6500 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6501 tx_flags |= IGB_TX_FLAGS_TSTAMP;
6502
6503 adapter->ptp_tx_skb = skb_get(skb);
6504 adapter->ptp_tx_start = jiffies;
6505 if (adapter->hw.mac.type == e1000_82576)
6506 schedule_work(&adapter->ptp_tx_work);
6507 } else {
6508 adapter->tx_hwtstamp_skipped++;
6509 }
6510 }
6511
6512 if (skb_vlan_tag_present(skb)) {
6513 tx_flags |= IGB_TX_FLAGS_VLAN;
6514 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6515 }
6516
6517 /* record initial flags and protocol */
6518 first->tx_flags = tx_flags;
6519 first->protocol = protocol;
6520
6521 tso = igb_tso(tx_ring, first, &hdr_len);
6522 if (tso < 0)
6523 goto out_drop;
6524 else if (!tso)
6525 igb_tx_csum(tx_ring, first);
6526
6527 if (igb_tx_map(tx_ring, first, hdr_len))
6528 goto cleanup_tx_tstamp;
6529
6530 return NETDEV_TX_OK;
6531
6532 out_drop:
6533 dev_kfree_skb_any(first->skb);
6534 first->skb = NULL;
6535 cleanup_tx_tstamp:
6536 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6537 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6538
6539 dev_kfree_skb_any(adapter->ptp_tx_skb);
6540 adapter->ptp_tx_skb = NULL;
6541 if (adapter->hw.mac.type == e1000_82576)
6542 cancel_work_sync(&adapter->ptp_tx_work);
6543 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6544 }
6545
6546 return NETDEV_TX_OK;
6547 }
6548
igb_tx_queue_mapping(struct igb_adapter * adapter,struct sk_buff * skb)6549 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6550 struct sk_buff *skb)
6551 {
6552 unsigned int r_idx = skb->queue_mapping;
6553
6554 if (r_idx >= adapter->num_tx_queues)
6555 r_idx = r_idx % adapter->num_tx_queues;
6556
6557 return adapter->tx_ring[r_idx];
6558 }
6559
igb_xmit_frame(struct sk_buff * skb,struct net_device * netdev)6560 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6561 struct net_device *netdev)
6562 {
6563 struct igb_adapter *adapter = netdev_priv(netdev);
6564
6565 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6566 * in order to meet this minimum size requirement.
6567 */
6568 if (skb_put_padto(skb, 17))
6569 return NETDEV_TX_OK;
6570
6571 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6572 }
6573
6574 /**
6575 * igb_tx_timeout - Respond to a Tx Hang
6576 * @netdev: network interface device structure
6577 * @txqueue: number of the Tx queue that hung (unused)
6578 **/
igb_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)6579 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6580 {
6581 struct igb_adapter *adapter = netdev_priv(netdev);
6582 struct e1000_hw *hw = &adapter->hw;
6583
6584 /* Do the reset outside of interrupt context */
6585 adapter->tx_timeout_count++;
6586
6587 if (hw->mac.type >= e1000_82580)
6588 hw->dev_spec._82575.global_device_reset = true;
6589
6590 schedule_work(&adapter->reset_task);
6591 wr32(E1000_EICS,
6592 (adapter->eims_enable_mask & ~adapter->eims_other));
6593 }
6594
igb_reset_task(struct work_struct * work)6595 static void igb_reset_task(struct work_struct *work)
6596 {
6597 struct igb_adapter *adapter;
6598 adapter = container_of(work, struct igb_adapter, reset_task);
6599
6600 rtnl_lock();
6601 /* If we're already down or resetting, just bail */
6602 if (test_bit(__IGB_DOWN, &adapter->state) ||
6603 test_bit(__IGB_RESETTING, &adapter->state)) {
6604 rtnl_unlock();
6605 return;
6606 }
6607
6608 igb_dump(adapter);
6609 netdev_err(adapter->netdev, "Reset adapter\n");
6610 igb_reinit_locked(adapter);
6611 rtnl_unlock();
6612 }
6613
6614 /**
6615 * igb_get_stats64 - Get System Network Statistics
6616 * @netdev: network interface device structure
6617 * @stats: rtnl_link_stats64 pointer
6618 **/
igb_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)6619 static void igb_get_stats64(struct net_device *netdev,
6620 struct rtnl_link_stats64 *stats)
6621 {
6622 struct igb_adapter *adapter = netdev_priv(netdev);
6623
6624 spin_lock(&adapter->stats64_lock);
6625 igb_update_stats(adapter);
6626 memcpy(stats, &adapter->stats64, sizeof(*stats));
6627 spin_unlock(&adapter->stats64_lock);
6628 }
6629
6630 /**
6631 * igb_change_mtu - Change the Maximum Transfer Unit
6632 * @netdev: network interface device structure
6633 * @new_mtu: new value for maximum frame size
6634 *
6635 * Returns 0 on success, negative on failure
6636 **/
igb_change_mtu(struct net_device * netdev,int new_mtu)6637 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6638 {
6639 struct igb_adapter *adapter = netdev_priv(netdev);
6640 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6641
6642 if (adapter->xdp_prog) {
6643 int i;
6644
6645 for (i = 0; i < adapter->num_rx_queues; i++) {
6646 struct igb_ring *ring = adapter->rx_ring[i];
6647
6648 if (max_frame > igb_rx_bufsz(ring)) {
6649 netdev_warn(adapter->netdev,
6650 "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6651 max_frame);
6652 return -EINVAL;
6653 }
6654 }
6655 }
6656
6657 /* adjust max frame to be at least the size of a standard frame */
6658 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6659 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6660
6661 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6662 usleep_range(1000, 2000);
6663
6664 /* igb_down has a dependency on max_frame_size */
6665 adapter->max_frame_size = max_frame;
6666
6667 if (netif_running(netdev))
6668 igb_down(adapter);
6669
6670 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6671 netdev->mtu, new_mtu);
6672 netdev->mtu = new_mtu;
6673
6674 if (netif_running(netdev))
6675 igb_up(adapter);
6676 else
6677 igb_reset(adapter);
6678
6679 clear_bit(__IGB_RESETTING, &adapter->state);
6680
6681 return 0;
6682 }
6683
6684 /**
6685 * igb_update_stats - Update the board statistics counters
6686 * @adapter: board private structure
6687 **/
igb_update_stats(struct igb_adapter * adapter)6688 void igb_update_stats(struct igb_adapter *adapter)
6689 {
6690 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6691 struct e1000_hw *hw = &adapter->hw;
6692 struct pci_dev *pdev = adapter->pdev;
6693 u32 reg, mpc;
6694 int i;
6695 u64 bytes, packets;
6696 unsigned int start;
6697 u64 _bytes, _packets;
6698
6699 /* Prevent stats update while adapter is being reset, or if the pci
6700 * connection is down.
6701 */
6702 if (adapter->link_speed == 0)
6703 return;
6704 if (pci_channel_offline(pdev))
6705 return;
6706
6707 bytes = 0;
6708 packets = 0;
6709
6710 rcu_read_lock();
6711 for (i = 0; i < adapter->num_rx_queues; i++) {
6712 struct igb_ring *ring = adapter->rx_ring[i];
6713 u32 rqdpc = rd32(E1000_RQDPC(i));
6714 if (hw->mac.type >= e1000_i210)
6715 wr32(E1000_RQDPC(i), 0);
6716
6717 if (rqdpc) {
6718 ring->rx_stats.drops += rqdpc;
6719 net_stats->rx_fifo_errors += rqdpc;
6720 }
6721
6722 do {
6723 start = u64_stats_fetch_begin(&ring->rx_syncp);
6724 _bytes = ring->rx_stats.bytes;
6725 _packets = ring->rx_stats.packets;
6726 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));
6727 bytes += _bytes;
6728 packets += _packets;
6729 }
6730
6731 net_stats->rx_bytes = bytes;
6732 net_stats->rx_packets = packets;
6733
6734 bytes = 0;
6735 packets = 0;
6736 for (i = 0; i < adapter->num_tx_queues; i++) {
6737 struct igb_ring *ring = adapter->tx_ring[i];
6738 do {
6739 start = u64_stats_fetch_begin(&ring->tx_syncp);
6740 _bytes = ring->tx_stats.bytes;
6741 _packets = ring->tx_stats.packets;
6742 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));
6743 bytes += _bytes;
6744 packets += _packets;
6745 }
6746 net_stats->tx_bytes = bytes;
6747 net_stats->tx_packets = packets;
6748 rcu_read_unlock();
6749
6750 /* read stats registers */
6751 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6752 adapter->stats.gprc += rd32(E1000_GPRC);
6753 adapter->stats.gorc += rd32(E1000_GORCL);
6754 rd32(E1000_GORCH); /* clear GORCL */
6755 adapter->stats.bprc += rd32(E1000_BPRC);
6756 adapter->stats.mprc += rd32(E1000_MPRC);
6757 adapter->stats.roc += rd32(E1000_ROC);
6758
6759 adapter->stats.prc64 += rd32(E1000_PRC64);
6760 adapter->stats.prc127 += rd32(E1000_PRC127);
6761 adapter->stats.prc255 += rd32(E1000_PRC255);
6762 adapter->stats.prc511 += rd32(E1000_PRC511);
6763 adapter->stats.prc1023 += rd32(E1000_PRC1023);
6764 adapter->stats.prc1522 += rd32(E1000_PRC1522);
6765 adapter->stats.symerrs += rd32(E1000_SYMERRS);
6766 adapter->stats.sec += rd32(E1000_SEC);
6767
6768 mpc = rd32(E1000_MPC);
6769 adapter->stats.mpc += mpc;
6770 net_stats->rx_fifo_errors += mpc;
6771 adapter->stats.scc += rd32(E1000_SCC);
6772 adapter->stats.ecol += rd32(E1000_ECOL);
6773 adapter->stats.mcc += rd32(E1000_MCC);
6774 adapter->stats.latecol += rd32(E1000_LATECOL);
6775 adapter->stats.dc += rd32(E1000_DC);
6776 adapter->stats.rlec += rd32(E1000_RLEC);
6777 adapter->stats.xonrxc += rd32(E1000_XONRXC);
6778 adapter->stats.xontxc += rd32(E1000_XONTXC);
6779 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6780 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6781 adapter->stats.fcruc += rd32(E1000_FCRUC);
6782 adapter->stats.gptc += rd32(E1000_GPTC);
6783 adapter->stats.gotc += rd32(E1000_GOTCL);
6784 rd32(E1000_GOTCH); /* clear GOTCL */
6785 adapter->stats.rnbc += rd32(E1000_RNBC);
6786 adapter->stats.ruc += rd32(E1000_RUC);
6787 adapter->stats.rfc += rd32(E1000_RFC);
6788 adapter->stats.rjc += rd32(E1000_RJC);
6789 adapter->stats.tor += rd32(E1000_TORH);
6790 adapter->stats.tot += rd32(E1000_TOTH);
6791 adapter->stats.tpr += rd32(E1000_TPR);
6792
6793 adapter->stats.ptc64 += rd32(E1000_PTC64);
6794 adapter->stats.ptc127 += rd32(E1000_PTC127);
6795 adapter->stats.ptc255 += rd32(E1000_PTC255);
6796 adapter->stats.ptc511 += rd32(E1000_PTC511);
6797 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6798 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6799
6800 adapter->stats.mptc += rd32(E1000_MPTC);
6801 adapter->stats.bptc += rd32(E1000_BPTC);
6802
6803 adapter->stats.tpt += rd32(E1000_TPT);
6804 adapter->stats.colc += rd32(E1000_COLC);
6805
6806 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6807 /* read internal phy specific stats */
6808 reg = rd32(E1000_CTRL_EXT);
6809 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6810 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6811
6812 /* this stat has invalid values on i210/i211 */
6813 if ((hw->mac.type != e1000_i210) &&
6814 (hw->mac.type != e1000_i211))
6815 adapter->stats.tncrs += rd32(E1000_TNCRS);
6816 }
6817
6818 adapter->stats.tsctc += rd32(E1000_TSCTC);
6819 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6820
6821 adapter->stats.iac += rd32(E1000_IAC);
6822 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6823 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6824 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6825 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6826 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6827 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6828 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6829 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6830
6831 /* Fill out the OS statistics structure */
6832 net_stats->multicast = adapter->stats.mprc;
6833 net_stats->collisions = adapter->stats.colc;
6834
6835 /* Rx Errors */
6836
6837 /* RLEC on some newer hardware can be incorrect so build
6838 * our own version based on RUC and ROC
6839 */
6840 net_stats->rx_errors = adapter->stats.rxerrc +
6841 adapter->stats.crcerrs + adapter->stats.algnerrc +
6842 adapter->stats.ruc + adapter->stats.roc +
6843 adapter->stats.cexterr;
6844 net_stats->rx_length_errors = adapter->stats.ruc +
6845 adapter->stats.roc;
6846 net_stats->rx_crc_errors = adapter->stats.crcerrs;
6847 net_stats->rx_frame_errors = adapter->stats.algnerrc;
6848 net_stats->rx_missed_errors = adapter->stats.mpc;
6849
6850 /* Tx Errors */
6851 net_stats->tx_errors = adapter->stats.ecol +
6852 adapter->stats.latecol;
6853 net_stats->tx_aborted_errors = adapter->stats.ecol;
6854 net_stats->tx_window_errors = adapter->stats.latecol;
6855 net_stats->tx_carrier_errors = adapter->stats.tncrs;
6856
6857 /* Tx Dropped needs to be maintained elsewhere */
6858
6859 /* Management Stats */
6860 adapter->stats.mgptc += rd32(E1000_MGTPTC);
6861 adapter->stats.mgprc += rd32(E1000_MGTPRC);
6862 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6863
6864 /* OS2BMC Stats */
6865 reg = rd32(E1000_MANC);
6866 if (reg & E1000_MANC_EN_BMC2OS) {
6867 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6868 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6869 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6870 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6871 }
6872 }
6873
igb_perout(struct igb_adapter * adapter,int tsintr_tt)6874 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt)
6875 {
6876 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt);
6877 struct e1000_hw *hw = &adapter->hw;
6878 struct timespec64 ts;
6879 u32 tsauxc;
6880
6881 if (pin < 0 || pin >= IGB_N_SDP)
6882 return;
6883
6884 spin_lock(&adapter->tmreg_lock);
6885
6886 if (hw->mac.type == e1000_82580 ||
6887 hw->mac.type == e1000_i354 ||
6888 hw->mac.type == e1000_i350) {
6889 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period);
6890 u32 systiml, systimh, level_mask, level, rem;
6891 u64 systim, now;
6892
6893 /* read systim registers in sequence */
6894 rd32(E1000_SYSTIMR);
6895 systiml = rd32(E1000_SYSTIML);
6896 systimh = rd32(E1000_SYSTIMH);
6897 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
6898 now = timecounter_cyc2time(&adapter->tc, systim);
6899
6900 if (pin < 2) {
6901 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000;
6902 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
6903 } else {
6904 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40;
6905 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
6906 }
6907
6908 div_u64_rem(now, ns, &rem);
6909 systim = systim + (ns - rem);
6910
6911 /* synchronize pin level with rising/falling edges */
6912 div_u64_rem(now, ns << 1, &rem);
6913 if (rem < ns) {
6914 /* first half of period */
6915 if (level == 0) {
6916 /* output is already low, skip this period */
6917 systim += ns;
6918 pr_notice("igb: periodic output on %s missed falling edge\n",
6919 adapter->sdp_config[pin].name);
6920 }
6921 } else {
6922 /* second half of period */
6923 if (level == 1) {
6924 /* output is already high, skip this period */
6925 systim += ns;
6926 pr_notice("igb: periodic output on %s missed rising edge\n",
6927 adapter->sdp_config[pin].name);
6928 }
6929 }
6930
6931 /* for this chip family tv_sec is the upper part of the binary value,
6932 * so not seconds
6933 */
6934 ts.tv_nsec = (u32)systim;
6935 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF;
6936 } else {
6937 ts = timespec64_add(adapter->perout[tsintr_tt].start,
6938 adapter->perout[tsintr_tt].period);
6939 }
6940
6941 /* u32 conversion of tv_sec is safe until y2106 */
6942 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
6943 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec);
6944 tsauxc = rd32(E1000_TSAUXC);
6945 tsauxc |= TSAUXC_EN_TT0;
6946 wr32(E1000_TSAUXC, tsauxc);
6947 adapter->perout[tsintr_tt].start = ts;
6948
6949 spin_unlock(&adapter->tmreg_lock);
6950 }
6951
igb_extts(struct igb_adapter * adapter,int tsintr_tt)6952 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt)
6953 {
6954 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt);
6955 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0;
6956 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0;
6957 struct e1000_hw *hw = &adapter->hw;
6958 struct ptp_clock_event event;
6959 struct timespec64 ts;
6960 unsigned long flags;
6961
6962 if (pin < 0 || pin >= IGB_N_SDP)
6963 return;
6964
6965 if (hw->mac.type == e1000_82580 ||
6966 hw->mac.type == e1000_i354 ||
6967 hw->mac.type == e1000_i350) {
6968 u64 ns = rd32(auxstmpl);
6969
6970 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32;
6971 spin_lock_irqsave(&adapter->tmreg_lock, flags);
6972 ns = timecounter_cyc2time(&adapter->tc, ns);
6973 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
6974 ts = ns_to_timespec64(ns);
6975 } else {
6976 ts.tv_nsec = rd32(auxstmpl);
6977 ts.tv_sec = rd32(auxstmph);
6978 }
6979
6980 event.type = PTP_CLOCK_EXTTS;
6981 event.index = tsintr_tt;
6982 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec;
6983 ptp_clock_event(adapter->ptp_clock, &event);
6984 }
6985
igb_tsync_interrupt(struct igb_adapter * adapter)6986 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6987 {
6988 struct e1000_hw *hw = &adapter->hw;
6989 u32 tsicr = rd32(E1000_TSICR);
6990 struct ptp_clock_event event;
6991
6992 if (tsicr & TSINTR_SYS_WRAP) {
6993 event.type = PTP_CLOCK_PPS;
6994 if (adapter->ptp_caps.pps)
6995 ptp_clock_event(adapter->ptp_clock, &event);
6996 }
6997
6998 if (tsicr & E1000_TSICR_TXTS) {
6999 /* retrieve hardware timestamp */
7000 schedule_work(&adapter->ptp_tx_work);
7001 }
7002
7003 if (tsicr & TSINTR_TT0)
7004 igb_perout(adapter, 0);
7005
7006 if (tsicr & TSINTR_TT1)
7007 igb_perout(adapter, 1);
7008
7009 if (tsicr & TSINTR_AUTT0)
7010 igb_extts(adapter, 0);
7011
7012 if (tsicr & TSINTR_AUTT1)
7013 igb_extts(adapter, 1);
7014 }
7015
igb_msix_other(int irq,void * data)7016 static irqreturn_t igb_msix_other(int irq, void *data)
7017 {
7018 struct igb_adapter *adapter = data;
7019 struct e1000_hw *hw = &adapter->hw;
7020 u32 icr = rd32(E1000_ICR);
7021 /* reading ICR causes bit 31 of EICR to be cleared */
7022
7023 if (icr & E1000_ICR_DRSTA)
7024 schedule_work(&adapter->reset_task);
7025
7026 if (icr & E1000_ICR_DOUTSYNC) {
7027 /* HW is reporting DMA is out of sync */
7028 adapter->stats.doosync++;
7029 /* The DMA Out of Sync is also indication of a spoof event
7030 * in IOV mode. Check the Wrong VM Behavior register to
7031 * see if it is really a spoof event.
7032 */
7033 igb_check_wvbr(adapter);
7034 }
7035
7036 /* Check for a mailbox event */
7037 if (icr & E1000_ICR_VMMB)
7038 igb_msg_task(adapter);
7039
7040 if (icr & E1000_ICR_LSC) {
7041 hw->mac.get_link_status = 1;
7042 /* guard against interrupt when we're going down */
7043 if (!test_bit(__IGB_DOWN, &adapter->state))
7044 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7045 }
7046
7047 if (icr & E1000_ICR_TS)
7048 igb_tsync_interrupt(adapter);
7049
7050 wr32(E1000_EIMS, adapter->eims_other);
7051
7052 return IRQ_HANDLED;
7053 }
7054
igb_write_itr(struct igb_q_vector * q_vector)7055 static void igb_write_itr(struct igb_q_vector *q_vector)
7056 {
7057 struct igb_adapter *adapter = q_vector->adapter;
7058 u32 itr_val = q_vector->itr_val & 0x7FFC;
7059
7060 if (!q_vector->set_itr)
7061 return;
7062
7063 if (!itr_val)
7064 itr_val = 0x4;
7065
7066 if (adapter->hw.mac.type == e1000_82575)
7067 itr_val |= itr_val << 16;
7068 else
7069 itr_val |= E1000_EITR_CNT_IGNR;
7070
7071 writel(itr_val, q_vector->itr_register);
7072 q_vector->set_itr = 0;
7073 }
7074
igb_msix_ring(int irq,void * data)7075 static irqreturn_t igb_msix_ring(int irq, void *data)
7076 {
7077 struct igb_q_vector *q_vector = data;
7078
7079 /* Write the ITR value calculated from the previous interrupt. */
7080 igb_write_itr(q_vector);
7081
7082 napi_schedule(&q_vector->napi);
7083
7084 return IRQ_HANDLED;
7085 }
7086
7087 #ifdef CONFIG_IGB_DCA
igb_update_tx_dca(struct igb_adapter * adapter,struct igb_ring * tx_ring,int cpu)7088 static void igb_update_tx_dca(struct igb_adapter *adapter,
7089 struct igb_ring *tx_ring,
7090 int cpu)
7091 {
7092 struct e1000_hw *hw = &adapter->hw;
7093 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
7094
7095 if (hw->mac.type != e1000_82575)
7096 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
7097
7098 /* We can enable relaxed ordering for reads, but not writes when
7099 * DCA is enabled. This is due to a known issue in some chipsets
7100 * which will cause the DCA tag to be cleared.
7101 */
7102 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
7103 E1000_DCA_TXCTRL_DATA_RRO_EN |
7104 E1000_DCA_TXCTRL_DESC_DCA_EN;
7105
7106 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
7107 }
7108
igb_update_rx_dca(struct igb_adapter * adapter,struct igb_ring * rx_ring,int cpu)7109 static void igb_update_rx_dca(struct igb_adapter *adapter,
7110 struct igb_ring *rx_ring,
7111 int cpu)
7112 {
7113 struct e1000_hw *hw = &adapter->hw;
7114 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
7115
7116 if (hw->mac.type != e1000_82575)
7117 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
7118
7119 /* We can enable relaxed ordering for reads, but not writes when
7120 * DCA is enabled. This is due to a known issue in some chipsets
7121 * which will cause the DCA tag to be cleared.
7122 */
7123 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
7124 E1000_DCA_RXCTRL_DESC_DCA_EN;
7125
7126 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
7127 }
7128
igb_update_dca(struct igb_q_vector * q_vector)7129 static void igb_update_dca(struct igb_q_vector *q_vector)
7130 {
7131 struct igb_adapter *adapter = q_vector->adapter;
7132 int cpu = get_cpu();
7133
7134 if (q_vector->cpu == cpu)
7135 goto out_no_update;
7136
7137 if (q_vector->tx.ring)
7138 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
7139
7140 if (q_vector->rx.ring)
7141 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
7142
7143 q_vector->cpu = cpu;
7144 out_no_update:
7145 put_cpu();
7146 }
7147
igb_setup_dca(struct igb_adapter * adapter)7148 static void igb_setup_dca(struct igb_adapter *adapter)
7149 {
7150 struct e1000_hw *hw = &adapter->hw;
7151 int i;
7152
7153 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
7154 return;
7155
7156 /* Always use CB2 mode, difference is masked in the CB driver. */
7157 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
7158
7159 for (i = 0; i < adapter->num_q_vectors; i++) {
7160 adapter->q_vector[i]->cpu = -1;
7161 igb_update_dca(adapter->q_vector[i]);
7162 }
7163 }
7164
__igb_notify_dca(struct device * dev,void * data)7165 static int __igb_notify_dca(struct device *dev, void *data)
7166 {
7167 struct net_device *netdev = dev_get_drvdata(dev);
7168 struct igb_adapter *adapter = netdev_priv(netdev);
7169 struct pci_dev *pdev = adapter->pdev;
7170 struct e1000_hw *hw = &adapter->hw;
7171 unsigned long event = *(unsigned long *)data;
7172
7173 switch (event) {
7174 case DCA_PROVIDER_ADD:
7175 /* if already enabled, don't do it again */
7176 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
7177 break;
7178 if (dca_add_requester(dev) == 0) {
7179 adapter->flags |= IGB_FLAG_DCA_ENABLED;
7180 dev_info(&pdev->dev, "DCA enabled\n");
7181 igb_setup_dca(adapter);
7182 break;
7183 }
7184 fallthrough; /* since DCA is disabled. */
7185 case DCA_PROVIDER_REMOVE:
7186 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
7187 /* without this a class_device is left
7188 * hanging around in the sysfs model
7189 */
7190 dca_remove_requester(dev);
7191 dev_info(&pdev->dev, "DCA disabled\n");
7192 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
7193 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
7194 }
7195 break;
7196 }
7197
7198 return 0;
7199 }
7200
igb_notify_dca(struct notifier_block * nb,unsigned long event,void * p)7201 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
7202 void *p)
7203 {
7204 int ret_val;
7205
7206 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7207 __igb_notify_dca);
7208
7209 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7210 }
7211 #endif /* CONFIG_IGB_DCA */
7212
7213 #ifdef CONFIG_PCI_IOV
igb_vf_configure(struct igb_adapter * adapter,int vf)7214 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7215 {
7216 unsigned char mac_addr[ETH_ALEN];
7217
7218 eth_zero_addr(mac_addr);
7219 igb_set_vf_mac(adapter, vf, mac_addr);
7220
7221 /* By default spoof check is enabled for all VFs */
7222 adapter->vf_data[vf].spoofchk_enabled = true;
7223
7224 /* By default VFs are not trusted */
7225 adapter->vf_data[vf].trusted = false;
7226
7227 return 0;
7228 }
7229
7230 #endif
igb_ping_all_vfs(struct igb_adapter * adapter)7231 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7232 {
7233 struct e1000_hw *hw = &adapter->hw;
7234 u32 ping;
7235 int i;
7236
7237 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7238 ping = E1000_PF_CONTROL_MSG;
7239 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7240 ping |= E1000_VT_MSGTYPE_CTS;
7241 igb_write_mbx(hw, &ping, 1, i);
7242 }
7243 }
7244
igb_set_vf_promisc(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7245 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7246 {
7247 struct e1000_hw *hw = &adapter->hw;
7248 u32 vmolr = rd32(E1000_VMOLR(vf));
7249 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7250
7251 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7252 IGB_VF_FLAG_MULTI_PROMISC);
7253 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7254
7255 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7256 vmolr |= E1000_VMOLR_MPME;
7257 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7258 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7259 } else {
7260 /* if we have hashes and we are clearing a multicast promisc
7261 * flag we need to write the hashes to the MTA as this step
7262 * was previously skipped
7263 */
7264 if (vf_data->num_vf_mc_hashes > 30) {
7265 vmolr |= E1000_VMOLR_MPME;
7266 } else if (vf_data->num_vf_mc_hashes) {
7267 int j;
7268
7269 vmolr |= E1000_VMOLR_ROMPE;
7270 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7271 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7272 }
7273 }
7274
7275 wr32(E1000_VMOLR(vf), vmolr);
7276
7277 /* there are flags left unprocessed, likely not supported */
7278 if (*msgbuf & E1000_VT_MSGINFO_MASK)
7279 return -EINVAL;
7280
7281 return 0;
7282 }
7283
igb_set_vf_multicasts(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7284 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7285 u32 *msgbuf, u32 vf)
7286 {
7287 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7288 u16 *hash_list = (u16 *)&msgbuf[1];
7289 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7290 int i;
7291
7292 /* salt away the number of multicast addresses assigned
7293 * to this VF for later use to restore when the PF multi cast
7294 * list changes
7295 */
7296 vf_data->num_vf_mc_hashes = n;
7297
7298 /* only up to 30 hash values supported */
7299 if (n > 30)
7300 n = 30;
7301
7302 /* store the hashes for later use */
7303 for (i = 0; i < n; i++)
7304 vf_data->vf_mc_hashes[i] = hash_list[i];
7305
7306 /* Flush and reset the mta with the new values */
7307 igb_set_rx_mode(adapter->netdev);
7308
7309 return 0;
7310 }
7311
igb_restore_vf_multicasts(struct igb_adapter * adapter)7312 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7313 {
7314 struct e1000_hw *hw = &adapter->hw;
7315 struct vf_data_storage *vf_data;
7316 int i, j;
7317
7318 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7319 u32 vmolr = rd32(E1000_VMOLR(i));
7320
7321 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7322
7323 vf_data = &adapter->vf_data[i];
7324
7325 if ((vf_data->num_vf_mc_hashes > 30) ||
7326 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7327 vmolr |= E1000_VMOLR_MPME;
7328 } else if (vf_data->num_vf_mc_hashes) {
7329 vmolr |= E1000_VMOLR_ROMPE;
7330 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7331 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7332 }
7333 wr32(E1000_VMOLR(i), vmolr);
7334 }
7335 }
7336
igb_clear_vf_vfta(struct igb_adapter * adapter,u32 vf)7337 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7338 {
7339 struct e1000_hw *hw = &adapter->hw;
7340 u32 pool_mask, vlvf_mask, i;
7341
7342 /* create mask for VF and other pools */
7343 pool_mask = E1000_VLVF_POOLSEL_MASK;
7344 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7345
7346 /* drop PF from pool bits */
7347 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7348 adapter->vfs_allocated_count);
7349
7350 /* Find the vlan filter for this id */
7351 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7352 u32 vlvf = rd32(E1000_VLVF(i));
7353 u32 vfta_mask, vid, vfta;
7354
7355 /* remove the vf from the pool */
7356 if (!(vlvf & vlvf_mask))
7357 continue;
7358
7359 /* clear out bit from VLVF */
7360 vlvf ^= vlvf_mask;
7361
7362 /* if other pools are present, just remove ourselves */
7363 if (vlvf & pool_mask)
7364 goto update_vlvfb;
7365
7366 /* if PF is present, leave VFTA */
7367 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7368 goto update_vlvf;
7369
7370 vid = vlvf & E1000_VLVF_VLANID_MASK;
7371 vfta_mask = BIT(vid % 32);
7372
7373 /* clear bit from VFTA */
7374 vfta = adapter->shadow_vfta[vid / 32];
7375 if (vfta & vfta_mask)
7376 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7377 update_vlvf:
7378 /* clear pool selection enable */
7379 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7380 vlvf &= E1000_VLVF_POOLSEL_MASK;
7381 else
7382 vlvf = 0;
7383 update_vlvfb:
7384 /* clear pool bits */
7385 wr32(E1000_VLVF(i), vlvf);
7386 }
7387 }
7388
igb_find_vlvf_entry(struct e1000_hw * hw,u32 vlan)7389 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7390 {
7391 u32 vlvf;
7392 int idx;
7393
7394 /* short cut the special case */
7395 if (vlan == 0)
7396 return 0;
7397
7398 /* Search for the VLAN id in the VLVF entries */
7399 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7400 vlvf = rd32(E1000_VLVF(idx));
7401 if ((vlvf & VLAN_VID_MASK) == vlan)
7402 break;
7403 }
7404
7405 return idx;
7406 }
7407
igb_update_pf_vlvf(struct igb_adapter * adapter,u32 vid)7408 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7409 {
7410 struct e1000_hw *hw = &adapter->hw;
7411 u32 bits, pf_id;
7412 int idx;
7413
7414 idx = igb_find_vlvf_entry(hw, vid);
7415 if (!idx)
7416 return;
7417
7418 /* See if any other pools are set for this VLAN filter
7419 * entry other than the PF.
7420 */
7421 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7422 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7423 bits &= rd32(E1000_VLVF(idx));
7424
7425 /* Disable the filter so this falls into the default pool. */
7426 if (!bits) {
7427 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7428 wr32(E1000_VLVF(idx), BIT(pf_id));
7429 else
7430 wr32(E1000_VLVF(idx), 0);
7431 }
7432 }
7433
igb_set_vf_vlan(struct igb_adapter * adapter,u32 vid,bool add,u32 vf)7434 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7435 bool add, u32 vf)
7436 {
7437 int pf_id = adapter->vfs_allocated_count;
7438 struct e1000_hw *hw = &adapter->hw;
7439 int err;
7440
7441 /* If VLAN overlaps with one the PF is currently monitoring make
7442 * sure that we are able to allocate a VLVF entry. This may be
7443 * redundant but it guarantees PF will maintain visibility to
7444 * the VLAN.
7445 */
7446 if (add && test_bit(vid, adapter->active_vlans)) {
7447 err = igb_vfta_set(hw, vid, pf_id, true, false);
7448 if (err)
7449 return err;
7450 }
7451
7452 err = igb_vfta_set(hw, vid, vf, add, false);
7453
7454 if (add && !err)
7455 return err;
7456
7457 /* If we failed to add the VF VLAN or we are removing the VF VLAN
7458 * we may need to drop the PF pool bit in order to allow us to free
7459 * up the VLVF resources.
7460 */
7461 if (test_bit(vid, adapter->active_vlans) ||
7462 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7463 igb_update_pf_vlvf(adapter, vid);
7464
7465 return err;
7466 }
7467
igb_set_vmvir(struct igb_adapter * adapter,u32 vid,u32 vf)7468 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7469 {
7470 struct e1000_hw *hw = &adapter->hw;
7471
7472 if (vid)
7473 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7474 else
7475 wr32(E1000_VMVIR(vf), 0);
7476 }
7477
igb_enable_port_vlan(struct igb_adapter * adapter,int vf,u16 vlan,u8 qos)7478 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7479 u16 vlan, u8 qos)
7480 {
7481 int err;
7482
7483 err = igb_set_vf_vlan(adapter, vlan, true, vf);
7484 if (err)
7485 return err;
7486
7487 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7488 igb_set_vmolr(adapter, vf, !vlan);
7489
7490 /* revoke access to previous VLAN */
7491 if (vlan != adapter->vf_data[vf].pf_vlan)
7492 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7493 false, vf);
7494
7495 adapter->vf_data[vf].pf_vlan = vlan;
7496 adapter->vf_data[vf].pf_qos = qos;
7497 igb_set_vf_vlan_strip(adapter, vf, true);
7498 dev_info(&adapter->pdev->dev,
7499 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7500 if (test_bit(__IGB_DOWN, &adapter->state)) {
7501 dev_warn(&adapter->pdev->dev,
7502 "The VF VLAN has been set, but the PF device is not up.\n");
7503 dev_warn(&adapter->pdev->dev,
7504 "Bring the PF device up before attempting to use the VF device.\n");
7505 }
7506
7507 return err;
7508 }
7509
igb_disable_port_vlan(struct igb_adapter * adapter,int vf)7510 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7511 {
7512 /* Restore tagless access via VLAN 0 */
7513 igb_set_vf_vlan(adapter, 0, true, vf);
7514
7515 igb_set_vmvir(adapter, 0, vf);
7516 igb_set_vmolr(adapter, vf, true);
7517
7518 /* Remove any PF assigned VLAN */
7519 if (adapter->vf_data[vf].pf_vlan)
7520 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7521 false, vf);
7522
7523 adapter->vf_data[vf].pf_vlan = 0;
7524 adapter->vf_data[vf].pf_qos = 0;
7525 igb_set_vf_vlan_strip(adapter, vf, false);
7526
7527 return 0;
7528 }
7529
igb_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)7530 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7531 u16 vlan, u8 qos, __be16 vlan_proto)
7532 {
7533 struct igb_adapter *adapter = netdev_priv(netdev);
7534
7535 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7536 return -EINVAL;
7537
7538 if (vlan_proto != htons(ETH_P_8021Q))
7539 return -EPROTONOSUPPORT;
7540
7541 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7542 igb_disable_port_vlan(adapter, vf);
7543 }
7544
igb_set_vf_vlan_msg(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7545 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7546 {
7547 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7548 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7549 int ret;
7550
7551 if (adapter->vf_data[vf].pf_vlan)
7552 return -1;
7553
7554 /* VLAN 0 is a special case, don't allow it to be removed */
7555 if (!vid && !add)
7556 return 0;
7557
7558 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7559 if (!ret)
7560 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7561 return ret;
7562 }
7563
igb_vf_reset(struct igb_adapter * adapter,u32 vf)7564 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7565 {
7566 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7567
7568 /* clear flags - except flag that indicates PF has set the MAC */
7569 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7570 vf_data->last_nack = jiffies;
7571
7572 /* reset vlans for device */
7573 igb_clear_vf_vfta(adapter, vf);
7574 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7575 igb_set_vmvir(adapter, vf_data->pf_vlan |
7576 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7577 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7578 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7579
7580 /* reset multicast table array for vf */
7581 adapter->vf_data[vf].num_vf_mc_hashes = 0;
7582
7583 /* Flush and reset the mta with the new values */
7584 igb_set_rx_mode(adapter->netdev);
7585 }
7586
igb_vf_reset_event(struct igb_adapter * adapter,u32 vf)7587 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7588 {
7589 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7590
7591 /* clear mac address as we were hotplug removed/added */
7592 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7593 eth_zero_addr(vf_mac);
7594
7595 /* process remaining reset events */
7596 igb_vf_reset(adapter, vf);
7597 }
7598
igb_vf_reset_msg(struct igb_adapter * adapter,u32 vf)7599 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7600 {
7601 struct e1000_hw *hw = &adapter->hw;
7602 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7603 u32 reg, msgbuf[3] = {};
7604 u8 *addr = (u8 *)(&msgbuf[1]);
7605
7606 /* process all the same items cleared in a function level reset */
7607 igb_vf_reset(adapter, vf);
7608
7609 /* set vf mac address */
7610 igb_set_vf_mac(adapter, vf, vf_mac);
7611
7612 /* enable transmit and receive for vf */
7613 reg = rd32(E1000_VFTE);
7614 wr32(E1000_VFTE, reg | BIT(vf));
7615 reg = rd32(E1000_VFRE);
7616 wr32(E1000_VFRE, reg | BIT(vf));
7617
7618 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7619
7620 /* reply to reset with ack and vf mac address */
7621 if (!is_zero_ether_addr(vf_mac)) {
7622 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7623 memcpy(addr, vf_mac, ETH_ALEN);
7624 } else {
7625 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7626 }
7627 igb_write_mbx(hw, msgbuf, 3, vf);
7628 }
7629
igb_flush_mac_table(struct igb_adapter * adapter)7630 static void igb_flush_mac_table(struct igb_adapter *adapter)
7631 {
7632 struct e1000_hw *hw = &adapter->hw;
7633 int i;
7634
7635 for (i = 0; i < hw->mac.rar_entry_count; i++) {
7636 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7637 eth_zero_addr(adapter->mac_table[i].addr);
7638 adapter->mac_table[i].queue = 0;
7639 igb_rar_set_index(adapter, i);
7640 }
7641 }
7642
igb_available_rars(struct igb_adapter * adapter,u8 queue)7643 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7644 {
7645 struct e1000_hw *hw = &adapter->hw;
7646 /* do not count rar entries reserved for VFs MAC addresses */
7647 int rar_entries = hw->mac.rar_entry_count -
7648 adapter->vfs_allocated_count;
7649 int i, count = 0;
7650
7651 for (i = 0; i < rar_entries; i++) {
7652 /* do not count default entries */
7653 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7654 continue;
7655
7656 /* do not count "in use" entries for different queues */
7657 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7658 (adapter->mac_table[i].queue != queue))
7659 continue;
7660
7661 count++;
7662 }
7663
7664 return count;
7665 }
7666
7667 /* Set default MAC address for the PF in the first RAR entry */
igb_set_default_mac_filter(struct igb_adapter * adapter)7668 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7669 {
7670 struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7671
7672 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7673 mac_table->queue = adapter->vfs_allocated_count;
7674 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7675
7676 igb_rar_set_index(adapter, 0);
7677 }
7678
7679 /* If the filter to be added and an already existing filter express
7680 * the same address and address type, it should be possible to only
7681 * override the other configurations, for example the queue to steer
7682 * traffic.
7683 */
igb_mac_entry_can_be_used(const struct igb_mac_addr * entry,const u8 * addr,const u8 flags)7684 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7685 const u8 *addr, const u8 flags)
7686 {
7687 if (!(entry->state & IGB_MAC_STATE_IN_USE))
7688 return true;
7689
7690 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7691 (flags & IGB_MAC_STATE_SRC_ADDR))
7692 return false;
7693
7694 if (!ether_addr_equal(addr, entry->addr))
7695 return false;
7696
7697 return true;
7698 }
7699
7700 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7701 * 'flags' is used to indicate what kind of match is made, match is by
7702 * default for the destination address, if matching by source address
7703 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7704 */
igb_add_mac_filter_flags(struct igb_adapter * adapter,const u8 * addr,const u8 queue,const u8 flags)7705 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7706 const u8 *addr, const u8 queue,
7707 const u8 flags)
7708 {
7709 struct e1000_hw *hw = &adapter->hw;
7710 int rar_entries = hw->mac.rar_entry_count -
7711 adapter->vfs_allocated_count;
7712 int i;
7713
7714 if (is_zero_ether_addr(addr))
7715 return -EINVAL;
7716
7717 /* Search for the first empty entry in the MAC table.
7718 * Do not touch entries at the end of the table reserved for the VF MAC
7719 * addresses.
7720 */
7721 for (i = 0; i < rar_entries; i++) {
7722 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7723 addr, flags))
7724 continue;
7725
7726 ether_addr_copy(adapter->mac_table[i].addr, addr);
7727 adapter->mac_table[i].queue = queue;
7728 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7729
7730 igb_rar_set_index(adapter, i);
7731 return i;
7732 }
7733
7734 return -ENOSPC;
7735 }
7736
igb_add_mac_filter(struct igb_adapter * adapter,const u8 * addr,const u8 queue)7737 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7738 const u8 queue)
7739 {
7740 return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7741 }
7742
7743 /* Remove a MAC filter for 'addr' directing matching traffic to
7744 * 'queue', 'flags' is used to indicate what kind of match need to be
7745 * removed, match is by default for the destination address, if
7746 * matching by source address is to be removed the flag
7747 * IGB_MAC_STATE_SRC_ADDR can be used.
7748 */
igb_del_mac_filter_flags(struct igb_adapter * adapter,const u8 * addr,const u8 queue,const u8 flags)7749 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7750 const u8 *addr, const u8 queue,
7751 const u8 flags)
7752 {
7753 struct e1000_hw *hw = &adapter->hw;
7754 int rar_entries = hw->mac.rar_entry_count -
7755 adapter->vfs_allocated_count;
7756 int i;
7757
7758 if (is_zero_ether_addr(addr))
7759 return -EINVAL;
7760
7761 /* Search for matching entry in the MAC table based on given address
7762 * and queue. Do not touch entries at the end of the table reserved
7763 * for the VF MAC addresses.
7764 */
7765 for (i = 0; i < rar_entries; i++) {
7766 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7767 continue;
7768 if ((adapter->mac_table[i].state & flags) != flags)
7769 continue;
7770 if (adapter->mac_table[i].queue != queue)
7771 continue;
7772 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7773 continue;
7774
7775 /* When a filter for the default address is "deleted",
7776 * we return it to its initial configuration
7777 */
7778 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7779 adapter->mac_table[i].state =
7780 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7781 adapter->mac_table[i].queue =
7782 adapter->vfs_allocated_count;
7783 } else {
7784 adapter->mac_table[i].state = 0;
7785 adapter->mac_table[i].queue = 0;
7786 eth_zero_addr(adapter->mac_table[i].addr);
7787 }
7788
7789 igb_rar_set_index(adapter, i);
7790 return 0;
7791 }
7792
7793 return -ENOENT;
7794 }
7795
igb_del_mac_filter(struct igb_adapter * adapter,const u8 * addr,const u8 queue)7796 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7797 const u8 queue)
7798 {
7799 return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7800 }
7801
igb_add_mac_steering_filter(struct igb_adapter * adapter,const u8 * addr,u8 queue,u8 flags)7802 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7803 const u8 *addr, u8 queue, u8 flags)
7804 {
7805 struct e1000_hw *hw = &adapter->hw;
7806
7807 /* In theory, this should be supported on 82575 as well, but
7808 * that part wasn't easily accessible during development.
7809 */
7810 if (hw->mac.type != e1000_i210)
7811 return -EOPNOTSUPP;
7812
7813 return igb_add_mac_filter_flags(adapter, addr, queue,
7814 IGB_MAC_STATE_QUEUE_STEERING | flags);
7815 }
7816
igb_del_mac_steering_filter(struct igb_adapter * adapter,const u8 * addr,u8 queue,u8 flags)7817 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7818 const u8 *addr, u8 queue, u8 flags)
7819 {
7820 return igb_del_mac_filter_flags(adapter, addr, queue,
7821 IGB_MAC_STATE_QUEUE_STEERING | flags);
7822 }
7823
igb_uc_sync(struct net_device * netdev,const unsigned char * addr)7824 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7825 {
7826 struct igb_adapter *adapter = netdev_priv(netdev);
7827 int ret;
7828
7829 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7830
7831 return min_t(int, ret, 0);
7832 }
7833
igb_uc_unsync(struct net_device * netdev,const unsigned char * addr)7834 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7835 {
7836 struct igb_adapter *adapter = netdev_priv(netdev);
7837
7838 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7839
7840 return 0;
7841 }
7842
igb_set_vf_mac_filter(struct igb_adapter * adapter,const int vf,const u32 info,const u8 * addr)7843 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7844 const u32 info, const u8 *addr)
7845 {
7846 struct pci_dev *pdev = adapter->pdev;
7847 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7848 struct list_head *pos;
7849 struct vf_mac_filter *entry = NULL;
7850 int ret = 0;
7851
7852 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7853 !vf_data->trusted) {
7854 dev_warn(&pdev->dev,
7855 "VF %d requested MAC filter but is administratively denied\n",
7856 vf);
7857 return -EINVAL;
7858 }
7859 if (!is_valid_ether_addr(addr)) {
7860 dev_warn(&pdev->dev,
7861 "VF %d attempted to set invalid MAC filter\n",
7862 vf);
7863 return -EINVAL;
7864 }
7865
7866 switch (info) {
7867 case E1000_VF_MAC_FILTER_CLR:
7868 /* remove all unicast MAC filters related to the current VF */
7869 list_for_each(pos, &adapter->vf_macs.l) {
7870 entry = list_entry(pos, struct vf_mac_filter, l);
7871 if (entry->vf == vf) {
7872 entry->vf = -1;
7873 entry->free = true;
7874 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7875 }
7876 }
7877 break;
7878 case E1000_VF_MAC_FILTER_ADD:
7879 /* try to find empty slot in the list */
7880 list_for_each(pos, &adapter->vf_macs.l) {
7881 entry = list_entry(pos, struct vf_mac_filter, l);
7882 if (entry->free)
7883 break;
7884 }
7885
7886 if (entry && entry->free) {
7887 entry->free = false;
7888 entry->vf = vf;
7889 ether_addr_copy(entry->vf_mac, addr);
7890
7891 ret = igb_add_mac_filter(adapter, addr, vf);
7892 ret = min_t(int, ret, 0);
7893 } else {
7894 ret = -ENOSPC;
7895 }
7896
7897 if (ret == -ENOSPC)
7898 dev_warn(&pdev->dev,
7899 "VF %d has requested MAC filter but there is no space for it\n",
7900 vf);
7901 break;
7902 default:
7903 ret = -EINVAL;
7904 break;
7905 }
7906
7907 return ret;
7908 }
7909
igb_set_vf_mac_addr(struct igb_adapter * adapter,u32 * msg,int vf)7910 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7911 {
7912 struct pci_dev *pdev = adapter->pdev;
7913 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7914 u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7915
7916 /* The VF MAC Address is stored in a packed array of bytes
7917 * starting at the second 32 bit word of the msg array
7918 */
7919 unsigned char *addr = (unsigned char *)&msg[1];
7920 int ret = 0;
7921
7922 if (!info) {
7923 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7924 !vf_data->trusted) {
7925 dev_warn(&pdev->dev,
7926 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7927 vf);
7928 return -EINVAL;
7929 }
7930
7931 if (!is_valid_ether_addr(addr)) {
7932 dev_warn(&pdev->dev,
7933 "VF %d attempted to set invalid MAC\n",
7934 vf);
7935 return -EINVAL;
7936 }
7937
7938 ret = igb_set_vf_mac(adapter, vf, addr);
7939 } else {
7940 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7941 }
7942
7943 return ret;
7944 }
7945
igb_rcv_ack_from_vf(struct igb_adapter * adapter,u32 vf)7946 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7947 {
7948 struct e1000_hw *hw = &adapter->hw;
7949 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7950 u32 msg = E1000_VT_MSGTYPE_NACK;
7951
7952 /* if device isn't clear to send it shouldn't be reading either */
7953 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7954 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7955 igb_write_mbx(hw, &msg, 1, vf);
7956 vf_data->last_nack = jiffies;
7957 }
7958 }
7959
igb_rcv_msg_from_vf(struct igb_adapter * adapter,u32 vf)7960 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7961 {
7962 struct pci_dev *pdev = adapter->pdev;
7963 u32 msgbuf[E1000_VFMAILBOX_SIZE];
7964 struct e1000_hw *hw = &adapter->hw;
7965 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7966 s32 retval;
7967
7968 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7969
7970 if (retval) {
7971 /* if receive failed revoke VF CTS stats and restart init */
7972 dev_err(&pdev->dev, "Error receiving message from VF\n");
7973 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7974 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7975 goto unlock;
7976 goto out;
7977 }
7978
7979 /* this is a message we already processed, do nothing */
7980 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7981 goto unlock;
7982
7983 /* until the vf completes a reset it should not be
7984 * allowed to start any configuration.
7985 */
7986 if (msgbuf[0] == E1000_VF_RESET) {
7987 /* unlocks mailbox */
7988 igb_vf_reset_msg(adapter, vf);
7989 return;
7990 }
7991
7992 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7993 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7994 goto unlock;
7995 retval = -1;
7996 goto out;
7997 }
7998
7999 switch ((msgbuf[0] & 0xFFFF)) {
8000 case E1000_VF_SET_MAC_ADDR:
8001 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
8002 break;
8003 case E1000_VF_SET_PROMISC:
8004 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
8005 break;
8006 case E1000_VF_SET_MULTICAST:
8007 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
8008 break;
8009 case E1000_VF_SET_LPE:
8010 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
8011 break;
8012 case E1000_VF_SET_VLAN:
8013 retval = -1;
8014 if (vf_data->pf_vlan)
8015 dev_warn(&pdev->dev,
8016 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
8017 vf);
8018 else
8019 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
8020 break;
8021 default:
8022 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
8023 retval = -1;
8024 break;
8025 }
8026
8027 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
8028 out:
8029 /* notify the VF of the results of what it sent us */
8030 if (retval)
8031 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
8032 else
8033 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
8034
8035 /* unlocks mailbox */
8036 igb_write_mbx(hw, msgbuf, 1, vf);
8037 return;
8038
8039 unlock:
8040 igb_unlock_mbx(hw, vf);
8041 }
8042
igb_msg_task(struct igb_adapter * adapter)8043 static void igb_msg_task(struct igb_adapter *adapter)
8044 {
8045 struct e1000_hw *hw = &adapter->hw;
8046 unsigned long flags;
8047 u32 vf;
8048
8049 spin_lock_irqsave(&adapter->vfs_lock, flags);
8050 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
8051 /* process any reset requests */
8052 if (!igb_check_for_rst(hw, vf))
8053 igb_vf_reset_event(adapter, vf);
8054
8055 /* process any messages pending */
8056 if (!igb_check_for_msg(hw, vf))
8057 igb_rcv_msg_from_vf(adapter, vf);
8058
8059 /* process any acks */
8060 if (!igb_check_for_ack(hw, vf))
8061 igb_rcv_ack_from_vf(adapter, vf);
8062 }
8063 spin_unlock_irqrestore(&adapter->vfs_lock, flags);
8064 }
8065
8066 /**
8067 * igb_set_uta - Set unicast filter table address
8068 * @adapter: board private structure
8069 * @set: boolean indicating if we are setting or clearing bits
8070 *
8071 * The unicast table address is a register array of 32-bit registers.
8072 * The table is meant to be used in a way similar to how the MTA is used
8073 * however due to certain limitations in the hardware it is necessary to
8074 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
8075 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
8076 **/
igb_set_uta(struct igb_adapter * adapter,bool set)8077 static void igb_set_uta(struct igb_adapter *adapter, bool set)
8078 {
8079 struct e1000_hw *hw = &adapter->hw;
8080 u32 uta = set ? ~0 : 0;
8081 int i;
8082
8083 /* we only need to do this if VMDq is enabled */
8084 if (!adapter->vfs_allocated_count)
8085 return;
8086
8087 for (i = hw->mac.uta_reg_count; i--;)
8088 array_wr32(E1000_UTA, i, uta);
8089 }
8090
8091 /**
8092 * igb_intr_msi - Interrupt Handler
8093 * @irq: interrupt number
8094 * @data: pointer to a network interface device structure
8095 **/
igb_intr_msi(int irq,void * data)8096 static irqreturn_t igb_intr_msi(int irq, void *data)
8097 {
8098 struct igb_adapter *adapter = data;
8099 struct igb_q_vector *q_vector = adapter->q_vector[0];
8100 struct e1000_hw *hw = &adapter->hw;
8101 /* read ICR disables interrupts using IAM */
8102 u32 icr = rd32(E1000_ICR);
8103
8104 igb_write_itr(q_vector);
8105
8106 if (icr & E1000_ICR_DRSTA)
8107 schedule_work(&adapter->reset_task);
8108
8109 if (icr & E1000_ICR_DOUTSYNC) {
8110 /* HW is reporting DMA is out of sync */
8111 adapter->stats.doosync++;
8112 }
8113
8114 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8115 hw->mac.get_link_status = 1;
8116 if (!test_bit(__IGB_DOWN, &adapter->state))
8117 mod_timer(&adapter->watchdog_timer, jiffies + 1);
8118 }
8119
8120 if (icr & E1000_ICR_TS)
8121 igb_tsync_interrupt(adapter);
8122
8123 napi_schedule(&q_vector->napi);
8124
8125 return IRQ_HANDLED;
8126 }
8127
8128 /**
8129 * igb_intr - Legacy Interrupt Handler
8130 * @irq: interrupt number
8131 * @data: pointer to a network interface device structure
8132 **/
igb_intr(int irq,void * data)8133 static irqreturn_t igb_intr(int irq, void *data)
8134 {
8135 struct igb_adapter *adapter = data;
8136 struct igb_q_vector *q_vector = adapter->q_vector[0];
8137 struct e1000_hw *hw = &adapter->hw;
8138 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
8139 * need for the IMC write
8140 */
8141 u32 icr = rd32(E1000_ICR);
8142
8143 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
8144 * not set, then the adapter didn't send an interrupt
8145 */
8146 if (!(icr & E1000_ICR_INT_ASSERTED))
8147 return IRQ_NONE;
8148
8149 igb_write_itr(q_vector);
8150
8151 if (icr & E1000_ICR_DRSTA)
8152 schedule_work(&adapter->reset_task);
8153
8154 if (icr & E1000_ICR_DOUTSYNC) {
8155 /* HW is reporting DMA is out of sync */
8156 adapter->stats.doosync++;
8157 }
8158
8159 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8160 hw->mac.get_link_status = 1;
8161 /* guard against interrupt when we're going down */
8162 if (!test_bit(__IGB_DOWN, &adapter->state))
8163 mod_timer(&adapter->watchdog_timer, jiffies + 1);
8164 }
8165
8166 if (icr & E1000_ICR_TS)
8167 igb_tsync_interrupt(adapter);
8168
8169 napi_schedule(&q_vector->napi);
8170
8171 return IRQ_HANDLED;
8172 }
8173
igb_ring_irq_enable(struct igb_q_vector * q_vector)8174 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
8175 {
8176 struct igb_adapter *adapter = q_vector->adapter;
8177 struct e1000_hw *hw = &adapter->hw;
8178
8179 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
8180 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
8181 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
8182 igb_set_itr(q_vector);
8183 else
8184 igb_update_ring_itr(q_vector);
8185 }
8186
8187 if (!test_bit(__IGB_DOWN, &adapter->state)) {
8188 if (adapter->flags & IGB_FLAG_HAS_MSIX)
8189 wr32(E1000_EIMS, q_vector->eims_value);
8190 else
8191 igb_irq_enable(adapter);
8192 }
8193 }
8194
8195 /**
8196 * igb_poll - NAPI Rx polling callback
8197 * @napi: napi polling structure
8198 * @budget: count of how many packets we should handle
8199 **/
igb_poll(struct napi_struct * napi,int budget)8200 static int igb_poll(struct napi_struct *napi, int budget)
8201 {
8202 struct igb_q_vector *q_vector = container_of(napi,
8203 struct igb_q_vector,
8204 napi);
8205 bool clean_complete = true;
8206 int work_done = 0;
8207
8208 #ifdef CONFIG_IGB_DCA
8209 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
8210 igb_update_dca(q_vector);
8211 #endif
8212 if (q_vector->tx.ring)
8213 clean_complete = igb_clean_tx_irq(q_vector, budget);
8214
8215 if (q_vector->rx.ring) {
8216 int cleaned = igb_clean_rx_irq(q_vector, budget);
8217
8218 work_done += cleaned;
8219 if (cleaned >= budget)
8220 clean_complete = false;
8221 }
8222
8223 /* If all work not completed, return budget and keep polling */
8224 if (!clean_complete)
8225 return budget;
8226
8227 /* Exit the polling mode, but don't re-enable interrupts if stack might
8228 * poll us due to busy-polling
8229 */
8230 if (likely(napi_complete_done(napi, work_done)))
8231 igb_ring_irq_enable(q_vector);
8232
8233 return work_done;
8234 }
8235
8236 /**
8237 * igb_clean_tx_irq - Reclaim resources after transmit completes
8238 * @q_vector: pointer to q_vector containing needed info
8239 * @napi_budget: Used to determine if we are in netpoll
8240 *
8241 * returns true if ring is completely cleaned
8242 **/
igb_clean_tx_irq(struct igb_q_vector * q_vector,int napi_budget)8243 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8244 {
8245 struct igb_adapter *adapter = q_vector->adapter;
8246 struct igb_ring *tx_ring = q_vector->tx.ring;
8247 struct igb_tx_buffer *tx_buffer;
8248 union e1000_adv_tx_desc *tx_desc;
8249 unsigned int total_bytes = 0, total_packets = 0;
8250 unsigned int budget = q_vector->tx.work_limit;
8251 unsigned int i = tx_ring->next_to_clean;
8252
8253 if (test_bit(__IGB_DOWN, &adapter->state))
8254 return true;
8255
8256 tx_buffer = &tx_ring->tx_buffer_info[i];
8257 tx_desc = IGB_TX_DESC(tx_ring, i);
8258 i -= tx_ring->count;
8259
8260 do {
8261 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8262
8263 /* if next_to_watch is not set then there is no work pending */
8264 if (!eop_desc)
8265 break;
8266
8267 /* prevent any other reads prior to eop_desc */
8268 smp_rmb();
8269
8270 /* if DD is not set pending work has not been completed */
8271 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8272 break;
8273
8274 /* clear next_to_watch to prevent false hangs */
8275 tx_buffer->next_to_watch = NULL;
8276
8277 /* update the statistics for this packet */
8278 total_bytes += tx_buffer->bytecount;
8279 total_packets += tx_buffer->gso_segs;
8280
8281 /* free the skb */
8282 if (tx_buffer->type == IGB_TYPE_SKB)
8283 napi_consume_skb(tx_buffer->skb, napi_budget);
8284 else
8285 xdp_return_frame(tx_buffer->xdpf);
8286
8287 /* unmap skb header data */
8288 dma_unmap_single(tx_ring->dev,
8289 dma_unmap_addr(tx_buffer, dma),
8290 dma_unmap_len(tx_buffer, len),
8291 DMA_TO_DEVICE);
8292
8293 /* clear tx_buffer data */
8294 dma_unmap_len_set(tx_buffer, len, 0);
8295
8296 /* clear last DMA location and unmap remaining buffers */
8297 while (tx_desc != eop_desc) {
8298 tx_buffer++;
8299 tx_desc++;
8300 i++;
8301 if (unlikely(!i)) {
8302 i -= tx_ring->count;
8303 tx_buffer = tx_ring->tx_buffer_info;
8304 tx_desc = IGB_TX_DESC(tx_ring, 0);
8305 }
8306
8307 /* unmap any remaining paged data */
8308 if (dma_unmap_len(tx_buffer, len)) {
8309 dma_unmap_page(tx_ring->dev,
8310 dma_unmap_addr(tx_buffer, dma),
8311 dma_unmap_len(tx_buffer, len),
8312 DMA_TO_DEVICE);
8313 dma_unmap_len_set(tx_buffer, len, 0);
8314 }
8315 }
8316
8317 /* move us one more past the eop_desc for start of next pkt */
8318 tx_buffer++;
8319 tx_desc++;
8320 i++;
8321 if (unlikely(!i)) {
8322 i -= tx_ring->count;
8323 tx_buffer = tx_ring->tx_buffer_info;
8324 tx_desc = IGB_TX_DESC(tx_ring, 0);
8325 }
8326
8327 /* issue prefetch for next Tx descriptor */
8328 prefetch(tx_desc);
8329
8330 /* update budget accounting */
8331 budget--;
8332 } while (likely(budget));
8333
8334 netdev_tx_completed_queue(txring_txq(tx_ring),
8335 total_packets, total_bytes);
8336 i += tx_ring->count;
8337 tx_ring->next_to_clean = i;
8338 u64_stats_update_begin(&tx_ring->tx_syncp);
8339 tx_ring->tx_stats.bytes += total_bytes;
8340 tx_ring->tx_stats.packets += total_packets;
8341 u64_stats_update_end(&tx_ring->tx_syncp);
8342 q_vector->tx.total_bytes += total_bytes;
8343 q_vector->tx.total_packets += total_packets;
8344
8345 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8346 struct e1000_hw *hw = &adapter->hw;
8347
8348 /* Detect a transmit hang in hardware, this serializes the
8349 * check with the clearing of time_stamp and movement of i
8350 */
8351 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8352 if (tx_buffer->next_to_watch &&
8353 time_after(jiffies, tx_buffer->time_stamp +
8354 (adapter->tx_timeout_factor * HZ)) &&
8355 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8356
8357 /* detected Tx unit hang */
8358 dev_err(tx_ring->dev,
8359 "Detected Tx Unit Hang\n"
8360 " Tx Queue <%d>\n"
8361 " TDH <%x>\n"
8362 " TDT <%x>\n"
8363 " next_to_use <%x>\n"
8364 " next_to_clean <%x>\n"
8365 "buffer_info[next_to_clean]\n"
8366 " time_stamp <%lx>\n"
8367 " next_to_watch <%p>\n"
8368 " jiffies <%lx>\n"
8369 " desc.status <%x>\n",
8370 tx_ring->queue_index,
8371 rd32(E1000_TDH(tx_ring->reg_idx)),
8372 readl(tx_ring->tail),
8373 tx_ring->next_to_use,
8374 tx_ring->next_to_clean,
8375 tx_buffer->time_stamp,
8376 tx_buffer->next_to_watch,
8377 jiffies,
8378 tx_buffer->next_to_watch->wb.status);
8379 netif_stop_subqueue(tx_ring->netdev,
8380 tx_ring->queue_index);
8381
8382 /* we are about to reset, no point in enabling stuff */
8383 return true;
8384 }
8385 }
8386
8387 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8388 if (unlikely(total_packets &&
8389 netif_carrier_ok(tx_ring->netdev) &&
8390 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8391 /* Make sure that anybody stopping the queue after this
8392 * sees the new next_to_clean.
8393 */
8394 smp_mb();
8395 if (__netif_subqueue_stopped(tx_ring->netdev,
8396 tx_ring->queue_index) &&
8397 !(test_bit(__IGB_DOWN, &adapter->state))) {
8398 netif_wake_subqueue(tx_ring->netdev,
8399 tx_ring->queue_index);
8400
8401 u64_stats_update_begin(&tx_ring->tx_syncp);
8402 tx_ring->tx_stats.restart_queue++;
8403 u64_stats_update_end(&tx_ring->tx_syncp);
8404 }
8405 }
8406
8407 return !!budget;
8408 }
8409
8410 /**
8411 * igb_reuse_rx_page - page flip buffer and store it back on the ring
8412 * @rx_ring: rx descriptor ring to store buffers on
8413 * @old_buff: donor buffer to have page reused
8414 *
8415 * Synchronizes page for reuse by the adapter
8416 **/
igb_reuse_rx_page(struct igb_ring * rx_ring,struct igb_rx_buffer * old_buff)8417 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8418 struct igb_rx_buffer *old_buff)
8419 {
8420 struct igb_rx_buffer *new_buff;
8421 u16 nta = rx_ring->next_to_alloc;
8422
8423 new_buff = &rx_ring->rx_buffer_info[nta];
8424
8425 /* update, and store next to alloc */
8426 nta++;
8427 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8428
8429 /* Transfer page from old buffer to new buffer.
8430 * Move each member individually to avoid possible store
8431 * forwarding stalls.
8432 */
8433 new_buff->dma = old_buff->dma;
8434 new_buff->page = old_buff->page;
8435 new_buff->page_offset = old_buff->page_offset;
8436 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
8437 }
8438
igb_can_reuse_rx_page(struct igb_rx_buffer * rx_buffer,int rx_buf_pgcnt)8439 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8440 int rx_buf_pgcnt)
8441 {
8442 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8443 struct page *page = rx_buffer->page;
8444
8445 /* avoid re-using remote and pfmemalloc pages */
8446 if (!dev_page_is_reusable(page))
8447 return false;
8448
8449 #if (PAGE_SIZE < 8192)
8450 /* if we are only owner of page we can reuse it */
8451 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8452 return false;
8453 #else
8454 #define IGB_LAST_OFFSET \
8455 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8456
8457 if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8458 return false;
8459 #endif
8460
8461 /* If we have drained the page fragment pool we need to update
8462 * the pagecnt_bias and page count so that we fully restock the
8463 * number of references the driver holds.
8464 */
8465 if (unlikely(pagecnt_bias == 1)) {
8466 page_ref_add(page, USHRT_MAX - 1);
8467 rx_buffer->pagecnt_bias = USHRT_MAX;
8468 }
8469
8470 return true;
8471 }
8472
8473 /**
8474 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8475 * @rx_ring: rx descriptor ring to transact packets on
8476 * @rx_buffer: buffer containing page to add
8477 * @skb: sk_buff to place the data into
8478 * @size: size of buffer to be added
8479 *
8480 * This function will add the data contained in rx_buffer->page to the skb.
8481 **/
igb_add_rx_frag(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)8482 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8483 struct igb_rx_buffer *rx_buffer,
8484 struct sk_buff *skb,
8485 unsigned int size)
8486 {
8487 #if (PAGE_SIZE < 8192)
8488 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8489 #else
8490 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8491 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8492 SKB_DATA_ALIGN(size);
8493 #endif
8494 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8495 rx_buffer->page_offset, size, truesize);
8496 #if (PAGE_SIZE < 8192)
8497 rx_buffer->page_offset ^= truesize;
8498 #else
8499 rx_buffer->page_offset += truesize;
8500 #endif
8501 }
8502
igb_construct_skb(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct xdp_buff * xdp,ktime_t timestamp)8503 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8504 struct igb_rx_buffer *rx_buffer,
8505 struct xdp_buff *xdp,
8506 ktime_t timestamp)
8507 {
8508 #if (PAGE_SIZE < 8192)
8509 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8510 #else
8511 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8512 xdp->data_hard_start);
8513 #endif
8514 unsigned int size = xdp->data_end - xdp->data;
8515 unsigned int headlen;
8516 struct sk_buff *skb;
8517
8518 /* prefetch first cache line of first page */
8519 net_prefetch(xdp->data);
8520
8521 /* allocate a skb to store the frags */
8522 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8523 if (unlikely(!skb))
8524 return NULL;
8525
8526 if (timestamp)
8527 skb_hwtstamps(skb)->hwtstamp = timestamp;
8528
8529 /* Determine available headroom for copy */
8530 headlen = size;
8531 if (headlen > IGB_RX_HDR_LEN)
8532 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8533
8534 /* align pull length to size of long to optimize memcpy performance */
8535 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8536
8537 /* update all of the pointers */
8538 size -= headlen;
8539 if (size) {
8540 skb_add_rx_frag(skb, 0, rx_buffer->page,
8541 (xdp->data + headlen) - page_address(rx_buffer->page),
8542 size, truesize);
8543 #if (PAGE_SIZE < 8192)
8544 rx_buffer->page_offset ^= truesize;
8545 #else
8546 rx_buffer->page_offset += truesize;
8547 #endif
8548 } else {
8549 rx_buffer->pagecnt_bias++;
8550 }
8551
8552 return skb;
8553 }
8554
igb_build_skb(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct xdp_buff * xdp,ktime_t timestamp)8555 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8556 struct igb_rx_buffer *rx_buffer,
8557 struct xdp_buff *xdp,
8558 ktime_t timestamp)
8559 {
8560 #if (PAGE_SIZE < 8192)
8561 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8562 #else
8563 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8564 SKB_DATA_ALIGN(xdp->data_end -
8565 xdp->data_hard_start);
8566 #endif
8567 unsigned int metasize = xdp->data - xdp->data_meta;
8568 struct sk_buff *skb;
8569
8570 /* prefetch first cache line of first page */
8571 net_prefetch(xdp->data_meta);
8572
8573 /* build an skb around the page buffer */
8574 skb = napi_build_skb(xdp->data_hard_start, truesize);
8575 if (unlikely(!skb))
8576 return NULL;
8577
8578 /* update pointers within the skb to store the data */
8579 skb_reserve(skb, xdp->data - xdp->data_hard_start);
8580 __skb_put(skb, xdp->data_end - xdp->data);
8581
8582 if (metasize)
8583 skb_metadata_set(skb, metasize);
8584
8585 if (timestamp)
8586 skb_hwtstamps(skb)->hwtstamp = timestamp;
8587
8588 /* update buffer offset */
8589 #if (PAGE_SIZE < 8192)
8590 rx_buffer->page_offset ^= truesize;
8591 #else
8592 rx_buffer->page_offset += truesize;
8593 #endif
8594
8595 return skb;
8596 }
8597
igb_run_xdp(struct igb_adapter * adapter,struct igb_ring * rx_ring,struct xdp_buff * xdp)8598 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8599 struct igb_ring *rx_ring,
8600 struct xdp_buff *xdp)
8601 {
8602 int err, result = IGB_XDP_PASS;
8603 struct bpf_prog *xdp_prog;
8604 u32 act;
8605
8606 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8607
8608 if (!xdp_prog)
8609 goto xdp_out;
8610
8611 prefetchw(xdp->data_hard_start); /* xdp_frame write */
8612
8613 act = bpf_prog_run_xdp(xdp_prog, xdp);
8614 switch (act) {
8615 case XDP_PASS:
8616 break;
8617 case XDP_TX:
8618 result = igb_xdp_xmit_back(adapter, xdp);
8619 if (result == IGB_XDP_CONSUMED)
8620 goto out_failure;
8621 break;
8622 case XDP_REDIRECT:
8623 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8624 if (err)
8625 goto out_failure;
8626 result = IGB_XDP_REDIR;
8627 break;
8628 default:
8629 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act);
8630 fallthrough;
8631 case XDP_ABORTED:
8632 out_failure:
8633 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8634 fallthrough;
8635 case XDP_DROP:
8636 result = IGB_XDP_CONSUMED;
8637 break;
8638 }
8639 xdp_out:
8640 return ERR_PTR(-result);
8641 }
8642
igb_rx_frame_truesize(struct igb_ring * rx_ring,unsigned int size)8643 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8644 unsigned int size)
8645 {
8646 unsigned int truesize;
8647
8648 #if (PAGE_SIZE < 8192)
8649 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8650 #else
8651 truesize = ring_uses_build_skb(rx_ring) ?
8652 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8653 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8654 SKB_DATA_ALIGN(size);
8655 #endif
8656 return truesize;
8657 }
8658
igb_rx_buffer_flip(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,unsigned int size)8659 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8660 struct igb_rx_buffer *rx_buffer,
8661 unsigned int size)
8662 {
8663 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8664 #if (PAGE_SIZE < 8192)
8665 rx_buffer->page_offset ^= truesize;
8666 #else
8667 rx_buffer->page_offset += truesize;
8668 #endif
8669 }
8670
igb_rx_checksum(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8671 static inline void igb_rx_checksum(struct igb_ring *ring,
8672 union e1000_adv_rx_desc *rx_desc,
8673 struct sk_buff *skb)
8674 {
8675 skb_checksum_none_assert(skb);
8676
8677 /* Ignore Checksum bit is set */
8678 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8679 return;
8680
8681 /* Rx checksum disabled via ethtool */
8682 if (!(ring->netdev->features & NETIF_F_RXCSUM))
8683 return;
8684
8685 /* TCP/UDP checksum error bit is set */
8686 if (igb_test_staterr(rx_desc,
8687 E1000_RXDEXT_STATERR_TCPE |
8688 E1000_RXDEXT_STATERR_IPE)) {
8689 /* work around errata with sctp packets where the TCPE aka
8690 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8691 * packets, (aka let the stack check the crc32c)
8692 */
8693 if (!((skb->len == 60) &&
8694 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8695 u64_stats_update_begin(&ring->rx_syncp);
8696 ring->rx_stats.csum_err++;
8697 u64_stats_update_end(&ring->rx_syncp);
8698 }
8699 /* let the stack verify checksum errors */
8700 return;
8701 }
8702 /* It must be a TCP or UDP packet with a valid checksum */
8703 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8704 E1000_RXD_STAT_UDPCS))
8705 skb->ip_summed = CHECKSUM_UNNECESSARY;
8706
8707 dev_dbg(ring->dev, "cksum success: bits %08X\n",
8708 le32_to_cpu(rx_desc->wb.upper.status_error));
8709 }
8710
igb_rx_hash(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8711 static inline void igb_rx_hash(struct igb_ring *ring,
8712 union e1000_adv_rx_desc *rx_desc,
8713 struct sk_buff *skb)
8714 {
8715 if (ring->netdev->features & NETIF_F_RXHASH)
8716 skb_set_hash(skb,
8717 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8718 PKT_HASH_TYPE_L3);
8719 }
8720
8721 /**
8722 * igb_is_non_eop - process handling of non-EOP buffers
8723 * @rx_ring: Rx ring being processed
8724 * @rx_desc: Rx descriptor for current buffer
8725 *
8726 * This function updates next to clean. If the buffer is an EOP buffer
8727 * this function exits returning false, otherwise it will place the
8728 * sk_buff in the next buffer to be chained and return true indicating
8729 * that this is in fact a non-EOP buffer.
8730 **/
igb_is_non_eop(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc)8731 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8732 union e1000_adv_rx_desc *rx_desc)
8733 {
8734 u32 ntc = rx_ring->next_to_clean + 1;
8735
8736 /* fetch, update, and store next to clean */
8737 ntc = (ntc < rx_ring->count) ? ntc : 0;
8738 rx_ring->next_to_clean = ntc;
8739
8740 prefetch(IGB_RX_DESC(rx_ring, ntc));
8741
8742 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8743 return false;
8744
8745 return true;
8746 }
8747
8748 /**
8749 * igb_cleanup_headers - Correct corrupted or empty headers
8750 * @rx_ring: rx descriptor ring packet is being transacted on
8751 * @rx_desc: pointer to the EOP Rx descriptor
8752 * @skb: pointer to current skb being fixed
8753 *
8754 * Address the case where we are pulling data in on pages only
8755 * and as such no data is present in the skb header.
8756 *
8757 * In addition if skb is not at least 60 bytes we need to pad it so that
8758 * it is large enough to qualify as a valid Ethernet frame.
8759 *
8760 * Returns true if an error was encountered and skb was freed.
8761 **/
igb_cleanup_headers(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8762 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8763 union e1000_adv_rx_desc *rx_desc,
8764 struct sk_buff *skb)
8765 {
8766 /* XDP packets use error pointer so abort at this point */
8767 if (IS_ERR(skb))
8768 return true;
8769
8770 if (unlikely((igb_test_staterr(rx_desc,
8771 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8772 struct net_device *netdev = rx_ring->netdev;
8773 if (!(netdev->features & NETIF_F_RXALL)) {
8774 dev_kfree_skb_any(skb);
8775 return true;
8776 }
8777 }
8778
8779 /* if eth_skb_pad returns an error the skb was freed */
8780 if (eth_skb_pad(skb))
8781 return true;
8782
8783 return false;
8784 }
8785
8786 /**
8787 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
8788 * @rx_ring: rx descriptor ring packet is being transacted on
8789 * @rx_desc: pointer to the EOP Rx descriptor
8790 * @skb: pointer to current skb being populated
8791 *
8792 * This function checks the ring, descriptor, and packet information in
8793 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
8794 * other fields within the skb.
8795 **/
igb_process_skb_fields(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8796 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8797 union e1000_adv_rx_desc *rx_desc,
8798 struct sk_buff *skb)
8799 {
8800 struct net_device *dev = rx_ring->netdev;
8801
8802 igb_rx_hash(rx_ring, rx_desc, skb);
8803
8804 igb_rx_checksum(rx_ring, rx_desc, skb);
8805
8806 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8807 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8808 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8809
8810 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8811 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8812 u16 vid;
8813
8814 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8815 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8816 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8817 else
8818 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8819
8820 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8821 }
8822
8823 skb_record_rx_queue(skb, rx_ring->queue_index);
8824
8825 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8826 }
8827
igb_rx_offset(struct igb_ring * rx_ring)8828 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8829 {
8830 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8831 }
8832
igb_get_rx_buffer(struct igb_ring * rx_ring,const unsigned int size,int * rx_buf_pgcnt)8833 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8834 const unsigned int size, int *rx_buf_pgcnt)
8835 {
8836 struct igb_rx_buffer *rx_buffer;
8837
8838 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8839 *rx_buf_pgcnt =
8840 #if (PAGE_SIZE < 8192)
8841 page_count(rx_buffer->page);
8842 #else
8843 0;
8844 #endif
8845 prefetchw(rx_buffer->page);
8846
8847 /* we are reusing so sync this buffer for CPU use */
8848 dma_sync_single_range_for_cpu(rx_ring->dev,
8849 rx_buffer->dma,
8850 rx_buffer->page_offset,
8851 size,
8852 DMA_FROM_DEVICE);
8853
8854 rx_buffer->pagecnt_bias--;
8855
8856 return rx_buffer;
8857 }
8858
igb_put_rx_buffer(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,int rx_buf_pgcnt)8859 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8860 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8861 {
8862 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8863 /* hand second half of page back to the ring */
8864 igb_reuse_rx_page(rx_ring, rx_buffer);
8865 } else {
8866 /* We are not reusing the buffer so unmap it and free
8867 * any references we are holding to it
8868 */
8869 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8870 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8871 IGB_RX_DMA_ATTR);
8872 __page_frag_cache_drain(rx_buffer->page,
8873 rx_buffer->pagecnt_bias);
8874 }
8875
8876 /* clear contents of rx_buffer */
8877 rx_buffer->page = NULL;
8878 }
8879
igb_clean_rx_irq(struct igb_q_vector * q_vector,const int budget)8880 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8881 {
8882 struct igb_adapter *adapter = q_vector->adapter;
8883 struct igb_ring *rx_ring = q_vector->rx.ring;
8884 struct sk_buff *skb = rx_ring->skb;
8885 unsigned int total_bytes = 0, total_packets = 0;
8886 u16 cleaned_count = igb_desc_unused(rx_ring);
8887 unsigned int xdp_xmit = 0;
8888 struct xdp_buff xdp;
8889 u32 frame_sz = 0;
8890 int rx_buf_pgcnt;
8891
8892 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8893 #if (PAGE_SIZE < 8192)
8894 frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8895 #endif
8896 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8897
8898 while (likely(total_packets < budget)) {
8899 union e1000_adv_rx_desc *rx_desc;
8900 struct igb_rx_buffer *rx_buffer;
8901 ktime_t timestamp = 0;
8902 int pkt_offset = 0;
8903 unsigned int size;
8904 void *pktbuf;
8905
8906 /* return some buffers to hardware, one at a time is too slow */
8907 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8908 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8909 cleaned_count = 0;
8910 }
8911
8912 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8913 size = le16_to_cpu(rx_desc->wb.upper.length);
8914 if (!size)
8915 break;
8916
8917 /* This memory barrier is needed to keep us from reading
8918 * any other fields out of the rx_desc until we know the
8919 * descriptor has been written back
8920 */
8921 dma_rmb();
8922
8923 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8924 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8925
8926 /* pull rx packet timestamp if available and valid */
8927 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8928 int ts_hdr_len;
8929
8930 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8931 pktbuf, ×tamp);
8932
8933 pkt_offset += ts_hdr_len;
8934 size -= ts_hdr_len;
8935 }
8936
8937 /* retrieve a buffer from the ring */
8938 if (!skb) {
8939 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8940 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8941
8942 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8943 xdp_buff_clear_frags_flag(&xdp);
8944 #if (PAGE_SIZE > 4096)
8945 /* At larger PAGE_SIZE, frame_sz depend on len size */
8946 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8947 #endif
8948 skb = igb_run_xdp(adapter, rx_ring, &xdp);
8949 }
8950
8951 if (IS_ERR(skb)) {
8952 unsigned int xdp_res = -PTR_ERR(skb);
8953
8954 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8955 xdp_xmit |= xdp_res;
8956 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8957 } else {
8958 rx_buffer->pagecnt_bias++;
8959 }
8960 total_packets++;
8961 total_bytes += size;
8962 } else if (skb)
8963 igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8964 else if (ring_uses_build_skb(rx_ring))
8965 skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8966 timestamp);
8967 else
8968 skb = igb_construct_skb(rx_ring, rx_buffer,
8969 &xdp, timestamp);
8970
8971 /* exit if we failed to retrieve a buffer */
8972 if (!skb) {
8973 rx_ring->rx_stats.alloc_failed++;
8974 rx_buffer->pagecnt_bias++;
8975 break;
8976 }
8977
8978 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8979 cleaned_count++;
8980
8981 /* fetch next buffer in frame if non-eop */
8982 if (igb_is_non_eop(rx_ring, rx_desc))
8983 continue;
8984
8985 /* verify the packet layout is correct */
8986 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8987 skb = NULL;
8988 continue;
8989 }
8990
8991 /* probably a little skewed due to removing CRC */
8992 total_bytes += skb->len;
8993
8994 /* populate checksum, timestamp, VLAN, and protocol */
8995 igb_process_skb_fields(rx_ring, rx_desc, skb);
8996
8997 napi_gro_receive(&q_vector->napi, skb);
8998
8999 /* reset skb pointer */
9000 skb = NULL;
9001
9002 /* update budget accounting */
9003 total_packets++;
9004 }
9005
9006 /* place incomplete frames back on ring for completion */
9007 rx_ring->skb = skb;
9008
9009 if (xdp_xmit & IGB_XDP_REDIR)
9010 xdp_do_flush();
9011
9012 if (xdp_xmit & IGB_XDP_TX) {
9013 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
9014
9015 igb_xdp_ring_update_tail(tx_ring);
9016 }
9017
9018 u64_stats_update_begin(&rx_ring->rx_syncp);
9019 rx_ring->rx_stats.packets += total_packets;
9020 rx_ring->rx_stats.bytes += total_bytes;
9021 u64_stats_update_end(&rx_ring->rx_syncp);
9022 q_vector->rx.total_packets += total_packets;
9023 q_vector->rx.total_bytes += total_bytes;
9024
9025 if (cleaned_count)
9026 igb_alloc_rx_buffers(rx_ring, cleaned_count);
9027
9028 return total_packets;
9029 }
9030
igb_alloc_mapped_page(struct igb_ring * rx_ring,struct igb_rx_buffer * bi)9031 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
9032 struct igb_rx_buffer *bi)
9033 {
9034 struct page *page = bi->page;
9035 dma_addr_t dma;
9036
9037 /* since we are recycling buffers we should seldom need to alloc */
9038 if (likely(page))
9039 return true;
9040
9041 /* alloc new page for storage */
9042 page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
9043 if (unlikely(!page)) {
9044 rx_ring->rx_stats.alloc_failed++;
9045 return false;
9046 }
9047
9048 /* map page for use */
9049 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
9050 igb_rx_pg_size(rx_ring),
9051 DMA_FROM_DEVICE,
9052 IGB_RX_DMA_ATTR);
9053
9054 /* if mapping failed free memory back to system since
9055 * there isn't much point in holding memory we can't use
9056 */
9057 if (dma_mapping_error(rx_ring->dev, dma)) {
9058 __free_pages(page, igb_rx_pg_order(rx_ring));
9059
9060 rx_ring->rx_stats.alloc_failed++;
9061 return false;
9062 }
9063
9064 bi->dma = dma;
9065 bi->page = page;
9066 bi->page_offset = igb_rx_offset(rx_ring);
9067 page_ref_add(page, USHRT_MAX - 1);
9068 bi->pagecnt_bias = USHRT_MAX;
9069
9070 return true;
9071 }
9072
9073 /**
9074 * igb_alloc_rx_buffers - Replace used receive buffers
9075 * @rx_ring: rx descriptor ring to allocate new receive buffers
9076 * @cleaned_count: count of buffers to allocate
9077 **/
igb_alloc_rx_buffers(struct igb_ring * rx_ring,u16 cleaned_count)9078 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9079 {
9080 union e1000_adv_rx_desc *rx_desc;
9081 struct igb_rx_buffer *bi;
9082 u16 i = rx_ring->next_to_use;
9083 u16 bufsz;
9084
9085 /* nothing to do */
9086 if (!cleaned_count)
9087 return;
9088
9089 rx_desc = IGB_RX_DESC(rx_ring, i);
9090 bi = &rx_ring->rx_buffer_info[i];
9091 i -= rx_ring->count;
9092
9093 bufsz = igb_rx_bufsz(rx_ring);
9094
9095 do {
9096 if (!igb_alloc_mapped_page(rx_ring, bi))
9097 break;
9098
9099 /* sync the buffer for use by the device */
9100 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
9101 bi->page_offset, bufsz,
9102 DMA_FROM_DEVICE);
9103
9104 /* Refresh the desc even if buffer_addrs didn't change
9105 * because each write-back erases this info.
9106 */
9107 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9108
9109 rx_desc++;
9110 bi++;
9111 i++;
9112 if (unlikely(!i)) {
9113 rx_desc = IGB_RX_DESC(rx_ring, 0);
9114 bi = rx_ring->rx_buffer_info;
9115 i -= rx_ring->count;
9116 }
9117
9118 /* clear the length for the next_to_use descriptor */
9119 rx_desc->wb.upper.length = 0;
9120
9121 cleaned_count--;
9122 } while (cleaned_count);
9123
9124 i += rx_ring->count;
9125
9126 if (rx_ring->next_to_use != i) {
9127 /* record the next descriptor to use */
9128 rx_ring->next_to_use = i;
9129
9130 /* update next to alloc since we have filled the ring */
9131 rx_ring->next_to_alloc = i;
9132
9133 /* Force memory writes to complete before letting h/w
9134 * know there are new descriptors to fetch. (Only
9135 * applicable for weak-ordered memory model archs,
9136 * such as IA-64).
9137 */
9138 dma_wmb();
9139 writel(i, rx_ring->tail);
9140 }
9141 }
9142
9143 /**
9144 * igb_mii_ioctl -
9145 * @netdev: pointer to netdev struct
9146 * @ifr: interface structure
9147 * @cmd: ioctl command to execute
9148 **/
igb_mii_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)9149 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9150 {
9151 struct igb_adapter *adapter = netdev_priv(netdev);
9152 struct mii_ioctl_data *data = if_mii(ifr);
9153
9154 if (adapter->hw.phy.media_type != e1000_media_type_copper)
9155 return -EOPNOTSUPP;
9156
9157 switch (cmd) {
9158 case SIOCGMIIPHY:
9159 data->phy_id = adapter->hw.phy.addr;
9160 break;
9161 case SIOCGMIIREG:
9162 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9163 &data->val_out))
9164 return -EIO;
9165 break;
9166 case SIOCSMIIREG:
9167 default:
9168 return -EOPNOTSUPP;
9169 }
9170 return 0;
9171 }
9172
9173 /**
9174 * igb_ioctl -
9175 * @netdev: pointer to netdev struct
9176 * @ifr: interface structure
9177 * @cmd: ioctl command to execute
9178 **/
igb_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)9179 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9180 {
9181 switch (cmd) {
9182 case SIOCGMIIPHY:
9183 case SIOCGMIIREG:
9184 case SIOCSMIIREG:
9185 return igb_mii_ioctl(netdev, ifr, cmd);
9186 case SIOCGHWTSTAMP:
9187 return igb_ptp_get_ts_config(netdev, ifr);
9188 case SIOCSHWTSTAMP:
9189 return igb_ptp_set_ts_config(netdev, ifr);
9190 default:
9191 return -EOPNOTSUPP;
9192 }
9193 }
9194
igb_read_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)9195 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9196 {
9197 struct igb_adapter *adapter = hw->back;
9198
9199 pci_read_config_word(adapter->pdev, reg, value);
9200 }
9201
igb_write_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)9202 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9203 {
9204 struct igb_adapter *adapter = hw->back;
9205
9206 pci_write_config_word(adapter->pdev, reg, *value);
9207 }
9208
igb_read_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)9209 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9210 {
9211 struct igb_adapter *adapter = hw->back;
9212
9213 if (pcie_capability_read_word(adapter->pdev, reg, value))
9214 return -E1000_ERR_CONFIG;
9215
9216 return 0;
9217 }
9218
igb_write_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)9219 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9220 {
9221 struct igb_adapter *adapter = hw->back;
9222
9223 if (pcie_capability_write_word(adapter->pdev, reg, *value))
9224 return -E1000_ERR_CONFIG;
9225
9226 return 0;
9227 }
9228
igb_vlan_mode(struct net_device * netdev,netdev_features_t features)9229 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9230 {
9231 struct igb_adapter *adapter = netdev_priv(netdev);
9232 struct e1000_hw *hw = &adapter->hw;
9233 u32 ctrl, rctl;
9234 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9235
9236 if (enable) {
9237 /* enable VLAN tag insert/strip */
9238 ctrl = rd32(E1000_CTRL);
9239 ctrl |= E1000_CTRL_VME;
9240 wr32(E1000_CTRL, ctrl);
9241
9242 /* Disable CFI check */
9243 rctl = rd32(E1000_RCTL);
9244 rctl &= ~E1000_RCTL_CFIEN;
9245 wr32(E1000_RCTL, rctl);
9246 } else {
9247 /* disable VLAN tag insert/strip */
9248 ctrl = rd32(E1000_CTRL);
9249 ctrl &= ~E1000_CTRL_VME;
9250 wr32(E1000_CTRL, ctrl);
9251 }
9252
9253 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9254 }
9255
igb_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)9256 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9257 __be16 proto, u16 vid)
9258 {
9259 struct igb_adapter *adapter = netdev_priv(netdev);
9260 struct e1000_hw *hw = &adapter->hw;
9261 int pf_id = adapter->vfs_allocated_count;
9262
9263 /* add the filter since PF can receive vlans w/o entry in vlvf */
9264 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9265 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9266
9267 set_bit(vid, adapter->active_vlans);
9268
9269 return 0;
9270 }
9271
igb_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)9272 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9273 __be16 proto, u16 vid)
9274 {
9275 struct igb_adapter *adapter = netdev_priv(netdev);
9276 int pf_id = adapter->vfs_allocated_count;
9277 struct e1000_hw *hw = &adapter->hw;
9278
9279 /* remove VID from filter table */
9280 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9281 igb_vfta_set(hw, vid, pf_id, false, true);
9282
9283 clear_bit(vid, adapter->active_vlans);
9284
9285 return 0;
9286 }
9287
igb_restore_vlan(struct igb_adapter * adapter)9288 static void igb_restore_vlan(struct igb_adapter *adapter)
9289 {
9290 u16 vid = 1;
9291
9292 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9293 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9294
9295 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9296 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9297 }
9298
igb_set_spd_dplx(struct igb_adapter * adapter,u32 spd,u8 dplx)9299 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9300 {
9301 struct pci_dev *pdev = adapter->pdev;
9302 struct e1000_mac_info *mac = &adapter->hw.mac;
9303
9304 mac->autoneg = 0;
9305
9306 /* Make sure dplx is at most 1 bit and lsb of speed is not set
9307 * for the switch() below to work
9308 */
9309 if ((spd & 1) || (dplx & ~1))
9310 goto err_inval;
9311
9312 /* Fiber NIC's only allow 1000 gbps Full duplex
9313 * and 100Mbps Full duplex for 100baseFx sfp
9314 */
9315 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9316 switch (spd + dplx) {
9317 case SPEED_10 + DUPLEX_HALF:
9318 case SPEED_10 + DUPLEX_FULL:
9319 case SPEED_100 + DUPLEX_HALF:
9320 goto err_inval;
9321 default:
9322 break;
9323 }
9324 }
9325
9326 switch (spd + dplx) {
9327 case SPEED_10 + DUPLEX_HALF:
9328 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9329 break;
9330 case SPEED_10 + DUPLEX_FULL:
9331 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9332 break;
9333 case SPEED_100 + DUPLEX_HALF:
9334 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9335 break;
9336 case SPEED_100 + DUPLEX_FULL:
9337 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9338 break;
9339 case SPEED_1000 + DUPLEX_FULL:
9340 mac->autoneg = 1;
9341 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9342 break;
9343 case SPEED_1000 + DUPLEX_HALF: /* not supported */
9344 default:
9345 goto err_inval;
9346 }
9347
9348 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9349 adapter->hw.phy.mdix = AUTO_ALL_MODES;
9350
9351 return 0;
9352
9353 err_inval:
9354 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9355 return -EINVAL;
9356 }
9357
__igb_shutdown(struct pci_dev * pdev,bool * enable_wake,bool runtime)9358 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9359 bool runtime)
9360 {
9361 struct net_device *netdev = pci_get_drvdata(pdev);
9362 struct igb_adapter *adapter = netdev_priv(netdev);
9363 struct e1000_hw *hw = &adapter->hw;
9364 u32 ctrl, rctl, status;
9365 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9366 bool wake;
9367
9368 rtnl_lock();
9369 netif_device_detach(netdev);
9370
9371 if (netif_running(netdev))
9372 __igb_close(netdev, true);
9373
9374 igb_ptp_suspend(adapter);
9375
9376 igb_clear_interrupt_scheme(adapter);
9377 rtnl_unlock();
9378
9379 status = rd32(E1000_STATUS);
9380 if (status & E1000_STATUS_LU)
9381 wufc &= ~E1000_WUFC_LNKC;
9382
9383 if (wufc) {
9384 igb_setup_rctl(adapter);
9385 igb_set_rx_mode(netdev);
9386
9387 /* turn on all-multi mode if wake on multicast is enabled */
9388 if (wufc & E1000_WUFC_MC) {
9389 rctl = rd32(E1000_RCTL);
9390 rctl |= E1000_RCTL_MPE;
9391 wr32(E1000_RCTL, rctl);
9392 }
9393
9394 ctrl = rd32(E1000_CTRL);
9395 ctrl |= E1000_CTRL_ADVD3WUC;
9396 wr32(E1000_CTRL, ctrl);
9397
9398 /* Allow time for pending master requests to run */
9399 igb_disable_pcie_master(hw);
9400
9401 wr32(E1000_WUC, E1000_WUC_PME_EN);
9402 wr32(E1000_WUFC, wufc);
9403 } else {
9404 wr32(E1000_WUC, 0);
9405 wr32(E1000_WUFC, 0);
9406 }
9407
9408 wake = wufc || adapter->en_mng_pt;
9409 if (!wake)
9410 igb_power_down_link(adapter);
9411 else
9412 igb_power_up_link(adapter);
9413
9414 if (enable_wake)
9415 *enable_wake = wake;
9416
9417 /* Release control of h/w to f/w. If f/w is AMT enabled, this
9418 * would have already happened in close and is redundant.
9419 */
9420 igb_release_hw_control(adapter);
9421
9422 pci_disable_device(pdev);
9423
9424 return 0;
9425 }
9426
igb_deliver_wake_packet(struct net_device * netdev)9427 static void igb_deliver_wake_packet(struct net_device *netdev)
9428 {
9429 struct igb_adapter *adapter = netdev_priv(netdev);
9430 struct e1000_hw *hw = &adapter->hw;
9431 struct sk_buff *skb;
9432 u32 wupl;
9433
9434 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9435
9436 /* WUPM stores only the first 128 bytes of the wake packet.
9437 * Read the packet only if we have the whole thing.
9438 */
9439 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9440 return;
9441
9442 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9443 if (!skb)
9444 return;
9445
9446 skb_put(skb, wupl);
9447
9448 /* Ensure reads are 32-bit aligned */
9449 wupl = roundup(wupl, 4);
9450
9451 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9452
9453 skb->protocol = eth_type_trans(skb, netdev);
9454 netif_rx(skb);
9455 }
9456
igb_suspend(struct device * dev)9457 static int __maybe_unused igb_suspend(struct device *dev)
9458 {
9459 return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9460 }
9461
__igb_resume(struct device * dev,bool rpm)9462 static int __maybe_unused __igb_resume(struct device *dev, bool rpm)
9463 {
9464 struct pci_dev *pdev = to_pci_dev(dev);
9465 struct net_device *netdev = pci_get_drvdata(pdev);
9466 struct igb_adapter *adapter = netdev_priv(netdev);
9467 struct e1000_hw *hw = &adapter->hw;
9468 u32 err, val;
9469
9470 pci_set_power_state(pdev, PCI_D0);
9471 pci_restore_state(pdev);
9472 pci_save_state(pdev);
9473
9474 if (!pci_device_is_present(pdev))
9475 return -ENODEV;
9476 err = pci_enable_device_mem(pdev);
9477 if (err) {
9478 dev_err(&pdev->dev,
9479 "igb: Cannot enable PCI device from suspend\n");
9480 return err;
9481 }
9482 pci_set_master(pdev);
9483
9484 pci_enable_wake(pdev, PCI_D3hot, 0);
9485 pci_enable_wake(pdev, PCI_D3cold, 0);
9486
9487 if (igb_init_interrupt_scheme(adapter, true)) {
9488 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9489 return -ENOMEM;
9490 }
9491
9492 igb_reset(adapter);
9493
9494 /* let the f/w know that the h/w is now under the control of the
9495 * driver.
9496 */
9497 igb_get_hw_control(adapter);
9498
9499 val = rd32(E1000_WUS);
9500 if (val & WAKE_PKT_WUS)
9501 igb_deliver_wake_packet(netdev);
9502
9503 wr32(E1000_WUS, ~0);
9504
9505 if (!rpm)
9506 rtnl_lock();
9507 if (!err && netif_running(netdev))
9508 err = __igb_open(netdev, true);
9509
9510 if (!err)
9511 netif_device_attach(netdev);
9512 if (!rpm)
9513 rtnl_unlock();
9514
9515 return err;
9516 }
9517
igb_resume(struct device * dev)9518 static int __maybe_unused igb_resume(struct device *dev)
9519 {
9520 return __igb_resume(dev, false);
9521 }
9522
igb_runtime_idle(struct device * dev)9523 static int __maybe_unused igb_runtime_idle(struct device *dev)
9524 {
9525 struct net_device *netdev = dev_get_drvdata(dev);
9526 struct igb_adapter *adapter = netdev_priv(netdev);
9527
9528 if (!igb_has_link(adapter))
9529 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9530
9531 return -EBUSY;
9532 }
9533
igb_runtime_suspend(struct device * dev)9534 static int __maybe_unused igb_runtime_suspend(struct device *dev)
9535 {
9536 return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9537 }
9538
igb_runtime_resume(struct device * dev)9539 static int __maybe_unused igb_runtime_resume(struct device *dev)
9540 {
9541 return __igb_resume(dev, true);
9542 }
9543
igb_shutdown(struct pci_dev * pdev)9544 static void igb_shutdown(struct pci_dev *pdev)
9545 {
9546 bool wake;
9547
9548 __igb_shutdown(pdev, &wake, 0);
9549
9550 if (system_state == SYSTEM_POWER_OFF) {
9551 pci_wake_from_d3(pdev, wake);
9552 pci_set_power_state(pdev, PCI_D3hot);
9553 }
9554 }
9555
igb_pci_sriov_configure(struct pci_dev * dev,int num_vfs)9556 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9557 {
9558 #ifdef CONFIG_PCI_IOV
9559 int err;
9560
9561 if (num_vfs == 0) {
9562 return igb_disable_sriov(dev, true);
9563 } else {
9564 err = igb_enable_sriov(dev, num_vfs, true);
9565 return err ? err : num_vfs;
9566 }
9567 #endif
9568 return 0;
9569 }
9570
9571 /**
9572 * igb_io_error_detected - called when PCI error is detected
9573 * @pdev: Pointer to PCI device
9574 * @state: The current pci connection state
9575 *
9576 * This function is called after a PCI bus error affecting
9577 * this device has been detected.
9578 **/
igb_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)9579 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9580 pci_channel_state_t state)
9581 {
9582 struct net_device *netdev = pci_get_drvdata(pdev);
9583 struct igb_adapter *adapter = netdev_priv(netdev);
9584
9585 if (state == pci_channel_io_normal) {
9586 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n");
9587 return PCI_ERS_RESULT_CAN_RECOVER;
9588 }
9589
9590 netif_device_detach(netdev);
9591
9592 if (state == pci_channel_io_perm_failure)
9593 return PCI_ERS_RESULT_DISCONNECT;
9594
9595 if (netif_running(netdev))
9596 igb_down(adapter);
9597 pci_disable_device(pdev);
9598
9599 /* Request a slot reset. */
9600 return PCI_ERS_RESULT_NEED_RESET;
9601 }
9602
9603 /**
9604 * igb_io_slot_reset - called after the pci bus has been reset.
9605 * @pdev: Pointer to PCI device
9606 *
9607 * Restart the card from scratch, as if from a cold-boot. Implementation
9608 * resembles the first-half of the __igb_resume routine.
9609 **/
igb_io_slot_reset(struct pci_dev * pdev)9610 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9611 {
9612 struct net_device *netdev = pci_get_drvdata(pdev);
9613 struct igb_adapter *adapter = netdev_priv(netdev);
9614 struct e1000_hw *hw = &adapter->hw;
9615 pci_ers_result_t result;
9616
9617 if (pci_enable_device_mem(pdev)) {
9618 dev_err(&pdev->dev,
9619 "Cannot re-enable PCI device after reset.\n");
9620 result = PCI_ERS_RESULT_DISCONNECT;
9621 } else {
9622 pci_set_master(pdev);
9623 pci_restore_state(pdev);
9624 pci_save_state(pdev);
9625
9626 pci_enable_wake(pdev, PCI_D3hot, 0);
9627 pci_enable_wake(pdev, PCI_D3cold, 0);
9628
9629 /* In case of PCI error, adapter lose its HW address
9630 * so we should re-assign it here.
9631 */
9632 hw->hw_addr = adapter->io_addr;
9633
9634 igb_reset(adapter);
9635 wr32(E1000_WUS, ~0);
9636 result = PCI_ERS_RESULT_RECOVERED;
9637 }
9638
9639 return result;
9640 }
9641
9642 /**
9643 * igb_io_resume - called when traffic can start flowing again.
9644 * @pdev: Pointer to PCI device
9645 *
9646 * This callback is called when the error recovery driver tells us that
9647 * its OK to resume normal operation. Implementation resembles the
9648 * second-half of the __igb_resume routine.
9649 */
igb_io_resume(struct pci_dev * pdev)9650 static void igb_io_resume(struct pci_dev *pdev)
9651 {
9652 struct net_device *netdev = pci_get_drvdata(pdev);
9653 struct igb_adapter *adapter = netdev_priv(netdev);
9654
9655 if (netif_running(netdev)) {
9656 if (igb_up(adapter)) {
9657 dev_err(&pdev->dev, "igb_up failed after reset\n");
9658 return;
9659 }
9660 }
9661
9662 netif_device_attach(netdev);
9663
9664 /* let the f/w know that the h/w is now under the control of the
9665 * driver.
9666 */
9667 igb_get_hw_control(adapter);
9668 }
9669
9670 /**
9671 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9672 * @adapter: Pointer to adapter structure
9673 * @index: Index of the RAR entry which need to be synced with MAC table
9674 **/
igb_rar_set_index(struct igb_adapter * adapter,u32 index)9675 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9676 {
9677 struct e1000_hw *hw = &adapter->hw;
9678 u32 rar_low, rar_high;
9679 u8 *addr = adapter->mac_table[index].addr;
9680
9681 /* HW expects these to be in network order when they are plugged
9682 * into the registers which are little endian. In order to guarantee
9683 * that ordering we need to do an leXX_to_cpup here in order to be
9684 * ready for the byteswap that occurs with writel
9685 */
9686 rar_low = le32_to_cpup((__le32 *)(addr));
9687 rar_high = le16_to_cpup((__le16 *)(addr + 4));
9688
9689 /* Indicate to hardware the Address is Valid. */
9690 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9691 if (is_valid_ether_addr(addr))
9692 rar_high |= E1000_RAH_AV;
9693
9694 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9695 rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9696
9697 switch (hw->mac.type) {
9698 case e1000_82575:
9699 case e1000_i210:
9700 if (adapter->mac_table[index].state &
9701 IGB_MAC_STATE_QUEUE_STEERING)
9702 rar_high |= E1000_RAH_QSEL_ENABLE;
9703
9704 rar_high |= E1000_RAH_POOL_1 *
9705 adapter->mac_table[index].queue;
9706 break;
9707 default:
9708 rar_high |= E1000_RAH_POOL_1 <<
9709 adapter->mac_table[index].queue;
9710 break;
9711 }
9712 }
9713
9714 wr32(E1000_RAL(index), rar_low);
9715 wrfl();
9716 wr32(E1000_RAH(index), rar_high);
9717 wrfl();
9718 }
9719
igb_set_vf_mac(struct igb_adapter * adapter,int vf,unsigned char * mac_addr)9720 static int igb_set_vf_mac(struct igb_adapter *adapter,
9721 int vf, unsigned char *mac_addr)
9722 {
9723 struct e1000_hw *hw = &adapter->hw;
9724 /* VF MAC addresses start at end of receive addresses and moves
9725 * towards the first, as a result a collision should not be possible
9726 */
9727 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9728 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9729
9730 ether_addr_copy(vf_mac_addr, mac_addr);
9731 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9732 adapter->mac_table[rar_entry].queue = vf;
9733 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9734 igb_rar_set_index(adapter, rar_entry);
9735
9736 return 0;
9737 }
9738
igb_ndo_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)9739 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9740 {
9741 struct igb_adapter *adapter = netdev_priv(netdev);
9742
9743 if (vf >= adapter->vfs_allocated_count)
9744 return -EINVAL;
9745
9746 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9747 * flag and allows to overwrite the MAC via VF netdev. This
9748 * is necessary to allow libvirt a way to restore the original
9749 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9750 * down a VM.
9751 */
9752 if (is_zero_ether_addr(mac)) {
9753 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9754 dev_info(&adapter->pdev->dev,
9755 "remove administratively set MAC on VF %d\n",
9756 vf);
9757 } else if (is_valid_ether_addr(mac)) {
9758 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9759 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9760 mac, vf);
9761 dev_info(&adapter->pdev->dev,
9762 "Reload the VF driver to make this change effective.");
9763 /* Generate additional warning if PF is down */
9764 if (test_bit(__IGB_DOWN, &adapter->state)) {
9765 dev_warn(&adapter->pdev->dev,
9766 "The VF MAC address has been set, but the PF device is not up.\n");
9767 dev_warn(&adapter->pdev->dev,
9768 "Bring the PF device up before attempting to use the VF device.\n");
9769 }
9770 } else {
9771 return -EINVAL;
9772 }
9773 return igb_set_vf_mac(adapter, vf, mac);
9774 }
9775
igb_link_mbps(int internal_link_speed)9776 static int igb_link_mbps(int internal_link_speed)
9777 {
9778 switch (internal_link_speed) {
9779 case SPEED_100:
9780 return 100;
9781 case SPEED_1000:
9782 return 1000;
9783 default:
9784 return 0;
9785 }
9786 }
9787
igb_set_vf_rate_limit(struct e1000_hw * hw,int vf,int tx_rate,int link_speed)9788 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9789 int link_speed)
9790 {
9791 int rf_dec, rf_int;
9792 u32 bcnrc_val;
9793
9794 if (tx_rate != 0) {
9795 /* Calculate the rate factor values to set */
9796 rf_int = link_speed / tx_rate;
9797 rf_dec = (link_speed - (rf_int * tx_rate));
9798 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9799 tx_rate;
9800
9801 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9802 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9803 E1000_RTTBCNRC_RF_INT_MASK);
9804 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9805 } else {
9806 bcnrc_val = 0;
9807 }
9808
9809 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9810 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9811 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9812 */
9813 wr32(E1000_RTTBCNRM, 0x14);
9814 wr32(E1000_RTTBCNRC, bcnrc_val);
9815 }
9816
igb_check_vf_rate_limit(struct igb_adapter * adapter)9817 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9818 {
9819 int actual_link_speed, i;
9820 bool reset_rate = false;
9821
9822 /* VF TX rate limit was not set or not supported */
9823 if ((adapter->vf_rate_link_speed == 0) ||
9824 (adapter->hw.mac.type != e1000_82576))
9825 return;
9826
9827 actual_link_speed = igb_link_mbps(adapter->link_speed);
9828 if (actual_link_speed != adapter->vf_rate_link_speed) {
9829 reset_rate = true;
9830 adapter->vf_rate_link_speed = 0;
9831 dev_info(&adapter->pdev->dev,
9832 "Link speed has been changed. VF Transmit rate is disabled\n");
9833 }
9834
9835 for (i = 0; i < adapter->vfs_allocated_count; i++) {
9836 if (reset_rate)
9837 adapter->vf_data[i].tx_rate = 0;
9838
9839 igb_set_vf_rate_limit(&adapter->hw, i,
9840 adapter->vf_data[i].tx_rate,
9841 actual_link_speed);
9842 }
9843 }
9844
igb_ndo_set_vf_bw(struct net_device * netdev,int vf,int min_tx_rate,int max_tx_rate)9845 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9846 int min_tx_rate, int max_tx_rate)
9847 {
9848 struct igb_adapter *adapter = netdev_priv(netdev);
9849 struct e1000_hw *hw = &adapter->hw;
9850 int actual_link_speed;
9851
9852 if (hw->mac.type != e1000_82576)
9853 return -EOPNOTSUPP;
9854
9855 if (min_tx_rate)
9856 return -EINVAL;
9857
9858 actual_link_speed = igb_link_mbps(adapter->link_speed);
9859 if ((vf >= adapter->vfs_allocated_count) ||
9860 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9861 (max_tx_rate < 0) ||
9862 (max_tx_rate > actual_link_speed))
9863 return -EINVAL;
9864
9865 adapter->vf_rate_link_speed = actual_link_speed;
9866 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9867 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9868
9869 return 0;
9870 }
9871
igb_ndo_set_vf_spoofchk(struct net_device * netdev,int vf,bool setting)9872 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9873 bool setting)
9874 {
9875 struct igb_adapter *adapter = netdev_priv(netdev);
9876 struct e1000_hw *hw = &adapter->hw;
9877 u32 reg_val, reg_offset;
9878
9879 if (!adapter->vfs_allocated_count)
9880 return -EOPNOTSUPP;
9881
9882 if (vf >= adapter->vfs_allocated_count)
9883 return -EINVAL;
9884
9885 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9886 reg_val = rd32(reg_offset);
9887 if (setting)
9888 reg_val |= (BIT(vf) |
9889 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9890 else
9891 reg_val &= ~(BIT(vf) |
9892 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9893 wr32(reg_offset, reg_val);
9894
9895 adapter->vf_data[vf].spoofchk_enabled = setting;
9896 return 0;
9897 }
9898
igb_ndo_set_vf_trust(struct net_device * netdev,int vf,bool setting)9899 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9900 {
9901 struct igb_adapter *adapter = netdev_priv(netdev);
9902
9903 if (vf >= adapter->vfs_allocated_count)
9904 return -EINVAL;
9905 if (adapter->vf_data[vf].trusted == setting)
9906 return 0;
9907
9908 adapter->vf_data[vf].trusted = setting;
9909
9910 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9911 vf, setting ? "" : "not ");
9912 return 0;
9913 }
9914
igb_ndo_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivi)9915 static int igb_ndo_get_vf_config(struct net_device *netdev,
9916 int vf, struct ifla_vf_info *ivi)
9917 {
9918 struct igb_adapter *adapter = netdev_priv(netdev);
9919 if (vf >= adapter->vfs_allocated_count)
9920 return -EINVAL;
9921 ivi->vf = vf;
9922 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9923 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9924 ivi->min_tx_rate = 0;
9925 ivi->vlan = adapter->vf_data[vf].pf_vlan;
9926 ivi->qos = adapter->vf_data[vf].pf_qos;
9927 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9928 ivi->trusted = adapter->vf_data[vf].trusted;
9929 return 0;
9930 }
9931
igb_vmm_control(struct igb_adapter * adapter)9932 static void igb_vmm_control(struct igb_adapter *adapter)
9933 {
9934 struct e1000_hw *hw = &adapter->hw;
9935 u32 reg;
9936
9937 switch (hw->mac.type) {
9938 case e1000_82575:
9939 case e1000_i210:
9940 case e1000_i211:
9941 case e1000_i354:
9942 default:
9943 /* replication is not supported for 82575 */
9944 return;
9945 case e1000_82576:
9946 /* notify HW that the MAC is adding vlan tags */
9947 reg = rd32(E1000_DTXCTL);
9948 reg |= E1000_DTXCTL_VLAN_ADDED;
9949 wr32(E1000_DTXCTL, reg);
9950 fallthrough;
9951 case e1000_82580:
9952 /* enable replication vlan tag stripping */
9953 reg = rd32(E1000_RPLOLR);
9954 reg |= E1000_RPLOLR_STRVLAN;
9955 wr32(E1000_RPLOLR, reg);
9956 fallthrough;
9957 case e1000_i350:
9958 /* none of the above registers are supported by i350 */
9959 break;
9960 }
9961
9962 if (adapter->vfs_allocated_count) {
9963 igb_vmdq_set_loopback_pf(hw, true);
9964 igb_vmdq_set_replication_pf(hw, true);
9965 igb_vmdq_set_anti_spoofing_pf(hw, true,
9966 adapter->vfs_allocated_count);
9967 } else {
9968 igb_vmdq_set_loopback_pf(hw, false);
9969 igb_vmdq_set_replication_pf(hw, false);
9970 }
9971 }
9972
igb_init_dmac(struct igb_adapter * adapter,u32 pba)9973 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9974 {
9975 struct e1000_hw *hw = &adapter->hw;
9976 u32 dmac_thr;
9977 u16 hwm;
9978 u32 reg;
9979
9980 if (hw->mac.type > e1000_82580) {
9981 if (adapter->flags & IGB_FLAG_DMAC) {
9982 /* force threshold to 0. */
9983 wr32(E1000_DMCTXTH, 0);
9984
9985 /* DMA Coalescing high water mark needs to be greater
9986 * than the Rx threshold. Set hwm to PBA - max frame
9987 * size in 16B units, capping it at PBA - 6KB.
9988 */
9989 hwm = 64 * (pba - 6);
9990 reg = rd32(E1000_FCRTC);
9991 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9992 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9993 & E1000_FCRTC_RTH_COAL_MASK);
9994 wr32(E1000_FCRTC, reg);
9995
9996 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9997 * frame size, capping it at PBA - 10KB.
9998 */
9999 dmac_thr = pba - 10;
10000 reg = rd32(E1000_DMACR);
10001 reg &= ~E1000_DMACR_DMACTHR_MASK;
10002 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
10003 & E1000_DMACR_DMACTHR_MASK);
10004
10005 /* transition to L0x or L1 if available..*/
10006 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
10007
10008 /* watchdog timer= +-1000 usec in 32usec intervals */
10009 reg |= (1000 >> 5);
10010
10011 /* Disable BMC-to-OS Watchdog Enable */
10012 if (hw->mac.type != e1000_i354)
10013 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
10014 wr32(E1000_DMACR, reg);
10015
10016 /* no lower threshold to disable
10017 * coalescing(smart fifb)-UTRESH=0
10018 */
10019 wr32(E1000_DMCRTRH, 0);
10020
10021 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
10022
10023 wr32(E1000_DMCTLX, reg);
10024
10025 /* free space in tx packet buffer to wake from
10026 * DMA coal
10027 */
10028 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
10029 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
10030 }
10031
10032 if (hw->mac.type >= e1000_i210 ||
10033 (adapter->flags & IGB_FLAG_DMAC)) {
10034 reg = rd32(E1000_PCIEMISC);
10035 reg |= E1000_PCIEMISC_LX_DECISION;
10036 wr32(E1000_PCIEMISC, reg);
10037 } /* endif adapter->dmac is not disabled */
10038 } else if (hw->mac.type == e1000_82580) {
10039 u32 reg = rd32(E1000_PCIEMISC);
10040
10041 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
10042 wr32(E1000_DMACR, 0);
10043 }
10044 }
10045
10046 /**
10047 * igb_read_i2c_byte - Reads 8 bit word over I2C
10048 * @hw: pointer to hardware structure
10049 * @byte_offset: byte offset to read
10050 * @dev_addr: device address
10051 * @data: value read
10052 *
10053 * Performs byte read operation over I2C interface at
10054 * a specified device address.
10055 **/
igb_read_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)10056 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10057 u8 dev_addr, u8 *data)
10058 {
10059 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10060 struct i2c_client *this_client = adapter->i2c_client;
10061 s32 status;
10062 u16 swfw_mask = 0;
10063
10064 if (!this_client)
10065 return E1000_ERR_I2C;
10066
10067 swfw_mask = E1000_SWFW_PHY0_SM;
10068
10069 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10070 return E1000_ERR_SWFW_SYNC;
10071
10072 status = i2c_smbus_read_byte_data(this_client, byte_offset);
10073 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10074
10075 if (status < 0)
10076 return E1000_ERR_I2C;
10077 else {
10078 *data = status;
10079 return 0;
10080 }
10081 }
10082
10083 /**
10084 * igb_write_i2c_byte - Writes 8 bit word over I2C
10085 * @hw: pointer to hardware structure
10086 * @byte_offset: byte offset to write
10087 * @dev_addr: device address
10088 * @data: value to write
10089 *
10090 * Performs byte write operation over I2C interface at
10091 * a specified device address.
10092 **/
igb_write_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)10093 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10094 u8 dev_addr, u8 data)
10095 {
10096 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10097 struct i2c_client *this_client = adapter->i2c_client;
10098 s32 status;
10099 u16 swfw_mask = E1000_SWFW_PHY0_SM;
10100
10101 if (!this_client)
10102 return E1000_ERR_I2C;
10103
10104 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10105 return E1000_ERR_SWFW_SYNC;
10106 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
10107 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10108
10109 if (status)
10110 return E1000_ERR_I2C;
10111 else
10112 return 0;
10113
10114 }
10115
igb_reinit_queues(struct igb_adapter * adapter)10116 int igb_reinit_queues(struct igb_adapter *adapter)
10117 {
10118 struct net_device *netdev = adapter->netdev;
10119 struct pci_dev *pdev = adapter->pdev;
10120 int err = 0;
10121
10122 if (netif_running(netdev))
10123 igb_close(netdev);
10124
10125 igb_reset_interrupt_capability(adapter);
10126
10127 if (igb_init_interrupt_scheme(adapter, true)) {
10128 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
10129 return -ENOMEM;
10130 }
10131
10132 if (netif_running(netdev))
10133 err = igb_open(netdev);
10134
10135 return err;
10136 }
10137
igb_nfc_filter_exit(struct igb_adapter * adapter)10138 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
10139 {
10140 struct igb_nfc_filter *rule;
10141
10142 spin_lock(&adapter->nfc_lock);
10143
10144 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10145 igb_erase_filter(adapter, rule);
10146
10147 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
10148 igb_erase_filter(adapter, rule);
10149
10150 spin_unlock(&adapter->nfc_lock);
10151 }
10152
igb_nfc_filter_restore(struct igb_adapter * adapter)10153 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
10154 {
10155 struct igb_nfc_filter *rule;
10156
10157 spin_lock(&adapter->nfc_lock);
10158
10159 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10160 igb_add_filter(adapter, rule);
10161
10162 spin_unlock(&adapter->nfc_lock);
10163 }
10164 /* igb_main.c */
10165