1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	auddsm {
15		/omit-if-no-ref/
16		auddsm_pins: auddsm-pins {
17			rockchip,pins =
18				/* auddsm_ln */
19				<3 RK_PA1 4 &pcfg_pull_none>,
20				/* auddsm_lp */
21				<3 RK_PA2 4 &pcfg_pull_none>,
22				/* auddsm_rn */
23				<3 RK_PA3 4 &pcfg_pull_none>,
24				/* auddsm_rp */
25				<3 RK_PA4 4 &pcfg_pull_none>;
26		};
27	};
28
29	bt1120 {
30		/omit-if-no-ref/
31		bt1120_pins: bt1120-pins {
32			rockchip,pins =
33				/* bt1120_clkout */
34				<4 RK_PB0 2 &pcfg_pull_none>,
35				/* bt1120_d0 */
36				<4 RK_PA0 2 &pcfg_pull_none>,
37				/* bt1120_d1 */
38				<4 RK_PA1 2 &pcfg_pull_none>,
39				/* bt1120_d2 */
40				<4 RK_PA2 2 &pcfg_pull_none>,
41				/* bt1120_d3 */
42				<4 RK_PA3 2 &pcfg_pull_none>,
43				/* bt1120_d4 */
44				<4 RK_PA4 2 &pcfg_pull_none>,
45				/* bt1120_d5 */
46				<4 RK_PA5 2 &pcfg_pull_none>,
47				/* bt1120_d6 */
48				<4 RK_PA6 2 &pcfg_pull_none>,
49				/* bt1120_d7 */
50				<4 RK_PA7 2 &pcfg_pull_none>,
51				/* bt1120_d8 */
52				<4 RK_PB2 2 &pcfg_pull_none>,
53				/* bt1120_d9 */
54				<4 RK_PB3 2 &pcfg_pull_none>,
55				/* bt1120_d10 */
56				<4 RK_PB4 2 &pcfg_pull_none>,
57				/* bt1120_d11 */
58				<4 RK_PB5 2 &pcfg_pull_none>,
59				/* bt1120_d12 */
60				<4 RK_PB6 2 &pcfg_pull_none>,
61				/* bt1120_d13 */
62				<4 RK_PB7 2 &pcfg_pull_none>,
63				/* bt1120_d14 */
64				<4 RK_PC0 2 &pcfg_pull_none>,
65				/* bt1120_d15 */
66				<4 RK_PC1 2 &pcfg_pull_none>;
67		};
68	};
69
70	can0 {
71		/omit-if-no-ref/
72		can0m0_pins: can0m0-pins {
73			rockchip,pins =
74				/* can0_rx_m0 */
75				<0 RK_PC0 11 &pcfg_pull_none>,
76				/* can0_tx_m0 */
77				<0 RK_PB7 11 &pcfg_pull_none>;
78		};
79
80		/omit-if-no-ref/
81		can0m1_pins: can0m1-pins {
82			rockchip,pins =
83				/* can0_rx_m1 */
84				<4 RK_PD5 9 &pcfg_pull_none>,
85				/* can0_tx_m1 */
86				<4 RK_PD4 9 &pcfg_pull_none>;
87		};
88	};
89
90	can1 {
91		/omit-if-no-ref/
92		can1m0_pins: can1m0-pins {
93			rockchip,pins =
94				/* can1_rx_m0 */
95				<3 RK_PB5 9 &pcfg_pull_none>,
96				/* can1_tx_m0 */
97				<3 RK_PB6 9 &pcfg_pull_none>;
98		};
99
100		/omit-if-no-ref/
101		can1m1_pins: can1m1-pins {
102			rockchip,pins =
103				/* can1_rx_m1 */
104				<4 RK_PB2 12 &pcfg_pull_none>,
105				/* can1_tx_m1 */
106				<4 RK_PB3 12 &pcfg_pull_none>;
107		};
108	};
109
110	can2 {
111		/omit-if-no-ref/
112		can2m0_pins: can2m0-pins {
113			rockchip,pins =
114				/* can2_rx_m0 */
115				<3 RK_PC4 9 &pcfg_pull_none>,
116				/* can2_tx_m0 */
117				<3 RK_PC5 9 &pcfg_pull_none>;
118		};
119
120		/omit-if-no-ref/
121		can2m1_pins: can2m1-pins {
122			rockchip,pins =
123				/* can2_rx_m1 */
124				<0 RK_PD4 10 &pcfg_pull_none>,
125				/* can2_tx_m1 */
126				<0 RK_PD5 10 &pcfg_pull_none>;
127		};
128	};
129
130	cif {
131		/omit-if-no-ref/
132		cif_clk: cif-clk {
133			rockchip,pins =
134				/* cif_clkout */
135				<4 RK_PB4 1 &pcfg_pull_none>;
136		};
137
138		/omit-if-no-ref/
139		cif_dvp_clk: cif-dvp-clk {
140			rockchip,pins =
141				/* cif_clkin */
142				<4 RK_PB0 1 &pcfg_pull_none>,
143				/* cif_href */
144				<4 RK_PB2 1 &pcfg_pull_none>,
145				/* cif_vsync */
146				<4 RK_PB3 1 &pcfg_pull_none>;
147		};
148
149		/omit-if-no-ref/
150		cif_dvp_bus16: cif-dvp-bus16 {
151			rockchip,pins =
152				/* cif_d8 */
153				<3 RK_PC4 1 &pcfg_pull_none>,
154				/* cif_d9 */
155				<3 RK_PC5 1 &pcfg_pull_none>,
156				/* cif_d10 */
157				<3 RK_PC6 1 &pcfg_pull_none>,
158				/* cif_d11 */
159				<3 RK_PC7 1 &pcfg_pull_none>,
160				/* cif_d12 */
161				<3 RK_PD0 1 &pcfg_pull_none>,
162				/* cif_d13 */
163				<3 RK_PD1 1 &pcfg_pull_none>,
164				/* cif_d14 */
165				<3 RK_PD2 1 &pcfg_pull_none>,
166				/* cif_d15 */
167				<3 RK_PD3 1 &pcfg_pull_none>;
168		};
169
170		/omit-if-no-ref/
171		cif_dvp_bus8: cif-dvp-bus8 {
172			rockchip,pins =
173				/* cif_d0 */
174				<4 RK_PA0 1 &pcfg_pull_none>,
175				/* cif_d1 */
176				<4 RK_PA1 1 &pcfg_pull_none>,
177				/* cif_d2 */
178				<4 RK_PA2 1 &pcfg_pull_none>,
179				/* cif_d3 */
180				<4 RK_PA3 1 &pcfg_pull_none>,
181				/* cif_d4 */
182				<4 RK_PA4 1 &pcfg_pull_none>,
183				/* cif_d5 */
184				<4 RK_PA5 1 &pcfg_pull_none>,
185				/* cif_d6 */
186				<4 RK_PA6 1 &pcfg_pull_none>,
187				/* cif_d7 */
188				<4 RK_PA7 1 &pcfg_pull_none>;
189		};
190	};
191
192	clk32k {
193		/omit-if-no-ref/
194		clk32k_in: clk32k-in {
195			rockchip,pins =
196				/* clk32k_in */
197				<0 RK_PB2 1 &pcfg_pull_none>;
198		};
199
200		/omit-if-no-ref/
201		clk32k_out0: clk32k-out0 {
202			rockchip,pins =
203				/* clk32k_out0 */
204				<0 RK_PB2 2 &pcfg_pull_none>;
205		};
206	};
207
208	cpu {
209		/omit-if-no-ref/
210		cpu_pins: cpu-pins {
211			rockchip,pins =
212				/* cpu_big0_avs */
213				<0 RK_PD1 2 &pcfg_pull_none>,
214				/* cpu_big1_avs */
215				<0 RK_PD5 2 &pcfg_pull_none>;
216		};
217	};
218
219	ddrphych0 {
220		/omit-if-no-ref/
221		ddrphych0_pins: ddrphych0-pins {
222			rockchip,pins =
223				/* ddrphych0_dtb0 */
224				<4 RK_PA0 7 &pcfg_pull_none>,
225				/* ddrphych0_dtb1 */
226				<4 RK_PA1 7 &pcfg_pull_none>,
227				/* ddrphych0_dtb2 */
228				<4 RK_PA2 7 &pcfg_pull_none>,
229				/* ddrphych0_dtb3 */
230				<4 RK_PA3 7 &pcfg_pull_none>;
231		};
232	};
233
234	ddrphych1 {
235		/omit-if-no-ref/
236		ddrphych1_pins: ddrphych1-pins {
237			rockchip,pins =
238				/* ddrphych1_dtb0 */
239				<4 RK_PA4 7 &pcfg_pull_none>,
240				/* ddrphych1_dtb1 */
241				<4 RK_PA5 7 &pcfg_pull_none>,
242				/* ddrphych1_dtb2 */
243				<4 RK_PA6 7 &pcfg_pull_none>,
244				/* ddrphych1_dtb3 */
245				<4 RK_PA7 7 &pcfg_pull_none>;
246		};
247	};
248
249	ddrphych2 {
250		/omit-if-no-ref/
251		ddrphych2_pins: ddrphych2-pins {
252			rockchip,pins =
253				/* ddrphych2_dtb0 */
254				<4 RK_PB0 7 &pcfg_pull_none>,
255				/* ddrphych2_dtb1 */
256				<4 RK_PB1 7 &pcfg_pull_none>,
257				/* ddrphych2_dtb2 */
258				<4 RK_PB2 7 &pcfg_pull_none>,
259				/* ddrphych2_dtb3 */
260				<4 RK_PB3 7 &pcfg_pull_none>;
261		};
262	};
263
264	ddrphych3 {
265		/omit-if-no-ref/
266		ddrphych3_pins: ddrphych3-pins {
267			rockchip,pins =
268				/* ddrphych3_dtb0 */
269				<4 RK_PB4 7 &pcfg_pull_none>,
270				/* ddrphych3_dtb1 */
271				<4 RK_PB5 7 &pcfg_pull_none>,
272				/* ddrphych3_dtb2 */
273				<4 RK_PB6 7 &pcfg_pull_none>,
274				/* ddrphych3_dtb3 */
275				<4 RK_PB7 7 &pcfg_pull_none>;
276		};
277	};
278
279	dp0 {
280		/omit-if-no-ref/
281		dp0m0_pins: dp0m0-pins {
282			rockchip,pins =
283				/* dp0_hpdin_m0 */
284				<4 RK_PB4 5 &pcfg_pull_none>;
285		};
286
287		/omit-if-no-ref/
288		dp0m1_pins: dp0m1-pins {
289			rockchip,pins =
290				/* dp0_hpdin_m1 */
291				<0 RK_PC4 10 &pcfg_pull_none>;
292		};
293
294		/omit-if-no-ref/
295		dp0m2_pins: dp0m2-pins {
296			rockchip,pins =
297				/* dp0_hpdin_m2 */
298				<1 RK_PA0 5 &pcfg_pull_none>;
299		};
300	};
301
302	dp1 {
303		/omit-if-no-ref/
304		dp1m0_pins: dp1m0-pins {
305			rockchip,pins =
306				/* dp1_hpdin_m0 */
307				<3 RK_PD5 5 &pcfg_pull_none>;
308		};
309
310		/omit-if-no-ref/
311		dp1m1_pins: dp1m1-pins {
312			rockchip,pins =
313				/* dp1_hpdin_m1 */
314				<0 RK_PC5 10 &pcfg_pull_none>;
315		};
316
317		/omit-if-no-ref/
318		dp1m2_pins: dp1m2-pins {
319			rockchip,pins =
320				/* dp1_hpdin_m2 */
321				<1 RK_PA1 5 &pcfg_pull_none>;
322		};
323	};
324
325	emmc {
326		/omit-if-no-ref/
327		emmc_rstnout: emmc-rstnout {
328			rockchip,pins =
329				/* emmc_rstn */
330				<2 RK_PA3 1 &pcfg_pull_none>;
331		};
332
333		/omit-if-no-ref/
334		emmc_bus8: emmc-bus8 {
335			rockchip,pins =
336				/* emmc_d0 */
337				<2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
338				/* emmc_d1 */
339				<2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
340				/* emmc_d2 */
341				<2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
342				/* emmc_d3 */
343				<2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
344				/* emmc_d4 */
345				<2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
346				/* emmc_d5 */
347				<2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
348				/* emmc_d6 */
349				<2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
350				/* emmc_d7 */
351				<2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
352		};
353
354		/omit-if-no-ref/
355		emmc_clk: emmc-clk {
356			rockchip,pins =
357				/* emmc_clkout */
358				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
359		};
360
361		/omit-if-no-ref/
362		emmc_cmd: emmc-cmd {
363			rockchip,pins =
364				/* emmc_cmd */
365				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
366		};
367
368		/omit-if-no-ref/
369		emmc_data_strobe: emmc-data-strobe {
370			rockchip,pins =
371				/* emmc_data_strobe */
372				<2 RK_PA2 1 &pcfg_pull_down>;
373		};
374	};
375
376	eth1 {
377		/omit-if-no-ref/
378		eth1_pins: eth1-pins {
379			rockchip,pins =
380				/* eth1_refclko_25m */
381				<3 RK_PA6 1 &pcfg_pull_none>;
382		};
383	};
384
385	fspi {
386		/omit-if-no-ref/
387		fspim0_pins: fspim0-pins {
388			rockchip,pins =
389				/* fspi_clk_m0 */
390				<2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
391				/* fspi_cs0n_m0 */
392				<2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
393				/* fspi_d0_m0 */
394				<2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
395				/* fspi_d1_m0 */
396				<2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
397				/* fspi_d2_m0 */
398				<2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
399				/* fspi_d3_m0 */
400				<2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
401		};
402
403		/omit-if-no-ref/
404		fspim0_cs1: fspim0-cs1 {
405			rockchip,pins =
406				/* fspi_cs1n_m0 */
407				<2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
408		};
409
410		/omit-if-no-ref/
411		fspim2_pins: fspim2-pins {
412			rockchip,pins =
413				/* fspi_clk_m2 */
414				<3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
415				/* fspi_cs0n_m2 */
416				<3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
417				/* fspi_d0_m2 */
418				<3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
419				/* fspi_d1_m2 */
420				<3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
421				/* fspi_d2_m2 */
422				<3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
423				/* fspi_d3_m2 */
424				<3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
425		};
426
427		/omit-if-no-ref/
428		fspim2_cs1: fspim2-cs1 {
429			rockchip,pins =
430				/* fspi_cs1n_m2 */
431				<3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
432		};
433	};
434
435	gmac1 {
436		/omit-if-no-ref/
437		gmac1_miim: gmac1-miim {
438			rockchip,pins =
439				/* gmac1_mdc */
440				<3 RK_PC2 1 &pcfg_pull_none>,
441				/* gmac1_mdio */
442				<3 RK_PC3 1 &pcfg_pull_none>;
443		};
444
445		/omit-if-no-ref/
446		gmac1_clkinout: gmac1-clkinout {
447			rockchip,pins =
448				/* gmac1_mclkinout */
449				<3 RK_PB6 1 &pcfg_pull_none>;
450		};
451
452		/omit-if-no-ref/
453		gmac1_rx_bus2: gmac1-rx-bus2 {
454			rockchip,pins =
455				/* gmac1_rxd0 */
456				<3 RK_PA7 1 &pcfg_pull_none>,
457				/* gmac1_rxd1 */
458				<3 RK_PB0 1 &pcfg_pull_none>,
459				/* gmac1_rxdv_crs */
460				<3 RK_PB1 1 &pcfg_pull_none>;
461		};
462
463		/omit-if-no-ref/
464		gmac1_tx_bus2: gmac1-tx-bus2 {
465			rockchip,pins =
466				/* gmac1_txd0 */
467				<3 RK_PB3 1 &pcfg_pull_none>,
468				/* gmac1_txd1 */
469				<3 RK_PB4 1 &pcfg_pull_none>,
470				/* gmac1_txen */
471				<3 RK_PB5 1 &pcfg_pull_none>;
472		};
473
474		/omit-if-no-ref/
475		gmac1_rgmii_clk: gmac1-rgmii-clk {
476			rockchip,pins =
477				/* gmac1_rxclk */
478				<3 RK_PA5 1 &pcfg_pull_none>,
479				/* gmac1_txclk */
480				<3 RK_PA4 1 &pcfg_pull_none>;
481		};
482
483		/omit-if-no-ref/
484		gmac1_rgmii_bus: gmac1-rgmii-bus {
485			rockchip,pins =
486				/* gmac1_rxd2 */
487				<3 RK_PA2 1 &pcfg_pull_none>,
488				/* gmac1_rxd3 */
489				<3 RK_PA3 1 &pcfg_pull_none>,
490				/* gmac1_txd2 */
491				<3 RK_PA0 1 &pcfg_pull_none>,
492				/* gmac1_txd3 */
493				<3 RK_PA1 1 &pcfg_pull_none>;
494		};
495
496		/omit-if-no-ref/
497		gmac1_ppsclk: gmac1-ppsclk {
498			rockchip,pins =
499				/* gmac1_ppsclk */
500				<3 RK_PC1 1 &pcfg_pull_none>;
501		};
502
503		/omit-if-no-ref/
504		gmac1_ppstrig: gmac1-ppstrig {
505			rockchip,pins =
506				/* gmac1_ppstrig */
507				<3 RK_PC0 1 &pcfg_pull_none>;
508		};
509
510		/omit-if-no-ref/
511		gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
512			rockchip,pins =
513				/* gmac1_ptp_ref_clk */
514				<3 RK_PB7 1 &pcfg_pull_none>;
515		};
516
517		/omit-if-no-ref/
518		gmac1_txer: gmac1-txer {
519			rockchip,pins =
520				/* gmac1_txer */
521				<3 RK_PB2 1 &pcfg_pull_none>;
522		};
523	};
524
525	gpu {
526		/omit-if-no-ref/
527		gpu_pins: gpu-pins {
528			rockchip,pins =
529				/* gpu_avs */
530				<0 RK_PC5 2 &pcfg_pull_none>;
531		};
532	};
533
534	hdmi {
535		/omit-if-no-ref/
536		hdmim0_rx_cec: hdmim0-rx-cec {
537			rockchip,pins =
538				/* hdmim0_rx_cec */
539				<4 RK_PB5 5 &pcfg_pull_none>;
540		};
541
542		/omit-if-no-ref/
543		hdmim0_rx_hpdin: hdmim0-rx-hpdin {
544			rockchip,pins =
545				/* hdmim0_rx_hpdin */
546				<4 RK_PB6 5 &pcfg_pull_none>;
547		};
548
549		/omit-if-no-ref/
550		hdmim0_rx_scl: hdmim0-rx-scl {
551			rockchip,pins =
552				/* hdmim0_rx_scl */
553				<0 RK_PD2 11 &pcfg_pull_none>;
554		};
555
556		/omit-if-no-ref/
557		hdmim0_rx_sda: hdmim0-rx-sda {
558			rockchip,pins =
559				/* hdmim0_rx_sda */
560				<0 RK_PD1 11 &pcfg_pull_none>;
561		};
562
563		/omit-if-no-ref/
564		hdmim0_tx0_cec: hdmim0-tx0-cec {
565			rockchip,pins =
566				/* hdmim0_tx0_cec */
567				<4 RK_PC1 5 &pcfg_pull_none>;
568		};
569
570		/omit-if-no-ref/
571		hdmim0_tx0_hpd: hdmim0-tx0-hpd {
572			rockchip,pins =
573				/* hdmim0_tx0_hpd */
574				<1 RK_PA5 5 &pcfg_pull_none>;
575		};
576
577		/omit-if-no-ref/
578		hdmim0_tx0_scl: hdmim0-tx0-scl {
579			rockchip,pins =
580				/* hdmim0_tx0_scl */
581				<4 RK_PB7 5 &pcfg_pull_none>;
582		};
583
584		/omit-if-no-ref/
585		hdmim0_tx0_sda: hdmim0-tx0-sda {
586			rockchip,pins =
587				/* hdmim0_tx0_sda */
588				<4 RK_PC0 5 &pcfg_pull_none>;
589		};
590
591		/omit-if-no-ref/
592		hdmim0_tx1_hpd: hdmim0-tx1-hpd {
593			rockchip,pins =
594				/* hdmim0_tx1_hpd */
595				<1 RK_PA6 5 &pcfg_pull_none>;
596		};
597		/omit-if-no-ref/
598		hdmim1_rx_cec: hdmim1-rx-cec {
599			rockchip,pins =
600				/* hdmim1_rx_cec */
601				<3 RK_PD1 5 &pcfg_pull_none>;
602		};
603
604		/omit-if-no-ref/
605		hdmim1_rx_hpdin: hdmim1-rx-hpdin {
606			rockchip,pins =
607				/* hdmim1_rx_hpdin */
608				<3 RK_PD4 5 &pcfg_pull_none>;
609		};
610
611		/omit-if-no-ref/
612		hdmim1_rx_scl: hdmim1-rx-scl {
613			rockchip,pins =
614				/* hdmim1_rx_scl */
615				<3 RK_PD2 5 &pcfg_pull_none>;
616		};
617
618		/omit-if-no-ref/
619		hdmim1_rx_sda: hdmim1-rx-sda {
620			rockchip,pins =
621				/* hdmim1_rx_sda */
622				<3 RK_PD3 5 &pcfg_pull_none>;
623		};
624
625		/omit-if-no-ref/
626		hdmim1_tx0_cec: hdmim1-tx0-cec {
627			rockchip,pins =
628				/* hdmim1_tx0_cec */
629				<0 RK_PD1 13 &pcfg_pull_none>;
630		};
631
632		/omit-if-no-ref/
633		hdmim1_tx0_hpd: hdmim1-tx0-hpd {
634			rockchip,pins =
635				/* hdmim1_tx0_hpd */
636				<3 RK_PD4 3 &pcfg_pull_none>;
637		};
638
639		/omit-if-no-ref/
640		hdmim1_tx0_scl: hdmim1-tx0-scl {
641			rockchip,pins =
642				/* hdmim1_tx0_scl */
643				<0 RK_PD5 11 &pcfg_pull_none>;
644		};
645
646		/omit-if-no-ref/
647		hdmim1_tx0_sda: hdmim1-tx0-sda {
648			rockchip,pins =
649				/* hdmim1_tx0_sda */
650				<0 RK_PD4 11 &pcfg_pull_none>;
651		};
652
653		/omit-if-no-ref/
654		hdmim1_tx1_cec: hdmim1-tx1-cec {
655			rockchip,pins =
656				/* hdmim1_tx1_cec */
657				<0 RK_PD2 13 &pcfg_pull_none>;
658		};
659
660		/omit-if-no-ref/
661		hdmim1_tx1_hpd: hdmim1-tx1-hpd {
662			rockchip,pins =
663				/* hdmim1_tx1_hpd */
664				<3 RK_PB7 5 &pcfg_pull_none>;
665		};
666
667		/omit-if-no-ref/
668		hdmim1_tx1_scl: hdmim1-tx1-scl {
669			rockchip,pins =
670				/* hdmim1_tx1_scl */
671				<3 RK_PC6 5 &pcfg_pull_none>;
672		};
673
674		/omit-if-no-ref/
675		hdmim1_tx1_sda: hdmim1-tx1-sda {
676			rockchip,pins =
677				/* hdmim1_tx1_sda */
678				<3 RK_PC5 5 &pcfg_pull_none>;
679		};
680		/omit-if-no-ref/
681		hdmim2_rx_cec: hdmim2-rx-cec {
682			rockchip,pins =
683				/* hdmim2_rx_cec */
684				<1 RK_PB7 5 &pcfg_pull_none>;
685		};
686
687		/omit-if-no-ref/
688		hdmim2_rx_hpdin: hdmim2-rx-hpdin {
689			rockchip,pins =
690				/* hdmim2_rx_hpdin */
691				<1 RK_PB6 5 &pcfg_pull_none>;
692		};
693
694		/omit-if-no-ref/
695		hdmim2_rx_scl: hdmim2-rx-scl {
696			rockchip,pins =
697				/* hdmim2_rx_scl */
698				<1 RK_PD6 5 &pcfg_pull_none>;
699		};
700
701		/omit-if-no-ref/
702		hdmim2_rx_sda: hdmim2-rx-sda {
703			rockchip,pins =
704				/* hdmim2_rx_sda */
705				<1 RK_PD7 5 &pcfg_pull_none>;
706		};
707
708		/omit-if-no-ref/
709		hdmim2_tx0_scl: hdmim2-tx0-scl {
710			rockchip,pins =
711				/* hdmim2_tx0_scl */
712				<3 RK_PC7 5 &pcfg_pull_none>;
713		};
714
715		/omit-if-no-ref/
716		hdmim2_tx0_sda: hdmim2-tx0-sda {
717			rockchip,pins =
718				/* hdmim2_tx0_sda */
719				<3 RK_PD0 5 &pcfg_pull_none>;
720		};
721
722		/omit-if-no-ref/
723		hdmim2_tx1_cec: hdmim2-tx1-cec {
724			rockchip,pins =
725				/* hdmim2_tx1_cec */
726				<3 RK_PC4 5 &pcfg_pull_none>;
727		};
728
729		/omit-if-no-ref/
730		hdmim2_tx1_scl: hdmim2-tx1-scl {
731			rockchip,pins =
732				/* hdmim2_tx1_scl */
733				<1 RK_PA4 5 &pcfg_pull_none>;
734		};
735
736		/omit-if-no-ref/
737		hdmim2_tx1_sda: hdmim2-tx1-sda {
738			rockchip,pins =
739				/* hdmim2_tx1_sda */
740				<1 RK_PA3 5 &pcfg_pull_none>;
741		};
742
743		/omit-if-no-ref/
744		hdmi_debug0: hdmi-debug0 {
745			rockchip,pins =
746				/* hdmi_debug0 */
747				<1 RK_PA7 7 &pcfg_pull_none>;
748		};
749
750		/omit-if-no-ref/
751		hdmi_debug1: hdmi-debug1 {
752			rockchip,pins =
753				/* hdmi_debug1 */
754				<1 RK_PB0 7 &pcfg_pull_none>;
755		};
756
757		/omit-if-no-ref/
758		hdmi_debug2: hdmi-debug2 {
759			rockchip,pins =
760				/* hdmi_debug2 */
761				<1 RK_PB1 7 &pcfg_pull_none>;
762		};
763
764		/omit-if-no-ref/
765		hdmi_debug3: hdmi-debug3 {
766			rockchip,pins =
767				/* hdmi_debug3 */
768				<1 RK_PB2 7 &pcfg_pull_none>;
769		};
770
771		/omit-if-no-ref/
772		hdmi_debug4: hdmi-debug4 {
773			rockchip,pins =
774				/* hdmi_debug4 */
775				<1 RK_PB3 7 &pcfg_pull_none>;
776		};
777
778		/omit-if-no-ref/
779		hdmi_debug5: hdmi-debug5 {
780			rockchip,pins =
781				/* hdmi_debug5 */
782				<1 RK_PB4 7 &pcfg_pull_none>;
783		};
784
785		/omit-if-no-ref/
786		hdmi_debug6: hdmi-debug6 {
787			rockchip,pins =
788				/* hdmi_debug6 */
789				<1 RK_PA0 7 &pcfg_pull_none>;
790		};
791	};
792
793	i2c0 {
794		/omit-if-no-ref/
795		i2c0m0_xfer: i2c0m0-xfer {
796			rockchip,pins =
797				/* i2c0_scl_m0 */
798				<0 RK_PB3 2 &pcfg_pull_none_smt>,
799				/* i2c0_sda_m0 */
800				<0 RK_PA6 2 &pcfg_pull_none_smt>;
801		};
802
803		/omit-if-no-ref/
804		i2c0m2_xfer: i2c0m2-xfer {
805			rockchip,pins =
806				/* i2c0_scl_m2 */
807				<0 RK_PD1 3 &pcfg_pull_none_smt>,
808				/* i2c0_sda_m2 */
809				<0 RK_PD2 3 &pcfg_pull_none_smt>;
810		};
811	};
812
813	i2c1 {
814		/omit-if-no-ref/
815		i2c1m0_xfer: i2c1m0-xfer {
816			rockchip,pins =
817				/* i2c1_scl_m0 */
818				<0 RK_PB5 9 &pcfg_pull_none_smt>,
819				/* i2c1_sda_m0 */
820				<0 RK_PB6 9 &pcfg_pull_none_smt>;
821		};
822
823		/omit-if-no-ref/
824		i2c1m1_xfer: i2c1m1-xfer {
825			rockchip,pins =
826				/* i2c1_scl_m1 */
827				<0 RK_PB0 2 &pcfg_pull_none_smt>,
828				/* i2c1_sda_m1 */
829				<0 RK_PB1 2 &pcfg_pull_none_smt>;
830		};
831
832		/omit-if-no-ref/
833		i2c1m2_xfer: i2c1m2-xfer {
834			rockchip,pins =
835				/* i2c1_scl_m2 */
836				<0 RK_PD4 9 &pcfg_pull_none_smt>,
837				/* i2c1_sda_m2 */
838				<0 RK_PD5 9 &pcfg_pull_none_smt>;
839		};
840
841		/omit-if-no-ref/
842		i2c1m3_xfer: i2c1m3-xfer {
843			rockchip,pins =
844				/* i2c1_scl_m3 */
845				<2 RK_PD4 9 &pcfg_pull_none_smt>,
846				/* i2c1_sda_m3 */
847				<2 RK_PD5 9 &pcfg_pull_none_smt>;
848		};
849
850		/omit-if-no-ref/
851		i2c1m4_xfer: i2c1m4-xfer {
852			rockchip,pins =
853				/* i2c1_scl_m4 */
854				<1 RK_PD2 9 &pcfg_pull_none_smt>,
855				/* i2c1_sda_m4 */
856				<1 RK_PD3 9 &pcfg_pull_none_smt>;
857		};
858	};
859
860	i2c2 {
861		/omit-if-no-ref/
862		i2c2m0_xfer: i2c2m0-xfer {
863			rockchip,pins =
864				/* i2c2_scl_m0 */
865				<0 RK_PB7 9 &pcfg_pull_none_smt>,
866				/* i2c2_sda_m0 */
867				<0 RK_PC0 9 &pcfg_pull_none_smt>;
868		};
869
870		/omit-if-no-ref/
871		i2c2m2_xfer: i2c2m2-xfer {
872			rockchip,pins =
873				/* i2c2_scl_m2 */
874				<2 RK_PA3 9 &pcfg_pull_none_smt>,
875				/* i2c2_sda_m2 */
876				<2 RK_PA2 9 &pcfg_pull_none_smt>;
877		};
878
879		/omit-if-no-ref/
880		i2c2m3_xfer: i2c2m3-xfer {
881			rockchip,pins =
882				/* i2c2_scl_m3 */
883				<1 RK_PC5 9 &pcfg_pull_none_smt>,
884				/* i2c2_sda_m3 */
885				<1 RK_PC4 9 &pcfg_pull_none_smt>;
886		};
887
888		/omit-if-no-ref/
889		i2c2m4_xfer: i2c2m4-xfer {
890			rockchip,pins =
891				/* i2c2_scl_m4 */
892				<1 RK_PA1 9 &pcfg_pull_none_smt>,
893				/* i2c2_sda_m4 */
894				<1 RK_PA0 9 &pcfg_pull_none_smt>;
895		};
896	};
897
898	i2c3 {
899		/omit-if-no-ref/
900		i2c3m0_xfer: i2c3m0-xfer {
901			rockchip,pins =
902				/* i2c3_scl_m0 */
903				<1 RK_PC1 9 &pcfg_pull_none_smt>,
904				/* i2c3_sda_m0 */
905				<1 RK_PC0 9 &pcfg_pull_none_smt>;
906		};
907
908		/omit-if-no-ref/
909		i2c3m1_xfer: i2c3m1-xfer {
910			rockchip,pins =
911				/* i2c3_scl_m1 */
912				<3 RK_PB7 9 &pcfg_pull_none_smt>,
913				/* i2c3_sda_m1 */
914				<3 RK_PC0 9 &pcfg_pull_none_smt>;
915		};
916
917		/omit-if-no-ref/
918		i2c3m2_xfer: i2c3m2-xfer {
919			rockchip,pins =
920				/* i2c3_scl_m2 */
921				<4 RK_PA4 9 &pcfg_pull_none_smt>,
922				/* i2c3_sda_m2 */
923				<4 RK_PA5 9 &pcfg_pull_none_smt>;
924		};
925
926		/omit-if-no-ref/
927		i2c3m4_xfer: i2c3m4-xfer {
928			rockchip,pins =
929				/* i2c3_scl_m4 */
930				<4 RK_PD0 9 &pcfg_pull_none_smt>,
931				/* i2c3_sda_m4 */
932				<4 RK_PD1 9 &pcfg_pull_none_smt>;
933		};
934	};
935
936	i2c4 {
937		/omit-if-no-ref/
938		i2c4m0_xfer: i2c4m0-xfer {
939			rockchip,pins =
940				/* i2c4_scl_m0 */
941				<3 RK_PA6 9 &pcfg_pull_none_smt>,
942				/* i2c4_sda_m0 */
943				<3 RK_PA5 9 &pcfg_pull_none_smt>;
944		};
945
946		/omit-if-no-ref/
947		i2c4m2_xfer: i2c4m2-xfer {
948			rockchip,pins =
949				/* i2c4_scl_m2 */
950				<0 RK_PC5 9 &pcfg_pull_none_smt>,
951				/* i2c4_sda_m2 */
952				<0 RK_PC4 9 &pcfg_pull_none_smt>;
953		};
954
955		/omit-if-no-ref/
956		i2c4m3_xfer: i2c4m3-xfer {
957			rockchip,pins =
958				/* i2c4_scl_m3 */
959				<1 RK_PA3 9 &pcfg_pull_none_smt>,
960				/* i2c4_sda_m3 */
961				<1 RK_PA2 9 &pcfg_pull_none_smt>;
962		};
963
964		/omit-if-no-ref/
965		i2c4m4_xfer: i2c4m4-xfer {
966			rockchip,pins =
967				/* i2c4_scl_m4 */
968				<1 RK_PC7 9 &pcfg_pull_none_smt>,
969				/* i2c4_sda_m4 */
970				<1 RK_PC6 9 &pcfg_pull_none_smt>;
971		};
972	};
973
974	i2c5 {
975		/omit-if-no-ref/
976		i2c5m0_xfer: i2c5m0-xfer {
977			rockchip,pins =
978				/* i2c5_scl_m0 */
979				<3 RK_PC7 9 &pcfg_pull_none_smt>,
980				/* i2c5_sda_m0 */
981				<3 RK_PD0 9 &pcfg_pull_none_smt>;
982		};
983
984		/omit-if-no-ref/
985		i2c5m1_xfer: i2c5m1-xfer {
986			rockchip,pins =
987				/* i2c5_scl_m1 */
988				<4 RK_PB6 9 &pcfg_pull_none_smt>,
989				/* i2c5_sda_m1 */
990				<4 RK_PB7 9 &pcfg_pull_none_smt>;
991		};
992
993		/omit-if-no-ref/
994		i2c5m2_xfer: i2c5m2-xfer {
995			rockchip,pins =
996				/* i2c5_scl_m2 */
997				<4 RK_PA6 9 &pcfg_pull_none_smt>,
998				/* i2c5_sda_m2 */
999				<4 RK_PA7 9 &pcfg_pull_none_smt>;
1000		};
1001
1002		/omit-if-no-ref/
1003		i2c5m3_xfer: i2c5m3-xfer {
1004			rockchip,pins =
1005				/* i2c5_scl_m3 */
1006				<1 RK_PB6 9 &pcfg_pull_none_smt>,
1007				/* i2c5_sda_m3 */
1008				<1 RK_PB7 9 &pcfg_pull_none_smt>;
1009		};
1010	};
1011
1012	i2c6 {
1013		/omit-if-no-ref/
1014		i2c6m0_xfer: i2c6m0-xfer {
1015			rockchip,pins =
1016				/* i2c6_scl_m0 */
1017				<0 RK_PD0 9 &pcfg_pull_none_smt>,
1018				/* i2c6_sda_m0 */
1019				<0 RK_PC7 9 &pcfg_pull_none_smt>;
1020		};
1021
1022		/omit-if-no-ref/
1023		i2c6m1_xfer: i2c6m1-xfer {
1024			rockchip,pins =
1025				/* i2c6_scl_m1 */
1026				<1 RK_PC3 9 &pcfg_pull_none_smt>,
1027				/* i2c6_sda_m1 */
1028				<1 RK_PC2 9 &pcfg_pull_none_smt>;
1029		};
1030
1031		/omit-if-no-ref/
1032		i2c6m3_xfer: i2c6m3-xfer {
1033			rockchip,pins =
1034				/* i2c6_scl_m3 */
1035				<4 RK_PB1 9 &pcfg_pull_none_smt>,
1036				/* i2c6_sda_m3 */
1037				<4 RK_PB0 9 &pcfg_pull_none_smt>;
1038		};
1039
1040		/omit-if-no-ref/
1041		i2c6m4_xfer: i2c6m4-xfer {
1042			rockchip,pins =
1043				/* i2c6_scl_m4 */
1044				<3 RK_PA1 9 &pcfg_pull_none_smt>,
1045				/* i2c6_sda_m4 */
1046				<3 RK_PA0 9 &pcfg_pull_none_smt>;
1047		};
1048	};
1049
1050	i2c7 {
1051		/omit-if-no-ref/
1052		i2c7m0_xfer: i2c7m0-xfer {
1053			rockchip,pins =
1054				/* i2c7_scl_m0 */
1055				<1 RK_PD0 9 &pcfg_pull_none_smt>,
1056				/* i2c7_sda_m0 */
1057				<1 RK_PD1 9 &pcfg_pull_none_smt>;
1058		};
1059
1060		/omit-if-no-ref/
1061		i2c7m2_xfer: i2c7m2-xfer {
1062			rockchip,pins =
1063				/* i2c7_scl_m2 */
1064				<3 RK_PD2 9 &pcfg_pull_none_smt>,
1065				/* i2c7_sda_m2 */
1066				<3 RK_PD3 9 &pcfg_pull_none_smt>;
1067		};
1068
1069		/omit-if-no-ref/
1070		i2c7m3_xfer: i2c7m3-xfer {
1071			rockchip,pins =
1072				/* i2c7_scl_m3 */
1073				<4 RK_PB2 9 &pcfg_pull_none_smt>,
1074				/* i2c7_sda_m3 */
1075				<4 RK_PB3 9 &pcfg_pull_none_smt>;
1076		};
1077	};
1078
1079	i2c8 {
1080		/omit-if-no-ref/
1081		i2c8m0_xfer: i2c8m0-xfer {
1082			rockchip,pins =
1083				/* i2c8_scl_m0 */
1084				<4 RK_PD2 9 &pcfg_pull_none_smt>,
1085				/* i2c8_sda_m0 */
1086				<4 RK_PD3 9 &pcfg_pull_none_smt>;
1087		};
1088
1089		/omit-if-no-ref/
1090		i2c8m2_xfer: i2c8m2-xfer {
1091			rockchip,pins =
1092				/* i2c8_scl_m2 */
1093				<1 RK_PD6 9 &pcfg_pull_none_smt>,
1094				/* i2c8_sda_m2 */
1095				<1 RK_PD7 9 &pcfg_pull_none_smt>;
1096		};
1097
1098		/omit-if-no-ref/
1099		i2c8m3_xfer: i2c8m3-xfer {
1100			rockchip,pins =
1101				/* i2c8_scl_m3 */
1102				<4 RK_PC0 9 &pcfg_pull_none_smt>,
1103				/* i2c8_sda_m3 */
1104				<4 RK_PC1 9 &pcfg_pull_none_smt>;
1105		};
1106
1107		/omit-if-no-ref/
1108		i2c8m4_xfer: i2c8m4-xfer {
1109			rockchip,pins =
1110				/* i2c8_scl_m4 */
1111				<3 RK_PC2 9 &pcfg_pull_none_smt>,
1112				/* i2c8_sda_m4 */
1113				<3 RK_PC3 9 &pcfg_pull_none_smt>;
1114		};
1115	};
1116
1117	i2s0 {
1118		/omit-if-no-ref/
1119		i2s0_lrck: i2s0-lrck {
1120			rockchip,pins =
1121				/* i2s0_lrck */
1122				<1 RK_PC5 1 &pcfg_pull_none>;
1123		};
1124
1125		/omit-if-no-ref/
1126		i2s0_mclk: i2s0-mclk {
1127			rockchip,pins =
1128				/* i2s0_mclk */
1129				<1 RK_PC2 1 &pcfg_pull_none>;
1130		};
1131
1132		/omit-if-no-ref/
1133		i2s0_sclk: i2s0-sclk {
1134			rockchip,pins =
1135				/* i2s0_sclk */
1136				<1 RK_PC3 1 &pcfg_pull_none>;
1137		};
1138
1139		/omit-if-no-ref/
1140		i2s0_sdi0: i2s0-sdi0 {
1141			rockchip,pins =
1142				/* i2s0_sdi0 */
1143				<1 RK_PD4 2 &pcfg_pull_none>;
1144		};
1145
1146		/omit-if-no-ref/
1147		i2s0_sdi1: i2s0-sdi1 {
1148			rockchip,pins =
1149				/* i2s0_sdi1 */
1150				<1 RK_PD3 2 &pcfg_pull_none>;
1151		};
1152
1153		/omit-if-no-ref/
1154		i2s0_sdi2: i2s0-sdi2 {
1155			rockchip,pins =
1156				/* i2s0_sdi2 */
1157				<1 RK_PD2 2 &pcfg_pull_none>;
1158		};
1159
1160		/omit-if-no-ref/
1161		i2s0_sdi3: i2s0-sdi3 {
1162			rockchip,pins =
1163				/* i2s0_sdi3 */
1164				<1 RK_PD1 2 &pcfg_pull_none>;
1165		};
1166
1167		/omit-if-no-ref/
1168		i2s0_sdo0: i2s0-sdo0 {
1169			rockchip,pins =
1170				/* i2s0_sdo0 */
1171				<1 RK_PC7 1 &pcfg_pull_none>;
1172		};
1173
1174		/omit-if-no-ref/
1175		i2s0_sdo1: i2s0-sdo1 {
1176			rockchip,pins =
1177				/* i2s0_sdo1 */
1178				<1 RK_PD0 1 &pcfg_pull_none>;
1179		};
1180
1181		/omit-if-no-ref/
1182		i2s0_sdo2: i2s0-sdo2 {
1183			rockchip,pins =
1184				/* i2s0_sdo2 */
1185				<1 RK_PD1 1 &pcfg_pull_none>;
1186		};
1187
1188		/omit-if-no-ref/
1189		i2s0_sdo3: i2s0-sdo3 {
1190			rockchip,pins =
1191				/* i2s0_sdo3 */
1192				<1 RK_PD2 1 &pcfg_pull_none>;
1193		};
1194	};
1195
1196	i2s1 {
1197		/omit-if-no-ref/
1198		i2s1m0_lrck: i2s1m0-lrck {
1199			rockchip,pins =
1200				/* i2s1m0_lrck */
1201				<4 RK_PA2 3 &pcfg_pull_none>;
1202		};
1203
1204		/omit-if-no-ref/
1205		i2s1m0_mclk: i2s1m0-mclk {
1206			rockchip,pins =
1207				/* i2s1m0_mclk */
1208				<4 RK_PA0 3 &pcfg_pull_none>;
1209		};
1210
1211		/omit-if-no-ref/
1212		i2s1m0_sclk: i2s1m0-sclk {
1213			rockchip,pins =
1214				/* i2s1m0_sclk */
1215				<4 RK_PA1 3 &pcfg_pull_none>;
1216		};
1217
1218		/omit-if-no-ref/
1219		i2s1m0_sdi0: i2s1m0-sdi0 {
1220			rockchip,pins =
1221				/* i2s1m0_sdi0 */
1222				<4 RK_PA5 3 &pcfg_pull_none>;
1223		};
1224
1225		/omit-if-no-ref/
1226		i2s1m0_sdi1: i2s1m0-sdi1 {
1227			rockchip,pins =
1228				/* i2s1m0_sdi1 */
1229				<4 RK_PA6 3 &pcfg_pull_none>;
1230		};
1231
1232		/omit-if-no-ref/
1233		i2s1m0_sdi2: i2s1m0-sdi2 {
1234			rockchip,pins =
1235				/* i2s1m0_sdi2 */
1236				<4 RK_PA7 3 &pcfg_pull_none>;
1237		};
1238
1239		/omit-if-no-ref/
1240		i2s1m0_sdi3: i2s1m0-sdi3 {
1241			rockchip,pins =
1242				/* i2s1m0_sdi3 */
1243				<4 RK_PB0 3 &pcfg_pull_none>;
1244		};
1245
1246		/omit-if-no-ref/
1247		i2s1m0_sdo0: i2s1m0-sdo0 {
1248			rockchip,pins =
1249				/* i2s1m0_sdo0 */
1250				<4 RK_PB1 3 &pcfg_pull_none>;
1251		};
1252
1253		/omit-if-no-ref/
1254		i2s1m0_sdo1: i2s1m0-sdo1 {
1255			rockchip,pins =
1256				/* i2s1m0_sdo1 */
1257				<4 RK_PB2 3 &pcfg_pull_none>;
1258		};
1259
1260		/omit-if-no-ref/
1261		i2s1m0_sdo2: i2s1m0-sdo2 {
1262			rockchip,pins =
1263				/* i2s1m0_sdo2 */
1264				<4 RK_PB3 3 &pcfg_pull_none>;
1265		};
1266
1267		/omit-if-no-ref/
1268		i2s1m0_sdo3: i2s1m0-sdo3 {
1269			rockchip,pins =
1270				/* i2s1m0_sdo3 */
1271				<4 RK_PB4 3 &pcfg_pull_none>;
1272		};
1273		/omit-if-no-ref/
1274		i2s1m1_lrck: i2s1m1-lrck {
1275			rockchip,pins =
1276				/* i2s1m1_lrck */
1277				<0 RK_PB7 1 &pcfg_pull_none>;
1278		};
1279
1280		/omit-if-no-ref/
1281		i2s1m1_mclk: i2s1m1-mclk {
1282			rockchip,pins =
1283				/* i2s1m1_mclk */
1284				<0 RK_PB5 1 &pcfg_pull_none>;
1285		};
1286
1287		/omit-if-no-ref/
1288		i2s1m1_sclk: i2s1m1-sclk {
1289			rockchip,pins =
1290				/* i2s1m1_sclk */
1291				<0 RK_PB6 1 &pcfg_pull_none>;
1292		};
1293
1294		/omit-if-no-ref/
1295		i2s1m1_sdi0: i2s1m1-sdi0 {
1296			rockchip,pins =
1297				/* i2s1m1_sdi0 */
1298				<0 RK_PC5 1 &pcfg_pull_none>;
1299		};
1300
1301		/omit-if-no-ref/
1302		i2s1m1_sdi1: i2s1m1-sdi1 {
1303			rockchip,pins =
1304				/* i2s1m1_sdi1 */
1305				<0 RK_PC6 1 &pcfg_pull_none>;
1306		};
1307
1308		/omit-if-no-ref/
1309		i2s1m1_sdi2: i2s1m1-sdi2 {
1310			rockchip,pins =
1311				/* i2s1m1_sdi2 */
1312				<0 RK_PC7 1 &pcfg_pull_none>;
1313		};
1314
1315		/omit-if-no-ref/
1316		i2s1m1_sdi3: i2s1m1-sdi3 {
1317			rockchip,pins =
1318				/* i2s1m1_sdi3 */
1319				<0 RK_PD0 1 &pcfg_pull_none>;
1320		};
1321
1322		/omit-if-no-ref/
1323		i2s1m1_sdo0: i2s1m1-sdo0 {
1324			rockchip,pins =
1325				/* i2s1m1_sdo0 */
1326				<0 RK_PD1 1 &pcfg_pull_none>;
1327		};
1328
1329		/omit-if-no-ref/
1330		i2s1m1_sdo1: i2s1m1-sdo1 {
1331			rockchip,pins =
1332				/* i2s1m1_sdo1 */
1333				<0 RK_PD2 1 &pcfg_pull_none>;
1334		};
1335
1336		/omit-if-no-ref/
1337		i2s1m1_sdo2: i2s1m1-sdo2 {
1338			rockchip,pins =
1339				/* i2s1m1_sdo2 */
1340				<0 RK_PD4 1 &pcfg_pull_none>;
1341		};
1342
1343		/omit-if-no-ref/
1344		i2s1m1_sdo3: i2s1m1-sdo3 {
1345			rockchip,pins =
1346				/* i2s1m1_sdo3 */
1347				<0 RK_PD5 1 &pcfg_pull_none>;
1348		};
1349	};
1350
1351	i2s2 {
1352		/omit-if-no-ref/
1353		i2s2m1_lrck: i2s2m1-lrck {
1354			rockchip,pins =
1355				/* i2s2m1_lrck */
1356				<3 RK_PB6 3 &pcfg_pull_none>;
1357		};
1358
1359		/omit-if-no-ref/
1360		i2s2m1_mclk: i2s2m1-mclk {
1361			rockchip,pins =
1362				/* i2s2m1_mclk */
1363				<3 RK_PB4 3 &pcfg_pull_none>;
1364		};
1365
1366		/omit-if-no-ref/
1367		i2s2m1_sclk: i2s2m1-sclk {
1368			rockchip,pins =
1369				/* i2s2m1_sclk */
1370				<3 RK_PB5 3 &pcfg_pull_none>;
1371		};
1372
1373		/omit-if-no-ref/
1374		i2s2m1_sdi: i2s2m1-sdi {
1375			rockchip,pins =
1376				/* i2s2m1_sdi */
1377				<3 RK_PB2 3 &pcfg_pull_none>;
1378		};
1379
1380		/omit-if-no-ref/
1381		i2s2m1_sdo: i2s2m1-sdo {
1382			rockchip,pins =
1383				/* i2s2m1_sdo */
1384				<3 RK_PB3 3 &pcfg_pull_none>;
1385		};
1386	};
1387
1388	i2s3 {
1389		/omit-if-no-ref/
1390		i2s3_lrck: i2s3-lrck {
1391			rockchip,pins =
1392				/* i2s3_lrck */
1393				<3 RK_PA2 3 &pcfg_pull_none>;
1394		};
1395
1396		/omit-if-no-ref/
1397		i2s3_mclk: i2s3-mclk {
1398			rockchip,pins =
1399				/* i2s3_mclk */
1400				<3 RK_PA0 3 &pcfg_pull_none>;
1401		};
1402
1403		/omit-if-no-ref/
1404		i2s3_sclk: i2s3-sclk {
1405			rockchip,pins =
1406				/* i2s3_sclk */
1407				<3 RK_PA1 3 &pcfg_pull_none>;
1408		};
1409
1410		/omit-if-no-ref/
1411		i2s3_sdi: i2s3-sdi {
1412			rockchip,pins =
1413				/* i2s3_sdi */
1414				<3 RK_PA4 3 &pcfg_pull_none>;
1415		};
1416
1417		/omit-if-no-ref/
1418		i2s3_sdo: i2s3-sdo {
1419			rockchip,pins =
1420				/* i2s3_sdo */
1421				<3 RK_PA3 3 &pcfg_pull_none>;
1422		};
1423	};
1424
1425	jtag {
1426		/omit-if-no-ref/
1427		jtagm0_pins: jtagm0-pins {
1428			rockchip,pins =
1429				/* jtag_tck_m0 */
1430				<4 RK_PD2 5 &pcfg_pull_none>,
1431				/* jtag_tms_m0 */
1432				<4 RK_PD3 5 &pcfg_pull_none>;
1433		};
1434
1435		/omit-if-no-ref/
1436		jtagm1_pins: jtagm1-pins {
1437			rockchip,pins =
1438				/* jtag_tck_m1 */
1439				<4 RK_PD0 5 &pcfg_pull_none>,
1440				/* jtag_tms_m1 */
1441				<4 RK_PD1 5 &pcfg_pull_none>;
1442		};
1443
1444		/omit-if-no-ref/
1445		jtagm2_pins: jtagm2-pins {
1446			rockchip,pins =
1447				/* jtag_tck_m2 */
1448				<0 RK_PB5 2 &pcfg_pull_none>,
1449				/* jtag_tms_m2 */
1450				<0 RK_PB6 2 &pcfg_pull_none>;
1451		};
1452	};
1453
1454	litcpu {
1455		/omit-if-no-ref/
1456		litcpu_pins: litcpu-pins {
1457			rockchip,pins =
1458				/* litcpu_avs */
1459				<0 RK_PD3 1 &pcfg_pull_none>;
1460		};
1461	};
1462
1463	mcu {
1464		/omit-if-no-ref/
1465		mcum0_pins: mcum0-pins {
1466			rockchip,pins =
1467				/* mcu_jtag_tck_m0 */
1468				<4 RK_PD4 5 &pcfg_pull_none>,
1469				/* mcu_jtag_tms_m0 */
1470				<4 RK_PD5 5 &pcfg_pull_none>;
1471		};
1472
1473		/omit-if-no-ref/
1474		mcum1_pins: mcum1-pins {
1475			rockchip,pins =
1476				/* mcu_jtag_tck_m1 */
1477				<3 RK_PD4 6 &pcfg_pull_none>,
1478				/* mcu_jtag_tms_m1 */
1479				<3 RK_PD5 6 &pcfg_pull_none>;
1480		};
1481	};
1482
1483	mipi {
1484		/omit-if-no-ref/
1485		mipim0_camera0_clk: mipim0-camera0-clk {
1486			rockchip,pins =
1487				/* mipim0_camera0_clk */
1488				<4 RK_PB1 1 &pcfg_pull_none>;
1489		};
1490
1491		/omit-if-no-ref/
1492		mipim0_camera1_clk: mipim0-camera1-clk {
1493			rockchip,pins =
1494				/* mipim0_camera1_clk */
1495				<1 RK_PB6 2 &pcfg_pull_none>;
1496		};
1497
1498		/omit-if-no-ref/
1499		mipim0_camera2_clk: mipim0-camera2-clk {
1500			rockchip,pins =
1501				/* mipim0_camera2_clk */
1502				<1 RK_PB7 2 &pcfg_pull_none>;
1503		};
1504
1505		/omit-if-no-ref/
1506		mipim0_camera3_clk: mipim0-camera3-clk {
1507			rockchip,pins =
1508				/* mipim0_camera3_clk */
1509				<1 RK_PD6 2 &pcfg_pull_none>;
1510		};
1511
1512		/omit-if-no-ref/
1513		mipim0_camera4_clk: mipim0-camera4-clk {
1514			rockchip,pins =
1515				/* mipim0_camera4_clk */
1516				<1 RK_PD7 2 &pcfg_pull_none>;
1517		};
1518
1519		/omit-if-no-ref/
1520		mipim1_camera0_clk: mipim1-camera0-clk {
1521			rockchip,pins =
1522				/* mipim1_camera0_clk */
1523				<3 RK_PA5 4 &pcfg_pull_none>;
1524		};
1525
1526		/omit-if-no-ref/
1527		mipim1_camera1_clk: mipim1-camera1-clk {
1528			rockchip,pins =
1529				/* mipim1_camera1_clk */
1530				<3 RK_PA6 4 &pcfg_pull_none>;
1531		};
1532
1533		/omit-if-no-ref/
1534		mipim1_camera2_clk: mipim1-camera2-clk {
1535			rockchip,pins =
1536				/* mipim1_camera2_clk */
1537				<3 RK_PA7 4 &pcfg_pull_none>;
1538		};
1539
1540		/omit-if-no-ref/
1541		mipim1_camera3_clk: mipim1-camera3-clk {
1542			rockchip,pins =
1543				/* mipim1_camera3_clk */
1544				<3 RK_PB0 4 &pcfg_pull_none>;
1545		};
1546
1547		/omit-if-no-ref/
1548		mipim1_camera4_clk: mipim1-camera4-clk {
1549			rockchip,pins =
1550				/* mipim1_camera4_clk */
1551				<3 RK_PB1 4 &pcfg_pull_none>;
1552		};
1553
1554		/omit-if-no-ref/
1555		mipi_te0: mipi-te0 {
1556			rockchip,pins =
1557				/* mipi_te0 */
1558				<3 RK_PC2 2 &pcfg_pull_none>;
1559		};
1560
1561		/omit-if-no-ref/
1562		mipi_te1: mipi-te1 {
1563			rockchip,pins =
1564				/* mipi_te1 */
1565				<3 RK_PC3 2 &pcfg_pull_none>;
1566		};
1567	};
1568
1569	npu {
1570		/omit-if-no-ref/
1571		npu_pins: npu-pins {
1572			rockchip,pins =
1573				/* npu_avs */
1574				<0 RK_PC6 2 &pcfg_pull_none>;
1575		};
1576	};
1577
1578	pcie20x1 {
1579		/omit-if-no-ref/
1580		pcie20x1m0_pins: pcie20x1m0-pins {
1581			rockchip,pins =
1582				/* pcie20x1_2_clkreqn_m0 */
1583				<3 RK_PC7 4 &pcfg_pull_none>,
1584				/* pcie20x1_2_perstn_m0 */
1585				<3 RK_PD1 4 &pcfg_pull_none>,
1586				/* pcie20x1_2_waken_m0 */
1587				<3 RK_PD0 4 &pcfg_pull_none>;
1588		};
1589
1590		/omit-if-no-ref/
1591		pcie20x1m1_pins: pcie20x1m1-pins {
1592			rockchip,pins =
1593				/* pcie20x1_2_clkreqn_m1 */
1594				<4 RK_PB7 4 &pcfg_pull_none>,
1595				/* pcie20x1_2_perstn_m1 */
1596				<4 RK_PC1 4 &pcfg_pull_none>,
1597				/* pcie20x1_2_waken_m1 */
1598				<4 RK_PC0 4 &pcfg_pull_none>;
1599		};
1600
1601		/omit-if-no-ref/
1602		pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
1603			rockchip,pins =
1604				/* pcie20x1_2_button_rstn */
1605				<4 RK_PB3 4 &pcfg_pull_none>;
1606		};
1607	};
1608
1609	pcie30phy {
1610		/omit-if-no-ref/
1611		pcie30phy_pins: pcie30phy-pins {
1612			rockchip,pins =
1613				/* pcie30phy_dtb0 */
1614				<1 RK_PC4 4 &pcfg_pull_none>,
1615				/* pcie30phy_dtb1 */
1616				<1 RK_PD1 4 &pcfg_pull_none>;
1617		};
1618	};
1619
1620	pcie30x1 {
1621		/omit-if-no-ref/
1622		pcie30x1m0_pins: pcie30x1m0-pins {
1623			rockchip,pins =
1624				/* pcie30x1_0_clkreqn_m0 */
1625				<0 RK_PC0 12 &pcfg_pull_none>,
1626				/* pcie30x1_0_perstn_m0 */
1627				<0 RK_PC5 12 &pcfg_pull_none>,
1628				/* pcie30x1_0_waken_m0 */
1629				<0 RK_PC4 12 &pcfg_pull_none>,
1630				/* pcie30x1_1_clkreqn_m0 */
1631				<0 RK_PB5 12 &pcfg_pull_none>,
1632				/* pcie30x1_1_perstn_m0 */
1633				<0 RK_PB7 12 &pcfg_pull_none>,
1634				/* pcie30x1_1_waken_m0 */
1635				<0 RK_PB6 12 &pcfg_pull_none>;
1636		};
1637
1638		/omit-if-no-ref/
1639		pcie30x1m1_pins: pcie30x1m1-pins {
1640			rockchip,pins =
1641				/* pcie30x1_0_clkreqn_m1 */
1642				<4 RK_PA3 4 &pcfg_pull_none>,
1643				/* pcie30x1_0_perstn_m1 */
1644				<4 RK_PA5 4 &pcfg_pull_none>,
1645				/* pcie30x1_0_waken_m1 */
1646				<4 RK_PA4 4 &pcfg_pull_none>,
1647				/* pcie30x1_1_clkreqn_m1 */
1648				<4 RK_PA0 4 &pcfg_pull_none>,
1649				/* pcie30x1_1_perstn_m1 */
1650				<4 RK_PA2 4 &pcfg_pull_none>,
1651				/* pcie30x1_1_waken_m1 */
1652				<4 RK_PA1 4 &pcfg_pull_none>;
1653		};
1654
1655		/omit-if-no-ref/
1656		pcie30x1m2_pins: pcie30x1m2-pins {
1657			rockchip,pins =
1658				/* pcie30x1_0_clkreqn_m2 */
1659				<1 RK_PB5 4 &pcfg_pull_none>,
1660				/* pcie30x1_0_perstn_m2 */
1661				<1 RK_PB4 4 &pcfg_pull_none>,
1662				/* pcie30x1_0_waken_m2 */
1663				<1 RK_PB3 4 &pcfg_pull_none>,
1664				/* pcie30x1_1_clkreqn_m2 */
1665				<1 RK_PA0 4 &pcfg_pull_none>,
1666				/* pcie30x1_1_perstn_m2 */
1667				<1 RK_PA7 4 &pcfg_pull_none>,
1668				/* pcie30x1_1_waken_m2 */
1669				<1 RK_PA1 4 &pcfg_pull_none>;
1670		};
1671
1672		/omit-if-no-ref/
1673		pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
1674			rockchip,pins =
1675				/* pcie30x1_0_button_rstn */
1676				<4 RK_PB1 4 &pcfg_pull_none>;
1677		};
1678
1679		/omit-if-no-ref/
1680		pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
1681			rockchip,pins =
1682				/* pcie30x1_1_button_rstn */
1683				<4 RK_PB2 4 &pcfg_pull_none>;
1684		};
1685	};
1686
1687	pcie30x2 {
1688		/omit-if-no-ref/
1689		pcie30x2m0_pins: pcie30x2m0-pins {
1690			rockchip,pins =
1691				/* pcie30x2_clkreqn_m0 */
1692				<0 RK_PD1 12 &pcfg_pull_none>,
1693				/* pcie30x2_perstn_m0 */
1694				<0 RK_PD4 12 &pcfg_pull_none>,
1695				/* pcie30x2_waken_m0 */
1696				<0 RK_PD2 12 &pcfg_pull_none>;
1697		};
1698
1699		/omit-if-no-ref/
1700		pcie30x2m1_pins: pcie30x2m1-pins {
1701			rockchip,pins =
1702				/* pcie30x2_clkreqn_m1 */
1703				<4 RK_PA6 4 &pcfg_pull_none>,
1704				/* pcie30x2_perstn_m1 */
1705				<4 RK_PB0 4 &pcfg_pull_none>,
1706				/* pcie30x2_waken_m1 */
1707				<4 RK_PA7 4 &pcfg_pull_none>;
1708		};
1709
1710		/omit-if-no-ref/
1711		pcie30x2m2_pins: pcie30x2m2-pins {
1712			rockchip,pins =
1713				/* pcie30x2_clkreqn_m2 */
1714				<3 RK_PD2 4 &pcfg_pull_none>,
1715				/* pcie30x2_perstn_m2 */
1716				<3 RK_PD4 4 &pcfg_pull_none>,
1717				/* pcie30x2_waken_m2 */
1718				<3 RK_PD3 4 &pcfg_pull_none>;
1719		};
1720
1721		/omit-if-no-ref/
1722		pcie30x2m3_pins: pcie30x2m3-pins {
1723			rockchip,pins =
1724				/* pcie30x2_clkreqn_m3 */
1725				<1 RK_PD7 4 &pcfg_pull_none>,
1726				/* pcie30x2_perstn_m3 */
1727				<1 RK_PB7 4 &pcfg_pull_none>,
1728				/* pcie30x2_waken_m3 */
1729				<1 RK_PB6 4 &pcfg_pull_none>;
1730		};
1731
1732		/omit-if-no-ref/
1733		pcie30x2_button_rstn: pcie30x2-button-rstn {
1734			rockchip,pins =
1735				/* pcie30x2_button_rstn */
1736				<3 RK_PC1 4 &pcfg_pull_none>;
1737		};
1738	};
1739
1740	pcie30x4 {
1741		/omit-if-no-ref/
1742		pcie30x4m0_pins: pcie30x4m0-pins {
1743			rockchip,pins =
1744				/* pcie30x4_clkreqn_m0 */
1745				<0 RK_PC6 12 &pcfg_pull_none>,
1746				/* pcie30x4_perstn_m0 */
1747				<0 RK_PD0 12 &pcfg_pull_none>,
1748				/* pcie30x4_waken_m0 */
1749				<0 RK_PC7 12 &pcfg_pull_none>;
1750		};
1751
1752		/omit-if-no-ref/
1753		pcie30x4m1_pins: pcie30x4m1-pins {
1754			rockchip,pins =
1755				/* pcie30x4_clkreqn_m1 */
1756				<4 RK_PB4 4 &pcfg_pull_none>,
1757				/* pcie30x4_perstn_m1 */
1758				<4 RK_PB6 4 &pcfg_pull_none>,
1759				/* pcie30x4_waken_m1 */
1760				<4 RK_PB5 4 &pcfg_pull_none>;
1761		};
1762
1763		/omit-if-no-ref/
1764		pcie30x4m2_pins: pcie30x4m2-pins {
1765			rockchip,pins =
1766				/* pcie30x4_clkreqn_m2 */
1767				<3 RK_PC4 4 &pcfg_pull_none>,
1768				/* pcie30x4_perstn_m2 */
1769				<3 RK_PC6 4 &pcfg_pull_none>,
1770				/* pcie30x4_waken_m2 */
1771				<3 RK_PC5 4 &pcfg_pull_none>;
1772		};
1773
1774		/omit-if-no-ref/
1775		pcie30x4m3_pins: pcie30x4m3-pins {
1776			rockchip,pins =
1777				/* pcie30x4_clkreqn_m3 */
1778				<1 RK_PB0 4 &pcfg_pull_none>,
1779				/* pcie30x4_perstn_m3 */
1780				<1 RK_PB2 4 &pcfg_pull_none>,
1781				/* pcie30x4_waken_m3 */
1782				<1 RK_PB1 4 &pcfg_pull_none>;
1783		};
1784
1785		/omit-if-no-ref/
1786		pcie30x4_button_rstn: pcie30x4-button-rstn {
1787			rockchip,pins =
1788				/* pcie30x4_button_rstn */
1789				<3 RK_PD5 4 &pcfg_pull_none>;
1790		};
1791	};
1792
1793	pdm0 {
1794		/omit-if-no-ref/
1795		pdm0m0_clk: pdm0m0-clk {
1796			rockchip,pins =
1797				/* pdm0_clk0_m0 */
1798				<1 RK_PC6 3 &pcfg_pull_none>;
1799		};
1800
1801		/omit-if-no-ref/
1802		pdm0m0_clk1: pdm0m0-clk1 {
1803			rockchip,pins =
1804				/* pdm0m0_clk1 */
1805				<1 RK_PC4 3 &pcfg_pull_none>;
1806		};
1807
1808		/omit-if-no-ref/
1809		pdm0m0_sdi0: pdm0m0-sdi0 {
1810			rockchip,pins =
1811				/* pdm0m0_sdi0 */
1812				<1 RK_PD5 3 &pcfg_pull_none>;
1813		};
1814
1815		/omit-if-no-ref/
1816		pdm0m0_sdi1: pdm0m0-sdi1 {
1817			rockchip,pins =
1818				/* pdm0m0_sdi1 */
1819				<1 RK_PD1 3 &pcfg_pull_none>;
1820		};
1821
1822		/omit-if-no-ref/
1823		pdm0m0_sdi2: pdm0m0-sdi2 {
1824			rockchip,pins =
1825				/* pdm0m0_sdi2 */
1826				<1 RK_PD2 3 &pcfg_pull_none>;
1827		};
1828
1829		/omit-if-no-ref/
1830		pdm0m0_sdi3: pdm0m0-sdi3 {
1831			rockchip,pins =
1832				/* pdm0m0_sdi3 */
1833				<1 RK_PD3 3 &pcfg_pull_none>;
1834		};
1835		/omit-if-no-ref/
1836		pdm0m1_clk: pdm0m1-clk {
1837			rockchip,pins =
1838				/* pdm0_clk0_m1 */
1839				<0 RK_PC0 2 &pcfg_pull_none>;
1840		};
1841
1842		/omit-if-no-ref/
1843		pdm0m1_clk1: pdm0m1-clk1 {
1844			rockchip,pins =
1845				/* pdm0m1_clk1 */
1846				<0 RK_PC4 2 &pcfg_pull_none>;
1847		};
1848
1849		/omit-if-no-ref/
1850		pdm0m1_sdi0: pdm0m1-sdi0 {
1851			rockchip,pins =
1852				/* pdm0m1_sdi0 */
1853				<0 RK_PC7 2 &pcfg_pull_none>;
1854		};
1855
1856		/omit-if-no-ref/
1857		pdm0m1_sdi1: pdm0m1-sdi1 {
1858			rockchip,pins =
1859				/* pdm0m1_sdi1 */
1860				<0 RK_PD0 2 &pcfg_pull_none>;
1861		};
1862
1863		/omit-if-no-ref/
1864		pdm0m1_sdi2: pdm0m1-sdi2 {
1865			rockchip,pins =
1866				/* pdm0m1_sdi2 */
1867				<0 RK_PD4 2 &pcfg_pull_none>;
1868		};
1869
1870		/omit-if-no-ref/
1871		pdm0m1_sdi3: pdm0m1-sdi3 {
1872			rockchip,pins =
1873				/* pdm0m1_sdi3 */
1874				<0 RK_PD6 2 &pcfg_pull_none>;
1875		};
1876	};
1877
1878	pdm1 {
1879		/omit-if-no-ref/
1880		pdm1m0_clk: pdm1m0-clk {
1881			rockchip,pins =
1882				/* pdm1_clk0_m0 */
1883				<4 RK_PD5 2 &pcfg_pull_none>;
1884		};
1885
1886		/omit-if-no-ref/
1887		pdm1m0_clk1: pdm1m0-clk1 {
1888			rockchip,pins =
1889				/* pdm1m0_clk1 */
1890				<4 RK_PD4 2 &pcfg_pull_none>;
1891		};
1892
1893		/omit-if-no-ref/
1894		pdm1m0_sdi0: pdm1m0-sdi0 {
1895			rockchip,pins =
1896				/* pdm1m0_sdi0 */
1897				<4 RK_PD3 2 &pcfg_pull_none>;
1898		};
1899
1900		/omit-if-no-ref/
1901		pdm1m0_sdi1: pdm1m0-sdi1 {
1902			rockchip,pins =
1903				/* pdm1m0_sdi1 */
1904				<4 RK_PD2 2 &pcfg_pull_none>;
1905		};
1906
1907		/omit-if-no-ref/
1908		pdm1m0_sdi2: pdm1m0-sdi2 {
1909			rockchip,pins =
1910				/* pdm1m0_sdi2 */
1911				<4 RK_PD1 2 &pcfg_pull_none>;
1912		};
1913
1914		/omit-if-no-ref/
1915		pdm1m0_sdi3: pdm1m0-sdi3 {
1916			rockchip,pins =
1917				/* pdm1m0_sdi3 */
1918				<4 RK_PD0 2 &pcfg_pull_none>;
1919		};
1920		/omit-if-no-ref/
1921		pdm1m1_clk: pdm1m1-clk {
1922			rockchip,pins =
1923				/* pdm1_clk0_m1 */
1924				<1 RK_PB4 2 &pcfg_pull_none>;
1925		};
1926
1927		/omit-if-no-ref/
1928		pdm1m1_clk1: pdm1m1-clk1 {
1929			rockchip,pins =
1930				/* pdm1m1_clk1 */
1931				<1 RK_PB3 2 &pcfg_pull_none>;
1932		};
1933
1934		/omit-if-no-ref/
1935		pdm1m1_sdi0: pdm1m1-sdi0 {
1936			rockchip,pins =
1937				/* pdm1m1_sdi0 */
1938				<1 RK_PA7 2 &pcfg_pull_none>;
1939		};
1940
1941		/omit-if-no-ref/
1942		pdm1m1_sdi1: pdm1m1-sdi1 {
1943			rockchip,pins =
1944				/* pdm1m1_sdi1 */
1945				<1 RK_PB0 2 &pcfg_pull_none>;
1946		};
1947
1948		/omit-if-no-ref/
1949		pdm1m1_sdi2: pdm1m1-sdi2 {
1950			rockchip,pins =
1951				/* pdm1m1_sdi2 */
1952				<1 RK_PB1 2 &pcfg_pull_none>;
1953		};
1954
1955		/omit-if-no-ref/
1956		pdm1m1_sdi3: pdm1m1-sdi3 {
1957			rockchip,pins =
1958				/* pdm1m1_sdi3 */
1959				<1 RK_PB2 2 &pcfg_pull_none>;
1960		};
1961	};
1962
1963	pmic {
1964		/omit-if-no-ref/
1965		pmic_pins: pmic-pins {
1966			rockchip,pins =
1967				/* pmic_int_l */
1968				<0 RK_PA7 0 &pcfg_pull_up>,
1969				/* pmic_sleep1 */
1970				<0 RK_PA2 1 &pcfg_pull_none>,
1971				/* pmic_sleep2 */
1972				<0 RK_PA3 1 &pcfg_pull_none>,
1973				/* pmic_sleep3 */
1974				<0 RK_PC1 1 &pcfg_pull_none>,
1975				/* pmic_sleep4 */
1976				<0 RK_PC2 1 &pcfg_pull_none>,
1977				/* pmic_sleep5 */
1978				<0 RK_PC3 1 &pcfg_pull_none>,
1979				/* pmic_sleep6 */
1980				<0 RK_PD6 1 &pcfg_pull_none>;
1981		};
1982	};
1983
1984	pmu {
1985		/omit-if-no-ref/
1986		pmu_pins: pmu-pins {
1987			rockchip,pins =
1988				/* pmu_debug */
1989				<0 RK_PA5 3 &pcfg_pull_none>;
1990		};
1991	};
1992
1993	pwm0 {
1994		/omit-if-no-ref/
1995		pwm0m0_pins: pwm0m0-pins {
1996			rockchip,pins =
1997				/* pwm0_m0 */
1998				<0 RK_PB7 3 &pcfg_pull_none>;
1999		};
2000
2001		/omit-if-no-ref/
2002		pwm0m1_pins: pwm0m1-pins {
2003			rockchip,pins =
2004				/* pwm0_m1 */
2005				<1 RK_PD2 11 &pcfg_pull_none>;
2006		};
2007
2008		/omit-if-no-ref/
2009		pwm0m2_pins: pwm0m2-pins {
2010			rockchip,pins =
2011				/* pwm0_m2 */
2012				<1 RK_PA2 11 &pcfg_pull_none>;
2013		};
2014	};
2015
2016	pwm1 {
2017		/omit-if-no-ref/
2018		pwm1m0_pins: pwm1m0-pins {
2019			rockchip,pins =
2020				/* pwm1_m0 */
2021				<0 RK_PC0 3 &pcfg_pull_none>;
2022		};
2023
2024		/omit-if-no-ref/
2025		pwm1m1_pins: pwm1m1-pins {
2026			rockchip,pins =
2027				/* pwm1_m1 */
2028				<1 RK_PD3 11 &pcfg_pull_none>;
2029		};
2030
2031		/omit-if-no-ref/
2032		pwm1m2_pins: pwm1m2-pins {
2033			rockchip,pins =
2034				/* pwm1_m2 */
2035				<1 RK_PA3 11 &pcfg_pull_none>;
2036		};
2037	};
2038
2039	pwm2 {
2040		/omit-if-no-ref/
2041		pwm2m0_pins: pwm2m0-pins {
2042			rockchip,pins =
2043				/* pwm2_m0 */
2044				<0 RK_PC4 3 &pcfg_pull_none>;
2045		};
2046
2047		/omit-if-no-ref/
2048		pwm2m1_pins: pwm2m1-pins {
2049			rockchip,pins =
2050				/* pwm2_m1 */
2051				<3 RK_PB1 11 &pcfg_pull_none>;
2052		};
2053	};
2054
2055	pwm3 {
2056		/omit-if-no-ref/
2057		pwm3m0_pins: pwm3m0-pins {
2058			rockchip,pins =
2059				/* pwm3_ir_m0 */
2060				<0 RK_PD4 3 &pcfg_pull_none>;
2061		};
2062
2063		/omit-if-no-ref/
2064		pwm3m1_pins: pwm3m1-pins {
2065			rockchip,pins =
2066				/* pwm3_ir_m1 */
2067				<3 RK_PB2 11 &pcfg_pull_none>;
2068		};
2069
2070		/omit-if-no-ref/
2071		pwm3m2_pins: pwm3m2-pins {
2072			rockchip,pins =
2073				/* pwm3_ir_m2 */
2074				<1 RK_PC2 11 &pcfg_pull_none>;
2075		};
2076
2077		/omit-if-no-ref/
2078		pwm3m3_pins: pwm3m3-pins {
2079			rockchip,pins =
2080				/* pwm3_ir_m3 */
2081				<1 RK_PA7 11 &pcfg_pull_none>;
2082		};
2083	};
2084
2085	pwm4 {
2086		/omit-if-no-ref/
2087		pwm4m0_pins: pwm4m0-pins {
2088			rockchip,pins =
2089				/* pwm4_m0 */
2090				<0 RK_PC5 11 &pcfg_pull_none>;
2091		};
2092	};
2093
2094	pwm5 {
2095		/omit-if-no-ref/
2096		pwm5m0_pins: pwm5m0-pins {
2097			rockchip,pins =
2098				/* pwm5_m0 */
2099				<0 RK_PB1 3 &pcfg_pull_none>;
2100		};
2101
2102		/omit-if-no-ref/
2103		pwm5m1_pins: pwm5m1-pins {
2104			rockchip,pins =
2105				/* pwm5_m1 */
2106				<0 RK_PC6 11 &pcfg_pull_none>;
2107		};
2108	};
2109
2110	pwm6 {
2111		/omit-if-no-ref/
2112		pwm6m0_pins: pwm6m0-pins {
2113			rockchip,pins =
2114				/* pwm6_m0 */
2115				<0 RK_PC7 11 &pcfg_pull_none>;
2116		};
2117
2118		/omit-if-no-ref/
2119		pwm6m1_pins: pwm6m1-pins {
2120			rockchip,pins =
2121				/* pwm6_m1 */
2122				<4 RK_PC1 11 &pcfg_pull_none>;
2123		};
2124	};
2125
2126	pwm7 {
2127		/omit-if-no-ref/
2128		pwm7m0_pins: pwm7m0-pins {
2129			rockchip,pins =
2130				/* pwm7_ir_m0 */
2131				<0 RK_PD0 11 &pcfg_pull_none>;
2132		};
2133
2134		/omit-if-no-ref/
2135		pwm7m1_pins: pwm7m1-pins {
2136			rockchip,pins =
2137				/* pwm7_ir_m1 */
2138				<4 RK_PD4 11 &pcfg_pull_none>;
2139		};
2140
2141		/omit-if-no-ref/
2142		pwm7m2_pins: pwm7m2-pins {
2143			rockchip,pins =
2144				/* pwm7_ir_m2 */
2145				<1 RK_PC3 11 &pcfg_pull_none>;
2146		};
2147	};
2148
2149	pwm8 {
2150		/omit-if-no-ref/
2151		pwm8m0_pins: pwm8m0-pins {
2152			rockchip,pins =
2153				/* pwm8_m0 */
2154				<3 RK_PA7 11 &pcfg_pull_none>;
2155		};
2156
2157		/omit-if-no-ref/
2158		pwm8m1_pins: pwm8m1-pins {
2159			rockchip,pins =
2160				/* pwm8_m1 */
2161				<4 RK_PD0 11 &pcfg_pull_none>;
2162		};
2163
2164		/omit-if-no-ref/
2165		pwm8m2_pins: pwm8m2-pins {
2166			rockchip,pins =
2167				/* pwm8_m2 */
2168				<3 RK_PD0 11 &pcfg_pull_none>;
2169		};
2170	};
2171
2172	pwm9 {
2173		/omit-if-no-ref/
2174		pwm9m0_pins: pwm9m0-pins {
2175			rockchip,pins =
2176				/* pwm9_m0 */
2177				<3 RK_PB0 11 &pcfg_pull_none>;
2178		};
2179
2180		/omit-if-no-ref/
2181		pwm9m1_pins: pwm9m1-pins {
2182			rockchip,pins =
2183				/* pwm9_m1 */
2184				<4 RK_PD1 11 &pcfg_pull_none>;
2185		};
2186
2187		/omit-if-no-ref/
2188		pwm9m2_pins: pwm9m2-pins {
2189			rockchip,pins =
2190				/* pwm9_m2 */
2191				<3 RK_PD1 11 &pcfg_pull_none>;
2192		};
2193	};
2194
2195	pwm10 {
2196		/omit-if-no-ref/
2197		pwm10m0_pins: pwm10m0-pins {
2198			rockchip,pins =
2199				/* pwm10_m0 */
2200				<3 RK_PA0 11 &pcfg_pull_none>;
2201		};
2202
2203		/omit-if-no-ref/
2204		pwm10m1_pins: pwm10m1-pins {
2205			rockchip,pins =
2206				/* pwm10_m1 */
2207				<4 RK_PD3 11 &pcfg_pull_none>;
2208		};
2209
2210		/omit-if-no-ref/
2211		pwm10m2_pins: pwm10m2-pins {
2212			rockchip,pins =
2213				/* pwm10_m2 */
2214				<3 RK_PD3 11 &pcfg_pull_none>;
2215		};
2216	};
2217
2218	pwm11 {
2219		/omit-if-no-ref/
2220		pwm11m0_pins: pwm11m0-pins {
2221			rockchip,pins =
2222				/* pwm11_ir_m0 */
2223				<3 RK_PA1 11 &pcfg_pull_none>;
2224		};
2225
2226		/omit-if-no-ref/
2227		pwm11m1_pins: pwm11m1-pins {
2228			rockchip,pins =
2229				/* pwm11_ir_m1 */
2230				<4 RK_PB4 11 &pcfg_pull_none>;
2231		};
2232
2233		/omit-if-no-ref/
2234		pwm11m2_pins: pwm11m2-pins {
2235			rockchip,pins =
2236				/* pwm11_ir_m2 */
2237				<1 RK_PC4 11 &pcfg_pull_none>;
2238		};
2239
2240		/omit-if-no-ref/
2241		pwm11m3_pins: pwm11m3-pins {
2242			rockchip,pins =
2243				/* pwm11_ir_m3 */
2244				<3 RK_PD5 11 &pcfg_pull_none>;
2245		};
2246	};
2247
2248	pwm12 {
2249		/omit-if-no-ref/
2250		pwm12m0_pins: pwm12m0-pins {
2251			rockchip,pins =
2252				/* pwm12_m0 */
2253				<3 RK_PB5 11 &pcfg_pull_none>;
2254		};
2255
2256		/omit-if-no-ref/
2257		pwm12m1_pins: pwm12m1-pins {
2258			rockchip,pins =
2259				/* pwm12_m1 */
2260				<4 RK_PB5 11 &pcfg_pull_none>;
2261		};
2262	};
2263
2264	pwm13 {
2265		/omit-if-no-ref/
2266		pwm13m0_pins: pwm13m0-pins {
2267			rockchip,pins =
2268				/* pwm13_m0 */
2269				<3 RK_PB6 11 &pcfg_pull_none>;
2270		};
2271
2272		/omit-if-no-ref/
2273		pwm13m1_pins: pwm13m1-pins {
2274			rockchip,pins =
2275				/* pwm13_m1 */
2276				<4 RK_PB6 11 &pcfg_pull_none>;
2277		};
2278
2279		/omit-if-no-ref/
2280		pwm13m2_pins: pwm13m2-pins {
2281			rockchip,pins =
2282				/* pwm13_m2 */
2283				<1 RK_PB7 11 &pcfg_pull_none>;
2284		};
2285	};
2286
2287	pwm14 {
2288		/omit-if-no-ref/
2289		pwm14m0_pins: pwm14m0-pins {
2290			rockchip,pins =
2291				/* pwm14_m0 */
2292				<3 RK_PC2 11 &pcfg_pull_none>;
2293		};
2294
2295		/omit-if-no-ref/
2296		pwm14m1_pins: pwm14m1-pins {
2297			rockchip,pins =
2298				/* pwm14_m1 */
2299				<4 RK_PB2 11 &pcfg_pull_none>;
2300		};
2301
2302		/omit-if-no-ref/
2303		pwm14m2_pins: pwm14m2-pins {
2304			rockchip,pins =
2305				/* pwm14_m2 */
2306				<1 RK_PD6 11 &pcfg_pull_none>;
2307		};
2308	};
2309
2310	pwm15 {
2311		/omit-if-no-ref/
2312		pwm15m0_pins: pwm15m0-pins {
2313			rockchip,pins =
2314				/* pwm15_ir_m0 */
2315				<3 RK_PC3 11 &pcfg_pull_none>;
2316		};
2317
2318		/omit-if-no-ref/
2319		pwm15m1_pins: pwm15m1-pins {
2320			rockchip,pins =
2321				/* pwm15_ir_m1 */
2322				<4 RK_PB3 11 &pcfg_pull_none>;
2323		};
2324
2325		/omit-if-no-ref/
2326		pwm15m2_pins: pwm15m2-pins {
2327			rockchip,pins =
2328				/* pwm15_ir_m2 */
2329				<1 RK_PC6 11 &pcfg_pull_none>;
2330		};
2331
2332		/omit-if-no-ref/
2333		pwm15m3_pins: pwm15m3-pins {
2334			rockchip,pins =
2335				/* pwm15_ir_m3 */
2336				<1 RK_PD7 11 &pcfg_pull_none>;
2337		};
2338	};
2339
2340	refclk {
2341		/omit-if-no-ref/
2342		refclk_pins: refclk-pins {
2343			rockchip,pins =
2344				/* refclk_out */
2345				<0 RK_PA0 1 &pcfg_pull_none>;
2346		};
2347	};
2348
2349	sata {
2350		/omit-if-no-ref/
2351		sata_pins: sata-pins {
2352			rockchip,pins =
2353				/* sata_cp_pod */
2354				<0 RK_PC6 13 &pcfg_pull_none>,
2355				/* sata_cpdet */
2356				<0 RK_PD4 13 &pcfg_pull_none>,
2357				/* sata_mp_switch */
2358				<0 RK_PD5 13 &pcfg_pull_none>;
2359		};
2360	};
2361
2362	sata0 {
2363		/omit-if-no-ref/
2364		sata0m0_pins: sata0m0-pins {
2365			rockchip,pins =
2366				/* sata0_act_led_m0 */
2367				<4 RK_PB6 6 &pcfg_pull_none>;
2368		};
2369
2370		/omit-if-no-ref/
2371		sata0m1_pins: sata0m1-pins {
2372			rockchip,pins =
2373				/* sata0_act_led_m1 */
2374				<1 RK_PB3 6 &pcfg_pull_none>;
2375		};
2376	};
2377
2378	sata1 {
2379		/omit-if-no-ref/
2380		sata1m0_pins: sata1m0-pins {
2381			rockchip,pins =
2382				/* sata1_act_led_m0 */
2383				<4 RK_PB5 6 &pcfg_pull_none>;
2384		};
2385
2386		/omit-if-no-ref/
2387		sata1m1_pins: sata1m1-pins {
2388			rockchip,pins =
2389				/* sata1_act_led_m1 */
2390				<1 RK_PA1 6 &pcfg_pull_none>;
2391		};
2392	};
2393
2394	sata2 {
2395		/omit-if-no-ref/
2396		sata2m0_pins: sata2m0-pins {
2397			rockchip,pins =
2398				/* sata2_act_led_m0 */
2399				<4 RK_PB1 6 &pcfg_pull_none>;
2400		};
2401
2402		/omit-if-no-ref/
2403		sata2m1_pins: sata2m1-pins {
2404			rockchip,pins =
2405				/* sata2_act_led_m1 */
2406				<1 RK_PB7 6 &pcfg_pull_none>;
2407		};
2408	};
2409
2410	sdio {
2411		/omit-if-no-ref/
2412		sdiom1_pins: sdiom1-pins {
2413			rockchip,pins =
2414				/* sdio_clk_m1 */
2415				<3 RK_PA5 2 &pcfg_pull_none>,
2416				/* sdio_cmd_m1 */
2417				<3 RK_PA4 2 &pcfg_pull_none>,
2418				/* sdio_d0_m1 */
2419				<3 RK_PA0 2 &pcfg_pull_none>,
2420				/* sdio_d1_m1 */
2421				<3 RK_PA1 2 &pcfg_pull_none>,
2422				/* sdio_d2_m1 */
2423				<3 RK_PA2 2 &pcfg_pull_none>,
2424				/* sdio_d3_m1 */
2425				<3 RK_PA3 2 &pcfg_pull_none>;
2426		};
2427	};
2428
2429	sdmmc {
2430		/omit-if-no-ref/
2431		sdmmc_bus4: sdmmc-bus4 {
2432			rockchip,pins =
2433				/* sdmmc_d0 */
2434				<4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
2435				/* sdmmc_d1 */
2436				<4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
2437				/* sdmmc_d2 */
2438				<4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
2439				/* sdmmc_d3 */
2440				<4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
2441		};
2442
2443		/omit-if-no-ref/
2444		sdmmc_clk: sdmmc-clk {
2445			rockchip,pins =
2446				/* sdmmc_clk */
2447				<4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
2448		};
2449
2450		/omit-if-no-ref/
2451		sdmmc_cmd: sdmmc-cmd {
2452			rockchip,pins =
2453				/* sdmmc_cmd */
2454				<4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
2455		};
2456
2457		/omit-if-no-ref/
2458		sdmmc_det: sdmmc-det {
2459			rockchip,pins =
2460				/* sdmmc_det */
2461				<0 RK_PA4 1 &pcfg_pull_up>;
2462		};
2463
2464		/omit-if-no-ref/
2465		sdmmc_pwren: sdmmc-pwren {
2466			rockchip,pins =
2467				/* sdmmc_pwren */
2468				<0 RK_PA5 2 &pcfg_pull_none>;
2469		};
2470	};
2471
2472	spdif0 {
2473		/omit-if-no-ref/
2474		spdif0m0_tx: spdif0m0-tx {
2475			rockchip,pins =
2476				/* spdif0m0_tx */
2477				<1 RK_PB6 3 &pcfg_pull_none>;
2478		};
2479
2480		/omit-if-no-ref/
2481		spdif0m1_tx: spdif0m1-tx {
2482			rockchip,pins =
2483				/* spdif0m1_tx */
2484				<4 RK_PB4 6 &pcfg_pull_none>;
2485		};
2486	};
2487
2488	spdif1 {
2489		/omit-if-no-ref/
2490		spdif1m0_tx: spdif1m0-tx {
2491			rockchip,pins =
2492				/* spdif1m0_tx */
2493				<1 RK_PB7 3 &pcfg_pull_none>;
2494		};
2495
2496		/omit-if-no-ref/
2497		spdif1m1_tx: spdif1m1-tx {
2498			rockchip,pins =
2499				/* spdif1m1_tx */
2500				<4 RK_PB1 2 &pcfg_pull_none>;
2501		};
2502
2503		/omit-if-no-ref/
2504		spdif1m2_tx: spdif1m2-tx {
2505			rockchip,pins =
2506				/* spdif1m2_tx */
2507				<4 RK_PC1 3 &pcfg_pull_none>;
2508		};
2509	};
2510
2511	spi0 {
2512		/omit-if-no-ref/
2513		spi0m0_pins: spi0m0-pins {
2514			rockchip,pins =
2515				/* spi0_clk_m0 */
2516				<0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2517				/* spi0_miso_m0 */
2518				<0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
2519				/* spi0_mosi_m0 */
2520				<0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2521		};
2522
2523		/omit-if-no-ref/
2524		spi0m0_cs0: spi0m0-cs0 {
2525			rockchip,pins =
2526				/* spi0_cs0_m0 */
2527				<0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2528		};
2529
2530		/omit-if-no-ref/
2531		spi0m0_cs1: spi0m0-cs1 {
2532			rockchip,pins =
2533				/* spi0_cs1_m0 */
2534				<0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2535		};
2536		/omit-if-no-ref/
2537		spi0m1_pins: spi0m1-pins {
2538			rockchip,pins =
2539				/* spi0_clk_m1 */
2540				<4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2541				/* spi0_miso_m1 */
2542				<4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2543				/* spi0_mosi_m1 */
2544				<4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2545		};
2546
2547		/omit-if-no-ref/
2548		spi0m1_cs0: spi0m1-cs0 {
2549			rockchip,pins =
2550				/* spi0_cs0_m1 */
2551				<4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2552		};
2553
2554		/omit-if-no-ref/
2555		spi0m1_cs1: spi0m1-cs1 {
2556			rockchip,pins =
2557				/* spi0_cs1_m1 */
2558				<4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
2559		};
2560		/omit-if-no-ref/
2561		spi0m2_pins: spi0m2-pins {
2562			rockchip,pins =
2563				/* spi0_clk_m2 */
2564				<1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
2565				/* spi0_miso_m2 */
2566				<1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
2567				/* spi0_mosi_m2 */
2568				<1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2569		};
2570
2571		/omit-if-no-ref/
2572		spi0m2_cs0: spi0m2-cs0 {
2573			rockchip,pins =
2574				/* spi0_cs0_m2 */
2575				<1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
2576		};
2577
2578		/omit-if-no-ref/
2579		spi0m2_cs1: spi0m2-cs1 {
2580			rockchip,pins =
2581				/* spi0_cs1_m2 */
2582				<1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
2583		};
2584		/omit-if-no-ref/
2585		spi0m3_pins: spi0m3-pins {
2586			rockchip,pins =
2587				/* spi0_clk_m3 */
2588				<3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2589				/* spi0_miso_m3 */
2590				<3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
2591				/* spi0_mosi_m3 */
2592				<3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2593		};
2594
2595		/omit-if-no-ref/
2596		spi0m3_cs0: spi0m3-cs0 {
2597			rockchip,pins =
2598				/* spi0_cs0_m3 */
2599				<3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2600		};
2601
2602		/omit-if-no-ref/
2603		spi0m3_cs1: spi0m3-cs1 {
2604			rockchip,pins =
2605				/* spi0_cs1_m3 */
2606				<3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2607		};
2608	};
2609
2610	spi1 {
2611		/omit-if-no-ref/
2612		spi1m1_pins: spi1m1-pins {
2613			rockchip,pins =
2614				/* spi1_clk_m1 */
2615				<3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
2616				/* spi1_miso_m1 */
2617				<3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2618				/* spi1_mosi_m1 */
2619				<3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2620		};
2621
2622		/omit-if-no-ref/
2623		spi1m1_cs0: spi1m1-cs0 {
2624			rockchip,pins =
2625				/* spi1_cs0_m1 */
2626				<3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
2627		};
2628
2629		/omit-if-no-ref/
2630		spi1m1_cs1: spi1m1-cs1 {
2631			rockchip,pins =
2632				/* spi1_cs1_m1 */
2633				<3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2634		};
2635
2636		/omit-if-no-ref/
2637		spi1m2_pins: spi1m2-pins {
2638			rockchip,pins =
2639				/* spi1_clk_m2 */
2640				<1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
2641				/* spi1_miso_m2 */
2642				<1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2643				/* spi1_mosi_m2 */
2644				<1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2645		};
2646
2647		/omit-if-no-ref/
2648		spi1m2_cs0: spi1m2-cs0 {
2649			rockchip,pins =
2650				/* spi1_cs0_m2 */
2651				<1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
2652		};
2653
2654		/omit-if-no-ref/
2655		spi1m2_cs1: spi1m2-cs1 {
2656			rockchip,pins =
2657				/* spi1_cs1_m2 */
2658				<1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2659		};
2660	};
2661
2662	spi2 {
2663		/omit-if-no-ref/
2664		spi2m0_pins: spi2m0-pins {
2665			rockchip,pins =
2666				/* spi2_clk_m0 */
2667				<1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2668				/* spi2_miso_m0 */
2669				<1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2670				/* spi2_mosi_m0 */
2671				<1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2672		};
2673
2674		/omit-if-no-ref/
2675		spi2m0_cs0: spi2m0-cs0 {
2676			rockchip,pins =
2677				/* spi2_cs0_m0 */
2678				<1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2679		};
2680
2681		/omit-if-no-ref/
2682		spi2m0_cs1: spi2m0-cs1 {
2683			rockchip,pins =
2684				/* spi2_cs1_m0 */
2685				<1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2686		};
2687
2688		/omit-if-no-ref/
2689		spi2m1_pins: spi2m1-pins {
2690			rockchip,pins =
2691				/* spi2_clk_m1 */
2692				<4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2693				/* spi2_miso_m1 */
2694				<4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2695				/* spi2_mosi_m1 */
2696				<4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2697		};
2698
2699		/omit-if-no-ref/
2700		spi2m1_cs0: spi2m1-cs0 {
2701			rockchip,pins =
2702				/* spi2_cs0_m1 */
2703				<4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2704		};
2705
2706		/omit-if-no-ref/
2707		spi2m1_cs1: spi2m1-cs1 {
2708			rockchip,pins =
2709				/* spi2_cs1_m1 */
2710				<4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2711		};
2712
2713		/omit-if-no-ref/
2714		spi2m2_pins: spi2m2-pins {
2715			rockchip,pins =
2716				/* spi2_clk_m2 */
2717				<0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
2718				/* spi2_miso_m2 */
2719				<0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
2720				/* spi2_mosi_m2 */
2721				<0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
2722		};
2723
2724		/omit-if-no-ref/
2725		spi2m2_cs0: spi2m2-cs0 {
2726			rockchip,pins =
2727				/* spi2_cs0_m2 */
2728				<0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
2729		};
2730
2731		/omit-if-no-ref/
2732		spi2m2_cs1: spi2m2-cs1 {
2733			rockchip,pins =
2734				/* spi2_cs1_m2 */
2735				<0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
2736		};
2737	};
2738
2739	spi3 {
2740		/omit-if-no-ref/
2741		spi3m1_pins: spi3m1-pins {
2742			rockchip,pins =
2743				/* spi3_clk_m1 */
2744				<4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
2745				/* spi3_miso_m1 */
2746				<4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
2747				/* spi3_mosi_m1 */
2748				<4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
2749		};
2750
2751		/omit-if-no-ref/
2752		spi3m1_cs0: spi3m1-cs0 {
2753			rockchip,pins =
2754				/* spi3_cs0_m1 */
2755				<4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2756		};
2757
2758		/omit-if-no-ref/
2759		spi3m1_cs1: spi3m1-cs1 {
2760			rockchip,pins =
2761				/* spi3_cs1_m1 */
2762				<4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2763		};
2764
2765		/omit-if-no-ref/
2766		spi3m2_pins: spi3m2-pins {
2767			rockchip,pins =
2768				/* spi3_clk_m2 */
2769				<0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2770				/* spi3_miso_m2 */
2771				<0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2772				/* spi3_mosi_m2 */
2773				<0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2774		};
2775
2776		/omit-if-no-ref/
2777		spi3m2_cs0: spi3m2-cs0 {
2778			rockchip,pins =
2779				/* spi3_cs0_m2 */
2780				<0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2781		};
2782
2783		/omit-if-no-ref/
2784		spi3m2_cs1: spi3m2-cs1 {
2785			rockchip,pins =
2786				/* spi3_cs1_m2 */
2787				<0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2788		};
2789
2790		/omit-if-no-ref/
2791		spi3m3_pins: spi3m3-pins {
2792			rockchip,pins =
2793				/* spi3_clk_m3 */
2794				<3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2795				/* spi3_miso_m3 */
2796				<3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2797				/* spi3_mosi_m3 */
2798				<3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
2799		};
2800
2801		/omit-if-no-ref/
2802		spi3m3_cs0: spi3m3-cs0 {
2803			rockchip,pins =
2804				/* spi3_cs0_m3 */
2805				<3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2806		};
2807
2808		/omit-if-no-ref/
2809		spi3m3_cs1: spi3m3-cs1 {
2810			rockchip,pins =
2811				/* spi3_cs1_m3 */
2812				<3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
2813		};
2814	};
2815
2816	spi4 {
2817		/omit-if-no-ref/
2818		spi4m0_pins: spi4m0-pins {
2819			rockchip,pins =
2820				/* spi4_clk_m0 */
2821				<1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
2822				/* spi4_miso_m0 */
2823				<1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2824				/* spi4_mosi_m0 */
2825				<1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2826		};
2827
2828		/omit-if-no-ref/
2829		spi4m0_cs0: spi4m0-cs0 {
2830			rockchip,pins =
2831				/* spi4_cs0_m0 */
2832				<1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2833		};
2834
2835		/omit-if-no-ref/
2836		spi4m0_cs1: spi4m0-cs1 {
2837			rockchip,pins =
2838				/* spi4_cs1_m0 */
2839				<1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2840		};
2841
2842		/omit-if-no-ref/
2843		spi4m1_pins: spi4m1-pins {
2844			rockchip,pins =
2845				/* spi4_clk_m1 */
2846				<3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2847				/* spi4_miso_m1 */
2848				<3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2849				/* spi4_mosi_m1 */
2850				<3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2851		};
2852
2853		/omit-if-no-ref/
2854		spi4m1_cs0: spi4m1-cs0 {
2855			rockchip,pins =
2856				/* spi4_cs0_m1 */
2857				<3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2858		};
2859
2860		/omit-if-no-ref/
2861		spi4m1_cs1: spi4m1-cs1 {
2862			rockchip,pins =
2863				/* spi4_cs1_m1 */
2864				<3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
2865		};
2866
2867		/omit-if-no-ref/
2868		spi4m2_pins: spi4m2-pins {
2869			rockchip,pins =
2870				/* spi4_clk_m2 */
2871				<1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2872				/* spi4_miso_m2 */
2873				<1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2874				/* spi4_mosi_m2 */
2875				<1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2876		};
2877
2878		/omit-if-no-ref/
2879		spi4m2_cs0: spi4m2-cs0 {
2880			rockchip,pins =
2881				/* spi4_cs0_m2 */
2882				<1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2883		};
2884	};
2885
2886	tsadc {
2887		/omit-if-no-ref/
2888		tsadcm1_shut: tsadcm1-shut {
2889			rockchip,pins =
2890				/* tsadcm1_shut */
2891				<0 RK_PA2 2 &pcfg_pull_none>;
2892		};
2893
2894		/omit-if-no-ref/
2895		tsadc_shut: tsadc-shut {
2896			rockchip,pins =
2897				/* tsadc_shut */
2898				<0 RK_PA1 2 &pcfg_pull_none>;
2899		};
2900
2901		/omit-if-no-ref/
2902		tsadc_shut_org: tsadc-shut-org {
2903			rockchip,pins =
2904				/* tsadc_shut_org */
2905				<0 RK_PA1 1 &pcfg_pull_none>;
2906		};
2907	};
2908
2909	uart0 {
2910		/omit-if-no-ref/
2911		uart0m0_xfer: uart0m0-xfer {
2912			rockchip,pins =
2913				/* uart0_rx_m0 */
2914				<0 RK_PC4 4 &pcfg_pull_up>,
2915				/* uart0_tx_m0 */
2916				<0 RK_PC5 4 &pcfg_pull_up>;
2917		};
2918
2919		/omit-if-no-ref/
2920		uart0m1_xfer: uart0m1-xfer {
2921			rockchip,pins =
2922				/* uart0_rx_m1 */
2923				<0 RK_PB0 4 &pcfg_pull_up>,
2924				/* uart0_tx_m1 */
2925				<0 RK_PB1 4 &pcfg_pull_up>;
2926		};
2927
2928		/omit-if-no-ref/
2929		uart0m2_xfer: uart0m2-xfer {
2930			rockchip,pins =
2931				/* uart0_rx_m2 */
2932				<4 RK_PA4 10 &pcfg_pull_up>,
2933				/* uart0_tx_m2 */
2934				<4 RK_PA3 10 &pcfg_pull_up>;
2935		};
2936
2937		/omit-if-no-ref/
2938		uart0_ctsn: uart0-ctsn {
2939			rockchip,pins =
2940				/* uart0_ctsn */
2941				<0 RK_PD1 4 &pcfg_pull_none>;
2942		};
2943
2944		/omit-if-no-ref/
2945		uart0_rtsn: uart0-rtsn {
2946			rockchip,pins =
2947				/* uart0_rtsn */
2948				<0 RK_PC6 4 &pcfg_pull_none>;
2949		};
2950	};
2951
2952	uart1 {
2953		/omit-if-no-ref/
2954		uart1m1_xfer: uart1m1-xfer {
2955			rockchip,pins =
2956				/* uart1_rx_m1 */
2957				<1 RK_PB7 10 &pcfg_pull_up>,
2958				/* uart1_tx_m1 */
2959				<1 RK_PB6 10 &pcfg_pull_up>;
2960		};
2961
2962		/omit-if-no-ref/
2963		uart1m1_ctsn: uart1m1-ctsn {
2964			rockchip,pins =
2965				/* uart1m1_ctsn */
2966				<1 RK_PD7 10 &pcfg_pull_none>;
2967		};
2968
2969		/omit-if-no-ref/
2970		uart1m1_rtsn: uart1m1-rtsn {
2971			rockchip,pins =
2972				/* uart1m1_rtsn */
2973				<1 RK_PD6 10 &pcfg_pull_none>;
2974		};
2975
2976		/omit-if-no-ref/
2977		uart1m2_xfer: uart1m2-xfer {
2978			rockchip,pins =
2979				/* uart1_rx_m2 */
2980				<0 RK_PD2 10 &pcfg_pull_up>,
2981				/* uart1_tx_m2 */
2982				<0 RK_PD1 10 &pcfg_pull_up>;
2983		};
2984
2985		/omit-if-no-ref/
2986		uart1m2_ctsn: uart1m2-ctsn {
2987			rockchip,pins =
2988				/* uart1m2_ctsn */
2989				<0 RK_PD0 10 &pcfg_pull_none>;
2990		};
2991
2992		/omit-if-no-ref/
2993		uart1m2_rtsn: uart1m2-rtsn {
2994			rockchip,pins =
2995				/* uart1m2_rtsn */
2996				<0 RK_PC7 10 &pcfg_pull_none>;
2997		};
2998	};
2999
3000	uart2 {
3001		/omit-if-no-ref/
3002		uart2m0_xfer: uart2m0-xfer {
3003			rockchip,pins =
3004				/* uart2_rx_m0 */
3005				<0 RK_PB6 10 &pcfg_pull_up>,
3006				/* uart2_tx_m0 */
3007				<0 RK_PB5 10 &pcfg_pull_up>;
3008		};
3009
3010		/omit-if-no-ref/
3011		uart2m1_xfer: uart2m1-xfer {
3012			rockchip,pins =
3013				/* uart2_rx_m1 */
3014				<4 RK_PD1 10 &pcfg_pull_up>,
3015				/* uart2_tx_m1 */
3016				<4 RK_PD0 10 &pcfg_pull_up>;
3017		};
3018
3019		/omit-if-no-ref/
3020		uart2m2_xfer: uart2m2-xfer {
3021			rockchip,pins =
3022				/* uart2_rx_m2 */
3023				<3 RK_PB2 10 &pcfg_pull_up>,
3024				/* uart2_tx_m2 */
3025				<3 RK_PB1 10 &pcfg_pull_up>;
3026		};
3027
3028		/omit-if-no-ref/
3029		uart2_ctsn: uart2-ctsn {
3030			rockchip,pins =
3031				/* uart2_ctsn */
3032				<3 RK_PB4 10 &pcfg_pull_none>;
3033		};
3034
3035		/omit-if-no-ref/
3036		uart2_rtsn: uart2-rtsn {
3037			rockchip,pins =
3038				/* uart2_rtsn */
3039				<3 RK_PB3 10 &pcfg_pull_none>;
3040		};
3041	};
3042
3043	uart3 {
3044		/omit-if-no-ref/
3045		uart3m0_xfer: uart3m0-xfer {
3046			rockchip,pins =
3047				/* uart3_rx_m0 */
3048				<1 RK_PC0 10 &pcfg_pull_up>,
3049				/* uart3_tx_m0 */
3050				<1 RK_PC1 10 &pcfg_pull_up>;
3051		};
3052
3053		/omit-if-no-ref/
3054		uart3m1_xfer: uart3m1-xfer {
3055			rockchip,pins =
3056				/* uart3_rx_m1 */
3057				<3 RK_PB6 10 &pcfg_pull_up>,
3058				/* uart3_tx_m1 */
3059				<3 RK_PB5 10 &pcfg_pull_up>;
3060		};
3061
3062		/omit-if-no-ref/
3063		uart3m2_xfer: uart3m2-xfer {
3064			rockchip,pins =
3065				/* uart3_rx_m2 */
3066				<4 RK_PA6 10 &pcfg_pull_up>,
3067				/* uart3_tx_m2 */
3068				<4 RK_PA5 10 &pcfg_pull_up>;
3069		};
3070
3071		/omit-if-no-ref/
3072		uart3_ctsn: uart3-ctsn {
3073			rockchip,pins =
3074				/* uart3_ctsn */
3075				<1 RK_PC3 10 &pcfg_pull_none>;
3076		};
3077
3078		/omit-if-no-ref/
3079		uart3_rtsn: uart3-rtsn {
3080			rockchip,pins =
3081				/* uart3_rtsn */
3082				<1 RK_PC2 10 &pcfg_pull_none>;
3083		};
3084	};
3085
3086	uart4 {
3087		/omit-if-no-ref/
3088		uart4m0_xfer: uart4m0-xfer {
3089			rockchip,pins =
3090				/* uart4_rx_m0 */
3091				<1 RK_PD3 10 &pcfg_pull_up>,
3092				/* uart4_tx_m0 */
3093				<1 RK_PD2 10 &pcfg_pull_up>;
3094		};
3095
3096		/omit-if-no-ref/
3097		uart4m1_xfer: uart4m1-xfer {
3098			rockchip,pins =
3099				/* uart4_rx_m1 */
3100				<3 RK_PD0 10 &pcfg_pull_up>,
3101				/* uart4_tx_m1 */
3102				<3 RK_PD1 10 &pcfg_pull_up>;
3103		};
3104
3105		/omit-if-no-ref/
3106		uart4m2_xfer: uart4m2-xfer {
3107			rockchip,pins =
3108				/* uart4_rx_m2 */
3109				<1 RK_PB2 10 &pcfg_pull_up>,
3110				/* uart4_tx_m2 */
3111				<1 RK_PB3 10 &pcfg_pull_up>;
3112		};
3113
3114		/omit-if-no-ref/
3115		uart4_ctsn: uart4-ctsn {
3116			rockchip,pins =
3117				/* uart4_ctsn */
3118				<1 RK_PC7 10 &pcfg_pull_none>;
3119		};
3120
3121		/omit-if-no-ref/
3122		uart4_rtsn: uart4-rtsn {
3123			rockchip,pins =
3124				/* uart4_rtsn */
3125				<1 RK_PC5 10 &pcfg_pull_none>;
3126		};
3127	};
3128
3129	uart5 {
3130		/omit-if-no-ref/
3131		uart5m0_xfer: uart5m0-xfer {
3132			rockchip,pins =
3133				/* uart5_rx_m0 */
3134				<4 RK_PD4 10 &pcfg_pull_up>,
3135				/* uart5_tx_m0 */
3136				<4 RK_PD5 10 &pcfg_pull_up>;
3137		};
3138
3139		/omit-if-no-ref/
3140		uart5m0_ctsn: uart5m0-ctsn {
3141			rockchip,pins =
3142				/* uart5m0_ctsn */
3143				<4 RK_PD2 10 &pcfg_pull_none>;
3144		};
3145
3146		/omit-if-no-ref/
3147		uart5m0_rtsn: uart5m0-rtsn {
3148			rockchip,pins =
3149				/* uart5m0_rtsn */
3150				<4 RK_PD3 10 &pcfg_pull_none>;
3151		};
3152
3153		/omit-if-no-ref/
3154		uart5m1_xfer: uart5m1-xfer {
3155			rockchip,pins =
3156				/* uart5_rx_m1 */
3157				<3 RK_PC5 10 &pcfg_pull_up>,
3158				/* uart5_tx_m1 */
3159				<3 RK_PC4 10 &pcfg_pull_up>;
3160		};
3161
3162		/omit-if-no-ref/
3163		uart5m1_ctsn: uart5m1-ctsn {
3164			rockchip,pins =
3165				/* uart5m1_ctsn */
3166				<2 RK_PA2 10 &pcfg_pull_none>;
3167		};
3168
3169		/omit-if-no-ref/
3170		uart5m1_rtsn: uart5m1-rtsn {
3171			rockchip,pins =
3172				/* uart5m1_rtsn */
3173				<2 RK_PA3 10 &pcfg_pull_none>;
3174		};
3175
3176		/omit-if-no-ref/
3177		uart5m2_xfer: uart5m2-xfer {
3178			rockchip,pins =
3179				/* uart5_rx_m2 */
3180				<2 RK_PD4 10 &pcfg_pull_up>,
3181				/* uart5_tx_m2 */
3182				<2 RK_PD5 10 &pcfg_pull_up>;
3183		};
3184	};
3185
3186	uart6 {
3187		/omit-if-no-ref/
3188		uart6m1_xfer: uart6m1-xfer {
3189			rockchip,pins =
3190				/* uart6_rx_m1 */
3191				<1 RK_PA0 10 &pcfg_pull_up>,
3192				/* uart6_tx_m1 */
3193				<1 RK_PA1 10 &pcfg_pull_up>;
3194		};
3195
3196		/omit-if-no-ref/
3197		uart6m1_ctsn: uart6m1-ctsn {
3198			rockchip,pins =
3199				/* uart6m1_ctsn */
3200				<1 RK_PA3 10 &pcfg_pull_none>;
3201		};
3202
3203		/omit-if-no-ref/
3204		uart6m1_rtsn: uart6m1-rtsn {
3205			rockchip,pins =
3206				/* uart6m1_rtsn */
3207				<1 RK_PA2 10 &pcfg_pull_none>;
3208		};
3209
3210		/omit-if-no-ref/
3211		uart6m2_xfer: uart6m2-xfer {
3212			rockchip,pins =
3213				/* uart6_rx_m2 */
3214				<1 RK_PD1 10 &pcfg_pull_up>,
3215				/* uart6_tx_m2 */
3216				<1 RK_PD0 10 &pcfg_pull_up>;
3217		};
3218	};
3219
3220	uart7 {
3221		/omit-if-no-ref/
3222		uart7m1_xfer: uart7m1-xfer {
3223			rockchip,pins =
3224				/* uart7_rx_m1 */
3225				<3 RK_PC1 10 &pcfg_pull_up>,
3226				/* uart7_tx_m1 */
3227				<3 RK_PC0 10 &pcfg_pull_up>;
3228		};
3229
3230		/omit-if-no-ref/
3231		uart7m1_ctsn: uart7m1-ctsn {
3232			rockchip,pins =
3233				/* uart7m1_ctsn */
3234				<3 RK_PC3 10 &pcfg_pull_none>;
3235		};
3236
3237		/omit-if-no-ref/
3238		uart7m1_rtsn: uart7m1-rtsn {
3239			rockchip,pins =
3240				/* uart7m1_rtsn */
3241				<3 RK_PC2 10 &pcfg_pull_none>;
3242		};
3243
3244		/omit-if-no-ref/
3245		uart7m2_xfer: uart7m2-xfer {
3246			rockchip,pins =
3247				/* uart7_rx_m2 */
3248				<1 RK_PB4 10 &pcfg_pull_up>,
3249				/* uart7_tx_m2 */
3250				<1 RK_PB5 10 &pcfg_pull_up>;
3251		};
3252	};
3253
3254	uart8 {
3255		/omit-if-no-ref/
3256		uart8m0_xfer: uart8m0-xfer {
3257			rockchip,pins =
3258				/* uart8_rx_m0 */
3259				<4 RK_PB1 10 &pcfg_pull_up>,
3260				/* uart8_tx_m0 */
3261				<4 RK_PB0 10 &pcfg_pull_up>;
3262		};
3263
3264		/omit-if-no-ref/
3265		uart8m0_ctsn: uart8m0-ctsn {
3266			rockchip,pins =
3267				/* uart8m0_ctsn */
3268				<4 RK_PB3 10 &pcfg_pull_none>;
3269		};
3270
3271		/omit-if-no-ref/
3272		uart8m0_rtsn: uart8m0-rtsn {
3273			rockchip,pins =
3274				/* uart8m0_rtsn */
3275				<4 RK_PB2 10 &pcfg_pull_none>;
3276		};
3277
3278		/omit-if-no-ref/
3279		uart8m1_xfer: uart8m1-xfer {
3280			rockchip,pins =
3281				/* uart8_rx_m1 */
3282				<3 RK_PA3 10 &pcfg_pull_up>,
3283				/* uart8_tx_m1 */
3284				<3 RK_PA2 10 &pcfg_pull_up>;
3285		};
3286
3287		/omit-if-no-ref/
3288		uart8m1_ctsn: uart8m1-ctsn {
3289			rockchip,pins =
3290				/* uart8m1_ctsn */
3291				<3 RK_PA5 10 &pcfg_pull_none>;
3292		};
3293
3294		/omit-if-no-ref/
3295		uart8m1_rtsn: uart8m1-rtsn {
3296			rockchip,pins =
3297				/* uart8m1_rtsn */
3298				<3 RK_PA4 10 &pcfg_pull_none>;
3299		};
3300
3301		/omit-if-no-ref/
3302		uart8_xfer: uart8-xfer {
3303			rockchip,pins =
3304				/* uart8_rx_ */
3305				<4 RK_PB1 10 &pcfg_pull_up>;
3306		};
3307	};
3308
3309	uart9 {
3310		/omit-if-no-ref/
3311		uart9m1_xfer: uart9m1-xfer {
3312			rockchip,pins =
3313				/* uart9_rx_m1 */
3314				<4 RK_PB5 10 &pcfg_pull_up>,
3315				/* uart9_tx_m1 */
3316				<4 RK_PB4 10 &pcfg_pull_up>;
3317		};
3318
3319		/omit-if-no-ref/
3320		uart9m1_ctsn: uart9m1-ctsn {
3321			rockchip,pins =
3322				/* uart9m1_ctsn */
3323				<4 RK_PA1 10 &pcfg_pull_none>;
3324		};
3325
3326		/omit-if-no-ref/
3327		uart9m1_rtsn: uart9m1-rtsn {
3328			rockchip,pins =
3329				/* uart9m1_rtsn */
3330				<4 RK_PA0 10 &pcfg_pull_none>;
3331		};
3332
3333		/omit-if-no-ref/
3334		uart9m2_xfer: uart9m2-xfer {
3335			rockchip,pins =
3336				/* uart9_rx_m2 */
3337				<3 RK_PD4 10 &pcfg_pull_up>,
3338				/* uart9_tx_m2 */
3339				<3 RK_PD5 10 &pcfg_pull_up>;
3340		};
3341
3342		/omit-if-no-ref/
3343		uart9m2_ctsn: uart9m2-ctsn {
3344			rockchip,pins =
3345				/* uart9m2_ctsn */
3346				<3 RK_PD3 10 &pcfg_pull_none>;
3347		};
3348
3349		/omit-if-no-ref/
3350		uart9m2_rtsn: uart9m2-rtsn {
3351			rockchip,pins =
3352				/* uart9m2_rtsn */
3353				<3 RK_PD2 10 &pcfg_pull_none>;
3354		};
3355	};
3356
3357	vop {
3358		/omit-if-no-ref/
3359		vop_pins: vop-pins {
3360			rockchip,pins =
3361				/* vop_post_empty */
3362				<1 RK_PA2 1 &pcfg_pull_none>;
3363		};
3364	};
3365};
3366
3367/*
3368 * This part is edited handly.
3369 */
3370&pinctrl {
3371	bt656 {
3372		/omit-if-no-ref/
3373		bt656_pins: bt656-pins {
3374			rockchip,pins =
3375				/* bt1120_clkout */
3376				<4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
3377				/* bt1120_d0 */
3378				<4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
3379				/* bt1120_d1 */
3380				<4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
3381				/* bt1120_d2 */
3382				<4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
3383				/* bt1120_d3 */
3384				<4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
3385				/* bt1120_d4 */
3386				<4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
3387				/* bt1120_d5 */
3388				<4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
3389				/* bt1120_d6 */
3390				<4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
3391				/* bt1120_d7 */
3392				<4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
3393		};
3394	};
3395
3396	gpio-func {
3397		/omit-if-no-ref/
3398		tsadc_gpio_func: tsadc-gpio-func {
3399			rockchip,pins =
3400				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
3401		};
3402	};
3403};
3404