xref: /openbmc/linux/drivers/ufs/core/ufshcd.c (revision 7bd9af25)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Universal Flash Storage Host controller driver Core
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6  *
7  * Authors:
8  *	Santosh Yaraganavi <santosh.sy@samsung.com>
9  *	Vinayak Holikatti <h.vinayak@samsung.com>
10  */
11 
12 #include <linux/async.h>
13 #include <linux/devfreq.h>
14 #include <linux/nls.h>
15 #include <linux/of.h>
16 #include <linux/bitfield.h>
17 #include <linux/blk-pm.h>
18 #include <linux/blkdev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sched/clock.h>
25 #include <linux/iopoll.h>
26 #include <scsi/scsi_cmnd.h>
27 #include <scsi/scsi_dbg.h>
28 #include <scsi/scsi_driver.h>
29 #include <scsi/scsi_eh.h>
30 #include "ufshcd-priv.h"
31 #include <ufs/ufs_quirks.h>
32 #include <ufs/unipro.h>
33 #include "ufs-sysfs.h"
34 #include "ufs-debugfs.h"
35 #include "ufs-fault-injection.h"
36 #include "ufs_bsg.h"
37 #include "ufshcd-crypto.h"
38 #include <asm/unaligned.h>
39 
40 #define CREATE_TRACE_POINTS
41 #include <trace/events/ufs.h>
42 
43 #define UFSHCD_ENABLE_INTRS	(UTP_TRANSFER_REQ_COMPL |\
44 				 UTP_TASK_REQ_COMPL |\
45 				 UFSHCD_ERROR_MASK)
46 
47 #define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\
48 				 UFSHCD_ERROR_MASK |\
49 				 MCQ_CQ_EVENT_STATUS)
50 
51 
52 /* UIC command timeout, unit: ms */
53 #define UIC_CMD_TIMEOUT	500
54 
55 /* NOP OUT retries waiting for NOP IN response */
56 #define NOP_OUT_RETRIES    10
57 /* Timeout after 50 msecs if NOP OUT hangs without response */
58 #define NOP_OUT_TIMEOUT    50 /* msecs */
59 
60 /* Query request retries */
61 #define QUERY_REQ_RETRIES 3
62 /* Query request timeout */
63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
64 
65 /* Advanced RPMB request timeout */
66 #define ADVANCED_RPMB_REQ_TIMEOUT  3000 /* 3 seconds */
67 
68 /* Task management command timeout */
69 #define TM_CMD_TIMEOUT	100 /* msecs */
70 
71 /* maximum number of retries for a general UIC command  */
72 #define UFS_UIC_COMMAND_RETRIES 3
73 
74 /* maximum number of link-startup retries */
75 #define DME_LINKSTARTUP_RETRIES 3
76 
77 /* maximum number of reset retries before giving up */
78 #define MAX_HOST_RESET_RETRIES 5
79 
80 /* Maximum number of error handler retries before giving up */
81 #define MAX_ERR_HANDLER_RETRIES 5
82 
83 /* Expose the flag value from utp_upiu_query.value */
84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
85 
86 /* Interrupt aggregation default timeout, unit: 40us */
87 #define INT_AGGR_DEF_TO	0x02
88 
89 /* default delay of autosuspend: 2000 ms */
90 #define RPM_AUTOSUSPEND_DELAY_MS 2000
91 
92 /* Default delay of RPM device flush delayed work */
93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
94 
95 /* Default value of wait time before gating device ref clock */
96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
97 
98 /* Polling time to wait for fDeviceInit */
99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
100 
101 /* UFSHC 4.0 compliant HC support this mode. */
102 static bool use_mcq_mode = true;
103 
is_mcq_supported(struct ufs_hba * hba)104 static bool is_mcq_supported(struct ufs_hba *hba)
105 {
106 	return hba->mcq_sup && use_mcq_mode;
107 }
108 
109 module_param(use_mcq_mode, bool, 0644);
110 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
111 
112 #define ufshcd_toggle_vreg(_dev, _vreg, _on)				\
113 	({                                                              \
114 		int _ret;                                               \
115 		if (_on)                                                \
116 			_ret = ufshcd_enable_vreg(_dev, _vreg);         \
117 		else                                                    \
118 			_ret = ufshcd_disable_vreg(_dev, _vreg);        \
119 		_ret;                                                   \
120 	})
121 
122 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
123 	size_t __len = (len);                                            \
124 	print_hex_dump(KERN_ERR, prefix_str,                             \
125 		       __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
126 		       16, 4, buf, __len, false);                        \
127 } while (0)
128 
ufshcd_dump_regs(struct ufs_hba * hba,size_t offset,size_t len,const char * prefix)129 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
130 		     const char *prefix)
131 {
132 	u32 *regs;
133 	size_t pos;
134 
135 	if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
136 		return -EINVAL;
137 
138 	regs = kzalloc(len, GFP_ATOMIC);
139 	if (!regs)
140 		return -ENOMEM;
141 
142 	for (pos = 0; pos < len; pos += 4) {
143 		if (offset == 0 &&
144 		    pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
145 		    pos <= REG_UIC_ERROR_CODE_DME)
146 			continue;
147 		regs[pos / 4] = ufshcd_readl(hba, offset + pos);
148 	}
149 
150 	ufshcd_hex_dump(prefix, regs, len);
151 	kfree(regs);
152 
153 	return 0;
154 }
155 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
156 
157 enum {
158 	UFSHCD_MAX_CHANNEL	= 0,
159 	UFSHCD_MAX_ID		= 1,
160 	UFSHCD_CMD_PER_LUN	= 32 - UFSHCD_NUM_RESERVED,
161 	UFSHCD_CAN_QUEUE	= 32 - UFSHCD_NUM_RESERVED,
162 };
163 
164 static const char *const ufshcd_state_name[] = {
165 	[UFSHCD_STATE_RESET]			= "reset",
166 	[UFSHCD_STATE_OPERATIONAL]		= "operational",
167 	[UFSHCD_STATE_ERROR]			= "error",
168 	[UFSHCD_STATE_EH_SCHEDULED_FATAL]	= "eh_fatal",
169 	[UFSHCD_STATE_EH_SCHEDULED_NON_FATAL]	= "eh_non_fatal",
170 };
171 
172 /* UFSHCD error handling flags */
173 enum {
174 	UFSHCD_EH_IN_PROGRESS = (1 << 0),
175 };
176 
177 /* UFSHCD UIC layer error flags */
178 enum {
179 	UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
180 	UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
181 	UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
182 	UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
183 	UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
184 	UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
185 	UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
186 };
187 
188 #define ufshcd_set_eh_in_progress(h) \
189 	((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
190 #define ufshcd_eh_in_progress(h) \
191 	((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
192 #define ufshcd_clear_eh_in_progress(h) \
193 	((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
194 
195 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
196 	[UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
197 	[UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
198 	[UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
199 	[UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
200 	[UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
201 	[UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
202 	/*
203 	 * For DeepSleep, the link is first put in hibern8 and then off.
204 	 * Leaving the link in hibern8 is not supported.
205 	 */
206 	[UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
207 };
208 
209 static inline enum ufs_dev_pwr_mode
ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)210 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
211 {
212 	return ufs_pm_lvl_states[lvl].dev_state;
213 }
214 
215 static inline enum uic_link_state
ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)216 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
217 {
218 	return ufs_pm_lvl_states[lvl].link_state;
219 }
220 
221 static inline enum ufs_pm_level
ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,enum uic_link_state link_state)222 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
223 					enum uic_link_state link_state)
224 {
225 	enum ufs_pm_level lvl;
226 
227 	for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
228 		if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
229 			(ufs_pm_lvl_states[lvl].link_state == link_state))
230 			return lvl;
231 	}
232 
233 	/* if no match found, return the level 0 */
234 	return UFS_PM_LVL_0;
235 }
236 
237 static const struct ufs_dev_quirk ufs_fixups[] = {
238 	/* UFS cards deviations table */
239 	{ .wmanufacturerid = UFS_VENDOR_MICRON,
240 	  .model = UFS_ANY_MODEL,
241 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
242 	{ .wmanufacturerid = UFS_VENDOR_SAMSUNG,
243 	  .model = UFS_ANY_MODEL,
244 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
245 		   UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
246 		   UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
247 	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
248 	  .model = UFS_ANY_MODEL,
249 	  .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
250 	{ .wmanufacturerid = UFS_VENDOR_SKHYNIX,
251 	  .model = "hB8aL1" /*H28U62301AMR*/,
252 	  .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
253 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
254 	  .model = UFS_ANY_MODEL,
255 	  .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
256 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
257 	  .model = "THGLF2G9C8KBADG",
258 	  .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
259 	{ .wmanufacturerid = UFS_VENDOR_TOSHIBA,
260 	  .model = "THGLF2G9D8KBADG",
261 	  .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
262 	{}
263 };
264 
265 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
266 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
267 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
268 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
269 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
270 static void ufshcd_hba_exit(struct ufs_hba *hba);
271 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
272 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
273 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
274 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
275 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
276 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
277 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
278 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
279 static irqreturn_t ufshcd_intr(int irq, void *__hba);
280 static int ufshcd_change_power_mode(struct ufs_hba *hba,
281 			     struct ufs_pa_layer_attr *pwr_mode);
282 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
283 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
284 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
285 					 struct ufs_vreg *vreg);
286 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
287 						 bool enable);
288 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
289 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
290 
ufshcd_enable_irq(struct ufs_hba * hba)291 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
292 {
293 	if (!hba->is_irq_enabled) {
294 		enable_irq(hba->irq);
295 		hba->is_irq_enabled = true;
296 	}
297 }
298 
ufshcd_disable_irq(struct ufs_hba * hba)299 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
300 {
301 	if (hba->is_irq_enabled) {
302 		disable_irq(hba->irq);
303 		hba->is_irq_enabled = false;
304 	}
305 }
306 
ufshcd_configure_wb(struct ufs_hba * hba)307 static void ufshcd_configure_wb(struct ufs_hba *hba)
308 {
309 	if (!ufshcd_is_wb_allowed(hba))
310 		return;
311 
312 	ufshcd_wb_toggle(hba, true);
313 
314 	ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
315 
316 	if (ufshcd_is_wb_buf_flush_allowed(hba))
317 		ufshcd_wb_toggle_buf_flush(hba, true);
318 }
319 
ufshcd_scsi_unblock_requests(struct ufs_hba * hba)320 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
321 {
322 	if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
323 		scsi_unblock_requests(hba->host);
324 }
325 
ufshcd_scsi_block_requests(struct ufs_hba * hba)326 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
327 {
328 	if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
329 		scsi_block_requests(hba->host);
330 }
331 
ufshcd_add_cmd_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)332 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
333 				      enum ufs_trace_str_t str_t)
334 {
335 	struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
336 	struct utp_upiu_header *header;
337 
338 	if (!trace_ufshcd_upiu_enabled())
339 		return;
340 
341 	if (str_t == UFS_CMD_SEND)
342 		header = &rq->header;
343 	else
344 		header = &hba->lrb[tag].ucd_rsp_ptr->header;
345 
346 	trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
347 			  UFS_TSF_CDB);
348 }
349 
ufshcd_add_query_upiu_trace(struct ufs_hba * hba,enum ufs_trace_str_t str_t,struct utp_upiu_req * rq_rsp)350 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
351 					enum ufs_trace_str_t str_t,
352 					struct utp_upiu_req *rq_rsp)
353 {
354 	if (!trace_ufshcd_upiu_enabled())
355 		return;
356 
357 	trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
358 			  &rq_rsp->qr, UFS_TSF_OSF);
359 }
360 
ufshcd_add_tm_upiu_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)361 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
362 				     enum ufs_trace_str_t str_t)
363 {
364 	struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
365 
366 	if (!trace_ufshcd_upiu_enabled())
367 		return;
368 
369 	if (str_t == UFS_TM_SEND)
370 		trace_ufshcd_upiu(dev_name(hba->dev), str_t,
371 				  &descp->upiu_req.req_header,
372 				  &descp->upiu_req.input_param1,
373 				  UFS_TSF_TM_INPUT);
374 	else
375 		trace_ufshcd_upiu(dev_name(hba->dev), str_t,
376 				  &descp->upiu_rsp.rsp_header,
377 				  &descp->upiu_rsp.output_param1,
378 				  UFS_TSF_TM_OUTPUT);
379 }
380 
ufshcd_add_uic_command_trace(struct ufs_hba * hba,const struct uic_command * ucmd,enum ufs_trace_str_t str_t)381 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
382 					 const struct uic_command *ucmd,
383 					 enum ufs_trace_str_t str_t)
384 {
385 	u32 cmd;
386 
387 	if (!trace_ufshcd_uic_command_enabled())
388 		return;
389 
390 	if (str_t == UFS_CMD_SEND)
391 		cmd = ucmd->command;
392 	else
393 		cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
394 
395 	trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
396 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
397 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
398 				 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
399 }
400 
ufshcd_add_command_trace(struct ufs_hba * hba,unsigned int tag,enum ufs_trace_str_t str_t)401 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
402 				     enum ufs_trace_str_t str_t)
403 {
404 	u64 lba = 0;
405 	u8 opcode = 0, group_id = 0;
406 	u32 doorbell = 0;
407 	u32 intr;
408 	int hwq_id = -1;
409 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
410 	struct scsi_cmnd *cmd = lrbp->cmd;
411 	struct request *rq = scsi_cmd_to_rq(cmd);
412 	int transfer_len = -1;
413 
414 	if (!cmd)
415 		return;
416 
417 	/* trace UPIU also */
418 	ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
419 	if (!trace_ufshcd_command_enabled())
420 		return;
421 
422 	opcode = cmd->cmnd[0];
423 
424 	if (opcode == READ_10 || opcode == WRITE_10) {
425 		/*
426 		 * Currently we only fully trace read(10) and write(10) commands
427 		 */
428 		transfer_len =
429 		       be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
430 		lba = scsi_get_lba(cmd);
431 		if (opcode == WRITE_10)
432 			group_id = lrbp->cmd->cmnd[6];
433 	} else if (opcode == UNMAP) {
434 		/*
435 		 * The number of Bytes to be unmapped beginning with the lba.
436 		 */
437 		transfer_len = blk_rq_bytes(rq);
438 		lba = scsi_get_lba(cmd);
439 	}
440 
441 	intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
442 
443 	if (is_mcq_enabled(hba)) {
444 		struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq);
445 
446 		hwq_id = hwq->id;
447 	} else {
448 		doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
449 	}
450 	trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
451 			doorbell, hwq_id, transfer_len, intr, lba, opcode, group_id);
452 }
453 
ufshcd_print_clk_freqs(struct ufs_hba * hba)454 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
455 {
456 	struct ufs_clk_info *clki;
457 	struct list_head *head = &hba->clk_list_head;
458 
459 	if (list_empty(head))
460 		return;
461 
462 	list_for_each_entry(clki, head, list) {
463 		if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
464 				clki->max_freq)
465 			dev_err(hba->dev, "clk: %s, rate: %u\n",
466 					clki->name, clki->curr_freq);
467 	}
468 }
469 
ufshcd_print_evt(struct ufs_hba * hba,u32 id,const char * err_name)470 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
471 			     const char *err_name)
472 {
473 	int i;
474 	bool found = false;
475 	const struct ufs_event_hist *e;
476 
477 	if (id >= UFS_EVT_CNT)
478 		return;
479 
480 	e = &hba->ufs_stats.event[id];
481 
482 	for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
483 		int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
484 
485 		if (e->tstamp[p] == 0)
486 			continue;
487 		dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
488 			e->val[p], div_u64(e->tstamp[p], 1000));
489 		found = true;
490 	}
491 
492 	if (!found)
493 		dev_err(hba->dev, "No record of %s\n", err_name);
494 	else
495 		dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
496 }
497 
ufshcd_print_evt_hist(struct ufs_hba * hba)498 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
499 {
500 	ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
501 
502 	ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
503 	ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
504 	ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
505 	ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
506 	ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
507 	ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
508 			 "auto_hibern8_err");
509 	ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
510 	ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
511 			 "link_startup_fail");
512 	ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
513 	ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
514 			 "suspend_fail");
515 	ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
516 	ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
517 			 "wlun suspend_fail");
518 	ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
519 	ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
520 	ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
521 
522 	ufshcd_vops_dbg_register_dump(hba);
523 }
524 
525 static
ufshcd_print_tr(struct ufs_hba * hba,int tag,bool pr_prdt)526 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt)
527 {
528 	const struct ufshcd_lrb *lrbp;
529 	int prdt_length;
530 
531 	lrbp = &hba->lrb[tag];
532 
533 	dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
534 			tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
535 	dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
536 			tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
537 	dev_err(hba->dev,
538 		"UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
539 		tag, (u64)lrbp->utrd_dma_addr);
540 
541 	ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
542 			sizeof(struct utp_transfer_req_desc));
543 	dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
544 		(u64)lrbp->ucd_req_dma_addr);
545 	ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
546 			sizeof(struct utp_upiu_req));
547 	dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
548 		(u64)lrbp->ucd_rsp_dma_addr);
549 	ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
550 			sizeof(struct utp_upiu_rsp));
551 
552 	prdt_length = le16_to_cpu(
553 		lrbp->utr_descriptor_ptr->prd_table_length);
554 	if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
555 		prdt_length /= ufshcd_sg_entry_size(hba);
556 
557 	dev_err(hba->dev,
558 		"UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
559 		tag, prdt_length,
560 		(u64)lrbp->ucd_prdt_dma_addr);
561 
562 	if (pr_prdt)
563 		ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
564 			ufshcd_sg_entry_size(hba) * prdt_length);
565 }
566 
ufshcd_print_tr_iter(struct request * req,void * priv)567 static bool ufshcd_print_tr_iter(struct request *req, void *priv)
568 {
569 	struct scsi_device *sdev = req->q->queuedata;
570 	struct Scsi_Host *shost = sdev->host;
571 	struct ufs_hba *hba = shost_priv(shost);
572 
573 	ufshcd_print_tr(hba, req->tag, *(bool *)priv);
574 
575 	return true;
576 }
577 
578 /**
579  * ufshcd_print_trs_all - print trs for all started requests.
580  * @hba: per-adapter instance.
581  * @pr_prdt: need to print prdt or not.
582  */
ufshcd_print_trs_all(struct ufs_hba * hba,bool pr_prdt)583 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt)
584 {
585 	blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt);
586 }
587 
ufshcd_print_tmrs(struct ufs_hba * hba,unsigned long bitmap)588 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
589 {
590 	int tag;
591 
592 	for_each_set_bit(tag, &bitmap, hba->nutmrs) {
593 		struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
594 
595 		dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
596 		ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
597 	}
598 }
599 
ufshcd_print_host_state(struct ufs_hba * hba)600 static void ufshcd_print_host_state(struct ufs_hba *hba)
601 {
602 	const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
603 
604 	dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
605 	dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
606 		hba->outstanding_reqs, hba->outstanding_tasks);
607 	dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
608 		hba->saved_err, hba->saved_uic_err);
609 	dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
610 		hba->curr_dev_pwr_mode, hba->uic_link_state);
611 	dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
612 		hba->pm_op_in_progress, hba->is_sys_suspended);
613 	dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
614 		hba->auto_bkops_enabled, hba->host->host_self_blocked);
615 	dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
616 	dev_err(hba->dev,
617 		"last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
618 		div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
619 		hba->ufs_stats.hibern8_exit_cnt);
620 	dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
621 		div_u64(hba->ufs_stats.last_intr_ts, 1000),
622 		hba->ufs_stats.last_intr_status);
623 	dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
624 		hba->eh_flags, hba->req_abort_count);
625 	dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
626 		hba->ufs_version, hba->capabilities, hba->caps);
627 	dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
628 		hba->dev_quirks);
629 	if (sdev_ufs)
630 		dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
631 			sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
632 
633 	ufshcd_print_clk_freqs(hba);
634 }
635 
636 /**
637  * ufshcd_print_pwr_info - print power params as saved in hba
638  * power info
639  * @hba: per-adapter instance
640  */
ufshcd_print_pwr_info(struct ufs_hba * hba)641 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
642 {
643 	static const char * const names[] = {
644 		"INVALID MODE",
645 		"FAST MODE",
646 		"SLOW_MODE",
647 		"INVALID MODE",
648 		"FASTAUTO_MODE",
649 		"SLOWAUTO_MODE",
650 		"INVALID MODE",
651 	};
652 
653 	/*
654 	 * Using dev_dbg to avoid messages during runtime PM to avoid
655 	 * never-ending cycles of messages written back to storage by user space
656 	 * causing runtime resume, causing more messages and so on.
657 	 */
658 	dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
659 		 __func__,
660 		 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
661 		 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
662 		 names[hba->pwr_info.pwr_rx],
663 		 names[hba->pwr_info.pwr_tx],
664 		 hba->pwr_info.hs_rate);
665 }
666 
ufshcd_device_reset(struct ufs_hba * hba)667 static void ufshcd_device_reset(struct ufs_hba *hba)
668 {
669 	int err;
670 
671 	err = ufshcd_vops_device_reset(hba);
672 
673 	if (!err) {
674 		ufshcd_set_ufs_dev_active(hba);
675 		if (ufshcd_is_wb_allowed(hba)) {
676 			hba->dev_info.wb_enabled = false;
677 			hba->dev_info.wb_buf_flush_enabled = false;
678 		}
679 	}
680 	if (err != -EOPNOTSUPP)
681 		ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
682 }
683 
ufshcd_delay_us(unsigned long us,unsigned long tolerance)684 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
685 {
686 	if (!us)
687 		return;
688 
689 	if (us < 10)
690 		udelay(us);
691 	else
692 		usleep_range(us, us + tolerance);
693 }
694 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
695 
696 /**
697  * ufshcd_wait_for_register - wait for register value to change
698  * @hba: per-adapter interface
699  * @reg: mmio register offset
700  * @mask: mask to apply to the read register value
701  * @val: value to wait for
702  * @interval_us: polling interval in microseconds
703  * @timeout_ms: timeout in milliseconds
704  *
705  * Return: -ETIMEDOUT on error, zero on success.
706  */
ufshcd_wait_for_register(struct ufs_hba * hba,u32 reg,u32 mask,u32 val,unsigned long interval_us,unsigned long timeout_ms)707 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
708 				u32 val, unsigned long interval_us,
709 				unsigned long timeout_ms)
710 {
711 	int err = 0;
712 	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
713 
714 	/* ignore bits that we don't intend to wait on */
715 	val = val & mask;
716 
717 	while ((ufshcd_readl(hba, reg) & mask) != val) {
718 		usleep_range(interval_us, interval_us + 50);
719 		if (time_after(jiffies, timeout)) {
720 			if ((ufshcd_readl(hba, reg) & mask) != val)
721 				err = -ETIMEDOUT;
722 			break;
723 		}
724 	}
725 
726 	return err;
727 }
728 
729 /**
730  * ufshcd_get_intr_mask - Get the interrupt bit mask
731  * @hba: Pointer to adapter instance
732  *
733  * Return: interrupt bit mask per version
734  */
ufshcd_get_intr_mask(struct ufs_hba * hba)735 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
736 {
737 	if (hba->ufs_version == ufshci_version(1, 0))
738 		return INTERRUPT_MASK_ALL_VER_10;
739 	if (hba->ufs_version <= ufshci_version(2, 0))
740 		return INTERRUPT_MASK_ALL_VER_11;
741 
742 	return INTERRUPT_MASK_ALL_VER_21;
743 }
744 
745 /**
746  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
747  * @hba: Pointer to adapter instance
748  *
749  * Return: UFSHCI version supported by the controller
750  */
ufshcd_get_ufs_version(struct ufs_hba * hba)751 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
752 {
753 	u32 ufshci_ver;
754 
755 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
756 		ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
757 	else
758 		ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
759 
760 	/*
761 	 * UFSHCI v1.x uses a different version scheme, in order
762 	 * to allow the use of comparisons with the ufshci_version
763 	 * function, we convert it to the same scheme as ufs 2.0+.
764 	 */
765 	if (ufshci_ver & 0x00010000)
766 		return ufshci_version(1, ufshci_ver & 0x00000100);
767 
768 	return ufshci_ver;
769 }
770 
771 /**
772  * ufshcd_is_device_present - Check if any device connected to
773  *			      the host controller
774  * @hba: pointer to adapter instance
775  *
776  * Return: true if device present, false if no device detected
777  */
ufshcd_is_device_present(struct ufs_hba * hba)778 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
779 {
780 	return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
781 }
782 
783 /**
784  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
785  * @lrbp: pointer to local command reference block
786  * @cqe: pointer to the completion queue entry
787  *
788  * This function is used to get the OCS field from UTRD
789  *
790  * Return: the OCS field in the UTRD.
791  */
ufshcd_get_tr_ocs(struct ufshcd_lrb * lrbp,struct cq_entry * cqe)792 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
793 				      struct cq_entry *cqe)
794 {
795 	if (cqe)
796 		return le32_to_cpu(cqe->status) & MASK_OCS;
797 
798 	return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS;
799 }
800 
801 /**
802  * ufshcd_utrl_clear() - Clear requests from the controller request list.
803  * @hba: per adapter instance
804  * @mask: mask with one bit set for each request to be cleared
805  */
ufshcd_utrl_clear(struct ufs_hba * hba,u32 mask)806 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
807 {
808 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
809 		mask = ~mask;
810 	/*
811 	 * From the UFSHCI specification: "UTP Transfer Request List CLear
812 	 * Register (UTRLCLR): This field is bit significant. Each bit
813 	 * corresponds to a slot in the UTP Transfer Request List, where bit 0
814 	 * corresponds to request slot 0. A bit in this field is set to ‘0’
815 	 * by host software to indicate to the host controller that a transfer
816 	 * request slot is cleared. The host controller
817 	 * shall free up any resources associated to the request slot
818 	 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
819 	 * host software indicates no change to request slots by setting the
820 	 * associated bits in this field to ‘1’. Bits in this field shall only
821 	 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
822 	 */
823 	ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
824 }
825 
826 /**
827  * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
828  * @hba: per adapter instance
829  * @pos: position of the bit to be cleared
830  */
ufshcd_utmrl_clear(struct ufs_hba * hba,u32 pos)831 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
832 {
833 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
834 		ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
835 	else
836 		ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
837 }
838 
839 /**
840  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
841  * @reg: Register value of host controller status
842  *
843  * Return: 0 on success; a positive value if failed.
844  */
ufshcd_get_lists_status(u32 reg)845 static inline int ufshcd_get_lists_status(u32 reg)
846 {
847 	return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
848 }
849 
850 /**
851  * ufshcd_get_uic_cmd_result - Get the UIC command result
852  * @hba: Pointer to adapter instance
853  *
854  * This function gets the result of UIC command completion
855  *
856  * Return: 0 on success; non-zero value on error.
857  */
ufshcd_get_uic_cmd_result(struct ufs_hba * hba)858 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
859 {
860 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
861 	       MASK_UIC_COMMAND_RESULT;
862 }
863 
864 /**
865  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
866  * @hba: Pointer to adapter instance
867  *
868  * This function gets UIC command argument3
869  *
870  * Return: 0 on success; non-zero value on error.
871  */
ufshcd_get_dme_attr_val(struct ufs_hba * hba)872 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
873 {
874 	return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
875 }
876 
877 /**
878  * ufshcd_get_req_rsp - returns the TR response transaction type
879  * @ucd_rsp_ptr: pointer to response UPIU
880  *
881  * Return: UPIU type.
882  */
883 static inline enum upiu_response_transaction
ufshcd_get_req_rsp(struct utp_upiu_rsp * ucd_rsp_ptr)884 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
885 {
886 	return ucd_rsp_ptr->header.transaction_code;
887 }
888 
889 /**
890  * ufshcd_is_exception_event - Check if the device raised an exception event
891  * @ucd_rsp_ptr: pointer to response UPIU
892  *
893  * The function checks if the device raised an exception event indicated in
894  * the Device Information field of response UPIU.
895  *
896  * Return: true if exception is raised, false otherwise.
897  */
ufshcd_is_exception_event(struct utp_upiu_rsp * ucd_rsp_ptr)898 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
899 {
900 	return ucd_rsp_ptr->header.device_information & 1;
901 }
902 
903 /**
904  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
905  * @hba: per adapter instance
906  */
907 static inline void
ufshcd_reset_intr_aggr(struct ufs_hba * hba)908 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
909 {
910 	ufshcd_writel(hba, INT_AGGR_ENABLE |
911 		      INT_AGGR_COUNTER_AND_TIMER_RESET,
912 		      REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
913 }
914 
915 /**
916  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
917  * @hba: per adapter instance
918  * @cnt: Interrupt aggregation counter threshold
919  * @tmout: Interrupt aggregation timeout value
920  */
921 static inline void
ufshcd_config_intr_aggr(struct ufs_hba * hba,u8 cnt,u8 tmout)922 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
923 {
924 	ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
925 		      INT_AGGR_COUNTER_THLD_VAL(cnt) |
926 		      INT_AGGR_TIMEOUT_VAL(tmout),
927 		      REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
928 }
929 
930 /**
931  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
932  * @hba: per adapter instance
933  */
ufshcd_disable_intr_aggr(struct ufs_hba * hba)934 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
935 {
936 	ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
937 }
938 
939 /**
940  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
941  *			When run-stop registers are set to 1, it indicates the
942  *			host controller that it can process the requests
943  * @hba: per adapter instance
944  */
ufshcd_enable_run_stop_reg(struct ufs_hba * hba)945 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
946 {
947 	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
948 		      REG_UTP_TASK_REQ_LIST_RUN_STOP);
949 	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
950 		      REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
951 }
952 
953 /**
954  * ufshcd_hba_start - Start controller initialization sequence
955  * @hba: per adapter instance
956  */
ufshcd_hba_start(struct ufs_hba * hba)957 static inline void ufshcd_hba_start(struct ufs_hba *hba)
958 {
959 	u32 val = CONTROLLER_ENABLE;
960 
961 	if (ufshcd_crypto_enable(hba))
962 		val |= CRYPTO_GENERAL_ENABLE;
963 
964 	ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
965 }
966 
967 /**
968  * ufshcd_is_hba_active - Get controller state
969  * @hba: per adapter instance
970  *
971  * Return: true if and only if the controller is active.
972  */
ufshcd_is_hba_active(struct ufs_hba * hba)973 bool ufshcd_is_hba_active(struct ufs_hba *hba)
974 {
975 	return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
976 }
977 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active);
978 
ufshcd_get_local_unipro_ver(struct ufs_hba * hba)979 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
980 {
981 	/* HCI version 1.0 and 1.1 supports UniPro 1.41 */
982 	if (hba->ufs_version <= ufshci_version(1, 1))
983 		return UFS_UNIPRO_VER_1_41;
984 	else
985 		return UFS_UNIPRO_VER_1_6;
986 }
987 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
988 
ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba * hba)989 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
990 {
991 	/*
992 	 * If both host and device support UniPro ver1.6 or later, PA layer
993 	 * parameters tuning happens during link startup itself.
994 	 *
995 	 * We can manually tune PA layer parameters if either host or device
996 	 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
997 	 * logic simple, we will only do manual tuning if local unipro version
998 	 * doesn't support ver1.6 or later.
999 	 */
1000 	return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
1001 }
1002 
1003 /**
1004  * ufshcd_set_clk_freq - set UFS controller clock frequencies
1005  * @hba: per adapter instance
1006  * @scale_up: If True, set max possible frequency othewise set low frequency
1007  *
1008  * Return: 0 if successful; < 0 upon failure.
1009  */
ufshcd_set_clk_freq(struct ufs_hba * hba,bool scale_up)1010 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1011 {
1012 	int ret = 0;
1013 	struct ufs_clk_info *clki;
1014 	struct list_head *head = &hba->clk_list_head;
1015 
1016 	if (list_empty(head))
1017 		goto out;
1018 
1019 	list_for_each_entry(clki, head, list) {
1020 		if (!IS_ERR_OR_NULL(clki->clk)) {
1021 			if (scale_up && clki->max_freq) {
1022 				if (clki->curr_freq == clki->max_freq)
1023 					continue;
1024 
1025 				ret = clk_set_rate(clki->clk, clki->max_freq);
1026 				if (ret) {
1027 					dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1028 						__func__, clki->name,
1029 						clki->max_freq, ret);
1030 					break;
1031 				}
1032 				trace_ufshcd_clk_scaling(dev_name(hba->dev),
1033 						"scaled up", clki->name,
1034 						clki->curr_freq,
1035 						clki->max_freq);
1036 
1037 				clki->curr_freq = clki->max_freq;
1038 
1039 			} else if (!scale_up && clki->min_freq) {
1040 				if (clki->curr_freq == clki->min_freq)
1041 					continue;
1042 
1043 				ret = clk_set_rate(clki->clk, clki->min_freq);
1044 				if (ret) {
1045 					dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1046 						__func__, clki->name,
1047 						clki->min_freq, ret);
1048 					break;
1049 				}
1050 				trace_ufshcd_clk_scaling(dev_name(hba->dev),
1051 						"scaled down", clki->name,
1052 						clki->curr_freq,
1053 						clki->min_freq);
1054 				clki->curr_freq = clki->min_freq;
1055 			}
1056 		}
1057 		dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1058 				clki->name, clk_get_rate(clki->clk));
1059 	}
1060 
1061 out:
1062 	return ret;
1063 }
1064 
1065 /**
1066  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1067  * @hba: per adapter instance
1068  * @scale_up: True if scaling up and false if scaling down
1069  *
1070  * Return: 0 if successful; < 0 upon failure.
1071  */
ufshcd_scale_clks(struct ufs_hba * hba,bool scale_up)1072 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1073 {
1074 	int ret = 0;
1075 	ktime_t start = ktime_get();
1076 
1077 	ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1078 	if (ret)
1079 		goto out;
1080 
1081 	ret = ufshcd_set_clk_freq(hba, scale_up);
1082 	if (ret)
1083 		goto out;
1084 
1085 	ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1086 	if (ret)
1087 		ufshcd_set_clk_freq(hba, !scale_up);
1088 
1089 out:
1090 	trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1091 			(scale_up ? "up" : "down"),
1092 			ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1093 	return ret;
1094 }
1095 
1096 /**
1097  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1098  * @hba: per adapter instance
1099  * @scale_up: True if scaling up and false if scaling down
1100  *
1101  * Return: true if scaling is required, false otherwise.
1102  */
ufshcd_is_devfreq_scaling_required(struct ufs_hba * hba,bool scale_up)1103 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1104 					       bool scale_up)
1105 {
1106 	struct ufs_clk_info *clki;
1107 	struct list_head *head = &hba->clk_list_head;
1108 
1109 	if (list_empty(head))
1110 		return false;
1111 
1112 	list_for_each_entry(clki, head, list) {
1113 		if (!IS_ERR_OR_NULL(clki->clk)) {
1114 			if (scale_up && clki->max_freq) {
1115 				if (clki->curr_freq == clki->max_freq)
1116 					continue;
1117 				return true;
1118 			} else if (!scale_up && clki->min_freq) {
1119 				if (clki->curr_freq == clki->min_freq)
1120 					continue;
1121 				return true;
1122 			}
1123 		}
1124 	}
1125 
1126 	return false;
1127 }
1128 
1129 /*
1130  * Determine the number of pending commands by counting the bits in the SCSI
1131  * device budget maps. This approach has been selected because a bit is set in
1132  * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1133  * flag. The host_self_blocked flag can be modified by calling
1134  * scsi_block_requests() or scsi_unblock_requests().
1135  */
ufshcd_pending_cmds(struct ufs_hba * hba)1136 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1137 {
1138 	const struct scsi_device *sdev;
1139 	u32 pending = 0;
1140 
1141 	lockdep_assert_held(hba->host->host_lock);
1142 	__shost_for_each_device(sdev, hba->host)
1143 		pending += sbitmap_weight(&sdev->budget_map);
1144 
1145 	return pending;
1146 }
1147 
1148 /*
1149  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1150  * has expired.
1151  *
1152  * Return: 0 upon success; -EBUSY upon timeout.
1153  */
ufshcd_wait_for_doorbell_clr(struct ufs_hba * hba,u64 wait_timeout_us)1154 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1155 					u64 wait_timeout_us)
1156 {
1157 	unsigned long flags;
1158 	int ret = 0;
1159 	u32 tm_doorbell;
1160 	u32 tr_pending;
1161 	bool timeout = false, do_last_check = false;
1162 	ktime_t start;
1163 
1164 	ufshcd_hold(hba);
1165 	spin_lock_irqsave(hba->host->host_lock, flags);
1166 	/*
1167 	 * Wait for all the outstanding tasks/transfer requests.
1168 	 * Verify by checking the doorbell registers are clear.
1169 	 */
1170 	start = ktime_get();
1171 	do {
1172 		if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1173 			ret = -EBUSY;
1174 			goto out;
1175 		}
1176 
1177 		tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1178 		tr_pending = ufshcd_pending_cmds(hba);
1179 		if (!tm_doorbell && !tr_pending) {
1180 			timeout = false;
1181 			break;
1182 		} else if (do_last_check) {
1183 			break;
1184 		}
1185 
1186 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1187 		io_schedule_timeout(msecs_to_jiffies(20));
1188 		if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1189 		    wait_timeout_us) {
1190 			timeout = true;
1191 			/*
1192 			 * We might have scheduled out for long time so make
1193 			 * sure to check if doorbells are cleared by this time
1194 			 * or not.
1195 			 */
1196 			do_last_check = true;
1197 		}
1198 		spin_lock_irqsave(hba->host->host_lock, flags);
1199 	} while (tm_doorbell || tr_pending);
1200 
1201 	if (timeout) {
1202 		dev_err(hba->dev,
1203 			"%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1204 			__func__, tm_doorbell, tr_pending);
1205 		ret = -EBUSY;
1206 	}
1207 out:
1208 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1209 	ufshcd_release(hba);
1210 	return ret;
1211 }
1212 
1213 /**
1214  * ufshcd_scale_gear - scale up/down UFS gear
1215  * @hba: per adapter instance
1216  * @scale_up: True for scaling up gear and false for scaling down
1217  *
1218  * Return: 0 for success; -EBUSY if scaling can't happen at this time;
1219  * non-zero for any other errors.
1220  */
ufshcd_scale_gear(struct ufs_hba * hba,bool scale_up)1221 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1222 {
1223 	int ret = 0;
1224 	struct ufs_pa_layer_attr new_pwr_info;
1225 
1226 	if (scale_up) {
1227 		memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
1228 		       sizeof(struct ufs_pa_layer_attr));
1229 	} else {
1230 		memcpy(&new_pwr_info, &hba->pwr_info,
1231 		       sizeof(struct ufs_pa_layer_attr));
1232 
1233 		if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1234 		    hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1235 			/* save the current power mode */
1236 			memcpy(&hba->clk_scaling.saved_pwr_info,
1237 				&hba->pwr_info,
1238 				sizeof(struct ufs_pa_layer_attr));
1239 
1240 			/* scale down gear */
1241 			new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1242 			new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1243 		}
1244 	}
1245 
1246 	/* check if the power mode needs to be changed or not? */
1247 	ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1248 	if (ret)
1249 		dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1250 			__func__, ret,
1251 			hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1252 			new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1253 
1254 	return ret;
1255 }
1256 
1257 /*
1258  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1259  * has expired.
1260  *
1261  * Return: 0 upon success; -EBUSY upon timeout.
1262  */
ufshcd_clock_scaling_prepare(struct ufs_hba * hba,u64 timeout_us)1263 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1264 {
1265 	int ret = 0;
1266 	/*
1267 	 * make sure that there are no outstanding requests when
1268 	 * clock scaling is in progress
1269 	 */
1270 	blk_mq_quiesce_tagset(&hba->host->tag_set);
1271 	mutex_lock(&hba->wb_mutex);
1272 	down_write(&hba->clk_scaling_lock);
1273 
1274 	if (!hba->clk_scaling.is_allowed ||
1275 	    ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
1276 		ret = -EBUSY;
1277 		up_write(&hba->clk_scaling_lock);
1278 		mutex_unlock(&hba->wb_mutex);
1279 		blk_mq_unquiesce_tagset(&hba->host->tag_set);
1280 		goto out;
1281 	}
1282 
1283 	/* let's not get into low power until clock scaling is completed */
1284 	ufshcd_hold(hba);
1285 
1286 out:
1287 	return ret;
1288 }
1289 
ufshcd_clock_scaling_unprepare(struct ufs_hba * hba,int err,bool scale_up)1290 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up)
1291 {
1292 	up_write(&hba->clk_scaling_lock);
1293 
1294 	/* Enable Write Booster if we have scaled up else disable it */
1295 	if (ufshcd_enable_wb_if_scaling_up(hba) && !err)
1296 		ufshcd_wb_toggle(hba, scale_up);
1297 
1298 	mutex_unlock(&hba->wb_mutex);
1299 
1300 	blk_mq_unquiesce_tagset(&hba->host->tag_set);
1301 	ufshcd_release(hba);
1302 }
1303 
1304 /**
1305  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1306  * @hba: per adapter instance
1307  * @scale_up: True for scaling up and false for scalin down
1308  *
1309  * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
1310  * for any other errors.
1311  */
ufshcd_devfreq_scale(struct ufs_hba * hba,bool scale_up)1312 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1313 {
1314 	int ret = 0;
1315 
1316 	ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
1317 	if (ret)
1318 		return ret;
1319 
1320 	/* scale down the gear before scaling down clocks */
1321 	if (!scale_up) {
1322 		ret = ufshcd_scale_gear(hba, false);
1323 		if (ret)
1324 			goto out_unprepare;
1325 	}
1326 
1327 	ret = ufshcd_scale_clks(hba, scale_up);
1328 	if (ret) {
1329 		if (!scale_up)
1330 			ufshcd_scale_gear(hba, true);
1331 		goto out_unprepare;
1332 	}
1333 
1334 	/* scale up the gear after scaling up clocks */
1335 	if (scale_up) {
1336 		ret = ufshcd_scale_gear(hba, true);
1337 		if (ret) {
1338 			ufshcd_scale_clks(hba, false);
1339 			goto out_unprepare;
1340 		}
1341 	}
1342 
1343 out_unprepare:
1344 	ufshcd_clock_scaling_unprepare(hba, ret, scale_up);
1345 	return ret;
1346 }
1347 
ufshcd_clk_scaling_suspend_work(struct work_struct * work)1348 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1349 {
1350 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1351 					   clk_scaling.suspend_work);
1352 	unsigned long irq_flags;
1353 
1354 	spin_lock_irqsave(hba->host->host_lock, irq_flags);
1355 	if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1356 		spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1357 		return;
1358 	}
1359 	hba->clk_scaling.is_suspended = true;
1360 	spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1361 
1362 	__ufshcd_suspend_clkscaling(hba);
1363 }
1364 
ufshcd_clk_scaling_resume_work(struct work_struct * work)1365 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1366 {
1367 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1368 					   clk_scaling.resume_work);
1369 	unsigned long irq_flags;
1370 
1371 	spin_lock_irqsave(hba->host->host_lock, irq_flags);
1372 	if (!hba->clk_scaling.is_suspended) {
1373 		spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1374 		return;
1375 	}
1376 	hba->clk_scaling.is_suspended = false;
1377 	spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1378 
1379 	devfreq_resume_device(hba->devfreq);
1380 }
1381 
ufshcd_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)1382 static int ufshcd_devfreq_target(struct device *dev,
1383 				unsigned long *freq, u32 flags)
1384 {
1385 	int ret = 0;
1386 	struct ufs_hba *hba = dev_get_drvdata(dev);
1387 	ktime_t start;
1388 	bool scale_up, sched_clk_scaling_suspend_work = false;
1389 	struct list_head *clk_list = &hba->clk_list_head;
1390 	struct ufs_clk_info *clki;
1391 	unsigned long irq_flags;
1392 
1393 	if (!ufshcd_is_clkscaling_supported(hba))
1394 		return -EINVAL;
1395 
1396 	clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1397 	/* Override with the closest supported frequency */
1398 	*freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1399 	spin_lock_irqsave(hba->host->host_lock, irq_flags);
1400 	if (ufshcd_eh_in_progress(hba)) {
1401 		spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1402 		return 0;
1403 	}
1404 
1405 	if (!hba->clk_scaling.active_reqs)
1406 		sched_clk_scaling_suspend_work = true;
1407 
1408 	if (list_empty(clk_list)) {
1409 		spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1410 		goto out;
1411 	}
1412 
1413 	/* Decide based on the rounded-off frequency and update */
1414 	scale_up = *freq == clki->max_freq;
1415 	if (!scale_up)
1416 		*freq = clki->min_freq;
1417 	/* Update the frequency */
1418 	if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1419 		spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1420 		ret = 0;
1421 		goto out; /* no state change required */
1422 	}
1423 	spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1424 
1425 	start = ktime_get();
1426 	ret = ufshcd_devfreq_scale(hba, scale_up);
1427 
1428 	trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1429 		(scale_up ? "up" : "down"),
1430 		ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1431 
1432 out:
1433 	if (sched_clk_scaling_suspend_work)
1434 		queue_work(hba->clk_scaling.workq,
1435 			   &hba->clk_scaling.suspend_work);
1436 
1437 	return ret;
1438 }
1439 
ufshcd_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)1440 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1441 		struct devfreq_dev_status *stat)
1442 {
1443 	struct ufs_hba *hba = dev_get_drvdata(dev);
1444 	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1445 	unsigned long flags;
1446 	struct list_head *clk_list = &hba->clk_list_head;
1447 	struct ufs_clk_info *clki;
1448 	ktime_t curr_t;
1449 
1450 	if (!ufshcd_is_clkscaling_supported(hba))
1451 		return -EINVAL;
1452 
1453 	memset(stat, 0, sizeof(*stat));
1454 
1455 	spin_lock_irqsave(hba->host->host_lock, flags);
1456 	curr_t = ktime_get();
1457 	if (!scaling->window_start_t)
1458 		goto start_window;
1459 
1460 	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1461 	/*
1462 	 * If current frequency is 0, then the ondemand governor considers
1463 	 * there's no initial frequency set. And it always requests to set
1464 	 * to max. frequency.
1465 	 */
1466 	stat->current_frequency = clki->curr_freq;
1467 	if (scaling->is_busy_started)
1468 		scaling->tot_busy_t += ktime_us_delta(curr_t,
1469 				scaling->busy_start_t);
1470 
1471 	stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1472 	stat->busy_time = scaling->tot_busy_t;
1473 start_window:
1474 	scaling->window_start_t = curr_t;
1475 	scaling->tot_busy_t = 0;
1476 
1477 	if (scaling->active_reqs) {
1478 		scaling->busy_start_t = curr_t;
1479 		scaling->is_busy_started = true;
1480 	} else {
1481 		scaling->busy_start_t = 0;
1482 		scaling->is_busy_started = false;
1483 	}
1484 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1485 	return 0;
1486 }
1487 
ufshcd_devfreq_init(struct ufs_hba * hba)1488 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1489 {
1490 	struct list_head *clk_list = &hba->clk_list_head;
1491 	struct ufs_clk_info *clki;
1492 	struct devfreq *devfreq;
1493 	int ret;
1494 
1495 	/* Skip devfreq if we don't have any clocks in the list */
1496 	if (list_empty(clk_list))
1497 		return 0;
1498 
1499 	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1500 	dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1501 	dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1502 
1503 	ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1504 					 &hba->vps->ondemand_data);
1505 	devfreq = devfreq_add_device(hba->dev,
1506 			&hba->vps->devfreq_profile,
1507 			DEVFREQ_GOV_SIMPLE_ONDEMAND,
1508 			&hba->vps->ondemand_data);
1509 	if (IS_ERR(devfreq)) {
1510 		ret = PTR_ERR(devfreq);
1511 		dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1512 
1513 		dev_pm_opp_remove(hba->dev, clki->min_freq);
1514 		dev_pm_opp_remove(hba->dev, clki->max_freq);
1515 		return ret;
1516 	}
1517 
1518 	hba->devfreq = devfreq;
1519 
1520 	return 0;
1521 }
1522 
ufshcd_devfreq_remove(struct ufs_hba * hba)1523 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1524 {
1525 	struct list_head *clk_list = &hba->clk_list_head;
1526 	struct ufs_clk_info *clki;
1527 
1528 	if (!hba->devfreq)
1529 		return;
1530 
1531 	devfreq_remove_device(hba->devfreq);
1532 	hba->devfreq = NULL;
1533 
1534 	clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1535 	dev_pm_opp_remove(hba->dev, clki->min_freq);
1536 	dev_pm_opp_remove(hba->dev, clki->max_freq);
1537 }
1538 
__ufshcd_suspend_clkscaling(struct ufs_hba * hba)1539 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1540 {
1541 	unsigned long flags;
1542 
1543 	devfreq_suspend_device(hba->devfreq);
1544 	spin_lock_irqsave(hba->host->host_lock, flags);
1545 	hba->clk_scaling.window_start_t = 0;
1546 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1547 }
1548 
ufshcd_suspend_clkscaling(struct ufs_hba * hba)1549 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1550 {
1551 	unsigned long flags;
1552 	bool suspend = false;
1553 
1554 	cancel_work_sync(&hba->clk_scaling.suspend_work);
1555 	cancel_work_sync(&hba->clk_scaling.resume_work);
1556 
1557 	spin_lock_irqsave(hba->host->host_lock, flags);
1558 	if (!hba->clk_scaling.is_suspended) {
1559 		suspend = true;
1560 		hba->clk_scaling.is_suspended = true;
1561 	}
1562 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1563 
1564 	if (suspend)
1565 		__ufshcd_suspend_clkscaling(hba);
1566 }
1567 
ufshcd_resume_clkscaling(struct ufs_hba * hba)1568 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1569 {
1570 	unsigned long flags;
1571 	bool resume = false;
1572 
1573 	spin_lock_irqsave(hba->host->host_lock, flags);
1574 	if (hba->clk_scaling.is_suspended) {
1575 		resume = true;
1576 		hba->clk_scaling.is_suspended = false;
1577 	}
1578 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1579 
1580 	if (resume)
1581 		devfreq_resume_device(hba->devfreq);
1582 }
1583 
ufshcd_clkscale_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1584 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1585 		struct device_attribute *attr, char *buf)
1586 {
1587 	struct ufs_hba *hba = dev_get_drvdata(dev);
1588 
1589 	return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1590 }
1591 
ufshcd_clkscale_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1592 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1593 		struct device_attribute *attr, const char *buf, size_t count)
1594 {
1595 	struct ufs_hba *hba = dev_get_drvdata(dev);
1596 	u32 value;
1597 	int err = 0;
1598 
1599 	if (kstrtou32(buf, 0, &value))
1600 		return -EINVAL;
1601 
1602 	down(&hba->host_sem);
1603 	if (!ufshcd_is_user_access_allowed(hba)) {
1604 		err = -EBUSY;
1605 		goto out;
1606 	}
1607 
1608 	value = !!value;
1609 	if (value == hba->clk_scaling.is_enabled)
1610 		goto out;
1611 
1612 	ufshcd_rpm_get_sync(hba);
1613 	ufshcd_hold(hba);
1614 
1615 	hba->clk_scaling.is_enabled = value;
1616 
1617 	if (value) {
1618 		ufshcd_resume_clkscaling(hba);
1619 	} else {
1620 		ufshcd_suspend_clkscaling(hba);
1621 		err = ufshcd_devfreq_scale(hba, true);
1622 		if (err)
1623 			dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1624 					__func__, err);
1625 	}
1626 
1627 	ufshcd_release(hba);
1628 	ufshcd_rpm_put_sync(hba);
1629 out:
1630 	up(&hba->host_sem);
1631 	return err ? err : count;
1632 }
1633 
ufshcd_init_clk_scaling_sysfs(struct ufs_hba * hba)1634 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1635 {
1636 	hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1637 	hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1638 	sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1639 	hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1640 	hba->clk_scaling.enable_attr.attr.mode = 0644;
1641 	if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1642 		dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1643 }
1644 
ufshcd_remove_clk_scaling_sysfs(struct ufs_hba * hba)1645 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1646 {
1647 	if (hba->clk_scaling.enable_attr.attr.name)
1648 		device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1649 }
1650 
ufshcd_init_clk_scaling(struct ufs_hba * hba)1651 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1652 {
1653 	char wq_name[sizeof("ufs_clkscaling_00")];
1654 
1655 	if (!ufshcd_is_clkscaling_supported(hba))
1656 		return;
1657 
1658 	if (!hba->clk_scaling.min_gear)
1659 		hba->clk_scaling.min_gear = UFS_HS_G1;
1660 
1661 	INIT_WORK(&hba->clk_scaling.suspend_work,
1662 		  ufshcd_clk_scaling_suspend_work);
1663 	INIT_WORK(&hba->clk_scaling.resume_work,
1664 		  ufshcd_clk_scaling_resume_work);
1665 
1666 	snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1667 		 hba->host->host_no);
1668 	hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1669 
1670 	hba->clk_scaling.is_initialized = true;
1671 }
1672 
ufshcd_exit_clk_scaling(struct ufs_hba * hba)1673 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1674 {
1675 	if (!hba->clk_scaling.is_initialized)
1676 		return;
1677 
1678 	ufshcd_remove_clk_scaling_sysfs(hba);
1679 	destroy_workqueue(hba->clk_scaling.workq);
1680 	ufshcd_devfreq_remove(hba);
1681 	hba->clk_scaling.is_initialized = false;
1682 }
1683 
ufshcd_ungate_work(struct work_struct * work)1684 static void ufshcd_ungate_work(struct work_struct *work)
1685 {
1686 	int ret;
1687 	unsigned long flags;
1688 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1689 			clk_gating.ungate_work);
1690 
1691 	cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1692 
1693 	spin_lock_irqsave(hba->host->host_lock, flags);
1694 	if (hba->clk_gating.state == CLKS_ON) {
1695 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1696 		return;
1697 	}
1698 
1699 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1700 	ufshcd_hba_vreg_set_hpm(hba);
1701 	ufshcd_setup_clocks(hba, true);
1702 
1703 	ufshcd_enable_irq(hba);
1704 
1705 	/* Exit from hibern8 */
1706 	if (ufshcd_can_hibern8_during_gating(hba)) {
1707 		/* Prevent gating in this path */
1708 		hba->clk_gating.is_suspended = true;
1709 		if (ufshcd_is_link_hibern8(hba)) {
1710 			ret = ufshcd_uic_hibern8_exit(hba);
1711 			if (ret)
1712 				dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1713 					__func__, ret);
1714 			else
1715 				ufshcd_set_link_active(hba);
1716 		}
1717 		hba->clk_gating.is_suspended = false;
1718 	}
1719 }
1720 
1721 /**
1722  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1723  * Also, exit from hibern8 mode and set the link as active.
1724  * @hba: per adapter instance
1725  */
ufshcd_hold(struct ufs_hba * hba)1726 void ufshcd_hold(struct ufs_hba *hba)
1727 {
1728 	bool flush_result;
1729 	unsigned long flags;
1730 
1731 	if (!ufshcd_is_clkgating_allowed(hba) ||
1732 	    !hba->clk_gating.is_initialized)
1733 		return;
1734 	spin_lock_irqsave(hba->host->host_lock, flags);
1735 	hba->clk_gating.active_reqs++;
1736 
1737 start:
1738 	switch (hba->clk_gating.state) {
1739 	case CLKS_ON:
1740 		/*
1741 		 * Wait for the ungate work to complete if in progress.
1742 		 * Though the clocks may be in ON state, the link could
1743 		 * still be in hibner8 state if hibern8 is allowed
1744 		 * during clock gating.
1745 		 * Make sure we exit hibern8 state also in addition to
1746 		 * clocks being ON.
1747 		 */
1748 		if (ufshcd_can_hibern8_during_gating(hba) &&
1749 		    ufshcd_is_link_hibern8(hba)) {
1750 			spin_unlock_irqrestore(hba->host->host_lock, flags);
1751 			flush_result = flush_work(&hba->clk_gating.ungate_work);
1752 			if (hba->clk_gating.is_suspended && !flush_result)
1753 				return;
1754 			spin_lock_irqsave(hba->host->host_lock, flags);
1755 			goto start;
1756 		}
1757 		break;
1758 	case REQ_CLKS_OFF:
1759 		if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1760 			hba->clk_gating.state = CLKS_ON;
1761 			trace_ufshcd_clk_gating(dev_name(hba->dev),
1762 						hba->clk_gating.state);
1763 			break;
1764 		}
1765 		/*
1766 		 * If we are here, it means gating work is either done or
1767 		 * currently running. Hence, fall through to cancel gating
1768 		 * work and to enable clocks.
1769 		 */
1770 		fallthrough;
1771 	case CLKS_OFF:
1772 		hba->clk_gating.state = REQ_CLKS_ON;
1773 		trace_ufshcd_clk_gating(dev_name(hba->dev),
1774 					hba->clk_gating.state);
1775 		queue_work(hba->clk_gating.clk_gating_workq,
1776 			   &hba->clk_gating.ungate_work);
1777 		/*
1778 		 * fall through to check if we should wait for this
1779 		 * work to be done or not.
1780 		 */
1781 		fallthrough;
1782 	case REQ_CLKS_ON:
1783 		spin_unlock_irqrestore(hba->host->host_lock, flags);
1784 		flush_work(&hba->clk_gating.ungate_work);
1785 		/* Make sure state is CLKS_ON before returning */
1786 		spin_lock_irqsave(hba->host->host_lock, flags);
1787 		goto start;
1788 	default:
1789 		dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1790 				__func__, hba->clk_gating.state);
1791 		break;
1792 	}
1793 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1794 }
1795 EXPORT_SYMBOL_GPL(ufshcd_hold);
1796 
ufshcd_gate_work(struct work_struct * work)1797 static void ufshcd_gate_work(struct work_struct *work)
1798 {
1799 	struct ufs_hba *hba = container_of(work, struct ufs_hba,
1800 			clk_gating.gate_work.work);
1801 	unsigned long flags;
1802 	int ret;
1803 
1804 	spin_lock_irqsave(hba->host->host_lock, flags);
1805 	/*
1806 	 * In case you are here to cancel this work the gating state
1807 	 * would be marked as REQ_CLKS_ON. In this case save time by
1808 	 * skipping the gating work and exit after changing the clock
1809 	 * state to CLKS_ON.
1810 	 */
1811 	if (hba->clk_gating.is_suspended ||
1812 		(hba->clk_gating.state != REQ_CLKS_OFF)) {
1813 		hba->clk_gating.state = CLKS_ON;
1814 		trace_ufshcd_clk_gating(dev_name(hba->dev),
1815 					hba->clk_gating.state);
1816 		goto rel_lock;
1817 	}
1818 
1819 	if (hba->clk_gating.active_reqs
1820 		|| hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1821 		|| hba->outstanding_reqs || hba->outstanding_tasks
1822 		|| hba->active_uic_cmd || hba->uic_async_done)
1823 		goto rel_lock;
1824 
1825 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1826 
1827 	/* put the link into hibern8 mode before turning off clocks */
1828 	if (ufshcd_can_hibern8_during_gating(hba)) {
1829 		ret = ufshcd_uic_hibern8_enter(hba);
1830 		if (ret) {
1831 			hba->clk_gating.state = CLKS_ON;
1832 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1833 					__func__, ret);
1834 			trace_ufshcd_clk_gating(dev_name(hba->dev),
1835 						hba->clk_gating.state);
1836 			goto out;
1837 		}
1838 		ufshcd_set_link_hibern8(hba);
1839 	}
1840 
1841 	ufshcd_disable_irq(hba);
1842 
1843 	ufshcd_setup_clocks(hba, false);
1844 
1845 	/* Put the host controller in low power mode if possible */
1846 	ufshcd_hba_vreg_set_lpm(hba);
1847 	/*
1848 	 * In case you are here to cancel this work the gating state
1849 	 * would be marked as REQ_CLKS_ON. In this case keep the state
1850 	 * as REQ_CLKS_ON which would anyway imply that clocks are off
1851 	 * and a request to turn them on is pending. By doing this way,
1852 	 * we keep the state machine in tact and this would ultimately
1853 	 * prevent from doing cancel work multiple times when there are
1854 	 * new requests arriving before the current cancel work is done.
1855 	 */
1856 	spin_lock_irqsave(hba->host->host_lock, flags);
1857 	if (hba->clk_gating.state == REQ_CLKS_OFF) {
1858 		hba->clk_gating.state = CLKS_OFF;
1859 		trace_ufshcd_clk_gating(dev_name(hba->dev),
1860 					hba->clk_gating.state);
1861 	}
1862 rel_lock:
1863 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1864 out:
1865 	return;
1866 }
1867 
1868 /* host lock must be held before calling this variant */
__ufshcd_release(struct ufs_hba * hba)1869 static void __ufshcd_release(struct ufs_hba *hba)
1870 {
1871 	if (!ufshcd_is_clkgating_allowed(hba))
1872 		return;
1873 
1874 	hba->clk_gating.active_reqs--;
1875 
1876 	if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1877 	    hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1878 	    hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
1879 	    hba->active_uic_cmd || hba->uic_async_done ||
1880 	    hba->clk_gating.state == CLKS_OFF)
1881 		return;
1882 
1883 	hba->clk_gating.state = REQ_CLKS_OFF;
1884 	trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1885 	queue_delayed_work(hba->clk_gating.clk_gating_workq,
1886 			   &hba->clk_gating.gate_work,
1887 			   msecs_to_jiffies(hba->clk_gating.delay_ms));
1888 }
1889 
ufshcd_release(struct ufs_hba * hba)1890 void ufshcd_release(struct ufs_hba *hba)
1891 {
1892 	unsigned long flags;
1893 
1894 	spin_lock_irqsave(hba->host->host_lock, flags);
1895 	__ufshcd_release(hba);
1896 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1897 }
1898 EXPORT_SYMBOL_GPL(ufshcd_release);
1899 
ufshcd_clkgate_delay_show(struct device * dev,struct device_attribute * attr,char * buf)1900 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1901 		struct device_attribute *attr, char *buf)
1902 {
1903 	struct ufs_hba *hba = dev_get_drvdata(dev);
1904 
1905 	return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1906 }
1907 
ufshcd_clkgate_delay_set(struct device * dev,unsigned long value)1908 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1909 {
1910 	struct ufs_hba *hba = dev_get_drvdata(dev);
1911 	unsigned long flags;
1912 
1913 	spin_lock_irqsave(hba->host->host_lock, flags);
1914 	hba->clk_gating.delay_ms = value;
1915 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1916 }
1917 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1918 
ufshcd_clkgate_delay_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1919 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1920 		struct device_attribute *attr, const char *buf, size_t count)
1921 {
1922 	unsigned long value;
1923 
1924 	if (kstrtoul(buf, 0, &value))
1925 		return -EINVAL;
1926 
1927 	ufshcd_clkgate_delay_set(dev, value);
1928 	return count;
1929 }
1930 
ufshcd_clkgate_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1931 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1932 		struct device_attribute *attr, char *buf)
1933 {
1934 	struct ufs_hba *hba = dev_get_drvdata(dev);
1935 
1936 	return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1937 }
1938 
ufshcd_clkgate_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1939 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1940 		struct device_attribute *attr, const char *buf, size_t count)
1941 {
1942 	struct ufs_hba *hba = dev_get_drvdata(dev);
1943 	unsigned long flags;
1944 	u32 value;
1945 
1946 	if (kstrtou32(buf, 0, &value))
1947 		return -EINVAL;
1948 
1949 	value = !!value;
1950 
1951 	spin_lock_irqsave(hba->host->host_lock, flags);
1952 	if (value == hba->clk_gating.is_enabled)
1953 		goto out;
1954 
1955 	if (value)
1956 		__ufshcd_release(hba);
1957 	else
1958 		hba->clk_gating.active_reqs++;
1959 
1960 	hba->clk_gating.is_enabled = value;
1961 out:
1962 	spin_unlock_irqrestore(hba->host->host_lock, flags);
1963 	return count;
1964 }
1965 
ufshcd_init_clk_gating_sysfs(struct ufs_hba * hba)1966 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1967 {
1968 	hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1969 	hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1970 	sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1971 	hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1972 	hba->clk_gating.delay_attr.attr.mode = 0644;
1973 	if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1974 		dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1975 
1976 	hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1977 	hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1978 	sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1979 	hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1980 	hba->clk_gating.enable_attr.attr.mode = 0644;
1981 	if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1982 		dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1983 }
1984 
ufshcd_remove_clk_gating_sysfs(struct ufs_hba * hba)1985 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1986 {
1987 	if (hba->clk_gating.delay_attr.attr.name)
1988 		device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1989 	if (hba->clk_gating.enable_attr.attr.name)
1990 		device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1991 }
1992 
ufshcd_init_clk_gating(struct ufs_hba * hba)1993 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1994 {
1995 	char wq_name[sizeof("ufs_clk_gating_00")];
1996 
1997 	if (!ufshcd_is_clkgating_allowed(hba))
1998 		return;
1999 
2000 	hba->clk_gating.state = CLKS_ON;
2001 
2002 	hba->clk_gating.delay_ms = 150;
2003 	INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2004 	INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2005 
2006 	snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
2007 		 hba->host->host_no);
2008 	hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
2009 					WQ_MEM_RECLAIM | WQ_HIGHPRI);
2010 
2011 	ufshcd_init_clk_gating_sysfs(hba);
2012 
2013 	hba->clk_gating.is_enabled = true;
2014 	hba->clk_gating.is_initialized = true;
2015 }
2016 
ufshcd_exit_clk_gating(struct ufs_hba * hba)2017 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2018 {
2019 	if (!hba->clk_gating.is_initialized)
2020 		return;
2021 
2022 	ufshcd_remove_clk_gating_sysfs(hba);
2023 
2024 	/* Ungate the clock if necessary. */
2025 	ufshcd_hold(hba);
2026 	hba->clk_gating.is_initialized = false;
2027 	ufshcd_release(hba);
2028 
2029 	destroy_workqueue(hba->clk_gating.clk_gating_workq);
2030 }
2031 
ufshcd_clk_scaling_start_busy(struct ufs_hba * hba)2032 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2033 {
2034 	bool queue_resume_work = false;
2035 	ktime_t curr_t = ktime_get();
2036 	unsigned long flags;
2037 
2038 	if (!ufshcd_is_clkscaling_supported(hba))
2039 		return;
2040 
2041 	spin_lock_irqsave(hba->host->host_lock, flags);
2042 	if (!hba->clk_scaling.active_reqs++)
2043 		queue_resume_work = true;
2044 
2045 	if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2046 		spin_unlock_irqrestore(hba->host->host_lock, flags);
2047 		return;
2048 	}
2049 
2050 	if (queue_resume_work)
2051 		queue_work(hba->clk_scaling.workq,
2052 			   &hba->clk_scaling.resume_work);
2053 
2054 	if (!hba->clk_scaling.window_start_t) {
2055 		hba->clk_scaling.window_start_t = curr_t;
2056 		hba->clk_scaling.tot_busy_t = 0;
2057 		hba->clk_scaling.is_busy_started = false;
2058 	}
2059 
2060 	if (!hba->clk_scaling.is_busy_started) {
2061 		hba->clk_scaling.busy_start_t = curr_t;
2062 		hba->clk_scaling.is_busy_started = true;
2063 	}
2064 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2065 }
2066 
ufshcd_clk_scaling_update_busy(struct ufs_hba * hba)2067 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2068 {
2069 	struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2070 	unsigned long flags;
2071 
2072 	if (!ufshcd_is_clkscaling_supported(hba))
2073 		return;
2074 
2075 	spin_lock_irqsave(hba->host->host_lock, flags);
2076 	hba->clk_scaling.active_reqs--;
2077 	if (!scaling->active_reqs && scaling->is_busy_started) {
2078 		scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2079 					scaling->busy_start_t));
2080 		scaling->busy_start_t = 0;
2081 		scaling->is_busy_started = false;
2082 	}
2083 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2084 }
2085 
ufshcd_monitor_opcode2dir(u8 opcode)2086 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2087 {
2088 	if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2089 		return READ;
2090 	else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2091 		return WRITE;
2092 	else
2093 		return -EINVAL;
2094 }
2095 
ufshcd_should_inform_monitor(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2096 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2097 						struct ufshcd_lrb *lrbp)
2098 {
2099 	const struct ufs_hba_monitor *m = &hba->monitor;
2100 
2101 	return (m->enabled && lrbp && lrbp->cmd &&
2102 		(!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2103 		ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2104 }
2105 
ufshcd_start_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2106 static void ufshcd_start_monitor(struct ufs_hba *hba,
2107 				 const struct ufshcd_lrb *lrbp)
2108 {
2109 	int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2110 	unsigned long flags;
2111 
2112 	spin_lock_irqsave(hba->host->host_lock, flags);
2113 	if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2114 		hba->monitor.busy_start_ts[dir] = ktime_get();
2115 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2116 }
2117 
ufshcd_update_monitor(struct ufs_hba * hba,const struct ufshcd_lrb * lrbp)2118 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
2119 {
2120 	int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2121 	unsigned long flags;
2122 
2123 	spin_lock_irqsave(hba->host->host_lock, flags);
2124 	if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2125 		const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2126 		struct ufs_hba_monitor *m = &hba->monitor;
2127 		ktime_t now, inc, lat;
2128 
2129 		now = lrbp->compl_time_stamp;
2130 		inc = ktime_sub(now, m->busy_start_ts[dir]);
2131 		m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2132 		m->nr_sec_rw[dir] += blk_rq_sectors(req);
2133 
2134 		/* Update latencies */
2135 		m->nr_req[dir]++;
2136 		lat = ktime_sub(now, lrbp->issue_time_stamp);
2137 		m->lat_sum[dir] += lat;
2138 		if (m->lat_max[dir] < lat || !m->lat_max[dir])
2139 			m->lat_max[dir] = lat;
2140 		if (m->lat_min[dir] > lat || !m->lat_min[dir])
2141 			m->lat_min[dir] = lat;
2142 
2143 		m->nr_queued[dir]--;
2144 		/* Push forward the busy start of monitor */
2145 		m->busy_start_ts[dir] = now;
2146 	}
2147 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2148 }
2149 
2150 /**
2151  * ufshcd_send_command - Send SCSI or device management commands
2152  * @hba: per adapter instance
2153  * @task_tag: Task tag of the command
2154  * @hwq: pointer to hardware queue instance
2155  */
2156 static inline
ufshcd_send_command(struct ufs_hba * hba,unsigned int task_tag,struct ufs_hw_queue * hwq)2157 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag,
2158 			 struct ufs_hw_queue *hwq)
2159 {
2160 	struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2161 	unsigned long flags;
2162 
2163 	lrbp->issue_time_stamp = ktime_get();
2164 	lrbp->issue_time_stamp_local_clock = local_clock();
2165 	lrbp->compl_time_stamp = ktime_set(0, 0);
2166 	lrbp->compl_time_stamp_local_clock = 0;
2167 	ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2168 	ufshcd_clk_scaling_start_busy(hba);
2169 	if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2170 		ufshcd_start_monitor(hba, lrbp);
2171 
2172 	if (is_mcq_enabled(hba)) {
2173 		int utrd_size = sizeof(struct utp_transfer_req_desc);
2174 		struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr;
2175 		struct utp_transfer_req_desc *dest;
2176 
2177 		spin_lock(&hwq->sq_lock);
2178 		dest = hwq->sqe_base_addr + hwq->sq_tail_slot;
2179 		memcpy(dest, src, utrd_size);
2180 		ufshcd_inc_sq_tail(hwq);
2181 		spin_unlock(&hwq->sq_lock);
2182 	} else {
2183 		spin_lock_irqsave(&hba->outstanding_lock, flags);
2184 		if (hba->vops && hba->vops->setup_xfer_req)
2185 			hba->vops->setup_xfer_req(hba, lrbp->task_tag,
2186 						  !!lrbp->cmd);
2187 		__set_bit(lrbp->task_tag, &hba->outstanding_reqs);
2188 		ufshcd_writel(hba, 1 << lrbp->task_tag,
2189 			      REG_UTP_TRANSFER_REQ_DOOR_BELL);
2190 		spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2191 	}
2192 }
2193 
2194 /**
2195  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2196  * @lrbp: pointer to local reference block
2197  */
ufshcd_copy_sense_data(struct ufshcd_lrb * lrbp)2198 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2199 {
2200 	u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2201 	u16 resp_len;
2202 	int len;
2203 
2204 	resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length);
2205 	if (sense_buffer && resp_len) {
2206 		int len_to_copy;
2207 
2208 		len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2209 		len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2210 
2211 		memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2212 		       len_to_copy);
2213 	}
2214 }
2215 
2216 /**
2217  * ufshcd_copy_query_response() - Copy the Query Response and the data
2218  * descriptor
2219  * @hba: per adapter instance
2220  * @lrbp: pointer to local reference block
2221  *
2222  * Return: 0 upon success; < 0 upon failure.
2223  */
2224 static
ufshcd_copy_query_response(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2225 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2226 {
2227 	struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2228 
2229 	memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2230 
2231 	/* Get the descriptor */
2232 	if (hba->dev_cmd.query.descriptor &&
2233 	    lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2234 		u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2235 				GENERAL_UPIU_REQUEST_SIZE;
2236 		u16 resp_len;
2237 		u16 buf_len;
2238 
2239 		/* data segment length */
2240 		resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
2241 				       .data_segment_length);
2242 		buf_len = be16_to_cpu(
2243 				hba->dev_cmd.query.request.upiu_req.length);
2244 		if (likely(buf_len >= resp_len)) {
2245 			memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2246 		} else {
2247 			dev_warn(hba->dev,
2248 				 "%s: rsp size %d is bigger than buffer size %d",
2249 				 __func__, resp_len, buf_len);
2250 			return -EINVAL;
2251 		}
2252 	}
2253 
2254 	return 0;
2255 }
2256 
2257 /**
2258  * ufshcd_hba_capabilities - Read controller capabilities
2259  * @hba: per adapter instance
2260  *
2261  * Return: 0 on success, negative on error.
2262  */
ufshcd_hba_capabilities(struct ufs_hba * hba)2263 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2264 {
2265 	int err;
2266 
2267 	hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2268 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
2269 		hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
2270 
2271 	/* nutrs and nutmrs are 0 based values */
2272 	hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2273 	hba->nutmrs =
2274 	((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2275 	hba->reserved_slot = hba->nutrs - 1;
2276 
2277 	/* Read crypto capabilities */
2278 	err = ufshcd_hba_init_crypto_capabilities(hba);
2279 	if (err) {
2280 		dev_err(hba->dev, "crypto setup failed\n");
2281 		return err;
2282 	}
2283 
2284 	/*
2285 	 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and
2286 	 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which
2287 	 * means we can simply read values regardless of version.
2288 	 */
2289 	hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2290 	/*
2291 	 * 0h: legacy single doorbell support is available
2292 	 * 1h: indicate that legacy single doorbell support has been removed
2293 	 */
2294 	hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities);
2295 	if (!hba->mcq_sup)
2296 		return 0;
2297 
2298 	hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2299 	hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT,
2300 				     hba->mcq_capabilities);
2301 
2302 	return 0;
2303 }
2304 
2305 /**
2306  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2307  *                            to accept UIC commands
2308  * @hba: per adapter instance
2309  *
2310  * Return: true on success, else false.
2311  */
ufshcd_ready_for_uic_cmd(struct ufs_hba * hba)2312 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2313 {
2314 	u32 val;
2315 	int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
2316 				    500, UIC_CMD_TIMEOUT * 1000, false, hba,
2317 				    REG_CONTROLLER_STATUS);
2318 	return ret == 0 ? true : false;
2319 }
2320 
2321 /**
2322  * ufshcd_get_upmcrs - Get the power mode change request status
2323  * @hba: Pointer to adapter instance
2324  *
2325  * This function gets the UPMCRS field of HCS register
2326  *
2327  * Return: value of UPMCRS field.
2328  */
ufshcd_get_upmcrs(struct ufs_hba * hba)2329 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2330 {
2331 	return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2332 }
2333 
2334 /**
2335  * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2336  * @hba: per adapter instance
2337  * @uic_cmd: UIC command
2338  */
2339 static inline void
ufshcd_dispatch_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2340 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2341 {
2342 	lockdep_assert_held(&hba->uic_cmd_mutex);
2343 
2344 	WARN_ON(hba->active_uic_cmd);
2345 
2346 	hba->active_uic_cmd = uic_cmd;
2347 
2348 	/* Write Args */
2349 	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2350 	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2351 	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2352 
2353 	ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2354 
2355 	/* Write UIC Cmd */
2356 	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2357 		      REG_UIC_COMMAND);
2358 }
2359 
2360 /**
2361  * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2362  * @hba: per adapter instance
2363  * @uic_cmd: UIC command
2364  *
2365  * Return: 0 only if success.
2366  */
2367 static int
ufshcd_wait_for_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2368 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2369 {
2370 	int ret;
2371 	unsigned long flags;
2372 
2373 	lockdep_assert_held(&hba->uic_cmd_mutex);
2374 
2375 	if (wait_for_completion_timeout(&uic_cmd->done,
2376 					msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2377 		ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2378 	} else {
2379 		ret = -ETIMEDOUT;
2380 		dev_err(hba->dev,
2381 			"uic cmd 0x%x with arg3 0x%x completion timeout\n",
2382 			uic_cmd->command, uic_cmd->argument3);
2383 
2384 		if (!uic_cmd->cmd_active) {
2385 			dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2386 				__func__);
2387 			ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2388 		}
2389 	}
2390 
2391 	spin_lock_irqsave(hba->host->host_lock, flags);
2392 	hba->active_uic_cmd = NULL;
2393 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2394 
2395 	return ret;
2396 }
2397 
2398 /**
2399  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2400  * @hba: per adapter instance
2401  * @uic_cmd: UIC command
2402  * @completion: initialize the completion only if this is set to true
2403  *
2404  * Return: 0 only if success.
2405  */
2406 static int
__ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd,bool completion)2407 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2408 		      bool completion)
2409 {
2410 	lockdep_assert_held(&hba->uic_cmd_mutex);
2411 
2412 	if (!ufshcd_ready_for_uic_cmd(hba)) {
2413 		dev_err(hba->dev,
2414 			"Controller not ready to accept UIC commands\n");
2415 		return -EIO;
2416 	}
2417 
2418 	if (completion)
2419 		init_completion(&uic_cmd->done);
2420 
2421 	uic_cmd->cmd_active = 1;
2422 	ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2423 
2424 	return 0;
2425 }
2426 
2427 /**
2428  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2429  * @hba: per adapter instance
2430  * @uic_cmd: UIC command
2431  *
2432  * Return: 0 only if success.
2433  */
ufshcd_send_uic_cmd(struct ufs_hba * hba,struct uic_command * uic_cmd)2434 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2435 {
2436 	int ret;
2437 
2438 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2439 		return 0;
2440 
2441 	ufshcd_hold(hba);
2442 	mutex_lock(&hba->uic_cmd_mutex);
2443 	ufshcd_add_delay_before_dme_cmd(hba);
2444 
2445 	ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2446 	if (!ret)
2447 		ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2448 
2449 	mutex_unlock(&hba->uic_cmd_mutex);
2450 
2451 	ufshcd_release(hba);
2452 	return ret;
2453 }
2454 
2455 /**
2456  * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2457  * @hba:	per-adapter instance
2458  * @lrbp:	pointer to local reference block
2459  * @sg_entries:	The number of sg lists actually used
2460  * @sg_list:	Pointer to SG list
2461  */
ufshcd_sgl_to_prdt(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int sg_entries,struct scatterlist * sg_list)2462 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2463 			       struct scatterlist *sg_list)
2464 {
2465 	struct ufshcd_sg_entry *prd;
2466 	struct scatterlist *sg;
2467 	int i;
2468 
2469 	if (sg_entries) {
2470 
2471 		if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2472 			lrbp->utr_descriptor_ptr->prd_table_length =
2473 				cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2474 		else
2475 			lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2476 
2477 		prd = lrbp->ucd_prdt_ptr;
2478 
2479 		for_each_sg(sg_list, sg, sg_entries, i) {
2480 			const unsigned int len = sg_dma_len(sg);
2481 
2482 			/*
2483 			 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2484 			 * based value that indicates the length, in bytes, of
2485 			 * the data block. A maximum of length of 256KB may
2486 			 * exist for any entry. Bits 1:0 of this field shall be
2487 			 * 11b to indicate Dword granularity. A value of '3'
2488 			 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2489 			 */
2490 			WARN_ONCE(len > SZ_256K, "len = %#x\n", len);
2491 			prd->size = cpu_to_le32(len - 1);
2492 			prd->addr = cpu_to_le64(sg->dma_address);
2493 			prd->reserved = 0;
2494 			prd = (void *)prd + ufshcd_sg_entry_size(hba);
2495 		}
2496 	} else {
2497 		lrbp->utr_descriptor_ptr->prd_table_length = 0;
2498 	}
2499 }
2500 
2501 /**
2502  * ufshcd_map_sg - Map scatter-gather list to prdt
2503  * @hba: per adapter instance
2504  * @lrbp: pointer to local reference block
2505  *
2506  * Return: 0 in case of success, non-zero value in case of failure.
2507  */
ufshcd_map_sg(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2508 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2509 {
2510 	struct scsi_cmnd *cmd = lrbp->cmd;
2511 	int sg_segments = scsi_dma_map(cmd);
2512 
2513 	if (sg_segments < 0)
2514 		return sg_segments;
2515 
2516 	ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
2517 
2518 	return 0;
2519 }
2520 
2521 /**
2522  * ufshcd_enable_intr - enable interrupts
2523  * @hba: per adapter instance
2524  * @intrs: interrupt bits
2525  */
ufshcd_enable_intr(struct ufs_hba * hba,u32 intrs)2526 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2527 {
2528 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2529 
2530 	if (hba->ufs_version == ufshci_version(1, 0)) {
2531 		u32 rw;
2532 		rw = set & INTERRUPT_MASK_RW_VER_10;
2533 		set = rw | ((set ^ intrs) & intrs);
2534 	} else {
2535 		set |= intrs;
2536 	}
2537 
2538 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2539 }
2540 
2541 /**
2542  * ufshcd_disable_intr - disable interrupts
2543  * @hba: per adapter instance
2544  * @intrs: interrupt bits
2545  */
ufshcd_disable_intr(struct ufs_hba * hba,u32 intrs)2546 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2547 {
2548 	u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2549 
2550 	if (hba->ufs_version == ufshci_version(1, 0)) {
2551 		u32 rw;
2552 		rw = (set & INTERRUPT_MASK_RW_VER_10) &
2553 			~(intrs & INTERRUPT_MASK_RW_VER_10);
2554 		set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2555 
2556 	} else {
2557 		set &= ~intrs;
2558 	}
2559 
2560 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2561 }
2562 
2563 /**
2564  * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2565  * descriptor according to request
2566  * @lrbp: pointer to local reference block
2567  * @upiu_flags: flags required in the header
2568  * @cmd_dir: requests data direction
2569  * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2570  */
ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb * lrbp,u8 * upiu_flags,enum dma_data_direction cmd_dir,int ehs_length)2571 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags,
2572 					enum dma_data_direction cmd_dir, int ehs_length)
2573 {
2574 	struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2575 	struct request_desc_header *h = &req_desc->header;
2576 	enum utp_data_direction data_direction;
2577 
2578 	*h = (typeof(*h)){ };
2579 
2580 	if (cmd_dir == DMA_FROM_DEVICE) {
2581 		data_direction = UTP_DEVICE_TO_HOST;
2582 		*upiu_flags = UPIU_CMD_FLAGS_READ;
2583 	} else if (cmd_dir == DMA_TO_DEVICE) {
2584 		data_direction = UTP_HOST_TO_DEVICE;
2585 		*upiu_flags = UPIU_CMD_FLAGS_WRITE;
2586 	} else {
2587 		data_direction = UTP_NO_DATA_TRANSFER;
2588 		*upiu_flags = UPIU_CMD_FLAGS_NONE;
2589 	}
2590 
2591 	h->command_type = lrbp->command_type;
2592 	h->data_direction = data_direction;
2593 	h->ehs_length = ehs_length;
2594 
2595 	if (lrbp->intr_cmd)
2596 		h->interrupt = 1;
2597 
2598 	/* Prepare crypto related dwords */
2599 	ufshcd_prepare_req_desc_hdr_crypto(lrbp, h);
2600 
2601 	/*
2602 	 * assigning invalid value for command status. Controller
2603 	 * updates OCS on command completion, with the command
2604 	 * status
2605 	 */
2606 	h->ocs = OCS_INVALID_COMMAND_STATUS;
2607 
2608 	req_desc->prd_table_length = 0;
2609 }
2610 
2611 /**
2612  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2613  * for scsi commands
2614  * @lrbp: local reference block pointer
2615  * @upiu_flags: flags
2616  */
2617 static
ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb * lrbp,u8 upiu_flags)2618 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2619 {
2620 	struct scsi_cmnd *cmd = lrbp->cmd;
2621 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2622 	unsigned short cdb_len;
2623 
2624 	ucd_req_ptr->header = (struct utp_upiu_header){
2625 		.transaction_code = UPIU_TRANSACTION_COMMAND,
2626 		.flags = upiu_flags,
2627 		.lun = lrbp->lun,
2628 		.task_tag = lrbp->task_tag,
2629 		.command_set_type = UPIU_COMMAND_SET_TYPE_SCSI,
2630 	};
2631 
2632 	ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2633 
2634 	cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2635 	memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2636 	memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2637 
2638 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2639 }
2640 
2641 /**
2642  * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2643  * @hba: UFS hba
2644  * @lrbp: local reference block pointer
2645  * @upiu_flags: flags
2646  */
ufshcd_prepare_utp_query_req_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,u8 upiu_flags)2647 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2648 				struct ufshcd_lrb *lrbp, u8 upiu_flags)
2649 {
2650 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2651 	struct ufs_query *query = &hba->dev_cmd.query;
2652 	u16 len = be16_to_cpu(query->request.upiu_req.length);
2653 
2654 	/* Query request header */
2655 	ucd_req_ptr->header = (struct utp_upiu_header){
2656 		.transaction_code = UPIU_TRANSACTION_QUERY_REQ,
2657 		.flags = upiu_flags,
2658 		.lun = lrbp->lun,
2659 		.task_tag = lrbp->task_tag,
2660 		.query_function = query->request.query_func,
2661 		/* Data segment length only need for WRITE_DESC */
2662 		.data_segment_length =
2663 			query->request.upiu_req.opcode ==
2664 					UPIU_QUERY_OPCODE_WRITE_DESC ?
2665 				cpu_to_be16(len) :
2666 				0,
2667 	};
2668 
2669 	/* Copy the Query Request buffer as is */
2670 	memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2671 			QUERY_OSF_SIZE);
2672 
2673 	/* Copy the Descriptor */
2674 	if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2675 		memcpy(ucd_req_ptr + 1, query->descriptor, len);
2676 
2677 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2678 }
2679 
ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb * lrbp)2680 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2681 {
2682 	struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2683 
2684 	memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2685 
2686 	ucd_req_ptr->header = (struct utp_upiu_header){
2687 		.transaction_code = UPIU_TRANSACTION_NOP_OUT,
2688 		.task_tag = lrbp->task_tag,
2689 	};
2690 
2691 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2692 }
2693 
2694 /**
2695  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2696  *			     for Device Management Purposes
2697  * @hba: per adapter instance
2698  * @lrbp: pointer to local reference block
2699  *
2700  * Return: 0 upon success; < 0 upon failure.
2701  */
ufshcd_compose_devman_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2702 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2703 				      struct ufshcd_lrb *lrbp)
2704 {
2705 	u8 upiu_flags;
2706 	int ret = 0;
2707 
2708 	if (hba->ufs_version <= ufshci_version(1, 1))
2709 		lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2710 	else
2711 		lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2712 
2713 	ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
2714 	if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2715 		ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2716 	else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2717 		ufshcd_prepare_utp_nop_upiu(lrbp);
2718 	else
2719 		ret = -EINVAL;
2720 
2721 	return ret;
2722 }
2723 
2724 /**
2725  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2726  *			   for SCSI Purposes
2727  * @hba: per adapter instance
2728  * @lrbp: pointer to local reference block
2729  *
2730  * Return: 0 upon success; < 0 upon failure.
2731  */
ufshcd_comp_scsi_upiu(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)2732 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2733 {
2734 	u8 upiu_flags;
2735 	int ret = 0;
2736 
2737 	if (hba->ufs_version <= ufshci_version(1, 1))
2738 		lrbp->command_type = UTP_CMD_TYPE_SCSI;
2739 	else
2740 		lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2741 
2742 	if (likely(lrbp->cmd)) {
2743 		ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0);
2744 		ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2745 	} else {
2746 		ret = -EINVAL;
2747 	}
2748 
2749 	return ret;
2750 }
2751 
2752 /**
2753  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2754  * @upiu_wlun_id: UPIU W-LUN id
2755  *
2756  * Return: SCSI W-LUN id.
2757  */
ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)2758 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2759 {
2760 	return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2761 }
2762 
is_device_wlun(struct scsi_device * sdev)2763 static inline bool is_device_wlun(struct scsi_device *sdev)
2764 {
2765 	return sdev->lun ==
2766 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2767 }
2768 
2769 /*
2770  * Associate the UFS controller queue with the default and poll HCTX types.
2771  * Initialize the mq_map[] arrays.
2772  */
ufshcd_map_queues(struct Scsi_Host * shost)2773 static void ufshcd_map_queues(struct Scsi_Host *shost)
2774 {
2775 	struct ufs_hba *hba = shost_priv(shost);
2776 	int i, queue_offset = 0;
2777 
2778 	if (!is_mcq_supported(hba)) {
2779 		hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2780 		hba->nr_queues[HCTX_TYPE_READ] = 0;
2781 		hba->nr_queues[HCTX_TYPE_POLL] = 1;
2782 		hba->nr_hw_queues = 1;
2783 	}
2784 
2785 	for (i = 0; i < shost->nr_maps; i++) {
2786 		struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2787 
2788 		map->nr_queues = hba->nr_queues[i];
2789 		if (!map->nr_queues)
2790 			continue;
2791 		map->queue_offset = queue_offset;
2792 		if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
2793 			map->queue_offset = 0;
2794 
2795 		blk_mq_map_queues(map);
2796 		queue_offset += map->nr_queues;
2797 	}
2798 }
2799 
ufshcd_init_lrb(struct ufs_hba * hba,struct ufshcd_lrb * lrb,int i)2800 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2801 {
2802 	struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2803 		i * ufshcd_get_ucd_size(hba);
2804 	struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2805 	dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2806 		i * ufshcd_get_ucd_size(hba);
2807 	u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset);
2808 	u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset);
2809 
2810 	lrb->utr_descriptor_ptr = utrdlp + i;
2811 	lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2812 		i * sizeof(struct utp_transfer_req_desc);
2813 	lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2814 	lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2815 	lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2816 	lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2817 	lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2818 	lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2819 }
2820 
2821 /**
2822  * ufshcd_queuecommand - main entry point for SCSI requests
2823  * @host: SCSI host pointer
2824  * @cmd: command from SCSI Midlayer
2825  *
2826  * Return: 0 for success, non-zero in case of failure.
2827  */
ufshcd_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)2828 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2829 {
2830 	struct ufs_hba *hba = shost_priv(host);
2831 	int tag = scsi_cmd_to_rq(cmd)->tag;
2832 	struct ufshcd_lrb *lrbp;
2833 	int err = 0;
2834 	struct ufs_hw_queue *hwq = NULL;
2835 
2836 	WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
2837 
2838 	switch (hba->ufshcd_state) {
2839 	case UFSHCD_STATE_OPERATIONAL:
2840 		break;
2841 	case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2842 		/*
2843 		 * SCSI error handler can call ->queuecommand() while UFS error
2844 		 * handler is in progress. Error interrupts could change the
2845 		 * state from UFSHCD_STATE_RESET to
2846 		 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2847 		 * being issued in that case.
2848 		 */
2849 		if (ufshcd_eh_in_progress(hba)) {
2850 			err = SCSI_MLQUEUE_HOST_BUSY;
2851 			goto out;
2852 		}
2853 		break;
2854 	case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2855 		/*
2856 		 * pm_runtime_get_sync() is used at error handling preparation
2857 		 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2858 		 * PM ops, it can never be finished if we let SCSI layer keep
2859 		 * retrying it, which gets err handler stuck forever. Neither
2860 		 * can we let the scsi cmd pass through, because UFS is in bad
2861 		 * state, the scsi cmd may eventually time out, which will get
2862 		 * err handler blocked for too long. So, just fail the scsi cmd
2863 		 * sent from PM ops, err handler can recover PM error anyways.
2864 		 */
2865 		if (hba->pm_op_in_progress) {
2866 			hba->force_reset = true;
2867 			set_host_byte(cmd, DID_BAD_TARGET);
2868 			scsi_done(cmd);
2869 			goto out;
2870 		}
2871 		fallthrough;
2872 	case UFSHCD_STATE_RESET:
2873 		err = SCSI_MLQUEUE_HOST_BUSY;
2874 		goto out;
2875 	case UFSHCD_STATE_ERROR:
2876 		set_host_byte(cmd, DID_ERROR);
2877 		scsi_done(cmd);
2878 		goto out;
2879 	}
2880 
2881 	hba->req_abort_count = 0;
2882 
2883 	ufshcd_hold(hba);
2884 
2885 	lrbp = &hba->lrb[tag];
2886 	lrbp->cmd = cmd;
2887 	lrbp->task_tag = tag;
2888 	lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2889 	lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2890 
2891 	ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
2892 
2893 	lrbp->req_abort_skip = false;
2894 
2895 	ufshcd_comp_scsi_upiu(hba, lrbp);
2896 
2897 	err = ufshcd_map_sg(hba, lrbp);
2898 	if (err) {
2899 		ufshcd_release(hba);
2900 		goto out;
2901 	}
2902 
2903 	if (is_mcq_enabled(hba))
2904 		hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
2905 
2906 	ufshcd_send_command(hba, tag, hwq);
2907 
2908 out:
2909 	if (ufs_trigger_eh()) {
2910 		unsigned long flags;
2911 
2912 		spin_lock_irqsave(hba->host->host_lock, flags);
2913 		ufshcd_schedule_eh_work(hba);
2914 		spin_unlock_irqrestore(hba->host->host_lock, flags);
2915 	}
2916 
2917 	return err;
2918 }
2919 
ufshcd_compose_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,enum dev_cmd_type cmd_type,int tag)2920 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2921 		struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2922 {
2923 	lrbp->cmd = NULL;
2924 	lrbp->task_tag = tag;
2925 	lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2926 	lrbp->intr_cmd = true; /* No interrupt aggregation */
2927 	ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2928 	hba->dev_cmd.type = cmd_type;
2929 
2930 	return ufshcd_compose_devman_upiu(hba, lrbp);
2931 }
2932 
2933 /*
2934  * Check with the block layer if the command is inflight
2935  * @cmd: command to check.
2936  *
2937  * Return: true if command is inflight; false if not.
2938  */
ufshcd_cmd_inflight(struct scsi_cmnd * cmd)2939 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd)
2940 {
2941 	struct request *rq;
2942 
2943 	if (!cmd)
2944 		return false;
2945 
2946 	rq = scsi_cmd_to_rq(cmd);
2947 	if (!blk_mq_request_started(rq))
2948 		return false;
2949 
2950 	return true;
2951 }
2952 
2953 /*
2954  * Clear the pending command in the controller and wait until
2955  * the controller confirms that the command has been cleared.
2956  * @hba: per adapter instance
2957  * @task_tag: The tag number of the command to be cleared.
2958  */
ufshcd_clear_cmd(struct ufs_hba * hba,u32 task_tag)2959 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag)
2960 {
2961 	u32 mask;
2962 	unsigned long flags;
2963 	int err;
2964 
2965 	if (is_mcq_enabled(hba)) {
2966 		/*
2967 		 * MCQ mode. Clean up the MCQ resources similar to
2968 		 * what the ufshcd_utrl_clear() does for SDB mode.
2969 		 */
2970 		err = ufshcd_mcq_sq_cleanup(hba, task_tag);
2971 		if (err) {
2972 			dev_err(hba->dev, "%s: failed tag=%d. err=%d\n",
2973 				__func__, task_tag, err);
2974 			return err;
2975 		}
2976 		return 0;
2977 	}
2978 
2979 	mask = 1U << task_tag;
2980 
2981 	/* clear outstanding transaction before retry */
2982 	spin_lock_irqsave(hba->host->host_lock, flags);
2983 	ufshcd_utrl_clear(hba, mask);
2984 	spin_unlock_irqrestore(hba->host->host_lock, flags);
2985 
2986 	/*
2987 	 * wait for h/w to clear corresponding bit in door-bell.
2988 	 * max. wait is 1 sec.
2989 	 */
2990 	return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
2991 					mask, ~mask, 1000, 1000);
2992 }
2993 
2994 /**
2995  * ufshcd_dev_cmd_completion() - handles device management command responses
2996  * @hba: per adapter instance
2997  * @lrbp: pointer to local reference block
2998  *
2999  * Return: 0 upon success; < 0 upon failure.
3000  */
3001 static int
ufshcd_dev_cmd_completion(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)3002 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3003 {
3004 	enum upiu_response_transaction resp;
3005 	int err = 0;
3006 
3007 	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
3008 	resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3009 
3010 	switch (resp) {
3011 	case UPIU_TRANSACTION_NOP_IN:
3012 		if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3013 			err = -EINVAL;
3014 			dev_err(hba->dev, "%s: unexpected response %x\n",
3015 					__func__, resp);
3016 		}
3017 		break;
3018 	case UPIU_TRANSACTION_QUERY_RSP: {
3019 		u8 response = lrbp->ucd_rsp_ptr->header.response;
3020 
3021 		if (response == 0)
3022 			err = ufshcd_copy_query_response(hba, lrbp);
3023 		break;
3024 	}
3025 	case UPIU_TRANSACTION_REJECT_UPIU:
3026 		/* TODO: handle Reject UPIU Response */
3027 		err = -EPERM;
3028 		dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3029 				__func__);
3030 		break;
3031 	case UPIU_TRANSACTION_RESPONSE:
3032 		if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3033 			err = -EINVAL;
3034 			dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3035 		}
3036 		break;
3037 	default:
3038 		err = -EINVAL;
3039 		dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3040 				__func__, resp);
3041 		break;
3042 	}
3043 
3044 	return err;
3045 }
3046 
ufshcd_wait_for_dev_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,int max_timeout)3047 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
3048 		struct ufshcd_lrb *lrbp, int max_timeout)
3049 {
3050 	unsigned long time_left = msecs_to_jiffies(max_timeout);
3051 	unsigned long flags;
3052 	bool pending;
3053 	int err;
3054 
3055 retry:
3056 	time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
3057 						time_left);
3058 
3059 	if (likely(time_left)) {
3060 		/*
3061 		 * The completion handler called complete() and the caller of
3062 		 * this function still owns the @lrbp tag so the code below does
3063 		 * not trigger any race conditions.
3064 		 */
3065 		hba->dev_cmd.complete = NULL;
3066 		err = ufshcd_get_tr_ocs(lrbp, NULL);
3067 		if (!err)
3068 			err = ufshcd_dev_cmd_completion(hba, lrbp);
3069 	} else {
3070 		err = -ETIMEDOUT;
3071 		dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3072 			__func__, lrbp->task_tag);
3073 
3074 		/* MCQ mode */
3075 		if (is_mcq_enabled(hba)) {
3076 			/* successfully cleared the command, retry if needed */
3077 			if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0)
3078 				err = -EAGAIN;
3079 			hba->dev_cmd.complete = NULL;
3080 			return err;
3081 		}
3082 
3083 		/* SDB mode */
3084 		if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) {
3085 			/* successfully cleared the command, retry if needed */
3086 			err = -EAGAIN;
3087 			/*
3088 			 * Since clearing the command succeeded we also need to
3089 			 * clear the task tag bit from the outstanding_reqs
3090 			 * variable.
3091 			 */
3092 			spin_lock_irqsave(&hba->outstanding_lock, flags);
3093 			pending = test_bit(lrbp->task_tag,
3094 					   &hba->outstanding_reqs);
3095 			if (pending) {
3096 				hba->dev_cmd.complete = NULL;
3097 				__clear_bit(lrbp->task_tag,
3098 					    &hba->outstanding_reqs);
3099 			}
3100 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3101 
3102 			if (!pending) {
3103 				/*
3104 				 * The completion handler ran while we tried to
3105 				 * clear the command.
3106 				 */
3107 				time_left = 1;
3108 				goto retry;
3109 			}
3110 		} else {
3111 			dev_err(hba->dev, "%s: failed to clear tag %d\n",
3112 				__func__, lrbp->task_tag);
3113 
3114 			spin_lock_irqsave(&hba->outstanding_lock, flags);
3115 			pending = test_bit(lrbp->task_tag,
3116 					   &hba->outstanding_reqs);
3117 			if (pending)
3118 				hba->dev_cmd.complete = NULL;
3119 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3120 
3121 			if (!pending) {
3122 				/*
3123 				 * The completion handler ran while we tried to
3124 				 * clear the command.
3125 				 */
3126 				time_left = 1;
3127 				goto retry;
3128 			}
3129 		}
3130 	}
3131 
3132 	return err;
3133 }
3134 
3135 /**
3136  * ufshcd_exec_dev_cmd - API for sending device management requests
3137  * @hba: UFS hba
3138  * @cmd_type: specifies the type (NOP, Query...)
3139  * @timeout: timeout in milliseconds
3140  *
3141  * Return: 0 upon success; < 0 upon failure.
3142  *
3143  * NOTE: Since there is only one available tag for device management commands,
3144  * it is expected you hold the hba->dev_cmd.lock mutex.
3145  */
ufshcd_exec_dev_cmd(struct ufs_hba * hba,enum dev_cmd_type cmd_type,int timeout)3146 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3147 		enum dev_cmd_type cmd_type, int timeout)
3148 {
3149 	DECLARE_COMPLETION_ONSTACK(wait);
3150 	const u32 tag = hba->reserved_slot;
3151 	struct ufshcd_lrb *lrbp;
3152 	int err;
3153 
3154 	/* Protects use of hba->reserved_slot. */
3155 	lockdep_assert_held(&hba->dev_cmd.lock);
3156 
3157 	down_read(&hba->clk_scaling_lock);
3158 
3159 	lrbp = &hba->lrb[tag];
3160 	lrbp->cmd = NULL;
3161 	err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3162 	if (unlikely(err))
3163 		goto out;
3164 
3165 	hba->dev_cmd.complete = &wait;
3166 
3167 	ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3168 
3169 	ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
3170 	err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3171 	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3172 				    (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3173 
3174 out:
3175 	up_read(&hba->clk_scaling_lock);
3176 	return err;
3177 }
3178 
3179 /**
3180  * ufshcd_init_query() - init the query response and request parameters
3181  * @hba: per-adapter instance
3182  * @request: address of the request pointer to be initialized
3183  * @response: address of the response pointer to be initialized
3184  * @opcode: operation to perform
3185  * @idn: flag idn to access
3186  * @index: LU number to access
3187  * @selector: query/flag/descriptor further identification
3188  */
ufshcd_init_query(struct ufs_hba * hba,struct ufs_query_req ** request,struct ufs_query_res ** response,enum query_opcode opcode,u8 idn,u8 index,u8 selector)3189 static inline void ufshcd_init_query(struct ufs_hba *hba,
3190 		struct ufs_query_req **request, struct ufs_query_res **response,
3191 		enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3192 {
3193 	*request = &hba->dev_cmd.query.request;
3194 	*response = &hba->dev_cmd.query.response;
3195 	memset(*request, 0, sizeof(struct ufs_query_req));
3196 	memset(*response, 0, sizeof(struct ufs_query_res));
3197 	(*request)->upiu_req.opcode = opcode;
3198 	(*request)->upiu_req.idn = idn;
3199 	(*request)->upiu_req.index = index;
3200 	(*request)->upiu_req.selector = selector;
3201 }
3202 
ufshcd_query_flag_retry(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3203 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3204 	enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3205 {
3206 	int ret;
3207 	int retries;
3208 
3209 	for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3210 		ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3211 		if (ret)
3212 			dev_dbg(hba->dev,
3213 				"%s: failed with error %d, retries %d\n",
3214 				__func__, ret, retries);
3215 		else
3216 			break;
3217 	}
3218 
3219 	if (ret)
3220 		dev_err(hba->dev,
3221 			"%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3222 			__func__, opcode, idn, ret, retries);
3223 	return ret;
3224 }
3225 
3226 /**
3227  * ufshcd_query_flag() - API function for sending flag query requests
3228  * @hba: per-adapter instance
3229  * @opcode: flag query to perform
3230  * @idn: flag idn to access
3231  * @index: flag index to access
3232  * @flag_res: the flag value after the query request completes
3233  *
3234  * Return: 0 for success, non-zero in case of failure.
3235  */
ufshcd_query_flag(struct ufs_hba * hba,enum query_opcode opcode,enum flag_idn idn,u8 index,bool * flag_res)3236 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3237 			enum flag_idn idn, u8 index, bool *flag_res)
3238 {
3239 	struct ufs_query_req *request = NULL;
3240 	struct ufs_query_res *response = NULL;
3241 	int err, selector = 0;
3242 	int timeout = QUERY_REQ_TIMEOUT;
3243 
3244 	BUG_ON(!hba);
3245 
3246 	ufshcd_hold(hba);
3247 	mutex_lock(&hba->dev_cmd.lock);
3248 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3249 			selector);
3250 
3251 	switch (opcode) {
3252 	case UPIU_QUERY_OPCODE_SET_FLAG:
3253 	case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3254 	case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3255 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3256 		break;
3257 	case UPIU_QUERY_OPCODE_READ_FLAG:
3258 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3259 		if (!flag_res) {
3260 			/* No dummy reads */
3261 			dev_err(hba->dev, "%s: Invalid argument for read request\n",
3262 					__func__);
3263 			err = -EINVAL;
3264 			goto out_unlock;
3265 		}
3266 		break;
3267 	default:
3268 		dev_err(hba->dev,
3269 			"%s: Expected query flag opcode but got = %d\n",
3270 			__func__, opcode);
3271 		err = -EINVAL;
3272 		goto out_unlock;
3273 	}
3274 
3275 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3276 
3277 	if (err) {
3278 		dev_err(hba->dev,
3279 			"%s: Sending flag query for idn %d failed, err = %d\n",
3280 			__func__, idn, err);
3281 		goto out_unlock;
3282 	}
3283 
3284 	if (flag_res)
3285 		*flag_res = (be32_to_cpu(response->upiu_res.value) &
3286 				MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3287 
3288 out_unlock:
3289 	mutex_unlock(&hba->dev_cmd.lock);
3290 	ufshcd_release(hba);
3291 	return err;
3292 }
3293 
3294 /**
3295  * ufshcd_query_attr - API function for sending attribute requests
3296  * @hba: per-adapter instance
3297  * @opcode: attribute opcode
3298  * @idn: attribute idn to access
3299  * @index: index field
3300  * @selector: selector field
3301  * @attr_val: the attribute value after the query request completes
3302  *
3303  * Return: 0 for success, non-zero in case of failure.
3304 */
ufshcd_query_attr(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3305 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3306 		      enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3307 {
3308 	struct ufs_query_req *request = NULL;
3309 	struct ufs_query_res *response = NULL;
3310 	int err;
3311 
3312 	BUG_ON(!hba);
3313 
3314 	if (!attr_val) {
3315 		dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3316 				__func__, opcode);
3317 		return -EINVAL;
3318 	}
3319 
3320 	ufshcd_hold(hba);
3321 
3322 	mutex_lock(&hba->dev_cmd.lock);
3323 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3324 			selector);
3325 
3326 	switch (opcode) {
3327 	case UPIU_QUERY_OPCODE_WRITE_ATTR:
3328 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3329 		request->upiu_req.value = cpu_to_be32(*attr_val);
3330 		break;
3331 	case UPIU_QUERY_OPCODE_READ_ATTR:
3332 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3333 		break;
3334 	default:
3335 		dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3336 				__func__, opcode);
3337 		err = -EINVAL;
3338 		goto out_unlock;
3339 	}
3340 
3341 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3342 
3343 	if (err) {
3344 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3345 				__func__, opcode, idn, index, err);
3346 		goto out_unlock;
3347 	}
3348 
3349 	*attr_val = be32_to_cpu(response->upiu_res.value);
3350 
3351 out_unlock:
3352 	mutex_unlock(&hba->dev_cmd.lock);
3353 	ufshcd_release(hba);
3354 	return err;
3355 }
3356 
3357 /**
3358  * ufshcd_query_attr_retry() - API function for sending query
3359  * attribute with retries
3360  * @hba: per-adapter instance
3361  * @opcode: attribute opcode
3362  * @idn: attribute idn to access
3363  * @index: index field
3364  * @selector: selector field
3365  * @attr_val: the attribute value after the query request
3366  * completes
3367  *
3368  * Return: 0 for success, non-zero in case of failure.
3369 */
ufshcd_query_attr_retry(struct ufs_hba * hba,enum query_opcode opcode,enum attr_idn idn,u8 index,u8 selector,u32 * attr_val)3370 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3371 	enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3372 	u32 *attr_val)
3373 {
3374 	int ret = 0;
3375 	u32 retries;
3376 
3377 	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3378 		ret = ufshcd_query_attr(hba, opcode, idn, index,
3379 						selector, attr_val);
3380 		if (ret)
3381 			dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3382 				__func__, ret, retries);
3383 		else
3384 			break;
3385 	}
3386 
3387 	if (ret)
3388 		dev_err(hba->dev,
3389 			"%s: query attribute, idn %d, failed with error %d after %d retries\n",
3390 			__func__, idn, ret, QUERY_REQ_RETRIES);
3391 	return ret;
3392 }
3393 
__ufshcd_query_descriptor(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3394 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3395 			enum query_opcode opcode, enum desc_idn idn, u8 index,
3396 			u8 selector, u8 *desc_buf, int *buf_len)
3397 {
3398 	struct ufs_query_req *request = NULL;
3399 	struct ufs_query_res *response = NULL;
3400 	int err;
3401 
3402 	BUG_ON(!hba);
3403 
3404 	if (!desc_buf) {
3405 		dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3406 				__func__, opcode);
3407 		return -EINVAL;
3408 	}
3409 
3410 	if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3411 		dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3412 				__func__, *buf_len);
3413 		return -EINVAL;
3414 	}
3415 
3416 	ufshcd_hold(hba);
3417 
3418 	mutex_lock(&hba->dev_cmd.lock);
3419 	ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3420 			selector);
3421 	hba->dev_cmd.query.descriptor = desc_buf;
3422 	request->upiu_req.length = cpu_to_be16(*buf_len);
3423 
3424 	switch (opcode) {
3425 	case UPIU_QUERY_OPCODE_WRITE_DESC:
3426 		request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3427 		break;
3428 	case UPIU_QUERY_OPCODE_READ_DESC:
3429 		request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3430 		break;
3431 	default:
3432 		dev_err(hba->dev,
3433 				"%s: Expected query descriptor opcode but got = 0x%.2x\n",
3434 				__func__, opcode);
3435 		err = -EINVAL;
3436 		goto out_unlock;
3437 	}
3438 
3439 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3440 
3441 	if (err) {
3442 		dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3443 				__func__, opcode, idn, index, err);
3444 		goto out_unlock;
3445 	}
3446 
3447 	*buf_len = be16_to_cpu(response->upiu_res.length);
3448 
3449 out_unlock:
3450 	hba->dev_cmd.query.descriptor = NULL;
3451 	mutex_unlock(&hba->dev_cmd.lock);
3452 	ufshcd_release(hba);
3453 	return err;
3454 }
3455 
3456 /**
3457  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3458  * @hba: per-adapter instance
3459  * @opcode: attribute opcode
3460  * @idn: attribute idn to access
3461  * @index: index field
3462  * @selector: selector field
3463  * @desc_buf: the buffer that contains the descriptor
3464  * @buf_len: length parameter passed to the device
3465  *
3466  * The buf_len parameter will contain, on return, the length parameter
3467  * received on the response.
3468  *
3469  * Return: 0 for success, non-zero in case of failure.
3470  */
ufshcd_query_descriptor_retry(struct ufs_hba * hba,enum query_opcode opcode,enum desc_idn idn,u8 index,u8 selector,u8 * desc_buf,int * buf_len)3471 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3472 				  enum query_opcode opcode,
3473 				  enum desc_idn idn, u8 index,
3474 				  u8 selector,
3475 				  u8 *desc_buf, int *buf_len)
3476 {
3477 	int err;
3478 	int retries;
3479 
3480 	for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3481 		err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3482 						selector, desc_buf, buf_len);
3483 		if (!err || err == -EINVAL)
3484 			break;
3485 	}
3486 
3487 	return err;
3488 }
3489 
3490 /**
3491  * ufshcd_read_desc_param - read the specified descriptor parameter
3492  * @hba: Pointer to adapter instance
3493  * @desc_id: descriptor idn value
3494  * @desc_index: descriptor index
3495  * @param_offset: offset of the parameter to read
3496  * @param_read_buf: pointer to buffer where parameter would be read
3497  * @param_size: sizeof(param_read_buf)
3498  *
3499  * Return: 0 in case of success, non-zero otherwise.
3500  */
ufshcd_read_desc_param(struct ufs_hba * hba,enum desc_idn desc_id,int desc_index,u8 param_offset,u8 * param_read_buf,u8 param_size)3501 int ufshcd_read_desc_param(struct ufs_hba *hba,
3502 			   enum desc_idn desc_id,
3503 			   int desc_index,
3504 			   u8 param_offset,
3505 			   u8 *param_read_buf,
3506 			   u8 param_size)
3507 {
3508 	int ret;
3509 	u8 *desc_buf;
3510 	int buff_len = QUERY_DESC_MAX_SIZE;
3511 	bool is_kmalloc = true;
3512 
3513 	/* Safety check */
3514 	if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3515 		return -EINVAL;
3516 
3517 	/* Check whether we need temp memory */
3518 	if (param_offset != 0 || param_size < buff_len) {
3519 		desc_buf = kzalloc(buff_len, GFP_KERNEL);
3520 		if (!desc_buf)
3521 			return -ENOMEM;
3522 	} else {
3523 		desc_buf = param_read_buf;
3524 		is_kmalloc = false;
3525 	}
3526 
3527 	/* Request for full descriptor */
3528 	ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3529 					    desc_id, desc_index, 0,
3530 					    desc_buf, &buff_len);
3531 	if (ret) {
3532 		dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3533 			__func__, desc_id, desc_index, param_offset, ret);
3534 		goto out;
3535 	}
3536 
3537 	/* Update descriptor length */
3538 	buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3539 
3540 	if (param_offset >= buff_len) {
3541 		dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3542 			__func__, param_offset, desc_id, buff_len);
3543 		ret = -EINVAL;
3544 		goto out;
3545 	}
3546 
3547 	/* Sanity check */
3548 	if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3549 		dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3550 			__func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3551 		ret = -EINVAL;
3552 		goto out;
3553 	}
3554 
3555 	if (is_kmalloc) {
3556 		/* Make sure we don't copy more data than available */
3557 		if (param_offset >= buff_len)
3558 			ret = -EINVAL;
3559 		else
3560 			memcpy(param_read_buf, &desc_buf[param_offset],
3561 			       min_t(u32, param_size, buff_len - param_offset));
3562 	}
3563 out:
3564 	if (is_kmalloc)
3565 		kfree(desc_buf);
3566 	return ret;
3567 }
3568 
3569 /**
3570  * struct uc_string_id - unicode string
3571  *
3572  * @len: size of this descriptor inclusive
3573  * @type: descriptor type
3574  * @uc: unicode string character
3575  */
3576 struct uc_string_id {
3577 	u8 len;
3578 	u8 type;
3579 	wchar_t uc[];
3580 } __packed;
3581 
3582 /* replace non-printable or non-ASCII characters with spaces */
ufshcd_remove_non_printable(u8 ch)3583 static inline char ufshcd_remove_non_printable(u8 ch)
3584 {
3585 	return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3586 }
3587 
3588 /**
3589  * ufshcd_read_string_desc - read string descriptor
3590  * @hba: pointer to adapter instance
3591  * @desc_index: descriptor index
3592  * @buf: pointer to buffer where descriptor would be read,
3593  *       the caller should free the memory.
3594  * @ascii: if true convert from unicode to ascii characters
3595  *         null terminated string.
3596  *
3597  * Return:
3598  * *      string size on success.
3599  * *      -ENOMEM: on allocation failure
3600  * *      -EINVAL: on a wrong parameter
3601  */
ufshcd_read_string_desc(struct ufs_hba * hba,u8 desc_index,u8 ** buf,bool ascii)3602 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3603 			    u8 **buf, bool ascii)
3604 {
3605 	struct uc_string_id *uc_str;
3606 	u8 *str;
3607 	int ret;
3608 
3609 	if (!buf)
3610 		return -EINVAL;
3611 
3612 	uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3613 	if (!uc_str)
3614 		return -ENOMEM;
3615 
3616 	ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3617 				     (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3618 	if (ret < 0) {
3619 		dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3620 			QUERY_REQ_RETRIES, ret);
3621 		str = NULL;
3622 		goto out;
3623 	}
3624 
3625 	if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3626 		dev_dbg(hba->dev, "String Desc is of zero length\n");
3627 		str = NULL;
3628 		ret = 0;
3629 		goto out;
3630 	}
3631 
3632 	if (ascii) {
3633 		ssize_t ascii_len;
3634 		int i;
3635 		/* remove header and divide by 2 to move from UTF16 to UTF8 */
3636 		ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3637 		str = kzalloc(ascii_len, GFP_KERNEL);
3638 		if (!str) {
3639 			ret = -ENOMEM;
3640 			goto out;
3641 		}
3642 
3643 		/*
3644 		 * the descriptor contains string in UTF16 format
3645 		 * we need to convert to utf-8 so it can be displayed
3646 		 */
3647 		ret = utf16s_to_utf8s(uc_str->uc,
3648 				      uc_str->len - QUERY_DESC_HDR_SIZE,
3649 				      UTF16_BIG_ENDIAN, str, ascii_len - 1);
3650 
3651 		/* replace non-printable or non-ASCII characters with spaces */
3652 		for (i = 0; i < ret; i++)
3653 			str[i] = ufshcd_remove_non_printable(str[i]);
3654 
3655 		str[ret++] = '\0';
3656 
3657 	} else {
3658 		str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3659 		if (!str) {
3660 			ret = -ENOMEM;
3661 			goto out;
3662 		}
3663 		ret = uc_str->len;
3664 	}
3665 out:
3666 	*buf = str;
3667 	kfree(uc_str);
3668 	return ret;
3669 }
3670 
3671 /**
3672  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3673  * @hba: Pointer to adapter instance
3674  * @lun: lun id
3675  * @param_offset: offset of the parameter to read
3676  * @param_read_buf: pointer to buffer where parameter would be read
3677  * @param_size: sizeof(param_read_buf)
3678  *
3679  * Return: 0 in case of success, non-zero otherwise.
3680  */
ufshcd_read_unit_desc_param(struct ufs_hba * hba,int lun,enum unit_desc_param param_offset,u8 * param_read_buf,u32 param_size)3681 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3682 					      int lun,
3683 					      enum unit_desc_param param_offset,
3684 					      u8 *param_read_buf,
3685 					      u32 param_size)
3686 {
3687 	/*
3688 	 * Unit descriptors are only available for general purpose LUs (LUN id
3689 	 * from 0 to 7) and RPMB Well known LU.
3690 	 */
3691 	if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3692 		return -EOPNOTSUPP;
3693 
3694 	return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3695 				      param_offset, param_read_buf, param_size);
3696 }
3697 
ufshcd_get_ref_clk_gating_wait(struct ufs_hba * hba)3698 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3699 {
3700 	int err = 0;
3701 	u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3702 
3703 	if (hba->dev_info.wspecversion >= 0x300) {
3704 		err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3705 				QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3706 				&gating_wait);
3707 		if (err)
3708 			dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3709 					 err, gating_wait);
3710 
3711 		if (gating_wait == 0) {
3712 			gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3713 			dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3714 					 gating_wait);
3715 		}
3716 
3717 		hba->dev_info.clk_gating_wait_us = gating_wait;
3718 	}
3719 
3720 	return err;
3721 }
3722 
3723 /**
3724  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3725  * @hba: per adapter instance
3726  *
3727  * 1. Allocate DMA memory for Command Descriptor array
3728  *	Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3729  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3730  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3731  *	(UTMRDL)
3732  * 4. Allocate memory for local reference block(lrb).
3733  *
3734  * Return: 0 for success, non-zero in case of failure.
3735  */
ufshcd_memory_alloc(struct ufs_hba * hba)3736 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3737 {
3738 	size_t utmrdl_size, utrdl_size, ucdl_size;
3739 
3740 	/* Allocate memory for UTP command descriptors */
3741 	ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs;
3742 	hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3743 						  ucdl_size,
3744 						  &hba->ucdl_dma_addr,
3745 						  GFP_KERNEL);
3746 
3747 	/*
3748 	 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3749 	 */
3750 	if (!hba->ucdl_base_addr ||
3751 	    WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3752 		dev_err(hba->dev,
3753 			"Command Descriptor Memory allocation failed\n");
3754 		goto out;
3755 	}
3756 
3757 	/*
3758 	 * Allocate memory for UTP Transfer descriptors
3759 	 * UFSHCI requires 1KB alignment of UTRD
3760 	 */
3761 	utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3762 	hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3763 						   utrdl_size,
3764 						   &hba->utrdl_dma_addr,
3765 						   GFP_KERNEL);
3766 	if (!hba->utrdl_base_addr ||
3767 	    WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) {
3768 		dev_err(hba->dev,
3769 			"Transfer Descriptor Memory allocation failed\n");
3770 		goto out;
3771 	}
3772 
3773 	/*
3774 	 * Skip utmrdl allocation; it may have been
3775 	 * allocated during first pass and not released during
3776 	 * MCQ memory allocation.
3777 	 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3778 	 */
3779 	if (hba->utmrdl_base_addr)
3780 		goto skip_utmrdl;
3781 	/*
3782 	 * Allocate memory for UTP Task Management descriptors
3783 	 * UFSHCI requires 1KB alignment of UTMRD
3784 	 */
3785 	utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3786 	hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3787 						    utmrdl_size,
3788 						    &hba->utmrdl_dma_addr,
3789 						    GFP_KERNEL);
3790 	if (!hba->utmrdl_base_addr ||
3791 	    WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) {
3792 		dev_err(hba->dev,
3793 		"Task Management Descriptor Memory allocation failed\n");
3794 		goto out;
3795 	}
3796 
3797 skip_utmrdl:
3798 	/* Allocate memory for local reference block */
3799 	hba->lrb = devm_kcalloc(hba->dev,
3800 				hba->nutrs, sizeof(struct ufshcd_lrb),
3801 				GFP_KERNEL);
3802 	if (!hba->lrb) {
3803 		dev_err(hba->dev, "LRB Memory allocation failed\n");
3804 		goto out;
3805 	}
3806 	return 0;
3807 out:
3808 	return -ENOMEM;
3809 }
3810 
3811 /**
3812  * ufshcd_host_memory_configure - configure local reference block with
3813  *				memory offsets
3814  * @hba: per adapter instance
3815  *
3816  * Configure Host memory space
3817  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3818  * address.
3819  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3820  * and PRDT offset.
3821  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3822  * into local reference block.
3823  */
ufshcd_host_memory_configure(struct ufs_hba * hba)3824 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3825 {
3826 	struct utp_transfer_req_desc *utrdlp;
3827 	dma_addr_t cmd_desc_dma_addr;
3828 	dma_addr_t cmd_desc_element_addr;
3829 	u16 response_offset;
3830 	u16 prdt_offset;
3831 	int cmd_desc_size;
3832 	int i;
3833 
3834 	utrdlp = hba->utrdl_base_addr;
3835 
3836 	response_offset =
3837 		offsetof(struct utp_transfer_cmd_desc, response_upiu);
3838 	prdt_offset =
3839 		offsetof(struct utp_transfer_cmd_desc, prd_table);
3840 
3841 	cmd_desc_size = ufshcd_get_ucd_size(hba);
3842 	cmd_desc_dma_addr = hba->ucdl_dma_addr;
3843 
3844 	for (i = 0; i < hba->nutrs; i++) {
3845 		/* Configure UTRD with command descriptor base address */
3846 		cmd_desc_element_addr =
3847 				(cmd_desc_dma_addr + (cmd_desc_size * i));
3848 		utrdlp[i].command_desc_base_addr =
3849 				cpu_to_le64(cmd_desc_element_addr);
3850 
3851 		/* Response upiu and prdt offset should be in double words */
3852 		if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3853 			utrdlp[i].response_upiu_offset =
3854 				cpu_to_le16(response_offset);
3855 			utrdlp[i].prd_table_offset =
3856 				cpu_to_le16(prdt_offset);
3857 			utrdlp[i].response_upiu_length =
3858 				cpu_to_le16(ALIGNED_UPIU_SIZE);
3859 		} else {
3860 			utrdlp[i].response_upiu_offset =
3861 				cpu_to_le16(response_offset >> 2);
3862 			utrdlp[i].prd_table_offset =
3863 				cpu_to_le16(prdt_offset >> 2);
3864 			utrdlp[i].response_upiu_length =
3865 				cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3866 		}
3867 
3868 		ufshcd_init_lrb(hba, &hba->lrb[i], i);
3869 	}
3870 }
3871 
3872 /**
3873  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3874  * @hba: per adapter instance
3875  *
3876  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3877  * in order to initialize the Unipro link startup procedure.
3878  * Once the Unipro links are up, the device connected to the controller
3879  * is detected.
3880  *
3881  * Return: 0 on success, non-zero value on failure.
3882  */
ufshcd_dme_link_startup(struct ufs_hba * hba)3883 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3884 {
3885 	struct uic_command uic_cmd = {0};
3886 	int ret;
3887 
3888 	uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3889 
3890 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3891 	if (ret)
3892 		dev_dbg(hba->dev,
3893 			"dme-link-startup: error code %d\n", ret);
3894 	return ret;
3895 }
3896 /**
3897  * ufshcd_dme_reset - UIC command for DME_RESET
3898  * @hba: per adapter instance
3899  *
3900  * DME_RESET command is issued in order to reset UniPro stack.
3901  * This function now deals with cold reset.
3902  *
3903  * Return: 0 on success, non-zero value on failure.
3904  */
ufshcd_dme_reset(struct ufs_hba * hba)3905 static int ufshcd_dme_reset(struct ufs_hba *hba)
3906 {
3907 	struct uic_command uic_cmd = {0};
3908 	int ret;
3909 
3910 	uic_cmd.command = UIC_CMD_DME_RESET;
3911 
3912 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3913 	if (ret)
3914 		dev_err(hba->dev,
3915 			"dme-reset: error code %d\n", ret);
3916 
3917 	return ret;
3918 }
3919 
ufshcd_dme_configure_adapt(struct ufs_hba * hba,int agreed_gear,int adapt_val)3920 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3921 			       int agreed_gear,
3922 			       int adapt_val)
3923 {
3924 	int ret;
3925 
3926 	if (agreed_gear < UFS_HS_G4)
3927 		adapt_val = PA_NO_ADAPT;
3928 
3929 	ret = ufshcd_dme_set(hba,
3930 			     UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3931 			     adapt_val);
3932 	return ret;
3933 }
3934 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3935 
3936 /**
3937  * ufshcd_dme_enable - UIC command for DME_ENABLE
3938  * @hba: per adapter instance
3939  *
3940  * DME_ENABLE command is issued in order to enable UniPro stack.
3941  *
3942  * Return: 0 on success, non-zero value on failure.
3943  */
ufshcd_dme_enable(struct ufs_hba * hba)3944 static int ufshcd_dme_enable(struct ufs_hba *hba)
3945 {
3946 	struct uic_command uic_cmd = {0};
3947 	int ret;
3948 
3949 	uic_cmd.command = UIC_CMD_DME_ENABLE;
3950 
3951 	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3952 	if (ret)
3953 		dev_err(hba->dev,
3954 			"dme-enable: error code %d\n", ret);
3955 
3956 	return ret;
3957 }
3958 
ufshcd_add_delay_before_dme_cmd(struct ufs_hba * hba)3959 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3960 {
3961 	#define MIN_DELAY_BEFORE_DME_CMDS_US	1000
3962 	unsigned long min_sleep_time_us;
3963 
3964 	if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3965 		return;
3966 
3967 	/*
3968 	 * last_dme_cmd_tstamp will be 0 only for 1st call to
3969 	 * this function
3970 	 */
3971 	if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3972 		min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3973 	} else {
3974 		unsigned long delta =
3975 			(unsigned long) ktime_to_us(
3976 				ktime_sub(ktime_get(),
3977 				hba->last_dme_cmd_tstamp));
3978 
3979 		if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3980 			min_sleep_time_us =
3981 				MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3982 		else
3983 			min_sleep_time_us = 0; /* no more delay required */
3984 	}
3985 
3986 	if (min_sleep_time_us > 0) {
3987 		/* allow sleep for extra 50us if needed */
3988 		usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3989 	}
3990 
3991 	/* update the last_dme_cmd_tstamp */
3992 	hba->last_dme_cmd_tstamp = ktime_get();
3993 }
3994 
3995 /**
3996  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3997  * @hba: per adapter instance
3998  * @attr_sel: uic command argument1
3999  * @attr_set: attribute set type as uic command argument2
4000  * @mib_val: setting value as uic command argument3
4001  * @peer: indicate whether peer or local
4002  *
4003  * Return: 0 on success, non-zero value on failure.
4004  */
ufshcd_dme_set_attr(struct ufs_hba * hba,u32 attr_sel,u8 attr_set,u32 mib_val,u8 peer)4005 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
4006 			u8 attr_set, u32 mib_val, u8 peer)
4007 {
4008 	struct uic_command uic_cmd = {0};
4009 	static const char *const action[] = {
4010 		"dme-set",
4011 		"dme-peer-set"
4012 	};
4013 	const char *set = action[!!peer];
4014 	int ret;
4015 	int retries = UFS_UIC_COMMAND_RETRIES;
4016 
4017 	uic_cmd.command = peer ?
4018 		UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
4019 	uic_cmd.argument1 = attr_sel;
4020 	uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
4021 	uic_cmd.argument3 = mib_val;
4022 
4023 	do {
4024 		/* for peer attributes we retry upon failure */
4025 		ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4026 		if (ret)
4027 			dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4028 				set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4029 	} while (ret && peer && --retries);
4030 
4031 	if (ret)
4032 		dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4033 			set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4034 			UFS_UIC_COMMAND_RETRIES - retries);
4035 
4036 	return ret;
4037 }
4038 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4039 
4040 /**
4041  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4042  * @hba: per adapter instance
4043  * @attr_sel: uic command argument1
4044  * @mib_val: the value of the attribute as returned by the UIC command
4045  * @peer: indicate whether peer or local
4046  *
4047  * Return: 0 on success, non-zero value on failure.
4048  */
ufshcd_dme_get_attr(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val,u8 peer)4049 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4050 			u32 *mib_val, u8 peer)
4051 {
4052 	struct uic_command uic_cmd = {0};
4053 	static const char *const action[] = {
4054 		"dme-get",
4055 		"dme-peer-get"
4056 	};
4057 	const char *get = action[!!peer];
4058 	int ret;
4059 	int retries = UFS_UIC_COMMAND_RETRIES;
4060 	struct ufs_pa_layer_attr orig_pwr_info;
4061 	struct ufs_pa_layer_attr temp_pwr_info;
4062 	bool pwr_mode_change = false;
4063 
4064 	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4065 		orig_pwr_info = hba->pwr_info;
4066 		temp_pwr_info = orig_pwr_info;
4067 
4068 		if (orig_pwr_info.pwr_tx == FAST_MODE ||
4069 		    orig_pwr_info.pwr_rx == FAST_MODE) {
4070 			temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4071 			temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4072 			pwr_mode_change = true;
4073 		} else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4074 		    orig_pwr_info.pwr_rx == SLOW_MODE) {
4075 			temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4076 			temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4077 			pwr_mode_change = true;
4078 		}
4079 		if (pwr_mode_change) {
4080 			ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
4081 			if (ret)
4082 				goto out;
4083 		}
4084 	}
4085 
4086 	uic_cmd.command = peer ?
4087 		UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
4088 	uic_cmd.argument1 = attr_sel;
4089 
4090 	do {
4091 		/* for peer attributes we retry upon failure */
4092 		ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4093 		if (ret)
4094 			dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4095 				get, UIC_GET_ATTR_ID(attr_sel), ret);
4096 	} while (ret && peer && --retries);
4097 
4098 	if (ret)
4099 		dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4100 			get, UIC_GET_ATTR_ID(attr_sel),
4101 			UFS_UIC_COMMAND_RETRIES - retries);
4102 
4103 	if (mib_val && !ret)
4104 		*mib_val = uic_cmd.argument3;
4105 
4106 	if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4107 	    && pwr_mode_change)
4108 		ufshcd_change_power_mode(hba, &orig_pwr_info);
4109 out:
4110 	return ret;
4111 }
4112 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4113 
4114 /**
4115  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4116  * state) and waits for it to take effect.
4117  *
4118  * @hba: per adapter instance
4119  * @cmd: UIC command to execute
4120  *
4121  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4122  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4123  * and device UniPro link and hence it's final completion would be indicated by
4124  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4125  * addition to normal UIC command completion Status (UCCS). This function only
4126  * returns after the relevant status bits indicate the completion.
4127  *
4128  * Return: 0 on success, non-zero value on failure.
4129  */
ufshcd_uic_pwr_ctrl(struct ufs_hba * hba,struct uic_command * cmd)4130 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4131 {
4132 	DECLARE_COMPLETION_ONSTACK(uic_async_done);
4133 	unsigned long flags;
4134 	u8 status;
4135 	int ret;
4136 	bool reenable_intr = false;
4137 
4138 	mutex_lock(&hba->uic_cmd_mutex);
4139 	ufshcd_add_delay_before_dme_cmd(hba);
4140 
4141 	spin_lock_irqsave(hba->host->host_lock, flags);
4142 	if (ufshcd_is_link_broken(hba)) {
4143 		ret = -ENOLINK;
4144 		goto out_unlock;
4145 	}
4146 	hba->uic_async_done = &uic_async_done;
4147 	if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4148 		ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4149 		/*
4150 		 * Make sure UIC command completion interrupt is disabled before
4151 		 * issuing UIC command.
4152 		 */
4153 		ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
4154 		reenable_intr = true;
4155 	}
4156 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4157 	ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4158 	if (ret) {
4159 		dev_err(hba->dev,
4160 			"pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4161 			cmd->command, cmd->argument3, ret);
4162 		goto out;
4163 	}
4164 
4165 	if (!wait_for_completion_timeout(hba->uic_async_done,
4166 					 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4167 		dev_err(hba->dev,
4168 			"pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4169 			cmd->command, cmd->argument3);
4170 
4171 		if (!cmd->cmd_active) {
4172 			dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4173 				__func__);
4174 			goto check_upmcrs;
4175 		}
4176 
4177 		ret = -ETIMEDOUT;
4178 		goto out;
4179 	}
4180 
4181 check_upmcrs:
4182 	status = ufshcd_get_upmcrs(hba);
4183 	if (status != PWR_LOCAL) {
4184 		dev_err(hba->dev,
4185 			"pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4186 			cmd->command, status);
4187 		ret = (status != PWR_OK) ? status : -1;
4188 	}
4189 out:
4190 	if (ret) {
4191 		ufshcd_print_host_state(hba);
4192 		ufshcd_print_pwr_info(hba);
4193 		ufshcd_print_evt_hist(hba);
4194 	}
4195 
4196 	spin_lock_irqsave(hba->host->host_lock, flags);
4197 	hba->active_uic_cmd = NULL;
4198 	hba->uic_async_done = NULL;
4199 	if (reenable_intr)
4200 		ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4201 	if (ret) {
4202 		ufshcd_set_link_broken(hba);
4203 		ufshcd_schedule_eh_work(hba);
4204 	}
4205 out_unlock:
4206 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4207 	mutex_unlock(&hba->uic_cmd_mutex);
4208 
4209 	return ret;
4210 }
4211 
4212 /**
4213  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4214  *				using DME_SET primitives.
4215  * @hba: per adapter instance
4216  * @mode: powr mode value
4217  *
4218  * Return: 0 on success, non-zero value on failure.
4219  */
ufshcd_uic_change_pwr_mode(struct ufs_hba * hba,u8 mode)4220 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4221 {
4222 	struct uic_command uic_cmd = {0};
4223 	int ret;
4224 
4225 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4226 		ret = ufshcd_dme_set(hba,
4227 				UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4228 		if (ret) {
4229 			dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4230 						__func__, ret);
4231 			goto out;
4232 		}
4233 	}
4234 
4235 	uic_cmd.command = UIC_CMD_DME_SET;
4236 	uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4237 	uic_cmd.argument3 = mode;
4238 	ufshcd_hold(hba);
4239 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4240 	ufshcd_release(hba);
4241 
4242 out:
4243 	return ret;
4244 }
4245 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4246 
ufshcd_link_recovery(struct ufs_hba * hba)4247 int ufshcd_link_recovery(struct ufs_hba *hba)
4248 {
4249 	int ret;
4250 	unsigned long flags;
4251 
4252 	spin_lock_irqsave(hba->host->host_lock, flags);
4253 	hba->ufshcd_state = UFSHCD_STATE_RESET;
4254 	ufshcd_set_eh_in_progress(hba);
4255 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4256 
4257 	/* Reset the attached device */
4258 	ufshcd_device_reset(hba);
4259 
4260 	ret = ufshcd_host_reset_and_restore(hba);
4261 
4262 	spin_lock_irqsave(hba->host->host_lock, flags);
4263 	if (ret)
4264 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
4265 	ufshcd_clear_eh_in_progress(hba);
4266 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4267 
4268 	if (ret)
4269 		dev_err(hba->dev, "%s: link recovery failed, err %d",
4270 			__func__, ret);
4271 
4272 	return ret;
4273 }
4274 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4275 
ufshcd_uic_hibern8_enter(struct ufs_hba * hba)4276 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4277 {
4278 	int ret;
4279 	struct uic_command uic_cmd = {0};
4280 	ktime_t start = ktime_get();
4281 
4282 	ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4283 
4284 	uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4285 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4286 	trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4287 			     ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4288 
4289 	if (ret)
4290 		dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4291 			__func__, ret);
4292 	else
4293 		ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4294 								POST_CHANGE);
4295 
4296 	return ret;
4297 }
4298 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4299 
ufshcd_uic_hibern8_exit(struct ufs_hba * hba)4300 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4301 {
4302 	struct uic_command uic_cmd = {0};
4303 	int ret;
4304 	ktime_t start = ktime_get();
4305 
4306 	ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4307 
4308 	uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4309 	ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4310 	trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4311 			     ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4312 
4313 	if (ret) {
4314 		dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4315 			__func__, ret);
4316 	} else {
4317 		ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4318 								POST_CHANGE);
4319 		hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4320 		hba->ufs_stats.hibern8_exit_cnt++;
4321 	}
4322 
4323 	return ret;
4324 }
4325 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4326 
ufshcd_auto_hibern8_update(struct ufs_hba * hba,u32 ahit)4327 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4328 {
4329 	unsigned long flags;
4330 	bool update = false;
4331 
4332 	if (!ufshcd_is_auto_hibern8_supported(hba))
4333 		return;
4334 
4335 	spin_lock_irqsave(hba->host->host_lock, flags);
4336 	if (hba->ahit != ahit) {
4337 		hba->ahit = ahit;
4338 		update = true;
4339 	}
4340 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4341 
4342 	if (update &&
4343 	    !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4344 		ufshcd_rpm_get_sync(hba);
4345 		ufshcd_hold(hba);
4346 		ufshcd_auto_hibern8_enable(hba);
4347 		ufshcd_release(hba);
4348 		ufshcd_rpm_put_sync(hba);
4349 	}
4350 }
4351 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4352 
ufshcd_auto_hibern8_enable(struct ufs_hba * hba)4353 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4354 {
4355 	if (!ufshcd_is_auto_hibern8_supported(hba))
4356 		return;
4357 
4358 	ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4359 }
4360 
4361  /**
4362  * ufshcd_init_pwr_info - setting the POR (power on reset)
4363  * values in hba power info
4364  * @hba: per-adapter instance
4365  */
ufshcd_init_pwr_info(struct ufs_hba * hba)4366 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4367 {
4368 	hba->pwr_info.gear_rx = UFS_PWM_G1;
4369 	hba->pwr_info.gear_tx = UFS_PWM_G1;
4370 	hba->pwr_info.lane_rx = UFS_LANE_1;
4371 	hba->pwr_info.lane_tx = UFS_LANE_1;
4372 	hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4373 	hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4374 	hba->pwr_info.hs_rate = 0;
4375 }
4376 
4377 /**
4378  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4379  * @hba: per-adapter instance
4380  *
4381  * Return: 0 upon success; < 0 upon failure.
4382  */
ufshcd_get_max_pwr_mode(struct ufs_hba * hba)4383 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4384 {
4385 	struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4386 
4387 	if (hba->max_pwr_info.is_valid)
4388 		return 0;
4389 
4390 	if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4391 		pwr_info->pwr_tx = FASTAUTO_MODE;
4392 		pwr_info->pwr_rx = FASTAUTO_MODE;
4393 	} else {
4394 		pwr_info->pwr_tx = FAST_MODE;
4395 		pwr_info->pwr_rx = FAST_MODE;
4396 	}
4397 	pwr_info->hs_rate = PA_HS_MODE_B;
4398 
4399 	/* Get the connected lane count */
4400 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4401 			&pwr_info->lane_rx);
4402 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4403 			&pwr_info->lane_tx);
4404 
4405 	if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4406 		dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4407 				__func__,
4408 				pwr_info->lane_rx,
4409 				pwr_info->lane_tx);
4410 		return -EINVAL;
4411 	}
4412 
4413 	/*
4414 	 * First, get the maximum gears of HS speed.
4415 	 * If a zero value, it means there is no HSGEAR capability.
4416 	 * Then, get the maximum gears of PWM speed.
4417 	 */
4418 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4419 	if (!pwr_info->gear_rx) {
4420 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4421 				&pwr_info->gear_rx);
4422 		if (!pwr_info->gear_rx) {
4423 			dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4424 				__func__, pwr_info->gear_rx);
4425 			return -EINVAL;
4426 		}
4427 		pwr_info->pwr_rx = SLOW_MODE;
4428 	}
4429 
4430 	ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4431 			&pwr_info->gear_tx);
4432 	if (!pwr_info->gear_tx) {
4433 		ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4434 				&pwr_info->gear_tx);
4435 		if (!pwr_info->gear_tx) {
4436 			dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4437 				__func__, pwr_info->gear_tx);
4438 			return -EINVAL;
4439 		}
4440 		pwr_info->pwr_tx = SLOW_MODE;
4441 	}
4442 
4443 	hba->max_pwr_info.is_valid = true;
4444 	return 0;
4445 }
4446 
ufshcd_change_power_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_mode)4447 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4448 			     struct ufs_pa_layer_attr *pwr_mode)
4449 {
4450 	int ret;
4451 
4452 	/* if already configured to the requested pwr_mode */
4453 	if (!hba->force_pmc &&
4454 	    pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4455 	    pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4456 	    pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4457 	    pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4458 	    pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4459 	    pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4460 	    pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4461 		dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4462 		return 0;
4463 	}
4464 
4465 	/*
4466 	 * Configure attributes for power mode change with below.
4467 	 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4468 	 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4469 	 * - PA_HSSERIES
4470 	 */
4471 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4472 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4473 			pwr_mode->lane_rx);
4474 	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4475 			pwr_mode->pwr_rx == FAST_MODE)
4476 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4477 	else
4478 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4479 
4480 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4481 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4482 			pwr_mode->lane_tx);
4483 	if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4484 			pwr_mode->pwr_tx == FAST_MODE)
4485 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4486 	else
4487 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4488 
4489 	if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4490 	    pwr_mode->pwr_tx == FASTAUTO_MODE ||
4491 	    pwr_mode->pwr_rx == FAST_MODE ||
4492 	    pwr_mode->pwr_tx == FAST_MODE)
4493 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4494 						pwr_mode->hs_rate);
4495 
4496 	if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4497 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4498 				DL_FC0ProtectionTimeOutVal_Default);
4499 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4500 				DL_TC0ReplayTimeOutVal_Default);
4501 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4502 				DL_AFC0ReqTimeOutVal_Default);
4503 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4504 				DL_FC1ProtectionTimeOutVal_Default);
4505 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4506 				DL_TC1ReplayTimeOutVal_Default);
4507 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4508 				DL_AFC1ReqTimeOutVal_Default);
4509 
4510 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4511 				DL_FC0ProtectionTimeOutVal_Default);
4512 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4513 				DL_TC0ReplayTimeOutVal_Default);
4514 		ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4515 				DL_AFC0ReqTimeOutVal_Default);
4516 	}
4517 
4518 	ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4519 			| pwr_mode->pwr_tx);
4520 
4521 	if (ret) {
4522 		dev_err(hba->dev,
4523 			"%s: power mode change failed %d\n", __func__, ret);
4524 	} else {
4525 		ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4526 								pwr_mode);
4527 
4528 		memcpy(&hba->pwr_info, pwr_mode,
4529 			sizeof(struct ufs_pa_layer_attr));
4530 	}
4531 
4532 	return ret;
4533 }
4534 
4535 /**
4536  * ufshcd_config_pwr_mode - configure a new power mode
4537  * @hba: per-adapter instance
4538  * @desired_pwr_mode: desired power configuration
4539  *
4540  * Return: 0 upon success; < 0 upon failure.
4541  */
ufshcd_config_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * desired_pwr_mode)4542 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4543 		struct ufs_pa_layer_attr *desired_pwr_mode)
4544 {
4545 	struct ufs_pa_layer_attr final_params = { 0 };
4546 	int ret;
4547 
4548 	ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4549 					desired_pwr_mode, &final_params);
4550 
4551 	if (ret)
4552 		memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4553 
4554 	ret = ufshcd_change_power_mode(hba, &final_params);
4555 
4556 	return ret;
4557 }
4558 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4559 
4560 /**
4561  * ufshcd_complete_dev_init() - checks device readiness
4562  * @hba: per-adapter instance
4563  *
4564  * Set fDeviceInit flag and poll until device toggles it.
4565  *
4566  * Return: 0 upon success; < 0 upon failure.
4567  */
ufshcd_complete_dev_init(struct ufs_hba * hba)4568 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4569 {
4570 	int err;
4571 	bool flag_res = true;
4572 	ktime_t timeout;
4573 
4574 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4575 		QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4576 	if (err) {
4577 		dev_err(hba->dev,
4578 			"%s: setting fDeviceInit flag failed with error %d\n",
4579 			__func__, err);
4580 		goto out;
4581 	}
4582 
4583 	/* Poll fDeviceInit flag to be cleared */
4584 	timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4585 	do {
4586 		err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4587 					QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4588 		if (!flag_res)
4589 			break;
4590 		usleep_range(500, 1000);
4591 	} while (ktime_before(ktime_get(), timeout));
4592 
4593 	if (err) {
4594 		dev_err(hba->dev,
4595 				"%s: reading fDeviceInit flag failed with error %d\n",
4596 				__func__, err);
4597 	} else if (flag_res) {
4598 		dev_err(hba->dev,
4599 				"%s: fDeviceInit was not cleared by the device\n",
4600 				__func__);
4601 		err = -EBUSY;
4602 	}
4603 out:
4604 	return err;
4605 }
4606 
4607 /**
4608  * ufshcd_make_hba_operational - Make UFS controller operational
4609  * @hba: per adapter instance
4610  *
4611  * To bring UFS host controller to operational state,
4612  * 1. Enable required interrupts
4613  * 2. Configure interrupt aggregation
4614  * 3. Program UTRL and UTMRL base address
4615  * 4. Configure run-stop-registers
4616  *
4617  * Return: 0 on success, non-zero value on failure.
4618  */
ufshcd_make_hba_operational(struct ufs_hba * hba)4619 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4620 {
4621 	int err = 0;
4622 	u32 reg;
4623 
4624 	/* Enable required interrupts */
4625 	ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4626 
4627 	/* Configure interrupt aggregation */
4628 	if (ufshcd_is_intr_aggr_allowed(hba))
4629 		ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4630 	else
4631 		ufshcd_disable_intr_aggr(hba);
4632 
4633 	/* Configure UTRL and UTMRL base address registers */
4634 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4635 			REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4636 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4637 			REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4638 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4639 			REG_UTP_TASK_REQ_LIST_BASE_L);
4640 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4641 			REG_UTP_TASK_REQ_LIST_BASE_H);
4642 
4643 	/*
4644 	 * Make sure base address and interrupt setup are updated before
4645 	 * enabling the run/stop registers below.
4646 	 */
4647 	wmb();
4648 
4649 	/*
4650 	 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4651 	 */
4652 	reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4653 	if (!(ufshcd_get_lists_status(reg))) {
4654 		ufshcd_enable_run_stop_reg(hba);
4655 	} else {
4656 		dev_err(hba->dev,
4657 			"Host controller not ready to process requests");
4658 		err = -EIO;
4659 	}
4660 
4661 	return err;
4662 }
4663 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4664 
4665 /**
4666  * ufshcd_hba_stop - Send controller to reset state
4667  * @hba: per adapter instance
4668  */
ufshcd_hba_stop(struct ufs_hba * hba)4669 void ufshcd_hba_stop(struct ufs_hba *hba)
4670 {
4671 	unsigned long flags;
4672 	int err;
4673 
4674 	/*
4675 	 * Obtain the host lock to prevent that the controller is disabled
4676 	 * while the UFS interrupt handler is active on another CPU.
4677 	 */
4678 	spin_lock_irqsave(hba->host->host_lock, flags);
4679 	ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4680 	spin_unlock_irqrestore(hba->host->host_lock, flags);
4681 
4682 	err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4683 					CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4684 					10, 1);
4685 	if (err)
4686 		dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4687 }
4688 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4689 
4690 /**
4691  * ufshcd_hba_execute_hce - initialize the controller
4692  * @hba: per adapter instance
4693  *
4694  * The controller resets itself and controller firmware initialization
4695  * sequence kicks off. When controller is ready it will set
4696  * the Host Controller Enable bit to 1.
4697  *
4698  * Return: 0 on success, non-zero value on failure.
4699  */
ufshcd_hba_execute_hce(struct ufs_hba * hba)4700 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4701 {
4702 	int retry_outer = 3;
4703 	int retry_inner;
4704 
4705 start:
4706 	if (ufshcd_is_hba_active(hba))
4707 		/* change controller state to "reset state" */
4708 		ufshcd_hba_stop(hba);
4709 
4710 	/* UniPro link is disabled at this point */
4711 	ufshcd_set_link_off(hba);
4712 
4713 	ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4714 
4715 	/* start controller initialization sequence */
4716 	ufshcd_hba_start(hba);
4717 
4718 	/*
4719 	 * To initialize a UFS host controller HCE bit must be set to 1.
4720 	 * During initialization the HCE bit value changes from 1->0->1.
4721 	 * When the host controller completes initialization sequence
4722 	 * it sets the value of HCE bit to 1. The same HCE bit is read back
4723 	 * to check if the controller has completed initialization sequence.
4724 	 * So without this delay the value HCE = 1, set in the previous
4725 	 * instruction might be read back.
4726 	 * This delay can be changed based on the controller.
4727 	 */
4728 	ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4729 
4730 	/* wait for the host controller to complete initialization */
4731 	retry_inner = 50;
4732 	while (!ufshcd_is_hba_active(hba)) {
4733 		if (retry_inner) {
4734 			retry_inner--;
4735 		} else {
4736 			dev_err(hba->dev,
4737 				"Controller enable failed\n");
4738 			if (retry_outer) {
4739 				retry_outer--;
4740 				goto start;
4741 			}
4742 			return -EIO;
4743 		}
4744 		usleep_range(1000, 1100);
4745 	}
4746 
4747 	/* enable UIC related interrupts */
4748 	ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4749 
4750 	ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4751 
4752 	return 0;
4753 }
4754 
ufshcd_hba_enable(struct ufs_hba * hba)4755 int ufshcd_hba_enable(struct ufs_hba *hba)
4756 {
4757 	int ret;
4758 
4759 	if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4760 		ufshcd_set_link_off(hba);
4761 		ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4762 
4763 		/* enable UIC related interrupts */
4764 		ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4765 		ret = ufshcd_dme_reset(hba);
4766 		if (ret) {
4767 			dev_err(hba->dev, "DME_RESET failed\n");
4768 			return ret;
4769 		}
4770 
4771 		ret = ufshcd_dme_enable(hba);
4772 		if (ret) {
4773 			dev_err(hba->dev, "Enabling DME failed\n");
4774 			return ret;
4775 		}
4776 
4777 		ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4778 	} else {
4779 		ret = ufshcd_hba_execute_hce(hba);
4780 	}
4781 
4782 	return ret;
4783 }
4784 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4785 
ufshcd_disable_tx_lcc(struct ufs_hba * hba,bool peer)4786 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4787 {
4788 	int tx_lanes = 0, i, err = 0;
4789 
4790 	if (!peer)
4791 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4792 			       &tx_lanes);
4793 	else
4794 		ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4795 				    &tx_lanes);
4796 	for (i = 0; i < tx_lanes; i++) {
4797 		if (!peer)
4798 			err = ufshcd_dme_set(hba,
4799 				UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4800 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4801 					0);
4802 		else
4803 			err = ufshcd_dme_peer_set(hba,
4804 				UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4805 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4806 					0);
4807 		if (err) {
4808 			dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4809 				__func__, peer, i, err);
4810 			break;
4811 		}
4812 	}
4813 
4814 	return err;
4815 }
4816 
ufshcd_disable_device_tx_lcc(struct ufs_hba * hba)4817 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4818 {
4819 	return ufshcd_disable_tx_lcc(hba, true);
4820 }
4821 
ufshcd_update_evt_hist(struct ufs_hba * hba,u32 id,u32 val)4822 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4823 {
4824 	struct ufs_event_hist *e;
4825 
4826 	if (id >= UFS_EVT_CNT)
4827 		return;
4828 
4829 	e = &hba->ufs_stats.event[id];
4830 	e->val[e->pos] = val;
4831 	e->tstamp[e->pos] = local_clock();
4832 	e->cnt += 1;
4833 	e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4834 
4835 	ufshcd_vops_event_notify(hba, id, &val);
4836 }
4837 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4838 
4839 /**
4840  * ufshcd_link_startup - Initialize unipro link startup
4841  * @hba: per adapter instance
4842  *
4843  * Return: 0 for success, non-zero in case of failure.
4844  */
ufshcd_link_startup(struct ufs_hba * hba)4845 static int ufshcd_link_startup(struct ufs_hba *hba)
4846 {
4847 	int ret;
4848 	int retries = DME_LINKSTARTUP_RETRIES;
4849 	bool link_startup_again = false;
4850 
4851 	/*
4852 	 * If UFS device isn't active then we will have to issue link startup
4853 	 * 2 times to make sure the device state move to active.
4854 	 */
4855 	if (!ufshcd_is_ufs_dev_active(hba))
4856 		link_startup_again = true;
4857 
4858 link_startup:
4859 	do {
4860 		ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4861 
4862 		ret = ufshcd_dme_link_startup(hba);
4863 
4864 		/* check if device is detected by inter-connect layer */
4865 		if (!ret && !ufshcd_is_device_present(hba)) {
4866 			ufshcd_update_evt_hist(hba,
4867 					       UFS_EVT_LINK_STARTUP_FAIL,
4868 					       0);
4869 			dev_err(hba->dev, "%s: Device not present\n", __func__);
4870 			ret = -ENXIO;
4871 			goto out;
4872 		}
4873 
4874 		/*
4875 		 * DME link lost indication is only received when link is up,
4876 		 * but we can't be sure if the link is up until link startup
4877 		 * succeeds. So reset the local Uni-Pro and try again.
4878 		 */
4879 		if (ret && retries && ufshcd_hba_enable(hba)) {
4880 			ufshcd_update_evt_hist(hba,
4881 					       UFS_EVT_LINK_STARTUP_FAIL,
4882 					       (u32)ret);
4883 			goto out;
4884 		}
4885 	} while (ret && retries--);
4886 
4887 	if (ret) {
4888 		/* failed to get the link up... retire */
4889 		ufshcd_update_evt_hist(hba,
4890 				       UFS_EVT_LINK_STARTUP_FAIL,
4891 				       (u32)ret);
4892 		goto out;
4893 	}
4894 
4895 	if (link_startup_again) {
4896 		link_startup_again = false;
4897 		retries = DME_LINKSTARTUP_RETRIES;
4898 		goto link_startup;
4899 	}
4900 
4901 	/* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4902 	ufshcd_init_pwr_info(hba);
4903 	ufshcd_print_pwr_info(hba);
4904 
4905 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4906 		ret = ufshcd_disable_device_tx_lcc(hba);
4907 		if (ret)
4908 			goto out;
4909 	}
4910 
4911 	/* Include any host controller configuration via UIC commands */
4912 	ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4913 	if (ret)
4914 		goto out;
4915 
4916 	/* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4917 	ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4918 	ret = ufshcd_make_hba_operational(hba);
4919 out:
4920 	if (ret) {
4921 		dev_err(hba->dev, "link startup failed %d\n", ret);
4922 		ufshcd_print_host_state(hba);
4923 		ufshcd_print_pwr_info(hba);
4924 		ufshcd_print_evt_hist(hba);
4925 	}
4926 	return ret;
4927 }
4928 
4929 /**
4930  * ufshcd_verify_dev_init() - Verify device initialization
4931  * @hba: per-adapter instance
4932  *
4933  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4934  * device Transport Protocol (UTP) layer is ready after a reset.
4935  * If the UTP layer at the device side is not initialized, it may
4936  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4937  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4938  *
4939  * Return: 0 upon success; < 0 upon failure.
4940  */
ufshcd_verify_dev_init(struct ufs_hba * hba)4941 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4942 {
4943 	int err = 0;
4944 	int retries;
4945 
4946 	ufshcd_hold(hba);
4947 	mutex_lock(&hba->dev_cmd.lock);
4948 	for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4949 		err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4950 					  hba->nop_out_timeout);
4951 
4952 		if (!err || err == -ETIMEDOUT)
4953 			break;
4954 
4955 		dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4956 	}
4957 	mutex_unlock(&hba->dev_cmd.lock);
4958 	ufshcd_release(hba);
4959 
4960 	if (err)
4961 		dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4962 	return err;
4963 }
4964 
4965 /**
4966  * ufshcd_setup_links - associate link b/w device wlun and other luns
4967  * @sdev: pointer to SCSI device
4968  * @hba: pointer to ufs hba
4969  */
ufshcd_setup_links(struct ufs_hba * hba,struct scsi_device * sdev)4970 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4971 {
4972 	struct device_link *link;
4973 
4974 	/*
4975 	 * Device wlun is the supplier & rest of the luns are consumers.
4976 	 * This ensures that device wlun suspends after all other luns.
4977 	 */
4978 	if (hba->ufs_device_wlun) {
4979 		link = device_link_add(&sdev->sdev_gendev,
4980 				       &hba->ufs_device_wlun->sdev_gendev,
4981 				       DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4982 		if (!link) {
4983 			dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4984 				dev_name(&hba->ufs_device_wlun->sdev_gendev));
4985 			return;
4986 		}
4987 		hba->luns_avail--;
4988 		/* Ignore REPORT_LUN wlun probing */
4989 		if (hba->luns_avail == 1) {
4990 			ufshcd_rpm_put(hba);
4991 			return;
4992 		}
4993 	} else {
4994 		/*
4995 		 * Device wlun is probed. The assumption is that WLUNs are
4996 		 * scanned before other LUNs.
4997 		 */
4998 		hba->luns_avail--;
4999 	}
5000 }
5001 
5002 /**
5003  * ufshcd_lu_init - Initialize the relevant parameters of the LU
5004  * @hba: per-adapter instance
5005  * @sdev: pointer to SCSI device
5006  */
ufshcd_lu_init(struct ufs_hba * hba,struct scsi_device * sdev)5007 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
5008 {
5009 	int len = QUERY_DESC_MAX_SIZE;
5010 	u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
5011 	u8 lun_qdepth = hba->nutrs;
5012 	u8 *desc_buf;
5013 	int ret;
5014 
5015 	desc_buf = kzalloc(len, GFP_KERNEL);
5016 	if (!desc_buf)
5017 		goto set_qdepth;
5018 
5019 	ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
5020 	if (ret < 0) {
5021 		if (ret == -EOPNOTSUPP)
5022 			/* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5023 			lun_qdepth = 1;
5024 		kfree(desc_buf);
5025 		goto set_qdepth;
5026 	}
5027 
5028 	if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5029 		/*
5030 		 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5031 		 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5032 		 */
5033 		lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5034 	}
5035 	/*
5036 	 * According to UFS device specification, the write protection mode is only supported by
5037 	 * normal LU, not supported by WLUN.
5038 	 */
5039 	if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5040 	    !hba->dev_info.is_lu_power_on_wp &&
5041 	    desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5042 		hba->dev_info.is_lu_power_on_wp = true;
5043 
5044 	/* In case of RPMB LU, check if advanced RPMB mode is enabled */
5045 	if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
5046 	    desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5047 		hba->dev_info.b_advanced_rpmb_en = true;
5048 
5049 
5050 	kfree(desc_buf);
5051 set_qdepth:
5052 	/*
5053 	 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5054 	 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5055 	 */
5056 	dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5057 	scsi_change_queue_depth(sdev, lun_qdepth);
5058 }
5059 
5060 /**
5061  * ufshcd_slave_alloc - handle initial SCSI device configurations
5062  * @sdev: pointer to SCSI device
5063  *
5064  * Return: success.
5065  */
ufshcd_slave_alloc(struct scsi_device * sdev)5066 static int ufshcd_slave_alloc(struct scsi_device *sdev)
5067 {
5068 	struct ufs_hba *hba;
5069 
5070 	hba = shost_priv(sdev->host);
5071 
5072 	/* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5073 	sdev->use_10_for_ms = 1;
5074 
5075 	/* DBD field should be set to 1 in mode sense(10) */
5076 	sdev->set_dbd_for_ms = 1;
5077 
5078 	/* allow SCSI layer to restart the device in case of errors */
5079 	sdev->allow_restart = 1;
5080 
5081 	/* REPORT SUPPORTED OPERATION CODES is not supported */
5082 	sdev->no_report_opcodes = 1;
5083 
5084 	/* WRITE_SAME command is not supported */
5085 	sdev->no_write_same = 1;
5086 
5087 	ufshcd_lu_init(hba, sdev);
5088 
5089 	ufshcd_setup_links(hba, sdev);
5090 
5091 	return 0;
5092 }
5093 
5094 /**
5095  * ufshcd_change_queue_depth - change queue depth
5096  * @sdev: pointer to SCSI device
5097  * @depth: required depth to set
5098  *
5099  * Change queue depth and make sure the max. limits are not crossed.
5100  *
5101  * Return: new queue depth.
5102  */
ufshcd_change_queue_depth(struct scsi_device * sdev,int depth)5103 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5104 {
5105 	return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5106 }
5107 
5108 /**
5109  * ufshcd_slave_configure - adjust SCSI device configurations
5110  * @sdev: pointer to SCSI device
5111  *
5112  * Return: 0 (success).
5113  */
ufshcd_slave_configure(struct scsi_device * sdev)5114 static int ufshcd_slave_configure(struct scsi_device *sdev)
5115 {
5116 	struct ufs_hba *hba = shost_priv(sdev->host);
5117 	struct request_queue *q = sdev->request_queue;
5118 
5119 	blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5120 	if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT)
5121 		blk_queue_update_dma_alignment(q, SZ_4K - 1);
5122 	/*
5123 	 * Block runtime-pm until all consumers are added.
5124 	 * Refer ufshcd_setup_links().
5125 	 */
5126 	if (is_device_wlun(sdev))
5127 		pm_runtime_get_noresume(&sdev->sdev_gendev);
5128 	else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5129 		sdev->rpm_autosuspend = 1;
5130 	/*
5131 	 * Do not print messages during runtime PM to avoid never-ending cycles
5132 	 * of messages written back to storage by user space causing runtime
5133 	 * resume, causing more messages and so on.
5134 	 */
5135 	sdev->silence_suspend = 1;
5136 
5137 	ufshcd_crypto_register(hba, q);
5138 
5139 	return 0;
5140 }
5141 
5142 /**
5143  * ufshcd_slave_destroy - remove SCSI device configurations
5144  * @sdev: pointer to SCSI device
5145  */
ufshcd_slave_destroy(struct scsi_device * sdev)5146 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5147 {
5148 	struct ufs_hba *hba;
5149 	unsigned long flags;
5150 
5151 	hba = shost_priv(sdev->host);
5152 
5153 	/* Drop the reference as it won't be needed anymore */
5154 	if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5155 		spin_lock_irqsave(hba->host->host_lock, flags);
5156 		hba->ufs_device_wlun = NULL;
5157 		spin_unlock_irqrestore(hba->host->host_lock, flags);
5158 	} else if (hba->ufs_device_wlun) {
5159 		struct device *supplier = NULL;
5160 
5161 		/* Ensure UFS Device WLUN exists and does not disappear */
5162 		spin_lock_irqsave(hba->host->host_lock, flags);
5163 		if (hba->ufs_device_wlun) {
5164 			supplier = &hba->ufs_device_wlun->sdev_gendev;
5165 			get_device(supplier);
5166 		}
5167 		spin_unlock_irqrestore(hba->host->host_lock, flags);
5168 
5169 		if (supplier) {
5170 			/*
5171 			 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5172 			 * device will not have been registered but can still
5173 			 * have a device link holding a reference to the device.
5174 			 */
5175 			device_link_remove(&sdev->sdev_gendev, supplier);
5176 			put_device(supplier);
5177 		}
5178 	}
5179 }
5180 
5181 /**
5182  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5183  * @lrbp: pointer to local reference block of completed command
5184  * @scsi_status: SCSI command status
5185  *
5186  * Return: value base on SCSI command status.
5187  */
5188 static inline int
ufshcd_scsi_cmd_status(struct ufshcd_lrb * lrbp,int scsi_status)5189 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5190 {
5191 	int result = 0;
5192 
5193 	switch (scsi_status) {
5194 	case SAM_STAT_CHECK_CONDITION:
5195 		ufshcd_copy_sense_data(lrbp);
5196 		fallthrough;
5197 	case SAM_STAT_GOOD:
5198 		result |= DID_OK << 16 | scsi_status;
5199 		break;
5200 	case SAM_STAT_TASK_SET_FULL:
5201 	case SAM_STAT_BUSY:
5202 	case SAM_STAT_TASK_ABORTED:
5203 		ufshcd_copy_sense_data(lrbp);
5204 		result |= scsi_status;
5205 		break;
5206 	default:
5207 		result |= DID_ERROR << 16;
5208 		break;
5209 	} /* end of switch */
5210 
5211 	return result;
5212 }
5213 
5214 /**
5215  * ufshcd_transfer_rsp_status - Get overall status of the response
5216  * @hba: per adapter instance
5217  * @lrbp: pointer to local reference block of completed command
5218  * @cqe: pointer to the completion queue entry
5219  *
5220  * Return: result of the command to notify SCSI midlayer.
5221  */
5222 static inline int
ufshcd_transfer_rsp_status(struct ufs_hba * hba,struct ufshcd_lrb * lrbp,struct cq_entry * cqe)5223 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
5224 			   struct cq_entry *cqe)
5225 {
5226 	int result = 0;
5227 	int scsi_status;
5228 	enum utp_ocs ocs;
5229 	u8 upiu_flags;
5230 	u32 resid;
5231 
5232 	upiu_flags = lrbp->ucd_rsp_ptr->header.flags;
5233 	resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count);
5234 	/*
5235 	 * Test !overflow instead of underflow to support UFS devices that do
5236 	 * not set either flag.
5237 	 */
5238 	if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW))
5239 		scsi_set_resid(lrbp->cmd, resid);
5240 
5241 	/* overall command status of utrd */
5242 	ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5243 
5244 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5245 		if (lrbp->ucd_rsp_ptr->header.response ||
5246 		    lrbp->ucd_rsp_ptr->header.status)
5247 			ocs = OCS_SUCCESS;
5248 	}
5249 
5250 	switch (ocs) {
5251 	case OCS_SUCCESS:
5252 		hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5253 		switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) {
5254 		case UPIU_TRANSACTION_RESPONSE:
5255 			/*
5256 			 * get the result based on SCSI status response
5257 			 * to notify the SCSI midlayer of the command status
5258 			 */
5259 			scsi_status = lrbp->ucd_rsp_ptr->header.status;
5260 			result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5261 
5262 			/*
5263 			 * Currently we are only supporting BKOPs exception
5264 			 * events hence we can ignore BKOPs exception event
5265 			 * during power management callbacks. BKOPs exception
5266 			 * event is not expected to be raised in runtime suspend
5267 			 * callback as it allows the urgent bkops.
5268 			 * During system suspend, we are anyway forcefully
5269 			 * disabling the bkops and if urgent bkops is needed
5270 			 * it will be enabled on system resume. Long term
5271 			 * solution could be to abort the system suspend if
5272 			 * UFS device needs urgent BKOPs.
5273 			 */
5274 			if (!hba->pm_op_in_progress &&
5275 			    !ufshcd_eh_in_progress(hba) &&
5276 			    ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5277 				/* Flushed in suspend */
5278 				schedule_work(&hba->eeh_work);
5279 			break;
5280 		case UPIU_TRANSACTION_REJECT_UPIU:
5281 			/* TODO: handle Reject UPIU Response */
5282 			result = DID_ERROR << 16;
5283 			dev_err(hba->dev,
5284 				"Reject UPIU not fully implemented\n");
5285 			break;
5286 		default:
5287 			dev_err(hba->dev,
5288 				"Unexpected request response code = %x\n",
5289 				result);
5290 			result = DID_ERROR << 16;
5291 			break;
5292 		}
5293 		break;
5294 	case OCS_ABORTED:
5295 		result |= DID_ABORT << 16;
5296 		break;
5297 	case OCS_INVALID_COMMAND_STATUS:
5298 		result |= DID_REQUEUE << 16;
5299 		break;
5300 	case OCS_INVALID_CMD_TABLE_ATTR:
5301 	case OCS_INVALID_PRDT_ATTR:
5302 	case OCS_MISMATCH_DATA_BUF_SIZE:
5303 	case OCS_MISMATCH_RESP_UPIU_SIZE:
5304 	case OCS_PEER_COMM_FAILURE:
5305 	case OCS_FATAL_ERROR:
5306 	case OCS_DEVICE_FATAL_ERROR:
5307 	case OCS_INVALID_CRYPTO_CONFIG:
5308 	case OCS_GENERAL_CRYPTO_ERROR:
5309 	default:
5310 		result |= DID_ERROR << 16;
5311 		dev_err(hba->dev,
5312 				"OCS error from controller = %x for tag %d\n",
5313 				ocs, lrbp->task_tag);
5314 		ufshcd_print_evt_hist(hba);
5315 		ufshcd_print_host_state(hba);
5316 		break;
5317 	} /* end of switch */
5318 
5319 	if ((host_byte(result) != DID_OK) &&
5320 	    (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5321 		ufshcd_print_tr(hba, lrbp->task_tag, true);
5322 	return result;
5323 }
5324 
ufshcd_is_auto_hibern8_error(struct ufs_hba * hba,u32 intr_mask)5325 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5326 					 u32 intr_mask)
5327 {
5328 	if (!ufshcd_is_auto_hibern8_supported(hba) ||
5329 	    !ufshcd_is_auto_hibern8_enabled(hba))
5330 		return false;
5331 
5332 	if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5333 		return false;
5334 
5335 	if (hba->active_uic_cmd &&
5336 	    (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5337 	    hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5338 		return false;
5339 
5340 	return true;
5341 }
5342 
5343 /**
5344  * ufshcd_uic_cmd_compl - handle completion of uic command
5345  * @hba: per adapter instance
5346  * @intr_status: interrupt status generated by the controller
5347  *
5348  * Return:
5349  *  IRQ_HANDLED - If interrupt is valid
5350  *  IRQ_NONE    - If invalid interrupt
5351  */
ufshcd_uic_cmd_compl(struct ufs_hba * hba,u32 intr_status)5352 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5353 {
5354 	irqreturn_t retval = IRQ_NONE;
5355 
5356 	spin_lock(hba->host->host_lock);
5357 	if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5358 		hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5359 
5360 	if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5361 		hba->active_uic_cmd->argument2 |=
5362 			ufshcd_get_uic_cmd_result(hba);
5363 		hba->active_uic_cmd->argument3 =
5364 			ufshcd_get_dme_attr_val(hba);
5365 		if (!hba->uic_async_done)
5366 			hba->active_uic_cmd->cmd_active = 0;
5367 		complete(&hba->active_uic_cmd->done);
5368 		retval = IRQ_HANDLED;
5369 	}
5370 
5371 	if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5372 		hba->active_uic_cmd->cmd_active = 0;
5373 		complete(hba->uic_async_done);
5374 		retval = IRQ_HANDLED;
5375 	}
5376 
5377 	if (retval == IRQ_HANDLED)
5378 		ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5379 					     UFS_CMD_COMP);
5380 	spin_unlock(hba->host->host_lock);
5381 	return retval;
5382 }
5383 
5384 /* Release the resources allocated for processing a SCSI command. */
ufshcd_release_scsi_cmd(struct ufs_hba * hba,struct ufshcd_lrb * lrbp)5385 void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5386 			     struct ufshcd_lrb *lrbp)
5387 {
5388 	struct scsi_cmnd *cmd = lrbp->cmd;
5389 
5390 	scsi_dma_unmap(cmd);
5391 	ufshcd_release(hba);
5392 	ufshcd_clk_scaling_update_busy(hba);
5393 }
5394 
5395 /**
5396  * ufshcd_compl_one_cqe - handle a completion queue entry
5397  * @hba: per adapter instance
5398  * @task_tag: the task tag of the request to be completed
5399  * @cqe: pointer to the completion queue entry
5400  */
ufshcd_compl_one_cqe(struct ufs_hba * hba,int task_tag,struct cq_entry * cqe)5401 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5402 			  struct cq_entry *cqe)
5403 {
5404 	struct ufshcd_lrb *lrbp;
5405 	struct scsi_cmnd *cmd;
5406 	enum utp_ocs ocs;
5407 
5408 	lrbp = &hba->lrb[task_tag];
5409 	lrbp->compl_time_stamp = ktime_get();
5410 	cmd = lrbp->cmd;
5411 	if (cmd) {
5412 		if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5413 			ufshcd_update_monitor(hba, lrbp);
5414 		ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP);
5415 		cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe);
5416 		ufshcd_release_scsi_cmd(hba, lrbp);
5417 		/* Do not touch lrbp after scsi done */
5418 		scsi_done(cmd);
5419 	} else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5420 		   lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5421 		if (hba->dev_cmd.complete) {
5422 			if (cqe) {
5423 				ocs = le32_to_cpu(cqe->status) & MASK_OCS;
5424 				lrbp->utr_descriptor_ptr->header.ocs = ocs;
5425 			}
5426 			complete(hba->dev_cmd.complete);
5427 			ufshcd_clk_scaling_update_busy(hba);
5428 		}
5429 	}
5430 }
5431 
5432 /**
5433  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5434  * @hba: per adapter instance
5435  * @completed_reqs: bitmask that indicates which requests to complete
5436  */
__ufshcd_transfer_req_compl(struct ufs_hba * hba,unsigned long completed_reqs)5437 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5438 					unsigned long completed_reqs)
5439 {
5440 	int tag;
5441 
5442 	for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5443 		ufshcd_compl_one_cqe(hba, tag, NULL);
5444 }
5445 
5446 /* Any value that is not an existing queue number is fine for this constant. */
5447 enum {
5448 	UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5449 };
5450 
ufshcd_clear_polled(struct ufs_hba * hba,unsigned long * completed_reqs)5451 static void ufshcd_clear_polled(struct ufs_hba *hba,
5452 				unsigned long *completed_reqs)
5453 {
5454 	int tag;
5455 
5456 	for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5457 		struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5458 
5459 		if (!cmd)
5460 			continue;
5461 		if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5462 			__clear_bit(tag, completed_reqs);
5463 	}
5464 }
5465 
5466 /*
5467  * Return: > 0 if one or more commands have been completed or 0 if no
5468  * requests have been completed.
5469  */
ufshcd_poll(struct Scsi_Host * shost,unsigned int queue_num)5470 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5471 {
5472 	struct ufs_hba *hba = shost_priv(shost);
5473 	unsigned long completed_reqs, flags;
5474 	u32 tr_doorbell;
5475 	struct ufs_hw_queue *hwq;
5476 
5477 	if (is_mcq_enabled(hba)) {
5478 		hwq = &hba->uhq[queue_num];
5479 
5480 		return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5481 	}
5482 
5483 	spin_lock_irqsave(&hba->outstanding_lock, flags);
5484 	tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5485 	completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5486 	WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5487 		  "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5488 		  hba->outstanding_reqs);
5489 	if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5490 		/* Do not complete polled requests from interrupt context. */
5491 		ufshcd_clear_polled(hba, &completed_reqs);
5492 	}
5493 	hba->outstanding_reqs &= ~completed_reqs;
5494 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5495 
5496 	if (completed_reqs)
5497 		__ufshcd_transfer_req_compl(hba, completed_reqs);
5498 
5499 	return completed_reqs != 0;
5500 }
5501 
5502 /**
5503  * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is
5504  * invoked from the error handler context or ufshcd_host_reset_and_restore()
5505  * to complete the pending transfers and free the resources associated with
5506  * the scsi command.
5507  *
5508  * @hba: per adapter instance
5509  * @force_compl: This flag is set to true when invoked
5510  * from ufshcd_host_reset_and_restore() in which case it requires special
5511  * handling because the host controller has been reset by ufshcd_hba_stop().
5512  */
ufshcd_mcq_compl_pending_transfer(struct ufs_hba * hba,bool force_compl)5513 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba,
5514 					      bool force_compl)
5515 {
5516 	struct ufs_hw_queue *hwq;
5517 	struct ufshcd_lrb *lrbp;
5518 	struct scsi_cmnd *cmd;
5519 	unsigned long flags;
5520 	u32 hwq_num, utag;
5521 	int tag;
5522 
5523 	for (tag = 0; tag < hba->nutrs; tag++) {
5524 		lrbp = &hba->lrb[tag];
5525 		cmd = lrbp->cmd;
5526 		if (!ufshcd_cmd_inflight(cmd) ||
5527 		    test_bit(SCMD_STATE_COMPLETE, &cmd->state))
5528 			continue;
5529 
5530 		utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
5531 		hwq_num = blk_mq_unique_tag_to_hwq(utag);
5532 		hwq = &hba->uhq[hwq_num];
5533 
5534 		if (force_compl) {
5535 			ufshcd_mcq_compl_all_cqes_lock(hba, hwq);
5536 			/*
5537 			 * For those cmds of which the cqes are not present
5538 			 * in the cq, complete them explicitly.
5539 			 */
5540 			if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) {
5541 				spin_lock_irqsave(&hwq->cq_lock, flags);
5542 				set_host_byte(cmd, DID_REQUEUE);
5543 				ufshcd_release_scsi_cmd(hba, lrbp);
5544 				scsi_done(cmd);
5545 				spin_unlock_irqrestore(&hwq->cq_lock, flags);
5546 			}
5547 		} else {
5548 			ufshcd_mcq_poll_cqe_lock(hba, hwq);
5549 		}
5550 	}
5551 }
5552 
5553 /**
5554  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5555  * @hba: per adapter instance
5556  *
5557  * Return:
5558  *  IRQ_HANDLED - If interrupt is valid
5559  *  IRQ_NONE    - If invalid interrupt
5560  */
ufshcd_transfer_req_compl(struct ufs_hba * hba)5561 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5562 {
5563 	/* Resetting interrupt aggregation counters first and reading the
5564 	 * DOOR_BELL afterward allows us to handle all the completed requests.
5565 	 * In order to prevent other interrupts starvation the DB is read once
5566 	 * after reset. The down side of this solution is the possibility of
5567 	 * false interrupt if device completes another request after resetting
5568 	 * aggregation and before reading the DB.
5569 	 */
5570 	if (ufshcd_is_intr_aggr_allowed(hba) &&
5571 	    !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5572 		ufshcd_reset_intr_aggr(hba);
5573 
5574 	if (ufs_fail_completion())
5575 		return IRQ_HANDLED;
5576 
5577 	/*
5578 	 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5579 	 * do not want polling to trigger spurious interrupt complaints.
5580 	 */
5581 	ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5582 
5583 	return IRQ_HANDLED;
5584 }
5585 
__ufshcd_write_ee_control(struct ufs_hba * hba,u32 ee_ctrl_mask)5586 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5587 {
5588 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5589 				       QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5590 				       &ee_ctrl_mask);
5591 }
5592 
ufshcd_write_ee_control(struct ufs_hba * hba)5593 int ufshcd_write_ee_control(struct ufs_hba *hba)
5594 {
5595 	int err;
5596 
5597 	mutex_lock(&hba->ee_ctrl_mutex);
5598 	err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5599 	mutex_unlock(&hba->ee_ctrl_mutex);
5600 	if (err)
5601 		dev_err(hba->dev, "%s: failed to write ee control %d\n",
5602 			__func__, err);
5603 	return err;
5604 }
5605 
ufshcd_update_ee_control(struct ufs_hba * hba,u16 * mask,const u16 * other_mask,u16 set,u16 clr)5606 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5607 			     const u16 *other_mask, u16 set, u16 clr)
5608 {
5609 	u16 new_mask, ee_ctrl_mask;
5610 	int err = 0;
5611 
5612 	mutex_lock(&hba->ee_ctrl_mutex);
5613 	new_mask = (*mask & ~clr) | set;
5614 	ee_ctrl_mask = new_mask | *other_mask;
5615 	if (ee_ctrl_mask != hba->ee_ctrl_mask)
5616 		err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5617 	/* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5618 	if (!err) {
5619 		hba->ee_ctrl_mask = ee_ctrl_mask;
5620 		*mask = new_mask;
5621 	}
5622 	mutex_unlock(&hba->ee_ctrl_mutex);
5623 	return err;
5624 }
5625 
5626 /**
5627  * ufshcd_disable_ee - disable exception event
5628  * @hba: per-adapter instance
5629  * @mask: exception event to disable
5630  *
5631  * Disables exception event in the device so that the EVENT_ALERT
5632  * bit is not set.
5633  *
5634  * Return: zero on success, non-zero error value on failure.
5635  */
ufshcd_disable_ee(struct ufs_hba * hba,u16 mask)5636 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5637 {
5638 	return ufshcd_update_ee_drv_mask(hba, 0, mask);
5639 }
5640 
5641 /**
5642  * ufshcd_enable_ee - enable exception event
5643  * @hba: per-adapter instance
5644  * @mask: exception event to enable
5645  *
5646  * Enable corresponding exception event in the device to allow
5647  * device to alert host in critical scenarios.
5648  *
5649  * Return: zero on success, non-zero error value on failure.
5650  */
ufshcd_enable_ee(struct ufs_hba * hba,u16 mask)5651 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5652 {
5653 	return ufshcd_update_ee_drv_mask(hba, mask, 0);
5654 }
5655 
5656 /**
5657  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5658  * @hba: per-adapter instance
5659  *
5660  * Allow device to manage background operations on its own. Enabling
5661  * this might lead to inconsistent latencies during normal data transfers
5662  * as the device is allowed to manage its own way of handling background
5663  * operations.
5664  *
5665  * Return: zero on success, non-zero on failure.
5666  */
ufshcd_enable_auto_bkops(struct ufs_hba * hba)5667 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5668 {
5669 	int err = 0;
5670 
5671 	if (hba->auto_bkops_enabled)
5672 		goto out;
5673 
5674 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5675 			QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5676 	if (err) {
5677 		dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5678 				__func__, err);
5679 		goto out;
5680 	}
5681 
5682 	hba->auto_bkops_enabled = true;
5683 	trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5684 
5685 	/* No need of URGENT_BKOPS exception from the device */
5686 	err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5687 	if (err)
5688 		dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5689 				__func__, err);
5690 out:
5691 	return err;
5692 }
5693 
5694 /**
5695  * ufshcd_disable_auto_bkops - block device in doing background operations
5696  * @hba: per-adapter instance
5697  *
5698  * Disabling background operations improves command response latency but
5699  * has drawback of device moving into critical state where the device is
5700  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5701  * host is idle so that BKOPS are managed effectively without any negative
5702  * impacts.
5703  *
5704  * Return: zero on success, non-zero on failure.
5705  */
ufshcd_disable_auto_bkops(struct ufs_hba * hba)5706 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5707 {
5708 	int err = 0;
5709 
5710 	if (!hba->auto_bkops_enabled)
5711 		goto out;
5712 
5713 	/*
5714 	 * If host assisted BKOPs is to be enabled, make sure
5715 	 * urgent bkops exception is allowed.
5716 	 */
5717 	err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5718 	if (err) {
5719 		dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5720 				__func__, err);
5721 		goto out;
5722 	}
5723 
5724 	err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5725 			QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5726 	if (err) {
5727 		dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5728 				__func__, err);
5729 		ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5730 		goto out;
5731 	}
5732 
5733 	hba->auto_bkops_enabled = false;
5734 	trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5735 	hba->is_urgent_bkops_lvl_checked = false;
5736 out:
5737 	return err;
5738 }
5739 
5740 /**
5741  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5742  * @hba: per adapter instance
5743  *
5744  * After a device reset the device may toggle the BKOPS_EN flag
5745  * to default value. The s/w tracking variables should be updated
5746  * as well. This function would change the auto-bkops state based on
5747  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5748  */
ufshcd_force_reset_auto_bkops(struct ufs_hba * hba)5749 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5750 {
5751 	if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5752 		hba->auto_bkops_enabled = false;
5753 		hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5754 		ufshcd_enable_auto_bkops(hba);
5755 	} else {
5756 		hba->auto_bkops_enabled = true;
5757 		hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5758 		ufshcd_disable_auto_bkops(hba);
5759 	}
5760 	hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5761 	hba->is_urgent_bkops_lvl_checked = false;
5762 }
5763 
ufshcd_get_bkops_status(struct ufs_hba * hba,u32 * status)5764 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5765 {
5766 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5767 			QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5768 }
5769 
5770 /**
5771  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5772  * @hba: per-adapter instance
5773  * @status: bkops_status value
5774  *
5775  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5776  * flag in the device to permit background operations if the device
5777  * bkops_status is greater than or equal to "status" argument passed to
5778  * this function, disable otherwise.
5779  *
5780  * Return: 0 for success, non-zero in case of failure.
5781  *
5782  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5783  * to know whether auto bkops is enabled or disabled after this function
5784  * returns control to it.
5785  */
ufshcd_bkops_ctrl(struct ufs_hba * hba,enum bkops_status status)5786 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5787 			     enum bkops_status status)
5788 {
5789 	int err;
5790 	u32 curr_status = 0;
5791 
5792 	err = ufshcd_get_bkops_status(hba, &curr_status);
5793 	if (err) {
5794 		dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5795 				__func__, err);
5796 		goto out;
5797 	} else if (curr_status > BKOPS_STATUS_MAX) {
5798 		dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5799 				__func__, curr_status);
5800 		err = -EINVAL;
5801 		goto out;
5802 	}
5803 
5804 	if (curr_status >= status)
5805 		err = ufshcd_enable_auto_bkops(hba);
5806 	else
5807 		err = ufshcd_disable_auto_bkops(hba);
5808 out:
5809 	return err;
5810 }
5811 
5812 /**
5813  * ufshcd_urgent_bkops - handle urgent bkops exception event
5814  * @hba: per-adapter instance
5815  *
5816  * Enable fBackgroundOpsEn flag in the device to permit background
5817  * operations.
5818  *
5819  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5820  * and negative error value for any other failure.
5821  *
5822  * Return: 0 upon success; < 0 upon failure.
5823  */
ufshcd_urgent_bkops(struct ufs_hba * hba)5824 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5825 {
5826 	return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5827 }
5828 
ufshcd_get_ee_status(struct ufs_hba * hba,u32 * status)5829 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5830 {
5831 	return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5832 			QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5833 }
5834 
ufshcd_bkops_exception_event_handler(struct ufs_hba * hba)5835 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5836 {
5837 	int err;
5838 	u32 curr_status = 0;
5839 
5840 	if (hba->is_urgent_bkops_lvl_checked)
5841 		goto enable_auto_bkops;
5842 
5843 	err = ufshcd_get_bkops_status(hba, &curr_status);
5844 	if (err) {
5845 		dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5846 				__func__, err);
5847 		goto out;
5848 	}
5849 
5850 	/*
5851 	 * We are seeing that some devices are raising the urgent bkops
5852 	 * exception events even when BKOPS status doesn't indicate performace
5853 	 * impacted or critical. Handle these device by determining their urgent
5854 	 * bkops status at runtime.
5855 	 */
5856 	if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5857 		dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5858 				__func__, curr_status);
5859 		/* update the current status as the urgent bkops level */
5860 		hba->urgent_bkops_lvl = curr_status;
5861 		hba->is_urgent_bkops_lvl_checked = true;
5862 	}
5863 
5864 enable_auto_bkops:
5865 	err = ufshcd_enable_auto_bkops(hba);
5866 out:
5867 	if (err < 0)
5868 		dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5869 				__func__, err);
5870 }
5871 
ufshcd_temp_exception_event_handler(struct ufs_hba * hba,u16 status)5872 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5873 {
5874 	u32 value;
5875 
5876 	if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5877 				QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5878 		return;
5879 
5880 	dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5881 
5882 	ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5883 
5884 	/*
5885 	 * A placeholder for the platform vendors to add whatever additional
5886 	 * steps required
5887 	 */
5888 }
5889 
__ufshcd_wb_toggle(struct ufs_hba * hba,bool set,enum flag_idn idn)5890 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5891 {
5892 	u8 index;
5893 	enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5894 				   UPIU_QUERY_OPCODE_CLEAR_FLAG;
5895 
5896 	index = ufshcd_wb_get_query_index(hba);
5897 	return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5898 }
5899 
ufshcd_wb_toggle(struct ufs_hba * hba,bool enable)5900 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5901 {
5902 	int ret;
5903 
5904 	if (!ufshcd_is_wb_allowed(hba) ||
5905 	    hba->dev_info.wb_enabled == enable)
5906 		return 0;
5907 
5908 	ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5909 	if (ret) {
5910 		dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
5911 			__func__, enable ? "enabling" : "disabling", ret);
5912 		return ret;
5913 	}
5914 
5915 	hba->dev_info.wb_enabled = enable;
5916 	dev_dbg(hba->dev, "%s: Write Booster %s\n",
5917 			__func__, enable ? "enabled" : "disabled");
5918 
5919 	return ret;
5920 }
5921 
ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba * hba,bool enable)5922 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
5923 						 bool enable)
5924 {
5925 	int ret;
5926 
5927 	ret = __ufshcd_wb_toggle(hba, enable,
5928 			QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5929 	if (ret) {
5930 		dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
5931 			__func__, enable ? "enabling" : "disabling", ret);
5932 		return;
5933 	}
5934 	dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
5935 			__func__, enable ? "enabled" : "disabled");
5936 }
5937 
ufshcd_wb_toggle_buf_flush(struct ufs_hba * hba,bool enable)5938 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
5939 {
5940 	int ret;
5941 
5942 	if (!ufshcd_is_wb_allowed(hba) ||
5943 	    hba->dev_info.wb_buf_flush_enabled == enable)
5944 		return 0;
5945 
5946 	ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5947 	if (ret) {
5948 		dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
5949 			__func__, enable ? "enabling" : "disabling", ret);
5950 		return ret;
5951 	}
5952 
5953 	hba->dev_info.wb_buf_flush_enabled = enable;
5954 	dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
5955 			__func__, enable ? "enabled" : "disabled");
5956 
5957 	return ret;
5958 }
5959 
ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba * hba,u32 avail_buf)5960 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5961 						u32 avail_buf)
5962 {
5963 	u32 cur_buf;
5964 	int ret;
5965 	u8 index;
5966 
5967 	index = ufshcd_wb_get_query_index(hba);
5968 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5969 					      QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5970 					      index, 0, &cur_buf);
5971 	if (ret) {
5972 		dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
5973 			__func__, ret);
5974 		return false;
5975 	}
5976 
5977 	if (!cur_buf) {
5978 		dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5979 			 cur_buf);
5980 		return false;
5981 	}
5982 	/* Let it continue to flush when available buffer exceeds threshold */
5983 	return avail_buf < hba->vps->wb_flush_threshold;
5984 }
5985 
ufshcd_wb_force_disable(struct ufs_hba * hba)5986 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5987 {
5988 	if (ufshcd_is_wb_buf_flush_allowed(hba))
5989 		ufshcd_wb_toggle_buf_flush(hba, false);
5990 
5991 	ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
5992 	ufshcd_wb_toggle(hba, false);
5993 	hba->caps &= ~UFSHCD_CAP_WB_EN;
5994 
5995 	dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5996 }
5997 
ufshcd_is_wb_buf_lifetime_available(struct ufs_hba * hba)5998 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5999 {
6000 	u32 lifetime;
6001 	int ret;
6002 	u8 index;
6003 
6004 	index = ufshcd_wb_get_query_index(hba);
6005 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6006 				      QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
6007 				      index, 0, &lifetime);
6008 	if (ret) {
6009 		dev_err(hba->dev,
6010 			"%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
6011 			__func__, ret);
6012 		return false;
6013 	}
6014 
6015 	if (lifetime == UFS_WB_EXCEED_LIFETIME) {
6016 		dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
6017 			__func__, lifetime);
6018 		return false;
6019 	}
6020 
6021 	dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
6022 		__func__, lifetime);
6023 
6024 	return true;
6025 }
6026 
ufshcd_wb_need_flush(struct ufs_hba * hba)6027 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
6028 {
6029 	int ret;
6030 	u32 avail_buf;
6031 	u8 index;
6032 
6033 	if (!ufshcd_is_wb_allowed(hba))
6034 		return false;
6035 
6036 	if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
6037 		ufshcd_wb_force_disable(hba);
6038 		return false;
6039 	}
6040 
6041 	/*
6042 	 * The ufs device needs the vcc to be ON to flush.
6043 	 * With user-space reduction enabled, it's enough to enable flush
6044 	 * by checking only the available buffer. The threshold
6045 	 * defined here is > 90% full.
6046 	 * With user-space preserved enabled, the current-buffer
6047 	 * should be checked too because the wb buffer size can reduce
6048 	 * when disk tends to be full. This info is provided by current
6049 	 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
6050 	 * keeping vcc on when current buffer is empty.
6051 	 */
6052 	index = ufshcd_wb_get_query_index(hba);
6053 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6054 				      QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6055 				      index, 0, &avail_buf);
6056 	if (ret) {
6057 		dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6058 			 __func__, ret);
6059 		return false;
6060 	}
6061 
6062 	if (!hba->dev_info.b_presrv_uspc_en)
6063 		return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6064 
6065 	return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
6066 }
6067 
ufshcd_rpm_dev_flush_recheck_work(struct work_struct * work)6068 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6069 {
6070 	struct ufs_hba *hba = container_of(to_delayed_work(work),
6071 					   struct ufs_hba,
6072 					   rpm_dev_flush_recheck_work);
6073 	/*
6074 	 * To prevent unnecessary VCC power drain after device finishes
6075 	 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
6076 	 * after a certain delay to recheck the threshold by next runtime
6077 	 * suspend.
6078 	 */
6079 	ufshcd_rpm_get_sync(hba);
6080 	ufshcd_rpm_put_sync(hba);
6081 }
6082 
6083 /**
6084  * ufshcd_exception_event_handler - handle exceptions raised by device
6085  * @work: pointer to work data
6086  *
6087  * Read bExceptionEventStatus attribute from the device and handle the
6088  * exception event accordingly.
6089  */
ufshcd_exception_event_handler(struct work_struct * work)6090 static void ufshcd_exception_event_handler(struct work_struct *work)
6091 {
6092 	struct ufs_hba *hba;
6093 	int err;
6094 	u32 status = 0;
6095 	hba = container_of(work, struct ufs_hba, eeh_work);
6096 
6097 	ufshcd_scsi_block_requests(hba);
6098 	err = ufshcd_get_ee_status(hba, &status);
6099 	if (err) {
6100 		dev_err(hba->dev, "%s: failed to get exception status %d\n",
6101 				__func__, err);
6102 		goto out;
6103 	}
6104 
6105 	trace_ufshcd_exception_event(dev_name(hba->dev), status);
6106 
6107 	if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6108 		ufshcd_bkops_exception_event_handler(hba);
6109 
6110 	if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6111 		ufshcd_temp_exception_event_handler(hba, status);
6112 
6113 	ufs_debugfs_exception_event(hba, status);
6114 out:
6115 	ufshcd_scsi_unblock_requests(hba);
6116 }
6117 
6118 /* Complete requests that have door-bell cleared */
ufshcd_complete_requests(struct ufs_hba * hba,bool force_compl)6119 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl)
6120 {
6121 	if (is_mcq_enabled(hba))
6122 		ufshcd_mcq_compl_pending_transfer(hba, force_compl);
6123 	else
6124 		ufshcd_transfer_req_compl(hba);
6125 
6126 	ufshcd_tmc_handler(hba);
6127 }
6128 
6129 /**
6130  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6131  *				to recover from the DL NAC errors or not.
6132  * @hba: per-adapter instance
6133  *
6134  * Return: true if error handling is required, false otherwise.
6135  */
ufshcd_quirk_dl_nac_errors(struct ufs_hba * hba)6136 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6137 {
6138 	unsigned long flags;
6139 	bool err_handling = true;
6140 
6141 	spin_lock_irqsave(hba->host->host_lock, flags);
6142 	/*
6143 	 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6144 	 * device fatal error and/or DL NAC & REPLAY timeout errors.
6145 	 */
6146 	if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6147 		goto out;
6148 
6149 	if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6150 	    ((hba->saved_err & UIC_ERROR) &&
6151 	     (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6152 		goto out;
6153 
6154 	if ((hba->saved_err & UIC_ERROR) &&
6155 	    (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6156 		int err;
6157 		/*
6158 		 * wait for 50ms to see if we can get any other errors or not.
6159 		 */
6160 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6161 		msleep(50);
6162 		spin_lock_irqsave(hba->host->host_lock, flags);
6163 
6164 		/*
6165 		 * now check if we have got any other severe errors other than
6166 		 * DL NAC error?
6167 		 */
6168 		if ((hba->saved_err & INT_FATAL_ERRORS) ||
6169 		    ((hba->saved_err & UIC_ERROR) &&
6170 		    (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6171 			goto out;
6172 
6173 		/*
6174 		 * As DL NAC is the only error received so far, send out NOP
6175 		 * command to confirm if link is still active or not.
6176 		 *   - If we don't get any response then do error recovery.
6177 		 *   - If we get response then clear the DL NAC error bit.
6178 		 */
6179 
6180 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6181 		err = ufshcd_verify_dev_init(hba);
6182 		spin_lock_irqsave(hba->host->host_lock, flags);
6183 
6184 		if (err)
6185 			goto out;
6186 
6187 		/* Link seems to be alive hence ignore the DL NAC errors */
6188 		if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6189 			hba->saved_err &= ~UIC_ERROR;
6190 		/* clear NAC error */
6191 		hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6192 		if (!hba->saved_uic_err)
6193 			err_handling = false;
6194 	}
6195 out:
6196 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6197 	return err_handling;
6198 }
6199 
6200 /* host lock must be held before calling this func */
ufshcd_is_saved_err_fatal(struct ufs_hba * hba)6201 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6202 {
6203 	return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6204 	       (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6205 }
6206 
ufshcd_schedule_eh_work(struct ufs_hba * hba)6207 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6208 {
6209 	lockdep_assert_held(hba->host->host_lock);
6210 
6211 	/* handle fatal errors only when link is not in error state */
6212 	if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6213 		if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6214 		    ufshcd_is_saved_err_fatal(hba))
6215 			hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6216 		else
6217 			hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6218 		queue_work(hba->eh_wq, &hba->eh_work);
6219 	}
6220 }
6221 
ufshcd_force_error_recovery(struct ufs_hba * hba)6222 static void ufshcd_force_error_recovery(struct ufs_hba *hba)
6223 {
6224 	spin_lock_irq(hba->host->host_lock);
6225 	hba->force_reset = true;
6226 	ufshcd_schedule_eh_work(hba);
6227 	spin_unlock_irq(hba->host->host_lock);
6228 }
6229 
ufshcd_clk_scaling_allow(struct ufs_hba * hba,bool allow)6230 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6231 {
6232 	mutex_lock(&hba->wb_mutex);
6233 	down_write(&hba->clk_scaling_lock);
6234 	hba->clk_scaling.is_allowed = allow;
6235 	up_write(&hba->clk_scaling_lock);
6236 	mutex_unlock(&hba->wb_mutex);
6237 }
6238 
ufshcd_clk_scaling_suspend(struct ufs_hba * hba,bool suspend)6239 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6240 {
6241 	if (suspend) {
6242 		if (hba->clk_scaling.is_enabled)
6243 			ufshcd_suspend_clkscaling(hba);
6244 		ufshcd_clk_scaling_allow(hba, false);
6245 	} else {
6246 		ufshcd_clk_scaling_allow(hba, true);
6247 		if (hba->clk_scaling.is_enabled)
6248 			ufshcd_resume_clkscaling(hba);
6249 	}
6250 }
6251 
ufshcd_err_handling_prepare(struct ufs_hba * hba)6252 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6253 {
6254 	ufshcd_rpm_get_sync(hba);
6255 	if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6256 	    hba->is_sys_suspended) {
6257 		enum ufs_pm_op pm_op;
6258 
6259 		/*
6260 		 * Don't assume anything of resume, if
6261 		 * resume fails, irq and clocks can be OFF, and powers
6262 		 * can be OFF or in LPM.
6263 		 */
6264 		ufshcd_setup_hba_vreg(hba, true);
6265 		ufshcd_enable_irq(hba);
6266 		ufshcd_setup_vreg(hba, true);
6267 		ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6268 		ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6269 		ufshcd_hold(hba);
6270 		if (!ufshcd_is_clkgating_allowed(hba))
6271 			ufshcd_setup_clocks(hba, true);
6272 		pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6273 		ufshcd_vops_resume(hba, pm_op);
6274 	} else {
6275 		ufshcd_hold(hba);
6276 		if (ufshcd_is_clkscaling_supported(hba) &&
6277 		    hba->clk_scaling.is_enabled)
6278 			ufshcd_suspend_clkscaling(hba);
6279 		ufshcd_clk_scaling_allow(hba, false);
6280 	}
6281 	ufshcd_scsi_block_requests(hba);
6282 	/* Wait for ongoing ufshcd_queuecommand() calls to finish. */
6283 	blk_mq_wait_quiesce_done(&hba->host->tag_set);
6284 	cancel_work_sync(&hba->eeh_work);
6285 }
6286 
ufshcd_err_handling_unprepare(struct ufs_hba * hba)6287 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6288 {
6289 	ufshcd_scsi_unblock_requests(hba);
6290 	ufshcd_release(hba);
6291 	if (ufshcd_is_clkscaling_supported(hba))
6292 		ufshcd_clk_scaling_suspend(hba, false);
6293 	ufshcd_rpm_put(hba);
6294 }
6295 
ufshcd_err_handling_should_stop(struct ufs_hba * hba)6296 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6297 {
6298 	return (!hba->is_powered || hba->shutting_down ||
6299 		!hba->ufs_device_wlun ||
6300 		hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6301 		(!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6302 		   ufshcd_is_link_broken(hba))));
6303 }
6304 
6305 #ifdef CONFIG_PM
ufshcd_recover_pm_error(struct ufs_hba * hba)6306 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6307 {
6308 	struct Scsi_Host *shost = hba->host;
6309 	struct scsi_device *sdev;
6310 	struct request_queue *q;
6311 	int ret;
6312 
6313 	hba->is_sys_suspended = false;
6314 	/*
6315 	 * Set RPM status of wlun device to RPM_ACTIVE,
6316 	 * this also clears its runtime error.
6317 	 */
6318 	ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6319 
6320 	/* hba device might have a runtime error otherwise */
6321 	if (ret)
6322 		ret = pm_runtime_set_active(hba->dev);
6323 	/*
6324 	 * If wlun device had runtime error, we also need to resume those
6325 	 * consumer scsi devices in case any of them has failed to be
6326 	 * resumed due to supplier runtime resume failure. This is to unblock
6327 	 * blk_queue_enter in case there are bios waiting inside it.
6328 	 */
6329 	if (!ret) {
6330 		shost_for_each_device(sdev, shost) {
6331 			q = sdev->request_queue;
6332 			if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6333 				       q->rpm_status == RPM_SUSPENDING))
6334 				pm_request_resume(q->dev);
6335 		}
6336 	}
6337 }
6338 #else
ufshcd_recover_pm_error(struct ufs_hba * hba)6339 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6340 {
6341 }
6342 #endif
6343 
ufshcd_is_pwr_mode_restore_needed(struct ufs_hba * hba)6344 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6345 {
6346 	struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6347 	u32 mode;
6348 
6349 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6350 
6351 	if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6352 		return true;
6353 
6354 	if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6355 		return true;
6356 
6357 	return false;
6358 }
6359 
ufshcd_abort_one(struct request * rq,void * priv)6360 static bool ufshcd_abort_one(struct request *rq, void *priv)
6361 {
6362 	int *ret = priv;
6363 	u32 tag = rq->tag;
6364 	struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
6365 	struct scsi_device *sdev = cmd->device;
6366 	struct Scsi_Host *shost = sdev->host;
6367 	struct ufs_hba *hba = shost_priv(shost);
6368 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6369 	struct ufs_hw_queue *hwq;
6370 	unsigned long flags;
6371 
6372 	*ret = ufshcd_try_to_abort_task(hba, tag);
6373 	dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6374 		hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6375 		*ret ? "failed" : "succeeded");
6376 
6377 	/* Release cmd in MCQ mode if abort succeeds */
6378 	if (is_mcq_enabled(hba) && (*ret == 0)) {
6379 		hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
6380 		if (!hwq)
6381 			return 0;
6382 		spin_lock_irqsave(&hwq->cq_lock, flags);
6383 		if (ufshcd_cmd_inflight(lrbp->cmd))
6384 			ufshcd_release_scsi_cmd(hba, lrbp);
6385 		spin_unlock_irqrestore(&hwq->cq_lock, flags);
6386 	}
6387 
6388 	return *ret == 0;
6389 }
6390 
6391 /**
6392  * ufshcd_abort_all - Abort all pending commands.
6393  * @hba: Host bus adapter pointer.
6394  *
6395  * Return: true if and only if the host controller needs to be reset.
6396  */
ufshcd_abort_all(struct ufs_hba * hba)6397 static bool ufshcd_abort_all(struct ufs_hba *hba)
6398 {
6399 	int tag, ret = 0;
6400 
6401 	blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret);
6402 	if (ret)
6403 		goto out;
6404 
6405 	/* Clear pending task management requests */
6406 	for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6407 		ret = ufshcd_clear_tm_cmd(hba, tag);
6408 		if (ret)
6409 			goto out;
6410 	}
6411 
6412 out:
6413 	/* Complete the requests that are cleared by s/w */
6414 	ufshcd_complete_requests(hba, false);
6415 
6416 	return ret != 0;
6417 }
6418 
6419 /**
6420  * ufshcd_err_handler - handle UFS errors that require s/w attention
6421  * @work: pointer to work structure
6422  */
ufshcd_err_handler(struct work_struct * work)6423 static void ufshcd_err_handler(struct work_struct *work)
6424 {
6425 	int retries = MAX_ERR_HANDLER_RETRIES;
6426 	struct ufs_hba *hba;
6427 	unsigned long flags;
6428 	bool needs_restore;
6429 	bool needs_reset;
6430 	int pmc_err;
6431 
6432 	hba = container_of(work, struct ufs_hba, eh_work);
6433 
6434 	dev_info(hba->dev,
6435 		 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6436 		 __func__, ufshcd_state_name[hba->ufshcd_state],
6437 		 hba->is_powered, hba->shutting_down, hba->saved_err,
6438 		 hba->saved_uic_err, hba->force_reset,
6439 		 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6440 
6441 	down(&hba->host_sem);
6442 	spin_lock_irqsave(hba->host->host_lock, flags);
6443 	if (ufshcd_err_handling_should_stop(hba)) {
6444 		if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6445 			hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6446 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6447 		up(&hba->host_sem);
6448 		return;
6449 	}
6450 	ufshcd_set_eh_in_progress(hba);
6451 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6452 	ufshcd_err_handling_prepare(hba);
6453 	/* Complete requests that have door-bell cleared by h/w */
6454 	ufshcd_complete_requests(hba, false);
6455 	spin_lock_irqsave(hba->host->host_lock, flags);
6456 again:
6457 	needs_restore = false;
6458 	needs_reset = false;
6459 
6460 	if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6461 		hba->ufshcd_state = UFSHCD_STATE_RESET;
6462 	/*
6463 	 * A full reset and restore might have happened after preparation
6464 	 * is finished, double check whether we should stop.
6465 	 */
6466 	if (ufshcd_err_handling_should_stop(hba))
6467 		goto skip_err_handling;
6468 
6469 	if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) &&
6470 	    !hba->force_reset) {
6471 		bool ret;
6472 
6473 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6474 		/* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6475 		ret = ufshcd_quirk_dl_nac_errors(hba);
6476 		spin_lock_irqsave(hba->host->host_lock, flags);
6477 		if (!ret && ufshcd_err_handling_should_stop(hba))
6478 			goto skip_err_handling;
6479 	}
6480 
6481 	if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6482 	    (hba->saved_uic_err &&
6483 	     (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6484 		bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6485 
6486 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6487 		ufshcd_print_host_state(hba);
6488 		ufshcd_print_pwr_info(hba);
6489 		ufshcd_print_evt_hist(hba);
6490 		ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6491 		ufshcd_print_trs_all(hba, pr_prdt);
6492 		spin_lock_irqsave(hba->host->host_lock, flags);
6493 	}
6494 
6495 	/*
6496 	 * if host reset is required then skip clearing the pending
6497 	 * transfers forcefully because they will get cleared during
6498 	 * host reset and restore
6499 	 */
6500 	if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6501 	    ufshcd_is_saved_err_fatal(hba) ||
6502 	    ((hba->saved_err & UIC_ERROR) &&
6503 	     (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6504 				    UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6505 		needs_reset = true;
6506 		goto do_reset;
6507 	}
6508 
6509 	/*
6510 	 * If LINERESET was caught, UFS might have been put to PWM mode,
6511 	 * check if power mode restore is needed.
6512 	 */
6513 	if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6514 		hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6515 		if (!hba->saved_uic_err)
6516 			hba->saved_err &= ~UIC_ERROR;
6517 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6518 		if (ufshcd_is_pwr_mode_restore_needed(hba))
6519 			needs_restore = true;
6520 		spin_lock_irqsave(hba->host->host_lock, flags);
6521 		if (!hba->saved_err && !needs_restore)
6522 			goto skip_err_handling;
6523 	}
6524 
6525 	hba->silence_err_logs = true;
6526 	/* release lock as clear command might sleep */
6527 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6528 
6529 	needs_reset = ufshcd_abort_all(hba);
6530 
6531 	spin_lock_irqsave(hba->host->host_lock, flags);
6532 	hba->silence_err_logs = false;
6533 	if (needs_reset)
6534 		goto do_reset;
6535 
6536 	/*
6537 	 * After all reqs and tasks are cleared from doorbell,
6538 	 * now it is safe to retore power mode.
6539 	 */
6540 	if (needs_restore) {
6541 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6542 		/*
6543 		 * Hold the scaling lock just in case dev cmds
6544 		 * are sent via bsg and/or sysfs.
6545 		 */
6546 		down_write(&hba->clk_scaling_lock);
6547 		hba->force_pmc = true;
6548 		pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6549 		if (pmc_err) {
6550 			needs_reset = true;
6551 			dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6552 					__func__, pmc_err);
6553 		}
6554 		hba->force_pmc = false;
6555 		ufshcd_print_pwr_info(hba);
6556 		up_write(&hba->clk_scaling_lock);
6557 		spin_lock_irqsave(hba->host->host_lock, flags);
6558 	}
6559 
6560 do_reset:
6561 	/* Fatal errors need reset */
6562 	if (needs_reset) {
6563 		int err;
6564 
6565 		hba->force_reset = false;
6566 		spin_unlock_irqrestore(hba->host->host_lock, flags);
6567 		err = ufshcd_reset_and_restore(hba);
6568 		if (err)
6569 			dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6570 					__func__, err);
6571 		else
6572 			ufshcd_recover_pm_error(hba);
6573 		spin_lock_irqsave(hba->host->host_lock, flags);
6574 	}
6575 
6576 skip_err_handling:
6577 	if (!needs_reset) {
6578 		if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6579 			hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6580 		if (hba->saved_err || hba->saved_uic_err)
6581 			dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6582 			    __func__, hba->saved_err, hba->saved_uic_err);
6583 	}
6584 	/* Exit in an operational state or dead */
6585 	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6586 	    hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6587 		if (--retries)
6588 			goto again;
6589 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
6590 	}
6591 	ufshcd_clear_eh_in_progress(hba);
6592 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6593 	ufshcd_err_handling_unprepare(hba);
6594 	up(&hba->host_sem);
6595 
6596 	dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6597 		 ufshcd_state_name[hba->ufshcd_state]);
6598 }
6599 
6600 /**
6601  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6602  * @hba: per-adapter instance
6603  *
6604  * Return:
6605  *  IRQ_HANDLED - If interrupt is valid
6606  *  IRQ_NONE    - If invalid interrupt
6607  */
ufshcd_update_uic_error(struct ufs_hba * hba)6608 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6609 {
6610 	u32 reg;
6611 	irqreturn_t retval = IRQ_NONE;
6612 
6613 	/* PHY layer error */
6614 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6615 	if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6616 	    (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6617 		ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6618 		/*
6619 		 * To know whether this error is fatal or not, DB timeout
6620 		 * must be checked but this error is handled separately.
6621 		 */
6622 		if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6623 			dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6624 					__func__);
6625 
6626 		/* Got a LINERESET indication. */
6627 		if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6628 			struct uic_command *cmd = NULL;
6629 
6630 			hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6631 			if (hba->uic_async_done && hba->active_uic_cmd)
6632 				cmd = hba->active_uic_cmd;
6633 			/*
6634 			 * Ignore the LINERESET during power mode change
6635 			 * operation via DME_SET command.
6636 			 */
6637 			if (cmd && (cmd->command == UIC_CMD_DME_SET))
6638 				hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6639 		}
6640 		retval |= IRQ_HANDLED;
6641 	}
6642 
6643 	/* PA_INIT_ERROR is fatal and needs UIC reset */
6644 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6645 	if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6646 	    (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6647 		ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6648 
6649 		if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6650 			hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6651 		else if (hba->dev_quirks &
6652 				UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6653 			if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6654 				hba->uic_error |=
6655 					UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6656 			else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6657 				hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6658 		}
6659 		retval |= IRQ_HANDLED;
6660 	}
6661 
6662 	/* UIC NL/TL/DME errors needs software retry */
6663 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6664 	if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6665 	    (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6666 		ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6667 		hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6668 		retval |= IRQ_HANDLED;
6669 	}
6670 
6671 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6672 	if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6673 	    (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6674 		ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6675 		hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6676 		retval |= IRQ_HANDLED;
6677 	}
6678 
6679 	reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6680 	if ((reg & UIC_DME_ERROR) &&
6681 	    (reg & UIC_DME_ERROR_CODE_MASK)) {
6682 		ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6683 		hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6684 		retval |= IRQ_HANDLED;
6685 	}
6686 
6687 	dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6688 			__func__, hba->uic_error);
6689 	return retval;
6690 }
6691 
6692 /**
6693  * ufshcd_check_errors - Check for errors that need s/w attention
6694  * @hba: per-adapter instance
6695  * @intr_status: interrupt status generated by the controller
6696  *
6697  * Return:
6698  *  IRQ_HANDLED - If interrupt is valid
6699  *  IRQ_NONE    - If invalid interrupt
6700  */
ufshcd_check_errors(struct ufs_hba * hba,u32 intr_status)6701 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6702 {
6703 	bool queue_eh_work = false;
6704 	irqreturn_t retval = IRQ_NONE;
6705 
6706 	spin_lock(hba->host->host_lock);
6707 	hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6708 
6709 	if (hba->errors & INT_FATAL_ERRORS) {
6710 		ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6711 				       hba->errors);
6712 		queue_eh_work = true;
6713 	}
6714 
6715 	if (hba->errors & UIC_ERROR) {
6716 		hba->uic_error = 0;
6717 		retval = ufshcd_update_uic_error(hba);
6718 		if (hba->uic_error)
6719 			queue_eh_work = true;
6720 	}
6721 
6722 	if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6723 		dev_err(hba->dev,
6724 			"%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6725 			__func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6726 			"Enter" : "Exit",
6727 			hba->errors, ufshcd_get_upmcrs(hba));
6728 		ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6729 				       hba->errors);
6730 		ufshcd_set_link_broken(hba);
6731 		queue_eh_work = true;
6732 	}
6733 
6734 	if (queue_eh_work) {
6735 		/*
6736 		 * update the transfer error masks to sticky bits, let's do this
6737 		 * irrespective of current ufshcd_state.
6738 		 */
6739 		hba->saved_err |= hba->errors;
6740 		hba->saved_uic_err |= hba->uic_error;
6741 
6742 		/* dump controller state before resetting */
6743 		if ((hba->saved_err &
6744 		     (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6745 		    (hba->saved_uic_err &&
6746 		     (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6747 			dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6748 					__func__, hba->saved_err,
6749 					hba->saved_uic_err);
6750 			ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6751 					 "host_regs: ");
6752 			ufshcd_print_pwr_info(hba);
6753 		}
6754 		ufshcd_schedule_eh_work(hba);
6755 		retval |= IRQ_HANDLED;
6756 	}
6757 	/*
6758 	 * if (!queue_eh_work) -
6759 	 * Other errors are either non-fatal where host recovers
6760 	 * itself without s/w intervention or errors that will be
6761 	 * handled by the SCSI core layer.
6762 	 */
6763 	hba->errors = 0;
6764 	hba->uic_error = 0;
6765 	spin_unlock(hba->host->host_lock);
6766 	return retval;
6767 }
6768 
6769 /**
6770  * ufshcd_tmc_handler - handle task management function completion
6771  * @hba: per adapter instance
6772  *
6773  * Return:
6774  *  IRQ_HANDLED - If interrupt is valid
6775  *  IRQ_NONE    - If invalid interrupt
6776  */
ufshcd_tmc_handler(struct ufs_hba * hba)6777 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6778 {
6779 	unsigned long flags, pending, issued;
6780 	irqreturn_t ret = IRQ_NONE;
6781 	int tag;
6782 
6783 	spin_lock_irqsave(hba->host->host_lock, flags);
6784 	pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6785 	issued = hba->outstanding_tasks & ~pending;
6786 	for_each_set_bit(tag, &issued, hba->nutmrs) {
6787 		struct request *req = hba->tmf_rqs[tag];
6788 		struct completion *c = req->end_io_data;
6789 
6790 		complete(c);
6791 		ret = IRQ_HANDLED;
6792 	}
6793 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6794 
6795 	return ret;
6796 }
6797 
6798 /**
6799  * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
6800  * @hba: per adapter instance
6801  *
6802  * Return: IRQ_HANDLED if interrupt is handled.
6803  */
ufshcd_handle_mcq_cq_events(struct ufs_hba * hba)6804 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
6805 {
6806 	struct ufs_hw_queue *hwq;
6807 	unsigned long outstanding_cqs;
6808 	unsigned int nr_queues;
6809 	int i, ret;
6810 	u32 events;
6811 
6812 	ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs);
6813 	if (ret)
6814 		outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
6815 
6816 	/* Exclude the poll queues */
6817 	nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
6818 	for_each_set_bit(i, &outstanding_cqs, nr_queues) {
6819 		hwq = &hba->uhq[i];
6820 
6821 		events = ufshcd_mcq_read_cqis(hba, i);
6822 		if (events)
6823 			ufshcd_mcq_write_cqis(hba, events, i);
6824 
6825 		if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
6826 			ufshcd_mcq_poll_cqe_lock(hba, hwq);
6827 	}
6828 
6829 	return IRQ_HANDLED;
6830 }
6831 
6832 /**
6833  * ufshcd_sl_intr - Interrupt service routine
6834  * @hba: per adapter instance
6835  * @intr_status: contains interrupts generated by the controller
6836  *
6837  * Return:
6838  *  IRQ_HANDLED - If interrupt is valid
6839  *  IRQ_NONE    - If invalid interrupt
6840  */
ufshcd_sl_intr(struct ufs_hba * hba,u32 intr_status)6841 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6842 {
6843 	irqreturn_t retval = IRQ_NONE;
6844 
6845 	if (intr_status & UFSHCD_UIC_MASK)
6846 		retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6847 
6848 	if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6849 		retval |= ufshcd_check_errors(hba, intr_status);
6850 
6851 	if (intr_status & UTP_TASK_REQ_COMPL)
6852 		retval |= ufshcd_tmc_handler(hba);
6853 
6854 	if (intr_status & UTP_TRANSFER_REQ_COMPL)
6855 		retval |= ufshcd_transfer_req_compl(hba);
6856 
6857 	if (intr_status & MCQ_CQ_EVENT_STATUS)
6858 		retval |= ufshcd_handle_mcq_cq_events(hba);
6859 
6860 	return retval;
6861 }
6862 
6863 /**
6864  * ufshcd_intr - Main interrupt service routine
6865  * @irq: irq number
6866  * @__hba: pointer to adapter instance
6867  *
6868  * Return:
6869  *  IRQ_HANDLED - If interrupt is valid
6870  *  IRQ_NONE    - If invalid interrupt
6871  */
ufshcd_intr(int irq,void * __hba)6872 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6873 {
6874 	u32 intr_status, enabled_intr_status = 0;
6875 	irqreturn_t retval = IRQ_NONE;
6876 	struct ufs_hba *hba = __hba;
6877 	int retries = hba->nutrs;
6878 
6879 	intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6880 	hba->ufs_stats.last_intr_status = intr_status;
6881 	hba->ufs_stats.last_intr_ts = local_clock();
6882 
6883 	/*
6884 	 * There could be max of hba->nutrs reqs in flight and in worst case
6885 	 * if the reqs get finished 1 by 1 after the interrupt status is
6886 	 * read, make sure we handle them by checking the interrupt status
6887 	 * again in a loop until we process all of the reqs before returning.
6888 	 */
6889 	while (intr_status && retries--) {
6890 		enabled_intr_status =
6891 			intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6892 		ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6893 		if (enabled_intr_status)
6894 			retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6895 
6896 		intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6897 	}
6898 
6899 	if (enabled_intr_status && retval == IRQ_NONE &&
6900 	    (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6901 	     hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6902 		dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6903 					__func__,
6904 					intr_status,
6905 					hba->ufs_stats.last_intr_status,
6906 					enabled_intr_status);
6907 		ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6908 	}
6909 
6910 	return retval;
6911 }
6912 
ufshcd_clear_tm_cmd(struct ufs_hba * hba,int tag)6913 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6914 {
6915 	int err = 0;
6916 	u32 mask = 1 << tag;
6917 	unsigned long flags;
6918 
6919 	if (!test_bit(tag, &hba->outstanding_tasks))
6920 		goto out;
6921 
6922 	spin_lock_irqsave(hba->host->host_lock, flags);
6923 	ufshcd_utmrl_clear(hba, tag);
6924 	spin_unlock_irqrestore(hba->host->host_lock, flags);
6925 
6926 	/* poll for max. 1 sec to clear door bell register by h/w */
6927 	err = ufshcd_wait_for_register(hba,
6928 			REG_UTP_TASK_REQ_DOOR_BELL,
6929 			mask, 0, 1000, 1000);
6930 
6931 	dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6932 		tag, err < 0 ? "failed" : "succeeded");
6933 
6934 out:
6935 	return err;
6936 }
6937 
__ufshcd_issue_tm_cmd(struct ufs_hba * hba,struct utp_task_req_desc * treq,u8 tm_function)6938 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6939 		struct utp_task_req_desc *treq, u8 tm_function)
6940 {
6941 	struct request_queue *q = hba->tmf_queue;
6942 	struct Scsi_Host *host = hba->host;
6943 	DECLARE_COMPLETION_ONSTACK(wait);
6944 	struct request *req;
6945 	unsigned long flags;
6946 	int task_tag, err;
6947 
6948 	/*
6949 	 * blk_mq_alloc_request() is used here only to get a free tag.
6950 	 */
6951 	req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
6952 	if (IS_ERR(req))
6953 		return PTR_ERR(req);
6954 
6955 	req->end_io_data = &wait;
6956 	ufshcd_hold(hba);
6957 
6958 	spin_lock_irqsave(host->host_lock, flags);
6959 
6960 	task_tag = req->tag;
6961 	WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6962 		  task_tag);
6963 	hba->tmf_rqs[req->tag] = req;
6964 	treq->upiu_req.req_header.task_tag = task_tag;
6965 
6966 	memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6967 	ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6968 
6969 	/* send command to the controller */
6970 	__set_bit(task_tag, &hba->outstanding_tasks);
6971 
6972 	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6973 	/* Make sure that doorbell is committed immediately */
6974 	wmb();
6975 
6976 	spin_unlock_irqrestore(host->host_lock, flags);
6977 
6978 	ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6979 
6980 	/* wait until the task management command is completed */
6981 	err = wait_for_completion_io_timeout(&wait,
6982 			msecs_to_jiffies(TM_CMD_TIMEOUT));
6983 	if (!err) {
6984 		ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6985 		dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6986 				__func__, tm_function);
6987 		if (ufshcd_clear_tm_cmd(hba, task_tag))
6988 			dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6989 					__func__, task_tag);
6990 		err = -ETIMEDOUT;
6991 	} else {
6992 		err = 0;
6993 		memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6994 
6995 		ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6996 	}
6997 
6998 	spin_lock_irqsave(hba->host->host_lock, flags);
6999 	hba->tmf_rqs[req->tag] = NULL;
7000 	__clear_bit(task_tag, &hba->outstanding_tasks);
7001 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7002 
7003 	ufshcd_release(hba);
7004 	blk_mq_free_request(req);
7005 
7006 	return err;
7007 }
7008 
7009 /**
7010  * ufshcd_issue_tm_cmd - issues task management commands to controller
7011  * @hba: per adapter instance
7012  * @lun_id: LUN ID to which TM command is sent
7013  * @task_id: task ID to which the TM command is applicable
7014  * @tm_function: task management function opcode
7015  * @tm_response: task management service response return value
7016  *
7017  * Return: non-zero value on error, zero on success.
7018  */
ufshcd_issue_tm_cmd(struct ufs_hba * hba,int lun_id,int task_id,u8 tm_function,u8 * tm_response)7019 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
7020 		u8 tm_function, u8 *tm_response)
7021 {
7022 	struct utp_task_req_desc treq = { };
7023 	enum utp_ocs ocs_value;
7024 	int err;
7025 
7026 	/* Configure task request descriptor */
7027 	treq.header.interrupt = 1;
7028 	treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7029 
7030 	/* Configure task request UPIU */
7031 	treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ;
7032 	treq.upiu_req.req_header.lun = lun_id;
7033 	treq.upiu_req.req_header.tm_function = tm_function;
7034 
7035 	/*
7036 	 * The host shall provide the same value for LUN field in the basic
7037 	 * header and for Input Parameter.
7038 	 */
7039 	treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
7040 	treq.upiu_req.input_param2 = cpu_to_be32(task_id);
7041 
7042 	err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
7043 	if (err == -ETIMEDOUT)
7044 		return err;
7045 
7046 	ocs_value = treq.header.ocs & MASK_OCS;
7047 	if (ocs_value != OCS_SUCCESS)
7048 		dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
7049 				__func__, ocs_value);
7050 	else if (tm_response)
7051 		*tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
7052 				MASK_TM_SERVICE_RESP;
7053 	return err;
7054 }
7055 
7056 /**
7057  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
7058  * @hba:	per-adapter instance
7059  * @req_upiu:	upiu request
7060  * @rsp_upiu:	upiu reply
7061  * @desc_buff:	pointer to descriptor buffer, NULL if NA
7062  * @buff_len:	descriptor size, 0 if NA
7063  * @cmd_type:	specifies the type (NOP, Query...)
7064  * @desc_op:	descriptor operation
7065  *
7066  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
7067  * Therefore, it "rides" the device management infrastructure: uses its tag and
7068  * tasks work queues.
7069  *
7070  * Since there is only one available tag for device management commands,
7071  * the caller is expected to hold the hba->dev_cmd.lock mutex.
7072  *
7073  * Return: 0 upon success; < 0 upon failure.
7074  */
ufshcd_issue_devman_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,u8 * desc_buff,int * buff_len,enum dev_cmd_type cmd_type,enum query_opcode desc_op)7075 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
7076 					struct utp_upiu_req *req_upiu,
7077 					struct utp_upiu_req *rsp_upiu,
7078 					u8 *desc_buff, int *buff_len,
7079 					enum dev_cmd_type cmd_type,
7080 					enum query_opcode desc_op)
7081 {
7082 	DECLARE_COMPLETION_ONSTACK(wait);
7083 	const u32 tag = hba->reserved_slot;
7084 	struct ufshcd_lrb *lrbp;
7085 	int err = 0;
7086 	u8 upiu_flags;
7087 
7088 	/* Protects use of hba->reserved_slot. */
7089 	lockdep_assert_held(&hba->dev_cmd.lock);
7090 
7091 	down_read(&hba->clk_scaling_lock);
7092 
7093 	lrbp = &hba->lrb[tag];
7094 	lrbp->cmd = NULL;
7095 	lrbp->task_tag = tag;
7096 	lrbp->lun = 0;
7097 	lrbp->intr_cmd = true;
7098 	ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7099 	hba->dev_cmd.type = cmd_type;
7100 
7101 	if (hba->ufs_version <= ufshci_version(1, 1))
7102 		lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
7103 	else
7104 		lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7105 
7106 	/* update the task tag in the request upiu */
7107 	req_upiu->header.task_tag = tag;
7108 
7109 	ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
7110 
7111 	/* just copy the upiu request as it is */
7112 	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7113 	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7114 		/* The Data Segment Area is optional depending upon the query
7115 		 * function value. for WRITE DESCRIPTOR, the data segment
7116 		 * follows right after the tsf.
7117 		 */
7118 		memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7119 		*buff_len = 0;
7120 	}
7121 
7122 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7123 
7124 	hba->dev_cmd.complete = &wait;
7125 
7126 	ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
7127 
7128 	ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7129 	/*
7130 	 * ignore the returning value here - ufshcd_check_query_response is
7131 	 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
7132 	 * read the response directly ignoring all errors.
7133 	 */
7134 	ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
7135 
7136 	/* just copy the upiu response as it is */
7137 	memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7138 	if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7139 		u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7140 		u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
7141 					   .data_segment_length);
7142 
7143 		if (*buff_len >= resp_len) {
7144 			memcpy(desc_buff, descp, resp_len);
7145 			*buff_len = resp_len;
7146 		} else {
7147 			dev_warn(hba->dev,
7148 				 "%s: rsp size %d is bigger than buffer size %d",
7149 				 __func__, resp_len, *buff_len);
7150 			*buff_len = 0;
7151 			err = -EINVAL;
7152 		}
7153 	}
7154 	ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
7155 				    (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
7156 
7157 	up_read(&hba->clk_scaling_lock);
7158 	return err;
7159 }
7160 
7161 /**
7162  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7163  * @hba:	per-adapter instance
7164  * @req_upiu:	upiu request
7165  * @rsp_upiu:	upiu reply - only 8 DW as we do not support scsi commands
7166  * @msgcode:	message code, one of UPIU Transaction Codes Initiator to Target
7167  * @desc_buff:	pointer to descriptor buffer, NULL if NA
7168  * @buff_len:	descriptor size, 0 if NA
7169  * @desc_op:	descriptor operation
7170  *
7171  * Supports UTP Transfer requests (nop and query), and UTP Task
7172  * Management requests.
7173  * It is up to the caller to fill the upiu conent properly, as it will
7174  * be copied without any further input validations.
7175  *
7176  * Return: 0 upon success; < 0 upon failure.
7177  */
ufshcd_exec_raw_upiu_cmd(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,enum upiu_request_transaction msgcode,u8 * desc_buff,int * buff_len,enum query_opcode desc_op)7178 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7179 			     struct utp_upiu_req *req_upiu,
7180 			     struct utp_upiu_req *rsp_upiu,
7181 			     enum upiu_request_transaction msgcode,
7182 			     u8 *desc_buff, int *buff_len,
7183 			     enum query_opcode desc_op)
7184 {
7185 	int err;
7186 	enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7187 	struct utp_task_req_desc treq = { };
7188 	enum utp_ocs ocs_value;
7189 	u8 tm_f = req_upiu->header.tm_function;
7190 
7191 	switch (msgcode) {
7192 	case UPIU_TRANSACTION_NOP_OUT:
7193 		cmd_type = DEV_CMD_TYPE_NOP;
7194 		fallthrough;
7195 	case UPIU_TRANSACTION_QUERY_REQ:
7196 		ufshcd_hold(hba);
7197 		mutex_lock(&hba->dev_cmd.lock);
7198 		err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7199 						   desc_buff, buff_len,
7200 						   cmd_type, desc_op);
7201 		mutex_unlock(&hba->dev_cmd.lock);
7202 		ufshcd_release(hba);
7203 
7204 		break;
7205 	case UPIU_TRANSACTION_TASK_REQ:
7206 		treq.header.interrupt = 1;
7207 		treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7208 
7209 		memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7210 
7211 		err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
7212 		if (err == -ETIMEDOUT)
7213 			break;
7214 
7215 		ocs_value = treq.header.ocs & MASK_OCS;
7216 		if (ocs_value != OCS_SUCCESS) {
7217 			dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7218 				ocs_value);
7219 			break;
7220 		}
7221 
7222 		memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7223 
7224 		break;
7225 	default:
7226 		err = -EINVAL;
7227 
7228 		break;
7229 	}
7230 
7231 	return err;
7232 }
7233 
7234 /**
7235  * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7236  * @hba:	per adapter instance
7237  * @req_upiu:	upiu request
7238  * @rsp_upiu:	upiu reply
7239  * @req_ehs:	EHS field which contains Advanced RPMB Request Message
7240  * @rsp_ehs:	EHS field which returns Advanced RPMB Response Message
7241  * @sg_cnt:	The number of sg lists actually used
7242  * @sg_list:	Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7243  * @dir:	DMA direction
7244  *
7245  * Return: zero on success, non-zero on failure.
7246  */
ufshcd_advanced_rpmb_req_handler(struct ufs_hba * hba,struct utp_upiu_req * req_upiu,struct utp_upiu_req * rsp_upiu,struct ufs_ehs * req_ehs,struct ufs_ehs * rsp_ehs,int sg_cnt,struct scatterlist * sg_list,enum dma_data_direction dir)7247 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7248 			 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7249 			 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7250 			 enum dma_data_direction dir)
7251 {
7252 	DECLARE_COMPLETION_ONSTACK(wait);
7253 	const u32 tag = hba->reserved_slot;
7254 	struct ufshcd_lrb *lrbp;
7255 	int err = 0;
7256 	int result;
7257 	u8 upiu_flags;
7258 	u8 *ehs_data;
7259 	u16 ehs_len;
7260 
7261 	/* Protects use of hba->reserved_slot. */
7262 	ufshcd_hold(hba);
7263 	mutex_lock(&hba->dev_cmd.lock);
7264 	down_read(&hba->clk_scaling_lock);
7265 
7266 	lrbp = &hba->lrb[tag];
7267 	lrbp->cmd = NULL;
7268 	lrbp->task_tag = tag;
7269 	lrbp->lun = UFS_UPIU_RPMB_WLUN;
7270 
7271 	lrbp->intr_cmd = true;
7272 	ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7273 	hba->dev_cmd.type = DEV_CMD_TYPE_RPMB;
7274 
7275 	/* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */
7276 	lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7277 
7278 	/*
7279 	 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes
7280 	 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1,
7281 	 * HW controller takes EHS length from UTRD.
7282 	 */
7283 	if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED)
7284 		ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2);
7285 	else
7286 		ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0);
7287 
7288 	/* update the task tag */
7289 	req_upiu->header.task_tag = tag;
7290 
7291 	/* copy the UPIU(contains CDB) request as it is */
7292 	memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7293 	/* Copy EHS, starting with byte32, immediately after the CDB package */
7294 	memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7295 
7296 	if (dir != DMA_NONE && sg_list)
7297 		ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7298 
7299 	memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7300 
7301 	hba->dev_cmd.complete = &wait;
7302 
7303 	ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7304 
7305 	err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT);
7306 
7307 	if (!err) {
7308 		/* Just copy the upiu response as it is */
7309 		memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7310 		/* Get the response UPIU result */
7311 		result = (lrbp->ucd_rsp_ptr->header.response << 8) |
7312 			lrbp->ucd_rsp_ptr->header.status;
7313 
7314 		ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length;
7315 		/*
7316 		 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7317 		 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7318 		 * Message is 02h
7319 		 */
7320 		if (ehs_len == 2 && rsp_ehs) {
7321 			/*
7322 			 * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7323 			 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7324 			 */
7325 			ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7326 			memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7327 		}
7328 	}
7329 
7330 	up_read(&hba->clk_scaling_lock);
7331 	mutex_unlock(&hba->dev_cmd.lock);
7332 	ufshcd_release(hba);
7333 	return err ? : result;
7334 }
7335 
7336 /**
7337  * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7338  * @cmd: SCSI command pointer
7339  *
7340  * Return: SUCCESS or FAILED.
7341  */
ufshcd_eh_device_reset_handler(struct scsi_cmnd * cmd)7342 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7343 {
7344 	unsigned long flags, pending_reqs = 0, not_cleared = 0;
7345 	struct Scsi_Host *host;
7346 	struct ufs_hba *hba;
7347 	struct ufs_hw_queue *hwq;
7348 	struct ufshcd_lrb *lrbp;
7349 	u32 pos, not_cleared_mask = 0;
7350 	int err;
7351 	u8 resp = 0xF, lun;
7352 
7353 	host = cmd->device->host;
7354 	hba = shost_priv(host);
7355 
7356 	lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7357 	err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7358 	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7359 		if (!err)
7360 			err = resp;
7361 		goto out;
7362 	}
7363 
7364 	if (is_mcq_enabled(hba)) {
7365 		for (pos = 0; pos < hba->nutrs; pos++) {
7366 			lrbp = &hba->lrb[pos];
7367 			if (ufshcd_cmd_inflight(lrbp->cmd) &&
7368 			    lrbp->lun == lun) {
7369 				ufshcd_clear_cmd(hba, pos);
7370 				hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
7371 				ufshcd_mcq_poll_cqe_lock(hba, hwq);
7372 			}
7373 		}
7374 		err = 0;
7375 		goto out;
7376 	}
7377 
7378 	/* clear the commands that were pending for corresponding LUN */
7379 	spin_lock_irqsave(&hba->outstanding_lock, flags);
7380 	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7381 		if (hba->lrb[pos].lun == lun)
7382 			__set_bit(pos, &pending_reqs);
7383 	hba->outstanding_reqs &= ~pending_reqs;
7384 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7385 
7386 	for_each_set_bit(pos, &pending_reqs, hba->nutrs) {
7387 		if (ufshcd_clear_cmd(hba, pos) < 0) {
7388 			spin_lock_irqsave(&hba->outstanding_lock, flags);
7389 			not_cleared = 1U << pos &
7390 				ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7391 			hba->outstanding_reqs |= not_cleared;
7392 			not_cleared_mask |= not_cleared;
7393 			spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7394 
7395 			dev_err(hba->dev, "%s: failed to clear request %d\n",
7396 				__func__, pos);
7397 		}
7398 	}
7399 	__ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask);
7400 
7401 out:
7402 	hba->req_abort_count = 0;
7403 	ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7404 	if (!err) {
7405 		err = SUCCESS;
7406 	} else {
7407 		dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7408 		err = FAILED;
7409 	}
7410 	return err;
7411 }
7412 
ufshcd_set_req_abort_skip(struct ufs_hba * hba,unsigned long bitmap)7413 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7414 {
7415 	struct ufshcd_lrb *lrbp;
7416 	int tag;
7417 
7418 	for_each_set_bit(tag, &bitmap, hba->nutrs) {
7419 		lrbp = &hba->lrb[tag];
7420 		lrbp->req_abort_skip = true;
7421 	}
7422 }
7423 
7424 /**
7425  * ufshcd_try_to_abort_task - abort a specific task
7426  * @hba: Pointer to adapter instance
7427  * @tag: Task tag/index to be aborted
7428  *
7429  * Abort the pending command in device by sending UFS_ABORT_TASK task management
7430  * command, and in host controller by clearing the door-bell register. There can
7431  * be race between controller sending the command to the device while abort is
7432  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7433  * really issued and then try to abort it.
7434  *
7435  * Return: zero on success, non-zero on failure.
7436  */
ufshcd_try_to_abort_task(struct ufs_hba * hba,int tag)7437 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7438 {
7439 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7440 	int err = 0;
7441 	int poll_cnt;
7442 	u8 resp = 0xF;
7443 	u32 reg;
7444 
7445 	for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7446 		err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7447 				UFS_QUERY_TASK, &resp);
7448 		if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7449 			/* cmd pending in the device */
7450 			dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7451 				__func__, tag);
7452 			break;
7453 		} else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7454 			/*
7455 			 * cmd not pending in the device, check if it is
7456 			 * in transition.
7457 			 */
7458 			dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7459 				__func__, tag);
7460 			if (is_mcq_enabled(hba)) {
7461 				/* MCQ mode */
7462 				if (ufshcd_cmd_inflight(lrbp->cmd)) {
7463 					/* sleep for max. 200us same delay as in SDB mode */
7464 					usleep_range(100, 200);
7465 					continue;
7466 				}
7467 				/* command completed already */
7468 				dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n",
7469 					__func__, tag);
7470 				goto out;
7471 			}
7472 
7473 			/* Single Doorbell Mode */
7474 			reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7475 			if (reg & (1 << tag)) {
7476 				/* sleep for max. 200us to stabilize */
7477 				usleep_range(100, 200);
7478 				continue;
7479 			}
7480 			/* command completed already */
7481 			dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7482 				__func__, tag);
7483 			goto out;
7484 		} else {
7485 			dev_err(hba->dev,
7486 				"%s: no response from device. tag = %d, err %d\n",
7487 				__func__, tag, err);
7488 			if (!err)
7489 				err = resp; /* service response error */
7490 			goto out;
7491 		}
7492 	}
7493 
7494 	if (!poll_cnt) {
7495 		err = -EBUSY;
7496 		goto out;
7497 	}
7498 
7499 	err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7500 			UFS_ABORT_TASK, &resp);
7501 	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7502 		if (!err) {
7503 			err = resp; /* service response error */
7504 			dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7505 				__func__, tag, err);
7506 		}
7507 		goto out;
7508 	}
7509 
7510 	err = ufshcd_clear_cmd(hba, tag);
7511 	if (err)
7512 		dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7513 			__func__, tag, err);
7514 
7515 out:
7516 	return err;
7517 }
7518 
7519 /**
7520  * ufshcd_abort - scsi host template eh_abort_handler callback
7521  * @cmd: SCSI command pointer
7522  *
7523  * Return: SUCCESS or FAILED.
7524  */
ufshcd_abort(struct scsi_cmnd * cmd)7525 static int ufshcd_abort(struct scsi_cmnd *cmd)
7526 {
7527 	struct Scsi_Host *host = cmd->device->host;
7528 	struct ufs_hba *hba = shost_priv(host);
7529 	int tag = scsi_cmd_to_rq(cmd)->tag;
7530 	struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7531 	unsigned long flags;
7532 	int err = FAILED;
7533 	bool outstanding;
7534 	u32 reg;
7535 
7536 	WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7537 
7538 	ufshcd_hold(hba);
7539 
7540 	if (!is_mcq_enabled(hba)) {
7541 		reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7542 		if (!test_bit(tag, &hba->outstanding_reqs)) {
7543 			/* If command is already aborted/completed, return FAILED. */
7544 			dev_err(hba->dev,
7545 				"%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7546 				__func__, tag, hba->outstanding_reqs, reg);
7547 			goto release;
7548 		}
7549 	}
7550 
7551 	/* Print Transfer Request of aborted task */
7552 	dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7553 
7554 	/*
7555 	 * Print detailed info about aborted request.
7556 	 * As more than one request might get aborted at the same time,
7557 	 * print full information only for the first aborted request in order
7558 	 * to reduce repeated printouts. For other aborted requests only print
7559 	 * basic details.
7560 	 */
7561 	scsi_print_command(cmd);
7562 	if (!hba->req_abort_count) {
7563 		ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7564 		ufshcd_print_evt_hist(hba);
7565 		ufshcd_print_host_state(hba);
7566 		ufshcd_print_pwr_info(hba);
7567 		ufshcd_print_tr(hba, tag, true);
7568 	} else {
7569 		ufshcd_print_tr(hba, tag, false);
7570 	}
7571 	hba->req_abort_count++;
7572 
7573 	if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) {
7574 		/* only execute this code in single doorbell mode */
7575 		dev_err(hba->dev,
7576 		"%s: cmd was completed, but without a notifying intr, tag = %d",
7577 		__func__, tag);
7578 		__ufshcd_transfer_req_compl(hba, 1UL << tag);
7579 		goto release;
7580 	}
7581 
7582 	/*
7583 	 * Task abort to the device W-LUN is illegal. When this command
7584 	 * will fail, due to spec violation, scsi err handling next step
7585 	 * will be to send LU reset which, again, is a spec violation.
7586 	 * To avoid these unnecessary/illegal steps, first we clean up
7587 	 * the lrb taken by this cmd and re-set it in outstanding_reqs,
7588 	 * then queue the eh_work and bail.
7589 	 */
7590 	if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7591 		ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7592 
7593 		spin_lock_irqsave(host->host_lock, flags);
7594 		hba->force_reset = true;
7595 		ufshcd_schedule_eh_work(hba);
7596 		spin_unlock_irqrestore(host->host_lock, flags);
7597 		goto release;
7598 	}
7599 
7600 	if (is_mcq_enabled(hba)) {
7601 		/* MCQ mode. Branch off to handle abort for mcq mode */
7602 		err = ufshcd_mcq_abort(cmd);
7603 		goto release;
7604 	}
7605 
7606 	/* Skip task abort in case previous aborts failed and report failure */
7607 	if (lrbp->req_abort_skip) {
7608 		dev_err(hba->dev, "%s: skipping abort\n", __func__);
7609 		ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7610 		goto release;
7611 	}
7612 
7613 	err = ufshcd_try_to_abort_task(hba, tag);
7614 	if (err) {
7615 		dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7616 		ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7617 		err = FAILED;
7618 		goto release;
7619 	}
7620 
7621 	/*
7622 	 * Clear the corresponding bit from outstanding_reqs since the command
7623 	 * has been aborted successfully.
7624 	 */
7625 	spin_lock_irqsave(&hba->outstanding_lock, flags);
7626 	outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7627 	spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7628 
7629 	if (outstanding)
7630 		ufshcd_release_scsi_cmd(hba, lrbp);
7631 
7632 	err = SUCCESS;
7633 
7634 release:
7635 	/* Matches the ufshcd_hold() call at the start of this function. */
7636 	ufshcd_release(hba);
7637 	return err;
7638 }
7639 
7640 /**
7641  * ufshcd_host_reset_and_restore - reset and restore host controller
7642  * @hba: per-adapter instance
7643  *
7644  * Note that host controller reset may issue DME_RESET to
7645  * local and remote (device) Uni-Pro stack and the attributes
7646  * are reset to default state.
7647  *
7648  * Return: zero on success, non-zero on failure.
7649  */
ufshcd_host_reset_and_restore(struct ufs_hba * hba)7650 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7651 {
7652 	int err;
7653 
7654 	/*
7655 	 * Stop the host controller and complete the requests
7656 	 * cleared by h/w
7657 	 */
7658 	ufshcd_hba_stop(hba);
7659 	hba->silence_err_logs = true;
7660 	ufshcd_complete_requests(hba, true);
7661 	hba->silence_err_logs = false;
7662 
7663 	/* scale up clocks to max frequency before full reinitialization */
7664 	ufshcd_scale_clks(hba, true);
7665 
7666 	err = ufshcd_hba_enable(hba);
7667 
7668 	/* Establish the link again and restore the device */
7669 	if (!err)
7670 		err = ufshcd_probe_hba(hba, false);
7671 
7672 	if (err)
7673 		dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7674 	ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7675 	return err;
7676 }
7677 
7678 /**
7679  * ufshcd_reset_and_restore - reset and re-initialize host/device
7680  * @hba: per-adapter instance
7681  *
7682  * Reset and recover device, host and re-establish link. This
7683  * is helpful to recover the communication in fatal error conditions.
7684  *
7685  * Return: zero on success, non-zero on failure.
7686  */
ufshcd_reset_and_restore(struct ufs_hba * hba)7687 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7688 {
7689 	u32 saved_err = 0;
7690 	u32 saved_uic_err = 0;
7691 	int err = 0;
7692 	unsigned long flags;
7693 	int retries = MAX_HOST_RESET_RETRIES;
7694 
7695 	spin_lock_irqsave(hba->host->host_lock, flags);
7696 	do {
7697 		/*
7698 		 * This is a fresh start, cache and clear saved error first,
7699 		 * in case new error generated during reset and restore.
7700 		 */
7701 		saved_err |= hba->saved_err;
7702 		saved_uic_err |= hba->saved_uic_err;
7703 		hba->saved_err = 0;
7704 		hba->saved_uic_err = 0;
7705 		hba->force_reset = false;
7706 		hba->ufshcd_state = UFSHCD_STATE_RESET;
7707 		spin_unlock_irqrestore(hba->host->host_lock, flags);
7708 
7709 		/* Reset the attached device */
7710 		ufshcd_device_reset(hba);
7711 
7712 		err = ufshcd_host_reset_and_restore(hba);
7713 
7714 		spin_lock_irqsave(hba->host->host_lock, flags);
7715 		if (err)
7716 			continue;
7717 		/* Do not exit unless operational or dead */
7718 		if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7719 		    hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7720 		    hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7721 			err = -EAGAIN;
7722 	} while (err && --retries);
7723 
7724 	/*
7725 	 * Inform scsi mid-layer that we did reset and allow to handle
7726 	 * Unit Attention properly.
7727 	 */
7728 	scsi_report_bus_reset(hba->host, 0);
7729 	if (err) {
7730 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
7731 		hba->saved_err |= saved_err;
7732 		hba->saved_uic_err |= saved_uic_err;
7733 	}
7734 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7735 
7736 	return err;
7737 }
7738 
7739 /**
7740  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7741  * @cmd: SCSI command pointer
7742  *
7743  * Return: SUCCESS or FAILED.
7744  */
ufshcd_eh_host_reset_handler(struct scsi_cmnd * cmd)7745 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7746 {
7747 	int err = SUCCESS;
7748 	unsigned long flags;
7749 	struct ufs_hba *hba;
7750 
7751 	hba = shost_priv(cmd->device->host);
7752 
7753 	spin_lock_irqsave(hba->host->host_lock, flags);
7754 	hba->force_reset = true;
7755 	ufshcd_schedule_eh_work(hba);
7756 	dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7757 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7758 
7759 	flush_work(&hba->eh_work);
7760 
7761 	spin_lock_irqsave(hba->host->host_lock, flags);
7762 	if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7763 		err = FAILED;
7764 	spin_unlock_irqrestore(hba->host->host_lock, flags);
7765 
7766 	return err;
7767 }
7768 
7769 /**
7770  * ufshcd_get_max_icc_level - calculate the ICC level
7771  * @sup_curr_uA: max. current supported by the regulator
7772  * @start_scan: row at the desc table to start scan from
7773  * @buff: power descriptor buffer
7774  *
7775  * Return: calculated max ICC level for specific regulator.
7776  */
ufshcd_get_max_icc_level(int sup_curr_uA,u32 start_scan,const char * buff)7777 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7778 				    const char *buff)
7779 {
7780 	int i;
7781 	int curr_uA;
7782 	u16 data;
7783 	u16 unit;
7784 
7785 	for (i = start_scan; i >= 0; i--) {
7786 		data = get_unaligned_be16(&buff[2 * i]);
7787 		unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7788 						ATTR_ICC_LVL_UNIT_OFFSET;
7789 		curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7790 		switch (unit) {
7791 		case UFSHCD_NANO_AMP:
7792 			curr_uA = curr_uA / 1000;
7793 			break;
7794 		case UFSHCD_MILI_AMP:
7795 			curr_uA = curr_uA * 1000;
7796 			break;
7797 		case UFSHCD_AMP:
7798 			curr_uA = curr_uA * 1000 * 1000;
7799 			break;
7800 		case UFSHCD_MICRO_AMP:
7801 		default:
7802 			break;
7803 		}
7804 		if (sup_curr_uA >= curr_uA)
7805 			break;
7806 	}
7807 	if (i < 0) {
7808 		i = 0;
7809 		pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7810 	}
7811 
7812 	return (u32)i;
7813 }
7814 
7815 /**
7816  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7817  * In case regulators are not initialized we'll return 0
7818  * @hba: per-adapter instance
7819  * @desc_buf: power descriptor buffer to extract ICC levels from.
7820  *
7821  * Return: calculated ICC level.
7822  */
ufshcd_find_max_sup_active_icc_level(struct ufs_hba * hba,const u8 * desc_buf)7823 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7824 						const u8 *desc_buf)
7825 {
7826 	u32 icc_level = 0;
7827 
7828 	if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7829 						!hba->vreg_info.vccq2) {
7830 		/*
7831 		 * Using dev_dbg to avoid messages during runtime PM to avoid
7832 		 * never-ending cycles of messages written back to storage by
7833 		 * user space causing runtime resume, causing more messages and
7834 		 * so on.
7835 		 */
7836 		dev_dbg(hba->dev,
7837 			"%s: Regulator capability was not set, actvIccLevel=%d",
7838 							__func__, icc_level);
7839 		goto out;
7840 	}
7841 
7842 	if (hba->vreg_info.vcc->max_uA)
7843 		icc_level = ufshcd_get_max_icc_level(
7844 				hba->vreg_info.vcc->max_uA,
7845 				POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7846 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7847 
7848 	if (hba->vreg_info.vccq->max_uA)
7849 		icc_level = ufshcd_get_max_icc_level(
7850 				hba->vreg_info.vccq->max_uA,
7851 				icc_level,
7852 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7853 
7854 	if (hba->vreg_info.vccq2->max_uA)
7855 		icc_level = ufshcd_get_max_icc_level(
7856 				hba->vreg_info.vccq2->max_uA,
7857 				icc_level,
7858 				&desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7859 out:
7860 	return icc_level;
7861 }
7862 
ufshcd_set_active_icc_lvl(struct ufs_hba * hba)7863 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7864 {
7865 	int ret;
7866 	u8 *desc_buf;
7867 	u32 icc_level;
7868 
7869 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7870 	if (!desc_buf)
7871 		return;
7872 
7873 	ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7874 				     desc_buf, QUERY_DESC_MAX_SIZE);
7875 	if (ret) {
7876 		dev_err(hba->dev,
7877 			"%s: Failed reading power descriptor ret = %d",
7878 			__func__, ret);
7879 		goto out;
7880 	}
7881 
7882 	icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
7883 	dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7884 
7885 	ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7886 		QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7887 
7888 	if (ret)
7889 		dev_err(hba->dev,
7890 			"%s: Failed configuring bActiveICCLevel = %d ret = %d",
7891 			__func__, icc_level, ret);
7892 
7893 out:
7894 	kfree(desc_buf);
7895 }
7896 
ufshcd_blk_pm_runtime_init(struct scsi_device * sdev)7897 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7898 {
7899 	scsi_autopm_get_device(sdev);
7900 	blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7901 	if (sdev->rpm_autosuspend)
7902 		pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7903 						 RPM_AUTOSUSPEND_DELAY_MS);
7904 	scsi_autopm_put_device(sdev);
7905 }
7906 
7907 /**
7908  * ufshcd_scsi_add_wlus - Adds required W-LUs
7909  * @hba: per-adapter instance
7910  *
7911  * UFS device specification requires the UFS devices to support 4 well known
7912  * logical units:
7913  *	"REPORT_LUNS" (address: 01h)
7914  *	"UFS Device" (address: 50h)
7915  *	"RPMB" (address: 44h)
7916  *	"BOOT" (address: 30h)
7917  * UFS device's power management needs to be controlled by "POWER CONDITION"
7918  * field of SSU (START STOP UNIT) command. But this "power condition" field
7919  * will take effect only when its sent to "UFS device" well known logical unit
7920  * hence we require the scsi_device instance to represent this logical unit in
7921  * order for the UFS host driver to send the SSU command for power management.
7922  *
7923  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7924  * Block) LU so user space process can control this LU. User space may also
7925  * want to have access to BOOT LU.
7926  *
7927  * This function adds scsi device instances for each of all well known LUs
7928  * (except "REPORT LUNS" LU).
7929  *
7930  * Return: zero on success (all required W-LUs are added successfully),
7931  * non-zero error value on failure (if failed to add any of the required W-LU).
7932  */
ufshcd_scsi_add_wlus(struct ufs_hba * hba)7933 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7934 {
7935 	int ret = 0;
7936 	struct scsi_device *sdev_boot, *sdev_rpmb;
7937 
7938 	hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
7939 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7940 	if (IS_ERR(hba->ufs_device_wlun)) {
7941 		ret = PTR_ERR(hba->ufs_device_wlun);
7942 		hba->ufs_device_wlun = NULL;
7943 		goto out;
7944 	}
7945 	scsi_device_put(hba->ufs_device_wlun);
7946 
7947 	sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7948 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7949 	if (IS_ERR(sdev_rpmb)) {
7950 		ret = PTR_ERR(sdev_rpmb);
7951 		goto remove_ufs_device_wlun;
7952 	}
7953 	ufshcd_blk_pm_runtime_init(sdev_rpmb);
7954 	scsi_device_put(sdev_rpmb);
7955 
7956 	sdev_boot = __scsi_add_device(hba->host, 0, 0,
7957 		ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7958 	if (IS_ERR(sdev_boot)) {
7959 		dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7960 	} else {
7961 		ufshcd_blk_pm_runtime_init(sdev_boot);
7962 		scsi_device_put(sdev_boot);
7963 	}
7964 	goto out;
7965 
7966 remove_ufs_device_wlun:
7967 	scsi_remove_device(hba->ufs_device_wlun);
7968 out:
7969 	return ret;
7970 }
7971 
ufshcd_wb_probe(struct ufs_hba * hba,const u8 * desc_buf)7972 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
7973 {
7974 	struct ufs_dev_info *dev_info = &hba->dev_info;
7975 	u8 lun;
7976 	u32 d_lu_wb_buf_alloc;
7977 	u32 ext_ufs_feature;
7978 
7979 	if (!ufshcd_is_wb_allowed(hba))
7980 		return;
7981 
7982 	/*
7983 	 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7984 	 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7985 	 * enabled
7986 	 */
7987 	if (!(dev_info->wspecversion >= 0x310 ||
7988 	      dev_info->wspecversion == 0x220 ||
7989 	     (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7990 		goto wb_disabled;
7991 
7992 	ext_ufs_feature = get_unaligned_be32(desc_buf +
7993 					DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7994 
7995 	if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7996 		goto wb_disabled;
7997 
7998 	/*
7999 	 * WB may be supported but not configured while provisioning. The spec
8000 	 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
8001 	 * buffer configured.
8002 	 */
8003 	dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
8004 
8005 	dev_info->b_presrv_uspc_en =
8006 		desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
8007 
8008 	if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
8009 		if (!get_unaligned_be32(desc_buf +
8010 				   DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
8011 			goto wb_disabled;
8012 	} else {
8013 		for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
8014 			d_lu_wb_buf_alloc = 0;
8015 			ufshcd_read_unit_desc_param(hba,
8016 					lun,
8017 					UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
8018 					(u8 *)&d_lu_wb_buf_alloc,
8019 					sizeof(d_lu_wb_buf_alloc));
8020 			if (d_lu_wb_buf_alloc) {
8021 				dev_info->wb_dedicated_lu = lun;
8022 				break;
8023 			}
8024 		}
8025 
8026 		if (!d_lu_wb_buf_alloc)
8027 			goto wb_disabled;
8028 	}
8029 
8030 	if (!ufshcd_is_wb_buf_lifetime_available(hba))
8031 		goto wb_disabled;
8032 
8033 	return;
8034 
8035 wb_disabled:
8036 	hba->caps &= ~UFSHCD_CAP_WB_EN;
8037 }
8038 
ufshcd_temp_notif_probe(struct ufs_hba * hba,const u8 * desc_buf)8039 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
8040 {
8041 	struct ufs_dev_info *dev_info = &hba->dev_info;
8042 	u32 ext_ufs_feature;
8043 	u8 mask = 0;
8044 
8045 	if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
8046 		return;
8047 
8048 	ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8049 
8050 	if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
8051 		mask |= MASK_EE_TOO_LOW_TEMP;
8052 
8053 	if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
8054 		mask |= MASK_EE_TOO_HIGH_TEMP;
8055 
8056 	if (mask) {
8057 		ufshcd_enable_ee(hba, mask);
8058 		ufs_hwmon_probe(hba, mask);
8059 	}
8060 }
8061 
ufshcd_ext_iid_probe(struct ufs_hba * hba,u8 * desc_buf)8062 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf)
8063 {
8064 	struct ufs_dev_info *dev_info = &hba->dev_info;
8065 	u32 ext_ufs_feature;
8066 	u32 ext_iid_en = 0;
8067 	int err;
8068 
8069 	/* Only UFS-4.0 and above may support EXT_IID */
8070 	if (dev_info->wspecversion < 0x400)
8071 		goto out;
8072 
8073 	ext_ufs_feature = get_unaligned_be32(desc_buf +
8074 				     DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8075 	if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP))
8076 		goto out;
8077 
8078 	err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8079 				      QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en);
8080 	if (err)
8081 		dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err);
8082 
8083 out:
8084 	dev_info->b_ext_iid_en = ext_iid_en;
8085 }
8086 
ufshcd_fixup_dev_quirks(struct ufs_hba * hba,const struct ufs_dev_quirk * fixups)8087 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
8088 			     const struct ufs_dev_quirk *fixups)
8089 {
8090 	const struct ufs_dev_quirk *f;
8091 	struct ufs_dev_info *dev_info = &hba->dev_info;
8092 
8093 	if (!fixups)
8094 		return;
8095 
8096 	for (f = fixups; f->quirk; f++) {
8097 		if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
8098 		     f->wmanufacturerid == UFS_ANY_VENDOR) &&
8099 		     ((dev_info->model &&
8100 		       STR_PRFX_EQUAL(f->model, dev_info->model)) ||
8101 		      !strcmp(f->model, UFS_ANY_MODEL)))
8102 			hba->dev_quirks |= f->quirk;
8103 	}
8104 }
8105 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
8106 
ufs_fixup_device_setup(struct ufs_hba * hba)8107 static void ufs_fixup_device_setup(struct ufs_hba *hba)
8108 {
8109 	/* fix by general quirk table */
8110 	ufshcd_fixup_dev_quirks(hba, ufs_fixups);
8111 
8112 	/* allow vendors to fix quirks */
8113 	ufshcd_vops_fixup_dev_quirks(hba);
8114 }
8115 
ufs_get_device_desc(struct ufs_hba * hba)8116 static int ufs_get_device_desc(struct ufs_hba *hba)
8117 {
8118 	int err;
8119 	u8 model_index;
8120 	u8 *desc_buf;
8121 	struct ufs_dev_info *dev_info = &hba->dev_info;
8122 
8123 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8124 	if (!desc_buf) {
8125 		err = -ENOMEM;
8126 		goto out;
8127 	}
8128 
8129 	err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
8130 				     QUERY_DESC_MAX_SIZE);
8131 	if (err) {
8132 		dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
8133 			__func__, err);
8134 		goto out;
8135 	}
8136 
8137 	/*
8138 	 * getting vendor (manufacturerID) and Bank Index in big endian
8139 	 * format
8140 	 */
8141 	dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
8142 				     desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8143 
8144 	/* getting Specification Version in big endian format */
8145 	dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8146 				      desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8147 	dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8148 
8149 	model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8150 
8151 	err = ufshcd_read_string_desc(hba, model_index,
8152 				      &dev_info->model, SD_ASCII_STD);
8153 	if (err < 0) {
8154 		dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8155 			__func__, err);
8156 		goto out;
8157 	}
8158 
8159 	hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8160 		desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8161 
8162 	ufs_fixup_device_setup(hba);
8163 
8164 	ufshcd_wb_probe(hba, desc_buf);
8165 
8166 	ufshcd_temp_notif_probe(hba, desc_buf);
8167 
8168 	if (hba->ext_iid_sup)
8169 		ufshcd_ext_iid_probe(hba, desc_buf);
8170 
8171 	/*
8172 	 * ufshcd_read_string_desc returns size of the string
8173 	 * reset the error value
8174 	 */
8175 	err = 0;
8176 
8177 out:
8178 	kfree(desc_buf);
8179 	return err;
8180 }
8181 
ufs_put_device_desc(struct ufs_hba * hba)8182 static void ufs_put_device_desc(struct ufs_hba *hba)
8183 {
8184 	struct ufs_dev_info *dev_info = &hba->dev_info;
8185 
8186 	kfree(dev_info->model);
8187 	dev_info->model = NULL;
8188 }
8189 
8190 /**
8191  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
8192  * @hba: per-adapter instance
8193  *
8194  * PA_TActivate parameter can be tuned manually if UniPro version is less than
8195  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
8196  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
8197  * the hibern8 exit latency.
8198  *
8199  * Return: zero on success, non-zero error value on failure.
8200  */
ufshcd_tune_pa_tactivate(struct ufs_hba * hba)8201 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
8202 {
8203 	int ret = 0;
8204 	u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
8205 
8206 	ret = ufshcd_dme_peer_get(hba,
8207 				  UIC_ARG_MIB_SEL(
8208 					RX_MIN_ACTIVATETIME_CAPABILITY,
8209 					UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8210 				  &peer_rx_min_activatetime);
8211 	if (ret)
8212 		goto out;
8213 
8214 	/* make sure proper unit conversion is applied */
8215 	tuned_pa_tactivate =
8216 		((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
8217 		 / PA_TACTIVATE_TIME_UNIT_US);
8218 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8219 			     tuned_pa_tactivate);
8220 
8221 out:
8222 	return ret;
8223 }
8224 
8225 /**
8226  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
8227  * @hba: per-adapter instance
8228  *
8229  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
8230  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
8231  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
8232  * This optimal value can help reduce the hibern8 exit latency.
8233  *
8234  * Return: zero on success, non-zero error value on failure.
8235  */
ufshcd_tune_pa_hibern8time(struct ufs_hba * hba)8236 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
8237 {
8238 	int ret = 0;
8239 	u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
8240 	u32 max_hibern8_time, tuned_pa_hibern8time;
8241 
8242 	ret = ufshcd_dme_get(hba,
8243 			     UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
8244 					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
8245 				  &local_tx_hibern8_time_cap);
8246 	if (ret)
8247 		goto out;
8248 
8249 	ret = ufshcd_dme_peer_get(hba,
8250 				  UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
8251 					UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8252 				  &peer_rx_hibern8_time_cap);
8253 	if (ret)
8254 		goto out;
8255 
8256 	max_hibern8_time = max(local_tx_hibern8_time_cap,
8257 			       peer_rx_hibern8_time_cap);
8258 	/* make sure proper unit conversion is applied */
8259 	tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
8260 				/ PA_HIBERN8_TIME_UNIT_US);
8261 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
8262 			     tuned_pa_hibern8time);
8263 out:
8264 	return ret;
8265 }
8266 
8267 /**
8268  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8269  * less than device PA_TACTIVATE time.
8270  * @hba: per-adapter instance
8271  *
8272  * Some UFS devices require host PA_TACTIVATE to be lower than device
8273  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8274  * for such devices.
8275  *
8276  * Return: zero on success, non-zero error value on failure.
8277  */
ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba * hba)8278 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8279 {
8280 	int ret = 0;
8281 	u32 granularity, peer_granularity;
8282 	u32 pa_tactivate, peer_pa_tactivate;
8283 	u32 pa_tactivate_us, peer_pa_tactivate_us;
8284 	static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8285 
8286 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8287 				  &granularity);
8288 	if (ret)
8289 		goto out;
8290 
8291 	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8292 				  &peer_granularity);
8293 	if (ret)
8294 		goto out;
8295 
8296 	if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8297 	    (granularity > PA_GRANULARITY_MAX_VAL)) {
8298 		dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8299 			__func__, granularity);
8300 		return -EINVAL;
8301 	}
8302 
8303 	if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8304 	    (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8305 		dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8306 			__func__, peer_granularity);
8307 		return -EINVAL;
8308 	}
8309 
8310 	ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8311 	if (ret)
8312 		goto out;
8313 
8314 	ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8315 				  &peer_pa_tactivate);
8316 	if (ret)
8317 		goto out;
8318 
8319 	pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8320 	peer_pa_tactivate_us = peer_pa_tactivate *
8321 			     gran_to_us_table[peer_granularity - 1];
8322 
8323 	if (pa_tactivate_us >= peer_pa_tactivate_us) {
8324 		u32 new_peer_pa_tactivate;
8325 
8326 		new_peer_pa_tactivate = pa_tactivate_us /
8327 				      gran_to_us_table[peer_granularity - 1];
8328 		new_peer_pa_tactivate++;
8329 		ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8330 					  new_peer_pa_tactivate);
8331 	}
8332 
8333 out:
8334 	return ret;
8335 }
8336 
ufshcd_tune_unipro_params(struct ufs_hba * hba)8337 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8338 {
8339 	if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
8340 		ufshcd_tune_pa_tactivate(hba);
8341 		ufshcd_tune_pa_hibern8time(hba);
8342 	}
8343 
8344 	ufshcd_vops_apply_dev_quirks(hba);
8345 
8346 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8347 		/* set 1ms timeout for PA_TACTIVATE */
8348 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
8349 
8350 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8351 		ufshcd_quirk_tune_host_pa_tactivate(hba);
8352 }
8353 
ufshcd_clear_dbg_ufs_stats(struct ufs_hba * hba)8354 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8355 {
8356 	hba->ufs_stats.hibern8_exit_cnt = 0;
8357 	hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
8358 	hba->req_abort_count = 0;
8359 }
8360 
ufshcd_device_geo_params_init(struct ufs_hba * hba)8361 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8362 {
8363 	int err;
8364 	u8 *desc_buf;
8365 
8366 	desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8367 	if (!desc_buf) {
8368 		err = -ENOMEM;
8369 		goto out;
8370 	}
8371 
8372 	err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
8373 				     desc_buf, QUERY_DESC_MAX_SIZE);
8374 	if (err) {
8375 		dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8376 				__func__, err);
8377 		goto out;
8378 	}
8379 
8380 	if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8381 		hba->dev_info.max_lu_supported = 32;
8382 	else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8383 		hba->dev_info.max_lu_supported = 8;
8384 
8385 out:
8386 	kfree(desc_buf);
8387 	return err;
8388 }
8389 
8390 struct ufs_ref_clk {
8391 	unsigned long freq_hz;
8392 	enum ufs_ref_clk_freq val;
8393 };
8394 
8395 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8396 	{19200000, REF_CLK_FREQ_19_2_MHZ},
8397 	{26000000, REF_CLK_FREQ_26_MHZ},
8398 	{38400000, REF_CLK_FREQ_38_4_MHZ},
8399 	{52000000, REF_CLK_FREQ_52_MHZ},
8400 	{0, REF_CLK_FREQ_INVAL},
8401 };
8402 
8403 static enum ufs_ref_clk_freq
ufs_get_bref_clk_from_hz(unsigned long freq)8404 ufs_get_bref_clk_from_hz(unsigned long freq)
8405 {
8406 	int i;
8407 
8408 	for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8409 		if (ufs_ref_clk_freqs[i].freq_hz == freq)
8410 			return ufs_ref_clk_freqs[i].val;
8411 
8412 	return REF_CLK_FREQ_INVAL;
8413 }
8414 
ufshcd_parse_dev_ref_clk_freq(struct ufs_hba * hba,struct clk * refclk)8415 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8416 {
8417 	unsigned long freq;
8418 
8419 	freq = clk_get_rate(refclk);
8420 
8421 	hba->dev_ref_clk_freq =
8422 		ufs_get_bref_clk_from_hz(freq);
8423 
8424 	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8425 		dev_err(hba->dev,
8426 		"invalid ref_clk setting = %ld\n", freq);
8427 }
8428 
ufshcd_set_dev_ref_clk(struct ufs_hba * hba)8429 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8430 {
8431 	int err;
8432 	u32 ref_clk;
8433 	u32 freq = hba->dev_ref_clk_freq;
8434 
8435 	err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8436 			QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8437 
8438 	if (err) {
8439 		dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8440 			err);
8441 		goto out;
8442 	}
8443 
8444 	if (ref_clk == freq)
8445 		goto out; /* nothing to update */
8446 
8447 	err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8448 			QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8449 
8450 	if (err) {
8451 		dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8452 			ufs_ref_clk_freqs[freq].freq_hz);
8453 		goto out;
8454 	}
8455 
8456 	dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8457 			ufs_ref_clk_freqs[freq].freq_hz);
8458 
8459 out:
8460 	return err;
8461 }
8462 
ufshcd_device_params_init(struct ufs_hba * hba)8463 static int ufshcd_device_params_init(struct ufs_hba *hba)
8464 {
8465 	bool flag;
8466 	int ret;
8467 
8468 	/* Init UFS geometry descriptor related parameters */
8469 	ret = ufshcd_device_geo_params_init(hba);
8470 	if (ret)
8471 		goto out;
8472 
8473 	/* Check and apply UFS device quirks */
8474 	ret = ufs_get_device_desc(hba);
8475 	if (ret) {
8476 		dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8477 			__func__, ret);
8478 		goto out;
8479 	}
8480 
8481 	ufshcd_get_ref_clk_gating_wait(hba);
8482 
8483 	if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8484 			QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8485 		hba->dev_info.f_power_on_wp_en = flag;
8486 
8487 	/* Probe maximum power mode co-supported by both UFS host and device */
8488 	if (ufshcd_get_max_pwr_mode(hba))
8489 		dev_err(hba->dev,
8490 			"%s: Failed getting max supported power mode\n",
8491 			__func__);
8492 out:
8493 	return ret;
8494 }
8495 
ufshcd_set_timestamp_attr(struct ufs_hba * hba)8496 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
8497 {
8498 	int err;
8499 	struct ufs_query_req *request = NULL;
8500 	struct ufs_query_res *response = NULL;
8501 	struct ufs_dev_info *dev_info = &hba->dev_info;
8502 	struct utp_upiu_query_v4_0 *upiu_data;
8503 
8504 	if (dev_info->wspecversion < 0x400)
8505 		return;
8506 
8507 	ufshcd_hold(hba);
8508 
8509 	mutex_lock(&hba->dev_cmd.lock);
8510 
8511 	ufshcd_init_query(hba, &request, &response,
8512 			  UPIU_QUERY_OPCODE_WRITE_ATTR,
8513 			  QUERY_ATTR_IDN_TIMESTAMP, 0, 0);
8514 
8515 	request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
8516 
8517 	upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req;
8518 
8519 	put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
8520 
8521 	err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
8522 
8523 	if (err)
8524 		dev_err(hba->dev, "%s: failed to set timestamp %d\n",
8525 			__func__, err);
8526 
8527 	mutex_unlock(&hba->dev_cmd.lock);
8528 	ufshcd_release(hba);
8529 }
8530 
8531 /**
8532  * ufshcd_add_lus - probe and add UFS logical units
8533  * @hba: per-adapter instance
8534  *
8535  * Return: 0 upon success; < 0 upon failure.
8536  */
ufshcd_add_lus(struct ufs_hba * hba)8537 static int ufshcd_add_lus(struct ufs_hba *hba)
8538 {
8539 	int ret;
8540 
8541 	/* Add required well known logical units to scsi mid layer */
8542 	ret = ufshcd_scsi_add_wlus(hba);
8543 	if (ret)
8544 		goto out;
8545 
8546 	/* Initialize devfreq after UFS device is detected */
8547 	if (ufshcd_is_clkscaling_supported(hba)) {
8548 		memcpy(&hba->clk_scaling.saved_pwr_info,
8549 			&hba->pwr_info,
8550 			sizeof(struct ufs_pa_layer_attr));
8551 		hba->clk_scaling.is_allowed = true;
8552 
8553 		ret = ufshcd_devfreq_init(hba);
8554 		if (ret)
8555 			goto out;
8556 
8557 		hba->clk_scaling.is_enabled = true;
8558 		ufshcd_init_clk_scaling_sysfs(hba);
8559 	}
8560 
8561 	ufs_bsg_probe(hba);
8562 	scsi_scan_host(hba->host);
8563 
8564 out:
8565 	return ret;
8566 }
8567 
8568 /* SDB - Single Doorbell */
ufshcd_release_sdb_queue(struct ufs_hba * hba,int nutrs)8569 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
8570 {
8571 	size_t ucdl_size, utrdl_size;
8572 
8573 	ucdl_size = ufshcd_get_ucd_size(hba) * nutrs;
8574 	dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr,
8575 			   hba->ucdl_dma_addr);
8576 
8577 	utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
8578 	dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr,
8579 			   hba->utrdl_dma_addr);
8580 
8581 	devm_kfree(hba->dev, hba->lrb);
8582 }
8583 
ufshcd_alloc_mcq(struct ufs_hba * hba)8584 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
8585 {
8586 	int ret;
8587 	int old_nutrs = hba->nutrs;
8588 
8589 	ret = ufshcd_mcq_decide_queue_depth(hba);
8590 	if (ret < 0)
8591 		return ret;
8592 
8593 	hba->nutrs = ret;
8594 	ret = ufshcd_mcq_init(hba);
8595 	if (ret)
8596 		goto err;
8597 
8598 	/*
8599 	 * Previously allocated memory for nutrs may not be enough in MCQ mode.
8600 	 * Number of supported tags in MCQ mode may be larger than SDB mode.
8601 	 */
8602 	if (hba->nutrs != old_nutrs) {
8603 		ufshcd_release_sdb_queue(hba, old_nutrs);
8604 		ret = ufshcd_memory_alloc(hba);
8605 		if (ret)
8606 			goto err;
8607 		ufshcd_host_memory_configure(hba);
8608 	}
8609 
8610 	ret = ufshcd_mcq_memory_alloc(hba);
8611 	if (ret)
8612 		goto err;
8613 
8614 	return 0;
8615 err:
8616 	hba->nutrs = old_nutrs;
8617 	return ret;
8618 }
8619 
ufshcd_config_mcq(struct ufs_hba * hba)8620 static void ufshcd_config_mcq(struct ufs_hba *hba)
8621 {
8622 	int ret;
8623 	u32 intrs;
8624 
8625 	ret = ufshcd_mcq_vops_config_esi(hba);
8626 	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8627 
8628 	intrs = UFSHCD_ENABLE_MCQ_INTRS;
8629 	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
8630 		intrs &= ~MCQ_CQ_EVENT_STATUS;
8631 	ufshcd_enable_intr(hba, intrs);
8632 	ufshcd_mcq_make_queues_operational(hba);
8633 	ufshcd_mcq_config_mac(hba, hba->nutrs);
8634 
8635 	hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
8636 	hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
8637 
8638 	/* Select MCQ mode */
8639 	ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
8640 		      REG_UFS_MEM_CFG);
8641 	hba->mcq_enabled = true;
8642 
8643 	dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
8644 		 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
8645 		 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
8646 		 hba->nutrs);
8647 }
8648 
ufshcd_device_init(struct ufs_hba * hba,bool init_dev_params)8649 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
8650 {
8651 	int ret;
8652 	struct Scsi_Host *host = hba->host;
8653 
8654 	hba->ufshcd_state = UFSHCD_STATE_RESET;
8655 
8656 	ret = ufshcd_link_startup(hba);
8657 	if (ret)
8658 		return ret;
8659 
8660 	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8661 		return ret;
8662 
8663 	/* Debug counters initialization */
8664 	ufshcd_clear_dbg_ufs_stats(hba);
8665 
8666 	/* UniPro link is active now */
8667 	ufshcd_set_link_active(hba);
8668 
8669 	/* Reconfigure MCQ upon reset */
8670 	if (is_mcq_enabled(hba) && !init_dev_params)
8671 		ufshcd_config_mcq(hba);
8672 
8673 	/* Verify device initialization by sending NOP OUT UPIU */
8674 	ret = ufshcd_verify_dev_init(hba);
8675 	if (ret)
8676 		return ret;
8677 
8678 	/* Initiate UFS initialization, and waiting until completion */
8679 	ret = ufshcd_complete_dev_init(hba);
8680 	if (ret)
8681 		return ret;
8682 
8683 	/*
8684 	 * Initialize UFS device parameters used by driver, these
8685 	 * parameters are associated with UFS descriptors.
8686 	 */
8687 	if (init_dev_params) {
8688 		ret = ufshcd_device_params_init(hba);
8689 		if (ret)
8690 			return ret;
8691 		if (is_mcq_supported(hba) && !hba->scsi_host_added) {
8692 			ret = ufshcd_alloc_mcq(hba);
8693 			if (!ret) {
8694 				ufshcd_config_mcq(hba);
8695 			} else {
8696 				/* Continue with SDB mode */
8697 				use_mcq_mode = false;
8698 				dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
8699 					 ret);
8700 			}
8701 			ret = scsi_add_host(host, hba->dev);
8702 			if (ret) {
8703 				dev_err(hba->dev, "scsi_add_host failed\n");
8704 				return ret;
8705 			}
8706 			hba->scsi_host_added = true;
8707 		} else if (is_mcq_supported(hba)) {
8708 			/* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */
8709 			ufshcd_config_mcq(hba);
8710 		}
8711 	}
8712 
8713 	ufshcd_tune_unipro_params(hba);
8714 
8715 	/* UFS device is also active now */
8716 	ufshcd_set_ufs_dev_active(hba);
8717 	ufshcd_force_reset_auto_bkops(hba);
8718 
8719 	ufshcd_set_timestamp_attr(hba);
8720 
8721 	/* Gear up to HS gear if supported */
8722 	if (hba->max_pwr_info.is_valid) {
8723 		/*
8724 		 * Set the right value to bRefClkFreq before attempting to
8725 		 * switch to HS gears.
8726 		 */
8727 		if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8728 			ufshcd_set_dev_ref_clk(hba);
8729 		ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8730 		if (ret) {
8731 			dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8732 					__func__, ret);
8733 			return ret;
8734 		}
8735 	}
8736 
8737 	return 0;
8738 }
8739 
8740 /**
8741  * ufshcd_probe_hba - probe hba to detect device and initialize it
8742  * @hba: per-adapter instance
8743  * @init_dev_params: whether or not to call ufshcd_device_params_init().
8744  *
8745  * Execute link-startup and verify device initialization
8746  *
8747  * Return: 0 upon success; < 0 upon failure.
8748  */
ufshcd_probe_hba(struct ufs_hba * hba,bool init_dev_params)8749 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8750 {
8751 	ktime_t start = ktime_get();
8752 	unsigned long flags;
8753 	int ret;
8754 
8755 	ret = ufshcd_device_init(hba, init_dev_params);
8756 	if (ret)
8757 		goto out;
8758 
8759 	if (!hba->pm_op_in_progress &&
8760 	    (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) {
8761 		/* Reset the device and controller before doing reinit */
8762 		ufshcd_device_reset(hba);
8763 		ufs_put_device_desc(hba);
8764 		ufshcd_hba_stop(hba);
8765 		ufshcd_vops_reinit_notify(hba);
8766 		ret = ufshcd_hba_enable(hba);
8767 		if (ret) {
8768 			dev_err(hba->dev, "Host controller enable failed\n");
8769 			ufshcd_print_evt_hist(hba);
8770 			ufshcd_print_host_state(hba);
8771 			goto out;
8772 		}
8773 
8774 		/* Reinit the device */
8775 		ret = ufshcd_device_init(hba, init_dev_params);
8776 		if (ret)
8777 			goto out;
8778 	}
8779 
8780 	ufshcd_print_pwr_info(hba);
8781 
8782 	/*
8783 	 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8784 	 * and for removable UFS card as well, hence always set the parameter.
8785 	 * Note: Error handler may issue the device reset hence resetting
8786 	 * bActiveICCLevel as well so it is always safe to set this here.
8787 	 */
8788 	ufshcd_set_active_icc_lvl(hba);
8789 
8790 	/* Enable UFS Write Booster if supported */
8791 	ufshcd_configure_wb(hba);
8792 
8793 	if (hba->ee_usr_mask)
8794 		ufshcd_write_ee_control(hba);
8795 	/* Enable Auto-Hibernate if configured */
8796 	ufshcd_auto_hibern8_enable(hba);
8797 
8798 out:
8799 	spin_lock_irqsave(hba->host->host_lock, flags);
8800 	if (ret)
8801 		hba->ufshcd_state = UFSHCD_STATE_ERROR;
8802 	else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8803 		hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8804 	spin_unlock_irqrestore(hba->host->host_lock, flags);
8805 
8806 	trace_ufshcd_init(dev_name(hba->dev), ret,
8807 		ktime_to_us(ktime_sub(ktime_get(), start)),
8808 		hba->curr_dev_pwr_mode, hba->uic_link_state);
8809 	return ret;
8810 }
8811 
8812 /**
8813  * ufshcd_async_scan - asynchronous execution for probing hba
8814  * @data: data pointer to pass to this function
8815  * @cookie: cookie data
8816  */
ufshcd_async_scan(void * data,async_cookie_t cookie)8817 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8818 {
8819 	struct ufs_hba *hba = (struct ufs_hba *)data;
8820 	int ret;
8821 
8822 	down(&hba->host_sem);
8823 	/* Initialize hba, detect and initialize UFS device */
8824 	ret = ufshcd_probe_hba(hba, true);
8825 	up(&hba->host_sem);
8826 	if (ret)
8827 		goto out;
8828 
8829 	/* Probe and add UFS logical units  */
8830 	ret = ufshcd_add_lus(hba);
8831 
8832 out:
8833 	pm_runtime_put_sync(hba->dev);
8834 
8835 	if (ret)
8836 		dev_err(hba->dev, "%s failed: %d\n", __func__, ret);
8837 }
8838 
ufshcd_eh_timed_out(struct scsi_cmnd * scmd)8839 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
8840 {
8841 	struct ufs_hba *hba = shost_priv(scmd->device->host);
8842 
8843 	if (!hba->system_suspending) {
8844 		/* Activate the error handler in the SCSI core. */
8845 		return SCSI_EH_NOT_HANDLED;
8846 	}
8847 
8848 	/*
8849 	 * If we get here we know that no TMFs are outstanding and also that
8850 	 * the only pending command is a START STOP UNIT command. Handle the
8851 	 * timeout of that command directly to prevent a deadlock between
8852 	 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
8853 	 */
8854 	ufshcd_link_recovery(hba);
8855 	dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
8856 		 __func__, hba->outstanding_tasks);
8857 
8858 	return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
8859 }
8860 
8861 static const struct attribute_group *ufshcd_driver_groups[] = {
8862 	&ufs_sysfs_unit_descriptor_group,
8863 	&ufs_sysfs_lun_attributes_group,
8864 	NULL,
8865 };
8866 
8867 static struct ufs_hba_variant_params ufs_hba_vps = {
8868 	.hba_enable_delay_us		= 1000,
8869 	.wb_flush_threshold		= UFS_WB_BUF_REMAIN_PERCENT(40),
8870 	.devfreq_profile.polling_ms	= 100,
8871 	.devfreq_profile.target		= ufshcd_devfreq_target,
8872 	.devfreq_profile.get_dev_status	= ufshcd_devfreq_get_dev_status,
8873 	.ondemand_data.upthreshold	= 70,
8874 	.ondemand_data.downdifferential	= 5,
8875 };
8876 
8877 static const struct scsi_host_template ufshcd_driver_template = {
8878 	.module			= THIS_MODULE,
8879 	.name			= UFSHCD,
8880 	.proc_name		= UFSHCD,
8881 	.map_queues		= ufshcd_map_queues,
8882 	.queuecommand		= ufshcd_queuecommand,
8883 	.mq_poll		= ufshcd_poll,
8884 	.slave_alloc		= ufshcd_slave_alloc,
8885 	.slave_configure	= ufshcd_slave_configure,
8886 	.slave_destroy		= ufshcd_slave_destroy,
8887 	.change_queue_depth	= ufshcd_change_queue_depth,
8888 	.eh_abort_handler	= ufshcd_abort,
8889 	.eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8890 	.eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
8891 	.eh_timed_out		= ufshcd_eh_timed_out,
8892 	.this_id		= -1,
8893 	.sg_tablesize		= SG_ALL,
8894 	.cmd_per_lun		= UFSHCD_CMD_PER_LUN,
8895 	.can_queue		= UFSHCD_CAN_QUEUE,
8896 	.max_segment_size	= PRDT_DATA_BYTE_COUNT_MAX,
8897 	.max_sectors		= SZ_1M / SECTOR_SIZE,
8898 	.max_host_blocked	= 1,
8899 	.track_queue_depth	= 1,
8900 	.skip_settle_delay	= 1,
8901 	.sdev_groups		= ufshcd_driver_groups,
8902 	.rpm_autosuspend_delay	= RPM_AUTOSUSPEND_DELAY_MS,
8903 };
8904 
ufshcd_config_vreg_load(struct device * dev,struct ufs_vreg * vreg,int ua)8905 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8906 				   int ua)
8907 {
8908 	int ret;
8909 
8910 	if (!vreg)
8911 		return 0;
8912 
8913 	/*
8914 	 * "set_load" operation shall be required on those regulators
8915 	 * which specifically configured current limitation. Otherwise
8916 	 * zero max_uA may cause unexpected behavior when regulator is
8917 	 * enabled or set as high power mode.
8918 	 */
8919 	if (!vreg->max_uA)
8920 		return 0;
8921 
8922 	ret = regulator_set_load(vreg->reg, ua);
8923 	if (ret < 0) {
8924 		dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8925 				__func__, vreg->name, ua, ret);
8926 	}
8927 
8928 	return ret;
8929 }
8930 
ufshcd_config_vreg_lpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8931 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8932 					 struct ufs_vreg *vreg)
8933 {
8934 	return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8935 }
8936 
ufshcd_config_vreg_hpm(struct ufs_hba * hba,struct ufs_vreg * vreg)8937 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8938 					 struct ufs_vreg *vreg)
8939 {
8940 	if (!vreg)
8941 		return 0;
8942 
8943 	return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8944 }
8945 
ufshcd_config_vreg(struct device * dev,struct ufs_vreg * vreg,bool on)8946 static int ufshcd_config_vreg(struct device *dev,
8947 		struct ufs_vreg *vreg, bool on)
8948 {
8949 	if (regulator_count_voltages(vreg->reg) <= 0)
8950 		return 0;
8951 
8952 	return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
8953 }
8954 
ufshcd_enable_vreg(struct device * dev,struct ufs_vreg * vreg)8955 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8956 {
8957 	int ret = 0;
8958 
8959 	if (!vreg || vreg->enabled)
8960 		goto out;
8961 
8962 	ret = ufshcd_config_vreg(dev, vreg, true);
8963 	if (!ret)
8964 		ret = regulator_enable(vreg->reg);
8965 
8966 	if (!ret)
8967 		vreg->enabled = true;
8968 	else
8969 		dev_err(dev, "%s: %s enable failed, err=%d\n",
8970 				__func__, vreg->name, ret);
8971 out:
8972 	return ret;
8973 }
8974 
ufshcd_disable_vreg(struct device * dev,struct ufs_vreg * vreg)8975 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8976 {
8977 	int ret = 0;
8978 
8979 	if (!vreg || !vreg->enabled || vreg->always_on)
8980 		goto out;
8981 
8982 	ret = regulator_disable(vreg->reg);
8983 
8984 	if (!ret) {
8985 		/* ignore errors on applying disable config */
8986 		ufshcd_config_vreg(dev, vreg, false);
8987 		vreg->enabled = false;
8988 	} else {
8989 		dev_err(dev, "%s: %s disable failed, err=%d\n",
8990 				__func__, vreg->name, ret);
8991 	}
8992 out:
8993 	return ret;
8994 }
8995 
ufshcd_setup_vreg(struct ufs_hba * hba,bool on)8996 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8997 {
8998 	int ret = 0;
8999 	struct device *dev = hba->dev;
9000 	struct ufs_vreg_info *info = &hba->vreg_info;
9001 
9002 	ret = ufshcd_toggle_vreg(dev, info->vcc, on);
9003 	if (ret)
9004 		goto out;
9005 
9006 	ret = ufshcd_toggle_vreg(dev, info->vccq, on);
9007 	if (ret)
9008 		goto out;
9009 
9010 	ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
9011 
9012 out:
9013 	if (ret) {
9014 		ufshcd_toggle_vreg(dev, info->vccq2, false);
9015 		ufshcd_toggle_vreg(dev, info->vccq, false);
9016 		ufshcd_toggle_vreg(dev, info->vcc, false);
9017 	}
9018 	return ret;
9019 }
9020 
ufshcd_setup_hba_vreg(struct ufs_hba * hba,bool on)9021 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
9022 {
9023 	struct ufs_vreg_info *info = &hba->vreg_info;
9024 
9025 	return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
9026 }
9027 
ufshcd_get_vreg(struct device * dev,struct ufs_vreg * vreg)9028 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
9029 {
9030 	int ret = 0;
9031 
9032 	if (!vreg)
9033 		goto out;
9034 
9035 	vreg->reg = devm_regulator_get(dev, vreg->name);
9036 	if (IS_ERR(vreg->reg)) {
9037 		ret = PTR_ERR(vreg->reg);
9038 		dev_err(dev, "%s: %s get failed, err=%d\n",
9039 				__func__, vreg->name, ret);
9040 	}
9041 out:
9042 	return ret;
9043 }
9044 EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
9045 
ufshcd_init_vreg(struct ufs_hba * hba)9046 static int ufshcd_init_vreg(struct ufs_hba *hba)
9047 {
9048 	int ret = 0;
9049 	struct device *dev = hba->dev;
9050 	struct ufs_vreg_info *info = &hba->vreg_info;
9051 
9052 	ret = ufshcd_get_vreg(dev, info->vcc);
9053 	if (ret)
9054 		goto out;
9055 
9056 	ret = ufshcd_get_vreg(dev, info->vccq);
9057 	if (!ret)
9058 		ret = ufshcd_get_vreg(dev, info->vccq2);
9059 out:
9060 	return ret;
9061 }
9062 
ufshcd_init_hba_vreg(struct ufs_hba * hba)9063 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
9064 {
9065 	struct ufs_vreg_info *info = &hba->vreg_info;
9066 
9067 	return ufshcd_get_vreg(hba->dev, info->vdd_hba);
9068 }
9069 
ufshcd_setup_clocks(struct ufs_hba * hba,bool on)9070 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
9071 {
9072 	int ret = 0;
9073 	struct ufs_clk_info *clki;
9074 	struct list_head *head = &hba->clk_list_head;
9075 	unsigned long flags;
9076 	ktime_t start = ktime_get();
9077 	bool clk_state_changed = false;
9078 
9079 	if (list_empty(head))
9080 		goto out;
9081 
9082 	ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
9083 	if (ret)
9084 		return ret;
9085 
9086 	list_for_each_entry(clki, head, list) {
9087 		if (!IS_ERR_OR_NULL(clki->clk)) {
9088 			/*
9089 			 * Don't disable clocks which are needed
9090 			 * to keep the link active.
9091 			 */
9092 			if (ufshcd_is_link_active(hba) &&
9093 			    clki->keep_link_active)
9094 				continue;
9095 
9096 			clk_state_changed = on ^ clki->enabled;
9097 			if (on && !clki->enabled) {
9098 				ret = clk_prepare_enable(clki->clk);
9099 				if (ret) {
9100 					dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
9101 						__func__, clki->name, ret);
9102 					goto out;
9103 				}
9104 			} else if (!on && clki->enabled) {
9105 				clk_disable_unprepare(clki->clk);
9106 			}
9107 			clki->enabled = on;
9108 			dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
9109 					clki->name, on ? "en" : "dis");
9110 		}
9111 	}
9112 
9113 	ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
9114 	if (ret)
9115 		return ret;
9116 
9117 out:
9118 	if (ret) {
9119 		list_for_each_entry(clki, head, list) {
9120 			if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
9121 				clk_disable_unprepare(clki->clk);
9122 		}
9123 	} else if (!ret && on) {
9124 		spin_lock_irqsave(hba->host->host_lock, flags);
9125 		hba->clk_gating.state = CLKS_ON;
9126 		trace_ufshcd_clk_gating(dev_name(hba->dev),
9127 					hba->clk_gating.state);
9128 		spin_unlock_irqrestore(hba->host->host_lock, flags);
9129 	}
9130 
9131 	if (clk_state_changed)
9132 		trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
9133 			(on ? "on" : "off"),
9134 			ktime_to_us(ktime_sub(ktime_get(), start)), ret);
9135 	return ret;
9136 }
9137 
ufshcd_parse_ref_clk_property(struct ufs_hba * hba)9138 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
9139 {
9140 	u32 freq;
9141 	int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
9142 
9143 	if (ret) {
9144 		dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
9145 		return REF_CLK_FREQ_INVAL;
9146 	}
9147 
9148 	return ufs_get_bref_clk_from_hz(freq);
9149 }
9150 
ufshcd_init_clocks(struct ufs_hba * hba)9151 static int ufshcd_init_clocks(struct ufs_hba *hba)
9152 {
9153 	int ret = 0;
9154 	struct ufs_clk_info *clki;
9155 	struct device *dev = hba->dev;
9156 	struct list_head *head = &hba->clk_list_head;
9157 
9158 	if (list_empty(head))
9159 		goto out;
9160 
9161 	list_for_each_entry(clki, head, list) {
9162 		if (!clki->name)
9163 			continue;
9164 
9165 		clki->clk = devm_clk_get(dev, clki->name);
9166 		if (IS_ERR(clki->clk)) {
9167 			ret = PTR_ERR(clki->clk);
9168 			dev_err(dev, "%s: %s clk get failed, %d\n",
9169 					__func__, clki->name, ret);
9170 			goto out;
9171 		}
9172 
9173 		/*
9174 		 * Parse device ref clk freq as per device tree "ref_clk".
9175 		 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9176 		 * in ufshcd_alloc_host().
9177 		 */
9178 		if (!strcmp(clki->name, "ref_clk"))
9179 			ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
9180 
9181 		if (clki->max_freq) {
9182 			ret = clk_set_rate(clki->clk, clki->max_freq);
9183 			if (ret) {
9184 				dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9185 					__func__, clki->name,
9186 					clki->max_freq, ret);
9187 				goto out;
9188 			}
9189 			clki->curr_freq = clki->max_freq;
9190 		}
9191 		dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9192 				clki->name, clk_get_rate(clki->clk));
9193 	}
9194 out:
9195 	return ret;
9196 }
9197 
ufshcd_variant_hba_init(struct ufs_hba * hba)9198 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9199 {
9200 	int err = 0;
9201 
9202 	if (!hba->vops)
9203 		goto out;
9204 
9205 	err = ufshcd_vops_init(hba);
9206 	if (err)
9207 		dev_err_probe(hba->dev, err,
9208 			      "%s: variant %s init failed with err %d\n",
9209 			      __func__, ufshcd_get_var_name(hba), err);
9210 out:
9211 	return err;
9212 }
9213 
ufshcd_variant_hba_exit(struct ufs_hba * hba)9214 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9215 {
9216 	if (!hba->vops)
9217 		return;
9218 
9219 	ufshcd_vops_exit(hba);
9220 }
9221 
ufshcd_hba_init(struct ufs_hba * hba)9222 static int ufshcd_hba_init(struct ufs_hba *hba)
9223 {
9224 	int err;
9225 
9226 	/*
9227 	 * Handle host controller power separately from the UFS device power
9228 	 * rails as it will help controlling the UFS host controller power
9229 	 * collapse easily which is different than UFS device power collapse.
9230 	 * Also, enable the host controller power before we go ahead with rest
9231 	 * of the initialization here.
9232 	 */
9233 	err = ufshcd_init_hba_vreg(hba);
9234 	if (err)
9235 		goto out;
9236 
9237 	err = ufshcd_setup_hba_vreg(hba, true);
9238 	if (err)
9239 		goto out;
9240 
9241 	err = ufshcd_init_clocks(hba);
9242 	if (err)
9243 		goto out_disable_hba_vreg;
9244 
9245 	if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9246 		hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9247 
9248 	err = ufshcd_setup_clocks(hba, true);
9249 	if (err)
9250 		goto out_disable_hba_vreg;
9251 
9252 	err = ufshcd_init_vreg(hba);
9253 	if (err)
9254 		goto out_disable_clks;
9255 
9256 	err = ufshcd_setup_vreg(hba, true);
9257 	if (err)
9258 		goto out_disable_clks;
9259 
9260 	err = ufshcd_variant_hba_init(hba);
9261 	if (err)
9262 		goto out_disable_vreg;
9263 
9264 	ufs_debugfs_hba_init(hba);
9265 
9266 	hba->is_powered = true;
9267 	goto out;
9268 
9269 out_disable_vreg:
9270 	ufshcd_setup_vreg(hba, false);
9271 out_disable_clks:
9272 	ufshcd_setup_clocks(hba, false);
9273 out_disable_hba_vreg:
9274 	ufshcd_setup_hba_vreg(hba, false);
9275 out:
9276 	return err;
9277 }
9278 
ufshcd_hba_exit(struct ufs_hba * hba)9279 static void ufshcd_hba_exit(struct ufs_hba *hba)
9280 {
9281 	if (hba->is_powered) {
9282 		ufshcd_exit_clk_scaling(hba);
9283 		ufshcd_exit_clk_gating(hba);
9284 		if (hba->eh_wq)
9285 			destroy_workqueue(hba->eh_wq);
9286 		ufs_debugfs_hba_exit(hba);
9287 		ufshcd_variant_hba_exit(hba);
9288 		ufshcd_setup_vreg(hba, false);
9289 		ufshcd_setup_clocks(hba, false);
9290 		ufshcd_setup_hba_vreg(hba, false);
9291 		hba->is_powered = false;
9292 		ufs_put_device_desc(hba);
9293 	}
9294 }
9295 
ufshcd_execute_start_stop(struct scsi_device * sdev,enum ufs_dev_pwr_mode pwr_mode,struct scsi_sense_hdr * sshdr)9296 static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9297 				     enum ufs_dev_pwr_mode pwr_mode,
9298 				     struct scsi_sense_hdr *sshdr)
9299 {
9300 	const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9301 	const struct scsi_exec_args args = {
9302 		.sshdr = sshdr,
9303 		.req_flags = BLK_MQ_REQ_PM,
9304 		.scmd_flags = SCMD_FAIL_IF_RECOVERING,
9305 	};
9306 
9307 	return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL,
9308 			/*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0,
9309 			&args);
9310 }
9311 
9312 /**
9313  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9314  *			     power mode
9315  * @hba: per adapter instance
9316  * @pwr_mode: device power mode to set
9317  *
9318  * Return: 0 if requested power mode is set successfully;
9319  *         < 0 if failed to set the requested power mode.
9320  */
ufshcd_set_dev_pwr_mode(struct ufs_hba * hba,enum ufs_dev_pwr_mode pwr_mode)9321 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9322 				     enum ufs_dev_pwr_mode pwr_mode)
9323 {
9324 	struct scsi_sense_hdr sshdr;
9325 	struct scsi_device *sdp;
9326 	unsigned long flags;
9327 	int ret, retries;
9328 
9329 	spin_lock_irqsave(hba->host->host_lock, flags);
9330 	sdp = hba->ufs_device_wlun;
9331 	if (sdp && scsi_device_online(sdp))
9332 		ret = scsi_device_get(sdp);
9333 	else
9334 		ret = -ENODEV;
9335 	spin_unlock_irqrestore(hba->host->host_lock, flags);
9336 
9337 	if (ret)
9338 		return ret;
9339 
9340 	/*
9341 	 * If scsi commands fail, the scsi mid-layer schedules scsi error-
9342 	 * handling, which would wait for host to be resumed. Since we know
9343 	 * we are functional while we are here, skip host resume in error
9344 	 * handling context.
9345 	 */
9346 	hba->host->eh_noresume = 1;
9347 
9348 	/*
9349 	 * Current function would be generally called from the power management
9350 	 * callbacks hence set the RQF_PM flag so that it doesn't resume the
9351 	 * already suspended childs.
9352 	 */
9353 	for (retries = 3; retries > 0; --retries) {
9354 		ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
9355 		/*
9356 		 * scsi_execute() only returns a negative value if the request
9357 		 * queue is dying.
9358 		 */
9359 		if (ret <= 0)
9360 			break;
9361 	}
9362 	if (ret) {
9363 		sdev_printk(KERN_WARNING, sdp,
9364 			    "START_STOP failed for power mode: %d, result %x\n",
9365 			    pwr_mode, ret);
9366 		if (ret > 0) {
9367 			if (scsi_sense_valid(&sshdr))
9368 				scsi_print_sense_hdr(sdp, NULL, &sshdr);
9369 			ret = -EIO;
9370 		}
9371 	} else {
9372 		hba->curr_dev_pwr_mode = pwr_mode;
9373 	}
9374 
9375 	scsi_device_put(sdp);
9376 	hba->host->eh_noresume = 0;
9377 	return ret;
9378 }
9379 
ufshcd_link_state_transition(struct ufs_hba * hba,enum uic_link_state req_link_state,bool check_for_bkops)9380 static int ufshcd_link_state_transition(struct ufs_hba *hba,
9381 					enum uic_link_state req_link_state,
9382 					bool check_for_bkops)
9383 {
9384 	int ret = 0;
9385 
9386 	if (req_link_state == hba->uic_link_state)
9387 		return 0;
9388 
9389 	if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9390 		ret = ufshcd_uic_hibern8_enter(hba);
9391 		if (!ret) {
9392 			ufshcd_set_link_hibern8(hba);
9393 		} else {
9394 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9395 					__func__, ret);
9396 			goto out;
9397 		}
9398 	}
9399 	/*
9400 	 * If autobkops is enabled, link can't be turned off because
9401 	 * turning off the link would also turn off the device, except in the
9402 	 * case of DeepSleep where the device is expected to remain powered.
9403 	 */
9404 	else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9405 		 (!check_for_bkops || !hba->auto_bkops_enabled)) {
9406 		/*
9407 		 * Let's make sure that link is in low power mode, we are doing
9408 		 * this currently by putting the link in Hibern8. Otherway to
9409 		 * put the link in low power mode is to send the DME end point
9410 		 * to device and then send the DME reset command to local
9411 		 * unipro. But putting the link in hibern8 is much faster.
9412 		 *
9413 		 * Note also that putting the link in Hibern8 is a requirement
9414 		 * for entering DeepSleep.
9415 		 */
9416 		ret = ufshcd_uic_hibern8_enter(hba);
9417 		if (ret) {
9418 			dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9419 					__func__, ret);
9420 			goto out;
9421 		}
9422 		/*
9423 		 * Change controller state to "reset state" which
9424 		 * should also put the link in off/reset state
9425 		 */
9426 		ufshcd_hba_stop(hba);
9427 		/*
9428 		 * TODO: Check if we need any delay to make sure that
9429 		 * controller is reset
9430 		 */
9431 		ufshcd_set_link_off(hba);
9432 	}
9433 
9434 out:
9435 	return ret;
9436 }
9437 
ufshcd_vreg_set_lpm(struct ufs_hba * hba)9438 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9439 {
9440 	bool vcc_off = false;
9441 
9442 	/*
9443 	 * It seems some UFS devices may keep drawing more than sleep current
9444 	 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9445 	 * To avoid this situation, add 2ms delay before putting these UFS
9446 	 * rails in LPM mode.
9447 	 */
9448 	if (!ufshcd_is_link_active(hba) &&
9449 	    hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9450 		usleep_range(2000, 2100);
9451 
9452 	/*
9453 	 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9454 	 * power.
9455 	 *
9456 	 * If UFS device and link is in OFF state, all power supplies (VCC,
9457 	 * VCCQ, VCCQ2) can be turned off if power on write protect is not
9458 	 * required. If UFS link is inactive (Hibern8 or OFF state) and device
9459 	 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9460 	 *
9461 	 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9462 	 * in low power state which would save some power.
9463 	 *
9464 	 * If Write Booster is enabled and the device needs to flush the WB
9465 	 * buffer OR if bkops status is urgent for WB, keep Vcc on.
9466 	 */
9467 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9468 	    !hba->dev_info.is_lu_power_on_wp) {
9469 		ufshcd_setup_vreg(hba, false);
9470 		vcc_off = true;
9471 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9472 		ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9473 		vcc_off = true;
9474 		if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9475 			ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9476 			ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9477 		}
9478 	}
9479 
9480 	/*
9481 	 * Some UFS devices require delay after VCC power rail is turned-off.
9482 	 */
9483 	if (vcc_off && hba->vreg_info.vcc &&
9484 		hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9485 		usleep_range(5000, 5100);
9486 }
9487 
9488 #ifdef CONFIG_PM
ufshcd_vreg_set_hpm(struct ufs_hba * hba)9489 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9490 {
9491 	int ret = 0;
9492 
9493 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9494 	    !hba->dev_info.is_lu_power_on_wp) {
9495 		ret = ufshcd_setup_vreg(hba, true);
9496 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
9497 		if (!ufshcd_is_link_active(hba)) {
9498 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9499 			if (ret)
9500 				goto vcc_disable;
9501 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9502 			if (ret)
9503 				goto vccq_lpm;
9504 		}
9505 		ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9506 	}
9507 	goto out;
9508 
9509 vccq_lpm:
9510 	ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9511 vcc_disable:
9512 	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9513 out:
9514 	return ret;
9515 }
9516 #endif /* CONFIG_PM */
9517 
ufshcd_hba_vreg_set_lpm(struct ufs_hba * hba)9518 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9519 {
9520 	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9521 		ufshcd_setup_hba_vreg(hba, false);
9522 }
9523 
ufshcd_hba_vreg_set_hpm(struct ufs_hba * hba)9524 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9525 {
9526 	if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9527 		ufshcd_setup_hba_vreg(hba, true);
9528 }
9529 
__ufshcd_wl_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)9530 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9531 {
9532 	int ret = 0;
9533 	bool check_for_bkops;
9534 	enum ufs_pm_level pm_lvl;
9535 	enum ufs_dev_pwr_mode req_dev_pwr_mode;
9536 	enum uic_link_state req_link_state;
9537 
9538 	hba->pm_op_in_progress = true;
9539 	if (pm_op != UFS_SHUTDOWN_PM) {
9540 		pm_lvl = pm_op == UFS_RUNTIME_PM ?
9541 			 hba->rpm_lvl : hba->spm_lvl;
9542 		req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9543 		req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9544 	} else {
9545 		req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9546 		req_link_state = UIC_LINK_OFF_STATE;
9547 	}
9548 
9549 	/*
9550 	 * If we can't transition into any of the low power modes
9551 	 * just gate the clocks.
9552 	 */
9553 	ufshcd_hold(hba);
9554 	hba->clk_gating.is_suspended = true;
9555 
9556 	if (ufshcd_is_clkscaling_supported(hba))
9557 		ufshcd_clk_scaling_suspend(hba, true);
9558 
9559 	if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9560 			req_link_state == UIC_LINK_ACTIVE_STATE) {
9561 		goto vops_suspend;
9562 	}
9563 
9564 	if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9565 	    (req_link_state == hba->uic_link_state))
9566 		goto enable_scaling;
9567 
9568 	/* UFS device & link must be active before we enter in this function */
9569 	if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9570 		/*  Wait err handler finish or trigger err recovery */
9571 		if (!ufshcd_eh_in_progress(hba))
9572 			ufshcd_force_error_recovery(hba);
9573 		ret = -EBUSY;
9574 		goto enable_scaling;
9575 	}
9576 
9577 	if (pm_op == UFS_RUNTIME_PM) {
9578 		if (ufshcd_can_autobkops_during_suspend(hba)) {
9579 			/*
9580 			 * The device is idle with no requests in the queue,
9581 			 * allow background operations if bkops status shows
9582 			 * that performance might be impacted.
9583 			 */
9584 			ret = ufshcd_urgent_bkops(hba);
9585 			if (ret) {
9586 				/*
9587 				 * If return err in suspend flow, IO will hang.
9588 				 * Trigger error handler and break suspend for
9589 				 * error recovery.
9590 				 */
9591 				ufshcd_force_error_recovery(hba);
9592 				ret = -EBUSY;
9593 				goto enable_scaling;
9594 			}
9595 		} else {
9596 			/* make sure that auto bkops is disabled */
9597 			ufshcd_disable_auto_bkops(hba);
9598 		}
9599 		/*
9600 		 * If device needs to do BKOP or WB buffer flush during
9601 		 * Hibern8, keep device power mode as "active power mode"
9602 		 * and VCC supply.
9603 		 */
9604 		hba->dev_info.b_rpm_dev_flush_capable =
9605 			hba->auto_bkops_enabled ||
9606 			(((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9607 			((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9608 			ufshcd_is_auto_hibern8_enabled(hba))) &&
9609 			ufshcd_wb_need_flush(hba));
9610 	}
9611 
9612 	flush_work(&hba->eeh_work);
9613 
9614 	ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9615 	if (ret)
9616 		goto enable_scaling;
9617 
9618 	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9619 		if (pm_op != UFS_RUNTIME_PM)
9620 			/* ensure that bkops is disabled */
9621 			ufshcd_disable_auto_bkops(hba);
9622 
9623 		if (!hba->dev_info.b_rpm_dev_flush_capable) {
9624 			ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9625 			if (ret && pm_op != UFS_SHUTDOWN_PM) {
9626 				/*
9627 				 * If return err in suspend flow, IO will hang.
9628 				 * Trigger error handler and break suspend for
9629 				 * error recovery.
9630 				 */
9631 				ufshcd_force_error_recovery(hba);
9632 				ret = -EBUSY;
9633 			}
9634 			if (ret)
9635 				goto enable_scaling;
9636 		}
9637 	}
9638 
9639 	/*
9640 	 * In the case of DeepSleep, the device is expected to remain powered
9641 	 * with the link off, so do not check for bkops.
9642 	 */
9643 	check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9644 	ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9645 	if (ret && pm_op != UFS_SHUTDOWN_PM) {
9646 		/*
9647 		 * If return err in suspend flow, IO will hang.
9648 		 * Trigger error handler and break suspend for
9649 		 * error recovery.
9650 		 */
9651 		ufshcd_force_error_recovery(hba);
9652 		ret = -EBUSY;
9653 	}
9654 	if (ret)
9655 		goto set_dev_active;
9656 
9657 vops_suspend:
9658 	/*
9659 	 * Call vendor specific suspend callback. As these callbacks may access
9660 	 * vendor specific host controller register space call them before the
9661 	 * host clocks are ON.
9662 	 */
9663 	ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9664 	if (ret)
9665 		goto set_link_active;
9666 	goto out;
9667 
9668 set_link_active:
9669 	/*
9670 	 * Device hardware reset is required to exit DeepSleep. Also, for
9671 	 * DeepSleep, the link is off so host reset and restore will be done
9672 	 * further below.
9673 	 */
9674 	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9675 		ufshcd_device_reset(hba);
9676 		WARN_ON(!ufshcd_is_link_off(hba));
9677 	}
9678 	if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9679 		ufshcd_set_link_active(hba);
9680 	else if (ufshcd_is_link_off(hba))
9681 		ufshcd_host_reset_and_restore(hba);
9682 set_dev_active:
9683 	/* Can also get here needing to exit DeepSleep */
9684 	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9685 		ufshcd_device_reset(hba);
9686 		ufshcd_host_reset_and_restore(hba);
9687 	}
9688 	if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9689 		ufshcd_disable_auto_bkops(hba);
9690 enable_scaling:
9691 	if (ufshcd_is_clkscaling_supported(hba))
9692 		ufshcd_clk_scaling_suspend(hba, false);
9693 
9694 	hba->dev_info.b_rpm_dev_flush_capable = false;
9695 out:
9696 	if (hba->dev_info.b_rpm_dev_flush_capable) {
9697 		schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9698 			msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9699 	}
9700 
9701 	if (ret) {
9702 		ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9703 		hba->clk_gating.is_suspended = false;
9704 		ufshcd_release(hba);
9705 	}
9706 	hba->pm_op_in_progress = false;
9707 	return ret;
9708 }
9709 
9710 #ifdef CONFIG_PM
__ufshcd_wl_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)9711 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9712 {
9713 	int ret;
9714 	enum uic_link_state old_link_state = hba->uic_link_state;
9715 
9716 	hba->pm_op_in_progress = true;
9717 
9718 	/*
9719 	 * Call vendor specific resume callback. As these callbacks may access
9720 	 * vendor specific host controller register space call them when the
9721 	 * host clocks are ON.
9722 	 */
9723 	ret = ufshcd_vops_resume(hba, pm_op);
9724 	if (ret)
9725 		goto out;
9726 
9727 	/* For DeepSleep, the only supported option is to have the link off */
9728 	WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9729 
9730 	if (ufshcd_is_link_hibern8(hba)) {
9731 		ret = ufshcd_uic_hibern8_exit(hba);
9732 		if (!ret) {
9733 			ufshcd_set_link_active(hba);
9734 		} else {
9735 			dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9736 					__func__, ret);
9737 			goto vendor_suspend;
9738 		}
9739 	} else if (ufshcd_is_link_off(hba)) {
9740 		/*
9741 		 * A full initialization of the host and the device is
9742 		 * required since the link was put to off during suspend.
9743 		 * Note, in the case of DeepSleep, the device will exit
9744 		 * DeepSleep due to device reset.
9745 		 */
9746 		ret = ufshcd_reset_and_restore(hba);
9747 		/*
9748 		 * ufshcd_reset_and_restore() should have already
9749 		 * set the link state as active
9750 		 */
9751 		if (ret || !ufshcd_is_link_active(hba))
9752 			goto vendor_suspend;
9753 	}
9754 
9755 	if (!ufshcd_is_ufs_dev_active(hba)) {
9756 		ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9757 		if (ret)
9758 			goto set_old_link_state;
9759 		ufshcd_set_timestamp_attr(hba);
9760 	}
9761 
9762 	if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9763 		ufshcd_enable_auto_bkops(hba);
9764 	else
9765 		/*
9766 		 * If BKOPs operations are urgently needed at this moment then
9767 		 * keep auto-bkops enabled or else disable it.
9768 		 */
9769 		ufshcd_urgent_bkops(hba);
9770 
9771 	if (hba->ee_usr_mask)
9772 		ufshcd_write_ee_control(hba);
9773 
9774 	if (ufshcd_is_clkscaling_supported(hba))
9775 		ufshcd_clk_scaling_suspend(hba, false);
9776 
9777 	if (hba->dev_info.b_rpm_dev_flush_capable) {
9778 		hba->dev_info.b_rpm_dev_flush_capable = false;
9779 		cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9780 	}
9781 
9782 	/* Enable Auto-Hibernate if configured */
9783 	ufshcd_auto_hibern8_enable(hba);
9784 
9785 	goto out;
9786 
9787 set_old_link_state:
9788 	ufshcd_link_state_transition(hba, old_link_state, 0);
9789 vendor_suspend:
9790 	ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9791 	ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9792 out:
9793 	if (ret)
9794 		ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9795 	hba->clk_gating.is_suspended = false;
9796 	ufshcd_release(hba);
9797 	hba->pm_op_in_progress = false;
9798 	return ret;
9799 }
9800 
ufshcd_wl_runtime_suspend(struct device * dev)9801 static int ufshcd_wl_runtime_suspend(struct device *dev)
9802 {
9803 	struct scsi_device *sdev = to_scsi_device(dev);
9804 	struct ufs_hba *hba;
9805 	int ret;
9806 	ktime_t start = ktime_get();
9807 
9808 	hba = shost_priv(sdev->host);
9809 
9810 	ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9811 	if (ret)
9812 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9813 
9814 	trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9815 		ktime_to_us(ktime_sub(ktime_get(), start)),
9816 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9817 
9818 	return ret;
9819 }
9820 
ufshcd_wl_runtime_resume(struct device * dev)9821 static int ufshcd_wl_runtime_resume(struct device *dev)
9822 {
9823 	struct scsi_device *sdev = to_scsi_device(dev);
9824 	struct ufs_hba *hba;
9825 	int ret = 0;
9826 	ktime_t start = ktime_get();
9827 
9828 	hba = shost_priv(sdev->host);
9829 
9830 	ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9831 	if (ret)
9832 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9833 
9834 	trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9835 		ktime_to_us(ktime_sub(ktime_get(), start)),
9836 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9837 
9838 	return ret;
9839 }
9840 #endif
9841 
9842 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_suspend(struct device * dev)9843 static int ufshcd_wl_suspend(struct device *dev)
9844 {
9845 	struct scsi_device *sdev = to_scsi_device(dev);
9846 	struct ufs_hba *hba;
9847 	int ret = 0;
9848 	ktime_t start = ktime_get();
9849 
9850 	hba = shost_priv(sdev->host);
9851 	down(&hba->host_sem);
9852 	hba->system_suspending = true;
9853 
9854 	if (pm_runtime_suspended(dev))
9855 		goto out;
9856 
9857 	ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9858 	if (ret) {
9859 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
9860 		up(&hba->host_sem);
9861 	}
9862 
9863 out:
9864 	if (!ret)
9865 		hba->is_sys_suspended = true;
9866 	trace_ufshcd_wl_suspend(dev_name(dev), ret,
9867 		ktime_to_us(ktime_sub(ktime_get(), start)),
9868 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9869 
9870 	return ret;
9871 }
9872 
ufshcd_wl_resume(struct device * dev)9873 static int ufshcd_wl_resume(struct device *dev)
9874 {
9875 	struct scsi_device *sdev = to_scsi_device(dev);
9876 	struct ufs_hba *hba;
9877 	int ret = 0;
9878 	ktime_t start = ktime_get();
9879 
9880 	hba = shost_priv(sdev->host);
9881 
9882 	if (pm_runtime_suspended(dev))
9883 		goto out;
9884 
9885 	ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9886 	if (ret)
9887 		dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9888 out:
9889 	trace_ufshcd_wl_resume(dev_name(dev), ret,
9890 		ktime_to_us(ktime_sub(ktime_get(), start)),
9891 		hba->curr_dev_pwr_mode, hba->uic_link_state);
9892 	if (!ret)
9893 		hba->is_sys_suspended = false;
9894 	hba->system_suspending = false;
9895 	up(&hba->host_sem);
9896 	return ret;
9897 }
9898 #endif
9899 
9900 /**
9901  * ufshcd_suspend - helper function for suspend operations
9902  * @hba: per adapter instance
9903  *
9904  * This function will put disable irqs, turn off clocks
9905  * and set vreg and hba-vreg in lpm mode.
9906  *
9907  * Return: 0 upon success; < 0 upon failure.
9908  */
ufshcd_suspend(struct ufs_hba * hba)9909 static int ufshcd_suspend(struct ufs_hba *hba)
9910 {
9911 	int ret;
9912 
9913 	if (!hba->is_powered)
9914 		return 0;
9915 	/*
9916 	 * Disable the host irq as host controller as there won't be any
9917 	 * host controller transaction expected till resume.
9918 	 */
9919 	ufshcd_disable_irq(hba);
9920 	ret = ufshcd_setup_clocks(hba, false);
9921 	if (ret) {
9922 		ufshcd_enable_irq(hba);
9923 		return ret;
9924 	}
9925 	if (ufshcd_is_clkgating_allowed(hba)) {
9926 		hba->clk_gating.state = CLKS_OFF;
9927 		trace_ufshcd_clk_gating(dev_name(hba->dev),
9928 					hba->clk_gating.state);
9929 	}
9930 
9931 	ufshcd_vreg_set_lpm(hba);
9932 	/* Put the host controller in low power mode if possible */
9933 	ufshcd_hba_vreg_set_lpm(hba);
9934 	return ret;
9935 }
9936 
9937 #ifdef CONFIG_PM
9938 /**
9939  * ufshcd_resume - helper function for resume operations
9940  * @hba: per adapter instance
9941  *
9942  * This function basically turns on the regulators, clocks and
9943  * irqs of the hba.
9944  *
9945  * Return: 0 for success and non-zero for failure.
9946  */
ufshcd_resume(struct ufs_hba * hba)9947 static int ufshcd_resume(struct ufs_hba *hba)
9948 {
9949 	int ret;
9950 
9951 	if (!hba->is_powered)
9952 		return 0;
9953 
9954 	ufshcd_hba_vreg_set_hpm(hba);
9955 	ret = ufshcd_vreg_set_hpm(hba);
9956 	if (ret)
9957 		goto out;
9958 
9959 	/* Make sure clocks are enabled before accessing controller */
9960 	ret = ufshcd_setup_clocks(hba, true);
9961 	if (ret)
9962 		goto disable_vreg;
9963 
9964 	/* enable the host irq as host controller would be active soon */
9965 	ufshcd_enable_irq(hba);
9966 
9967 	goto out;
9968 
9969 disable_vreg:
9970 	ufshcd_vreg_set_lpm(hba);
9971 out:
9972 	if (ret)
9973 		ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9974 	return ret;
9975 }
9976 #endif /* CONFIG_PM */
9977 
9978 #ifdef CONFIG_PM_SLEEP
9979 /**
9980  * ufshcd_system_suspend - system suspend callback
9981  * @dev: Device associated with the UFS controller.
9982  *
9983  * Executed before putting the system into a sleep state in which the contents
9984  * of main memory are preserved.
9985  *
9986  * Return: 0 for success and non-zero for failure.
9987  */
ufshcd_system_suspend(struct device * dev)9988 int ufshcd_system_suspend(struct device *dev)
9989 {
9990 	struct ufs_hba *hba = dev_get_drvdata(dev);
9991 	int ret = 0;
9992 	ktime_t start = ktime_get();
9993 
9994 	if (pm_runtime_suspended(hba->dev))
9995 		goto out;
9996 
9997 	ret = ufshcd_suspend(hba);
9998 out:
9999 	trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
10000 		ktime_to_us(ktime_sub(ktime_get(), start)),
10001 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10002 	return ret;
10003 }
10004 EXPORT_SYMBOL(ufshcd_system_suspend);
10005 
10006 /**
10007  * ufshcd_system_resume - system resume callback
10008  * @dev: Device associated with the UFS controller.
10009  *
10010  * Executed after waking the system up from a sleep state in which the contents
10011  * of main memory were preserved.
10012  *
10013  * Return: 0 for success and non-zero for failure.
10014  */
ufshcd_system_resume(struct device * dev)10015 int ufshcd_system_resume(struct device *dev)
10016 {
10017 	struct ufs_hba *hba = dev_get_drvdata(dev);
10018 	ktime_t start = ktime_get();
10019 	int ret = 0;
10020 
10021 	if (pm_runtime_suspended(hba->dev))
10022 		goto out;
10023 
10024 	ret = ufshcd_resume(hba);
10025 
10026 out:
10027 	trace_ufshcd_system_resume(dev_name(hba->dev), ret,
10028 		ktime_to_us(ktime_sub(ktime_get(), start)),
10029 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10030 
10031 	return ret;
10032 }
10033 EXPORT_SYMBOL(ufshcd_system_resume);
10034 #endif /* CONFIG_PM_SLEEP */
10035 
10036 #ifdef CONFIG_PM
10037 /**
10038  * ufshcd_runtime_suspend - runtime suspend callback
10039  * @dev: Device associated with the UFS controller.
10040  *
10041  * Check the description of ufshcd_suspend() function for more details.
10042  *
10043  * Return: 0 for success and non-zero for failure.
10044  */
ufshcd_runtime_suspend(struct device * dev)10045 int ufshcd_runtime_suspend(struct device *dev)
10046 {
10047 	struct ufs_hba *hba = dev_get_drvdata(dev);
10048 	int ret;
10049 	ktime_t start = ktime_get();
10050 
10051 	ret = ufshcd_suspend(hba);
10052 
10053 	trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
10054 		ktime_to_us(ktime_sub(ktime_get(), start)),
10055 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10056 	return ret;
10057 }
10058 EXPORT_SYMBOL(ufshcd_runtime_suspend);
10059 
10060 /**
10061  * ufshcd_runtime_resume - runtime resume routine
10062  * @dev: Device associated with the UFS controller.
10063  *
10064  * This function basically brings controller
10065  * to active state. Following operations are done in this function:
10066  *
10067  * 1. Turn on all the controller related clocks
10068  * 2. Turn ON VCC rail
10069  *
10070  * Return: 0 upon success; < 0 upon failure.
10071  */
ufshcd_runtime_resume(struct device * dev)10072 int ufshcd_runtime_resume(struct device *dev)
10073 {
10074 	struct ufs_hba *hba = dev_get_drvdata(dev);
10075 	int ret;
10076 	ktime_t start = ktime_get();
10077 
10078 	ret = ufshcd_resume(hba);
10079 
10080 	trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
10081 		ktime_to_us(ktime_sub(ktime_get(), start)),
10082 		hba->curr_dev_pwr_mode, hba->uic_link_state);
10083 	return ret;
10084 }
10085 EXPORT_SYMBOL(ufshcd_runtime_resume);
10086 #endif /* CONFIG_PM */
10087 
ufshcd_wl_shutdown(struct device * dev)10088 static void ufshcd_wl_shutdown(struct device *dev)
10089 {
10090 	struct scsi_device *sdev = to_scsi_device(dev);
10091 	struct ufs_hba *hba = shost_priv(sdev->host);
10092 
10093 	down(&hba->host_sem);
10094 	hba->shutting_down = true;
10095 	up(&hba->host_sem);
10096 
10097 	/* Turn on everything while shutting down */
10098 	ufshcd_rpm_get_sync(hba);
10099 	scsi_device_quiesce(sdev);
10100 	shost_for_each_device(sdev, hba->host) {
10101 		if (sdev == hba->ufs_device_wlun)
10102 			continue;
10103 		mutex_lock(&sdev->state_mutex);
10104 		scsi_device_set_state(sdev, SDEV_OFFLINE);
10105 		mutex_unlock(&sdev->state_mutex);
10106 	}
10107 	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10108 
10109 	/*
10110 	 * Next, turn off the UFS controller and the UFS regulators. Disable
10111 	 * clocks.
10112 	 */
10113 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
10114 		ufshcd_suspend(hba);
10115 
10116 	hba->is_powered = false;
10117 }
10118 
10119 /**
10120  * ufshcd_remove - de-allocate SCSI host and host memory space
10121  *		data structure memory
10122  * @hba: per adapter instance
10123  */
ufshcd_remove(struct ufs_hba * hba)10124 void ufshcd_remove(struct ufs_hba *hba)
10125 {
10126 	if (hba->ufs_device_wlun)
10127 		ufshcd_rpm_get_sync(hba);
10128 	ufs_hwmon_remove(hba);
10129 	ufs_bsg_remove(hba);
10130 	ufs_sysfs_remove_nodes(hba->dev);
10131 	blk_mq_destroy_queue(hba->tmf_queue);
10132 	blk_put_queue(hba->tmf_queue);
10133 	blk_mq_free_tag_set(&hba->tmf_tag_set);
10134 	if (hba->scsi_host_added)
10135 		scsi_remove_host(hba->host);
10136 	/* disable interrupts */
10137 	ufshcd_disable_intr(hba, hba->intr_mask);
10138 	ufshcd_hba_stop(hba);
10139 	ufshcd_hba_exit(hba);
10140 }
10141 EXPORT_SYMBOL_GPL(ufshcd_remove);
10142 
10143 #ifdef CONFIG_PM_SLEEP
ufshcd_system_freeze(struct device * dev)10144 int ufshcd_system_freeze(struct device *dev)
10145 {
10146 
10147 	return ufshcd_system_suspend(dev);
10148 
10149 }
10150 EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
10151 
ufshcd_system_restore(struct device * dev)10152 int ufshcd_system_restore(struct device *dev)
10153 {
10154 
10155 	struct ufs_hba *hba = dev_get_drvdata(dev);
10156 	int ret;
10157 
10158 	ret = ufshcd_system_resume(dev);
10159 	if (ret)
10160 		return ret;
10161 
10162 	/* Configure UTRL and UTMRL base address registers */
10163 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10164 			REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10165 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10166 			REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10167 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10168 			REG_UTP_TASK_REQ_LIST_BASE_L);
10169 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10170 			REG_UTP_TASK_REQ_LIST_BASE_H);
10171 	/*
10172 	 * Make sure that UTRL and UTMRL base address registers
10173 	 * are updated with the latest queue addresses. Only after
10174 	 * updating these addresses, we can queue the new commands.
10175 	 */
10176 	ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
10177 
10178 	return 0;
10179 
10180 }
10181 EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10182 
ufshcd_system_thaw(struct device * dev)10183 int ufshcd_system_thaw(struct device *dev)
10184 {
10185 	return ufshcd_system_resume(dev);
10186 }
10187 EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10188 #endif /* CONFIG_PM_SLEEP  */
10189 
10190 /**
10191  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
10192  * @hba: pointer to Host Bus Adapter (HBA)
10193  */
ufshcd_dealloc_host(struct ufs_hba * hba)10194 void ufshcd_dealloc_host(struct ufs_hba *hba)
10195 {
10196 	scsi_host_put(hba->host);
10197 }
10198 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
10199 
10200 /**
10201  * ufshcd_set_dma_mask - Set dma mask based on the controller
10202  *			 addressing capability
10203  * @hba: per adapter instance
10204  *
10205  * Return: 0 for success, non-zero for failure.
10206  */
ufshcd_set_dma_mask(struct ufs_hba * hba)10207 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10208 {
10209 	if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10210 		if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
10211 			return 0;
10212 	}
10213 	return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
10214 }
10215 
10216 /**
10217  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10218  * @dev: pointer to device handle
10219  * @hba_handle: driver private handle
10220  *
10221  * Return: 0 on success, non-zero value on failure.
10222  */
ufshcd_alloc_host(struct device * dev,struct ufs_hba ** hba_handle)10223 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10224 {
10225 	struct Scsi_Host *host;
10226 	struct ufs_hba *hba;
10227 	int err = 0;
10228 
10229 	if (!dev) {
10230 		dev_err(dev,
10231 		"Invalid memory reference for dev is NULL\n");
10232 		err = -ENODEV;
10233 		goto out_error;
10234 	}
10235 
10236 	host = scsi_host_alloc(&ufshcd_driver_template,
10237 				sizeof(struct ufs_hba));
10238 	if (!host) {
10239 		dev_err(dev, "scsi_host_alloc failed\n");
10240 		err = -ENOMEM;
10241 		goto out_error;
10242 	}
10243 	host->nr_maps = HCTX_TYPE_POLL + 1;
10244 	hba = shost_priv(host);
10245 	hba->host = host;
10246 	hba->dev = dev;
10247 	hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10248 	hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10249 	ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
10250 	INIT_LIST_HEAD(&hba->clk_list_head);
10251 	spin_lock_init(&hba->outstanding_lock);
10252 
10253 	*hba_handle = hba;
10254 
10255 out_error:
10256 	return err;
10257 }
10258 EXPORT_SYMBOL(ufshcd_alloc_host);
10259 
10260 /* This function exists because blk_mq_alloc_tag_set() requires this. */
ufshcd_queue_tmf(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * qd)10261 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10262 				     const struct blk_mq_queue_data *qd)
10263 {
10264 	WARN_ON_ONCE(true);
10265 	return BLK_STS_NOTSUPP;
10266 }
10267 
10268 static const struct blk_mq_ops ufshcd_tmf_ops = {
10269 	.queue_rq = ufshcd_queue_tmf,
10270 };
10271 
10272 /**
10273  * ufshcd_init - Driver initialization routine
10274  * @hba: per-adapter instance
10275  * @mmio_base: base register address
10276  * @irq: Interrupt line of device
10277  *
10278  * Return: 0 on success, non-zero value on failure.
10279  */
ufshcd_init(struct ufs_hba * hba,void __iomem * mmio_base,unsigned int irq)10280 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10281 {
10282 	int err;
10283 	struct Scsi_Host *host = hba->host;
10284 	struct device *dev = hba->dev;
10285 	char eh_wq_name[sizeof("ufs_eh_wq_00")];
10286 
10287 	/*
10288 	 * dev_set_drvdata() must be called before any callbacks are registered
10289 	 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10290 	 * sysfs).
10291 	 */
10292 	dev_set_drvdata(dev, hba);
10293 
10294 	if (!mmio_base) {
10295 		dev_err(hba->dev,
10296 		"Invalid memory reference for mmio_base is NULL\n");
10297 		err = -ENODEV;
10298 		goto out_error;
10299 	}
10300 
10301 	hba->mmio_base = mmio_base;
10302 	hba->irq = irq;
10303 	hba->vps = &ufs_hba_vps;
10304 
10305 	err = ufshcd_hba_init(hba);
10306 	if (err)
10307 		goto out_error;
10308 
10309 	/* Read capabilities registers */
10310 	err = ufshcd_hba_capabilities(hba);
10311 	if (err)
10312 		goto out_disable;
10313 
10314 	/* Get UFS version supported by the controller */
10315 	hba->ufs_version = ufshcd_get_ufs_version(hba);
10316 
10317 	/* Get Interrupt bit mask per version */
10318 	hba->intr_mask = ufshcd_get_intr_mask(hba);
10319 
10320 	err = ufshcd_set_dma_mask(hba);
10321 	if (err) {
10322 		dev_err(hba->dev, "set dma mask failed\n");
10323 		goto out_disable;
10324 	}
10325 
10326 	/* Allocate memory for host memory space */
10327 	err = ufshcd_memory_alloc(hba);
10328 	if (err) {
10329 		dev_err(hba->dev, "Memory allocation failed\n");
10330 		goto out_disable;
10331 	}
10332 
10333 	/* Configure LRB */
10334 	ufshcd_host_memory_configure(hba);
10335 
10336 	host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10337 	host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
10338 	host->max_id = UFSHCD_MAX_ID;
10339 	host->max_lun = UFS_MAX_LUNS;
10340 	host->max_channel = UFSHCD_MAX_CHANNEL;
10341 	host->unique_id = host->host_no;
10342 	host->max_cmd_len = UFS_CDB_SIZE;
10343 	host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING);
10344 
10345 	hba->max_pwr_info.is_valid = false;
10346 
10347 	/* Initialize work queues */
10348 	snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
10349 		 hba->host->host_no);
10350 	hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
10351 	if (!hba->eh_wq) {
10352 		dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10353 			__func__);
10354 		err = -ENOMEM;
10355 		goto out_disable;
10356 	}
10357 	INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10358 	INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10359 
10360 	sema_init(&hba->host_sem, 1);
10361 
10362 	/* Initialize UIC command mutex */
10363 	mutex_init(&hba->uic_cmd_mutex);
10364 
10365 	/* Initialize mutex for device management commands */
10366 	mutex_init(&hba->dev_cmd.lock);
10367 
10368 	/* Initialize mutex for exception event control */
10369 	mutex_init(&hba->ee_ctrl_mutex);
10370 
10371 	mutex_init(&hba->wb_mutex);
10372 	init_rwsem(&hba->clk_scaling_lock);
10373 
10374 	ufshcd_init_clk_gating(hba);
10375 
10376 	ufshcd_init_clk_scaling(hba);
10377 
10378 	/*
10379 	 * In order to avoid any spurious interrupt immediately after
10380 	 * registering UFS controller interrupt handler, clear any pending UFS
10381 	 * interrupt status and disable all the UFS interrupts.
10382 	 */
10383 	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10384 		      REG_INTERRUPT_STATUS);
10385 	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10386 	/*
10387 	 * Make sure that UFS interrupts are disabled and any pending interrupt
10388 	 * status is cleared before registering UFS interrupt handler.
10389 	 */
10390 	ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
10391 
10392 	/* IRQ registration */
10393 	err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
10394 	if (err) {
10395 		dev_err(hba->dev, "request irq failed\n");
10396 		goto out_disable;
10397 	} else {
10398 		hba->is_irq_enabled = true;
10399 	}
10400 
10401 	if (!is_mcq_supported(hba)) {
10402 		if (!hba->lsdb_sup) {
10403 			dev_err(hba->dev, "%s: failed to initialize (legacy doorbell mode not supported)\n",
10404 				__func__);
10405 			err = -EINVAL;
10406 			goto out_disable;
10407 		}
10408 		err = scsi_add_host(host, hba->dev);
10409 		if (err) {
10410 			dev_err(hba->dev, "scsi_add_host failed\n");
10411 			goto out_disable;
10412 		}
10413 		hba->scsi_host_added = true;
10414 	}
10415 
10416 	hba->tmf_tag_set = (struct blk_mq_tag_set) {
10417 		.nr_hw_queues	= 1,
10418 		.queue_depth	= hba->nutmrs,
10419 		.ops		= &ufshcd_tmf_ops,
10420 		.flags		= BLK_MQ_F_NO_SCHED,
10421 	};
10422 	err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
10423 	if (err < 0)
10424 		goto out_remove_scsi_host;
10425 	hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
10426 	if (IS_ERR(hba->tmf_queue)) {
10427 		err = PTR_ERR(hba->tmf_queue);
10428 		goto free_tmf_tag_set;
10429 	}
10430 	hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
10431 				    sizeof(*hba->tmf_rqs), GFP_KERNEL);
10432 	if (!hba->tmf_rqs) {
10433 		err = -ENOMEM;
10434 		goto free_tmf_queue;
10435 	}
10436 
10437 	/* Reset the attached device */
10438 	ufshcd_device_reset(hba);
10439 
10440 	ufshcd_init_crypto(hba);
10441 
10442 	/* Host controller enable */
10443 	err = ufshcd_hba_enable(hba);
10444 	if (err) {
10445 		dev_err(hba->dev, "Host controller enable failed\n");
10446 		ufshcd_print_evt_hist(hba);
10447 		ufshcd_print_host_state(hba);
10448 		goto free_tmf_queue;
10449 	}
10450 
10451 	/*
10452 	 * Set the default power management level for runtime and system PM.
10453 	 * Default power saving mode is to keep UFS link in Hibern8 state
10454 	 * and UFS device in sleep state.
10455 	 */
10456 	hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10457 						UFS_SLEEP_PWR_MODE,
10458 						UIC_LINK_HIBERN8_STATE);
10459 	hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10460 						UFS_SLEEP_PWR_MODE,
10461 						UIC_LINK_HIBERN8_STATE);
10462 
10463 	INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
10464 			  ufshcd_rpm_dev_flush_recheck_work);
10465 
10466 	/* Set the default auto-hiberate idle timer value to 150 ms */
10467 	if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10468 		hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10469 			    FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10470 	}
10471 
10472 	/* Hold auto suspend until async scan completes */
10473 	pm_runtime_get_sync(dev);
10474 	atomic_set(&hba->scsi_block_reqs_cnt, 0);
10475 	/*
10476 	 * We are assuming that device wasn't put in sleep/power-down
10477 	 * state exclusively during the boot stage before kernel.
10478 	 * This assumption helps avoid doing link startup twice during
10479 	 * ufshcd_probe_hba().
10480 	 */
10481 	ufshcd_set_ufs_dev_active(hba);
10482 
10483 	async_schedule(ufshcd_async_scan, hba);
10484 	ufs_sysfs_add_nodes(hba->dev);
10485 
10486 	device_enable_async_suspend(dev);
10487 	return 0;
10488 
10489 free_tmf_queue:
10490 	blk_mq_destroy_queue(hba->tmf_queue);
10491 	blk_put_queue(hba->tmf_queue);
10492 free_tmf_tag_set:
10493 	blk_mq_free_tag_set(&hba->tmf_tag_set);
10494 out_remove_scsi_host:
10495 	if (hba->scsi_host_added)
10496 		scsi_remove_host(hba->host);
10497 out_disable:
10498 	hba->is_irq_enabled = false;
10499 	ufshcd_hba_exit(hba);
10500 out_error:
10501 	return err;
10502 }
10503 EXPORT_SYMBOL_GPL(ufshcd_init);
10504 
ufshcd_resume_complete(struct device * dev)10505 void ufshcd_resume_complete(struct device *dev)
10506 {
10507 	struct ufs_hba *hba = dev_get_drvdata(dev);
10508 
10509 	if (hba->complete_put) {
10510 		ufshcd_rpm_put(hba);
10511 		hba->complete_put = false;
10512 	}
10513 }
10514 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10515 
ufshcd_rpm_ok_for_spm(struct ufs_hba * hba)10516 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10517 {
10518 	struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
10519 	enum ufs_dev_pwr_mode dev_pwr_mode;
10520 	enum uic_link_state link_state;
10521 	unsigned long flags;
10522 	bool res;
10523 
10524 	spin_lock_irqsave(&dev->power.lock, flags);
10525 	dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10526 	link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10527 	res = pm_runtime_suspended(dev) &&
10528 	      hba->curr_dev_pwr_mode == dev_pwr_mode &&
10529 	      hba->uic_link_state == link_state &&
10530 	      !hba->dev_info.b_rpm_dev_flush_capable;
10531 	spin_unlock_irqrestore(&dev->power.lock, flags);
10532 
10533 	return res;
10534 }
10535 
__ufshcd_suspend_prepare(struct device * dev,bool rpm_ok_for_spm)10536 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
10537 {
10538 	struct ufs_hba *hba = dev_get_drvdata(dev);
10539 	int ret;
10540 
10541 	/*
10542 	 * SCSI assumes that runtime-pm and system-pm for scsi drivers
10543 	 * are same. And it doesn't wake up the device for system-suspend
10544 	 * if it's runtime suspended. But ufs doesn't follow that.
10545 	 * Refer ufshcd_resume_complete()
10546 	 */
10547 	if (hba->ufs_device_wlun) {
10548 		/* Prevent runtime suspend */
10549 		ufshcd_rpm_get_noresume(hba);
10550 		/*
10551 		 * Check if already runtime suspended in same state as system
10552 		 * suspend would be.
10553 		 */
10554 		if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10555 			/* RPM state is not ok for SPM, so runtime resume */
10556 			ret = ufshcd_rpm_resume(hba);
10557 			if (ret < 0 && ret != -EACCES) {
10558 				ufshcd_rpm_put(hba);
10559 				return ret;
10560 			}
10561 		}
10562 		hba->complete_put = true;
10563 	}
10564 	return 0;
10565 }
10566 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10567 
ufshcd_suspend_prepare(struct device * dev)10568 int ufshcd_suspend_prepare(struct device *dev)
10569 {
10570 	return __ufshcd_suspend_prepare(dev, true);
10571 }
10572 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10573 
10574 #ifdef CONFIG_PM_SLEEP
ufshcd_wl_poweroff(struct device * dev)10575 static int ufshcd_wl_poweroff(struct device *dev)
10576 {
10577 	struct scsi_device *sdev = to_scsi_device(dev);
10578 	struct ufs_hba *hba = shost_priv(sdev->host);
10579 
10580 	__ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10581 	return 0;
10582 }
10583 #endif
10584 
ufshcd_wl_probe(struct device * dev)10585 static int ufshcd_wl_probe(struct device *dev)
10586 {
10587 	struct scsi_device *sdev = to_scsi_device(dev);
10588 
10589 	if (!is_device_wlun(sdev))
10590 		return -ENODEV;
10591 
10592 	blk_pm_runtime_init(sdev->request_queue, dev);
10593 	pm_runtime_set_autosuspend_delay(dev, 0);
10594 	pm_runtime_allow(dev);
10595 
10596 	return  0;
10597 }
10598 
ufshcd_wl_remove(struct device * dev)10599 static int ufshcd_wl_remove(struct device *dev)
10600 {
10601 	pm_runtime_forbid(dev);
10602 	return 0;
10603 }
10604 
10605 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10606 #ifdef CONFIG_PM_SLEEP
10607 	.suspend = ufshcd_wl_suspend,
10608 	.resume = ufshcd_wl_resume,
10609 	.freeze = ufshcd_wl_suspend,
10610 	.thaw = ufshcd_wl_resume,
10611 	.poweroff = ufshcd_wl_poweroff,
10612 	.restore = ufshcd_wl_resume,
10613 #endif
10614 	SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10615 };
10616 
ufshcd_check_header_layout(void)10617 static void ufshcd_check_header_layout(void)
10618 {
10619 	/*
10620 	 * gcc compilers before version 10 cannot do constant-folding for
10621 	 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and
10622 	 * before.
10623 	 */
10624 	if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000)
10625 		return;
10626 
10627 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10628 				.cci = 3})[0] != 3);
10629 
10630 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10631 				.ehs_length = 2})[1] != 2);
10632 
10633 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10634 				.enable_crypto = 1})[2]
10635 		     != 0x80);
10636 
10637 	BUILD_BUG_ON((((u8 *)&(struct request_desc_header){
10638 					.command_type = 5,
10639 					.data_direction = 3,
10640 					.interrupt = 1,
10641 				})[3]) != ((5 << 4) | (3 << 1) | 1));
10642 
10643 	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10644 				.dunl = cpu_to_le32(0xdeadbeef)})[1] !=
10645 		cpu_to_le32(0xdeadbeef));
10646 
10647 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10648 				.ocs = 4})[8] != 4);
10649 
10650 	BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10651 				.cds = 5})[9] != 5);
10652 
10653 	BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10654 				.dunu = cpu_to_le32(0xbadcafe)})[3] !=
10655 		cpu_to_le32(0xbadcafe));
10656 
10657 	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10658 			     .iid = 0xf })[4] != 0xf0);
10659 
10660 	BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10661 			     .command_set_type = 0xf })[4] != 0xf);
10662 }
10663 
10664 /*
10665  * ufs_dev_wlun_template - describes ufs device wlun
10666  * ufs-device wlun - used to send pm commands
10667  * All luns are consumers of ufs-device wlun.
10668  *
10669  * Currently, no sd driver is present for wluns.
10670  * Hence the no specific pm operations are performed.
10671  * With ufs design, SSU should be sent to ufs-device wlun.
10672  * Hence register a scsi driver for ufs wluns only.
10673  */
10674 static struct scsi_driver ufs_dev_wlun_template = {
10675 	.gendrv = {
10676 		.name = "ufs_device_wlun",
10677 		.owner = THIS_MODULE,
10678 		.probe = ufshcd_wl_probe,
10679 		.remove = ufshcd_wl_remove,
10680 		.pm = &ufshcd_wl_pm_ops,
10681 		.shutdown = ufshcd_wl_shutdown,
10682 	},
10683 };
10684 
ufshcd_core_init(void)10685 static int __init ufshcd_core_init(void)
10686 {
10687 	int ret;
10688 
10689 	ufshcd_check_header_layout();
10690 
10691 	ufs_debugfs_init();
10692 
10693 	ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10694 	if (ret)
10695 		ufs_debugfs_exit();
10696 	return ret;
10697 }
10698 
ufshcd_core_exit(void)10699 static void __exit ufshcd_core_exit(void)
10700 {
10701 	ufs_debugfs_exit();
10702 	scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
10703 }
10704 
10705 module_init(ufshcd_core_init);
10706 module_exit(ufshcd_core_exit);
10707 
10708 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10709 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
10710 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
10711 MODULE_SOFTDEP("pre: governor_simpleondemand");
10712 MODULE_LICENSE("GPL");
10713