xref: /openbmc/qemu/include/hw/ppc/spapr_xive.h (revision aadac5b3)
1 /*
2  * QEMU PowerPC sPAPR XIVE interrupt controller model
3  *
4  * Copyright (c) 2017-2018, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #ifndef PPC_SPAPR_XIVE_H
11 #define PPC_SPAPR_XIVE_H
12 
13 #include "hw/ppc/spapr_irq.h"
14 #include "hw/ppc/xive.h"
15 
16 #define TYPE_SPAPR_XIVE "spapr-xive"
17 #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
18 #define SPAPR_XIVE_CLASS(klass)                                         \
19     OBJECT_CLASS_CHECK(SpaprXiveClass, (klass), TYPE_SPAPR_XIVE)
20 #define SPAPR_XIVE_GET_CLASS(obj)                               \
21     OBJECT_GET_CLASS(SpaprXiveClass, (obj), TYPE_SPAPR_XIVE)
22 
23 typedef struct SpaprXive {
24     XiveRouter    parent;
25 
26     /* Internal interrupt source for IPIs and virtual devices */
27     XiveSource    source;
28     hwaddr        vc_base;
29 
30     /* END ESB MMIOs */
31     XiveENDSource end_source;
32     hwaddr        end_base;
33 
34     /* DT */
35     gchar *nodename;
36 
37     /* Routing table */
38     XiveEAS       *eat;
39     uint32_t      nr_irqs;
40     XiveEND       *endt;
41     uint32_t      nr_ends;
42 
43     /* TIMA mapping address */
44     hwaddr        tm_base;
45     MemoryRegion  tm_mmio;
46 
47     /* KVM support */
48     int           fd;
49     void          *tm_mmap;
50     MemoryRegion  tm_mmio_kvm;
51     VMChangeStateEntry *change;
52 
53     uint8_t       hv_prio;
54 } SpaprXive;
55 
56 typedef struct SpaprXiveClass {
57     XiveRouterClass parent;
58 
59     DeviceRealize parent_realize;
60 } SpaprXiveClass;
61 
62 /*
63  * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
64  * to the controller block id value. It can nevertheless be changed
65  * for testing purpose.
66  */
67 #define SPAPR_XIVE_BLOCK_ID 0x0
68 
69 struct SpaprMachineState;
70 void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
71 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
72 void spapr_xive_map_mmio(SpaprXive *xive);
73 
74 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,
75                              uint32_t *out_server, uint8_t *out_prio);
76 
77 /*
78  * KVM XIVE device helpers
79  */
80 int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
81                         Error **errp);
82 void kvmppc_xive_disconnect(SpaprInterruptController *intc);
83 void kvmppc_xive_reset(SpaprXive *xive, Error **errp);
84 int kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
85                                   Error **errp);
86 void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp);
87 uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
88                             uint64_t data, bool write);
89 int kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,
90                                  uint32_t end_idx, XiveEND *end,
91                                  Error **errp);
92 int kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,
93                                  uint32_t end_idx, XiveEND *end,
94                                  Error **errp);
95 void kvmppc_xive_synchronize_state(SpaprXive *xive, Error **errp);
96 int kvmppc_xive_pre_save(SpaprXive *xive);
97 int kvmppc_xive_post_load(SpaprXive *xive, int version_id);
98 
99 #endif /* PPC_SPAPR_XIVE_H */
100