1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h> 13#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sd_emmc_b; /* SD card */ 23 mmc1 = &sd_emmc_c; /* eMMC */ 24 mmc2 = &sd_emmc_a; /* SDIO */ 25 }; 26 27 chosen { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 simplefb_cvbs: framebuffer-cvbs { 33 compatible = "amlogic,simple-framebuffer", 34 "simple-framebuffer"; 35 amlogic,pipeline = "vpu-cvbs"; 36 clocks = <&clkc CLKID_HDMI>, 37 <&clkc CLKID_HTX_PCLK>, 38 <&clkc CLKID_VPU_INTR>; 39 status = "disabled"; 40 }; 41 42 simplefb_hdmi: framebuffer-hdmi { 43 compatible = "amlogic,simple-framebuffer", 44 "simple-framebuffer"; 45 amlogic,pipeline = "vpu-hdmi"; 46 clocks = <&clkc CLKID_HDMI>, 47 <&clkc CLKID_HTX_PCLK>, 48 <&clkc CLKID_VPU_INTR>; 49 status = "disabled"; 50 }; 51 }; 52 53 efuse: efuse { 54 compatible = "amlogic,meson-gxbb-efuse"; 55 clocks = <&clkc CLKID_EFUSE>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 read-only; 59 secure-monitor = <&sm>; 60 }; 61 62 gpu_opp_table: opp-table-gpu { 63 compatible = "operating-points-v2"; 64 65 opp-124999998 { 66 opp-hz = /bits/ 64 <124999998>; 67 opp-microvolt = <800000>; 68 }; 69 opp-249999996 { 70 opp-hz = /bits/ 64 <249999996>; 71 opp-microvolt = <800000>; 72 }; 73 opp-285714281 { 74 opp-hz = /bits/ 64 <285714281>; 75 opp-microvolt = <800000>; 76 }; 77 opp-399999994 { 78 opp-hz = /bits/ 64 <399999994>; 79 opp-microvolt = <800000>; 80 }; 81 opp-499999992 { 82 opp-hz = /bits/ 64 <499999992>; 83 opp-microvolt = <800000>; 84 }; 85 opp-666666656 { 86 opp-hz = /bits/ 64 <666666656>; 87 opp-microvolt = <800000>; 88 }; 89 opp-799999987 { 90 opp-hz = /bits/ 64 <799999987>; 91 opp-microvolt = <800000>; 92 }; 93 }; 94 95 psci { 96 compatible = "arm,psci-1.0"; 97 method = "smc"; 98 }; 99 100 reserved-memory { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 106 secmon_reserved: secmon@5000000 { 107 reg = <0x0 0x05000000 0x0 0x300000>; 108 no-map; 109 }; 110 111 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 112 secmon_reserved_bl32: secmon@5300000 { 113 reg = <0x0 0x05300000 0x0 0x2000000>; 114 no-map; 115 }; 116 117 linux,cma { 118 compatible = "shared-dma-pool"; 119 reusable; 120 size = <0x0 0x10000000>; 121 alignment = <0x0 0x400000>; 122 linux,cma-default; 123 }; 124 }; 125 126 sm: secure-monitor { 127 compatible = "amlogic,meson-gxbb-sm"; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 pcie: pcie@fc000000 { 137 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 138 reg = <0x0 0xfc000000 0x0 0x400000>, 139 <0x0 0xff648000 0x0 0x2000>, 140 <0x0 0xfc400000 0x0 0x200000>; 141 reg-names = "elbi", "cfg", "config"; 142 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 143 #interrupt-cells = <1>; 144 interrupt-map-mask = <0 0 0 0>; 145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146 bus-range = <0x0 0xff>; 147 #address-cells = <3>; 148 #size-cells = <2>; 149 device_type = "pci"; 150 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 151 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 152 153 clocks = <&clkc CLKID_PCIE_PHY 154 &clkc CLKID_PCIE_COMB 155 &clkc CLKID_PCIE_PLL>; 156 clock-names = "general", 157 "pclk", 158 "port"; 159 resets = <&reset RESET_PCIE_CTRL_A>, 160 <&reset RESET_PCIE_APB>; 161 reset-names = "port", 162 "apb"; 163 num-lanes = <1>; 164 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 165 phy-names = "pcie"; 166 status = "disabled"; 167 }; 168 169 ethmac: ethernet@ff3f0000 { 170 compatible = "amlogic,meson-g12a-dwmac", 171 "snps,dwmac-3.70a", 172 "snps,dwmac"; 173 reg = <0x0 0xff3f0000 0x0 0x10000>, 174 <0x0 0xff634540 0x0 0x8>; 175 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "macirq"; 177 clocks = <&clkc CLKID_ETH>, 178 <&clkc CLKID_FCLK_DIV2>, 179 <&clkc CLKID_MPLL2>, 180 <&clkc CLKID_FCLK_DIV2>; 181 clock-names = "stmmaceth", "clkin0", "clkin1", 182 "timing-adjustment"; 183 rx-fifo-depth = <4096>; 184 tx-fifo-depth = <2048>; 185 status = "disabled"; 186 187 mdio0: mdio { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 compatible = "snps,dwmac-mdio"; 191 }; 192 }; 193 194 apb: bus@ff600000 { 195 compatible = "simple-bus"; 196 reg = <0x0 0xff600000 0x0 0x200000>; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 200 201 hdmi_tx: hdmi-tx@0 { 202 compatible = "amlogic,meson-g12a-dw-hdmi"; 203 reg = <0x0 0x0 0x0 0x10000>; 204 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 205 resets = <&reset RESET_HDMITX_CAPB3>, 206 <&reset RESET_HDMITX_PHY>, 207 <&reset RESET_HDMITX>; 208 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 209 clocks = <&clkc CLKID_HDMI>, 210 <&clkc CLKID_HTX_PCLK>, 211 <&clkc CLKID_VPU_INTR>; 212 clock-names = "isfr", "iahb", "venci"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 #sound-dai-cells = <0>; 216 status = "disabled"; 217 218 assigned-clocks = <&clkc CLKID_HDMI_SEL>, 219 <&clkc CLKID_HDMI>; 220 assigned-clock-parents = <&xtal>, <0>; 221 assigned-clock-rates = <0>, <24000000>; 222 223 /* VPU VENC Input */ 224 hdmi_tx_venc_port: port@0 { 225 reg = <0>; 226 227 hdmi_tx_in: endpoint { 228 remote-endpoint = <&hdmi_tx_out>; 229 }; 230 }; 231 232 /* TMDS Output */ 233 hdmi_tx_tmds_port: port@1 { 234 reg = <1>; 235 }; 236 }; 237 238 apb_efuse: bus@30000 { 239 compatible = "simple-bus"; 240 reg = <0x0 0x30000 0x0 0x2000>; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 244 245 hwrng: rng@218 { 246 compatible = "amlogic,meson-rng"; 247 reg = <0x0 0x218 0x0 0x4>; 248 clocks = <&clkc CLKID_RNG0>; 249 clock-names = "core"; 250 }; 251 }; 252 253 acodec: audio-controller@32000 { 254 compatible = "amlogic,t9015"; 255 reg = <0x0 0x32000 0x0 0x14>; 256 #sound-dai-cells = <0>; 257 sound-name-prefix = "ACODEC"; 258 clocks = <&clkc CLKID_AUDIO_CODEC>; 259 clock-names = "pclk"; 260 resets = <&reset RESET_AUDIO_CODEC>; 261 status = "disabled"; 262 }; 263 264 periphs: bus@34400 { 265 compatible = "simple-bus"; 266 reg = <0x0 0x34400 0x0 0x400>; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 270 271 periphs_pinctrl: pinctrl@40 { 272 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 gpio: bank@40 { 278 reg = <0x0 0x40 0x0 0x4c>, 279 <0x0 0xe8 0x0 0x18>, 280 <0x0 0x120 0x0 0x18>, 281 <0x0 0x2c0 0x0 0x40>, 282 <0x0 0x340 0x0 0x1c>; 283 reg-names = "gpio", 284 "pull", 285 "pull-enable", 286 "mux", 287 "ds"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 gpio-ranges = <&periphs_pinctrl 0 0 86>; 291 }; 292 293 cec_ao_a_h_pins: cec_ao_a_h { 294 mux { 295 groups = "cec_ao_a_h"; 296 function = "cec_ao_a_h"; 297 bias-disable; 298 }; 299 }; 300 301 cec_ao_b_h_pins: cec_ao_b_h { 302 mux { 303 groups = "cec_ao_b_h"; 304 function = "cec_ao_b_h"; 305 bias-disable; 306 }; 307 }; 308 309 emmc_ctrl_pins: emmc-ctrl { 310 mux-0 { 311 groups = "emmc_cmd"; 312 function = "emmc"; 313 bias-pull-up; 314 drive-strength-microamp = <4000>; 315 }; 316 317 mux-1 { 318 groups = "emmc_clk"; 319 function = "emmc"; 320 bias-disable; 321 drive-strength-microamp = <4000>; 322 }; 323 }; 324 325 emmc_data_4b_pins: emmc-data-4b { 326 mux-0 { 327 groups = "emmc_nand_d0", 328 "emmc_nand_d1", 329 "emmc_nand_d2", 330 "emmc_nand_d3"; 331 function = "emmc"; 332 bias-pull-up; 333 drive-strength-microamp = <4000>; 334 }; 335 }; 336 337 emmc_data_8b_pins: emmc-data-8b { 338 mux-0 { 339 groups = "emmc_nand_d0", 340 "emmc_nand_d1", 341 "emmc_nand_d2", 342 "emmc_nand_d3", 343 "emmc_nand_d4", 344 "emmc_nand_d5", 345 "emmc_nand_d6", 346 "emmc_nand_d7"; 347 function = "emmc"; 348 bias-pull-up; 349 drive-strength-microamp = <4000>; 350 }; 351 }; 352 353 emmc_ds_pins: emmc-ds { 354 mux { 355 groups = "emmc_nand_ds"; 356 function = "emmc"; 357 bias-pull-down; 358 drive-strength-microamp = <4000>; 359 }; 360 }; 361 362 emmc_clk_gate_pins: emmc_clk_gate { 363 mux { 364 groups = "BOOT_8"; 365 function = "gpio_periphs"; 366 bias-pull-down; 367 drive-strength-microamp = <4000>; 368 }; 369 }; 370 371 hdmitx_ddc_pins: hdmitx_ddc { 372 mux { 373 groups = "hdmitx_sda", 374 "hdmitx_sck"; 375 function = "hdmitx"; 376 bias-disable; 377 drive-strength-microamp = <4000>; 378 }; 379 }; 380 381 hdmitx_hpd_pins: hdmitx_hpd { 382 mux { 383 groups = "hdmitx_hpd_in"; 384 function = "hdmitx"; 385 bias-disable; 386 }; 387 }; 388 389 390 i2c0_sda_c_pins: i2c0-sda-c { 391 mux { 392 groups = "i2c0_sda_c"; 393 function = "i2c0"; 394 bias-disable; 395 drive-strength-microamp = <3000>; 396 397 }; 398 }; 399 400 i2c0_sck_c_pins: i2c0-sck-c { 401 mux { 402 groups = "i2c0_sck_c"; 403 function = "i2c0"; 404 bias-disable; 405 drive-strength-microamp = <3000>; 406 }; 407 }; 408 409 i2c0_sda_z0_pins: i2c0-sda-z0 { 410 mux { 411 groups = "i2c0_sda_z0"; 412 function = "i2c0"; 413 bias-disable; 414 drive-strength-microamp = <3000>; 415 }; 416 }; 417 418 i2c0_sck_z1_pins: i2c0-sck-z1 { 419 mux { 420 groups = "i2c0_sck_z1"; 421 function = "i2c0"; 422 bias-disable; 423 drive-strength-microamp = <3000>; 424 }; 425 }; 426 427 i2c0_sda_z7_pins: i2c0-sda-z7 { 428 mux { 429 groups = "i2c0_sda_z7"; 430 function = "i2c0"; 431 bias-disable; 432 drive-strength-microamp = <3000>; 433 }; 434 }; 435 436 i2c0_sda_z8_pins: i2c0-sda-z8 { 437 mux { 438 groups = "i2c0_sda_z8"; 439 function = "i2c0"; 440 bias-disable; 441 drive-strength-microamp = <3000>; 442 }; 443 }; 444 445 i2c1_sda_x_pins: i2c1-sda-x { 446 mux { 447 groups = "i2c1_sda_x"; 448 function = "i2c1"; 449 bias-disable; 450 drive-strength-microamp = <3000>; 451 }; 452 }; 453 454 i2c1_sck_x_pins: i2c1-sck-x { 455 mux { 456 groups = "i2c1_sck_x"; 457 function = "i2c1"; 458 bias-disable; 459 drive-strength-microamp = <3000>; 460 }; 461 }; 462 463 i2c1_sda_h2_pins: i2c1-sda-h2 { 464 mux { 465 groups = "i2c1_sda_h2"; 466 function = "i2c1"; 467 bias-disable; 468 drive-strength-microamp = <3000>; 469 }; 470 }; 471 472 i2c1_sck_h3_pins: i2c1-sck-h3 { 473 mux { 474 groups = "i2c1_sck_h3"; 475 function = "i2c1"; 476 bias-disable; 477 drive-strength-microamp = <3000>; 478 }; 479 }; 480 481 i2c1_sda_h6_pins: i2c1-sda-h6 { 482 mux { 483 groups = "i2c1_sda_h6"; 484 function = "i2c1"; 485 bias-disable; 486 drive-strength-microamp = <3000>; 487 }; 488 }; 489 490 i2c1_sck_h7_pins: i2c1-sck-h7 { 491 mux { 492 groups = "i2c1_sck_h7"; 493 function = "i2c1"; 494 bias-disable; 495 drive-strength-microamp = <3000>; 496 }; 497 }; 498 499 i2c2_sda_x_pins: i2c2-sda-x { 500 mux { 501 groups = "i2c2_sda_x"; 502 function = "i2c2"; 503 bias-disable; 504 drive-strength-microamp = <3000>; 505 }; 506 }; 507 508 i2c2_sck_x_pins: i2c2-sck-x { 509 mux { 510 groups = "i2c2_sck_x"; 511 function = "i2c2"; 512 bias-disable; 513 drive-strength-microamp = <3000>; 514 }; 515 }; 516 517 i2c2_sda_z_pins: i2c2-sda-z { 518 mux { 519 groups = "i2c2_sda_z"; 520 function = "i2c2"; 521 bias-disable; 522 drive-strength-microamp = <3000>; 523 }; 524 }; 525 526 i2c2_sck_z_pins: i2c2-sck-z { 527 mux { 528 groups = "i2c2_sck_z"; 529 function = "i2c2"; 530 bias-disable; 531 drive-strength-microamp = <3000>; 532 }; 533 }; 534 535 i2c3_sda_h_pins: i2c3-sda-h { 536 mux { 537 groups = "i2c3_sda_h"; 538 function = "i2c3"; 539 bias-disable; 540 drive-strength-microamp = <3000>; 541 }; 542 }; 543 544 i2c3_sck_h_pins: i2c3-sck-h { 545 mux { 546 groups = "i2c3_sck_h"; 547 function = "i2c3"; 548 bias-disable; 549 drive-strength-microamp = <3000>; 550 }; 551 }; 552 553 i2c3_sda_a_pins: i2c3-sda-a { 554 mux { 555 groups = "i2c3_sda_a"; 556 function = "i2c3"; 557 bias-disable; 558 drive-strength-microamp = <3000>; 559 }; 560 }; 561 562 i2c3_sck_a_pins: i2c3-sck-a { 563 mux { 564 groups = "i2c3_sck_a"; 565 function = "i2c3"; 566 bias-disable; 567 drive-strength-microamp = <3000>; 568 }; 569 }; 570 571 mclk0_a_pins: mclk0-a { 572 mux { 573 groups = "mclk0_a"; 574 function = "mclk0"; 575 bias-disable; 576 drive-strength-microamp = <3000>; 577 }; 578 }; 579 580 mclk1_a_pins: mclk1-a { 581 mux { 582 groups = "mclk1_a"; 583 function = "mclk1"; 584 bias-disable; 585 drive-strength-microamp = <3000>; 586 }; 587 }; 588 589 mclk1_x_pins: mclk1-x { 590 mux { 591 groups = "mclk1_x"; 592 function = "mclk1"; 593 bias-disable; 594 drive-strength-microamp = <3000>; 595 }; 596 }; 597 598 mclk1_z_pins: mclk1-z { 599 mux { 600 groups = "mclk1_z"; 601 function = "mclk1"; 602 bias-disable; 603 drive-strength-microamp = <3000>; 604 }; 605 }; 606 607 nor_pins: nor { 608 mux { 609 groups = "nor_d", 610 "nor_q", 611 "nor_c", 612 "nor_cs"; 613 function = "nor"; 614 bias-disable; 615 }; 616 }; 617 618 pdm_din0_a_pins: pdm-din0-a { 619 mux { 620 groups = "pdm_din0_a"; 621 function = "pdm"; 622 bias-disable; 623 }; 624 }; 625 626 pdm_din0_c_pins: pdm-din0-c { 627 mux { 628 groups = "pdm_din0_c"; 629 function = "pdm"; 630 bias-disable; 631 }; 632 }; 633 634 pdm_din0_x_pins: pdm-din0-x { 635 mux { 636 groups = "pdm_din0_x"; 637 function = "pdm"; 638 bias-disable; 639 }; 640 }; 641 642 pdm_din0_z_pins: pdm-din0-z { 643 mux { 644 groups = "pdm_din0_z"; 645 function = "pdm"; 646 bias-disable; 647 }; 648 }; 649 650 pdm_din1_a_pins: pdm-din1-a { 651 mux { 652 groups = "pdm_din1_a"; 653 function = "pdm"; 654 bias-disable; 655 }; 656 }; 657 658 pdm_din1_c_pins: pdm-din1-c { 659 mux { 660 groups = "pdm_din1_c"; 661 function = "pdm"; 662 bias-disable; 663 }; 664 }; 665 666 pdm_din1_x_pins: pdm-din1-x { 667 mux { 668 groups = "pdm_din1_x"; 669 function = "pdm"; 670 bias-disable; 671 }; 672 }; 673 674 pdm_din1_z_pins: pdm-din1-z { 675 mux { 676 groups = "pdm_din1_z"; 677 function = "pdm"; 678 bias-disable; 679 }; 680 }; 681 682 pdm_din2_a_pins: pdm-din2-a { 683 mux { 684 groups = "pdm_din2_a"; 685 function = "pdm"; 686 bias-disable; 687 }; 688 }; 689 690 pdm_din2_c_pins: pdm-din2-c { 691 mux { 692 groups = "pdm_din2_c"; 693 function = "pdm"; 694 bias-disable; 695 }; 696 }; 697 698 pdm_din2_x_pins: pdm-din2-x { 699 mux { 700 groups = "pdm_din2_x"; 701 function = "pdm"; 702 bias-disable; 703 }; 704 }; 705 706 pdm_din2_z_pins: pdm-din2-z { 707 mux { 708 groups = "pdm_din2_z"; 709 function = "pdm"; 710 bias-disable; 711 }; 712 }; 713 714 pdm_din3_a_pins: pdm-din3-a { 715 mux { 716 groups = "pdm_din3_a"; 717 function = "pdm"; 718 bias-disable; 719 }; 720 }; 721 722 pdm_din3_c_pins: pdm-din3-c { 723 mux { 724 groups = "pdm_din3_c"; 725 function = "pdm"; 726 bias-disable; 727 }; 728 }; 729 730 pdm_din3_x_pins: pdm-din3-x { 731 mux { 732 groups = "pdm_din3_x"; 733 function = "pdm"; 734 bias-disable; 735 }; 736 }; 737 738 pdm_din3_z_pins: pdm-din3-z { 739 mux { 740 groups = "pdm_din3_z"; 741 function = "pdm"; 742 bias-disable; 743 }; 744 }; 745 746 pdm_dclk_a_pins: pdm-dclk-a { 747 mux { 748 groups = "pdm_dclk_a"; 749 function = "pdm"; 750 bias-disable; 751 drive-strength-microamp = <500>; 752 }; 753 }; 754 755 pdm_dclk_c_pins: pdm-dclk-c { 756 mux { 757 groups = "pdm_dclk_c"; 758 function = "pdm"; 759 bias-disable; 760 drive-strength-microamp = <500>; 761 }; 762 }; 763 764 pdm_dclk_x_pins: pdm-dclk-x { 765 mux { 766 groups = "pdm_dclk_x"; 767 function = "pdm"; 768 bias-disable; 769 drive-strength-microamp = <500>; 770 }; 771 }; 772 773 pdm_dclk_z_pins: pdm-dclk-z { 774 mux { 775 groups = "pdm_dclk_z"; 776 function = "pdm"; 777 bias-disable; 778 drive-strength-microamp = <500>; 779 }; 780 }; 781 782 pwm_a_pins: pwm-a { 783 mux { 784 groups = "pwm_a"; 785 function = "pwm_a"; 786 bias-disable; 787 }; 788 }; 789 790 pwm_b_x7_pins: pwm-b-x7 { 791 mux { 792 groups = "pwm_b_x7"; 793 function = "pwm_b"; 794 bias-disable; 795 }; 796 }; 797 798 pwm_b_x19_pins: pwm-b-x19 { 799 mux { 800 groups = "pwm_b_x19"; 801 function = "pwm_b"; 802 bias-disable; 803 }; 804 }; 805 806 pwm_c_c_pins: pwm-c-c { 807 mux { 808 groups = "pwm_c_c"; 809 function = "pwm_c"; 810 bias-disable; 811 }; 812 }; 813 814 pwm_c_x5_pins: pwm-c-x5 { 815 mux { 816 groups = "pwm_c_x5"; 817 function = "pwm_c"; 818 bias-disable; 819 }; 820 }; 821 822 pwm_c_x8_pins: pwm-c-x8 { 823 mux { 824 groups = "pwm_c_x8"; 825 function = "pwm_c"; 826 bias-disable; 827 }; 828 }; 829 830 pwm_d_x3_pins: pwm-d-x3 { 831 mux { 832 groups = "pwm_d_x3"; 833 function = "pwm_d"; 834 bias-disable; 835 }; 836 }; 837 838 pwm_d_x6_pins: pwm-d-x6 { 839 mux { 840 groups = "pwm_d_x6"; 841 function = "pwm_d"; 842 bias-disable; 843 }; 844 }; 845 846 pwm_e_pins: pwm-e { 847 mux { 848 groups = "pwm_e"; 849 function = "pwm_e"; 850 bias-disable; 851 }; 852 }; 853 854 pwm_f_z_pins: pwm-f-z { 855 mux { 856 groups = "pwm_f_z"; 857 function = "pwm_f"; 858 bias-disable; 859 }; 860 }; 861 862 pwm_f_a_pins: pwm-f-a { 863 mux { 864 groups = "pwm_f_a"; 865 function = "pwm_f"; 866 bias-disable; 867 }; 868 }; 869 870 pwm_f_x_pins: pwm-f-x { 871 mux { 872 groups = "pwm_f_x"; 873 function = "pwm_f"; 874 bias-disable; 875 }; 876 }; 877 878 pwm_f_h_pins: pwm-f-h { 879 mux { 880 groups = "pwm_f_h"; 881 function = "pwm_f"; 882 bias-disable; 883 }; 884 }; 885 886 sdcard_c_pins: sdcard_c { 887 mux-0 { 888 groups = "sdcard_d0_c", 889 "sdcard_d1_c", 890 "sdcard_d2_c", 891 "sdcard_d3_c", 892 "sdcard_cmd_c"; 893 function = "sdcard"; 894 bias-pull-up; 895 drive-strength-microamp = <4000>; 896 }; 897 898 mux-1 { 899 groups = "sdcard_clk_c"; 900 function = "sdcard"; 901 bias-disable; 902 drive-strength-microamp = <4000>; 903 }; 904 }; 905 906 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 907 mux { 908 groups = "GPIOC_4"; 909 function = "gpio_periphs"; 910 bias-pull-down; 911 drive-strength-microamp = <4000>; 912 }; 913 }; 914 915 sdcard_z_pins: sdcard_z { 916 mux-0 { 917 groups = "sdcard_d0_z", 918 "sdcard_d1_z", 919 "sdcard_d2_z", 920 "sdcard_d3_z", 921 "sdcard_cmd_z"; 922 function = "sdcard"; 923 bias-pull-up; 924 drive-strength-microamp = <4000>; 925 }; 926 927 mux-1 { 928 groups = "sdcard_clk_z"; 929 function = "sdcard"; 930 bias-disable; 931 drive-strength-microamp = <4000>; 932 }; 933 }; 934 935 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 936 mux { 937 groups = "GPIOZ_6"; 938 function = "gpio_periphs"; 939 bias-pull-down; 940 drive-strength-microamp = <4000>; 941 }; 942 }; 943 944 sdio_pins: sdio { 945 mux { 946 groups = "sdio_d0", 947 "sdio_d1", 948 "sdio_d2", 949 "sdio_d3", 950 "sdio_clk", 951 "sdio_cmd"; 952 function = "sdio"; 953 bias-disable; 954 drive-strength-microamp = <4000>; 955 }; 956 }; 957 958 sdio_clk_gate_pins: sdio_clk_gate { 959 mux { 960 groups = "GPIOX_4"; 961 function = "gpio_periphs"; 962 bias-pull-down; 963 drive-strength-microamp = <4000>; 964 }; 965 }; 966 967 spdif_in_a10_pins: spdif-in-a10 { 968 mux { 969 groups = "spdif_in_a10"; 970 function = "spdif_in"; 971 bias-disable; 972 }; 973 }; 974 975 spdif_in_a12_pins: spdif-in-a12 { 976 mux { 977 groups = "spdif_in_a12"; 978 function = "spdif_in"; 979 bias-disable; 980 }; 981 }; 982 983 spdif_in_h_pins: spdif-in-h { 984 mux { 985 groups = "spdif_in_h"; 986 function = "spdif_in"; 987 bias-disable; 988 }; 989 }; 990 991 spdif_out_h_pins: spdif-out-h { 992 mux { 993 groups = "spdif_out_h"; 994 function = "spdif_out"; 995 drive-strength-microamp = <500>; 996 bias-disable; 997 }; 998 }; 999 1000 spdif_out_a11_pins: spdif-out-a11 { 1001 mux { 1002 groups = "spdif_out_a11"; 1003 function = "spdif_out"; 1004 drive-strength-microamp = <500>; 1005 bias-disable; 1006 }; 1007 }; 1008 1009 spdif_out_a13_pins: spdif-out-a13 { 1010 mux { 1011 groups = "spdif_out_a13"; 1012 function = "spdif_out"; 1013 drive-strength-microamp = <500>; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 spicc0_x_pins: spicc0-x { 1019 mux { 1020 groups = "spi0_mosi_x", 1021 "spi0_miso_x", 1022 "spi0_clk_x"; 1023 function = "spi0"; 1024 drive-strength-microamp = <4000>; 1025 bias-disable; 1026 }; 1027 }; 1028 1029 spicc0_ss0_x_pins: spicc0-ss0-x { 1030 mux { 1031 groups = "spi0_ss0_x"; 1032 function = "spi0"; 1033 drive-strength-microamp = <4000>; 1034 bias-disable; 1035 }; 1036 }; 1037 1038 spicc0_c_pins: spicc0-c { 1039 mux { 1040 groups = "spi0_mosi_c", 1041 "spi0_miso_c", 1042 "spi0_ss0_c", 1043 "spi0_clk_c"; 1044 function = "spi0"; 1045 drive-strength-microamp = <4000>; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 spicc1_pins: spicc1 { 1051 mux { 1052 groups = "spi1_mosi", 1053 "spi1_miso", 1054 "spi1_clk"; 1055 function = "spi1"; 1056 drive-strength-microamp = <4000>; 1057 }; 1058 }; 1059 1060 spicc1_ss0_pins: spicc1-ss0 { 1061 mux { 1062 groups = "spi1_ss0"; 1063 function = "spi1"; 1064 drive-strength-microamp = <4000>; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 tdm_a_din0_pins: tdm-a-din0 { 1070 mux { 1071 groups = "tdm_a_din0"; 1072 function = "tdm_a"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 1078 tdm_a_din1_pins: tdm-a-din1 { 1079 mux { 1080 groups = "tdm_a_din1"; 1081 function = "tdm_a"; 1082 bias-disable; 1083 }; 1084 }; 1085 1086 tdm_a_dout0_pins: tdm-a-dout0 { 1087 mux { 1088 groups = "tdm_a_dout0"; 1089 function = "tdm_a"; 1090 bias-disable; 1091 drive-strength-microamp = <3000>; 1092 }; 1093 }; 1094 1095 tdm_a_dout1_pins: tdm-a-dout1 { 1096 mux { 1097 groups = "tdm_a_dout1"; 1098 function = "tdm_a"; 1099 bias-disable; 1100 drive-strength-microamp = <3000>; 1101 }; 1102 }; 1103 1104 tdm_a_fs_pins: tdm-a-fs { 1105 mux { 1106 groups = "tdm_a_fs"; 1107 function = "tdm_a"; 1108 bias-disable; 1109 drive-strength-microamp = <3000>; 1110 }; 1111 }; 1112 1113 tdm_a_sclk_pins: tdm-a-sclk { 1114 mux { 1115 groups = "tdm_a_sclk"; 1116 function = "tdm_a"; 1117 bias-disable; 1118 drive-strength-microamp = <3000>; 1119 }; 1120 }; 1121 1122 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1123 mux { 1124 groups = "tdm_a_slv_fs"; 1125 function = "tdm_a"; 1126 bias-disable; 1127 }; 1128 }; 1129 1130 1131 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1132 mux { 1133 groups = "tdm_a_slv_sclk"; 1134 function = "tdm_a"; 1135 bias-disable; 1136 }; 1137 }; 1138 1139 tdm_b_din0_pins: tdm-b-din0 { 1140 mux { 1141 groups = "tdm_b_din0"; 1142 function = "tdm_b"; 1143 bias-disable; 1144 }; 1145 }; 1146 1147 tdm_b_din1_pins: tdm-b-din1 { 1148 mux { 1149 groups = "tdm_b_din1"; 1150 function = "tdm_b"; 1151 bias-disable; 1152 }; 1153 }; 1154 1155 tdm_b_din2_pins: tdm-b-din2 { 1156 mux { 1157 groups = "tdm_b_din2"; 1158 function = "tdm_b"; 1159 bias-disable; 1160 }; 1161 }; 1162 1163 tdm_b_din3_a_pins: tdm-b-din3-a { 1164 mux { 1165 groups = "tdm_b_din3_a"; 1166 function = "tdm_b"; 1167 bias-disable; 1168 }; 1169 }; 1170 1171 tdm_b_din3_h_pins: tdm-b-din3-h { 1172 mux { 1173 groups = "tdm_b_din3_h"; 1174 function = "tdm_b"; 1175 bias-disable; 1176 }; 1177 }; 1178 1179 tdm_b_dout0_pins: tdm-b-dout0 { 1180 mux { 1181 groups = "tdm_b_dout0"; 1182 function = "tdm_b"; 1183 bias-disable; 1184 drive-strength-microamp = <3000>; 1185 }; 1186 }; 1187 1188 tdm_b_dout1_pins: tdm-b-dout1 { 1189 mux { 1190 groups = "tdm_b_dout1"; 1191 function = "tdm_b"; 1192 bias-disable; 1193 drive-strength-microamp = <3000>; 1194 }; 1195 }; 1196 1197 tdm_b_dout2_pins: tdm-b-dout2 { 1198 mux { 1199 groups = "tdm_b_dout2"; 1200 function = "tdm_b"; 1201 bias-disable; 1202 drive-strength-microamp = <3000>; 1203 }; 1204 }; 1205 1206 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1207 mux { 1208 groups = "tdm_b_dout3_a"; 1209 function = "tdm_b"; 1210 bias-disable; 1211 drive-strength-microamp = <3000>; 1212 }; 1213 }; 1214 1215 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1216 mux { 1217 groups = "tdm_b_dout3_h"; 1218 function = "tdm_b"; 1219 bias-disable; 1220 drive-strength-microamp = <3000>; 1221 }; 1222 }; 1223 1224 tdm_b_fs_pins: tdm-b-fs { 1225 mux { 1226 groups = "tdm_b_fs"; 1227 function = "tdm_b"; 1228 bias-disable; 1229 drive-strength-microamp = <3000>; 1230 }; 1231 }; 1232 1233 tdm_b_sclk_pins: tdm-b-sclk { 1234 mux { 1235 groups = "tdm_b_sclk"; 1236 function = "tdm_b"; 1237 bias-disable; 1238 drive-strength-microamp = <3000>; 1239 }; 1240 }; 1241 1242 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1243 mux { 1244 groups = "tdm_b_slv_fs"; 1245 function = "tdm_b"; 1246 bias-disable; 1247 }; 1248 }; 1249 1250 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1251 mux { 1252 groups = "tdm_b_slv_sclk"; 1253 function = "tdm_b"; 1254 bias-disable; 1255 }; 1256 }; 1257 1258 tdm_c_din0_a_pins: tdm-c-din0-a { 1259 mux { 1260 groups = "tdm_c_din0_a"; 1261 function = "tdm_c"; 1262 bias-disable; 1263 }; 1264 }; 1265 1266 tdm_c_din0_z_pins: tdm-c-din0-z { 1267 mux { 1268 groups = "tdm_c_din0_z"; 1269 function = "tdm_c"; 1270 bias-disable; 1271 }; 1272 }; 1273 1274 tdm_c_din1_a_pins: tdm-c-din1-a { 1275 mux { 1276 groups = "tdm_c_din1_a"; 1277 function = "tdm_c"; 1278 bias-disable; 1279 }; 1280 }; 1281 1282 tdm_c_din1_z_pins: tdm-c-din1-z { 1283 mux { 1284 groups = "tdm_c_din1_z"; 1285 function = "tdm_c"; 1286 bias-disable; 1287 }; 1288 }; 1289 1290 tdm_c_din2_a_pins: tdm-c-din2-a { 1291 mux { 1292 groups = "tdm_c_din2_a"; 1293 function = "tdm_c"; 1294 bias-disable; 1295 }; 1296 }; 1297 1298 eth_leds_pins: eth-leds { 1299 mux { 1300 groups = "eth_link_led", 1301 "eth_act_led"; 1302 function = "eth"; 1303 bias-disable; 1304 }; 1305 }; 1306 1307 eth_pins: eth { 1308 mux { 1309 groups = "eth_mdio", 1310 "eth_mdc", 1311 "eth_rgmii_rx_clk", 1312 "eth_rx_dv", 1313 "eth_rxd0", 1314 "eth_rxd1", 1315 "eth_txen", 1316 "eth_txd0", 1317 "eth_txd1"; 1318 function = "eth"; 1319 drive-strength-microamp = <4000>; 1320 bias-disable; 1321 }; 1322 }; 1323 1324 eth_rgmii_pins: eth-rgmii { 1325 mux { 1326 groups = "eth_rxd2_rgmii", 1327 "eth_rxd3_rgmii", 1328 "eth_rgmii_tx_clk", 1329 "eth_txd2_rgmii", 1330 "eth_txd3_rgmii"; 1331 function = "eth"; 1332 drive-strength-microamp = <4000>; 1333 bias-disable; 1334 }; 1335 }; 1336 1337 tdm_c_din2_z_pins: tdm-c-din2-z { 1338 mux { 1339 groups = "tdm_c_din2_z"; 1340 function = "tdm_c"; 1341 bias-disable; 1342 }; 1343 }; 1344 1345 tdm_c_din3_a_pins: tdm-c-din3-a { 1346 mux { 1347 groups = "tdm_c_din3_a"; 1348 function = "tdm_c"; 1349 bias-disable; 1350 }; 1351 }; 1352 1353 tdm_c_din3_z_pins: tdm-c-din3-z { 1354 mux { 1355 groups = "tdm_c_din3_z"; 1356 function = "tdm_c"; 1357 bias-disable; 1358 }; 1359 }; 1360 1361 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1362 mux { 1363 groups = "tdm_c_dout0_a"; 1364 function = "tdm_c"; 1365 bias-disable; 1366 drive-strength-microamp = <3000>; 1367 }; 1368 }; 1369 1370 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1371 mux { 1372 groups = "tdm_c_dout0_z"; 1373 function = "tdm_c"; 1374 bias-disable; 1375 drive-strength-microamp = <3000>; 1376 }; 1377 }; 1378 1379 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1380 mux { 1381 groups = "tdm_c_dout1_a"; 1382 function = "tdm_c"; 1383 bias-disable; 1384 drive-strength-microamp = <3000>; 1385 }; 1386 }; 1387 1388 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1389 mux { 1390 groups = "tdm_c_dout1_z"; 1391 function = "tdm_c"; 1392 bias-disable; 1393 drive-strength-microamp = <3000>; 1394 }; 1395 }; 1396 1397 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1398 mux { 1399 groups = "tdm_c_dout2_a"; 1400 function = "tdm_c"; 1401 bias-disable; 1402 drive-strength-microamp = <3000>; 1403 }; 1404 }; 1405 1406 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1407 mux { 1408 groups = "tdm_c_dout2_z"; 1409 function = "tdm_c"; 1410 bias-disable; 1411 drive-strength-microamp = <3000>; 1412 }; 1413 }; 1414 1415 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1416 mux { 1417 groups = "tdm_c_dout3_a"; 1418 function = "tdm_c"; 1419 bias-disable; 1420 drive-strength-microamp = <3000>; 1421 }; 1422 }; 1423 1424 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1425 mux { 1426 groups = "tdm_c_dout3_z"; 1427 function = "tdm_c"; 1428 bias-disable; 1429 drive-strength-microamp = <3000>; 1430 }; 1431 }; 1432 1433 tdm_c_fs_a_pins: tdm-c-fs-a { 1434 mux { 1435 groups = "tdm_c_fs_a"; 1436 function = "tdm_c"; 1437 bias-disable; 1438 drive-strength-microamp = <3000>; 1439 }; 1440 }; 1441 1442 tdm_c_fs_z_pins: tdm-c-fs-z { 1443 mux { 1444 groups = "tdm_c_fs_z"; 1445 function = "tdm_c"; 1446 bias-disable; 1447 drive-strength-microamp = <3000>; 1448 }; 1449 }; 1450 1451 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1452 mux { 1453 groups = "tdm_c_sclk_a"; 1454 function = "tdm_c"; 1455 bias-disable; 1456 drive-strength-microamp = <3000>; 1457 }; 1458 }; 1459 1460 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1461 mux { 1462 groups = "tdm_c_sclk_z"; 1463 function = "tdm_c"; 1464 bias-disable; 1465 drive-strength-microamp = <3000>; 1466 }; 1467 }; 1468 1469 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1470 mux { 1471 groups = "tdm_c_slv_fs_a"; 1472 function = "tdm_c"; 1473 bias-disable; 1474 }; 1475 }; 1476 1477 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1478 mux { 1479 groups = "tdm_c_slv_fs_z"; 1480 function = "tdm_c"; 1481 bias-disable; 1482 }; 1483 }; 1484 1485 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1486 mux { 1487 groups = "tdm_c_slv_sclk_a"; 1488 function = "tdm_c"; 1489 bias-disable; 1490 }; 1491 }; 1492 1493 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1494 mux { 1495 groups = "tdm_c_slv_sclk_z"; 1496 function = "tdm_c"; 1497 bias-disable; 1498 }; 1499 }; 1500 1501 uart_a_pins: uart-a { 1502 mux { 1503 groups = "uart_a_tx", 1504 "uart_a_rx"; 1505 function = "uart_a"; 1506 bias-disable; 1507 }; 1508 }; 1509 1510 uart_a_cts_rts_pins: uart-a-cts-rts { 1511 mux { 1512 groups = "uart_a_cts", 1513 "uart_a_rts"; 1514 function = "uart_a"; 1515 bias-disable; 1516 }; 1517 }; 1518 1519 uart_b_pins: uart-b { 1520 mux { 1521 groups = "uart_b_tx", 1522 "uart_b_rx"; 1523 function = "uart_b"; 1524 bias-disable; 1525 }; 1526 }; 1527 1528 uart_c_pins: uart-c { 1529 mux { 1530 groups = "uart_c_tx", 1531 "uart_c_rx"; 1532 function = "uart_c"; 1533 bias-disable; 1534 }; 1535 }; 1536 1537 uart_c_cts_rts_pins: uart-c-cts-rts { 1538 mux { 1539 groups = "uart_c_cts", 1540 "uart_c_rts"; 1541 function = "uart_c"; 1542 bias-disable; 1543 }; 1544 }; 1545 }; 1546 }; 1547 1548 cpu_temp: temperature-sensor@34800 { 1549 compatible = "amlogic,g12a-cpu-thermal", 1550 "amlogic,g12a-thermal"; 1551 reg = <0x0 0x34800 0x0 0x50>; 1552 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1553 clocks = <&clkc CLKID_TS>; 1554 #thermal-sensor-cells = <0>; 1555 amlogic,ao-secure = <&sec_AO>; 1556 }; 1557 1558 ddr_temp: temperature-sensor@34c00 { 1559 compatible = "amlogic,g12a-ddr-thermal", 1560 "amlogic,g12a-thermal"; 1561 reg = <0x0 0x34c00 0x0 0x50>; 1562 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1563 clocks = <&clkc CLKID_TS>; 1564 #thermal-sensor-cells = <0>; 1565 amlogic,ao-secure = <&sec_AO>; 1566 }; 1567 1568 usb2_phy0: phy@36000 { 1569 compatible = "amlogic,g12a-usb2-phy"; 1570 reg = <0x0 0x36000 0x0 0x2000>; 1571 clocks = <&xtal>; 1572 clock-names = "xtal"; 1573 resets = <&reset RESET_USB_PHY20>; 1574 reset-names = "phy"; 1575 #phy-cells = <0>; 1576 }; 1577 1578 dmc: bus@38000 { 1579 compatible = "simple-bus"; 1580 #address-cells = <2>; 1581 #size-cells = <2>; 1582 ranges = <0x0 0x0 0x0 0x38000 0x0 0x2000>; 1583 1584 canvas: video-lut@48 { 1585 compatible = "amlogic,canvas"; 1586 reg = <0x0 0x48 0x0 0x14>; 1587 }; 1588 1589 pmu: pmu@80 { 1590 reg = <0x0 0x80 0x0 0x40>, 1591 <0x0 0xc00 0x0 0x40>; 1592 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1593 }; 1594 }; 1595 1596 usb2_phy1: phy@3a000 { 1597 compatible = "amlogic,g12a-usb2-phy"; 1598 reg = <0x0 0x3a000 0x0 0x2000>; 1599 clocks = <&xtal>; 1600 clock-names = "xtal"; 1601 resets = <&reset RESET_USB_PHY21>; 1602 reset-names = "phy"; 1603 #phy-cells = <0>; 1604 }; 1605 1606 hiu: bus@3c000 { 1607 compatible = "simple-bus"; 1608 reg = <0x0 0x3c000 0x0 0x1400>; 1609 #address-cells = <2>; 1610 #size-cells = <2>; 1611 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1612 1613 hhi: system-controller@0 { 1614 compatible = "amlogic,meson-gx-hhi-sysctrl", 1615 "simple-mfd", "syscon"; 1616 reg = <0 0 0 0x400>; 1617 1618 clkc: clock-controller { 1619 compatible = "amlogic,g12a-clkc"; 1620 #clock-cells = <1>; 1621 clocks = <&xtal>; 1622 clock-names = "xtal"; 1623 }; 1624 1625 pwrc: power-controller { 1626 compatible = "amlogic,meson-g12a-pwrc"; 1627 #power-domain-cells = <1>; 1628 amlogic,ao-sysctrl = <&rti>; 1629 resets = <&reset RESET_VIU>, 1630 <&reset RESET_VENC>, 1631 <&reset RESET_VCBUS>, 1632 <&reset RESET_BT656>, 1633 <&reset RESET_RDMA>, 1634 <&reset RESET_VENCI>, 1635 <&reset RESET_VENCP>, 1636 <&reset RESET_VDAC>, 1637 <&reset RESET_VDI6>, 1638 <&reset RESET_VENCL>, 1639 <&reset RESET_VID_LOCK>; 1640 reset-names = "viu", "venc", "vcbus", "bt656", 1641 "rdma", "venci", "vencp", "vdac", 1642 "vdi6", "vencl", "vid_lock"; 1643 clocks = <&clkc CLKID_VPU>, 1644 <&clkc CLKID_VAPB>; 1645 clock-names = "vpu", "vapb"; 1646 /* 1647 * VPU clocking is provided by two identical clock paths 1648 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1649 * free mux to safely change frequency while running. 1650 * Same for VAPB but with a final gate after the glitch free mux. 1651 */ 1652 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1653 <&clkc CLKID_VPU_0>, 1654 <&clkc CLKID_VPU>, /* Glitch free mux */ 1655 <&clkc CLKID_VAPB_0_SEL>, 1656 <&clkc CLKID_VAPB_0>, 1657 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1658 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1659 <0>, /* Do Nothing */ 1660 <&clkc CLKID_VPU_0>, 1661 <&clkc CLKID_FCLK_DIV4>, 1662 <0>, /* Do Nothing */ 1663 <&clkc CLKID_VAPB_0>; 1664 assigned-clock-rates = <0>, /* Do Nothing */ 1665 <666666666>, 1666 <0>, /* Do Nothing */ 1667 <0>, /* Do Nothing */ 1668 <250000000>, 1669 <0>; /* Do Nothing */ 1670 }; 1671 }; 1672 }; 1673 1674 usb3_pcie_phy: phy@46000 { 1675 compatible = "amlogic,g12a-usb3-pcie-phy"; 1676 reg = <0x0 0x46000 0x0 0x2000>; 1677 clocks = <&clkc CLKID_PCIE_PLL>; 1678 clock-names = "ref_clk"; 1679 resets = <&reset RESET_PCIE_PHY>; 1680 reset-names = "phy"; 1681 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1682 assigned-clock-rates = <100000000>; 1683 #phy-cells = <1>; 1684 }; 1685 1686 eth_phy: mdio-multiplexer@4c000 { 1687 compatible = "amlogic,g12a-mdio-mux"; 1688 reg = <0x0 0x4c000 0x0 0xa4>; 1689 clocks = <&clkc CLKID_ETH_PHY>, 1690 <&xtal>, 1691 <&clkc CLKID_MPLL_50M>; 1692 clock-names = "pclk", "clkin0", "clkin1"; 1693 mdio-parent-bus = <&mdio0>; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 ext_mdio: mdio@0 { 1698 reg = <0>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 }; 1702 1703 int_mdio: mdio@1 { 1704 reg = <1>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 1708 internal_ephy: ethernet-phy@8 { 1709 compatible = "ethernet-phy-id0180.3301", 1710 "ethernet-phy-ieee802.3-c22"; 1711 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1712 reg = <8>; 1713 max-speed = <100>; 1714 }; 1715 }; 1716 }; 1717 }; 1718 1719 aobus: bus@ff800000 { 1720 compatible = "simple-bus"; 1721 reg = <0x0 0xff800000 0x0 0x100000>; 1722 #address-cells = <2>; 1723 #size-cells = <2>; 1724 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1725 1726 rti: sys-ctrl@0 { 1727 compatible = "amlogic,meson-gx-ao-sysctrl", 1728 "simple-mfd", "syscon"; 1729 reg = <0x0 0x0 0x0 0x100>; 1730 #address-cells = <2>; 1731 #size-cells = <2>; 1732 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1733 1734 clkc_AO: clock-controller { 1735 compatible = "amlogic,meson-g12a-aoclkc"; 1736 #clock-cells = <1>; 1737 #reset-cells = <1>; 1738 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1739 clock-names = "xtal", "mpeg-clk"; 1740 }; 1741 1742 ao_pinctrl: pinctrl { 1743 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1744 #address-cells = <2>; 1745 #size-cells = <2>; 1746 ranges; 1747 1748 gpio_ao: bank@14 { 1749 reg = <0x0 0x14 0x0 0x8>, 1750 <0x0 0x1c 0x0 0x8>, 1751 <0x0 0x24 0x0 0x14>; 1752 reg-names = "mux", 1753 "ds", 1754 "gpio"; 1755 gpio-controller; 1756 #gpio-cells = <2>; 1757 gpio-ranges = <&ao_pinctrl 0 0 15>; 1758 }; 1759 1760 i2c_ao_sck_pins: i2c_ao_sck_pins { 1761 mux { 1762 groups = "i2c_ao_sck"; 1763 function = "i2c_ao"; 1764 bias-disable; 1765 drive-strength-microamp = <3000>; 1766 }; 1767 }; 1768 1769 i2c_ao_sda_pins: i2c_ao_sda { 1770 mux { 1771 groups = "i2c_ao_sda"; 1772 function = "i2c_ao"; 1773 bias-disable; 1774 drive-strength-microamp = <3000>; 1775 }; 1776 }; 1777 1778 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1779 mux { 1780 groups = "i2c_ao_sck_e"; 1781 function = "i2c_ao"; 1782 bias-disable; 1783 drive-strength-microamp = <3000>; 1784 }; 1785 }; 1786 1787 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1788 mux { 1789 groups = "i2c_ao_sda_e"; 1790 function = "i2c_ao"; 1791 bias-disable; 1792 drive-strength-microamp = <3000>; 1793 }; 1794 }; 1795 1796 mclk0_ao_pins: mclk0-ao { 1797 mux { 1798 groups = "mclk0_ao"; 1799 function = "mclk0_ao"; 1800 bias-disable; 1801 drive-strength-microamp = <3000>; 1802 }; 1803 }; 1804 1805 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1806 mux { 1807 groups = "tdm_ao_b_din0"; 1808 function = "tdm_ao_b"; 1809 bias-disable; 1810 }; 1811 }; 1812 1813 spdif_ao_out_pins: spdif-ao-out { 1814 mux { 1815 groups = "spdif_ao_out"; 1816 function = "spdif_ao_out"; 1817 drive-strength-microamp = <500>; 1818 bias-disable; 1819 }; 1820 }; 1821 1822 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1823 mux { 1824 groups = "tdm_ao_b_din1"; 1825 function = "tdm_ao_b"; 1826 bias-disable; 1827 }; 1828 }; 1829 1830 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1831 mux { 1832 groups = "tdm_ao_b_din2"; 1833 function = "tdm_ao_b"; 1834 bias-disable; 1835 }; 1836 }; 1837 1838 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1839 mux { 1840 groups = "tdm_ao_b_dout0"; 1841 function = "tdm_ao_b"; 1842 bias-disable; 1843 drive-strength-microamp = <3000>; 1844 }; 1845 }; 1846 1847 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1848 mux { 1849 groups = "tdm_ao_b_dout1"; 1850 function = "tdm_ao_b"; 1851 bias-disable; 1852 drive-strength-microamp = <3000>; 1853 }; 1854 }; 1855 1856 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1857 mux { 1858 groups = "tdm_ao_b_dout2"; 1859 function = "tdm_ao_b"; 1860 bias-disable; 1861 drive-strength-microamp = <3000>; 1862 }; 1863 }; 1864 1865 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1866 mux { 1867 groups = "tdm_ao_b_fs"; 1868 function = "tdm_ao_b"; 1869 bias-disable; 1870 drive-strength-microamp = <3000>; 1871 }; 1872 }; 1873 1874 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1875 mux { 1876 groups = "tdm_ao_b_sclk"; 1877 function = "tdm_ao_b"; 1878 bias-disable; 1879 drive-strength-microamp = <3000>; 1880 }; 1881 }; 1882 1883 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1884 mux { 1885 groups = "tdm_ao_b_slv_fs"; 1886 function = "tdm_ao_b"; 1887 bias-disable; 1888 }; 1889 }; 1890 1891 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1892 mux { 1893 groups = "tdm_ao_b_slv_sclk"; 1894 function = "tdm_ao_b"; 1895 bias-disable; 1896 }; 1897 }; 1898 1899 uart_ao_a_pins: uart-a-ao { 1900 mux { 1901 groups = "uart_ao_a_tx", 1902 "uart_ao_a_rx"; 1903 function = "uart_ao_a"; 1904 bias-disable; 1905 }; 1906 }; 1907 1908 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1909 mux { 1910 groups = "uart_ao_a_cts", 1911 "uart_ao_a_rts"; 1912 function = "uart_ao_a"; 1913 bias-disable; 1914 }; 1915 }; 1916 1917 uart_ao_b_2_3_pins: uart-ao-b-2-3 { 1918 mux { 1919 groups = "uart_ao_b_tx_2", 1920 "uart_ao_b_rx_3"; 1921 function = "uart_ao_b"; 1922 bias-disable; 1923 }; 1924 }; 1925 1926 uart_ao_b_8_9_pins: uart-ao-b-8-9 { 1927 mux { 1928 groups = "uart_ao_b_tx_8", 1929 "uart_ao_b_rx_9"; 1930 function = "uart_ao_b"; 1931 bias-disable; 1932 }; 1933 }; 1934 1935 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { 1936 mux { 1937 groups = "uart_ao_b_cts", 1938 "uart_ao_b_rts"; 1939 function = "uart_ao_b"; 1940 bias-disable; 1941 }; 1942 }; 1943 1944 pwm_a_e_pins: pwm-a-e { 1945 mux { 1946 groups = "pwm_a_e"; 1947 function = "pwm_a_e"; 1948 bias-disable; 1949 }; 1950 }; 1951 1952 pwm_ao_a_pins: pwm-ao-a { 1953 mux { 1954 groups = "pwm_ao_a"; 1955 function = "pwm_ao_a"; 1956 bias-disable; 1957 }; 1958 }; 1959 1960 pwm_ao_b_pins: pwm-ao-b { 1961 mux { 1962 groups = "pwm_ao_b"; 1963 function = "pwm_ao_b"; 1964 bias-disable; 1965 }; 1966 }; 1967 1968 pwm_ao_c_4_pins: pwm-ao-c-4 { 1969 mux { 1970 groups = "pwm_ao_c_4"; 1971 function = "pwm_ao_c"; 1972 bias-disable; 1973 }; 1974 }; 1975 1976 pwm_ao_c_6_pins: pwm-ao-c-6 { 1977 mux { 1978 groups = "pwm_ao_c_6"; 1979 function = "pwm_ao_c"; 1980 bias-disable; 1981 }; 1982 }; 1983 1984 pwm_ao_d_5_pins: pwm-ao-d-5 { 1985 mux { 1986 groups = "pwm_ao_d_5"; 1987 function = "pwm_ao_d"; 1988 bias-disable; 1989 }; 1990 }; 1991 1992 pwm_ao_d_10_pins: pwm-ao-d-10 { 1993 mux { 1994 groups = "pwm_ao_d_10"; 1995 function = "pwm_ao_d"; 1996 bias-disable; 1997 }; 1998 }; 1999 2000 pwm_ao_d_e_pins: pwm-ao-d-e { 2001 mux { 2002 groups = "pwm_ao_d_e"; 2003 function = "pwm_ao_d"; 2004 }; 2005 }; 2006 2007 remote_input_ao_pins: remote-input-ao { 2008 mux { 2009 groups = "remote_ao_input"; 2010 function = "remote_ao_input"; 2011 bias-disable; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 vrtc: rtc@a8 { 2018 compatible = "amlogic,meson-vrtc"; 2019 reg = <0x0 0x000a8 0x0 0x4>; 2020 }; 2021 2022 cec_AO: cec@100 { 2023 compatible = "amlogic,meson-gx-ao-cec"; 2024 reg = <0x0 0x00100 0x0 0x14>; 2025 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2026 clocks = <&clkc_AO CLKID_AO_CEC>; 2027 clock-names = "core"; 2028 status = "disabled"; 2029 }; 2030 2031 sec_AO: ao-secure@140 { 2032 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2033 reg = <0x0 0x140 0x0 0x140>; 2034 amlogic,has-chip-id; 2035 }; 2036 2037 cecb_AO: cec@280 { 2038 compatible = "amlogic,meson-g12a-ao-cec"; 2039 reg = <0x0 0x00280 0x0 0x1c>; 2040 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2041 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2042 clock-names = "oscin"; 2043 status = "disabled"; 2044 }; 2045 2046 pwm_AO_cd: pwm@2000 { 2047 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2048 reg = <0x0 0x2000 0x0 0x20>; 2049 #pwm-cells = <3>; 2050 status = "disabled"; 2051 }; 2052 2053 uart_AO: serial@3000 { 2054 compatible = "amlogic,meson-g12a-uart", 2055 "amlogic,meson-gx-uart", 2056 "amlogic,meson-ao-uart"; 2057 reg = <0x0 0x3000 0x0 0x18>; 2058 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2059 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2060 clock-names = "xtal", "pclk", "baud"; 2061 status = "disabled"; 2062 }; 2063 2064 uart_AO_B: serial@4000 { 2065 compatible = "amlogic,meson-g12a-uart", 2066 "amlogic,meson-gx-uart", 2067 "amlogic,meson-ao-uart"; 2068 reg = <0x0 0x4000 0x0 0x18>; 2069 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2070 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2071 clock-names = "xtal", "pclk", "baud"; 2072 status = "disabled"; 2073 }; 2074 2075 i2c_AO: i2c@5000 { 2076 compatible = "amlogic,meson-axg-i2c"; 2077 status = "disabled"; 2078 reg = <0x0 0x05000 0x0 0x20>; 2079 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2080 #address-cells = <1>; 2081 #size-cells = <0>; 2082 clocks = <&clkc CLKID_I2C>; 2083 }; 2084 2085 pwm_AO_ab: pwm@7000 { 2086 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2087 reg = <0x0 0x7000 0x0 0x20>; 2088 #pwm-cells = <3>; 2089 status = "disabled"; 2090 }; 2091 2092 ir: ir@8000 { 2093 compatible = "amlogic,meson-gxbb-ir"; 2094 reg = <0x0 0x8000 0x0 0x20>; 2095 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2096 status = "disabled"; 2097 }; 2098 2099 saradc: adc@9000 { 2100 compatible = "amlogic,meson-g12a-saradc", 2101 "amlogic,meson-saradc"; 2102 reg = <0x0 0x9000 0x0 0x48>; 2103 #io-channel-cells = <1>; 2104 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2105 clocks = <&xtal>, 2106 <&clkc_AO CLKID_AO_SAR_ADC>, 2107 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2108 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2109 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2110 status = "disabled"; 2111 }; 2112 }; 2113 2114 vdec: video-decoder@ff620000 { 2115 compatible = "amlogic,g12a-vdec"; 2116 reg = <0x0 0xff620000 0x0 0x10000>, 2117 <0x0 0xffd0e180 0x0 0xe4>; 2118 reg-names = "dos", "esparser"; 2119 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2120 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2121 interrupt-names = "vdec", "esparser"; 2122 2123 amlogic,ao-sysctrl = <&rti>; 2124 amlogic,canvas = <&canvas>; 2125 2126 clocks = <&clkc CLKID_PARSER>, 2127 <&clkc CLKID_DOS>, 2128 <&clkc CLKID_VDEC_1>, 2129 <&clkc CLKID_VDEC_HEVC>, 2130 <&clkc CLKID_VDEC_HEVCF>; 2131 clock-names = "dos_parser", "dos", "vdec_1", 2132 "vdec_hevc", "vdec_hevcf"; 2133 resets = <&reset RESET_PARSER>; 2134 reset-names = "esparser"; 2135 }; 2136 2137 vpu: vpu@ff900000 { 2138 compatible = "amlogic,meson-g12a-vpu"; 2139 reg = <0x0 0xff900000 0x0 0x100000>, 2140 <0x0 0xff63c000 0x0 0x1000>; 2141 reg-names = "vpu", "hhi"; 2142 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2143 #address-cells = <1>; 2144 #size-cells = <0>; 2145 amlogic,canvas = <&canvas>; 2146 2147 /* CVBS VDAC output port */ 2148 cvbs_vdac_port: port@0 { 2149 reg = <0>; 2150 }; 2151 2152 /* HDMI-TX output port */ 2153 hdmi_tx_port: port@1 { 2154 reg = <1>; 2155 2156 hdmi_tx_out: endpoint { 2157 remote-endpoint = <&hdmi_tx_in>; 2158 }; 2159 }; 2160 }; 2161 2162 gic: interrupt-controller@ffc01000 { 2163 compatible = "arm,gic-400"; 2164 reg = <0x0 0xffc01000 0 0x1000>, 2165 <0x0 0xffc02000 0 0x2000>, 2166 <0x0 0xffc04000 0 0x2000>, 2167 <0x0 0xffc06000 0 0x2000>; 2168 interrupt-controller; 2169 interrupts = <GIC_PPI 9 2170 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2171 #interrupt-cells = <3>; 2172 #address-cells = <0>; 2173 }; 2174 2175 cbus: bus@ffd00000 { 2176 compatible = "simple-bus"; 2177 reg = <0x0 0xffd00000 0x0 0x100000>; 2178 #address-cells = <2>; 2179 #size-cells = <2>; 2180 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2181 2182 reset: reset-controller@1004 { 2183 compatible = "amlogic,meson-axg-reset"; 2184 reg = <0x0 0x1004 0x0 0x9c>; 2185 #reset-cells = <1>; 2186 }; 2187 2188 gpio_intc: interrupt-controller@f080 { 2189 compatible = "amlogic,meson-g12a-gpio-intc", 2190 "amlogic,meson-gpio-intc"; 2191 reg = <0x0 0xf080 0x0 0x10>; 2192 interrupt-controller; 2193 #interrupt-cells = <2>; 2194 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2195 }; 2196 2197 watchdog: watchdog@f0d0 { 2198 compatible = "amlogic,meson-gxbb-wdt"; 2199 reg = <0x0 0xf0d0 0x0 0x10>; 2200 clocks = <&xtal>; 2201 }; 2202 2203 spicc0: spi@13000 { 2204 compatible = "amlogic,meson-g12a-spicc"; 2205 reg = <0x0 0x13000 0x0 0x44>; 2206 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&clkc CLKID_SPICC0>, 2208 <&clkc CLKID_SPICC0_SCLK>; 2209 clock-names = "core", "pclk"; 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 status = "disabled"; 2213 }; 2214 2215 spicc1: spi@15000 { 2216 compatible = "amlogic,meson-g12a-spicc"; 2217 reg = <0x0 0x15000 0x0 0x44>; 2218 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&clkc CLKID_SPICC1>, 2220 <&clkc CLKID_SPICC1_SCLK>; 2221 clock-names = "core", "pclk"; 2222 #address-cells = <1>; 2223 #size-cells = <0>; 2224 status = "disabled"; 2225 }; 2226 2227 spifc: spi@14000 { 2228 compatible = "amlogic,meson-gxbb-spifc"; 2229 status = "disabled"; 2230 reg = <0x0 0x14000 0x0 0x80>; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 clocks = <&clkc CLKID_CLK81>; 2234 }; 2235 2236 pwm_ef: pwm@19000 { 2237 compatible = "amlogic,meson-g12a-ee-pwm"; 2238 reg = <0x0 0x19000 0x0 0x20>; 2239 #pwm-cells = <3>; 2240 status = "disabled"; 2241 }; 2242 2243 pwm_cd: pwm@1a000 { 2244 compatible = "amlogic,meson-g12a-ee-pwm"; 2245 reg = <0x0 0x1a000 0x0 0x20>; 2246 #pwm-cells = <3>; 2247 status = "disabled"; 2248 }; 2249 2250 pwm_ab: pwm@1b000 { 2251 compatible = "amlogic,meson-g12a-ee-pwm"; 2252 reg = <0x0 0x1b000 0x0 0x20>; 2253 #pwm-cells = <3>; 2254 status = "disabled"; 2255 }; 2256 2257 i2c3: i2c@1c000 { 2258 compatible = "amlogic,meson-axg-i2c"; 2259 status = "disabled"; 2260 reg = <0x0 0x1c000 0x0 0x20>; 2261 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 clocks = <&clkc CLKID_I2C>; 2265 }; 2266 2267 i2c2: i2c@1d000 { 2268 compatible = "amlogic,meson-axg-i2c"; 2269 status = "disabled"; 2270 reg = <0x0 0x1d000 0x0 0x20>; 2271 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 clocks = <&clkc CLKID_I2C>; 2275 }; 2276 2277 i2c1: i2c@1e000 { 2278 compatible = "amlogic,meson-axg-i2c"; 2279 status = "disabled"; 2280 reg = <0x0 0x1e000 0x0 0x20>; 2281 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 clocks = <&clkc CLKID_I2C>; 2285 }; 2286 2287 i2c0: i2c@1f000 { 2288 compatible = "amlogic,meson-axg-i2c"; 2289 status = "disabled"; 2290 reg = <0x0 0x1f000 0x0 0x20>; 2291 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2292 #address-cells = <1>; 2293 #size-cells = <0>; 2294 clocks = <&clkc CLKID_I2C>; 2295 }; 2296 2297 clk_msr: clock-measure@18000 { 2298 compatible = "amlogic,meson-g12a-clk-measure"; 2299 reg = <0x0 0x18000 0x0 0x10>; 2300 }; 2301 2302 uart_C: serial@22000 { 2303 compatible = "amlogic,meson-g12a-uart", 2304 "amlogic,meson-gx-uart"; 2305 reg = <0x0 0x22000 0x0 0x18>; 2306 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2307 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2308 clock-names = "xtal", "pclk", "baud"; 2309 status = "disabled"; 2310 }; 2311 2312 uart_B: serial@23000 { 2313 compatible = "amlogic,meson-g12a-uart", 2314 "amlogic,meson-gx-uart"; 2315 reg = <0x0 0x23000 0x0 0x18>; 2316 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2317 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2318 clock-names = "xtal", "pclk", "baud"; 2319 status = "disabled"; 2320 }; 2321 2322 uart_A: serial@24000 { 2323 compatible = "amlogic,meson-g12a-uart", 2324 "amlogic,meson-gx-uart"; 2325 reg = <0x0 0x24000 0x0 0x18>; 2326 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2327 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2328 clock-names = "xtal", "pclk", "baud"; 2329 status = "disabled"; 2330 fifo-size = <128>; 2331 }; 2332 }; 2333 2334 sd_emmc_a: mmc@ffe03000 { 2335 compatible = "amlogic,meson-axg-mmc"; 2336 reg = <0x0 0xffe03000 0x0 0x800>; 2337 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2338 status = "disabled"; 2339 clocks = <&clkc CLKID_SD_EMMC_A>, 2340 <&clkc CLKID_SD_EMMC_A_CLK0>, 2341 <&clkc CLKID_FCLK_DIV2>; 2342 clock-names = "core", "clkin0", "clkin1"; 2343 resets = <&reset RESET_SD_EMMC_A>; 2344 }; 2345 2346 sd_emmc_b: mmc@ffe05000 { 2347 compatible = "amlogic,meson-axg-mmc"; 2348 reg = <0x0 0xffe05000 0x0 0x800>; 2349 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2350 status = "disabled"; 2351 clocks = <&clkc CLKID_SD_EMMC_B>, 2352 <&clkc CLKID_SD_EMMC_B_CLK0>, 2353 <&clkc CLKID_FCLK_DIV2>; 2354 clock-names = "core", "clkin0", "clkin1"; 2355 resets = <&reset RESET_SD_EMMC_B>; 2356 }; 2357 2358 sd_emmc_c: mmc@ffe07000 { 2359 compatible = "amlogic,meson-axg-mmc"; 2360 reg = <0x0 0xffe07000 0x0 0x800>; 2361 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2362 status = "disabled"; 2363 clocks = <&clkc CLKID_SD_EMMC_C>, 2364 <&clkc CLKID_SD_EMMC_C_CLK0>, 2365 <&clkc CLKID_FCLK_DIV2>; 2366 clock-names = "core", "clkin0", "clkin1"; 2367 resets = <&reset RESET_SD_EMMC_C>; 2368 }; 2369 2370 usb: usb@ffe09000 { 2371 status = "disabled"; 2372 compatible = "amlogic,meson-g12a-usb-ctrl"; 2373 reg = <0x0 0xffe09000 0x0 0xa0>; 2374 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2375 #address-cells = <2>; 2376 #size-cells = <2>; 2377 ranges; 2378 2379 clocks = <&clkc CLKID_USB>; 2380 resets = <&reset RESET_USB>; 2381 2382 dr_mode = "otg"; 2383 2384 phys = <&usb2_phy0>, <&usb2_phy1>, 2385 <&usb3_pcie_phy PHY_TYPE_USB3>; 2386 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2387 2388 dwc2: usb@ff400000 { 2389 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2390 reg = <0x0 0xff400000 0x0 0x40000>; 2391 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2392 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2393 clock-names = "otg"; 2394 phys = <&usb2_phy1>; 2395 phy-names = "usb2-phy"; 2396 dr_mode = "peripheral"; 2397 g-rx-fifo-size = <192>; 2398 g-np-tx-fifo-size = <128>; 2399 g-tx-fifo-size = <128 128 16 16 16>; 2400 }; 2401 2402 dwc3: usb@ff500000 { 2403 compatible = "snps,dwc3"; 2404 reg = <0x0 0xff500000 0x0 0x100000>; 2405 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2406 dr_mode = "host"; 2407 snps,dis_u2_susphy_quirk; 2408 snps,quirk-frame-length-adjustment = <0x20>; 2409 snps,parkmode-disable-ss-quirk; 2410 }; 2411 }; 2412 2413 mali: gpu@ffe40000 { 2414 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2415 reg = <0x0 0xffe40000 0x0 0x40000>; 2416 interrupt-parent = <&gic>; 2417 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2418 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2420 interrupt-names = "job", "mmu", "gpu"; 2421 clocks = <&clkc CLKID_MALI>; 2422 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2423 operating-points-v2 = <&gpu_opp_table>; 2424 #cooling-cells = <2>; 2425 }; 2426 }; 2427 2428 thermal-zones { 2429 cpu_thermal: cpu-thermal { 2430 polling-delay = <1000>; 2431 polling-delay-passive = <100>; 2432 thermal-sensors = <&cpu_temp>; 2433 2434 trips { 2435 cpu_passive: cpu-passive { 2436 temperature = <85000>; /* millicelsius */ 2437 hysteresis = <2000>; /* millicelsius */ 2438 type = "passive"; 2439 }; 2440 2441 cpu_hot: cpu-hot { 2442 temperature = <95000>; /* millicelsius */ 2443 hysteresis = <2000>; /* millicelsius */ 2444 type = "hot"; 2445 }; 2446 2447 cpu_critical: cpu-critical { 2448 temperature = <110000>; /* millicelsius */ 2449 hysteresis = <2000>; /* millicelsius */ 2450 type = "critical"; 2451 }; 2452 }; 2453 }; 2454 2455 ddr_thermal: ddr-thermal { 2456 polling-delay = <1000>; 2457 polling-delay-passive = <100>; 2458 thermal-sensors = <&ddr_temp>; 2459 2460 trips { 2461 ddr_passive: ddr-passive { 2462 temperature = <85000>; /* millicelsius */ 2463 hysteresis = <2000>; /* millicelsius */ 2464 type = "passive"; 2465 }; 2466 2467 ddr_critical: ddr-critical { 2468 temperature = <110000>; /* millicelsius */ 2469 hysteresis = <2000>; /* millicelsius */ 2470 type = "critical"; 2471 }; 2472 }; 2473 2474 cooling-maps { 2475 map { 2476 trip = <&ddr_passive>; 2477 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2478 }; 2479 }; 2480 }; 2481 }; 2482 2483 timer { 2484 compatible = "arm,armv8-timer"; 2485 interrupts = <GIC_PPI 13 2486 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2487 <GIC_PPI 14 2488 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2489 <GIC_PPI 11 2490 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2491 <GIC_PPI 10 2492 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2493 arm,no-tick-in-suspend; 2494 }; 2495 2496 xtal: xtal-clk { 2497 compatible = "fixed-clock"; 2498 clock-frequency = <24000000>; 2499 clock-output-names = "xtal"; 2500 #clock-cells = <0>; 2501 }; 2502 2503 npu: npu@ff100000 { 2504 compatible = "vivante,gc"; 2505 reg = <0x0 0xff100000 0x0 0x20000>; 2506 interrupts = <0 147 4>; 2507 clocks = <&clkc CLKID_NNA_CORE_CLK>, 2508 <&clkc CLKID_NNA_AXI_CLK>; 2509 clock-names = "core", "bus"; 2510 resets = <&reset RESET_NNA>; 2511 status = "disabled"; 2512 }; 2513}; 2514