1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/platform_data/gpio-davinci.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/spinlock.h>
25 #include <linux/pm_runtime.h>
26
27 #define MAX_REGS_BANKS 5
28 #define MAX_INT_PER_BANK 32
29
30 struct davinci_gpio_regs {
31 u32 dir;
32 u32 out_data;
33 u32 set_data;
34 u32 clr_data;
35 u32 in_data;
36 u32 set_rising;
37 u32 clr_rising;
38 u32 set_falling;
39 u32 clr_falling;
40 u32 intstat;
41 };
42
43 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
44
45 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
46
47 static void __iomem *gpio_base;
48 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
49
50 struct davinci_gpio_irq_data {
51 void __iomem *regs;
52 struct davinci_gpio_controller *chip;
53 int bank_num;
54 };
55
56 struct davinci_gpio_controller {
57 struct gpio_chip chip;
58 struct irq_domain *irq_domain;
59 /* Serialize access to GPIO registers */
60 spinlock_t lock;
61 void __iomem *regs[MAX_REGS_BANKS];
62 int gpio_unbanked;
63 int irqs[MAX_INT_PER_BANK];
64 struct davinci_gpio_regs context[MAX_REGS_BANKS];
65 u32 binten_context;
66 };
67
__gpio_mask(unsigned gpio)68 static inline u32 __gpio_mask(unsigned gpio)
69 {
70 return 1 << (gpio % 32);
71 }
72
irq2regs(struct irq_data * d)73 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
74 {
75 struct davinci_gpio_regs __iomem *g;
76
77 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
78
79 return g;
80 }
81
82 static int davinci_gpio_irq_setup(struct platform_device *pdev);
83
84 /*--------------------------------------------------------------------------*/
85
86 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
__davinci_direction(struct gpio_chip * chip,unsigned offset,bool out,int value)87 static inline int __davinci_direction(struct gpio_chip *chip,
88 unsigned offset, bool out, int value)
89 {
90 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
91 struct davinci_gpio_regs __iomem *g;
92 unsigned long flags;
93 u32 temp;
94 int bank = offset / 32;
95 u32 mask = __gpio_mask(offset);
96
97 g = d->regs[bank];
98 spin_lock_irqsave(&d->lock, flags);
99 temp = readl_relaxed(&g->dir);
100 if (out) {
101 temp &= ~mask;
102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
103 } else {
104 temp |= mask;
105 }
106 writel_relaxed(temp, &g->dir);
107 spin_unlock_irqrestore(&d->lock, flags);
108
109 return 0;
110 }
111
davinci_direction_in(struct gpio_chip * chip,unsigned offset)112 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
113 {
114 return __davinci_direction(chip, offset, false, 0);
115 }
116
117 static int
davinci_direction_out(struct gpio_chip * chip,unsigned offset,int value)118 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
119 {
120 return __davinci_direction(chip, offset, true, value);
121 }
122
123 /*
124 * Read the pin's value (works even if it's set up as output);
125 * returns zero/nonzero.
126 *
127 * Note that changes are synched to the GPIO clock, so reading values back
128 * right after you've set them may give old values.
129 */
davinci_gpio_get(struct gpio_chip * chip,unsigned offset)130 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
131 {
132 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
133 struct davinci_gpio_regs __iomem *g;
134 int bank = offset / 32;
135
136 g = d->regs[bank];
137
138 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
139 }
140
141 /*
142 * Assuming the pin is muxed as a gpio output, set its output value.
143 */
144 static void
davinci_gpio_set(struct gpio_chip * chip,unsigned offset,int value)145 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
146 {
147 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
148 struct davinci_gpio_regs __iomem *g;
149 int bank = offset / 32;
150
151 g = d->regs[bank];
152
153 writel_relaxed(__gpio_mask(offset),
154 value ? &g->set_data : &g->clr_data);
155 }
156
157 static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device * pdev)158 davinci_gpio_get_pdata(struct platform_device *pdev)
159 {
160 struct device_node *dn = pdev->dev.of_node;
161 struct davinci_gpio_platform_data *pdata;
162 int ret;
163 u32 val;
164
165 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
166 return dev_get_platdata(&pdev->dev);
167
168 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
169 if (!pdata)
170 return NULL;
171
172 ret = of_property_read_u32(dn, "ti,ngpio", &val);
173 if (ret)
174 goto of_err;
175
176 pdata->ngpio = val;
177
178 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
179 if (ret)
180 goto of_err;
181
182 pdata->gpio_unbanked = val;
183
184 return pdata;
185
186 of_err:
187 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
188 return NULL;
189 }
190
davinci_gpio_probe(struct platform_device * pdev)191 static int davinci_gpio_probe(struct platform_device *pdev)
192 {
193 int bank, i, ret = 0;
194 unsigned int ngpio, nbank, nirq;
195 struct davinci_gpio_controller *chips;
196 struct davinci_gpio_platform_data *pdata;
197 struct device *dev = &pdev->dev;
198
199 pdata = davinci_gpio_get_pdata(pdev);
200 if (!pdata) {
201 dev_err(dev, "No platform data found\n");
202 return -EINVAL;
203 }
204
205 dev->platform_data = pdata;
206
207 /*
208 * The gpio banks conceptually expose a segmented bitmap,
209 * and "ngpio" is one more than the largest zero-based
210 * bit index that's valid.
211 */
212 ngpio = pdata->ngpio;
213 if (ngpio == 0) {
214 dev_err(dev, "How many GPIOs?\n");
215 return -EINVAL;
216 }
217
218 /*
219 * If there are unbanked interrupts then the number of
220 * interrupts is equal to number of gpios else all are banked so
221 * number of interrupts is equal to number of banks(each with 16 gpios)
222 */
223 if (pdata->gpio_unbanked)
224 nirq = pdata->gpio_unbanked;
225 else
226 nirq = DIV_ROUND_UP(ngpio, 16);
227
228 if (nirq > MAX_INT_PER_BANK) {
229 dev_err(dev, "Too many IRQs!\n");
230 return -EINVAL;
231 }
232
233 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
234 if (!chips)
235 return -ENOMEM;
236
237 gpio_base = devm_platform_ioremap_resource(pdev, 0);
238 if (IS_ERR(gpio_base))
239 return PTR_ERR(gpio_base);
240
241 for (i = 0; i < nirq; i++) {
242 chips->irqs[i] = platform_get_irq(pdev, i);
243 if (chips->irqs[i] < 0)
244 return chips->irqs[i];
245 }
246
247 chips->chip.label = dev_name(dev);
248
249 chips->chip.direction_input = davinci_direction_in;
250 chips->chip.get = davinci_gpio_get;
251 chips->chip.direction_output = davinci_direction_out;
252 chips->chip.set = davinci_gpio_set;
253
254 chips->chip.ngpio = ngpio;
255 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
256
257 #ifdef CONFIG_OF_GPIO
258 chips->chip.parent = dev;
259 chips->chip.request = gpiochip_generic_request;
260 chips->chip.free = gpiochip_generic_free;
261 #endif
262 spin_lock_init(&chips->lock);
263
264 nbank = DIV_ROUND_UP(ngpio, 32);
265 for (bank = 0; bank < nbank; bank++)
266 chips->regs[bank] = gpio_base + offset_array[bank];
267
268 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
269 if (ret)
270 return ret;
271
272 platform_set_drvdata(pdev, chips);
273 ret = davinci_gpio_irq_setup(pdev);
274 if (ret)
275 return ret;
276
277 return 0;
278 }
279
280 /*--------------------------------------------------------------------------*/
281 /*
282 * We expect irqs will normally be set up as input pins, but they can also be
283 * used as output pins ... which is convenient for testing.
284 *
285 * NOTE: The first few GPIOs also have direct INTC hookups in addition
286 * to their GPIOBNK0 irq, with a bit less overhead.
287 *
288 * All those INTC hookups (direct, plus several IRQ banks) can also
289 * serve as EDMA event triggers.
290 */
291
gpio_irq_disable(struct irq_data * d)292 static void gpio_irq_disable(struct irq_data *d)
293 {
294 struct davinci_gpio_regs __iomem *g = irq2regs(d);
295 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
296
297 writel_relaxed(mask, &g->clr_falling);
298 writel_relaxed(mask, &g->clr_rising);
299 }
300
gpio_irq_enable(struct irq_data * d)301 static void gpio_irq_enable(struct irq_data *d)
302 {
303 struct davinci_gpio_regs __iomem *g = irq2regs(d);
304 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
305 unsigned status = irqd_get_trigger_type(d);
306
307 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
308 if (!status)
309 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
310
311 if (status & IRQ_TYPE_EDGE_FALLING)
312 writel_relaxed(mask, &g->set_falling);
313 if (status & IRQ_TYPE_EDGE_RISING)
314 writel_relaxed(mask, &g->set_rising);
315 }
316
gpio_irq_type(struct irq_data * d,unsigned trigger)317 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
318 {
319 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
320 return -EINVAL;
321
322 return 0;
323 }
324
325 static struct irq_chip gpio_irqchip = {
326 .name = "GPIO",
327 .irq_enable = gpio_irq_enable,
328 .irq_disable = gpio_irq_disable,
329 .irq_set_type = gpio_irq_type,
330 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
331 };
332
gpio_irq_handler(struct irq_desc * desc)333 static void gpio_irq_handler(struct irq_desc *desc)
334 {
335 struct davinci_gpio_regs __iomem *g;
336 u32 mask = 0xffff;
337 int bank_num;
338 struct davinci_gpio_controller *d;
339 struct davinci_gpio_irq_data *irqdata;
340
341 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
342 bank_num = irqdata->bank_num;
343 g = irqdata->regs;
344 d = irqdata->chip;
345
346 /* we only care about one bank */
347 if ((bank_num % 2) == 1)
348 mask <<= 16;
349
350 /* temporarily mask (level sensitive) parent IRQ */
351 chained_irq_enter(irq_desc_get_chip(desc), desc);
352 while (1) {
353 u32 status;
354 int bit;
355 irq_hw_number_t hw_irq;
356
357 /* ack any irqs */
358 status = readl_relaxed(&g->intstat) & mask;
359 if (!status)
360 break;
361 writel_relaxed(status, &g->intstat);
362
363 /* now demux them to the right lowlevel handler */
364
365 while (status) {
366 bit = __ffs(status);
367 status &= ~BIT(bit);
368 /* Max number of gpios per controller is 144 so
369 * hw_irq will be in [0..143]
370 */
371 hw_irq = (bank_num / 2) * 32 + bit;
372
373 generic_handle_domain_irq(d->irq_domain, hw_irq);
374 }
375 }
376 chained_irq_exit(irq_desc_get_chip(desc), desc);
377 /* now it may re-trigger */
378 }
379
gpio_to_irq_banked(struct gpio_chip * chip,unsigned offset)380 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
381 {
382 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
383
384 if (d->irq_domain)
385 return irq_create_mapping(d->irq_domain, offset);
386 else
387 return -ENXIO;
388 }
389
gpio_to_irq_unbanked(struct gpio_chip * chip,unsigned offset)390 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
391 {
392 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
393
394 /*
395 * NOTE: we assume for now that only irqs in the first gpio_chip
396 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
397 */
398 if (offset < d->gpio_unbanked)
399 return d->irqs[offset];
400 else
401 return -ENODEV;
402 }
403
gpio_irq_type_unbanked(struct irq_data * data,unsigned trigger)404 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
405 {
406 struct davinci_gpio_controller *d;
407 struct davinci_gpio_regs __iomem *g;
408 u32 mask, i;
409
410 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
411 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
412 for (i = 0; i < MAX_INT_PER_BANK; i++)
413 if (data->irq == d->irqs[i])
414 break;
415
416 if (i == MAX_INT_PER_BANK)
417 return -EINVAL;
418
419 mask = __gpio_mask(i);
420
421 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
422 return -EINVAL;
423
424 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
425 ? &g->set_falling : &g->clr_falling);
426 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
427 ? &g->set_rising : &g->clr_rising);
428
429 return 0;
430 }
431
432 static int
davinci_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)433 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
434 irq_hw_number_t hw)
435 {
436 struct davinci_gpio_controller *chips =
437 (struct davinci_gpio_controller *)d->host_data;
438 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
439
440 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
441 "davinci_gpio");
442 irq_set_irq_type(irq, IRQ_TYPE_NONE);
443 irq_set_chip_data(irq, (__force void *)g);
444 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
445
446 return 0;
447 }
448
449 static const struct irq_domain_ops davinci_gpio_irq_ops = {
450 .map = davinci_gpio_irq_map,
451 .xlate = irq_domain_xlate_onetwocell,
452 };
453
davinci_gpio_get_irq_chip(unsigned int irq)454 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
455 {
456 static struct irq_chip_type gpio_unbanked;
457
458 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
459
460 return &gpio_unbanked.chip;
461 };
462
keystone_gpio_get_irq_chip(unsigned int irq)463 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
464 {
465 static struct irq_chip gpio_unbanked;
466
467 gpio_unbanked = *irq_get_chip(irq);
468 return &gpio_unbanked;
469 };
470
471 static const struct of_device_id davinci_gpio_ids[];
472
473 /*
474 * NOTE: for suspend/resume, probably best to make a platform_device with
475 * suspend_late/resume_resume calls hooking into results of the set_wake()
476 * calls ... so if no gpios are wakeup events the clock can be disabled,
477 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
478 * (dm6446) can be set appropriately for GPIOV33 pins.
479 */
480
davinci_gpio_irq_setup(struct platform_device * pdev)481 static int davinci_gpio_irq_setup(struct platform_device *pdev)
482 {
483 unsigned gpio, bank;
484 int irq;
485 int ret;
486 struct clk *clk;
487 u32 binten = 0;
488 unsigned ngpio;
489 struct device *dev = &pdev->dev;
490 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
491 struct davinci_gpio_platform_data *pdata = dev->platform_data;
492 struct davinci_gpio_regs __iomem *g;
493 struct irq_domain *irq_domain = NULL;
494 const struct of_device_id *match;
495 struct irq_chip *irq_chip;
496 struct davinci_gpio_irq_data *irqdata;
497 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
498
499 /*
500 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
501 */
502 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
503 match = of_match_device(of_match_ptr(davinci_gpio_ids),
504 dev);
505 if (match)
506 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
507
508 ngpio = pdata->ngpio;
509
510 clk = devm_clk_get(dev, "gpio");
511 if (IS_ERR(clk)) {
512 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
513 return PTR_ERR(clk);
514 }
515
516 ret = clk_prepare_enable(clk);
517 if (ret)
518 return ret;
519
520 if (!pdata->gpio_unbanked) {
521 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
522 if (irq < 0) {
523 dev_err(dev, "Couldn't allocate IRQ numbers\n");
524 clk_disable_unprepare(clk);
525 return irq;
526 }
527
528 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
529 &davinci_gpio_irq_ops,
530 chips);
531 if (!irq_domain) {
532 dev_err(dev, "Couldn't register an IRQ domain\n");
533 clk_disable_unprepare(clk);
534 return -ENODEV;
535 }
536 }
537
538 /*
539 * Arrange gpiod_to_irq() support, handling either direct IRQs or
540 * banked IRQs. Having GPIOs in the first GPIO bank use direct
541 * IRQs, while the others use banked IRQs, would need some setup
542 * tweaks to recognize hardware which can do that.
543 */
544 chips->chip.to_irq = gpio_to_irq_banked;
545 chips->irq_domain = irq_domain;
546
547 /*
548 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
549 * controller only handling trigger modes. We currently assume no
550 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
551 */
552 if (pdata->gpio_unbanked) {
553 /* pass "bank 0" GPIO IRQs to AINTC */
554 chips->chip.to_irq = gpio_to_irq_unbanked;
555 chips->gpio_unbanked = pdata->gpio_unbanked;
556 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
557
558 /* AINTC handles mask/unmask; GPIO handles triggering */
559 irq = chips->irqs[0];
560 irq_chip = gpio_get_irq_chip(irq);
561 irq_chip->name = "GPIO-AINTC";
562 irq_chip->irq_set_type = gpio_irq_type_unbanked;
563
564 /* default trigger: both edges */
565 g = chips->regs[0];
566 writel_relaxed(~0, &g->set_falling);
567 writel_relaxed(~0, &g->set_rising);
568
569 /* set the direct IRQs up to use that irqchip */
570 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
571 irq_set_chip(chips->irqs[gpio], irq_chip);
572 irq_set_handler_data(chips->irqs[gpio], chips);
573 irq_set_status_flags(chips->irqs[gpio],
574 IRQ_TYPE_EDGE_BOTH);
575 }
576
577 goto done;
578 }
579
580 /*
581 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
582 * then chain through our own handler.
583 */
584 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
585 /* disabled by default, enabled only as needed
586 * There are register sets for 32 GPIOs. 2 banks of 16
587 * GPIOs are covered by each set of registers hence divide by 2
588 */
589 g = chips->regs[bank / 2];
590 writel_relaxed(~0, &g->clr_falling);
591 writel_relaxed(~0, &g->clr_rising);
592
593 /*
594 * Each chip handles 32 gpios, and each irq bank consists of 16
595 * gpio irqs. Pass the irq bank's corresponding controller to
596 * the chained irq handler.
597 */
598 irqdata = devm_kzalloc(&pdev->dev,
599 sizeof(struct
600 davinci_gpio_irq_data),
601 GFP_KERNEL);
602 if (!irqdata) {
603 clk_disable_unprepare(clk);
604 return -ENOMEM;
605 }
606
607 irqdata->regs = g;
608 irqdata->bank_num = bank;
609 irqdata->chip = chips;
610
611 irq_set_chained_handler_and_data(chips->irqs[bank],
612 gpio_irq_handler, irqdata);
613
614 binten |= BIT(bank);
615 }
616
617 done:
618 /*
619 * BINTEN -- per-bank interrupt enable. genirq would also let these
620 * bits be set/cleared dynamically.
621 */
622 writel_relaxed(binten, gpio_base + BINTEN);
623
624 return 0;
625 }
626
davinci_gpio_save_context(struct davinci_gpio_controller * chips,u32 nbank)627 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
628 u32 nbank)
629 {
630 struct davinci_gpio_regs __iomem *g;
631 struct davinci_gpio_regs *context;
632 u32 bank;
633 void __iomem *base;
634
635 base = chips->regs[0] - offset_array[0];
636 chips->binten_context = readl_relaxed(base + BINTEN);
637
638 for (bank = 0; bank < nbank; bank++) {
639 g = chips->regs[bank];
640 context = &chips->context[bank];
641 context->dir = readl_relaxed(&g->dir);
642 context->set_data = readl_relaxed(&g->set_data);
643 context->set_rising = readl_relaxed(&g->set_rising);
644 context->set_falling = readl_relaxed(&g->set_falling);
645 }
646
647 /* Clear all interrupt status registers */
648 writel_relaxed(GENMASK(31, 0), &g->intstat);
649 }
650
davinci_gpio_restore_context(struct davinci_gpio_controller * chips,u32 nbank)651 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
652 u32 nbank)
653 {
654 struct davinci_gpio_regs __iomem *g;
655 struct davinci_gpio_regs *context;
656 u32 bank;
657 void __iomem *base;
658
659 base = chips->regs[0] - offset_array[0];
660
661 if (readl_relaxed(base + BINTEN) != chips->binten_context)
662 writel_relaxed(chips->binten_context, base + BINTEN);
663
664 for (bank = 0; bank < nbank; bank++) {
665 g = chips->regs[bank];
666 context = &chips->context[bank];
667 if (readl_relaxed(&g->dir) != context->dir)
668 writel_relaxed(context->dir, &g->dir);
669 if (readl_relaxed(&g->set_data) != context->set_data)
670 writel_relaxed(context->set_data, &g->set_data);
671 if (readl_relaxed(&g->set_rising) != context->set_rising)
672 writel_relaxed(context->set_rising, &g->set_rising);
673 if (readl_relaxed(&g->set_falling) != context->set_falling)
674 writel_relaxed(context->set_falling, &g->set_falling);
675 }
676 }
677
davinci_gpio_suspend(struct device * dev)678 static int davinci_gpio_suspend(struct device *dev)
679 {
680 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
681 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
682 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
683
684 davinci_gpio_save_context(chips, nbank);
685
686 return 0;
687 }
688
davinci_gpio_resume(struct device * dev)689 static int davinci_gpio_resume(struct device *dev)
690 {
691 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
692 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
693 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
694
695 davinci_gpio_restore_context(chips, nbank);
696
697 return 0;
698 }
699
700 static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
701 davinci_gpio_resume);
702
703 static const struct of_device_id davinci_gpio_ids[] = {
704 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
705 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
706 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
707 { /* sentinel */ },
708 };
709 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
710
711 static struct platform_driver davinci_gpio_driver = {
712 .probe = davinci_gpio_probe,
713 .driver = {
714 .name = "davinci_gpio",
715 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
716 .of_match_table = of_match_ptr(davinci_gpio_ids),
717 },
718 };
719
720 /*
721 * GPIO driver registration needs to be done before machine_init functions
722 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
723 */
davinci_gpio_drv_reg(void)724 static int __init davinci_gpio_drv_reg(void)
725 {
726 return platform_driver_register(&davinci_gpio_driver);
727 }
728 postcore_initcall(davinci_gpio_drv_reg);
729
davinci_gpio_exit(void)730 static void __exit davinci_gpio_exit(void)
731 {
732 platform_driver_unregister(&davinci_gpio_driver);
733 }
734 module_exit(davinci_gpio_exit);
735
736 MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
737 MODULE_DESCRIPTION("DAVINCI GPIO driver");
738 MODULE_LICENSE("GPL");
739 MODULE_ALIAS("platform:gpio-davinci");
740