1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v8_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_amdkfd.h"
33 #include "amdgpu_gem.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
40
41 #include "oss/oss_3_0_d.h"
42 #include "oss/oss_3_0_sh_mask.h"
43
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46
47 #include "vid.h"
48 #include "vi.h"
49
50 #include "amdgpu_atombios.h"
51
52 #include "ivsrcid/ivsrcid_vislands30.h"
53
54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56 static int gmc_v8_0_wait_for_idle(void *handle);
57
58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
66
67 static const u32 golden_settings_tonga_a11[] = {
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75 };
76
77 static const u32 tonga_mgcg_cgcg_init[] = {
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
79 };
80
81 static const u32 golden_settings_fiji_a10[] = {
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86 };
87
88 static const u32 fiji_mgcg_cgcg_init[] = {
89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
90 };
91
92 static const u32 golden_settings_polaris11_a11[] = {
93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
97 };
98
99 static const u32 golden_settings_polaris10_a11[] = {
100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
105 };
106
107 static const u32 cz_mgcg_cgcg_init[] = {
108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
109 };
110
111 static const u32 stoney_mgcg_cgcg_init[] = {
112 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
114 };
115
116 static const u32 golden_settings_stoney_common[] = {
117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
119 };
120
gmc_v8_0_init_golden_registers(struct amdgpu_device * adev)121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
122 {
123 switch (adev->asic_type) {
124 case CHIP_FIJI:
125 amdgpu_device_program_register_sequence(adev,
126 fiji_mgcg_cgcg_init,
127 ARRAY_SIZE(fiji_mgcg_cgcg_init));
128 amdgpu_device_program_register_sequence(adev,
129 golden_settings_fiji_a10,
130 ARRAY_SIZE(golden_settings_fiji_a10));
131 break;
132 case CHIP_TONGA:
133 amdgpu_device_program_register_sequence(adev,
134 tonga_mgcg_cgcg_init,
135 ARRAY_SIZE(tonga_mgcg_cgcg_init));
136 amdgpu_device_program_register_sequence(adev,
137 golden_settings_tonga_a11,
138 ARRAY_SIZE(golden_settings_tonga_a11));
139 break;
140 case CHIP_POLARIS11:
141 case CHIP_POLARIS12:
142 case CHIP_VEGAM:
143 amdgpu_device_program_register_sequence(adev,
144 golden_settings_polaris11_a11,
145 ARRAY_SIZE(golden_settings_polaris11_a11));
146 break;
147 case CHIP_POLARIS10:
148 amdgpu_device_program_register_sequence(adev,
149 golden_settings_polaris10_a11,
150 ARRAY_SIZE(golden_settings_polaris10_a11));
151 break;
152 case CHIP_CARRIZO:
153 amdgpu_device_program_register_sequence(adev,
154 cz_mgcg_cgcg_init,
155 ARRAY_SIZE(cz_mgcg_cgcg_init));
156 break;
157 case CHIP_STONEY:
158 amdgpu_device_program_register_sequence(adev,
159 stoney_mgcg_cgcg_init,
160 ARRAY_SIZE(stoney_mgcg_cgcg_init));
161 amdgpu_device_program_register_sequence(adev,
162 golden_settings_stoney_common,
163 ARRAY_SIZE(golden_settings_stoney_common));
164 break;
165 default:
166 break;
167 }
168 }
169
gmc_v8_0_mc_stop(struct amdgpu_device * adev)170 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
171 {
172 u32 blackout;
173
174 gmc_v8_0_wait_for_idle(adev);
175
176 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
177 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
178 /* Block CPU access */
179 WREG32(mmBIF_FB_EN, 0);
180 /* blackout the MC */
181 blackout = REG_SET_FIELD(blackout,
182 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
183 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
184 }
185 /* wait for the MC to settle */
186 udelay(100);
187 }
188
gmc_v8_0_mc_resume(struct amdgpu_device * adev)189 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
190 {
191 u32 tmp;
192
193 /* unblackout the MC */
194 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
195 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
197 /* allow CPU access */
198 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
199 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
200 WREG32(mmBIF_FB_EN, tmp);
201 }
202
203 /**
204 * gmc_v8_0_init_microcode - load ucode images from disk
205 *
206 * @adev: amdgpu_device pointer
207 *
208 * Use the firmware interface to load the ucode images into
209 * the driver (not loaded into hw).
210 * Returns 0 on success, error on failure.
211 */
gmc_v8_0_init_microcode(struct amdgpu_device * adev)212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
213 {
214 const char *chip_name;
215 char fw_name[30];
216 int err;
217
218 DRM_DEBUG("\n");
219
220 switch (adev->asic_type) {
221 case CHIP_TONGA:
222 chip_name = "tonga";
223 break;
224 case CHIP_POLARIS11:
225 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
226 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
227 chip_name = "polaris11_k";
228 else
229 chip_name = "polaris11";
230 break;
231 case CHIP_POLARIS10:
232 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
233 chip_name = "polaris10_k";
234 else
235 chip_name = "polaris10";
236 break;
237 case CHIP_POLARIS12:
238 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
239 chip_name = "polaris12_k";
240 } else {
241 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
242 /* Polaris12 32bit ASIC needs a special MC firmware */
243 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
244 chip_name = "polaris12_32";
245 else
246 chip_name = "polaris12";
247 }
248 break;
249 case CHIP_FIJI:
250 case CHIP_CARRIZO:
251 case CHIP_STONEY:
252 case CHIP_VEGAM:
253 return 0;
254 default:
255 return -EINVAL;
256 }
257
258 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
259 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
260 if (err) {
261 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
262 amdgpu_ucode_release(&adev->gmc.fw);
263 }
264 return err;
265 }
266
267 /**
268 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
269 *
270 * @adev: amdgpu_device pointer
271 *
272 * Load the GDDR MC ucode into the hw (VI).
273 * Returns 0 on success, error on failure.
274 */
gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device * adev)275 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
276 {
277 const struct mc_firmware_header_v1_0 *hdr;
278 const __le32 *fw_data = NULL;
279 const __le32 *io_mc_regs = NULL;
280 u32 running;
281 int i, ucode_size, regs_size;
282
283 /* Skip MC ucode loading on SR-IOV capable boards.
284 * vbios does this for us in asic_init in that case.
285 * Skip MC ucode loading on VF, because hypervisor will do that
286 * for this adaptor.
287 */
288 if (amdgpu_sriov_bios(adev))
289 return 0;
290
291 if (!adev->gmc.fw)
292 return -EINVAL;
293
294 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
295 amdgpu_ucode_print_mc_hdr(&hdr->header);
296
297 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
298 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
299 io_mc_regs = (const __le32 *)
300 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
301 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
302 fw_data = (const __le32 *)
303 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
304
305 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
306
307 if (running == 0) {
308 /* reset the engine and set to writable */
309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
311
312 /* load mc io regs */
313 for (i = 0; i < regs_size; i++) {
314 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
315 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
316 }
317 /* load the MC ucode */
318 for (i = 0; i < ucode_size; i++)
319 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
320
321 /* put the engine back into the active state */
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
323 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
324 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
325
326 /* wait for training to complete */
327 for (i = 0; i < adev->usec_timeout; i++) {
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
329 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
330 break;
331 udelay(1);
332 }
333 for (i = 0; i < adev->usec_timeout; i++) {
334 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
335 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
336 break;
337 udelay(1);
338 }
339 }
340
341 return 0;
342 }
343
gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device * adev)344 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
345 {
346 const struct mc_firmware_header_v1_0 *hdr;
347 const __le32 *fw_data = NULL;
348 const __le32 *io_mc_regs = NULL;
349 u32 data;
350 int i, ucode_size, regs_size;
351
352 /* Skip MC ucode loading on SR-IOV capable boards.
353 * vbios does this for us in asic_init in that case.
354 * Skip MC ucode loading on VF, because hypervisor will do that
355 * for this adaptor.
356 */
357 if (amdgpu_sriov_bios(adev))
358 return 0;
359
360 if (!adev->gmc.fw)
361 return -EINVAL;
362
363 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
364 amdgpu_ucode_print_mc_hdr(&hdr->header);
365
366 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
367 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
368 io_mc_regs = (const __le32 *)
369 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
370 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
371 fw_data = (const __le32 *)
372 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
373
374 data = RREG32(mmMC_SEQ_MISC0);
375 data &= ~(0x40);
376 WREG32(mmMC_SEQ_MISC0, data);
377
378 /* load mc io regs */
379 for (i = 0; i < regs_size; i++) {
380 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
381 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
382 }
383
384 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
385 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
386
387 /* load the MC ucode */
388 for (i = 0; i < ucode_size; i++)
389 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
390
391 /* put the engine back into the active state */
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
394 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
395
396 /* wait for training to complete */
397 for (i = 0; i < adev->usec_timeout; i++) {
398 data = RREG32(mmMC_SEQ_MISC0);
399 if (data & 0x80)
400 break;
401 udelay(1);
402 }
403
404 return 0;
405 }
406
gmc_v8_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)407 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
408 struct amdgpu_gmc *mc)
409 {
410 u64 base = 0;
411
412 if (!amdgpu_sriov_vf(adev))
413 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
414 base <<= 24;
415
416 amdgpu_gmc_vram_location(adev, mc, base);
417 amdgpu_gmc_gart_location(adev, mc);
418 }
419
420 /**
421 * gmc_v8_0_mc_program - program the GPU memory controller
422 *
423 * @adev: amdgpu_device pointer
424 *
425 * Set the location of vram, gart, and AGP in the GPU's
426 * physical address space (VI).
427 */
gmc_v8_0_mc_program(struct amdgpu_device * adev)428 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
429 {
430 u32 tmp;
431 int i, j;
432
433 /* Initialize HDP */
434 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
435 WREG32((0xb05 + j), 0x00000000);
436 WREG32((0xb06 + j), 0x00000000);
437 WREG32((0xb07 + j), 0x00000000);
438 WREG32((0xb08 + j), 0x00000000);
439 WREG32((0xb09 + j), 0x00000000);
440 }
441 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
442
443 if (gmc_v8_0_wait_for_idle((void *)adev))
444 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
445
446 if (adev->mode_info.num_crtc) {
447 /* Lockout access through VGA aperture*/
448 tmp = RREG32(mmVGA_HDP_CONTROL);
449 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
450 WREG32(mmVGA_HDP_CONTROL, tmp);
451
452 /* disable VGA render */
453 tmp = RREG32(mmVGA_RENDER_CONTROL);
454 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
455 WREG32(mmVGA_RENDER_CONTROL, tmp);
456 }
457 /* Update configuration */
458 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
459 adev->gmc.vram_start >> 12);
460 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
461 adev->gmc.vram_end >> 12);
462 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
463 adev->mem_scratch.gpu_addr >> 12);
464
465 if (amdgpu_sriov_vf(adev)) {
466 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
467 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
468 WREG32(mmMC_VM_FB_LOCATION, tmp);
469 /* XXX double check these! */
470 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
471 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
472 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
473 }
474
475 WREG32(mmMC_VM_AGP_BASE, 0);
476 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
477 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
478 if (gmc_v8_0_wait_for_idle((void *)adev))
479 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
480
481 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
482
483 tmp = RREG32(mmHDP_MISC_CNTL);
484 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
485 WREG32(mmHDP_MISC_CNTL, tmp);
486
487 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
488 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
489 }
490
491 /**
492 * gmc_v8_0_mc_init - initialize the memory controller driver params
493 *
494 * @adev: amdgpu_device pointer
495 *
496 * Look up the amount of vram, vram width, and decide how to place
497 * vram and gart within the GPU's physical address space (VI).
498 * Returns 0 for success.
499 */
gmc_v8_0_mc_init(struct amdgpu_device * adev)500 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
501 {
502 int r;
503 u32 tmp;
504
505 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
506 if (!adev->gmc.vram_width) {
507 int chansize, numchan;
508
509 /* Get VRAM informations */
510 tmp = RREG32(mmMC_ARB_RAMCFG);
511 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
512 chansize = 64;
513 else
514 chansize = 32;
515
516 tmp = RREG32(mmMC_SHARED_CHMAP);
517 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
518 case 0:
519 default:
520 numchan = 1;
521 break;
522 case 1:
523 numchan = 2;
524 break;
525 case 2:
526 numchan = 4;
527 break;
528 case 3:
529 numchan = 8;
530 break;
531 case 4:
532 numchan = 3;
533 break;
534 case 5:
535 numchan = 6;
536 break;
537 case 6:
538 numchan = 10;
539 break;
540 case 7:
541 numchan = 12;
542 break;
543 case 8:
544 numchan = 16;
545 break;
546 }
547 adev->gmc.vram_width = numchan * chansize;
548 }
549 /* size in MB on si */
550 tmp = RREG32(mmCONFIG_MEMSIZE);
551 /* some boards may have garbage in the upper 16 bits */
552 if (tmp & 0xffff0000) {
553 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
554 if (tmp & 0xffff)
555 tmp &= 0xffff;
556 }
557 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
558 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
559
560 if (!(adev->flags & AMD_IS_APU)) {
561 r = amdgpu_device_resize_fb_bar(adev);
562 if (r)
563 return r;
564 }
565 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
566 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
567
568 #ifdef CONFIG_X86_64
569 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
570 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
571 adev->gmc.aper_size = adev->gmc.real_vram_size;
572 }
573 #endif
574
575 adev->gmc.visible_vram_size = adev->gmc.aper_size;
576
577 /* set the gart size */
578 if (amdgpu_gart_size == -1) {
579 switch (adev->asic_type) {
580 case CHIP_POLARIS10: /* all engines support GPUVM */
581 case CHIP_POLARIS11: /* all engines support GPUVM */
582 case CHIP_POLARIS12: /* all engines support GPUVM */
583 case CHIP_VEGAM: /* all engines support GPUVM */
584 default:
585 adev->gmc.gart_size = 256ULL << 20;
586 break;
587 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
588 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
589 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
590 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
591 adev->gmc.gart_size = 1024ULL << 20;
592 break;
593 }
594 } else {
595 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
596 }
597
598 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
599 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
600
601 return 0;
602 }
603
604 /**
605 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
606 *
607 * @adev: amdgpu_device pointer
608 * @pasid: pasid to be flush
609 * @flush_type: type of flush
610 * @all_hub: flush all hubs
611 * @inst: is used to select which instance of KIQ to use for the invalidation
612 *
613 * Flush the TLB for the requested pasid.
614 */
gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub,uint32_t inst)615 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
616 uint16_t pasid, uint32_t flush_type,
617 bool all_hub, uint32_t inst)
618 {
619 int vmid;
620 unsigned int tmp;
621
622 if (amdgpu_in_reset(adev))
623 return -EIO;
624
625 for (vmid = 1; vmid < 16; vmid++) {
626
627 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
628 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
629 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
630 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
631 RREG32(mmVM_INVALIDATE_RESPONSE);
632 break;
633 }
634 }
635
636 return 0;
637
638 }
639
640 /*
641 * GART
642 * VMID 0 is the physical GPU addresses as used by the kernel.
643 * VMIDs 1-15 are used for userspace clients and are handled
644 * by the amdgpu vm/hsa code.
645 */
646
647 /**
648 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
649 *
650 * @adev: amdgpu_device pointer
651 * @vmid: vm instance to flush
652 * @vmhub: which hub to flush
653 * @flush_type: type of flush
654 *
655 * Flush the TLB for the requested page table (VI).
656 */
gmc_v8_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)657 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
658 uint32_t vmhub, uint32_t flush_type)
659 {
660 /* bits 0-15 are the VM contexts0-15 */
661 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
662 }
663
gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)664 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
665 unsigned int vmid, uint64_t pd_addr)
666 {
667 uint32_t reg;
668
669 if (vmid < 8)
670 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
671 else
672 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
673 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
674
675 /* bits 0-15 are the VM contexts0-15 */
676 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
677
678 return pd_addr;
679 }
680
gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned int vmid,unsigned int pasid)681 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
682 unsigned int pasid)
683 {
684 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
685 }
686
687 /*
688 * PTE format on VI:
689 * 63:40 reserved
690 * 39:12 4k physical page base address
691 * 11:7 fragment
692 * 6 write
693 * 5 read
694 * 4 exe
695 * 3 reserved
696 * 2 snooped
697 * 1 system
698 * 0 valid
699 *
700 * PDE format on VI:
701 * 63:59 block fragment size
702 * 58:40 reserved
703 * 39:1 physical base address of PTE
704 * bits 5:1 must be 0.
705 * 0 valid
706 */
707
gmc_v8_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)708 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
709 uint64_t *addr, uint64_t *flags)
710 {
711 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
712 }
713
gmc_v8_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)714 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
715 struct amdgpu_bo_va_mapping *mapping,
716 uint64_t *flags)
717 {
718 *flags &= ~AMDGPU_PTE_EXECUTABLE;
719 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
720 *flags &= ~AMDGPU_PTE_PRT;
721 }
722
723 /**
724 * gmc_v8_0_set_fault_enable_default - update VM fault handling
725 *
726 * @adev: amdgpu_device pointer
727 * @value: true redirects VM faults to the default page
728 */
gmc_v8_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)729 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
730 bool value)
731 {
732 u32 tmp;
733
734 tmp = RREG32(mmVM_CONTEXT1_CNTL);
735 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
736 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
737 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
738 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
739 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
740 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
741 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
742 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
744 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
746 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
748 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
749 WREG32(mmVM_CONTEXT1_CNTL, tmp);
750 }
751
752 /**
753 * gmc_v8_0_set_prt() - set PRT VM fault
754 *
755 * @adev: amdgpu_device pointer
756 * @enable: enable/disable VM fault handling for PRT
757 */
gmc_v8_0_set_prt(struct amdgpu_device * adev,bool enable)758 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
759 {
760 u32 tmp;
761
762 if (enable && !adev->gmc.prt_warning) {
763 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
764 adev->gmc.prt_warning = true;
765 }
766
767 tmp = RREG32(mmVM_PRT_CNTL);
768 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
769 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
770 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
771 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
772 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
773 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
774 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
775 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
777 L2_CACHE_STORE_INVALID_ENTRIES, enable);
778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
779 L1_TLB_STORE_INVALID_ENTRIES, enable);
780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
781 MASK_PDE0_FAULT, enable);
782 WREG32(mmVM_PRT_CNTL, tmp);
783
784 if (enable) {
785 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
786 uint32_t high = adev->vm_manager.max_pfn -
787 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
788
789 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
790 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
791 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
792 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
793 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
794 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
795 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
796 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
797 } else {
798 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
799 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
800 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
801 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
802 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
803 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
804 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
805 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
806 }
807 }
808
809 /**
810 * gmc_v8_0_gart_enable - gart enable
811 *
812 * @adev: amdgpu_device pointer
813 *
814 * This sets up the TLBs, programs the page tables for VMID0,
815 * sets up the hw for VMIDs 1-15 which are allocated on
816 * demand, and sets up the global locations for the LDS, GDS,
817 * and GPUVM for FSA64 clients (VI).
818 * Returns 0 for success, errors for failure.
819 */
gmc_v8_0_gart_enable(struct amdgpu_device * adev)820 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
821 {
822 uint64_t table_addr;
823 u32 tmp, field;
824 int i;
825
826 if (adev->gart.bo == NULL) {
827 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
828 return -EINVAL;
829 }
830 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
831 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
832
833 /* Setup TLB control */
834 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
835 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
836 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
837 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
838 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
839 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
840 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
841 /* Setup L2 cache */
842 tmp = RREG32(mmVM_L2_CNTL);
843 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
845 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
847 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
850 WREG32(mmVM_L2_CNTL, tmp);
851 tmp = RREG32(mmVM_L2_CNTL2);
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
854 WREG32(mmVM_L2_CNTL2, tmp);
855
856 field = adev->vm_manager.fragment_size;
857 tmp = RREG32(mmVM_L2_CNTL3);
858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
861 WREG32(mmVM_L2_CNTL3, tmp);
862 /* XXX: set to enable PTE/PDE in system memory */
863 tmp = RREG32(mmVM_L2_CNTL4);
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
876 WREG32(mmVM_L2_CNTL4, tmp);
877 /* setup context0 */
878 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
879 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
880 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
881 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
882 (u32)(adev->dummy_page_addr >> 12));
883 WREG32(mmVM_CONTEXT0_CNTL2, 0);
884 tmp = RREG32(mmVM_CONTEXT0_CNTL);
885 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
886 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
887 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
888 WREG32(mmVM_CONTEXT0_CNTL, tmp);
889
890 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
891 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
892 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
893
894 /* empty context1-15 */
895 /* FIXME start with 4G, once using 2 level pt switch to full
896 * vm size space
897 */
898 /* set vm size, must be a multiple of 4 */
899 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
900 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
901 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
902 if (i < 8)
903 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
904 table_addr >> 12);
905 else
906 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
907 table_addr >> 12);
908 }
909
910 /* enable context1-15 */
911 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
912 (u32)(adev->dummy_page_addr >> 12));
913 WREG32(mmVM_CONTEXT1_CNTL2, 4);
914 tmp = RREG32(mmVM_CONTEXT1_CNTL);
915 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
916 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
917 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
918 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
919 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
920 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
921 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
922 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
925 adev->vm_manager.block_size - 9);
926 WREG32(mmVM_CONTEXT1_CNTL, tmp);
927 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
928 gmc_v8_0_set_fault_enable_default(adev, false);
929 else
930 gmc_v8_0_set_fault_enable_default(adev, true);
931
932 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
933 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
934 (unsigned int)(adev->gmc.gart_size >> 20),
935 (unsigned long long)table_addr);
936 return 0;
937 }
938
gmc_v8_0_gart_init(struct amdgpu_device * adev)939 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
940 {
941 int r;
942
943 if (adev->gart.bo) {
944 WARN(1, "R600 PCIE GART already initialized\n");
945 return 0;
946 }
947 /* Initialize common gart structure */
948 r = amdgpu_gart_init(adev);
949 if (r)
950 return r;
951 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
952 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
953 return amdgpu_gart_table_vram_alloc(adev);
954 }
955
956 /**
957 * gmc_v8_0_gart_disable - gart disable
958 *
959 * @adev: amdgpu_device pointer
960 *
961 * This disables all VM page table (VI).
962 */
gmc_v8_0_gart_disable(struct amdgpu_device * adev)963 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
964 {
965 u32 tmp;
966
967 /* Disable all tables */
968 WREG32(mmVM_CONTEXT0_CNTL, 0);
969 WREG32(mmVM_CONTEXT1_CNTL, 0);
970 /* Setup TLB control */
971 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
972 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
973 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
974 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
975 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
976 /* Setup L2 cache */
977 tmp = RREG32(mmVM_L2_CNTL);
978 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
979 WREG32(mmVM_L2_CNTL, tmp);
980 WREG32(mmVM_L2_CNTL2, 0);
981 }
982
983 /**
984 * gmc_v8_0_vm_decode_fault - print human readable fault info
985 *
986 * @adev: amdgpu_device pointer
987 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
988 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
989 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
990 * @pasid: debug logging only - no functional use
991 *
992 * Print human readable fault information (VI).
993 */
gmc_v8_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client,unsigned int pasid)994 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
995 u32 addr, u32 mc_client, unsigned int pasid)
996 {
997 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
998 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
999 PROTECTIONS);
1000 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1001 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1002 u32 mc_id;
1003
1004 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1005 MEMORY_CLIENT_ID);
1006
1007 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1008 protections, vmid, pasid, addr,
1009 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1010 MEMORY_CLIENT_RW) ?
1011 "write" : "read", block, mc_client, mc_id);
1012 }
1013
gmc_v8_0_convert_vram_type(int mc_seq_vram_type)1014 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1015 {
1016 switch (mc_seq_vram_type) {
1017 case MC_SEQ_MISC0__MT__GDDR1:
1018 return AMDGPU_VRAM_TYPE_GDDR1;
1019 case MC_SEQ_MISC0__MT__DDR2:
1020 return AMDGPU_VRAM_TYPE_DDR2;
1021 case MC_SEQ_MISC0__MT__GDDR3:
1022 return AMDGPU_VRAM_TYPE_GDDR3;
1023 case MC_SEQ_MISC0__MT__GDDR4:
1024 return AMDGPU_VRAM_TYPE_GDDR4;
1025 case MC_SEQ_MISC0__MT__GDDR5:
1026 return AMDGPU_VRAM_TYPE_GDDR5;
1027 case MC_SEQ_MISC0__MT__HBM:
1028 return AMDGPU_VRAM_TYPE_HBM;
1029 case MC_SEQ_MISC0__MT__DDR3:
1030 return AMDGPU_VRAM_TYPE_DDR3;
1031 default:
1032 return AMDGPU_VRAM_TYPE_UNKNOWN;
1033 }
1034 }
1035
gmc_v8_0_early_init(void * handle)1036 static int gmc_v8_0_early_init(void *handle)
1037 {
1038 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039
1040 gmc_v8_0_set_gmc_funcs(adev);
1041 gmc_v8_0_set_irq_funcs(adev);
1042
1043 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1044 adev->gmc.shared_aperture_end =
1045 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1046 adev->gmc.private_aperture_start =
1047 adev->gmc.shared_aperture_end + 1;
1048 adev->gmc.private_aperture_end =
1049 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1050 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1051
1052 return 0;
1053 }
1054
gmc_v8_0_late_init(void * handle)1055 static int gmc_v8_0_late_init(void *handle)
1056 {
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058
1059 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1060 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1061 else
1062 return 0;
1063 }
1064
gmc_v8_0_get_vbios_fb_size(struct amdgpu_device * adev)1065 static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1066 {
1067 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1068 unsigned int size;
1069
1070 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1071 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1072 } else {
1073 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1074
1075 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1076 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1077 4);
1078 }
1079
1080 return size;
1081 }
1082
1083 #define mmMC_SEQ_MISC0_FIJI 0xA71
1084
gmc_v8_0_sw_init(void * handle)1085 static int gmc_v8_0_sw_init(void *handle)
1086 {
1087 int r;
1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089
1090 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1091
1092 if (adev->flags & AMD_IS_APU) {
1093 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1094 } else {
1095 u32 tmp;
1096
1097 if ((adev->asic_type == CHIP_FIJI) ||
1098 (adev->asic_type == CHIP_VEGAM))
1099 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1100 else
1101 tmp = RREG32(mmMC_SEQ_MISC0);
1102 tmp &= MC_SEQ_MISC0__MT__MASK;
1103 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1104 }
1105
1106 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1107 if (r)
1108 return r;
1109
1110 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1111 if (r)
1112 return r;
1113
1114 /* Adjust VM size here.
1115 * Currently set to 4GB ((1 << 20) 4k pages).
1116 * Max GPUVM size for cayman and SI is 40 bits.
1117 */
1118 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1119
1120 /* Set the internal MC address mask
1121 * This is the max address of the GPU's
1122 * internal address space.
1123 */
1124 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1125
1126 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1127 if (r) {
1128 pr_warn("No suitable DMA available\n");
1129 return r;
1130 }
1131 adev->need_swiotlb = drm_need_swiotlb(40);
1132
1133 r = gmc_v8_0_init_microcode(adev);
1134 if (r) {
1135 DRM_ERROR("Failed to load mc firmware!\n");
1136 return r;
1137 }
1138
1139 r = gmc_v8_0_mc_init(adev);
1140 if (r)
1141 return r;
1142
1143 amdgpu_gmc_get_vbios_allocations(adev);
1144
1145 /* Memory manager */
1146 r = amdgpu_bo_init(adev);
1147 if (r)
1148 return r;
1149
1150 r = gmc_v8_0_gart_init(adev);
1151 if (r)
1152 return r;
1153
1154 /*
1155 * number of VMs
1156 * VMID 0 is reserved for System
1157 * amdgpu graphics/compute will use VMIDs 1-7
1158 * amdkfd will use VMIDs 8-15
1159 */
1160 adev->vm_manager.first_kfd_vmid = 8;
1161 amdgpu_vm_manager_init(adev);
1162
1163 /* base offset of vram pages */
1164 if (adev->flags & AMD_IS_APU) {
1165 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1166
1167 tmp <<= 22;
1168 adev->vm_manager.vram_base_offset = tmp;
1169 } else {
1170 adev->vm_manager.vram_base_offset = 0;
1171 }
1172
1173 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1174 GFP_KERNEL);
1175 if (!adev->gmc.vm_fault_info)
1176 return -ENOMEM;
1177 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1178
1179 return 0;
1180 }
1181
gmc_v8_0_sw_fini(void * handle)1182 static int gmc_v8_0_sw_fini(void *handle)
1183 {
1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186 amdgpu_gem_force_release(adev);
1187 amdgpu_vm_manager_fini(adev);
1188 kfree(adev->gmc.vm_fault_info);
1189 amdgpu_gart_table_vram_free(adev);
1190 amdgpu_bo_fini(adev);
1191 amdgpu_ucode_release(&adev->gmc.fw);
1192
1193 return 0;
1194 }
1195
gmc_v8_0_hw_init(void * handle)1196 static int gmc_v8_0_hw_init(void *handle)
1197 {
1198 int r;
1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200
1201 gmc_v8_0_init_golden_registers(adev);
1202
1203 gmc_v8_0_mc_program(adev);
1204
1205 if (adev->asic_type == CHIP_TONGA) {
1206 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1207 if (r) {
1208 DRM_ERROR("Failed to load MC firmware!\n");
1209 return r;
1210 }
1211 } else if (adev->asic_type == CHIP_POLARIS11 ||
1212 adev->asic_type == CHIP_POLARIS10 ||
1213 adev->asic_type == CHIP_POLARIS12) {
1214 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1215 if (r) {
1216 DRM_ERROR("Failed to load MC firmware!\n");
1217 return r;
1218 }
1219 }
1220
1221 r = gmc_v8_0_gart_enable(adev);
1222 if (r)
1223 return r;
1224
1225 if (amdgpu_emu_mode == 1)
1226 return amdgpu_gmc_vram_checking(adev);
1227
1228 return 0;
1229 }
1230
gmc_v8_0_hw_fini(void * handle)1231 static int gmc_v8_0_hw_fini(void *handle)
1232 {
1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1236 gmc_v8_0_gart_disable(adev);
1237
1238 return 0;
1239 }
1240
gmc_v8_0_suspend(void * handle)1241 static int gmc_v8_0_suspend(void *handle)
1242 {
1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245 gmc_v8_0_hw_fini(adev);
1246
1247 return 0;
1248 }
1249
gmc_v8_0_resume(void * handle)1250 static int gmc_v8_0_resume(void *handle)
1251 {
1252 int r;
1253 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254
1255 r = gmc_v8_0_hw_init(adev);
1256 if (r)
1257 return r;
1258
1259 amdgpu_vmid_reset_all(adev);
1260
1261 return 0;
1262 }
1263
gmc_v8_0_is_idle(void * handle)1264 static bool gmc_v8_0_is_idle(void *handle)
1265 {
1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267 u32 tmp = RREG32(mmSRBM_STATUS);
1268
1269 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1270 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1271 return false;
1272
1273 return true;
1274 }
1275
gmc_v8_0_wait_for_idle(void * handle)1276 static int gmc_v8_0_wait_for_idle(void *handle)
1277 {
1278 unsigned int i;
1279 u32 tmp;
1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281
1282 for (i = 0; i < adev->usec_timeout; i++) {
1283 /* read MC_STATUS */
1284 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1285 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1286 SRBM_STATUS__MCC_BUSY_MASK |
1287 SRBM_STATUS__MCD_BUSY_MASK |
1288 SRBM_STATUS__VMC_BUSY_MASK |
1289 SRBM_STATUS__VMC1_BUSY_MASK);
1290 if (!tmp)
1291 return 0;
1292 udelay(1);
1293 }
1294 return -ETIMEDOUT;
1295
1296 }
1297
gmc_v8_0_check_soft_reset(void * handle)1298 static bool gmc_v8_0_check_soft_reset(void *handle)
1299 {
1300 u32 srbm_soft_reset = 0;
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302 u32 tmp = RREG32(mmSRBM_STATUS);
1303
1304 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1305 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1306 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1307
1308 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1309 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1310 if (!(adev->flags & AMD_IS_APU))
1311 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1312 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1313 }
1314
1315 if (srbm_soft_reset) {
1316 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1317 return true;
1318 }
1319
1320 adev->gmc.srbm_soft_reset = 0;
1321
1322 return false;
1323 }
1324
gmc_v8_0_pre_soft_reset(void * handle)1325 static int gmc_v8_0_pre_soft_reset(void *handle)
1326 {
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329 if (!adev->gmc.srbm_soft_reset)
1330 return 0;
1331
1332 gmc_v8_0_mc_stop(adev);
1333 if (gmc_v8_0_wait_for_idle(adev))
1334 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1335
1336 return 0;
1337 }
1338
gmc_v8_0_soft_reset(void * handle)1339 static int gmc_v8_0_soft_reset(void *handle)
1340 {
1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1342 u32 srbm_soft_reset;
1343
1344 if (!adev->gmc.srbm_soft_reset)
1345 return 0;
1346 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1347
1348 if (srbm_soft_reset) {
1349 u32 tmp;
1350
1351 tmp = RREG32(mmSRBM_SOFT_RESET);
1352 tmp |= srbm_soft_reset;
1353 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1354 WREG32(mmSRBM_SOFT_RESET, tmp);
1355 tmp = RREG32(mmSRBM_SOFT_RESET);
1356
1357 udelay(50);
1358
1359 tmp &= ~srbm_soft_reset;
1360 WREG32(mmSRBM_SOFT_RESET, tmp);
1361 tmp = RREG32(mmSRBM_SOFT_RESET);
1362
1363 /* Wait a little for things to settle down */
1364 udelay(50);
1365 }
1366
1367 return 0;
1368 }
1369
gmc_v8_0_post_soft_reset(void * handle)1370 static int gmc_v8_0_post_soft_reset(void *handle)
1371 {
1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373
1374 if (!adev->gmc.srbm_soft_reset)
1375 return 0;
1376
1377 gmc_v8_0_mc_resume(adev);
1378 return 0;
1379 }
1380
gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)1381 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1382 struct amdgpu_irq_src *src,
1383 unsigned int type,
1384 enum amdgpu_interrupt_state state)
1385 {
1386 u32 tmp;
1387 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1388 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1389 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1390 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1391 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1392 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1393 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1394
1395 switch (state) {
1396 case AMDGPU_IRQ_STATE_DISABLE:
1397 /* system context */
1398 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1399 tmp &= ~bits;
1400 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1401 /* VMs */
1402 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1403 tmp &= ~bits;
1404 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1405 break;
1406 case AMDGPU_IRQ_STATE_ENABLE:
1407 /* system context */
1408 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1409 tmp |= bits;
1410 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1411 /* VMs */
1412 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1413 tmp |= bits;
1414 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1415 break;
1416 default:
1417 break;
1418 }
1419
1420 return 0;
1421 }
1422
gmc_v8_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1423 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1424 struct amdgpu_irq_src *source,
1425 struct amdgpu_iv_entry *entry)
1426 {
1427 u32 addr, status, mc_client, vmid;
1428
1429 if (amdgpu_sriov_vf(adev)) {
1430 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1431 entry->src_id, entry->src_data[0]);
1432 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1433 return 0;
1434 }
1435
1436 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1437 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1438 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1439 /* reset addr and status */
1440 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1441
1442 if (!addr && !status)
1443 return 0;
1444
1445 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1446 gmc_v8_0_set_fault_enable_default(adev, false);
1447
1448 if (printk_ratelimit()) {
1449 struct amdgpu_task_info task_info;
1450
1451 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1452 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1453
1454 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1455 entry->src_id, entry->src_data[0], task_info.process_name,
1456 task_info.tgid, task_info.task_name, task_info.pid);
1457 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1458 addr);
1459 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1460 status);
1461 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1462 entry->pasid);
1463 }
1464
1465 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1466 VMID);
1467 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1468 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1469 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1470 u32 protections = REG_GET_FIELD(status,
1471 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1472 PROTECTIONS);
1473
1474 info->vmid = vmid;
1475 info->mc_id = REG_GET_FIELD(status,
1476 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1477 MEMORY_CLIENT_ID);
1478 info->status = status;
1479 info->page_addr = addr;
1480 info->prot_valid = protections & 0x7 ? true : false;
1481 info->prot_read = protections & 0x8 ? true : false;
1482 info->prot_write = protections & 0x10 ? true : false;
1483 info->prot_exec = protections & 0x20 ? true : false;
1484 mb();
1485 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1486 }
1487
1488 return 0;
1489 }
1490
fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1491 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1492 bool enable)
1493 {
1494 uint32_t data;
1495
1496 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1497 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1498 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1499 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1500
1501 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1502 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1503 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1504
1505 data = RREG32(mmMC_HUB_MISC_VM_CG);
1506 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1507 WREG32(mmMC_HUB_MISC_VM_CG, data);
1508
1509 data = RREG32(mmMC_XPB_CLK_GAT);
1510 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1511 WREG32(mmMC_XPB_CLK_GAT, data);
1512
1513 data = RREG32(mmATC_MISC_CG);
1514 data |= ATC_MISC_CG__ENABLE_MASK;
1515 WREG32(mmATC_MISC_CG, data);
1516
1517 data = RREG32(mmMC_CITF_MISC_WR_CG);
1518 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1519 WREG32(mmMC_CITF_MISC_WR_CG, data);
1520
1521 data = RREG32(mmMC_CITF_MISC_RD_CG);
1522 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1523 WREG32(mmMC_CITF_MISC_RD_CG, data);
1524
1525 data = RREG32(mmMC_CITF_MISC_VM_CG);
1526 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1527 WREG32(mmMC_CITF_MISC_VM_CG, data);
1528
1529 data = RREG32(mmVM_L2_CG);
1530 data |= VM_L2_CG__ENABLE_MASK;
1531 WREG32(mmVM_L2_CG, data);
1532 } else {
1533 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1534 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1535 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1536
1537 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1538 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1539 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1540
1541 data = RREG32(mmMC_HUB_MISC_VM_CG);
1542 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1543 WREG32(mmMC_HUB_MISC_VM_CG, data);
1544
1545 data = RREG32(mmMC_XPB_CLK_GAT);
1546 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1547 WREG32(mmMC_XPB_CLK_GAT, data);
1548
1549 data = RREG32(mmATC_MISC_CG);
1550 data &= ~ATC_MISC_CG__ENABLE_MASK;
1551 WREG32(mmATC_MISC_CG, data);
1552
1553 data = RREG32(mmMC_CITF_MISC_WR_CG);
1554 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1555 WREG32(mmMC_CITF_MISC_WR_CG, data);
1556
1557 data = RREG32(mmMC_CITF_MISC_RD_CG);
1558 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1559 WREG32(mmMC_CITF_MISC_RD_CG, data);
1560
1561 data = RREG32(mmMC_CITF_MISC_VM_CG);
1562 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1563 WREG32(mmMC_CITF_MISC_VM_CG, data);
1564
1565 data = RREG32(mmVM_L2_CG);
1566 data &= ~VM_L2_CG__ENABLE_MASK;
1567 WREG32(mmVM_L2_CG, data);
1568 }
1569 }
1570
fiji_update_mc_light_sleep(struct amdgpu_device * adev,bool enable)1571 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1572 bool enable)
1573 {
1574 uint32_t data;
1575
1576 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1577 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1578 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1579 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1580
1581 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1582 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1583 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1584
1585 data = RREG32(mmMC_HUB_MISC_VM_CG);
1586 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1587 WREG32(mmMC_HUB_MISC_VM_CG, data);
1588
1589 data = RREG32(mmMC_XPB_CLK_GAT);
1590 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1591 WREG32(mmMC_XPB_CLK_GAT, data);
1592
1593 data = RREG32(mmATC_MISC_CG);
1594 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1595 WREG32(mmATC_MISC_CG, data);
1596
1597 data = RREG32(mmMC_CITF_MISC_WR_CG);
1598 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1599 WREG32(mmMC_CITF_MISC_WR_CG, data);
1600
1601 data = RREG32(mmMC_CITF_MISC_RD_CG);
1602 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1603 WREG32(mmMC_CITF_MISC_RD_CG, data);
1604
1605 data = RREG32(mmMC_CITF_MISC_VM_CG);
1606 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1607 WREG32(mmMC_CITF_MISC_VM_CG, data);
1608
1609 data = RREG32(mmVM_L2_CG);
1610 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1611 WREG32(mmVM_L2_CG, data);
1612 } else {
1613 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1614 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1615 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1616
1617 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1618 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1619 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1620
1621 data = RREG32(mmMC_HUB_MISC_VM_CG);
1622 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1623 WREG32(mmMC_HUB_MISC_VM_CG, data);
1624
1625 data = RREG32(mmMC_XPB_CLK_GAT);
1626 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1627 WREG32(mmMC_XPB_CLK_GAT, data);
1628
1629 data = RREG32(mmATC_MISC_CG);
1630 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1631 WREG32(mmATC_MISC_CG, data);
1632
1633 data = RREG32(mmMC_CITF_MISC_WR_CG);
1634 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1635 WREG32(mmMC_CITF_MISC_WR_CG, data);
1636
1637 data = RREG32(mmMC_CITF_MISC_RD_CG);
1638 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1639 WREG32(mmMC_CITF_MISC_RD_CG, data);
1640
1641 data = RREG32(mmMC_CITF_MISC_VM_CG);
1642 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1643 WREG32(mmMC_CITF_MISC_VM_CG, data);
1644
1645 data = RREG32(mmVM_L2_CG);
1646 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1647 WREG32(mmVM_L2_CG, data);
1648 }
1649 }
1650
gmc_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1651 static int gmc_v8_0_set_clockgating_state(void *handle,
1652 enum amd_clockgating_state state)
1653 {
1654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1655
1656 if (amdgpu_sriov_vf(adev))
1657 return 0;
1658
1659 switch (adev->asic_type) {
1660 case CHIP_FIJI:
1661 fiji_update_mc_medium_grain_clock_gating(adev,
1662 state == AMD_CG_STATE_GATE);
1663 fiji_update_mc_light_sleep(adev,
1664 state == AMD_CG_STATE_GATE);
1665 break;
1666 default:
1667 break;
1668 }
1669 return 0;
1670 }
1671
gmc_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)1672 static int gmc_v8_0_set_powergating_state(void *handle,
1673 enum amd_powergating_state state)
1674 {
1675 return 0;
1676 }
1677
gmc_v8_0_get_clockgating_state(void * handle,u64 * flags)1678 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)
1679 {
1680 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1681 int data;
1682
1683 if (amdgpu_sriov_vf(adev))
1684 *flags = 0;
1685
1686 /* AMD_CG_SUPPORT_MC_MGCG */
1687 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1688 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1689 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1690
1691 /* AMD_CG_SUPPORT_MC_LS */
1692 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1693 *flags |= AMD_CG_SUPPORT_MC_LS;
1694 }
1695
1696 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1697 .name = "gmc_v8_0",
1698 .early_init = gmc_v8_0_early_init,
1699 .late_init = gmc_v8_0_late_init,
1700 .sw_init = gmc_v8_0_sw_init,
1701 .sw_fini = gmc_v8_0_sw_fini,
1702 .hw_init = gmc_v8_0_hw_init,
1703 .hw_fini = gmc_v8_0_hw_fini,
1704 .suspend = gmc_v8_0_suspend,
1705 .resume = gmc_v8_0_resume,
1706 .is_idle = gmc_v8_0_is_idle,
1707 .wait_for_idle = gmc_v8_0_wait_for_idle,
1708 .check_soft_reset = gmc_v8_0_check_soft_reset,
1709 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1710 .soft_reset = gmc_v8_0_soft_reset,
1711 .post_soft_reset = gmc_v8_0_post_soft_reset,
1712 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1713 .set_powergating_state = gmc_v8_0_set_powergating_state,
1714 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1715 };
1716
1717 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1718 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1719 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1720 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1721 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1722 .set_prt = gmc_v8_0_set_prt,
1723 .get_vm_pde = gmc_v8_0_get_vm_pde,
1724 .get_vm_pte = gmc_v8_0_get_vm_pte,
1725 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1726 };
1727
1728 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1729 .set = gmc_v8_0_vm_fault_interrupt_state,
1730 .process = gmc_v8_0_process_interrupt,
1731 };
1732
gmc_v8_0_set_gmc_funcs(struct amdgpu_device * adev)1733 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1734 {
1735 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1736 }
1737
gmc_v8_0_set_irq_funcs(struct amdgpu_device * adev)1738 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1739 {
1740 adev->gmc.vm_fault.num_types = 1;
1741 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1742 }
1743
1744 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = {
1745 .type = AMD_IP_BLOCK_TYPE_GMC,
1746 .major = 8,
1747 .minor = 0,
1748 .rev = 0,
1749 .funcs = &gmc_v8_0_ip_funcs,
1750 };
1751
1752 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = {
1753 .type = AMD_IP_BLOCK_TYPE_GMC,
1754 .major = 8,
1755 .minor = 1,
1756 .rev = 0,
1757 .funcs = &gmc_v8_0_ip_funcs,
1758 };
1759
1760 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = {
1761 .type = AMD_IP_BLOCK_TYPE_GMC,
1762 .major = 8,
1763 .minor = 5,
1764 .rev = 0,
1765 .funcs = &gmc_v8_0_ip_funcs,
1766 };
1767