1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #ifndef __RTL_WIFI_H__
5 #define __RTL_WIFI_H__
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/sched.h>
10 #include <linux/firmware.h>
11 #include <linux/etherdevice.h>
12 #include <linux/vmalloc.h>
13 #include <linux/usb.h>
14 #include <net/mac80211.h>
15 #include <linux/completion.h>
16 #include <linux/bitfield.h>
17 #include "debug.h"
18
19 #define MASKBYTE0 0xff
20 #define MASKBYTE1 0xff00
21 #define MASKBYTE2 0xff0000
22 #define MASKBYTE3 0xff000000
23 #define MASKHWORD 0xffff0000
24 #define MASKLWORD 0x0000ffff
25 #define MASKDWORD 0xffffffff
26 #define MASK12BITS 0xfff
27 #define MASKH4BITS 0xf0000000
28 #define MASKOFDM_D 0xffc00000
29 #define MASKCCK 0x3f3f3f3f
30
31 #define MASK4BITS 0x0f
32 #define MASK20BITS 0xfffff
33 #define RFREG_OFFSET_MASK 0xfffff
34
35 #define MASKBYTE0 0xff
36 #define MASKBYTE1 0xff00
37 #define MASKBYTE2 0xff0000
38 #define MASKBYTE3 0xff000000
39 #define MASKHWORD 0xffff0000
40 #define MASKLWORD 0x0000ffff
41 #define MASKDWORD 0xffffffff
42 #define MASK12BITS 0xfff
43 #define MASKH4BITS 0xf0000000
44 #define MASKOFDM_D 0xffc00000
45 #define MASKCCK 0x3f3f3f3f
46
47 #define MASK4BITS 0x0f
48 #define MASK20BITS 0xfffff
49 #define RFREG_OFFSET_MASK 0xfffff
50
51 #define RF_CHANGE_BY_INIT 0
52 #define RF_CHANGE_BY_IPS BIT(28)
53 #define RF_CHANGE_BY_PS BIT(29)
54 #define RF_CHANGE_BY_HW BIT(30)
55 #define RF_CHANGE_BY_SW BIT(31)
56
57 #define IQK_ADDA_REG_NUM 16
58 #define IQK_MAC_REG_NUM 4
59 #define IQK_THRESHOLD 8
60
61 #define MAX_KEY_LEN 61
62 #define KEY_BUF_SIZE 5
63
64 /* QoS related. */
65 /*aci: 0x00 Best Effort*/
66 /*aci: 0x01 Background*/
67 /*aci: 0x10 Video*/
68 /*aci: 0x11 Voice*/
69 /*Max: define total number.*/
70 #define AC0_BE 0
71 #define AC1_BK 1
72 #define AC2_VI 2
73 #define AC3_VO 3
74 #define AC_MAX 4
75 #define QOS_QUEUE_NUM 4
76 #define RTL_MAC80211_NUM_QUEUE 5
77 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
78 #define RTL_USB_MAX_RX_COUNT 100
79 #define QBSS_LOAD_SIZE 5
80 #define MAX_WMMELE_LENGTH 64
81 #define ASPM_L1_LATENCY 7
82
83 #define TOTAL_CAM_ENTRY 32
84
85 /*slot time for 11g. */
86 #define RTL_SLOT_TIME_9 9
87 #define RTL_SLOT_TIME_20 20
88
89 /*related to tcp/ip. */
90 #define SNAP_SIZE 6
91 #define PROTOC_TYPE_SIZE 2
92
93 /*related with 802.11 frame*/
94 #define MAC80211_3ADDR_LEN 24
95 #define MAC80211_4ADDR_LEN 30
96
97 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
98 #define CHANNEL_MAX_NUMBER_2G 14
99 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
100 *"phy_GetChnlGroup8812A" and
101 * "Hal_ReadTxPowerInfo8812A"
102 */
103 #define CHANNEL_MAX_NUMBER_5G_80M 7
104 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
105 #define MAX_PG_GROUP 13
106 #define CHANNEL_GROUP_MAX_2G 3
107 #define CHANNEL_GROUP_IDX_5GL 3
108 #define CHANNEL_GROUP_IDX_5GM 6
109 #define CHANNEL_GROUP_IDX_5GH 9
110 #define CHANNEL_GROUP_MAX_5G 9
111 #define AVG_THERMAL_NUM 8
112 #define AVG_THERMAL_NUM_88E 4
113 #define AVG_THERMAL_NUM_8723BE 4
114 #define MAX_TID_COUNT 9
115
116 /* for early mode */
117 #define FCS_LEN 4
118 #define EM_HDR_LEN 8
119
120 enum rtl8192c_h2c_cmd {
121 H2C_AP_OFFLOAD = 0,
122 H2C_SETPWRMODE = 1,
123 H2C_JOINBSSRPT = 2,
124 H2C_RSVDPAGE = 3,
125 H2C_RSSI_REPORT = 5,
126 H2C_RA_MASK = 6,
127 H2C_MACID_PS_MODE = 7,
128 H2C_P2P_PS_OFFLOAD = 8,
129 H2C_MAC_MODE_SEL = 9,
130 H2C_PWRM = 15,
131 H2C_P2P_PS_CTW_CMD = 24,
132 MAX_H2CCMD
133 };
134
135 enum {
136 H2C_BT_PORT_ID = 0x71,
137 };
138
139 enum rtl_c2h_evt_v1 {
140 C2H_DBG = 0,
141 C2H_LB = 1,
142 C2H_TXBF = 2,
143 C2H_TX_REPORT = 3,
144 C2H_BT_INFO = 9,
145 C2H_BT_MP = 11,
146 C2H_RA_RPT = 12,
147
148 C2H_FW_SWCHNL = 0x10,
149 C2H_IQK_FINISH = 0x11,
150
151 C2H_EXT_V2 = 0xFF,
152 };
153
154 enum rtl_c2h_evt_v2 {
155 C2H_V2_CCX_RPT = 0x0F,
156 };
157
158 #define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; })
159 #define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; })
160 #define C2H_DATA_OFFSET 2
161 #define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; })
162
163 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6])
164 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0)
165 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F)
166 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6])
167 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0)
168 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F)
169
170 #define MAX_TX_COUNT 4
171 #define MAX_REGULATION_NUM 4
172 #define MAX_RF_PATH_NUM 4
173 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
174 #define MAX_2_4G_BANDWIDTH_NUM 4
175 #define MAX_5G_BANDWIDTH_NUM 4
176 #define MAX_RF_PATH 4
177 #define MAX_CHNL_GROUP_24G 6
178 #define MAX_CHNL_GROUP_5G 14
179
180 #define TX_PWR_BY_RATE_NUM_BAND 2
181 #define TX_PWR_BY_RATE_NUM_RF 4
182 #define TX_PWR_BY_RATE_NUM_SECTION 12
183 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */
184 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
185 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
186
187 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
188
189 #define DEL_SW_IDX_SZ 30
190
191 /* For now, it's just for 8192ee
192 * but not OK yet, keep it 0
193 */
194 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
195
196 enum rf_tx_num {
197 RF_1TX = 0,
198 RF_2TX,
199 RF_MAX_TX_NUM,
200 RF_TX_NUM_NONIMPLEMENT,
201 };
202
203 #define PACKET_NORMAL 0
204 #define PACKET_DHCP 1
205 #define PACKET_ARP 2
206 #define PACKET_EAPOL 3
207
208 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
209 #define RSVD_WOL_PATTERN_NUM 1
210 #define WKFMCAM_ADDR_NUM 6
211 #define WKFMCAM_SIZE 24
212
213 #define MAX_WOL_BIT_MASK_SIZE 16
214 /* MIN LEN keeps 13 here */
215 #define MIN_WOL_PATTERN_SIZE 13
216 #define MAX_WOL_PATTERN_SIZE 128
217
218 #define WAKE_ON_MAGIC_PACKET BIT(0)
219 #define WAKE_ON_PATTERN_MATCH BIT(1)
220
221 #define WOL_REASON_PTK_UPDATE BIT(0)
222 #define WOL_REASON_GTK_UPDATE BIT(1)
223 #define WOL_REASON_DISASSOC BIT(2)
224 #define WOL_REASON_DEAUTH BIT(3)
225 #define WOL_REASON_AP_LOST BIT(4)
226 #define WOL_REASON_MAGIC_PKT BIT(5)
227 #define WOL_REASON_UNICAST_PKT BIT(6)
228 #define WOL_REASON_PATTERN_PKT BIT(7)
229 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
230 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
231 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
232
233 struct rtlwifi_firmware_header {
234 __le16 signature;
235 u8 category;
236 u8 function;
237 __le16 version;
238 u8 subversion;
239 u8 rsvd1;
240 u8 month;
241 u8 date;
242 u8 hour;
243 u8 minute;
244 __le16 ramcodesize;
245 __le16 rsvd2;
246 __le32 svnindex;
247 __le32 rsvd3;
248 __le32 rsvd4;
249 __le32 rsvd5;
250 };
251
252 struct txpower_info_2g {
253 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
254 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
255 /*If only one tx, only BW20 and OFDM are used.*/
256 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
261 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 };
263
264 struct txpower_info_5g {
265 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
266 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
267 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
268 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
269 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
270 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
271 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
272 };
273
274 enum rate_section {
275 CCK = 0,
276 OFDM,
277 HT_MCS0_MCS7,
278 HT_MCS8_MCS15,
279 VHT_1SSMCS0_1SSMCS9,
280 VHT_2SSMCS0_2SSMCS9,
281 MAX_RATE_SECTION,
282 };
283
284 enum intf_type {
285 INTF_PCI = 0,
286 INTF_USB = 1,
287 };
288
289 enum radio_path {
290 RF90_PATH_A = 0,
291 RF90_PATH_B = 1,
292 RF90_PATH_C = 2,
293 RF90_PATH_D = 3,
294 };
295
296 enum radio_mask {
297 RF_MASK_A = BIT(0),
298 RF_MASK_B = BIT(1),
299 RF_MASK_C = BIT(2),
300 RF_MASK_D = BIT(3),
301 };
302
303 enum regulation_txpwr_lmt {
304 TXPWR_LMT_FCC = 0,
305 TXPWR_LMT_MKK = 1,
306 TXPWR_LMT_ETSI = 2,
307 TXPWR_LMT_WW = 3,
308
309 TXPWR_LMT_MAX_REGULATION_NUM = 4
310 };
311
312 enum rt_eeprom_type {
313 EEPROM_93C46,
314 EEPROM_93C56,
315 EEPROM_BOOT_EFUSE,
316 };
317
318 enum ttl_status {
319 RTL_STATUS_INTERFACE_START = 0,
320 };
321
322 enum hardware_type {
323 HARDWARE_TYPE_RTL8192E,
324 HARDWARE_TYPE_RTL8192U,
325 HARDWARE_TYPE_RTL8192SE,
326 HARDWARE_TYPE_RTL8192SU,
327 HARDWARE_TYPE_RTL8192CE,
328 HARDWARE_TYPE_RTL8192CU,
329 HARDWARE_TYPE_RTL8192DE,
330 HARDWARE_TYPE_RTL8192DU,
331 HARDWARE_TYPE_RTL8723AE,
332 HARDWARE_TYPE_RTL8723U,
333 HARDWARE_TYPE_RTL8188EE,
334 HARDWARE_TYPE_RTL8723BE,
335 HARDWARE_TYPE_RTL8192EE,
336 HARDWARE_TYPE_RTL8821AE,
337 HARDWARE_TYPE_RTL8812AE,
338 HARDWARE_TYPE_RTL8822BE,
339
340 /* keep it last */
341 HARDWARE_TYPE_NUM
342 };
343
344 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
345 #define IS_NEW_GENERATION_IC(rtlpriv) \
346 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
347 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
349 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
350 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
351 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
352 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
353 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
354 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
355 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
356 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
357 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
358 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
359 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
360 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
361
362 #define RX_HAL_IS_CCK_RATE(rxmcs) \
363 ((rxmcs) == DESC_RATE1M || \
364 (rxmcs) == DESC_RATE2M || \
365 (rxmcs) == DESC_RATE5_5M || \
366 (rxmcs) == DESC_RATE11M)
367
368 enum scan_operation_backup_opt {
369 SCAN_OPT_BACKUP = 0,
370 SCAN_OPT_BACKUP_BAND0 = 0,
371 SCAN_OPT_BACKUP_BAND1,
372 SCAN_OPT_RESTORE,
373 SCAN_OPT_MAX
374 };
375
376 /*RF state.*/
377 enum rf_pwrstate {
378 ERFON,
379 ERFSLEEP,
380 ERFOFF
381 };
382
383 struct bb_reg_def {
384 u32 rfintfs;
385 u32 rfintfi;
386 u32 rfintfo;
387 u32 rfintfe;
388 u32 rf3wire_offset;
389 u32 rflssi_select;
390 u32 rftxgain_stage;
391 u32 rfhssi_para1;
392 u32 rfhssi_para2;
393 u32 rfsw_ctrl;
394 u32 rfagc_control1;
395 u32 rfagc_control2;
396 u32 rfrxiq_imbal;
397 u32 rfrx_afe;
398 u32 rftxiq_imbal;
399 u32 rftx_afe;
400 u32 rf_rb; /* rflssi_readback */
401 u32 rf_rbpi; /* rflssi_readbackpi */
402 };
403
404 enum io_type {
405 IO_CMD_PAUSE_DM_BY_SCAN = 0,
406 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
407 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
408 IO_CMD_RESUME_DM_BY_SCAN = 2,
409 };
410
411 enum hw_variables {
412 HW_VAR_ETHER_ADDR = 0x0,
413 HW_VAR_MULTICAST_REG = 0x1,
414 HW_VAR_BASIC_RATE = 0x2,
415 HW_VAR_BSSID = 0x3,
416 HW_VAR_MEDIA_STATUS = 0x4,
417 HW_VAR_SECURITY_CONF = 0x5,
418 HW_VAR_BEACON_INTERVAL = 0x6,
419 HW_VAR_ATIM_WINDOW = 0x7,
420 HW_VAR_LISTEN_INTERVAL = 0x8,
421 HW_VAR_CS_COUNTER = 0x9,
422 HW_VAR_DEFAULTKEY0 = 0xa,
423 HW_VAR_DEFAULTKEY1 = 0xb,
424 HW_VAR_DEFAULTKEY2 = 0xc,
425 HW_VAR_DEFAULTKEY3 = 0xd,
426 HW_VAR_SIFS = 0xe,
427 HW_VAR_R2T_SIFS = 0xf,
428 HW_VAR_DIFS = 0x10,
429 HW_VAR_EIFS = 0x11,
430 HW_VAR_SLOT_TIME = 0x12,
431 HW_VAR_ACK_PREAMBLE = 0x13,
432 HW_VAR_CW_CONFIG = 0x14,
433 HW_VAR_CW_VALUES = 0x15,
434 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
435 HW_VAR_CONTENTION_WINDOW = 0x17,
436 HW_VAR_RETRY_COUNT = 0x18,
437 HW_VAR_TR_SWITCH = 0x19,
438 HW_VAR_COMMAND = 0x1a,
439 HW_VAR_WPA_CONFIG = 0x1b,
440 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
441 HW_VAR_SHORTGI_DENSITY = 0x1d,
442 HW_VAR_AMPDU_FACTOR = 0x1e,
443 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
444 HW_VAR_AC_PARAM = 0x20,
445 HW_VAR_ACM_CTRL = 0x21,
446 HW_VAR_DIS_REQ_QSIZE = 0x22,
447 HW_VAR_CCX_CHNL_LOAD = 0x23,
448 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
449 HW_VAR_CCX_CLM_NHM = 0x25,
450 HW_VAR_TXOPLIMIT = 0x26,
451 HW_VAR_TURBO_MODE = 0x27,
452 HW_VAR_RF_STATE = 0x28,
453 HW_VAR_RF_OFF_BY_HW = 0x29,
454 HW_VAR_BUS_SPEED = 0x2a,
455 HW_VAR_SET_DEV_POWER = 0x2b,
456
457 HW_VAR_RCR = 0x2c,
458 HW_VAR_RATR_0 = 0x2d,
459 HW_VAR_RRSR = 0x2e,
460 HW_VAR_CPU_RST = 0x2f,
461 HW_VAR_CHECK_BSSID = 0x30,
462 HW_VAR_LBK_MODE = 0x31,
463 HW_VAR_AES_11N_FIX = 0x32,
464 HW_VAR_USB_RX_AGGR = 0x33,
465 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
466 HW_VAR_RETRY_LIMIT = 0x35,
467 HW_VAR_INIT_TX_RATE = 0x36,
468 HW_VAR_TX_RATE_REG = 0x37,
469 HW_VAR_EFUSE_USAGE = 0x38,
470 HW_VAR_EFUSE_BYTES = 0x39,
471 HW_VAR_AUTOLOAD_STATUS = 0x3a,
472 HW_VAR_RF_2R_DISABLE = 0x3b,
473 HW_VAR_SET_RPWM = 0x3c,
474 HW_VAR_H2C_FW_PWRMODE = 0x3d,
475 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
476 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
477 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
478 HW_VAR_FW_PSMODE_STATUS = 0x41,
479 HW_VAR_INIT_RTS_RATE = 0x42,
480 HW_VAR_RESUME_CLK_ON = 0x43,
481 HW_VAR_FW_LPS_ACTION = 0x44,
482 HW_VAR_1X1_RECV_COMBINE = 0x45,
483 HW_VAR_STOP_SEND_BEACON = 0x46,
484 HW_VAR_TSF_TIMER = 0x47,
485 HW_VAR_IO_CMD = 0x48,
486
487 HW_VAR_RF_RECOVERY = 0x49,
488 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
489 HW_VAR_WF_MASK = 0x4b,
490 HW_VAR_WF_CRC = 0x4c,
491 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
492 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
493 HW_VAR_RESET_WFCRC = 0x4f,
494
495 HW_VAR_HANDLE_FW_C2H = 0x50,
496 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
497 HW_VAR_AID = 0x52,
498 HW_VAR_HW_SEQ_ENABLE = 0x53,
499 HW_VAR_CORRECT_TSF = 0x54,
500 HW_VAR_BCN_VALID = 0x55,
501 HW_VAR_FWLPS_RF_ON = 0x56,
502 HW_VAR_DUAL_TSF_RST = 0x57,
503 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
504 HW_VAR_INT_MIGRATION = 0x59,
505 HW_VAR_INT_AC = 0x5a,
506 HW_VAR_RF_TIMING = 0x5b,
507
508 HAL_DEF_WOWLAN = 0x5c,
509 HW_VAR_MRC = 0x5d,
510 HW_VAR_KEEP_ALIVE = 0x5e,
511 HW_VAR_NAV_UPPER = 0x5f,
512
513 HW_VAR_MGT_FILTER = 0x60,
514 HW_VAR_CTRL_FILTER = 0x61,
515 HW_VAR_DATA_FILTER = 0x62,
516 };
517
518 enum rt_media_status {
519 RT_MEDIA_DISCONNECT = 0,
520 RT_MEDIA_CONNECT = 1
521 };
522
523 enum rt_oem_id {
524 RT_CID_DEFAULT = 0,
525 RT_CID_8187_ALPHA0 = 1,
526 RT_CID_8187_SERCOMM_PS = 2,
527 RT_CID_8187_HW_LED = 3,
528 RT_CID_8187_NETGEAR = 4,
529 RT_CID_WHQL = 5,
530 RT_CID_819X_CAMEO = 6,
531 RT_CID_819X_RUNTOP = 7,
532 RT_CID_819X_SENAO = 8,
533 RT_CID_TOSHIBA = 9,
534 RT_CID_819X_NETCORE = 10,
535 RT_CID_NETTRONIX = 11,
536 RT_CID_DLINK = 12,
537 RT_CID_PRONET = 13,
538 RT_CID_COREGA = 14,
539 RT_CID_819X_ALPHA = 15,
540 RT_CID_819X_SITECOM = 16,
541 RT_CID_CCX = 17,
542 RT_CID_819X_LENOVO = 18,
543 RT_CID_819X_QMI = 19,
544 RT_CID_819X_EDIMAX_BELKIN = 20,
545 RT_CID_819X_SERCOMM_BELKIN = 21,
546 RT_CID_819X_CAMEO1 = 22,
547 RT_CID_819X_MSI = 23,
548 RT_CID_819X_ACER = 24,
549 RT_CID_819X_HP = 27,
550 RT_CID_819X_CLEVO = 28,
551 RT_CID_819X_ARCADYAN_BELKIN = 29,
552 RT_CID_819X_SAMSUNG = 30,
553 RT_CID_819X_WNC_COREGA = 31,
554 RT_CID_819X_FOXCOON = 32,
555 RT_CID_819X_DELL = 33,
556 RT_CID_819X_PRONETS = 34,
557 RT_CID_819X_EDIMAX_ASUS = 35,
558 RT_CID_NETGEAR = 36,
559 RT_CID_PLANEX = 37,
560 RT_CID_CC_C = 38,
561 RT_CID_LENOVO_CHINA = 40,
562 };
563
564 enum hw_descs {
565 HW_DESC_OWN,
566 HW_DESC_RXOWN,
567 HW_DESC_TX_NEXTDESC_ADDR,
568 HW_DESC_TXBUFF_ADDR,
569 HW_DESC_RXBUFF_ADDR,
570 HW_DESC_RXPKT_LEN,
571 HW_DESC_RXERO,
572 HW_DESC_RX_PREPARE,
573 };
574
575 enum prime_sc {
576 PRIME_CHNL_OFFSET_DONT_CARE = 0,
577 PRIME_CHNL_OFFSET_LOWER = 1,
578 PRIME_CHNL_OFFSET_UPPER = 2,
579 };
580
581 enum rf_type {
582 RF_1T1R = 0,
583 RF_1T2R = 1,
584 RF_2T2R = 2,
585 RF_2T2R_GREEN = 3,
586 RF_2T3R = 4,
587 RF_2T4R = 5,
588 RF_3T3R = 6,
589 RF_3T4R = 7,
590 RF_4T4R = 8,
591 };
592
593 enum ht_channel_width {
594 HT_CHANNEL_WIDTH_20 = 0,
595 HT_CHANNEL_WIDTH_20_40 = 1,
596 HT_CHANNEL_WIDTH_80 = 2,
597 HT_CHANNEL_WIDTH_MAX,
598 };
599
600 /* Ref: 802.11i spec D10.0 7.3.2.25.1
601 * Cipher Suites Encryption Algorithms
602 */
603 enum rt_enc_alg {
604 NO_ENCRYPTION = 0,
605 WEP40_ENCRYPTION = 1,
606 TKIP_ENCRYPTION = 2,
607 RSERVED_ENCRYPTION = 3,
608 AESCCMP_ENCRYPTION = 4,
609 WEP104_ENCRYPTION = 5,
610 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
611 };
612
613 enum rtl_hal_state {
614 _HAL_STATE_STOP = 0,
615 _HAL_STATE_START = 1,
616 };
617
618 enum rtl_desc_rate {
619 DESC_RATE1M = 0x00,
620 DESC_RATE2M = 0x01,
621 DESC_RATE5_5M = 0x02,
622 DESC_RATE11M = 0x03,
623
624 DESC_RATE6M = 0x04,
625 DESC_RATE9M = 0x05,
626 DESC_RATE12M = 0x06,
627 DESC_RATE18M = 0x07,
628 DESC_RATE24M = 0x08,
629 DESC_RATE36M = 0x09,
630 DESC_RATE48M = 0x0a,
631 DESC_RATE54M = 0x0b,
632
633 DESC_RATEMCS0 = 0x0c,
634 DESC_RATEMCS1 = 0x0d,
635 DESC_RATEMCS2 = 0x0e,
636 DESC_RATEMCS3 = 0x0f,
637 DESC_RATEMCS4 = 0x10,
638 DESC_RATEMCS5 = 0x11,
639 DESC_RATEMCS6 = 0x12,
640 DESC_RATEMCS7 = 0x13,
641 DESC_RATEMCS8 = 0x14,
642 DESC_RATEMCS9 = 0x15,
643 DESC_RATEMCS10 = 0x16,
644 DESC_RATEMCS11 = 0x17,
645 DESC_RATEMCS12 = 0x18,
646 DESC_RATEMCS13 = 0x19,
647 DESC_RATEMCS14 = 0x1a,
648 DESC_RATEMCS15 = 0x1b,
649 DESC_RATEMCS15_SG = 0x1c,
650 DESC_RATEMCS32 = 0x20,
651
652 DESC_RATEVHT1SS_MCS0 = 0x2c,
653 DESC_RATEVHT1SS_MCS1 = 0x2d,
654 DESC_RATEVHT1SS_MCS2 = 0x2e,
655 DESC_RATEVHT1SS_MCS3 = 0x2f,
656 DESC_RATEVHT1SS_MCS4 = 0x30,
657 DESC_RATEVHT1SS_MCS5 = 0x31,
658 DESC_RATEVHT1SS_MCS6 = 0x32,
659 DESC_RATEVHT1SS_MCS7 = 0x33,
660 DESC_RATEVHT1SS_MCS8 = 0x34,
661 DESC_RATEVHT1SS_MCS9 = 0x35,
662 DESC_RATEVHT2SS_MCS0 = 0x36,
663 DESC_RATEVHT2SS_MCS1 = 0x37,
664 DESC_RATEVHT2SS_MCS2 = 0x38,
665 DESC_RATEVHT2SS_MCS3 = 0x39,
666 DESC_RATEVHT2SS_MCS4 = 0x3a,
667 DESC_RATEVHT2SS_MCS5 = 0x3b,
668 DESC_RATEVHT2SS_MCS6 = 0x3c,
669 DESC_RATEVHT2SS_MCS7 = 0x3d,
670 DESC_RATEVHT2SS_MCS8 = 0x3e,
671 DESC_RATEVHT2SS_MCS9 = 0x3f,
672 };
673
674 enum rtl_var_map {
675 /*reg map */
676 SYS_ISO_CTRL = 0,
677 SYS_FUNC_EN,
678 SYS_CLK,
679 MAC_RCR_AM,
680 MAC_RCR_AB,
681 MAC_RCR_ACRC32,
682 MAC_RCR_ACF,
683 MAC_RCR_AAP,
684 MAC_HIMR,
685 MAC_HIMRE,
686 MAC_HSISR,
687
688 /*efuse map */
689 EFUSE_TEST,
690 EFUSE_CTRL,
691 EFUSE_CLK,
692 EFUSE_CLK_CTRL,
693 EFUSE_PWC_EV12V,
694 EFUSE_FEN_ELDR,
695 EFUSE_LOADER_CLK_EN,
696 EFUSE_ANA8M,
697 EFUSE_HWSET_MAX_SIZE,
698 EFUSE_MAX_SECTION_MAP,
699 EFUSE_REAL_CONTENT_SIZE,
700 EFUSE_OOB_PROTECT_BYTES_LEN,
701 EFUSE_ACCESS,
702
703 /*CAM map */
704 RWCAM,
705 WCAMI,
706 RCAMO,
707 CAMDBG,
708 SECR,
709 SEC_CAM_NONE,
710 SEC_CAM_WEP40,
711 SEC_CAM_TKIP,
712 SEC_CAM_AES,
713 SEC_CAM_WEP104,
714
715 /*IMR map */
716 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
717 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
718 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
719 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
720 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
721 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
722 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
723 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
724 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
725 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
726 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
727 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
728 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
729 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
730 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
731 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
732 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
733 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
734 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
735 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
736 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
737 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
738 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
739 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
740 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
741 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
742 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
743 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
744 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
745 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
746 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
747 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
748 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
749 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
750 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
751 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
752 * RTL_IMR_TBDER)
753 */
754 RTL_IMR_C2HCMD, /*fw interrupt*/
755
756 /*CCK Rates, TxHT = 0 */
757 RTL_RC_CCK_RATE1M,
758 RTL_RC_CCK_RATE2M,
759 RTL_RC_CCK_RATE5_5M,
760 RTL_RC_CCK_RATE11M,
761
762 /*OFDM Rates, TxHT = 0 */
763 RTL_RC_OFDM_RATE6M,
764 RTL_RC_OFDM_RATE9M,
765 RTL_RC_OFDM_RATE12M,
766 RTL_RC_OFDM_RATE18M,
767 RTL_RC_OFDM_RATE24M,
768 RTL_RC_OFDM_RATE36M,
769 RTL_RC_OFDM_RATE48M,
770 RTL_RC_OFDM_RATE54M,
771
772 RTL_RC_HT_RATEMCS7,
773 RTL_RC_HT_RATEMCS15,
774
775 RTL_RC_VHT_RATE_1SS_MCS7,
776 RTL_RC_VHT_RATE_1SS_MCS8,
777 RTL_RC_VHT_RATE_1SS_MCS9,
778 RTL_RC_VHT_RATE_2SS_MCS7,
779 RTL_RC_VHT_RATE_2SS_MCS8,
780 RTL_RC_VHT_RATE_2SS_MCS9,
781
782 /*keep it last */
783 RTL_VAR_MAP_MAX,
784 };
785
786 /*Firmware PS mode for control LPS.*/
787 enum _fw_ps_mode {
788 FW_PS_ACTIVE_MODE = 0,
789 FW_PS_MIN_MODE = 1,
790 FW_PS_MAX_MODE = 2,
791 FW_PS_DTIM_MODE = 3,
792 FW_PS_VOIP_MODE = 4,
793 FW_PS_UAPSD_WMM_MODE = 5,
794 FW_PS_UAPSD_MODE = 6,
795 FW_PS_IBSS_MODE = 7,
796 FW_PS_WWLAN_MODE = 8,
797 FW_PS_PM_RADIO_OFF = 9,
798 FW_PS_PM_CARD_DISABLE = 10,
799 };
800
801 enum rt_psmode {
802 EACTIVE, /*Active/Continuous access. */
803 EMAXPS, /*Max power save mode. */
804 EFASTPS, /*Fast power save mode. */
805 EAUTOPS, /*Auto power save mode. */
806 };
807
808 /*LED related.*/
809 enum led_ctl_mode {
810 LED_CTL_POWER_ON = 1,
811 LED_CTL_LINK = 2,
812 LED_CTL_NO_LINK = 3,
813 LED_CTL_TX = 4,
814 LED_CTL_RX = 5,
815 LED_CTL_SITE_SURVEY = 6,
816 LED_CTL_POWER_OFF = 7,
817 LED_CTL_START_TO_LINK = 8,
818 LED_CTL_START_WPS = 9,
819 LED_CTL_STOP_WPS = 10,
820 };
821
822 enum rtl_led_pin {
823 LED_PIN_GPIO0,
824 LED_PIN_LED0,
825 LED_PIN_LED1,
826 LED_PIN_LED2
827 };
828
829 /*QoS related.*/
830 /*acm implementation method.*/
831 enum acm_method {
832 EACMWAY0_SWANDHW = 0,
833 EACMWAY1_HW = 1,
834 EACMWAY2_SW = 2,
835 };
836
837 enum macphy_mode {
838 SINGLEMAC_SINGLEPHY = 0,
839 DUALMAC_DUALPHY,
840 DUALMAC_SINGLEPHY,
841 };
842
843 enum band_type {
844 BAND_ON_2_4G = 0,
845 BAND_ON_5G,
846 BAND_ON_BOTH,
847 BANDMAX
848 };
849
850 /* aci/aifsn Field.
851 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
852 */
853 union aci_aifsn {
854 u8 char_data;
855
856 struct {
857 u8 aifsn:4;
858 u8 acm:1;
859 u8 aci:2;
860 u8 reserved:1;
861 } f; /* Field */
862 };
863
864 /*mlme related.*/
865 enum wireless_mode {
866 WIRELESS_MODE_UNKNOWN = 0x00,
867 WIRELESS_MODE_A = 0x01,
868 WIRELESS_MODE_B = 0x02,
869 WIRELESS_MODE_G = 0x04,
870 WIRELESS_MODE_AUTO = 0x08,
871 WIRELESS_MODE_N_24G = 0x10,
872 WIRELESS_MODE_N_5G = 0x20,
873 WIRELESS_MODE_AC_5G = 0x40,
874 WIRELESS_MODE_AC_24G = 0x80,
875 WIRELESS_MODE_AC_ONLY = 0x100,
876 WIRELESS_MODE_MAX = 0x800
877 };
878
879 #define IS_WIRELESS_MODE_A(wirelessmode) \
880 (wirelessmode == WIRELESS_MODE_A)
881 #define IS_WIRELESS_MODE_B(wirelessmode) \
882 (wirelessmode == WIRELESS_MODE_B)
883 #define IS_WIRELESS_MODE_G(wirelessmode) \
884 (wirelessmode == WIRELESS_MODE_G)
885 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
886 (wirelessmode == WIRELESS_MODE_N_24G)
887 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
888 (wirelessmode == WIRELESS_MODE_N_5G)
889
890 enum ratr_table_mode {
891 RATR_INX_WIRELESS_NGB = 0,
892 RATR_INX_WIRELESS_NG = 1,
893 RATR_INX_WIRELESS_NB = 2,
894 RATR_INX_WIRELESS_N = 3,
895 RATR_INX_WIRELESS_GB = 4,
896 RATR_INX_WIRELESS_G = 5,
897 RATR_INX_WIRELESS_B = 6,
898 RATR_INX_WIRELESS_MC = 7,
899 RATR_INX_WIRELESS_A = 8,
900 RATR_INX_WIRELESS_AC_5N = 8,
901 RATR_INX_WIRELESS_AC_24N = 9,
902 };
903
904 enum ratr_table_mode_new {
905 RATEID_IDX_BGN_40M_2SS = 0,
906 RATEID_IDX_BGN_40M_1SS = 1,
907 RATEID_IDX_BGN_20M_2SS_BN = 2,
908 RATEID_IDX_BGN_20M_1SS_BN = 3,
909 RATEID_IDX_GN_N2SS = 4,
910 RATEID_IDX_GN_N1SS = 5,
911 RATEID_IDX_BG = 6,
912 RATEID_IDX_G = 7,
913 RATEID_IDX_B = 8,
914 RATEID_IDX_VHT_2SS = 9,
915 RATEID_IDX_VHT_1SS = 10,
916 RATEID_IDX_MIX1 = 11,
917 RATEID_IDX_MIX2 = 12,
918 RATEID_IDX_VHT_3SS = 13,
919 RATEID_IDX_BGN_3SS = 14,
920 };
921
922 enum rtl_link_state {
923 MAC80211_NOLINK = 0,
924 MAC80211_LINKING = 1,
925 MAC80211_LINKED = 2,
926 MAC80211_LINKED_SCANNING = 3,
927 };
928
929 enum act_category {
930 ACT_CAT_QOS = 1,
931 ACT_CAT_DLS = 2,
932 ACT_CAT_BA = 3,
933 ACT_CAT_HT = 7,
934 ACT_CAT_WMM = 17,
935 };
936
937 enum ba_action {
938 ACT_ADDBAREQ = 0,
939 ACT_ADDBARSP = 1,
940 ACT_DELBA = 2,
941 };
942
943 enum rt_polarity_ctl {
944 RT_POLARITY_LOW_ACT = 0,
945 RT_POLARITY_HIGH_ACT = 1,
946 };
947
948 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
949 enum fw_wow_reason_v2 {
950 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
951 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
952 FW_WOW_V2_DISASSOC_EVENT = 0x04,
953 FW_WOW_V2_DEAUTH_EVENT = 0x08,
954 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
955 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
956 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
957 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
958 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
959 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
960 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
961 FW_WOW_V2_REASON_MAX = 0xff,
962 };
963
964 enum wolpattern_type {
965 UNICAST_PATTERN = 0,
966 MULTICAST_PATTERN = 1,
967 BROADCAST_PATTERN = 2,
968 DONT_CARE_DA = 3,
969 UNKNOWN_TYPE = 4,
970 };
971
972 enum package_type {
973 PACKAGE_DEFAULT,
974 PACKAGE_QFN68,
975 PACKAGE_TFBGA90,
976 PACKAGE_TFBGA80,
977 PACKAGE_TFBGA79
978 };
979
980 enum rtl_spec_ver {
981 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
982 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
983 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */
984 };
985
986 enum dm_info_query {
987 DM_INFO_FA_OFDM,
988 DM_INFO_FA_CCK,
989 DM_INFO_FA_TOTAL,
990 DM_INFO_CCA_OFDM,
991 DM_INFO_CCA_CCK,
992 DM_INFO_CCA_ALL,
993 DM_INFO_CRC32_OK_VHT,
994 DM_INFO_CRC32_OK_HT,
995 DM_INFO_CRC32_OK_LEGACY,
996 DM_INFO_CRC32_OK_CCK,
997 DM_INFO_CRC32_ERROR_VHT,
998 DM_INFO_CRC32_ERROR_HT,
999 DM_INFO_CRC32_ERROR_LEGACY,
1000 DM_INFO_CRC32_ERROR_CCK,
1001 DM_INFO_EDCCA_FLAG,
1002 DM_INFO_OFDM_ENABLE,
1003 DM_INFO_CCK_ENABLE,
1004 DM_INFO_CRC32_OK_HT_AGG,
1005 DM_INFO_CRC32_ERROR_HT_AGG,
1006 DM_INFO_DBG_PORT_0,
1007 DM_INFO_CURR_IGI,
1008 DM_INFO_RSSI_MIN,
1009 DM_INFO_RSSI_MAX,
1010 DM_INFO_CLM_RATIO,
1011 DM_INFO_NHM_RATIO,
1012 DM_INFO_IQK_ALL,
1013 DM_INFO_IQK_OK,
1014 DM_INFO_IQK_NG,
1015 DM_INFO_SIZE,
1016 };
1017
1018 enum rx_packet_type {
1019 NORMAL_RX,
1020 TX_REPORT1,
1021 TX_REPORT2,
1022 HIS_REPORT,
1023 C2H_PACKET,
1024 };
1025
1026 struct rtlwifi_tx_info {
1027 int sn;
1028 unsigned long send_time;
1029 };
1030
rtl_tx_skb_cb_info(struct sk_buff * skb)1031 static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb)
1032 {
1033 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1034
1035 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) >
1036 sizeof(info->status.status_driver_data));
1037
1038 return (struct rtlwifi_tx_info *)(info->status.status_driver_data);
1039 }
1040
1041 struct octet_string {
1042 u8 *octet;
1043 u16 length;
1044 };
1045
1046 struct rtl_hdr_3addr {
1047 __le16 frame_ctl;
1048 __le16 duration_id;
1049 u8 addr1[ETH_ALEN];
1050 u8 addr2[ETH_ALEN];
1051 u8 addr3[ETH_ALEN];
1052 __le16 seq_ctl;
1053 u8 payload[];
1054 } __packed;
1055
1056 struct rtl_info_element {
1057 u8 id;
1058 u8 len;
1059 u8 data[];
1060 } __packed;
1061
1062 struct rtl_probe_rsp {
1063 struct rtl_hdr_3addr header;
1064 u32 time_stamp[2];
1065 __le16 beacon_interval;
1066 __le16 capability;
1067 /*SSID, supported rates, FH params, DS params,
1068 * CF params, IBSS params, TIM (if beacon), RSN
1069 */
1070 struct rtl_info_element info_element[];
1071 } __packed;
1072
1073 struct rtl_led_ctl {
1074 bool led_opendrain;
1075 enum rtl_led_pin sw_led0;
1076 enum rtl_led_pin sw_led1;
1077 };
1078
1079 struct rtl_qos_parameters {
1080 __le16 cw_min;
1081 __le16 cw_max;
1082 u8 aifs;
1083 u8 flag;
1084 __le16 tx_op;
1085 } __packed;
1086
1087 struct rt_smooth_data {
1088 u32 elements[100]; /*array to store values */
1089 u32 index; /*index to current array to store */
1090 u32 total_num; /*num of valid elements */
1091 u32 total_val; /*sum of valid elements */
1092 };
1093
1094 struct false_alarm_statistics {
1095 u32 cnt_parity_fail;
1096 u32 cnt_rate_illegal;
1097 u32 cnt_crc8_fail;
1098 u32 cnt_mcs_fail;
1099 u32 cnt_fast_fsync_fail;
1100 u32 cnt_sb_search_fail;
1101 u32 cnt_ofdm_fail;
1102 u32 cnt_cck_fail;
1103 u32 cnt_all;
1104 u32 cnt_ofdm_cca;
1105 u32 cnt_cck_cca;
1106 u32 cnt_cca_all;
1107 u32 cnt_bw_usc;
1108 u32 cnt_bw_lsc;
1109 };
1110
1111 struct init_gain {
1112 u8 xaagccore1;
1113 u8 xbagccore1;
1114 u8 xcagccore1;
1115 u8 xdagccore1;
1116 u8 cca;
1117
1118 };
1119
1120 struct wireless_stats {
1121 u64 txbytesunicast;
1122 u64 txbytesmulticast;
1123 u64 txbytesbroadcast;
1124 u64 rxbytesunicast;
1125
1126 u64 txbytesunicast_inperiod;
1127 u64 rxbytesunicast_inperiod;
1128 u32 txbytesunicast_inperiod_tp;
1129 u32 rxbytesunicast_inperiod_tp;
1130 u64 txbytesunicast_last;
1131 u64 rxbytesunicast_last;
1132
1133 long rx_snr_db[4];
1134 /*Correct smoothed ss in Dbm, only used
1135 * in driver to report real power now.
1136 */
1137 long recv_signal_power;
1138 long signal_quality;
1139 long last_sigstrength_inpercent;
1140
1141 u32 rssi_calculate_cnt;
1142 u32 pwdb_all_cnt;
1143
1144 /* Transformed, in dbm. Beautified signal
1145 * strength for UI, not correct.
1146 */
1147 long signal_strength;
1148
1149 u8 rx_rssi_percentage[4];
1150 u8 rx_evm_dbm[4];
1151 u8 rx_evm_percentage[2];
1152
1153 u16 rx_cfo_short[4];
1154 u16 rx_cfo_tail[4];
1155
1156 struct rt_smooth_data ui_rssi;
1157 struct rt_smooth_data ui_link_quality;
1158 };
1159
1160 struct rate_adaptive {
1161 u8 rate_adaptive_disabled;
1162 u8 ratr_state;
1163 u16 reserve;
1164
1165 u32 high_rssi_thresh_for_ra;
1166 u32 high2low_rssi_thresh_for_ra;
1167 u8 low2high_rssi_thresh_for_ra40m;
1168 u32 low_rssi_thresh_for_ra40m;
1169 u8 low2high_rssi_thresh_for_ra20m;
1170 u32 low_rssi_thresh_for_ra20m;
1171 u32 upper_rssi_threshold_ratr;
1172 u32 middleupper_rssi_threshold_ratr;
1173 u32 middle_rssi_threshold_ratr;
1174 u32 middlelow_rssi_threshold_ratr;
1175 u32 low_rssi_threshold_ratr;
1176 u32 ultralow_rssi_threshold_ratr;
1177 u32 low_rssi_threshold_ratr_40m;
1178 u32 low_rssi_threshold_ratr_20m;
1179 u8 ping_rssi_enable;
1180 u32 ping_rssi_ratr;
1181 u32 ping_rssi_thresh_for_ra;
1182 u32 last_ratr;
1183 u8 pre_ratr_state;
1184 u8 ldpc_thres;
1185 bool use_ldpc;
1186 bool lower_rts_rate;
1187 bool is_special_data;
1188 };
1189
1190 struct regd_pair_mapping {
1191 u16 reg_dmnenum;
1192 u16 reg_5ghz_ctl;
1193 u16 reg_2ghz_ctl;
1194 };
1195
1196 struct dynamic_primary_cca {
1197 u8 pricca_flag;
1198 u8 intf_flag;
1199 u8 intf_type;
1200 u8 dup_rts_flag;
1201 u8 monitor_flag;
1202 u8 ch_offset;
1203 u8 mf_state;
1204 };
1205
1206 struct rtl_regulatory {
1207 s8 alpha2[2];
1208 u16 country_code;
1209 u16 max_power_level;
1210 u32 tp_scale;
1211 u16 current_rd;
1212 u16 current_rd_ext;
1213 int16_t power_limit;
1214 struct regd_pair_mapping *regpair;
1215 };
1216
1217 struct rtl_rfkill {
1218 bool rfkill_state; /*0 is off, 1 is on */
1219 };
1220
1221 /*for P2P PS**/
1222 #define P2P_MAX_NOA_NUM 2
1223
1224 enum p2p_role {
1225 P2P_ROLE_DISABLE = 0,
1226 P2P_ROLE_DEVICE = 1,
1227 P2P_ROLE_CLIENT = 2,
1228 P2P_ROLE_GO = 3
1229 };
1230
1231 enum p2p_ps_state {
1232 P2P_PS_DISABLE = 0,
1233 P2P_PS_ENABLE = 1,
1234 P2P_PS_SCAN = 2,
1235 P2P_PS_SCAN_DONE = 3,
1236 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1237 };
1238
1239 enum p2p_ps_mode {
1240 P2P_PS_NONE = 0,
1241 P2P_PS_CTWINDOW = 1,
1242 P2P_PS_NOA = 2,
1243 P2P_PS_MIX = 3, /* CTWindow and NoA */
1244 };
1245
1246 struct rtl_p2p_ps_info {
1247 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1248 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1249 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1250 /* Client traffic window. A period of time in TU after TBTT. */
1251 u8 ctwindow;
1252 u8 opp_ps; /* opportunistic power save. */
1253 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1254 /* Count for owner, Type of client. */
1255 u8 noa_count_type[P2P_MAX_NOA_NUM];
1256 /* Max duration for owner, preferred or min acceptable duration
1257 * for client.
1258 */
1259 u32 noa_duration[P2P_MAX_NOA_NUM];
1260 /* Length of interval for owner, preferred or max acceptable intervali
1261 * of client.
1262 */
1263 u32 noa_interval[P2P_MAX_NOA_NUM];
1264 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1265 u32 noa_start_time[P2P_MAX_NOA_NUM];
1266 };
1267
1268 struct p2p_ps_offload_t {
1269 u8 offload_en:1;
1270 u8 role:1; /* 1: Owner, 0: Client */
1271 u8 ctwindow_en:1;
1272 u8 noa0_en:1;
1273 u8 noa1_en:1;
1274 u8 allstasleep:1;
1275 u8 discovery:1;
1276 u8 reserved:1;
1277 };
1278
1279 #define IQK_MATRIX_REG_NUM 8
1280 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1281
1282 struct iqk_matrix_regs {
1283 bool iqk_done;
1284 long value[1][IQK_MATRIX_REG_NUM];
1285 };
1286
1287 struct phy_parameters {
1288 u16 length;
1289 u32 *pdata;
1290 };
1291
1292 enum hw_param_tab_index {
1293 PHY_REG_2T,
1294 PHY_REG_1T,
1295 PHY_REG_PG,
1296 RADIOA_2T,
1297 RADIOB_2T,
1298 RADIOA_1T,
1299 RADIOB_1T,
1300 MAC_REG,
1301 AGCTAB_2T,
1302 AGCTAB_1T,
1303 MAX_TAB
1304 };
1305
1306 struct rtl_phy {
1307 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1308 struct init_gain initgain_backup;
1309 enum io_type current_io_type;
1310
1311 u8 rf_mode;
1312 u8 rf_type;
1313 u8 current_chan_bw;
1314 u8 set_bwmode_inprogress;
1315 u8 sw_chnl_inprogress;
1316 u8 sw_chnl_stage;
1317 u8 sw_chnl_step;
1318 u8 current_channel;
1319 u8 h2c_box_num;
1320 u8 set_io_inprogress;
1321 u8 lck_inprogress;
1322
1323 /* record for power tracking */
1324 s32 reg_e94;
1325 s32 reg_e9c;
1326 s32 reg_ea4;
1327 s32 reg_eac;
1328 s32 reg_eb4;
1329 s32 reg_ebc;
1330 s32 reg_ec4;
1331 s32 reg_ecc;
1332 u8 rfpienable;
1333 u8 reserve_0;
1334 u16 reserve_1;
1335 u32 reg_c04, reg_c08, reg_874;
1336 u32 adda_backup[16];
1337 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1338 u32 iqk_bb_backup[10];
1339 bool iqk_initialized;
1340
1341 bool rfpath_rx_enable[MAX_RF_PATH];
1342 u8 reg_837;
1343 /* Dual mac */
1344 bool need_iqk;
1345 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1346
1347 bool rfpi_enable;
1348 bool iqk_in_progress;
1349
1350 u8 pwrgroup_cnt;
1351 u8 cck_high_power;
1352 /* this is for 88E & 8723A */
1353 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1354 /* MAX_PG_GROUP groups of pwr diff by rates */
1355 u32 mcs_offset[MAX_PG_GROUP][16];
1356 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1357 [TX_PWR_BY_RATE_NUM_RF]
1358 [TX_PWR_BY_RATE_NUM_RF]
1359 [TX_PWR_BY_RATE_NUM_RATE];
1360 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1361 [TX_PWR_BY_RATE_NUM_RF]
1362 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1363 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1364 [TX_PWR_BY_RATE_NUM_RF]
1365 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1366 u8 default_initialgain[4];
1367
1368 /* the current Tx power level */
1369 u8 cur_cck_txpwridx;
1370 u8 cur_ofdm24g_txpwridx;
1371 u8 cur_bw20_txpwridx;
1372 u8 cur_bw40_txpwridx;
1373
1374 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1375 [MAX_2_4G_BANDWIDTH_NUM]
1376 [MAX_RATE_SECTION_NUM]
1377 [CHANNEL_MAX_NUMBER_2G]
1378 [MAX_RF_PATH_NUM];
1379 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1380 [MAX_5G_BANDWIDTH_NUM]
1381 [MAX_RATE_SECTION_NUM]
1382 [CHANNEL_MAX_NUMBER_5G]
1383 [MAX_RF_PATH_NUM];
1384
1385 u32 rfreg_chnlval[2];
1386 bool apk_done;
1387 u32 reg_rf3c[2]; /* pathA / pathB */
1388
1389 u32 backup_rf_0x1a;/*92ee*/
1390 /* bfsync */
1391 u8 framesync;
1392 u32 framesync_c34;
1393
1394 u8 num_total_rfpath;
1395 struct phy_parameters hwparam_tables[MAX_TAB];
1396 u16 rf_pathmap;
1397
1398 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1399 enum rt_polarity_ctl polarity_ctl;
1400 };
1401
1402 #define MAX_TID_COUNT 9
1403 #define RTL_AGG_STOP 0
1404 #define RTL_AGG_PROGRESS 1
1405 #define RTL_AGG_START 2
1406 #define RTL_AGG_OPERATIONAL 3
1407 #define RTL_AGG_OFF 0
1408 #define RTL_AGG_ON 1
1409 #define RTL_RX_AGG_START 1
1410 #define RTL_RX_AGG_STOP 0
1411 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1412 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1413
1414 struct rtl_ht_agg {
1415 u16 txq_id;
1416 u16 wait_for_ba;
1417 u16 start_idx;
1418 u64 bitmap;
1419 u32 rate_n_flags;
1420 u8 agg_state;
1421 u8 rx_agg_state;
1422 };
1423
1424 struct rssi_sta {
1425 long undec_sm_pwdb;
1426 long undec_sm_cck;
1427 };
1428
1429 struct rtl_tid_data {
1430 struct rtl_ht_agg agg;
1431 };
1432
1433 struct rtl_sta_info {
1434 struct list_head list;
1435 struct rtl_tid_data tids[MAX_TID_COUNT];
1436 /* just used for ap adhoc or mesh*/
1437 struct rssi_sta rssi_stat;
1438 u8 rssi_level;
1439 u16 wireless_mode;
1440 u8 ratr_index;
1441 u8 mimo_ps;
1442 u8 mac_addr[ETH_ALEN];
1443 } __packed;
1444
1445 struct rtl_priv;
1446 struct rtl_io {
1447 struct device *dev;
1448 struct mutex bb_mutex;
1449
1450 /*PCI MEM map */
1451 unsigned long pci_mem_end; /*shared mem end */
1452 unsigned long pci_mem_start; /*shared mem start */
1453
1454 /*PCI IO map */
1455 unsigned long pci_base_addr; /*device I/O address */
1456
1457 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1458 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1459 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1460
1461 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1462 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1463 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1464
1465 };
1466
1467 struct rtl_mac {
1468 u8 mac_addr[ETH_ALEN];
1469 u8 mac80211_registered;
1470 u8 beacon_enabled;
1471
1472 u32 tx_ss_num;
1473 u32 rx_ss_num;
1474
1475 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1476 struct ieee80211_hw *hw;
1477 struct ieee80211_vif *vif;
1478 enum nl80211_iftype opmode;
1479
1480 /*Probe Beacon management */
1481 struct rtl_tid_data tids[MAX_TID_COUNT];
1482 enum rtl_link_state link_state;
1483
1484 int n_channels;
1485 int n_bitrates;
1486
1487 bool offchan_delay;
1488 u8 p2p; /*using p2p role*/
1489 bool p2p_in_use;
1490
1491 /*filters */
1492 u32 rx_conf;
1493 u16 rx_mgt_filter;
1494 u16 rx_ctrl_filter;
1495 u16 rx_data_filter;
1496
1497 bool act_scanning;
1498 u8 cnt_after_linked;
1499 bool skip_scan;
1500
1501 /* early mode */
1502 /* skb wait queue */
1503 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1504
1505 u8 ht_stbc_cap;
1506 u8 ht_cur_stbc;
1507
1508 /*vht support*/
1509 u8 vht_enable;
1510 u8 bw_80;
1511 u8 vht_cur_ldpc;
1512 u8 vht_cur_stbc;
1513 u8 vht_stbc_cap;
1514 u8 vht_ldpc_cap;
1515
1516 /*RDG*/
1517 bool rdg_en;
1518
1519 /*AP*/
1520 u8 bssid[ETH_ALEN] __aligned(2);
1521 u32 vendor;
1522 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1523 u32 basic_rates; /* b/g rates */
1524 u8 ht_enable;
1525 u8 sgi_40;
1526 u8 sgi_20;
1527 u8 bw_40;
1528 u16 mode; /* wireless mode */
1529 u8 slot_time;
1530 u8 short_preamble;
1531 u8 use_cts_protect;
1532 u8 cur_40_prime_sc;
1533 u8 cur_40_prime_sc_bk;
1534 u8 cur_80_prime_sc;
1535 u64 tsf;
1536 u8 retry_short;
1537 u8 retry_long;
1538 u16 assoc_id;
1539 bool hiddenssid;
1540
1541 /*IBSS*/
1542 int beacon_interval;
1543
1544 /*AMPDU*/
1545 u8 min_space_cfg; /*For Min spacing configurations */
1546 u8 max_mss_density;
1547 u8 current_ampdu_factor;
1548 u8 current_ampdu_density;
1549
1550 /*QOS & EDCA */
1551 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1552 struct rtl_qos_parameters ac[AC_MAX];
1553
1554 /* counters */
1555 u64 last_txok_cnt;
1556 u64 last_rxok_cnt;
1557 u32 last_bt_edca_ul;
1558 u32 last_bt_edca_dl;
1559 };
1560
1561 struct btdm_8723 {
1562 bool all_off;
1563 bool agc_table_en;
1564 bool adc_back_off_on;
1565 bool b2_ant_hid_en;
1566 bool low_penalty_rate_adaptive;
1567 bool rf_rx_lpf_shrink;
1568 bool reject_aggre_pkt;
1569 bool tra_tdma_on;
1570 u8 tra_tdma_nav;
1571 u8 tra_tdma_ant;
1572 bool tdma_on;
1573 u8 tdma_ant;
1574 u8 tdma_nav;
1575 u8 tdma_dac_swing;
1576 u8 fw_dac_swing_lvl;
1577 bool ps_tdma_on;
1578 u8 ps_tdma_byte[5];
1579 bool pta_on;
1580 u32 val_0x6c0;
1581 u32 val_0x6c8;
1582 u32 val_0x6cc;
1583 bool sw_dac_swing_on;
1584 u32 sw_dac_swing_lvl;
1585 u32 wlan_act_hi;
1586 u32 wlan_act_lo;
1587 u32 bt_retry_index;
1588 bool dec_bt_pwr;
1589 bool ignore_wlan_act;
1590 };
1591
1592 struct bt_coexist_8723 {
1593 u32 high_priority_tx;
1594 u32 high_priority_rx;
1595 u32 low_priority_tx;
1596 u32 low_priority_rx;
1597 u8 c2h_bt_info;
1598 bool c2h_bt_info_req_sent;
1599 bool c2h_bt_inquiry_page;
1600 u32 bt_inq_page_start_time;
1601 u8 bt_retry_cnt;
1602 u8 c2h_bt_info_original;
1603 u8 bt_inquiry_page_cnt;
1604 struct btdm_8723 btdm;
1605 };
1606
1607 struct rtl_hal {
1608 struct ieee80211_hw *hw;
1609 bool driver_is_goingto_unload;
1610 bool up_first_time;
1611 bool first_init;
1612 bool being_init_adapter;
1613 bool bbrf_ready;
1614 bool mac_func_enable;
1615 bool pre_edcca_enable;
1616 struct bt_coexist_8723 hal_coex_8723;
1617
1618 enum intf_type interface;
1619 u16 hw_type; /*92c or 92d or 92s and so on */
1620 u8 ic_class;
1621 u8 oem_id;
1622 u32 version; /*version of chip */
1623 u8 state; /*stop 0, start 1 */
1624 u8 board_type;
1625 u8 package_type;
1626 u8 external_pa;
1627
1628 u8 pa_mode;
1629 u8 pa_type_2g;
1630 u8 pa_type_5g;
1631 u8 lna_type_2g;
1632 u8 lna_type_5g;
1633 u8 external_pa_2g;
1634 u8 external_lna_2g;
1635 u8 external_pa_5g;
1636 u8 external_lna_5g;
1637 u8 type_glna;
1638 u8 type_gpa;
1639 u8 type_alna;
1640 u8 type_apa;
1641 u8 rfe_type;
1642
1643 /*firmware */
1644 u32 fwsize;
1645 u8 *pfirmware;
1646 u16 fw_version;
1647 u16 fw_subversion;
1648 bool h2c_setinprogress;
1649 u8 last_hmeboxnum;
1650 bool fw_ready;
1651 /*Reserve page start offset except beacon in TxQ. */
1652 u8 fw_rsvdpage_startoffset;
1653 u8 h2c_txcmd_seq;
1654 u8 current_ra_rate;
1655
1656 /* FW Cmd IO related */
1657 u16 fwcmd_iomap;
1658 u32 fwcmd_ioparam;
1659 bool set_fwcmd_inprogress;
1660 u8 current_fwcmd_io;
1661
1662 struct p2p_ps_offload_t p2p_ps_offload;
1663 bool fw_clk_change_in_progress;
1664 bool allow_sw_to_change_hwclc;
1665 u8 fw_ps_state;
1666
1667 /*AMPDU init min space*/
1668 u8 minspace_cfg; /*For Min spacing configurations */
1669
1670 /* Dual mac */
1671 enum macphy_mode macphymode;
1672 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1673 enum band_type current_bandtypebackup;
1674 enum band_type bandset;
1675 /* dual MAC 0--Mac0 1--Mac1 */
1676 u32 interfaceindex;
1677 /* just for DualMac S3S4 */
1678 u8 macphyctl_reg;
1679 bool earlymode_enable;
1680 u8 max_earlymode_num;
1681 /* Dual mac*/
1682 bool during_mac0init_radiob;
1683 bool during_mac1init_radioa;
1684 bool reloadtxpowerindex;
1685 /* True if IMR or IQK have done
1686 * for 2.4G in scan progress
1687 */
1688 bool load_imrandiqk_setting_for2g;
1689
1690 bool disable_amsdu_8k;
1691 bool master_of_dmsp;
1692 bool slave_of_dmsp;
1693
1694 u16 rx_tag;/*for 92ee*/
1695 u8 rts_en;
1696
1697 /*for wowlan*/
1698 bool wow_enable;
1699 bool enter_pnp_sleep;
1700 bool wake_from_pnp_sleep;
1701 bool wow_enabled;
1702 time64_t last_suspend_sec;
1703 u32 wowlan_fwsize;
1704 u8 *wowlan_firmware;
1705
1706 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1707
1708 bool real_wow_v2_enable;
1709 bool re_init_llt_table;
1710 };
1711
1712 struct rtl_security {
1713 /*default 0 */
1714 bool use_sw_sec;
1715
1716 bool being_setkey;
1717 bool use_defaultkey;
1718 /*Encryption Algorithm for Unicast Packet */
1719 enum rt_enc_alg pairwise_enc_algorithm;
1720 /*Encryption Algorithm for Brocast/Multicast */
1721 enum rt_enc_alg group_enc_algorithm;
1722 /*Cam Entry Bitmap */
1723 u32 hwsec_cam_bitmap;
1724 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1725 /*local Key buffer, indx 0 is for
1726 * pairwise key 1-4 is for agoup key.
1727 */
1728 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1729 u8 key_len[KEY_BUF_SIZE];
1730
1731 /*The pointer of Pairwise Key,
1732 * it always points to KeyBuf[4]
1733 */
1734 u8 *pairwise_key;
1735 };
1736
1737 #define ASSOCIATE_ENTRY_NUM 33
1738
1739 struct fast_ant_training {
1740 u8 bssid[6];
1741 u8 antsel_rx_keep_0;
1742 u8 antsel_rx_keep_1;
1743 u8 antsel_rx_keep_2;
1744 u32 ant_sum[7];
1745 u32 ant_cnt[7];
1746 u32 ant_ave[7];
1747 u8 fat_state;
1748 u32 train_idx;
1749 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1750 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1751 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1752 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1753 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1754 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1755 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1756 u8 rx_idle_ant;
1757 bool becomelinked;
1758 };
1759
1760 struct dm_phy_dbg_info {
1761 s8 rx_snrdb[4];
1762 u64 num_qry_phy_status;
1763 u64 num_qry_phy_status_cck;
1764 u64 num_qry_phy_status_ofdm;
1765 u16 num_qry_beacon_pkt;
1766 u16 num_non_be_pkt;
1767 s32 rx_evm[4];
1768 };
1769
1770 struct rtl_dm {
1771 /*PHY status for Dynamic Management */
1772 long entry_min_undec_sm_pwdb;
1773 long undec_sm_cck;
1774 long undec_sm_pwdb; /*out dm */
1775 long entry_max_undec_sm_pwdb;
1776 s32 ofdm_pkt_cnt;
1777 bool dm_initialgain_enable;
1778 bool dynamic_txpower_enable;
1779 bool current_turbo_edca;
1780 bool is_any_nonbepkts; /*out dm */
1781 bool is_cur_rdlstate;
1782 bool txpower_trackinginit;
1783 bool disable_framebursting;
1784 bool cck_inch14;
1785 bool txpower_tracking;
1786 bool useramask;
1787 bool rfpath_rxenable[4];
1788 bool inform_fw_driverctrldm;
1789 bool current_mrc_switch;
1790 u8 txpowercount;
1791 u8 powerindex_backup[6];
1792
1793 u8 thermalvalue_rxgain;
1794 u8 thermalvalue_iqk;
1795 u8 thermalvalue_lck;
1796 u8 thermalvalue;
1797 u8 last_dtp_lvl;
1798 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1799 u8 thermalvalue_avg_index;
1800 u8 tm_trigger;
1801 bool done_txpower;
1802 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1803 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1804 u8 dm_flag_tmp;
1805 u8 dm_type;
1806 u8 dm_rssi_sel;
1807 u8 txpower_track_control;
1808 bool interrupt_migration;
1809 bool disable_tx_int;
1810 s8 ofdm_index[MAX_RF_PATH];
1811 u8 default_ofdm_index;
1812 u8 default_cck_index;
1813 s8 cck_index;
1814 s8 delta_power_index[MAX_RF_PATH];
1815 s8 delta_power_index_last[MAX_RF_PATH];
1816 s8 power_index_offset[MAX_RF_PATH];
1817 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1818 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1819 s8 remnant_cck_idx;
1820 bool modify_txagc_flag_path_a;
1821 bool modify_txagc_flag_path_b;
1822
1823 bool one_entry_only;
1824 struct dm_phy_dbg_info dbginfo;
1825
1826 /* Dynamic ATC switch */
1827 bool atc_status;
1828 bool large_cfo_hit;
1829 bool is_freeze;
1830 int cfo_tail[2];
1831 int cfo_ave_pre;
1832 int crystal_cap;
1833 u8 cfo_threshold;
1834 u32 packet_count;
1835 u32 packet_count_pre;
1836 u8 tx_rate;
1837
1838 /*88e tx power tracking*/
1839 u8 swing_idx_ofdm[MAX_RF_PATH];
1840 u8 swing_idx_ofdm_cur;
1841 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1842 bool swing_flag_ofdm;
1843 u8 swing_idx_cck;
1844 u8 swing_idx_cck_cur;
1845 u8 swing_idx_cck_base;
1846 bool swing_flag_cck;
1847
1848 s8 swing_diff_2g;
1849 s8 swing_diff_5g;
1850
1851 /* DMSP */
1852 bool supp_phymode_switch;
1853
1854 /* DulMac */
1855 struct fast_ant_training fat_table;
1856
1857 u8 resp_tx_path;
1858 u8 path_sel;
1859 u32 patha_sum;
1860 u32 pathb_sum;
1861 u32 patha_cnt;
1862 u32 pathb_cnt;
1863
1864 u8 pre_channel;
1865 u8 *p_channel;
1866 u8 linked_interval;
1867
1868 u64 last_tx_ok_cnt;
1869 u64 last_rx_ok_cnt;
1870 };
1871
1872 #define EFUSE_MAX_LOGICAL_SIZE 512
1873
1874 struct rtl_efuse {
1875 const struct rtl_efuse_ops *efuse_ops;
1876 bool autoload_ok;
1877 bool bootfromefuse;
1878 u16 max_physical_size;
1879
1880 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1881 u16 efuse_usedbytes;
1882 u8 efuse_usedpercentage;
1883
1884 u8 autoload_failflag;
1885 u8 autoload_status;
1886
1887 short epromtype;
1888 u16 eeprom_vid;
1889 u16 eeprom_did;
1890 u16 eeprom_svid;
1891 u16 eeprom_smid;
1892 u8 eeprom_oemid;
1893 u16 eeprom_channelplan;
1894 u8 eeprom_version;
1895 u8 board_type;
1896 u8 external_pa;
1897
1898 u8 dev_addr[6];
1899 u8 wowlan_enable;
1900 u8 antenna_div_cfg;
1901 u8 antenna_div_type;
1902
1903 bool txpwr_fromeprom;
1904 u8 eeprom_crystalcap;
1905 u8 eeprom_tssi[2];
1906 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1907 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1908 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1909 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1910 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1911 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1912
1913 u8 internal_pa_5g[2]; /* pathA / pathB */
1914 u8 eeprom_c9;
1915 u8 eeprom_cc;
1916
1917 /*For power group */
1918 u8 eeprom_pwrgroup[2][3];
1919 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1920 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1921
1922 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1923 /*For HT 40MHZ pwr */
1924 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1925 /*For HT 40MHZ pwr */
1926 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1927
1928 /*--------------------------------------------------------*
1929 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1930 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1931 * define new arrays in Windows code.
1932 * BUT, in linux code, we use the same array for all ICs.
1933 *
1934 * The Correspondance relation between two arrays is:
1935 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1936 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1937 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1938 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1939 *
1940 * Sizes of these arrays are decided by the larger ones.
1941 */
1942 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1943 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1944 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1945 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1946
1947 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1948 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1949 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1950 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1951 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1952 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1953
1954 u8 txpwr_safetyflag; /* Band edge enable flag */
1955 u16 eeprom_txpowerdiff;
1956 u8 antenna_txpwdiff[3];
1957
1958 u8 eeprom_regulatory;
1959 u8 eeprom_thermalmeter;
1960 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1961 u16 tssi_13dbm;
1962 u8 crystalcap; /* CrystalCap. */
1963 u8 delta_iqk;
1964 u8 delta_lck;
1965
1966 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1967 bool apk_thermalmeterignore;
1968
1969 bool b1x1_recvcombine;
1970 bool b1ss_support;
1971
1972 /*channel plan */
1973 u8 channel_plan;
1974 };
1975
1976 struct rtl_efuse_ops {
1977 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data);
1978 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type,
1979 u16 offset, u32 *value);
1980 };
1981
1982 struct rtl_tx_report {
1983 atomic_t sn;
1984 u16 last_sent_sn;
1985 unsigned long last_sent_time;
1986 u16 last_recv_sn;
1987 struct sk_buff_head queue;
1988 };
1989
1990 struct rtl_ps_ctl {
1991 bool pwrdomain_protect;
1992 bool in_powersavemode;
1993 bool rfchange_inprogress;
1994 bool swrf_processing;
1995 bool hwradiooff;
1996 /* just for PCIE ASPM
1997 * If it supports ASPM, Offset[560h] = 0x40,
1998 * otherwise Offset[560h] = 0x00.
1999 */
2000 bool support_aspm;
2001 bool support_backdoor;
2002
2003 /*for LPS */
2004 enum rt_psmode dot11_psmode; /*Power save mode configured. */
2005 bool swctrl_lps;
2006 bool leisure_ps;
2007 bool fwctrl_lps;
2008 u8 fwctrl_psmode;
2009 /*For Fw control LPS mode */
2010 u8 reg_fwctrl_lps;
2011 /*Record Fw PS mode status. */
2012 bool fw_current_inpsmode;
2013 u8 reg_max_lps_awakeintvl;
2014 bool report_linked;
2015 bool low_power_enable;/*for 32k*/
2016
2017 /*for IPS */
2018 bool inactiveps;
2019
2020 u32 rfoff_reason;
2021
2022 /*RF OFF Level */
2023 u32 cur_ps_level;
2024 u32 reg_rfps_level;
2025
2026 /*just for PCIE ASPM */
2027 u8 const_amdpci_aspm;
2028 bool pwrdown_mode;
2029
2030 enum rf_pwrstate inactive_pwrstate;
2031 enum rf_pwrstate rfpwr_state; /*cur power state */
2032
2033 /* for SW LPS*/
2034 bool sw_ps_enabled;
2035 bool state;
2036 bool state_inap;
2037 bool multi_buffered;
2038 u16 nullfunc_seq;
2039 unsigned int dtim_counter;
2040 unsigned int sleep_ms;
2041 unsigned long last_sleep_jiffies;
2042 unsigned long last_awake_jiffies;
2043 unsigned long last_delaylps_stamp_jiffies;
2044 unsigned long last_dtim;
2045 unsigned long last_beacon;
2046 unsigned long last_action;
2047 unsigned long last_slept;
2048
2049 /*For P2P PS */
2050 struct rtl_p2p_ps_info p2p_ps_info;
2051 u8 pwr_mode;
2052 u8 smart_ps;
2053
2054 /* wake up on line */
2055 u8 wo_wlan_mode;
2056 u8 arp_offload_enable;
2057 u8 gtk_offload_enable;
2058 /* Used for WOL, indicates the reason for waking event.*/
2059 u32 wakeup_reason;
2060 };
2061
2062 struct rtl_stats {
2063 u8 psaddr[ETH_ALEN];
2064 u32 mac_time[2];
2065 s8 rssi;
2066 u8 signal;
2067 u8 noise;
2068 u8 rate; /* hw desc rate */
2069 u8 received_channel;
2070 u8 control;
2071 u8 mask;
2072 u8 freq;
2073 u16 len;
2074 u64 tsf;
2075 u32 beacon_time;
2076 u8 nic_type;
2077 u16 length;
2078 u8 signalquality; /*in 0-100 index. */
2079 /* Real power in dBm for this packet,
2080 * no beautification and aggregation.
2081 */
2082 s32 recvsignalpower;
2083 s8 rxpower; /*in dBm Translate from PWdB */
2084 u8 signalstrength; /*in 0-100 index. */
2085 u16 hwerror:1;
2086 u16 crc:1;
2087 u16 icv:1;
2088 u16 shortpreamble:1;
2089 u16 antenna:1;
2090 u16 decrypted:1;
2091 u16 wakeup:1;
2092 u32 timestamp_low;
2093 u32 timestamp_high;
2094 bool shift;
2095
2096 u8 rx_drvinfo_size;
2097 u8 rx_bufshift;
2098 bool isampdu;
2099 bool isfirst_ampdu;
2100 bool rx_is40mhzpacket;
2101 u8 rx_packet_bw;
2102 u32 rx_pwdb_all;
2103 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2104 s8 rx_mimo_signalquality[4];
2105 u8 rx_mimo_evm_dbm[4];
2106 u16 cfo_short[4]; /* per-path's Cfo_short */
2107 u16 cfo_tail[4];
2108
2109 s8 rx_mimo_sig_qual[4];
2110 u8 rx_pwr[4]; /* per-path's pwdb */
2111 u8 rx_snr[4]; /* per-path's SNR */
2112 u8 bandwidth;
2113 u8 bt_coex_pwr_adjust;
2114 bool packet_matchbssid;
2115 bool is_cck;
2116 bool is_ht;
2117 bool packet_toself;
2118 bool packet_beacon; /*for rssi */
2119 s8 cck_adc_pwdb[4]; /*for rx path selection */
2120
2121 bool is_vht;
2122 bool is_short_gi;
2123 u8 vht_nss;
2124
2125 u8 packet_report_type;
2126
2127 u32 macid;
2128 u32 bt_rx_rssi_percentage;
2129 u32 macid_valid_entry[2];
2130 };
2131
2132 struct rt_link_detect {
2133 /* count for roaming */
2134 u32 bcn_rx_inperiod;
2135 u32 roam_times;
2136
2137 u32 num_tx_in4period[4];
2138 u32 num_rx_in4period[4];
2139
2140 u32 num_tx_inperiod;
2141 u32 num_rx_inperiod;
2142
2143 bool busytraffic;
2144 bool tx_busy_traffic;
2145 bool rx_busy_traffic;
2146 bool higher_busytraffic;
2147 bool higher_busyrxtraffic;
2148
2149 u32 tidtx_in4period[MAX_TID_COUNT][4];
2150 u32 tidtx_inperiod[MAX_TID_COUNT];
2151 bool higher_busytxtraffic[MAX_TID_COUNT];
2152 };
2153
2154 struct rtl_tcb_desc {
2155 u8 packet_bw:2;
2156 u8 multicast:1;
2157 u8 broadcast:1;
2158
2159 u8 rts_stbc:1;
2160 u8 rts_enable:1;
2161 u8 cts_enable:1;
2162 u8 rts_use_shortpreamble:1;
2163 u8 rts_use_shortgi:1;
2164 u8 rts_sc:1;
2165 u8 rts_bw:1;
2166 u8 rts_rate;
2167
2168 u8 use_shortgi:1;
2169 u8 use_shortpreamble:1;
2170 u8 use_driver_rate:1;
2171 u8 disable_ratefallback:1;
2172
2173 u8 use_spe_rpt:1;
2174
2175 u8 ratr_index;
2176 u8 mac_id;
2177 u8 hw_rate;
2178
2179 u8 last_inipkt:1;
2180 u8 cmd_or_init:1;
2181 u8 queue_index;
2182
2183 /* early mode */
2184 u8 empkt_num;
2185 /* The max value by HW */
2186 u32 empkt_len[10];
2187 bool tx_enable_sw_calc_duration;
2188 };
2189
2190 struct rtl_wow_pattern {
2191 u8 type;
2192 u16 crc;
2193 u32 mask[4];
2194 };
2195
2196 /* struct to store contents of interrupt vectors */
2197 struct rtl_int {
2198 u32 inta;
2199 u32 intb;
2200 u32 intc;
2201 u32 intd;
2202 };
2203
2204 struct rtl_hal_ops {
2205 int (*init_sw_vars)(struct ieee80211_hw *hw);
2206 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2207 void (*read_chip_version)(struct ieee80211_hw *hw);
2208 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2209 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2210 struct rtl_int *intvec);
2211 int (*hw_init)(struct ieee80211_hw *hw);
2212 void (*hw_disable)(struct ieee80211_hw *hw);
2213 void (*hw_suspend)(struct ieee80211_hw *hw);
2214 void (*hw_resume)(struct ieee80211_hw *hw);
2215 void (*enable_interrupt)(struct ieee80211_hw *hw);
2216 void (*disable_interrupt)(struct ieee80211_hw *hw);
2217 int (*set_network_type)(struct ieee80211_hw *hw,
2218 enum nl80211_iftype type);
2219 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2220 bool check_bssid);
2221 void (*set_bw_mode)(struct ieee80211_hw *hw,
2222 enum nl80211_channel_type ch_type);
2223 u8 (*switch_channel)(struct ieee80211_hw *hw);
2224 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2225 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2226 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2227 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2228 u32 add_msr, u32 rm_msr);
2229 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2230 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2231 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2232 struct ieee80211_sta *sta, u8 rssi_leve,
2233 bool update_bw);
2234 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2235 u8 *desc, u8 queue_index,
2236 struct sk_buff *skb, dma_addr_t addr);
2237 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2238 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2239 u8 queue_index);
2240 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2241 u8 queue_index);
2242 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2243 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2244 u8 *pbd_desc_tx,
2245 struct ieee80211_tx_info *info,
2246 struct ieee80211_sta *sta,
2247 struct sk_buff *skb, u8 hw_queue,
2248 struct rtl_tcb_desc *ptcb_desc);
2249 void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
2250 u32 buffer_len, bool bsspspoll);
2251 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2252 bool firstseg, bool lastseg,
2253 struct sk_buff *skb);
2254 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2255 u8 *pdesc, u8 *pbd_desc,
2256 struct sk_buff *skb, u8 hw_queue);
2257 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2258 struct rtl_stats *stats,
2259 struct ieee80211_rx_status *rx_status,
2260 u8 *pdesc, struct sk_buff *skb);
2261 void (*set_channel_access)(struct ieee80211_hw *hw);
2262 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2263 void (*dm_watchdog)(struct ieee80211_hw *hw);
2264 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2265 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2266 enum rf_pwrstate rfpwr_state);
2267 void (*led_control)(struct ieee80211_hw *hw,
2268 enum led_ctl_mode ledaction);
2269 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2270 u8 desc_name, u8 *val);
2271 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2272 u8 desc_name);
2273 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2274 u8 hw_queue, u16 index);
2275 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2276 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2277 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2278 u8 *macaddr, bool is_group, u8 enc_algo,
2279 bool is_wepkey, bool clear_all);
2280 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2281 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2282 u32 data);
2283 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2284 u32 regaddr, u32 bitmask);
2285 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2286 u32 regaddr, u32 bitmask, u32 data);
2287 void (*linked_set_reg)(struct ieee80211_hw *hw);
2288 void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
2289 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2290 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2291 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2292 u8 *powerlevel);
2293 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2294 u8 *ppowerlevel, u8 channel);
2295 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2296 u8 configtype);
2297 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2298 u8 configtype);
2299 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2300 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2301 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2302 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2303 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2304 bool mstate);
2305 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2306 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2307 u32 cmd_len, u8 *p_cmdbuffer);
2308 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2309 bool (*get_btc_status)(void);
2310 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2311 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2312 struct rtl_wow_pattern *rtl_pattern,
2313 u8 index);
2314 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2315 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw,
2316 u8 *cmd_buf, u8 cmd_len);
2317 };
2318
2319 struct rtl_intf_ops {
2320 /*com */
2321 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2322 int (*adapter_start)(struct ieee80211_hw *hw);
2323 void (*adapter_stop)(struct ieee80211_hw *hw);
2324 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2325 struct rtl_priv **buddy_priv);
2326
2327 int (*adapter_tx)(struct ieee80211_hw *hw,
2328 struct ieee80211_sta *sta,
2329 struct sk_buff *skb,
2330 struct rtl_tcb_desc *ptcb_desc);
2331 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2332 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2333 bool (*waitq_insert)(struct ieee80211_hw *hw,
2334 struct ieee80211_sta *sta,
2335 struct sk_buff *skb);
2336
2337 /*pci */
2338 void (*disable_aspm)(struct ieee80211_hw *hw);
2339 void (*enable_aspm)(struct ieee80211_hw *hw);
2340
2341 /*usb */
2342 };
2343
2344 struct rtl_mod_params {
2345 /* default: 0,0 */
2346 u64 debug_mask;
2347 /* default: 0 = using hardware encryption */
2348 bool sw_crypto;
2349
2350 /* default: 0 = DBG_EMERG (0)*/
2351 int debug_level;
2352
2353 /* default: 1 = using no linked power save */
2354 bool inactiveps;
2355
2356 /* default: 1 = using linked sw power save */
2357 bool swctrl_lps;
2358
2359 /* default: 1 = using linked fw power save */
2360 bool fwctrl_lps;
2361
2362 /* default: 0 = not using MSI interrupts mode
2363 * submodules should set their own default value
2364 */
2365 bool msi_support;
2366
2367 /* default: 0 = dma 32 */
2368 bool dma64;
2369
2370 /* default: 1 = enable aspm */
2371 int aspm_support;
2372
2373 /* default 0: 1 means disable */
2374 bool disable_watchdog;
2375
2376 /* default 0: 1 means do not disable interrupts */
2377 bool int_clear;
2378
2379 /* select antenna */
2380 int ant_sel;
2381 };
2382
2383 struct rtl_hal_usbint_cfg {
2384 /* data - rx */
2385 u32 in_ep_num;
2386 u32 rx_urb_num;
2387 u32 rx_max_size;
2388
2389 /* op - rx */
2390 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2391 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2392 struct sk_buff_head *);
2393
2394 /* tx */
2395 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2396 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2397 struct sk_buff *);
2398 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2399 struct sk_buff_head *);
2400
2401 /* endpoint mapping */
2402 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2403 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2404 };
2405
2406 struct rtl_hal_cfg {
2407 u8 bar_id;
2408 bool write_readback;
2409 char *name;
2410 char *alt_fw_name;
2411 struct rtl_hal_ops *ops;
2412 struct rtl_mod_params *mod_params;
2413 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2414 enum rtl_spec_ver spec_ver;
2415
2416 /*this map used for some registers or vars
2417 * defined int HAL but used in MAIN
2418 */
2419 u32 maps[RTL_VAR_MAP_MAX];
2420
2421 };
2422
2423 struct rtl_locks {
2424 /* mutex */
2425 struct mutex conf_mutex;
2426 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2427 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2428
2429 /*spin lock */
2430 spinlock_t irq_th_lock;
2431 spinlock_t h2c_lock;
2432 spinlock_t rf_ps_lock;
2433 spinlock_t rf_lock;
2434 spinlock_t waitq_lock;
2435 spinlock_t entry_list_lock;
2436 spinlock_t usb_lock;
2437 spinlock_t scan_list_lock; /* lock for the scan list */
2438
2439 /*FW clock change */
2440 spinlock_t fw_ps_lock;
2441
2442 /*Dual mac*/
2443 spinlock_t cck_and_rw_pagea_lock;
2444
2445 spinlock_t iqk_lock;
2446 };
2447
2448 struct rtl_works {
2449 struct ieee80211_hw *hw;
2450
2451 /*timer */
2452 struct timer_list watchdog_timer;
2453 struct timer_list fw_clockoff_timer;
2454 struct timer_list fast_antenna_training_timer;
2455 /*task */
2456 struct tasklet_struct irq_tasklet;
2457 struct tasklet_struct irq_prepare_bcn_tasklet;
2458
2459 /*work queue */
2460 struct workqueue_struct *rtl_wq;
2461 struct delayed_work watchdog_wq;
2462 struct delayed_work ips_nic_off_wq;
2463 struct delayed_work c2hcmd_wq;
2464
2465 /* For SW LPS */
2466 struct delayed_work ps_work;
2467 struct delayed_work ps_rfon_wq;
2468 struct delayed_work fwevt_wq;
2469
2470 struct work_struct lps_change_work;
2471 struct work_struct fill_h2c_cmd;
2472 struct work_struct update_beacon_work;
2473 };
2474
2475 struct rtl_debug {
2476 /* add for debug */
2477 struct dentry *debugfs_dir;
2478 char debugfs_name[20];
2479 };
2480
2481 #define MIMO_PS_STATIC 0
2482 #define MIMO_PS_DYNAMIC 1
2483 #define MIMO_PS_NOLIMIT 3
2484
2485 struct rtl_dmsp_ctl {
2486 bool activescan_for_slaveofdmsp;
2487 bool scan_for_anothermac_fordmsp;
2488 bool scan_for_itself_fordmsp;
2489 bool writedig_for_anothermacofdmsp;
2490 u32 curdigvalue_for_anothermacofdmsp;
2491 bool changecckpdstate_for_anothermacofdmsp;
2492 u8 curcckpdstate_for_anothermacofdmsp;
2493 bool changetxhighpowerlvl_for_anothermacofdmsp;
2494 u8 curtxhighlvl_for_anothermacofdmsp;
2495 long rssivalmin_for_anothermacofdmsp;
2496 };
2497
2498 struct ps_t {
2499 u8 pre_ccastate;
2500 u8 cur_ccasate;
2501 u8 pre_rfstate;
2502 u8 cur_rfstate;
2503 u8 initialize;
2504 long rssi_val_min;
2505 };
2506
2507 struct dig_t {
2508 u32 rssi_lowthresh;
2509 u32 rssi_highthresh;
2510 u32 fa_lowthresh;
2511 u32 fa_highthresh;
2512 long last_min_undec_pwdb_for_dm;
2513 long rssi_highpower_lowthresh;
2514 long rssi_highpower_highthresh;
2515 u32 recover_cnt;
2516 u32 pre_igvalue;
2517 u32 cur_igvalue;
2518 long rssi_val;
2519 u8 dig_enable_flag;
2520 u8 dig_ext_port_stage;
2521 u8 dig_algorithm;
2522 u8 dig_twoport_algorithm;
2523 u8 dig_dbgmode;
2524 u8 dig_slgorithm_switch;
2525 u8 cursta_cstate;
2526 u8 presta_cstate;
2527 u8 curmultista_cstate;
2528 u8 stop_dig;
2529 s8 back_val;
2530 s8 back_range_max;
2531 s8 back_range_min;
2532 u8 rx_gain_max;
2533 u8 rx_gain_min;
2534 u8 min_undec_pwdb_for_dm;
2535 u8 rssi_val_min;
2536 u8 pre_cck_cca_thres;
2537 u8 cur_cck_cca_thres;
2538 u8 pre_cck_pd_state;
2539 u8 cur_cck_pd_state;
2540 u8 pre_cck_fa_state;
2541 u8 cur_cck_fa_state;
2542 u8 pre_ccastate;
2543 u8 cur_ccasate;
2544 u8 large_fa_hit;
2545 u8 forbidden_igi;
2546 u8 dig_state;
2547 u8 dig_highpwrstate;
2548 u8 cur_sta_cstate;
2549 u8 pre_sta_cstate;
2550 u8 cur_ap_cstate;
2551 u8 pre_ap_cstate;
2552 u8 cur_pd_thstate;
2553 u8 pre_pd_thstate;
2554 u8 cur_cs_ratiostate;
2555 u8 pre_cs_ratiostate;
2556 u8 backoff_enable_flag;
2557 s8 backoffval_range_max;
2558 s8 backoffval_range_min;
2559 u8 dig_min_0;
2560 u8 dig_min_1;
2561 u8 bt30_cur_igi;
2562 bool media_connect_0;
2563 bool media_connect_1;
2564
2565 u32 antdiv_rssi_max;
2566 u32 rssi_max;
2567 };
2568
2569 struct rtl_global_var {
2570 /* from this list we can get
2571 * other adapter's rtl_priv
2572 */
2573 struct list_head glb_priv_list;
2574 spinlock_t glb_list_lock;
2575 };
2576
2577 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2578
2579 struct rtl_btc_info {
2580 u8 bt_type;
2581 u8 btcoexist;
2582 u8 ant_num;
2583 u8 single_ant_path;
2584
2585 u8 ap_num;
2586 bool in_4way;
2587 unsigned long in_4way_ts;
2588 };
2589
2590 struct bt_coexist_info {
2591 struct rtl_btc_ops *btc_ops;
2592 struct rtl_btc_info btc_info;
2593 /* btc context */
2594 void *btc_context;
2595 void *wifi_only_context;
2596 /* EEPROM BT info. */
2597 u8 eeprom_bt_coexist;
2598 u8 eeprom_bt_type;
2599 u8 eeprom_bt_ant_num;
2600 u8 eeprom_bt_ant_isol;
2601 u8 eeprom_bt_radio_shared;
2602
2603 u8 bt_coexistence;
2604 u8 bt_ant_num;
2605 u8 bt_coexist_type;
2606 u8 bt_state;
2607 u8 bt_cur_state; /* 0:on, 1:off */
2608 u8 bt_ant_isolation; /* 0:good, 1:bad */
2609 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2610 u8 bt_service;
2611 u8 bt_radio_shared_type;
2612 u8 bt_rfreg_origin_1e;
2613 u8 bt_rfreg_origin_1f;
2614 u8 bt_rssi_state;
2615 u32 ratio_tx;
2616 u32 ratio_pri;
2617 u32 bt_edca_ul;
2618 u32 bt_edca_dl;
2619
2620 bool init_set;
2621 bool bt_busy_traffic;
2622 bool bt_traffic_mode_set;
2623 bool bt_non_traffic_mode_set;
2624
2625 bool fw_coexist_all_off;
2626 bool sw_coexist_all_off;
2627 bool hw_coexist_all_off;
2628 u32 cstate;
2629 u32 previous_state;
2630 u32 cstate_h;
2631 u32 previous_state_h;
2632
2633 u8 bt_pre_rssi_state;
2634 u8 bt_pre_rssi_state1;
2635
2636 u8 reg_bt_iso;
2637 u8 reg_bt_sco;
2638 bool balance_on;
2639 u8 bt_active_zero_cnt;
2640 bool cur_bt_disabled;
2641 bool pre_bt_disabled;
2642
2643 u8 bt_profile_case;
2644 u8 bt_profile_action;
2645 bool bt_busy;
2646 bool hold_for_bt_operation;
2647 u8 lps_counter;
2648 };
2649
2650 struct rtl_btc_ops {
2651 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2652 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2653 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2654 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2655 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2656 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2657 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2658 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2659 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2660 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2661 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2662 u8 scantype);
2663 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2664 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2665 enum rt_media_status mstatus);
2666 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2667 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2668 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2669 u8 *tmp_buf, u8 length);
2670 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2671 u8 *tmp_buf, u8 length);
2672 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2673 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2674 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2675 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2676 u8 pkt_type);
2677 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2678 bool scanning);
2679 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2680 u8 type, bool scanning);
2681 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2682 struct seq_file *m);
2683 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2684 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2685 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2686 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2687 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2688 u8 *ctrl_agg_size, u8 *agg_size);
2689 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2690 };
2691
2692 struct proxim {
2693 bool proxim_on;
2694
2695 void *proximity_priv;
2696 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2697 struct sk_buff *skb);
2698 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2699 };
2700
2701 struct rtl_c2hcmd {
2702 struct list_head list;
2703 u8 tag;
2704 u8 len;
2705 u8 *val;
2706 };
2707
2708 struct rtl_bssid_entry {
2709 struct list_head list;
2710 u8 bssid[ETH_ALEN];
2711 u32 age;
2712 };
2713
2714 struct rtl_scan_list {
2715 int num;
2716 struct list_head list; /* sort by age */
2717 };
2718
2719 struct rtl_priv {
2720 struct ieee80211_hw *hw;
2721 struct completion firmware_loading_complete;
2722 struct list_head list;
2723 struct rtl_priv *buddy_priv;
2724 struct rtl_global_var *glb_var;
2725 struct rtl_dmsp_ctl dmsp_ctl;
2726 struct rtl_locks locks;
2727 struct rtl_works works;
2728 struct rtl_mac mac80211;
2729 struct rtl_hal rtlhal;
2730 struct rtl_regulatory regd;
2731 struct rtl_rfkill rfkill;
2732 struct rtl_io io;
2733 struct rtl_phy phy;
2734 struct rtl_dm dm;
2735 struct rtl_security sec;
2736 struct rtl_efuse efuse;
2737 struct rtl_led_ctl ledctl;
2738 struct rtl_tx_report tx_report;
2739 struct rtl_scan_list scan_list;
2740
2741 struct rtl_ps_ctl psc;
2742 struct rate_adaptive ra;
2743 struct dynamic_primary_cca primarycca;
2744 struct wireless_stats stats;
2745 struct rt_link_detect link_info;
2746 struct false_alarm_statistics falsealm_cnt;
2747
2748 struct rtl_rate_priv *rate_priv;
2749
2750 /* sta entry list for ap adhoc or mesh */
2751 struct list_head entry_list;
2752
2753 /* c2hcmd list for kthread level access */
2754 struct sk_buff_head c2hcmd_queue;
2755
2756 struct rtl_debug dbg;
2757 int max_fw_size;
2758
2759 /* hal_cfg : for diff cards
2760 * intf_ops : for diff interrface usb/pcie
2761 */
2762 struct rtl_hal_cfg *cfg;
2763 const struct rtl_intf_ops *intf_ops;
2764
2765 /* this var will be set by set_bit,
2766 * and was used to indicate status of
2767 * interface or hardware
2768 */
2769 unsigned long status;
2770
2771 /* tables for dm */
2772 struct dig_t dm_digtable;
2773 struct ps_t dm_pstable;
2774
2775 u32 reg_874;
2776 u32 reg_c70;
2777 u32 reg_85c;
2778 u32 reg_a74;
2779 bool reg_init; /* true if regs saved */
2780 bool bt_operation_on;
2781 __le32 *usb_data;
2782 int usb_data_index;
2783 bool initialized;
2784 bool enter_ps; /* true when entering PS */
2785 u8 rate_mask[5];
2786
2787 /* intel Proximity, should be alloc mem
2788 * in intel Proximity module and can only
2789 * be used in intel Proximity mode
2790 */
2791 struct proxim proximity;
2792
2793 /*for bt coexist use*/
2794 struct bt_coexist_info btcoexist;
2795
2796 /* separate 92ee from other ICs,
2797 * 92ee use new trx flow.
2798 */
2799 bool use_new_trx_flow;
2800
2801 #ifdef CONFIG_PM
2802 struct wiphy_wowlan_support wowlan;
2803 #endif
2804 /* This must be the last item so
2805 * that it points to the data allocated
2806 * beyond this structure like:
2807 * rtl_pci_priv or rtl_usb_priv
2808 */
2809 u8 priv[] __aligned(sizeof(void *));
2810 };
2811
2812 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2813 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2814 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2815 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2816 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2817
2818 /* Bluetooth Co-existence Related */
2819
2820 enum bt_ant_num {
2821 ANT_X2 = 0,
2822 ANT_X1 = 1,
2823 };
2824
2825 enum bt_ant_path {
2826 ANT_MAIN = 0,
2827 ANT_AUX = 1,
2828 };
2829
2830 enum bt_co_type {
2831 BT_2WIRE = 0,
2832 BT_ISSC_3WIRE = 1,
2833 BT_ACCEL = 2,
2834 BT_CSR_BC4 = 3,
2835 BT_CSR_BC8 = 4,
2836 BT_RTL8756 = 5,
2837 BT_RTL8723A = 6,
2838 BT_RTL8821A = 7,
2839 BT_RTL8723B = 8,
2840 BT_RTL8192E = 9,
2841 BT_RTL8812A = 11,
2842 };
2843
2844 enum bt_cur_state {
2845 BT_OFF = 0,
2846 BT_ON = 1,
2847 };
2848
2849 enum bt_service_type {
2850 BT_SCO = 0,
2851 BT_A2DP = 1,
2852 BT_HID = 2,
2853 BT_HID_IDLE = 3,
2854 BT_SCAN = 4,
2855 BT_IDLE = 5,
2856 BT_OTHER_ACTION = 6,
2857 BT_BUSY = 7,
2858 BT_OTHERBUSY = 8,
2859 BT_PAN = 9,
2860 };
2861
2862 enum bt_radio_shared {
2863 BT_RADIO_SHARED = 0,
2864 BT_RADIO_INDIVIDUAL = 1,
2865 };
2866
2867 /****************************************
2868 * mem access macro define start
2869 * Call endian free function when
2870 * 1. Read/write packet content.
2871 * 2. Before write integer to IO.
2872 * 3. After read integer from IO.
2873 ****************************************/
2874
2875 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2876 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2877
2878 /* mem access macro define end */
2879
2880 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2881
2882 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2883 #define RTL_WATCH_DOG_TIME 2000
2884 #define MSECS(t) msecs_to_jiffies(t)
2885 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2886 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2887 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2888 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2889 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2890
2891 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2892 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2893 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2894 /*NIC halt, re-initialize hw parameters*/
2895 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2896 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2897 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2898 /*Always enable ASPM and Clock Req in initialization.*/
2899 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2900 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2901 #define RT_PS_LEVEL_ASPM BIT(7)
2902 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2903 #define RT_RF_LPS_DISALBE_2R BIT(30)
2904 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2905 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2906 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2907 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2908 (ppsc->cur_ps_level &= (~(_ps_flg)))
2909 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2910 (ppsc->cur_ps_level |= _ps_flg)
2911
2912 #define FILL_OCTET_STRING(_os, _octet, _len) \
2913 (_os).octet = (u8 *)(_octet); \
2914 (_os).length = (_len);
2915
2916 #define CP_MACADDR(des, src) \
2917 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2918 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2919 (des)[4] = (src)[4], (des)[5] = (src)[5])
2920
2921 #define LDPC_HT_ENABLE_RX BIT(0)
2922 #define LDPC_HT_ENABLE_TX BIT(1)
2923 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2924 #define LDPC_HT_CAP_TX BIT(3)
2925
2926 #define STBC_HT_ENABLE_RX BIT(0)
2927 #define STBC_HT_ENABLE_TX BIT(1)
2928 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2929 #define STBC_HT_CAP_TX BIT(3)
2930
2931 #define LDPC_VHT_ENABLE_RX BIT(0)
2932 #define LDPC_VHT_ENABLE_TX BIT(1)
2933 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2934 #define LDPC_VHT_CAP_TX BIT(3)
2935
2936 #define STBC_VHT_ENABLE_RX BIT(0)
2937 #define STBC_VHT_ENABLE_TX BIT(1)
2938 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2939 #define STBC_VHT_CAP_TX BIT(3)
2940
2941 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2942
2943 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2944
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)2945 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2946 {
2947 return rtlpriv->io.read8_sync(rtlpriv, addr);
2948 }
2949
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)2950 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2951 {
2952 return rtlpriv->io.read16_sync(rtlpriv, addr);
2953 }
2954
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)2955 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2956 {
2957 return rtlpriv->io.read32_sync(rtlpriv, addr);
2958 }
2959
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)2960 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2961 {
2962 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2963
2964 if (rtlpriv->cfg->write_readback)
2965 rtlpriv->io.read8_sync(rtlpriv, addr);
2966 }
2967
rtl_write_byte_with_val32(struct ieee80211_hw * hw,u32 addr,u32 val8)2968 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
2969 u32 addr, u32 val8)
2970 {
2971 struct rtl_priv *rtlpriv = rtl_priv(hw);
2972
2973 rtl_write_byte(rtlpriv, addr, (u8)val8);
2974 }
2975
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)2976 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2977 {
2978 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2979
2980 if (rtlpriv->cfg->write_readback)
2981 rtlpriv->io.read16_sync(rtlpriv, addr);
2982 }
2983
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)2984 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2985 u32 addr, u32 val32)
2986 {
2987 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2988
2989 if (rtlpriv->cfg->write_readback)
2990 rtlpriv->io.read32_sync(rtlpriv, addr);
2991 }
2992
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)2993 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2994 u32 regaddr, u32 bitmask)
2995 {
2996 struct rtl_priv *rtlpriv = hw->priv;
2997
2998 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2999 }
3000
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)3001 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3002 u32 bitmask, u32 data)
3003 {
3004 struct rtl_priv *rtlpriv = hw->priv;
3005
3006 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3007 }
3008
rtl_set_bbreg_with_dwmask(struct ieee80211_hw * hw,u32 regaddr,u32 data)3009 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3010 u32 regaddr, u32 data)
3011 {
3012 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3013 }
3014
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)3015 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3016 enum radio_path rfpath, u32 regaddr,
3017 u32 bitmask)
3018 {
3019 struct rtl_priv *rtlpriv = hw->priv;
3020
3021 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3022 }
3023
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)3024 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3025 enum radio_path rfpath, u32 regaddr,
3026 u32 bitmask, u32 data)
3027 {
3028 struct rtl_priv *rtlpriv = hw->priv;
3029
3030 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3031 }
3032
is_hal_stop(struct rtl_hal * rtlhal)3033 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3034 {
3035 return (_HAL_STATE_STOP == rtlhal->state);
3036 }
3037
set_hal_start(struct rtl_hal * rtlhal)3038 static inline void set_hal_start(struct rtl_hal *rtlhal)
3039 {
3040 rtlhal->state = _HAL_STATE_START;
3041 }
3042
set_hal_stop(struct rtl_hal * rtlhal)3043 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3044 {
3045 rtlhal->state = _HAL_STATE_STOP;
3046 }
3047
get_rf_type(struct rtl_phy * rtlphy)3048 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3049 {
3050 return rtlphy->rf_type;
3051 }
3052
rtl_get_hdr(struct sk_buff * skb)3053 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3054 {
3055 return (struct ieee80211_hdr *)(skb->data);
3056 }
3057
rtl_get_fc(struct sk_buff * skb)3058 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3059 {
3060 return rtl_get_hdr(skb)->frame_control;
3061 }
3062
rtl_get_tid(struct sk_buff * skb)3063 static inline u16 rtl_get_tid(struct sk_buff *skb)
3064 {
3065 return ieee80211_get_tid(rtl_get_hdr(skb));
3066 }
3067
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)3068 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3069 struct ieee80211_vif *vif,
3070 const u8 *bssid)
3071 {
3072 return ieee80211_find_sta(vif, bssid);
3073 }
3074
rtl_find_sta(struct ieee80211_hw * hw,u8 * mac_addr)3075 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3076 u8 *mac_addr)
3077 {
3078 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3079
3080 return ieee80211_find_sta(mac->vif, mac_addr);
3081 }
3082
calculate_bit_shift(u32 bitmask)3083 static inline u32 calculate_bit_shift(u32 bitmask)
3084 {
3085 if (WARN_ON_ONCE(!bitmask))
3086 return 0;
3087
3088 return __ffs(bitmask);
3089 }
3090 #endif
3091