1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26 #include "fuc/os.h"
27
28 #include <core/client.h>
29 #include <core/firmware.h>
30 #include <core/option.h>
31 #include <subdev/acr.h>
32 #include <subdev/fb.h>
33 #include <subdev/mc.h>
34 #include <subdev/pmu.h>
35 #include <subdev/therm.h>
36 #include <subdev/timer.h>
37 #include <engine/fifo.h>
38
39 #include <nvif/class.h>
40 #include <nvif/cl9097.h>
41 #include <nvif/if900d.h>
42 #include <nvif/unpack.h>
43
44 /*******************************************************************************
45 * Zero Bandwidth Clear
46 ******************************************************************************/
47
48 static void
gf100_gr_zbc_clear_color(struct gf100_gr * gr,int zbc)49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
50 {
51 struct nvkm_device *device = gr->base.engine.subdev.device;
52 if (gr->zbc_color[zbc].format) {
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
57 }
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
59 nvkm_wr32(device, 0x405820, zbc);
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
61 }
62
63 static int
gf100_gr_zbc_color_get(struct gf100_gr * gr,int format,const u32 ds[4],const u32 l2[4])64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
65 const u32 ds[4], const u32 l2[4])
66 {
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
68 int zbc = -ENOSPC, i;
69
70 for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) {
71 if (gr->zbc_color[i].format) {
72 if (gr->zbc_color[i].format != format)
73 continue;
74 if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
75 gr->zbc_color[i].ds)))
76 continue;
77 if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
78 gr->zbc_color[i].l2))) {
79 WARN_ON(1);
80 return -EINVAL;
81 }
82 return i;
83 } else {
84 zbc = (zbc < 0) ? i : zbc;
85 }
86 }
87
88 if (zbc < 0)
89 return zbc;
90
91 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
92 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
93 gr->zbc_color[zbc].format = format;
94 nvkm_ltc_zbc_color_get(ltc, zbc, l2);
95 gr->func->zbc->clear_color(gr, zbc);
96 return zbc;
97 }
98
99 static void
gf100_gr_zbc_clear_depth(struct gf100_gr * gr,int zbc)100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
101 {
102 struct nvkm_device *device = gr->base.engine.subdev.device;
103 if (gr->zbc_depth[zbc].format)
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
106 nvkm_wr32(device, 0x405820, zbc);
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
108 }
109
110 static int
gf100_gr_zbc_depth_get(struct gf100_gr * gr,int format,const u32 ds,const u32 l2)111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
112 const u32 ds, const u32 l2)
113 {
114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
115 int zbc = -ENOSPC, i;
116
117 for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
118 if (gr->zbc_depth[i].format) {
119 if (gr->zbc_depth[i].format != format)
120 continue;
121 if (gr->zbc_depth[i].ds != ds)
122 continue;
123 if (gr->zbc_depth[i].l2 != l2) {
124 WARN_ON(1);
125 return -EINVAL;
126 }
127 return i;
128 } else {
129 zbc = (zbc < 0) ? i : zbc;
130 }
131 }
132
133 if (zbc < 0)
134 return zbc;
135
136 gr->zbc_depth[zbc].format = format;
137 gr->zbc_depth[zbc].ds = ds;
138 gr->zbc_depth[zbc].l2 = l2;
139 nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
140 gr->func->zbc->clear_depth(gr, zbc);
141 return zbc;
142 }
143
144 const struct gf100_gr_func_zbc
145 gf100_gr_zbc = {
146 .clear_color = gf100_gr_zbc_clear_color,
147 .clear_depth = gf100_gr_zbc_clear_depth,
148 };
149
150 /*******************************************************************************
151 * Graphics object classes
152 ******************************************************************************/
153 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
154
155 struct gf100_gr_object {
156 struct nvkm_object object;
157 struct gf100_gr_chan *chan;
158 };
159
160 static int
gf100_fermi_mthd_zbc_color(struct nvkm_object * object,void * data,u32 size)161 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
162 {
163 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
164 union {
165 struct fermi_a_zbc_color_v0 v0;
166 } *args = data;
167 int ret = -ENOSYS;
168
169 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
170 switch (args->v0.format) {
171 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
172 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
173 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
174 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
175 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
176 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
177 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
178 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
179 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
180 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
181 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
182 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
183 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
184 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
185 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
186 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
187 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
188 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
189 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
190 ret = gf100_gr_zbc_color_get(gr, args->v0.format,
191 args->v0.ds,
192 args->v0.l2);
193 if (ret >= 0) {
194 args->v0.index = ret;
195 return 0;
196 }
197 break;
198 default:
199 return -EINVAL;
200 }
201 }
202
203 return ret;
204 }
205
206 static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object * object,void * data,u32 size)207 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
208 {
209 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
210 union {
211 struct fermi_a_zbc_depth_v0 v0;
212 } *args = data;
213 int ret = -ENOSYS;
214
215 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
216 switch (args->v0.format) {
217 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
218 ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
219 args->v0.ds,
220 args->v0.l2);
221 return (ret >= 0) ? 0 : -ENOSPC;
222 default:
223 return -EINVAL;
224 }
225 }
226
227 return ret;
228 }
229
230 static int
gf100_fermi_mthd(struct nvkm_object * object,u32 mthd,void * data,u32 size)231 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
232 {
233 nvif_ioctl(object, "fermi mthd %08x\n", mthd);
234 switch (mthd) {
235 case FERMI_A_ZBC_COLOR:
236 return gf100_fermi_mthd_zbc_color(object, data, size);
237 case FERMI_A_ZBC_DEPTH:
238 return gf100_fermi_mthd_zbc_depth(object, data, size);
239 default:
240 break;
241 }
242 return -EINVAL;
243 }
244
245 const struct nvkm_object_func
246 gf100_fermi = {
247 .mthd = gf100_fermi_mthd,
248 };
249
250 static void
gf100_gr_mthd_set_shader_exceptions(struct nvkm_device * device,u32 data)251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
252 {
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
255 }
256
257 static bool
gf100_gr_mthd_sw(struct nvkm_device * device,u16 class,u32 mthd,u32 data)258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
259 {
260 switch (class & 0x00ff) {
261 case 0x97:
262 case 0xc0:
263 switch (mthd) {
264 case 0x1528:
265 gf100_gr_mthd_set_shader_exceptions(device, data);
266 return true;
267 default:
268 break;
269 }
270 break;
271 default:
272 break;
273 }
274 return false;
275 }
276
277 static const struct nvkm_object_func
278 gf100_gr_object_func = {
279 };
280
281 static int
gf100_gr_object_new(const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)282 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
283 struct nvkm_object **pobject)
284 {
285 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
286 struct gf100_gr_object *object;
287
288 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
289 return -ENOMEM;
290 *pobject = &object->object;
291
292 nvkm_object_ctor(oclass->base.func ? oclass->base.func :
293 &gf100_gr_object_func, oclass, &object->object);
294 object->chan = chan;
295 return 0;
296 }
297
298 static int
gf100_gr_object_get(struct nvkm_gr * base,int index,struct nvkm_sclass * sclass)299 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
300 {
301 struct gf100_gr *gr = gf100_gr(base);
302 int c = 0;
303
304 while (gr->func->sclass[c].oclass) {
305 if (c++ == index) {
306 *sclass = gr->func->sclass[index];
307 sclass->ctor = gf100_gr_object_new;
308 return index;
309 }
310 }
311
312 return c;
313 }
314
315 /*******************************************************************************
316 * PGRAPH context
317 ******************************************************************************/
318
319 static int
gf100_gr_chan_bind(struct nvkm_object * object,struct nvkm_gpuobj * parent,int align,struct nvkm_gpuobj ** pgpuobj)320 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
321 int align, struct nvkm_gpuobj **pgpuobj)
322 {
323 struct gf100_gr_chan *chan = gf100_gr_chan(object);
324 struct gf100_gr *gr = chan->gr;
325 int ret, i;
326
327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
328 align, false, parent, pgpuobj);
329 if (ret)
330 return ret;
331
332 nvkm_kmap(*pgpuobj);
333 for (i = 0; i < gr->size; i += 4)
334 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
335
336 if (!gr->firmware) {
337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
339 } else {
340 nvkm_wo32(*pgpuobj, 0xf4, 0);
341 nvkm_wo32(*pgpuobj, 0xf8, 0);
342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
344 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
345 nvkm_wo32(*pgpuobj, 0x1c, 1);
346 nvkm_wo32(*pgpuobj, 0x20, 0);
347 nvkm_wo32(*pgpuobj, 0x28, 0);
348 nvkm_wo32(*pgpuobj, 0x2c, 0);
349 }
350 nvkm_done(*pgpuobj);
351 return 0;
352 }
353
354 static void *
gf100_gr_chan_dtor(struct nvkm_object * object)355 gf100_gr_chan_dtor(struct nvkm_object *object)
356 {
357 struct gf100_gr_chan *chan = gf100_gr_chan(object);
358
359 nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
360 nvkm_memory_unref(&chan->mmio);
361
362 nvkm_vmm_put(chan->vmm, &chan->attrib_cb);
363 nvkm_vmm_put(chan->vmm, &chan->unknown);
364 nvkm_vmm_put(chan->vmm, &chan->bundle_cb);
365 nvkm_vmm_put(chan->vmm, &chan->pagepool);
366 nvkm_vmm_unref(&chan->vmm);
367 return chan;
368 }
369
370 static const struct nvkm_object_func
371 gf100_gr_chan = {
372 .dtor = gf100_gr_chan_dtor,
373 .bind = gf100_gr_chan_bind,
374 };
375
376 static int
gf100_gr_chan_new(struct nvkm_gr * base,struct nvkm_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)377 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
378 const struct nvkm_oclass *oclass,
379 struct nvkm_object **pobject)
380 {
381 struct gf100_gr *gr = gf100_gr(base);
382 struct gf100_gr_chan *chan;
383 struct gf100_vmm_map_v0 args = { .priv = 1 };
384 struct nvkm_device *device = gr->base.engine.subdev.device;
385 int ret;
386
387 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
388 return -ENOMEM;
389 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
390 chan->gr = gr;
391 chan->vmm = nvkm_vmm_ref(fifoch->vmm);
392 *pobject = &chan->object;
393
394 /* Map pagepool. */
395 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->pagepool), &chan->pagepool);
396 if (ret)
397 return ret;
398
399 ret = nvkm_memory_map(gr->pagepool, 0, chan->vmm, chan->pagepool, &args, sizeof(args));
400 if (ret)
401 return ret;
402
403 /* Map bundle circular buffer. */
404 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->bundle_cb), &chan->bundle_cb);
405 if (ret)
406 return ret;
407
408 ret = nvkm_memory_map(gr->bundle_cb, 0, chan->vmm, chan->bundle_cb, &args, sizeof(args));
409 if (ret)
410 return ret;
411
412 /* Map attribute circular buffer. */
413 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->attrib_cb), &chan->attrib_cb);
414 if (ret)
415 return ret;
416
417 if (device->card_type < GP100) {
418 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, NULL, 0);
419 if (ret)
420 return ret;
421 } else {
422 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb,
423 &args, sizeof(args));;
424 if (ret)
425 return ret;
426 }
427
428 /* Map some context buffer of unknown purpose. */
429 if (gr->func->grctx->unknown_size) {
430 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->unknown), &chan->unknown);
431 if (ret)
432 return ret;
433
434 ret = nvkm_memory_map(gr->unknown, 0, chan->vmm, chan->unknown,
435 &args, sizeof(args));
436 if (ret)
437 return ret;
438 }
439
440 /* Generate golden context image. */
441 mutex_lock(&gr->fecs.mutex);
442 if (gr->data == NULL) {
443 ret = gf100_grctx_generate(gr, chan, fifoch->inst);
444 if (ret) {
445 nvkm_error(&base->engine.subdev, "failed to construct context\n");
446 mutex_unlock(&gr->fecs.mutex);
447 return ret;
448 }
449 }
450 mutex_unlock(&gr->fecs.mutex);
451
452 /* allocate memory for a "mmio list" buffer that's used by the HUB
453 * fuc to modify some per-context register settings on first load
454 * of the context.
455 */
456 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
457 false, &chan->mmio);
458 if (ret)
459 return ret;
460
461 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
462 if (ret)
463 return ret;
464
465 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
466 chan->mmio_vma, &args, sizeof(args));
467 if (ret)
468 return ret;
469
470 /* finally, fill in the mmio list and point the context at it */
471 nvkm_kmap(chan->mmio);
472 gr->func->grctx->pagepool(chan, chan->pagepool->addr);
473 gr->func->grctx->bundle(chan, chan->bundle_cb->addr, gr->func->grctx->bundle_size);
474 gr->func->grctx->attrib_cb(chan, chan->attrib_cb->addr, gr->func->grctx->attrib_cb_size(gr));
475 gr->func->grctx->attrib(chan);
476 if (gr->func->grctx->patch_ltc)
477 gr->func->grctx->patch_ltc(chan);
478 if (gr->func->grctx->unknown_size)
479 gr->func->grctx->unknown(chan, chan->unknown->addr, gr->func->grctx->unknown_size);
480 nvkm_done(chan->mmio);
481 return 0;
482 }
483
484 /*******************************************************************************
485 * PGRAPH register lists
486 ******************************************************************************/
487
488 const struct gf100_gr_init
489 gf100_gr_init_main_0[] = {
490 { 0x400080, 1, 0x04, 0x003083c2 },
491 { 0x400088, 1, 0x04, 0x00006fe7 },
492 { 0x40008c, 1, 0x04, 0x00000000 },
493 { 0x400090, 1, 0x04, 0x00000030 },
494 { 0x40013c, 1, 0x04, 0x013901f7 },
495 { 0x400140, 1, 0x04, 0x00000100 },
496 { 0x400144, 1, 0x04, 0x00000000 },
497 { 0x400148, 1, 0x04, 0x00000110 },
498 { 0x400138, 1, 0x04, 0x00000000 },
499 { 0x400130, 2, 0x04, 0x00000000 },
500 { 0x400124, 1, 0x04, 0x00000002 },
501 {}
502 };
503
504 const struct gf100_gr_init
505 gf100_gr_init_fe_0[] = {
506 { 0x40415c, 1, 0x04, 0x00000000 },
507 { 0x404170, 1, 0x04, 0x00000000 },
508 {}
509 };
510
511 const struct gf100_gr_init
512 gf100_gr_init_pri_0[] = {
513 { 0x404488, 2, 0x04, 0x00000000 },
514 {}
515 };
516
517 const struct gf100_gr_init
518 gf100_gr_init_rstr2d_0[] = {
519 { 0x407808, 1, 0x04, 0x00000000 },
520 {}
521 };
522
523 const struct gf100_gr_init
524 gf100_gr_init_pd_0[] = {
525 { 0x406024, 1, 0x04, 0x00000000 },
526 {}
527 };
528
529 const struct gf100_gr_init
530 gf100_gr_init_ds_0[] = {
531 { 0x405844, 1, 0x04, 0x00ffffff },
532 { 0x405850, 1, 0x04, 0x00000000 },
533 { 0x405908, 1, 0x04, 0x00000000 },
534 {}
535 };
536
537 const struct gf100_gr_init
538 gf100_gr_init_scc_0[] = {
539 { 0x40803c, 1, 0x04, 0x00000000 },
540 {}
541 };
542
543 const struct gf100_gr_init
544 gf100_gr_init_prop_0[] = {
545 { 0x4184a0, 1, 0x04, 0x00000000 },
546 {}
547 };
548
549 const struct gf100_gr_init
550 gf100_gr_init_gpc_unk_0[] = {
551 { 0x418604, 1, 0x04, 0x00000000 },
552 { 0x418680, 1, 0x04, 0x00000000 },
553 { 0x418714, 1, 0x04, 0x80000000 },
554 { 0x418384, 1, 0x04, 0x00000000 },
555 {}
556 };
557
558 const struct gf100_gr_init
559 gf100_gr_init_setup_0[] = {
560 { 0x418814, 3, 0x04, 0x00000000 },
561 {}
562 };
563
564 const struct gf100_gr_init
565 gf100_gr_init_crstr_0[] = {
566 { 0x418b04, 1, 0x04, 0x00000000 },
567 {}
568 };
569
570 const struct gf100_gr_init
571 gf100_gr_init_setup_1[] = {
572 { 0x4188c8, 1, 0x04, 0x80000000 },
573 { 0x4188cc, 1, 0x04, 0x00000000 },
574 { 0x4188d0, 1, 0x04, 0x00010000 },
575 { 0x4188d4, 1, 0x04, 0x00000001 },
576 {}
577 };
578
579 const struct gf100_gr_init
580 gf100_gr_init_zcull_0[] = {
581 { 0x418910, 1, 0x04, 0x00010001 },
582 { 0x418914, 1, 0x04, 0x00000301 },
583 { 0x418918, 1, 0x04, 0x00800000 },
584 { 0x418980, 1, 0x04, 0x77777770 },
585 { 0x418984, 3, 0x04, 0x77777777 },
586 {}
587 };
588
589 const struct gf100_gr_init
590 gf100_gr_init_gpm_0[] = {
591 { 0x418c04, 1, 0x04, 0x00000000 },
592 { 0x418c88, 1, 0x04, 0x00000000 },
593 {}
594 };
595
596 const struct gf100_gr_init
597 gf100_gr_init_gpc_unk_1[] = {
598 { 0x418d00, 1, 0x04, 0x00000000 },
599 { 0x418f08, 1, 0x04, 0x00000000 },
600 { 0x418e00, 1, 0x04, 0x00000050 },
601 { 0x418e08, 1, 0x04, 0x00000000 },
602 {}
603 };
604
605 const struct gf100_gr_init
606 gf100_gr_init_gcc_0[] = {
607 { 0x41900c, 1, 0x04, 0x00000000 },
608 { 0x419018, 1, 0x04, 0x00000000 },
609 {}
610 };
611
612 const struct gf100_gr_init
613 gf100_gr_init_tpccs_0[] = {
614 { 0x419d08, 2, 0x04, 0x00000000 },
615 { 0x419d10, 1, 0x04, 0x00000014 },
616 {}
617 };
618
619 const struct gf100_gr_init
620 gf100_gr_init_tex_0[] = {
621 { 0x419ab0, 1, 0x04, 0x00000000 },
622 { 0x419ab8, 1, 0x04, 0x000000e7 },
623 { 0x419abc, 2, 0x04, 0x00000000 },
624 {}
625 };
626
627 const struct gf100_gr_init
628 gf100_gr_init_pe_0[] = {
629 { 0x41980c, 3, 0x04, 0x00000000 },
630 { 0x419844, 1, 0x04, 0x00000000 },
631 { 0x41984c, 1, 0x04, 0x00005bc5 },
632 { 0x419850, 4, 0x04, 0x00000000 },
633 {}
634 };
635
636 const struct gf100_gr_init
637 gf100_gr_init_l1c_0[] = {
638 { 0x419c98, 1, 0x04, 0x00000000 },
639 { 0x419ca8, 1, 0x04, 0x80000000 },
640 { 0x419cb4, 1, 0x04, 0x00000000 },
641 { 0x419cb8, 1, 0x04, 0x00008bf4 },
642 { 0x419cbc, 1, 0x04, 0x28137606 },
643 { 0x419cc0, 2, 0x04, 0x00000000 },
644 {}
645 };
646
647 const struct gf100_gr_init
648 gf100_gr_init_wwdx_0[] = {
649 { 0x419bd4, 1, 0x04, 0x00800000 },
650 { 0x419bdc, 1, 0x04, 0x00000000 },
651 {}
652 };
653
654 const struct gf100_gr_init
655 gf100_gr_init_tpccs_1[] = {
656 { 0x419d2c, 1, 0x04, 0x00000000 },
657 {}
658 };
659
660 const struct gf100_gr_init
661 gf100_gr_init_mpc_0[] = {
662 { 0x419c0c, 1, 0x04, 0x00000000 },
663 {}
664 };
665
666 static const struct gf100_gr_init
667 gf100_gr_init_sm_0[] = {
668 { 0x419e00, 1, 0x04, 0x00000000 },
669 { 0x419ea0, 1, 0x04, 0x00000000 },
670 { 0x419ea4, 1, 0x04, 0x00000100 },
671 { 0x419ea8, 1, 0x04, 0x00001100 },
672 { 0x419eac, 1, 0x04, 0x11100702 },
673 { 0x419eb0, 1, 0x04, 0x00000003 },
674 { 0x419eb4, 4, 0x04, 0x00000000 },
675 { 0x419ec8, 1, 0x04, 0x06060618 },
676 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
677 { 0x419ed4, 1, 0x04, 0x011104f1 },
678 { 0x419edc, 1, 0x04, 0x00000000 },
679 { 0x419f00, 1, 0x04, 0x00000000 },
680 { 0x419f2c, 1, 0x04, 0x00000000 },
681 {}
682 };
683
684 const struct gf100_gr_init
685 gf100_gr_init_be_0[] = {
686 { 0x40880c, 1, 0x04, 0x00000000 },
687 { 0x408910, 9, 0x04, 0x00000000 },
688 { 0x408950, 1, 0x04, 0x00000000 },
689 { 0x408954, 1, 0x04, 0x0000ffff },
690 { 0x408984, 1, 0x04, 0x00000000 },
691 { 0x408988, 1, 0x04, 0x08040201 },
692 { 0x40898c, 1, 0x04, 0x80402010 },
693 {}
694 };
695
696 const struct gf100_gr_init
697 gf100_gr_init_fe_1[] = {
698 { 0x4040f0, 1, 0x04, 0x00000000 },
699 {}
700 };
701
702 const struct gf100_gr_init
703 gf100_gr_init_pe_1[] = {
704 { 0x419880, 1, 0x04, 0x00000002 },
705 {}
706 };
707
708 static const struct gf100_gr_pack
709 gf100_gr_pack_mmio[] = {
710 { gf100_gr_init_main_0 },
711 { gf100_gr_init_fe_0 },
712 { gf100_gr_init_pri_0 },
713 { gf100_gr_init_rstr2d_0 },
714 { gf100_gr_init_pd_0 },
715 { gf100_gr_init_ds_0 },
716 { gf100_gr_init_scc_0 },
717 { gf100_gr_init_prop_0 },
718 { gf100_gr_init_gpc_unk_0 },
719 { gf100_gr_init_setup_0 },
720 { gf100_gr_init_crstr_0 },
721 { gf100_gr_init_setup_1 },
722 { gf100_gr_init_zcull_0 },
723 { gf100_gr_init_gpm_0 },
724 { gf100_gr_init_gpc_unk_1 },
725 { gf100_gr_init_gcc_0 },
726 { gf100_gr_init_tpccs_0 },
727 { gf100_gr_init_tex_0 },
728 { gf100_gr_init_pe_0 },
729 { gf100_gr_init_l1c_0 },
730 { gf100_gr_init_wwdx_0 },
731 { gf100_gr_init_tpccs_1 },
732 { gf100_gr_init_mpc_0 },
733 { gf100_gr_init_sm_0 },
734 { gf100_gr_init_be_0 },
735 { gf100_gr_init_fe_1 },
736 { gf100_gr_init_pe_1 },
737 {}
738 };
739
740 /*******************************************************************************
741 * PGRAPH engine/subdev functions
742 ******************************************************************************/
743
744 static u32
gf100_gr_ctxsw_inst(struct nvkm_gr * gr)745 gf100_gr_ctxsw_inst(struct nvkm_gr *gr)
746 {
747 return nvkm_rd32(gr->engine.subdev.device, 0x409b00);
748 }
749
750 static int
gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr * gr,u32 mthd)751 gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd)
752 {
753 struct nvkm_device *device = gr->base.engine.subdev.device;
754
755 nvkm_wr32(device, 0x409804, 0xffffffff);
756 nvkm_wr32(device, 0x409800, 0x00000000);
757 nvkm_wr32(device, 0x409500, 0xffffffff);
758 nvkm_wr32(device, 0x409504, mthd);
759 nvkm_msec(device, 2000,
760 u32 stat = nvkm_rd32(device, 0x409804);
761 if (stat == 0x00000002)
762 return -EIO;
763 if (stat == 0x00000001)
764 return 0;
765 );
766
767 return -ETIMEDOUT;
768 }
769
770 static int
gf100_gr_fecs_start_ctxsw(struct nvkm_gr * base)771 gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base)
772 {
773 struct gf100_gr *gr = gf100_gr(base);
774 int ret = 0;
775
776 mutex_lock(&gr->fecs.mutex);
777 if (!--gr->fecs.disable) {
778 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39)))
779 gr->fecs.disable++;
780 }
781 mutex_unlock(&gr->fecs.mutex);
782 return ret;
783 }
784
785 static int
gf100_gr_fecs_stop_ctxsw(struct nvkm_gr * base)786 gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base)
787 {
788 struct gf100_gr *gr = gf100_gr(base);
789 int ret = 0;
790
791 mutex_lock(&gr->fecs.mutex);
792 if (!gr->fecs.disable++) {
793 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38)))
794 gr->fecs.disable--;
795 }
796 mutex_unlock(&gr->fecs.mutex);
797 return ret;
798 }
799
800 static int
gf100_gr_fecs_halt_pipeline(struct gf100_gr * gr)801 gf100_gr_fecs_halt_pipeline(struct gf100_gr *gr)
802 {
803 int ret = 0;
804
805 if (gr->firmware) {
806 mutex_lock(&gr->fecs.mutex);
807 ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x04);
808 mutex_unlock(&gr->fecs.mutex);
809 }
810
811 return ret;
812 }
813
814 int
gf100_gr_fecs_wfi_golden_save(struct gf100_gr * gr,u32 inst)815 gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst)
816 {
817 struct nvkm_device *device = gr->base.engine.subdev.device;
818
819 nvkm_mask(device, 0x409800, 0x00000003, 0x00000000);
820 nvkm_wr32(device, 0x409500, inst);
821 nvkm_wr32(device, 0x409504, 0x00000009);
822 nvkm_msec(device, 2000,
823 u32 stat = nvkm_rd32(device, 0x409800);
824 if (stat & 0x00000002)
825 return -EIO;
826 if (stat & 0x00000001)
827 return 0;
828 );
829
830 return -ETIMEDOUT;
831 }
832
833 int
gf100_gr_fecs_bind_pointer(struct gf100_gr * gr,u32 inst)834 gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst)
835 {
836 struct nvkm_device *device = gr->base.engine.subdev.device;
837
838 nvkm_mask(device, 0x409800, 0x00000030, 0x00000000);
839 nvkm_wr32(device, 0x409500, inst);
840 nvkm_wr32(device, 0x409504, 0x00000003);
841 nvkm_msec(device, 2000,
842 u32 stat = nvkm_rd32(device, 0x409800);
843 if (stat & 0x00000020)
844 return -EIO;
845 if (stat & 0x00000010)
846 return 0;
847 );
848
849 return -ETIMEDOUT;
850 }
851
852 static int
gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr * gr,u64 addr)853 gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr)
854 {
855 struct nvkm_device *device = gr->base.engine.subdev.device;
856
857 nvkm_wr32(device, 0x409810, addr >> 8);
858 nvkm_wr32(device, 0x409800, 0x00000000);
859 nvkm_wr32(device, 0x409500, 0x00000001);
860 nvkm_wr32(device, 0x409504, 0x00000032);
861 nvkm_msec(device, 2000,
862 if (nvkm_rd32(device, 0x409800) == 0x00000001)
863 return 0;
864 );
865
866 return -ETIMEDOUT;
867 }
868
869 static int
gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr * gr,u32 inst)870 gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst)
871 {
872 struct nvkm_device *device = gr->base.engine.subdev.device;
873
874 nvkm_wr32(device, 0x409810, inst);
875 nvkm_wr32(device, 0x409800, 0x00000000);
876 nvkm_wr32(device, 0x409500, 0x00000001);
877 nvkm_wr32(device, 0x409504, 0x00000031);
878 nvkm_msec(device, 2000,
879 if (nvkm_rd32(device, 0x409800) == 0x00000001)
880 return 0;
881 );
882
883 return -ETIMEDOUT;
884 }
885
886 static int
gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr * gr,u32 * psize)887 gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize)
888 {
889 struct nvkm_device *device = gr->base.engine.subdev.device;
890
891 nvkm_wr32(device, 0x409800, 0x00000000);
892 nvkm_wr32(device, 0x409500, 0x00000001);
893 nvkm_wr32(device, 0x409504, 0x00000030);
894 nvkm_msec(device, 2000,
895 if ((*psize = nvkm_rd32(device, 0x409800)))
896 return 0;
897 );
898
899 return -ETIMEDOUT;
900 }
901
902 static int
gf100_gr_fecs_elpg_bind(struct gf100_gr * gr)903 gf100_gr_fecs_elpg_bind(struct gf100_gr *gr)
904 {
905 u32 size;
906 int ret;
907
908 ret = gf100_gr_fecs_discover_reglist_image_size(gr, &size);
909 if (ret)
910 return ret;
911
912 /*XXX: We need to allocate + map the above into PMU's inst block,
913 * which which means we probably need a proper PMU before we
914 * even bother.
915 */
916
917 ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0);
918 if (ret)
919 return ret;
920
921 return gf100_gr_fecs_set_reglist_virtual_address(gr, 0);
922 }
923
924 static int
gf100_gr_fecs_discover_pm_image_size(struct gf100_gr * gr,u32 * psize)925 gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize)
926 {
927 struct nvkm_device *device = gr->base.engine.subdev.device;
928
929 nvkm_wr32(device, 0x409800, 0x00000000);
930 nvkm_wr32(device, 0x409500, 0x00000000);
931 nvkm_wr32(device, 0x409504, 0x00000025);
932 nvkm_msec(device, 2000,
933 if ((*psize = nvkm_rd32(device, 0x409800)))
934 return 0;
935 );
936
937 return -ETIMEDOUT;
938 }
939
940 static int
gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr * gr,u32 * psize)941 gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize)
942 {
943 struct nvkm_device *device = gr->base.engine.subdev.device;
944
945 nvkm_wr32(device, 0x409800, 0x00000000);
946 nvkm_wr32(device, 0x409500, 0x00000000);
947 nvkm_wr32(device, 0x409504, 0x00000016);
948 nvkm_msec(device, 2000,
949 if ((*psize = nvkm_rd32(device, 0x409800)))
950 return 0;
951 );
952
953 return -ETIMEDOUT;
954 }
955
956 static int
gf100_gr_fecs_discover_image_size(struct gf100_gr * gr,u32 * psize)957 gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize)
958 {
959 struct nvkm_device *device = gr->base.engine.subdev.device;
960
961 nvkm_wr32(device, 0x409800, 0x00000000);
962 nvkm_wr32(device, 0x409500, 0x00000000);
963 nvkm_wr32(device, 0x409504, 0x00000010);
964 nvkm_msec(device, 2000,
965 if ((*psize = nvkm_rd32(device, 0x409800)))
966 return 0;
967 );
968
969 return -ETIMEDOUT;
970 }
971
972 static void
gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr * gr,u32 timeout)973 gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout)
974 {
975 struct nvkm_device *device = gr->base.engine.subdev.device;
976
977 nvkm_wr32(device, 0x409800, 0x00000000);
978 nvkm_wr32(device, 0x409500, timeout);
979 nvkm_wr32(device, 0x409504, 0x00000021);
980 }
981
982 static bool
gf100_gr_chsw_load(struct nvkm_gr * base)983 gf100_gr_chsw_load(struct nvkm_gr *base)
984 {
985 struct gf100_gr *gr = gf100_gr(base);
986 if (!gr->firmware) {
987 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
988 if (trace & 0x00000040)
989 return true;
990 } else {
991 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
992 if (mthd & 0x00080000)
993 return true;
994 }
995 return false;
996 }
997
998 int
gf100_gr_rops(struct gf100_gr * gr)999 gf100_gr_rops(struct gf100_gr *gr)
1000 {
1001 struct nvkm_device *device = gr->base.engine.subdev.device;
1002 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
1003 }
1004
1005 void
gf100_gr_zbc_init(struct gf100_gr * gr)1006 gf100_gr_zbc_init(struct gf100_gr *gr)
1007 {
1008 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1009 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
1010 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
1011 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
1012 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1013 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
1014 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
1015 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
1016 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
1017 int index, c = ltc->zbc_color_min, d = ltc->zbc_depth_min, s = ltc->zbc_depth_min;
1018
1019 if (!gr->zbc_color[0].format) {
1020 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++;
1021 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++;
1022 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++;
1023 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++;
1024 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;
1025 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;
1026 if (gr->func->zbc->stencil_get) {
1027 gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++;
1028 gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++;
1029 gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++;
1030 }
1031 }
1032
1033 for (index = c; index <= ltc->zbc_color_max; index++)
1034 gr->func->zbc->clear_color(gr, index);
1035 for (index = d; index <= ltc->zbc_depth_max; index++)
1036 gr->func->zbc->clear_depth(gr, index);
1037
1038 if (gr->func->zbc->clear_stencil) {
1039 for (index = s; index <= ltc->zbc_depth_max; index++)
1040 gr->func->zbc->clear_stencil(gr, index);
1041 }
1042 }
1043
1044 /**
1045 * Wait until GR goes idle. GR is considered idle if it is disabled by the
1046 * MC (0x200) register, or GR is not busy and a context switch is not in
1047 * progress.
1048 */
1049 int
gf100_gr_wait_idle(struct gf100_gr * gr)1050 gf100_gr_wait_idle(struct gf100_gr *gr)
1051 {
1052 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1053 struct nvkm_device *device = subdev->device;
1054 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
1055 bool gr_enabled, ctxsw_active, gr_busy;
1056
1057 do {
1058 /*
1059 * required to make sure FIFO_ENGINE_STATUS (0x2640) is
1060 * up-to-date
1061 */
1062 nvkm_rd32(device, 0x400700);
1063
1064 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
1065 ctxsw_active = nvkm_fifo_ctxsw_in_progress(&gr->base.engine);
1066 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
1067
1068 if (!gr_enabled || (!gr_busy && !ctxsw_active))
1069 return 0;
1070 } while (time_before(jiffies, end_jiffies));
1071
1072 nvkm_error(subdev,
1073 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
1074 gr_enabled, ctxsw_active, gr_busy);
1075 return -EAGAIN;
1076 }
1077
1078 void
gf100_gr_mmio(struct gf100_gr * gr,const struct gf100_gr_pack * p)1079 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
1080 {
1081 struct nvkm_device *device = gr->base.engine.subdev.device;
1082 const struct gf100_gr_pack *pack;
1083 const struct gf100_gr_init *init;
1084
1085 pack_for_each_init(init, pack, p) {
1086 u32 next = init->addr + init->count * init->pitch;
1087 u32 addr = init->addr;
1088 while (addr < next) {
1089 nvkm_wr32(device, addr, init->data);
1090 addr += init->pitch;
1091 }
1092 }
1093 }
1094
1095 void
gf100_gr_icmd(struct gf100_gr * gr,const struct gf100_gr_pack * p)1096 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
1097 {
1098 struct nvkm_device *device = gr->base.engine.subdev.device;
1099 const struct gf100_gr_pack *pack;
1100 const struct gf100_gr_init *init;
1101 u64 data = 0;
1102
1103 nvkm_wr32(device, 0x400208, 0x80000000);
1104
1105 pack_for_each_init(init, pack, p) {
1106 u32 next = init->addr + init->count * init->pitch;
1107 u32 addr = init->addr;
1108
1109 if ((pack == p && init == p->init) || data != init->data) {
1110 nvkm_wr32(device, 0x400204, init->data);
1111 if (pack->type == 64)
1112 nvkm_wr32(device, 0x40020c, upper_32_bits(init->data));
1113 data = init->data;
1114 }
1115
1116 while (addr < next) {
1117 nvkm_wr32(device, 0x400200, addr);
1118 /**
1119 * Wait for GR to go idle after submitting a
1120 * GO_IDLE bundle
1121 */
1122 if ((addr & 0xffff) == 0xe100)
1123 gf100_gr_wait_idle(gr);
1124 nvkm_msec(device, 2000,
1125 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
1126 break;
1127 );
1128 addr += init->pitch;
1129 }
1130 }
1131
1132 nvkm_wr32(device, 0x400208, 0x00000000);
1133 }
1134
1135 void
gf100_gr_mthd(struct gf100_gr * gr,const struct gf100_gr_pack * p)1136 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
1137 {
1138 struct nvkm_device *device = gr->base.engine.subdev.device;
1139 const struct gf100_gr_pack *pack;
1140 const struct gf100_gr_init *init;
1141 u32 data = 0;
1142
1143 pack_for_each_init(init, pack, p) {
1144 u32 ctrl = 0x80000000 | pack->type;
1145 u32 next = init->addr + init->count * init->pitch;
1146 u32 addr = init->addr;
1147
1148 if ((pack == p && init == p->init) || data != init->data) {
1149 nvkm_wr32(device, 0x40448c, init->data);
1150 data = init->data;
1151 }
1152
1153 while (addr < next) {
1154 nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
1155 addr += init->pitch;
1156 }
1157 }
1158 }
1159
1160 u64
gf100_gr_units(struct nvkm_gr * base)1161 gf100_gr_units(struct nvkm_gr *base)
1162 {
1163 struct gf100_gr *gr = gf100_gr(base);
1164 u64 cfg;
1165
1166 cfg = (u32)gr->gpc_nr;
1167 cfg |= (u32)gr->tpc_total << 8;
1168 cfg |= (u64)gr->rop_nr << 32;
1169
1170 return cfg;
1171 }
1172
1173 static const struct nvkm_bitfield gf100_dispatch_error[] = {
1174 { 0x00000001, "INJECTED_BUNDLE_ERROR" },
1175 { 0x00000002, "CLASS_SUBCH_MISMATCH" },
1176 { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
1177 {}
1178 };
1179
1180 static const struct nvkm_bitfield gf100_m2mf_error[] = {
1181 { 0x00000001, "PUSH_TOO_MUCH_DATA" },
1182 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
1183 {}
1184 };
1185
1186 static const struct nvkm_bitfield gf100_unk6_error[] = {
1187 { 0x00000001, "TEMP_TOO_SMALL" },
1188 {}
1189 };
1190
1191 static const struct nvkm_bitfield gf100_ccache_error[] = {
1192 { 0x00000001, "INTR" },
1193 { 0x00000002, "LDCONST_OOB" },
1194 {}
1195 };
1196
1197 static const struct nvkm_bitfield gf100_macro_error[] = {
1198 { 0x00000001, "TOO_FEW_PARAMS" },
1199 { 0x00000002, "TOO_MANY_PARAMS" },
1200 { 0x00000004, "ILLEGAL_OPCODE" },
1201 { 0x00000008, "DOUBLE_BRANCH" },
1202 { 0x00000010, "WATCHDOG" },
1203 {}
1204 };
1205
1206 static const struct nvkm_bitfield gk104_sked_error[] = {
1207 { 0x00000040, "CTA_RESUME" },
1208 { 0x00000080, "CONSTANT_BUFFER_SIZE" },
1209 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
1210 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
1211 { 0x00000800, "WARP_CSTACK_SIZE" },
1212 { 0x00001000, "TOTAL_TEMP_SIZE" },
1213 { 0x00002000, "REGISTER_COUNT" },
1214 { 0x00040000, "TOTAL_THREADS" },
1215 { 0x00100000, "PROGRAM_OFFSET" },
1216 { 0x00200000, "SHARED_MEMORY_SIZE" },
1217 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
1218 { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
1219 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
1220 { 0x04000000, "TOTAL_REGISTER_COUNT" },
1221 {}
1222 };
1223
1224 static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
1225 { 0x00000002, "RT_PITCH_OVERRUN" },
1226 { 0x00000010, "RT_WIDTH_OVERRUN" },
1227 { 0x00000020, "RT_HEIGHT_OVERRUN" },
1228 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
1229 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
1230 { 0x00000400, "RT_LINEAR_MISMATCH" },
1231 {}
1232 };
1233
1234 static void
gf100_gr_trap_gpc_rop(struct gf100_gr * gr,int gpc)1235 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
1236 {
1237 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1238 struct nvkm_device *device = subdev->device;
1239 char error[128];
1240 u32 trap[4];
1241
1242 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
1243 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
1244 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
1245 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
1246
1247 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
1248
1249 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
1250 "format = %x, storage type = %x\n",
1251 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
1252 (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
1253 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1254 }
1255
1256 const struct nvkm_enum gf100_mp_warp_error[] = {
1257 { 0x01, "STACK_ERROR" },
1258 { 0x02, "API_STACK_ERROR" },
1259 { 0x03, "RET_EMPTY_STACK_ERROR" },
1260 { 0x04, "PC_WRAP" },
1261 { 0x05, "MISALIGNED_PC" },
1262 { 0x06, "PC_OVERFLOW" },
1263 { 0x07, "MISALIGNED_IMMC_ADDR" },
1264 { 0x08, "MISALIGNED_REG" },
1265 { 0x09, "ILLEGAL_INSTR_ENCODING" },
1266 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
1267 { 0x0b, "ILLEGAL_INSTR_PARAM" },
1268 { 0x0c, "INVALID_CONST_ADDR" },
1269 { 0x0d, "OOR_REG" },
1270 { 0x0e, "OOR_ADDR" },
1271 { 0x0f, "MISALIGNED_ADDR" },
1272 { 0x10, "INVALID_ADDR_SPACE" },
1273 { 0x11, "ILLEGAL_INSTR_PARAM2" },
1274 { 0x12, "INVALID_CONST_ADDR_LDC" },
1275 { 0x13, "GEOMETRY_SM_ERROR" },
1276 { 0x14, "DIVERGENT" },
1277 { 0x15, "WARP_EXIT" },
1278 {}
1279 };
1280
1281 const struct nvkm_bitfield gf100_mp_global_error[] = {
1282 { 0x00000001, "SM_TO_SM_FAULT" },
1283 { 0x00000002, "L1_ERROR" },
1284 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1285 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1286 { 0x00000010, "BPT_INT" },
1287 { 0x00000020, "BPT_PAUSE" },
1288 { 0x00000040, "SINGLE_STEP_COMPLETE" },
1289 { 0x20000000, "ECC_SEC_ERROR" },
1290 { 0x40000000, "ECC_DED_ERROR" },
1291 { 0x80000000, "TIMEOUT" },
1292 {}
1293 };
1294
1295 void
gf100_gr_trap_mp(struct gf100_gr * gr,int gpc,int tpc)1296 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
1297 {
1298 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1299 struct nvkm_device *device = subdev->device;
1300 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1301 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
1302 const struct nvkm_enum *warp;
1303 char glob[128];
1304
1305 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
1306 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
1307
1308 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
1309 "global %08x [%s] warp %04x [%s]\n",
1310 gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
1311
1312 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1313 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
1314 }
1315
1316 static void
gf100_gr_trap_tpc(struct gf100_gr * gr,int gpc,int tpc)1317 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
1318 {
1319 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1320 struct nvkm_device *device = subdev->device;
1321 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
1322
1323 if (stat & 0x00000001) {
1324 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
1325 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
1326 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
1327 stat &= ~0x00000001;
1328 }
1329
1330 if (stat & 0x00000002) {
1331 gr->func->trap_mp(gr, gpc, tpc);
1332 stat &= ~0x00000002;
1333 }
1334
1335 if (stat & 0x00000004) {
1336 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
1337 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
1338 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
1339 stat &= ~0x00000004;
1340 }
1341
1342 if (stat & 0x00000008) {
1343 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
1344 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
1345 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
1346 stat &= ~0x00000008;
1347 }
1348
1349 if (stat & 0x00000010) {
1350 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1351 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
1352 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1353 stat &= ~0x00000010;
1354 }
1355
1356 if (stat) {
1357 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
1358 }
1359 }
1360
1361 static void
gf100_gr_trap_gpc(struct gf100_gr * gr,int gpc)1362 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
1363 {
1364 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1365 struct nvkm_device *device = subdev->device;
1366 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
1367 int tpc;
1368
1369 if (stat & 0x00000001) {
1370 gf100_gr_trap_gpc_rop(gr, gpc);
1371 stat &= ~0x00000001;
1372 }
1373
1374 if (stat & 0x00000002) {
1375 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
1376 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
1377 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1378 stat &= ~0x00000002;
1379 }
1380
1381 if (stat & 0x00000004) {
1382 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
1383 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
1384 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1385 stat &= ~0x00000004;
1386 }
1387
1388 if (stat & 0x00000008) {
1389 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
1390 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
1391 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1392 stat &= ~0x00000009;
1393 }
1394
1395 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1396 u32 mask = 0x00010000 << tpc;
1397 if (stat & mask) {
1398 gf100_gr_trap_tpc(gr, gpc, tpc);
1399 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
1400 stat &= ~mask;
1401 }
1402 }
1403
1404 if (stat) {
1405 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
1406 }
1407 }
1408
1409 static void
gf100_gr_trap_intr(struct gf100_gr * gr)1410 gf100_gr_trap_intr(struct gf100_gr *gr)
1411 {
1412 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1413 struct nvkm_device *device = subdev->device;
1414 char error[128];
1415 u32 trap = nvkm_rd32(device, 0x400108);
1416 int rop, gpc;
1417
1418 if (trap & 0x00000001) {
1419 u32 stat = nvkm_rd32(device, 0x404000);
1420
1421 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
1422 stat & 0x3fffffff);
1423 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
1424 nvkm_wr32(device, 0x404000, 0xc0000000);
1425 nvkm_wr32(device, 0x400108, 0x00000001);
1426 trap &= ~0x00000001;
1427 }
1428
1429 if (trap & 0x00000002) {
1430 u32 stat = nvkm_rd32(device, 0x404600);
1431
1432 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
1433 stat & 0x3fffffff);
1434 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
1435
1436 nvkm_wr32(device, 0x404600, 0xc0000000);
1437 nvkm_wr32(device, 0x400108, 0x00000002);
1438 trap &= ~0x00000002;
1439 }
1440
1441 if (trap & 0x00000008) {
1442 u32 stat = nvkm_rd32(device, 0x408030);
1443
1444 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
1445 stat & 0x3fffffff);
1446 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
1447 nvkm_wr32(device, 0x408030, 0xc0000000);
1448 nvkm_wr32(device, 0x400108, 0x00000008);
1449 trap &= ~0x00000008;
1450 }
1451
1452 if (trap & 0x00000010) {
1453 u32 stat = nvkm_rd32(device, 0x405840);
1454 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
1455 stat, stat & 0xffffff, (stat >> 24) & 0x3f);
1456 nvkm_wr32(device, 0x405840, 0xc0000000);
1457 nvkm_wr32(device, 0x400108, 0x00000010);
1458 trap &= ~0x00000010;
1459 }
1460
1461 if (trap & 0x00000040) {
1462 u32 stat = nvkm_rd32(device, 0x40601c);
1463
1464 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
1465 stat & 0x3fffffff);
1466 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
1467
1468 nvkm_wr32(device, 0x40601c, 0xc0000000);
1469 nvkm_wr32(device, 0x400108, 0x00000040);
1470 trap &= ~0x00000040;
1471 }
1472
1473 if (trap & 0x00000080) {
1474 u32 stat = nvkm_rd32(device, 0x404490);
1475 u32 pc = nvkm_rd32(device, 0x404494);
1476 u32 op = nvkm_rd32(device, 0x40449c);
1477
1478 nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
1479 stat & 0x1fffffff);
1480 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
1481 stat, error, pc & 0x7ff,
1482 (pc & 0x10000000) ? "" : " (invalid)",
1483 op);
1484
1485 nvkm_wr32(device, 0x404490, 0xc0000000);
1486 nvkm_wr32(device, 0x400108, 0x00000080);
1487 trap &= ~0x00000080;
1488 }
1489
1490 if (trap & 0x00000100) {
1491 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
1492
1493 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
1494 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
1495
1496 if (stat)
1497 nvkm_wr32(device, 0x407020, 0x40000000);
1498 nvkm_wr32(device, 0x400108, 0x00000100);
1499 trap &= ~0x00000100;
1500 }
1501
1502 if (trap & 0x01000000) {
1503 u32 stat = nvkm_rd32(device, 0x400118);
1504 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
1505 u32 mask = 0x00000001 << gpc;
1506 if (stat & mask) {
1507 gf100_gr_trap_gpc(gr, gpc);
1508 nvkm_wr32(device, 0x400118, mask);
1509 stat &= ~mask;
1510 }
1511 }
1512 nvkm_wr32(device, 0x400108, 0x01000000);
1513 trap &= ~0x01000000;
1514 }
1515
1516 if (trap & 0x02000000) {
1517 for (rop = 0; rop < gr->rop_nr; rop++) {
1518 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1519 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1520 nvkm_error(subdev, "ROP%d %08x %08x\n",
1521 rop, statz, statc);
1522 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1523 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1524 }
1525 nvkm_wr32(device, 0x400108, 0x02000000);
1526 trap &= ~0x02000000;
1527 }
1528
1529 if (trap) {
1530 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
1531 nvkm_wr32(device, 0x400108, trap);
1532 }
1533 }
1534
1535 static void
gf100_gr_ctxctl_debug_unit(struct gf100_gr * gr,u32 base)1536 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
1537 {
1538 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1539 struct nvkm_device *device = subdev->device;
1540 nvkm_error(subdev, "%06x - done %08x\n", base,
1541 nvkm_rd32(device, base + 0x400));
1542 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1543 nvkm_rd32(device, base + 0x800),
1544 nvkm_rd32(device, base + 0x804),
1545 nvkm_rd32(device, base + 0x808),
1546 nvkm_rd32(device, base + 0x80c));
1547 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1548 nvkm_rd32(device, base + 0x810),
1549 nvkm_rd32(device, base + 0x814),
1550 nvkm_rd32(device, base + 0x818),
1551 nvkm_rd32(device, base + 0x81c));
1552 }
1553
1554 void
gf100_gr_ctxctl_debug(struct gf100_gr * gr)1555 gf100_gr_ctxctl_debug(struct gf100_gr *gr)
1556 {
1557 struct nvkm_device *device = gr->base.engine.subdev.device;
1558 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1559 u32 gpc;
1560
1561 gf100_gr_ctxctl_debug_unit(gr, 0x409000);
1562 for (gpc = 0; gpc < gpcnr; gpc++)
1563 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
1564 }
1565
1566 static void
gf100_gr_ctxctl_isr(struct gf100_gr * gr)1567 gf100_gr_ctxctl_isr(struct gf100_gr *gr)
1568 {
1569 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1570 struct nvkm_device *device = subdev->device;
1571 u32 stat = nvkm_rd32(device, 0x409c18);
1572
1573 if (!gr->firmware && (stat & 0x00000001)) {
1574 u32 code = nvkm_rd32(device, 0x409814);
1575 if (code == E_BAD_FWMTHD) {
1576 u32 class = nvkm_rd32(device, 0x409808);
1577 u32 addr = nvkm_rd32(device, 0x40980c);
1578 u32 subc = (addr & 0x00070000) >> 16;
1579 u32 mthd = (addr & 0x00003ffc);
1580 u32 data = nvkm_rd32(device, 0x409810);
1581
1582 nvkm_error(subdev, "FECS MTHD subc %d class %04x "
1583 "mthd %04x data %08x\n",
1584 subc, class, mthd, data);
1585 } else {
1586 nvkm_error(subdev, "FECS ucode error %d\n", code);
1587 }
1588 nvkm_wr32(device, 0x409c20, 0x00000001);
1589 stat &= ~0x00000001;
1590 }
1591
1592 if (!gr->firmware && (stat & 0x00080000)) {
1593 nvkm_error(subdev, "FECS watchdog timeout\n");
1594 gf100_gr_ctxctl_debug(gr);
1595 nvkm_wr32(device, 0x409c20, 0x00080000);
1596 stat &= ~0x00080000;
1597 }
1598
1599 if (stat) {
1600 nvkm_error(subdev, "FECS %08x\n", stat);
1601 gf100_gr_ctxctl_debug(gr);
1602 nvkm_wr32(device, 0x409c20, stat);
1603 }
1604 }
1605
1606 static irqreturn_t
gf100_gr_intr(struct nvkm_inth * inth)1607 gf100_gr_intr(struct nvkm_inth *inth)
1608 {
1609 struct gf100_gr *gr = container_of(inth, typeof(*gr), base.engine.subdev.inth);
1610 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1611 struct nvkm_device *device = subdev->device;
1612 struct nvkm_chan *chan;
1613 unsigned long flags;
1614 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1615 u32 stat = nvkm_rd32(device, 0x400100);
1616 u32 addr = nvkm_rd32(device, 0x400704);
1617 u32 mthd = (addr & 0x00003ffc);
1618 u32 subc = (addr & 0x00070000) >> 16;
1619 u32 data = nvkm_rd32(device, 0x400708);
1620 u32 code = nvkm_rd32(device, 0x400110);
1621 u32 class;
1622 const char *name = "unknown";
1623 int chid = -1;
1624
1625 chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags);
1626 if (chan) {
1627 name = chan->name;
1628 chid = chan->id;
1629 }
1630
1631 if (device->card_type < NV_E0 || subc < 4)
1632 class = nvkm_rd32(device, 0x404200 + (subc * 4));
1633 else
1634 class = 0x0000;
1635
1636 if (stat & 0x00000001) {
1637 /*
1638 * notifier interrupt, only needed for cyclestats
1639 * can be safely ignored
1640 */
1641 nvkm_wr32(device, 0x400100, 0x00000001);
1642 stat &= ~0x00000001;
1643 }
1644
1645 if (stat & 0x00000010) {
1646 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
1647 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
1648 "subc %d class %04x mthd %04x data %08x\n",
1649 chid, inst << 12, name, subc,
1650 class, mthd, data);
1651 }
1652 nvkm_wr32(device, 0x400100, 0x00000010);
1653 stat &= ~0x00000010;
1654 }
1655
1656 if (stat & 0x00000020) {
1657 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
1658 "subc %d class %04x mthd %04x data %08x\n",
1659 chid, inst << 12, name, subc, class, mthd, data);
1660 nvkm_wr32(device, 0x400100, 0x00000020);
1661 stat &= ~0x00000020;
1662 }
1663
1664 if (stat & 0x00100000) {
1665 const struct nvkm_enum *en =
1666 nvkm_enum_find(nv50_data_error_names, code);
1667 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
1668 "subc %d class %04x mthd %04x data %08x\n",
1669 code, en ? en->name : "", chid, inst << 12,
1670 name, subc, class, mthd, data);
1671 nvkm_wr32(device, 0x400100, 0x00100000);
1672 stat &= ~0x00100000;
1673 }
1674
1675 if (stat & 0x00200000) {
1676 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
1677 chid, inst << 12, name);
1678 gf100_gr_trap_intr(gr);
1679 nvkm_wr32(device, 0x400100, 0x00200000);
1680 stat &= ~0x00200000;
1681 }
1682
1683 if (stat & 0x00080000) {
1684 gf100_gr_ctxctl_isr(gr);
1685 nvkm_wr32(device, 0x400100, 0x00080000);
1686 stat &= ~0x00080000;
1687 }
1688
1689 if (stat) {
1690 nvkm_error(subdev, "intr %08x\n", stat);
1691 nvkm_wr32(device, 0x400100, stat);
1692 }
1693
1694 nvkm_wr32(device, 0x400500, 0x00010001);
1695 nvkm_chan_put(&chan, flags);
1696 return IRQ_HANDLED;
1697 }
1698
1699 static void
gf100_gr_init_fw(struct nvkm_falcon * falcon,struct nvkm_blob * code,struct nvkm_blob * data)1700 gf100_gr_init_fw(struct nvkm_falcon *falcon,
1701 struct nvkm_blob *code, struct nvkm_blob *data)
1702 {
1703 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
1704 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
1705 }
1706
1707 static void
gf100_gr_init_csdata(struct gf100_gr * gr,const struct gf100_gr_pack * pack,u32 falcon,u32 starstar,u32 base)1708 gf100_gr_init_csdata(struct gf100_gr *gr,
1709 const struct gf100_gr_pack *pack,
1710 u32 falcon, u32 starstar, u32 base)
1711 {
1712 struct nvkm_device *device = gr->base.engine.subdev.device;
1713 const struct gf100_gr_pack *iter;
1714 const struct gf100_gr_init *init;
1715 u32 addr = ~0, prev = ~0, xfer = 0;
1716 u32 star, temp;
1717
1718 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1719 star = nvkm_rd32(device, falcon + 0x01c4);
1720 temp = nvkm_rd32(device, falcon + 0x01c4);
1721 if (temp > star)
1722 star = temp;
1723 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1724
1725 pack_for_each_init(init, iter, pack) {
1726 u32 head = init->addr - base;
1727 u32 tail = head + init->count * init->pitch;
1728 while (head < tail) {
1729 if (head != prev + 4 || xfer >= 32) {
1730 if (xfer) {
1731 u32 data = ((--xfer << 26) | addr);
1732 nvkm_wr32(device, falcon + 0x01c4, data);
1733 star += 4;
1734 }
1735 addr = head;
1736 xfer = 0;
1737 }
1738 prev = head;
1739 xfer = xfer + 1;
1740 head = head + init->pitch;
1741 }
1742 }
1743
1744 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1745 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1746 nvkm_wr32(device, falcon + 0x01c4, star + 4);
1747 }
1748
1749 /* Initialize context from an external (secure or not) firmware */
1750 static int
gf100_gr_init_ctxctl_ext(struct gf100_gr * gr)1751 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
1752 {
1753 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1754 struct nvkm_device *device = subdev->device;
1755 u32 lsf_mask = 0;
1756 int ret;
1757
1758 /* load fuc microcode */
1759 nvkm_mc_unk260(device, 0);
1760
1761 /* securely-managed falcons must be reset using secure boot */
1762
1763 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) {
1764 gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst,
1765 &gr->fecs.data);
1766 } else {
1767 lsf_mask |= BIT(NVKM_ACR_LSF_FECS);
1768 }
1769
1770 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) {
1771 gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst,
1772 &gr->gpccs.data);
1773 } else {
1774 lsf_mask |= BIT(NVKM_ACR_LSF_GPCCS);
1775 }
1776
1777 if (lsf_mask) {
1778 ret = nvkm_acr_bootstrap_falcons(device, lsf_mask);
1779 if (ret)
1780 return ret;
1781 }
1782
1783 nvkm_mc_unk260(device, 1);
1784
1785 /* start both of them running */
1786 nvkm_wr32(device, 0x409800, 0x00000000);
1787 nvkm_wr32(device, 0x41a10c, 0x00000000);
1788 nvkm_wr32(device, 0x40910c, 0x00000000);
1789
1790 nvkm_falcon_start(&gr->gpccs.falcon);
1791 nvkm_falcon_start(&gr->fecs.falcon);
1792
1793 if (nvkm_msec(device, 2000,
1794 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1795 break;
1796 ) < 0)
1797 return -EBUSY;
1798
1799 gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff);
1800
1801 /* Determine how much memory is required to store main context image. */
1802 ret = gf100_gr_fecs_discover_image_size(gr, &gr->size);
1803 if (ret)
1804 return ret;
1805
1806 /* Determine how much memory is required to store ZCULL image. */
1807 ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull);
1808 if (ret)
1809 return ret;
1810
1811 /* Determine how much memory is required to store PerfMon image. */
1812 ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm);
1813 if (ret)
1814 return ret;
1815
1816 /*XXX: We (likely) require PMU support to even bother with this.
1817 *
1818 * Also, it seems like not all GPUs support ELPG. Traces I
1819 * have here show RM enabling it on Kepler/Turing, but none
1820 * of the GPUs between those. NVGPU decides this by PCIID.
1821 */
1822 if (0) {
1823 ret = gf100_gr_fecs_elpg_bind(gr);
1824 if (ret)
1825 return ret;
1826 }
1827
1828 return 0;
1829 }
1830
1831 static int
gf100_gr_init_ctxctl_int(struct gf100_gr * gr)1832 gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
1833 {
1834 const struct gf100_grctx_func *grctx = gr->func->grctx;
1835 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1836 struct nvkm_device *device = subdev->device;
1837
1838 if (!gr->func->fecs.ucode) {
1839 return -ENOSYS;
1840 }
1841
1842 /* load HUB microcode */
1843 nvkm_mc_unk260(device, 0);
1844 nvkm_falcon_load_dmem(&gr->fecs.falcon,
1845 gr->func->fecs.ucode->data.data, 0x0,
1846 gr->func->fecs.ucode->data.size, 0);
1847 nvkm_falcon_load_imem(&gr->fecs.falcon,
1848 gr->func->fecs.ucode->code.data, 0x0,
1849 gr->func->fecs.ucode->code.size, 0, 0, false);
1850
1851 /* load GPC microcode */
1852 nvkm_falcon_load_dmem(&gr->gpccs.falcon,
1853 gr->func->gpccs.ucode->data.data, 0x0,
1854 gr->func->gpccs.ucode->data.size, 0);
1855 nvkm_falcon_load_imem(&gr->gpccs.falcon,
1856 gr->func->gpccs.ucode->code.data, 0x0,
1857 gr->func->gpccs.ucode->code.size, 0, 0, false);
1858 nvkm_mc_unk260(device, 1);
1859
1860 /* load register lists */
1861 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
1862 gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000);
1863 gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000);
1864 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
1865 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
1866
1867 /* start HUB ucode running, it'll init the GPCs */
1868 nvkm_wr32(device, 0x40910c, 0x00000000);
1869 nvkm_wr32(device, 0x409100, 0x00000002);
1870 if (nvkm_msec(device, 2000,
1871 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1872 break;
1873 ) < 0) {
1874 gf100_gr_ctxctl_debug(gr);
1875 return -EBUSY;
1876 }
1877
1878 gr->size = nvkm_rd32(device, 0x409804);
1879 return 0;
1880 }
1881
1882 int
gf100_gr_init_ctxctl(struct gf100_gr * gr)1883 gf100_gr_init_ctxctl(struct gf100_gr *gr)
1884 {
1885 int ret;
1886
1887 if (gr->firmware)
1888 ret = gf100_gr_init_ctxctl_ext(gr);
1889 else
1890 ret = gf100_gr_init_ctxctl_int(gr);
1891
1892 return ret;
1893 }
1894
1895 int
gf100_gr_oneinit_sm_id(struct gf100_gr * gr)1896 gf100_gr_oneinit_sm_id(struct gf100_gr *gr)
1897 {
1898 int tpc, gpc;
1899
1900 for (tpc = 0; tpc < gr->tpc_max; tpc++) {
1901 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1902 if (tpc < gr->tpc_nr[gpc]) {
1903 gr->sm[gr->sm_nr].gpc = gpc;
1904 gr->sm[gr->sm_nr].tpc = tpc;
1905 gr->sm_nr++;
1906 }
1907 }
1908 }
1909
1910 return 0;
1911 }
1912
1913 void
gf100_gr_oneinit_tiles(struct gf100_gr * gr)1914 gf100_gr_oneinit_tiles(struct gf100_gr *gr)
1915 {
1916 static const u8 primes[] = {
1917 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61
1918 };
1919 int init_frac[GPC_MAX], init_err[GPC_MAX], run_err[GPC_MAX], i, j;
1920 u32 mul_factor, comm_denom;
1921 u8 gpc_map[GPC_MAX];
1922 bool sorted;
1923
1924 switch (gr->tpc_total) {
1925 case 15: gr->screen_tile_row_offset = 0x06; break;
1926 case 14: gr->screen_tile_row_offset = 0x05; break;
1927 case 13: gr->screen_tile_row_offset = 0x02; break;
1928 case 11: gr->screen_tile_row_offset = 0x07; break;
1929 case 10: gr->screen_tile_row_offset = 0x06; break;
1930 case 7:
1931 case 5: gr->screen_tile_row_offset = 0x01; break;
1932 case 3: gr->screen_tile_row_offset = 0x02; break;
1933 case 2:
1934 case 1: gr->screen_tile_row_offset = 0x01; break;
1935 default: gr->screen_tile_row_offset = 0x03;
1936 for (i = 0; i < ARRAY_SIZE(primes); i++) {
1937 if (gr->tpc_total % primes[i]) {
1938 gr->screen_tile_row_offset = primes[i];
1939 break;
1940 }
1941 }
1942 break;
1943 }
1944
1945 /* Sort GPCs by TPC count, highest-to-lowest. */
1946 for (i = 0; i < gr->gpc_nr; i++)
1947 gpc_map[i] = i;
1948 sorted = false;
1949
1950 while (!sorted) {
1951 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) {
1952 if (gr->tpc_nr[gpc_map[i + 1]] >
1953 gr->tpc_nr[gpc_map[i + 0]]) {
1954 u8 swap = gpc_map[i];
1955 gpc_map[i + 0] = gpc_map[i + 1];
1956 gpc_map[i + 1] = swap;
1957 sorted = false;
1958 }
1959 }
1960 }
1961
1962 /* Determine tile->GPC mapping */
1963 mul_factor = gr->gpc_nr * gr->tpc_max;
1964 if (mul_factor & 1)
1965 mul_factor = 2;
1966 else
1967 mul_factor = 1;
1968
1969 comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor;
1970
1971 for (i = 0; i < gr->gpc_nr; i++) {
1972 init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor;
1973 init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2;
1974 run_err[i] = init_frac[i] + init_err[i];
1975 }
1976
1977 for (i = 0; i < gr->tpc_total;) {
1978 for (j = 0; j < gr->gpc_nr; j++) {
1979 if ((run_err[j] * 2) >= comm_denom) {
1980 gr->tile[i++] = gpc_map[j];
1981 run_err[j] += init_frac[j] - comm_denom;
1982 } else {
1983 run_err[j] += init_frac[j];
1984 }
1985 }
1986 }
1987 }
1988
1989 static int
gf100_gr_oneinit(struct nvkm_gr * base)1990 gf100_gr_oneinit(struct nvkm_gr *base)
1991 {
1992 struct gf100_gr *gr = gf100_gr(base);
1993 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1994 struct nvkm_device *device = subdev->device;
1995 struct nvkm_intr *intr = &device->mc->intr;
1996 enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;
1997 int ret, i, j;
1998
1999 if (gr->func->oneinit_intr)
2000 intr = gr->func->oneinit_intr(gr, &intr_type);
2001
2002 ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,
2003 gf100_gr_intr, &gr->base.engine.subdev.inth);
2004 if (ret)
2005 return ret;
2006
2007 nvkm_pmu_pgob(device->pmu, false);
2008
2009 gr->rop_nr = gr->func->rops(gr);
2010 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
2011 for (i = 0; i < gr->gpc_nr; i++) {
2012 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
2013 gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]);
2014 gr->tpc_total += gr->tpc_nr[i];
2015 for (j = 0; j < gr->func->ppc_nr; j++) {
2016 gr->ppc_tpc_mask[i][j] =
2017 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
2018 if (gr->ppc_tpc_mask[i][j] == 0)
2019 continue;
2020
2021 gr->ppc_nr[i]++;
2022
2023 gr->ppc_mask[i] |= (1 << j);
2024 gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]);
2025 if (gr->ppc_tpc_min == 0 ||
2026 gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j])
2027 gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j];
2028 if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])
2029 gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];
2030 }
2031
2032 gr->ppc_total += gr->ppc_nr[i];
2033 }
2034
2035 /* Allocate global context buffers. */
2036 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->pagepool_size,
2037 0x100, false, &gr->pagepool);
2038 if (ret)
2039 return ret;
2040
2041 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->bundle_size,
2042 0x100, false, &gr->bundle_cb);
2043 if (ret)
2044 return ret;
2045
2046 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->attrib_cb_size(gr),
2047 0x1000, false, &gr->attrib_cb);
2048 if (ret)
2049 return ret;
2050
2051 if (gr->func->grctx->unknown_size) {
2052 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size,
2053 0x100, false, &gr->unknown);
2054 if (ret)
2055 return ret;
2056 }
2057
2058 memset(gr->tile, 0xff, sizeof(gr->tile));
2059 gr->func->oneinit_tiles(gr);
2060
2061 return gr->func->oneinit_sm_id(gr);
2062 }
2063
2064 static int
gf100_gr_init_(struct nvkm_gr * base)2065 gf100_gr_init_(struct nvkm_gr *base)
2066 {
2067 struct gf100_gr *gr = gf100_gr(base);
2068 struct nvkm_subdev *subdev = &base->engine.subdev;
2069 struct nvkm_device *device = subdev->device;
2070 bool reset = device->chipset == 0x137 || device->chipset == 0x138;
2071 int ret;
2072
2073 /* On certain GP107/GP108 boards, we trigger a weird issue where
2074 * GR will stop responding to PRI accesses after we've asked the
2075 * SEC2 RTOS to boot the GR falcons. This happens with far more
2076 * frequency when cold-booting a board (ie. returning from D3).
2077 *
2078 * The root cause for this is not known and has proven difficult
2079 * to isolate, with many avenues being dead-ends.
2080 *
2081 * A workaround was discovered by Karol, whereby putting GR into
2082 * reset for an extended period right before initialisation
2083 * prevents the problem from occuring.
2084 *
2085 * XXX: As RM does not require any such workaround, this is more
2086 * of a hack than a true fix.
2087 */
2088 reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset);
2089 if (reset) {
2090 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
2091 nvkm_rd32(device, 0x000200);
2092 msleep(50);
2093 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
2094 nvkm_rd32(device, 0x000200);
2095 }
2096
2097 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
2098
2099 ret = nvkm_falcon_get(&gr->fecs.falcon, subdev);
2100 if (ret)
2101 return ret;
2102
2103 ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev);
2104 if (ret)
2105 return ret;
2106
2107 ret = gr->func->init(gr);
2108 if (ret)
2109 return ret;
2110
2111 nvkm_inth_allow(&subdev->inth);
2112 return 0;
2113 }
2114
2115 static int
gf100_gr_fini(struct nvkm_gr * base,bool suspend)2116 gf100_gr_fini(struct nvkm_gr *base, bool suspend)
2117 {
2118 struct gf100_gr *gr = gf100_gr(base);
2119 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
2120
2121 nvkm_inth_block(&subdev->inth);
2122
2123 nvkm_falcon_put(&gr->gpccs.falcon, subdev);
2124 nvkm_falcon_put(&gr->fecs.falcon, subdev);
2125 return 0;
2126 }
2127
2128 static void *
gf100_gr_dtor(struct nvkm_gr * base)2129 gf100_gr_dtor(struct nvkm_gr *base)
2130 {
2131 struct gf100_gr *gr = gf100_gr(base);
2132
2133 kfree(gr->data);
2134
2135 nvkm_memory_unref(&gr->unknown);
2136 nvkm_memory_unref(&gr->attrib_cb);
2137 nvkm_memory_unref(&gr->bundle_cb);
2138 nvkm_memory_unref(&gr->pagepool);
2139
2140 nvkm_falcon_dtor(&gr->gpccs.falcon);
2141 nvkm_falcon_dtor(&gr->fecs.falcon);
2142
2143 nvkm_blob_dtor(&gr->fecs.inst);
2144 nvkm_blob_dtor(&gr->fecs.data);
2145 nvkm_blob_dtor(&gr->gpccs.inst);
2146 nvkm_blob_dtor(&gr->gpccs.data);
2147
2148 vfree(gr->bundle64);
2149 vfree(gr->bundle_veid);
2150 vfree(gr->bundle);
2151 vfree(gr->method);
2152 vfree(gr->sw_ctx);
2153 vfree(gr->sw_nonctx);
2154 vfree(gr->sw_nonctx1);
2155 vfree(gr->sw_nonctx2);
2156 vfree(gr->sw_nonctx3);
2157 vfree(gr->sw_nonctx4);
2158
2159 return gr;
2160 }
2161
2162 static const struct nvkm_falcon_func
2163 gf100_gr_flcn = {
2164 .load_imem = nvkm_falcon_v1_load_imem,
2165 .load_dmem = nvkm_falcon_v1_load_dmem,
2166 .start = nvkm_falcon_v1_start,
2167 };
2168
2169 void
gf100_gr_init_num_tpc_per_gpc(struct gf100_gr * gr,bool pd,bool ds)2170 gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds)
2171 {
2172 struct nvkm_device *device = gr->base.engine.subdev.device;
2173 int gpc, i, j;
2174 u32 data;
2175
2176 for (gpc = 0, i = 0; i < 4; i++) {
2177 for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++)
2178 data |= gr->tpc_nr[gpc] << (j * 4);
2179 if (pd)
2180 nvkm_wr32(device, 0x406028 + (i * 4), data);
2181 if (ds)
2182 nvkm_wr32(device, 0x405870 + (i * 4), data);
2183 }
2184 }
2185
2186 void
gf100_gr_init_400054(struct gf100_gr * gr)2187 gf100_gr_init_400054(struct gf100_gr *gr)
2188 {
2189 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
2190 }
2191
2192 void
gf100_gr_init_exception2(struct gf100_gr * gr)2193 gf100_gr_init_exception2(struct gf100_gr *gr)
2194 {
2195 struct nvkm_device *device = gr->base.engine.subdev.device;
2196
2197 nvkm_wr32(device, 0x40011c, 0xffffffff);
2198 nvkm_wr32(device, 0x400134, 0xffffffff);
2199 }
2200
2201 void
gf100_gr_init_rop_exceptions(struct gf100_gr * gr)2202 gf100_gr_init_rop_exceptions(struct gf100_gr *gr)
2203 {
2204 struct nvkm_device *device = gr->base.engine.subdev.device;
2205 int rop;
2206
2207 for (rop = 0; rop < gr->rop_nr; rop++) {
2208 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
2209 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
2210 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2211 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
2212 }
2213 }
2214
2215 void
gf100_gr_init_shader_exceptions(struct gf100_gr * gr,int gpc,int tpc)2216 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
2217 {
2218 struct nvkm_device *device = gr->base.engine.subdev.device;
2219 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2220 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
2221 }
2222
2223 void
gf100_gr_init_tex_hww_esr(struct gf100_gr * gr,int gpc,int tpc)2224 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc)
2225 {
2226 struct nvkm_device *device = gr->base.engine.subdev.device;
2227 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2228 }
2229
2230 void
gf100_gr_init_419eb4(struct gf100_gr * gr)2231 gf100_gr_init_419eb4(struct gf100_gr *gr)
2232 {
2233 struct nvkm_device *device = gr->base.engine.subdev.device;
2234 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
2235 }
2236
2237 void
gf100_gr_init_419cc0(struct gf100_gr * gr)2238 gf100_gr_init_419cc0(struct gf100_gr *gr)
2239 {
2240 struct nvkm_device *device = gr->base.engine.subdev.device;
2241 int gpc, tpc;
2242
2243 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
2244
2245 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2246 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++)
2247 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2248 }
2249 }
2250
2251 void
gf100_gr_init_40601c(struct gf100_gr * gr)2252 gf100_gr_init_40601c(struct gf100_gr *gr)
2253 {
2254 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
2255 }
2256
2257 void
gf100_gr_init_fecs_exceptions(struct gf100_gr * gr)2258 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
2259 {
2260 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001;
2261 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
2262 }
2263
2264 void
gf100_gr_init_gpc_mmu(struct gf100_gr * gr)2265 gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
2266 {
2267 struct nvkm_device *device = gr->base.engine.subdev.device;
2268 struct nvkm_fb *fb = device->fb;
2269
2270 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
2271 nvkm_wr32(device, 0x4188a4, 0x03000000);
2272 nvkm_wr32(device, 0x418888, 0x00000000);
2273 nvkm_wr32(device, 0x41888c, 0x00000000);
2274 nvkm_wr32(device, 0x418890, 0x00000000);
2275 nvkm_wr32(device, 0x418894, 0x00000000);
2276 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
2277 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
2278 }
2279
2280 void
gf100_gr_init_num_active_ltcs(struct gf100_gr * gr)2281 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr)
2282 {
2283 struct nvkm_device *device = gr->base.engine.subdev.device;
2284 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
2285 }
2286
2287 void
gf100_gr_init_zcull(struct gf100_gr * gr)2288 gf100_gr_init_zcull(struct gf100_gr *gr)
2289 {
2290 struct nvkm_device *device = gr->base.engine.subdev.device;
2291 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
2292 const u8 tile_nr = ALIGN(gr->tpc_total, 32);
2293 u8 bank[GPC_MAX] = {}, gpc, i, j;
2294 u32 data;
2295
2296 for (i = 0; i < tile_nr; i += 8) {
2297 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
2298 data |= bank[gr->tile[i + j]] << (j * 4);
2299 bank[gr->tile[i + j]]++;
2300 }
2301 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
2302 }
2303
2304 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2305 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
2306 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
2307 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
2308 gr->tpc_total);
2309 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
2310 }
2311
2312 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
2313 }
2314
2315 void
gf100_gr_init_vsc_stream_master(struct gf100_gr * gr)2316 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr)
2317 {
2318 struct nvkm_device *device = gr->base.engine.subdev.device;
2319 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
2320 }
2321
2322 static int
gf100_gr_reset(struct nvkm_gr * base)2323 gf100_gr_reset(struct nvkm_gr *base)
2324 {
2325 struct nvkm_subdev *subdev = &base->engine.subdev;
2326 struct nvkm_device *device = subdev->device;
2327 struct gf100_gr *gr = gf100_gr(base);
2328
2329 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000);
2330
2331 WARN_ON(gf100_gr_fecs_halt_pipeline(gr));
2332
2333 subdev->func->fini(subdev, false);
2334 nvkm_mc_disable(device, subdev->type, subdev->inst);
2335 if (gr->func->gpccs.reset)
2336 gr->func->gpccs.reset(gr);
2337
2338 nvkm_mc_enable(device, subdev->type, subdev->inst);
2339 return subdev->func->init(subdev);
2340 }
2341
2342 int
gf100_gr_init(struct gf100_gr * gr)2343 gf100_gr_init(struct gf100_gr *gr)
2344 {
2345 struct nvkm_device *device = gr->base.engine.subdev.device;
2346 int gpc, tpc;
2347
2348 nvkm_mask(device, 0x400500, 0x00010001, 0x00000000);
2349
2350 gr->func->init_gpc_mmu(gr);
2351
2352 if (gr->sw_nonctx1) {
2353 gf100_gr_mmio(gr, gr->sw_nonctx1);
2354 gf100_gr_mmio(gr, gr->sw_nonctx2);
2355 gf100_gr_mmio(gr, gr->sw_nonctx3);
2356 gf100_gr_mmio(gr, gr->sw_nonctx4);
2357 } else
2358 if (gr->sw_nonctx) {
2359 gf100_gr_mmio(gr, gr->sw_nonctx);
2360 } else {
2361 gf100_gr_mmio(gr, gr->func->mmio);
2362 }
2363
2364 gf100_gr_wait_idle(gr);
2365
2366 if (gr->func->init_r405a14)
2367 gr->func->init_r405a14(gr);
2368
2369 if (gr->func->clkgate_pack)
2370 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack);
2371
2372 if (gr->func->init_bios)
2373 gr->func->init_bios(gr);
2374
2375 gr->func->init_vsc_stream_master(gr);
2376 gr->func->init_zcull(gr);
2377 gr->func->init_num_active_ltcs(gr);
2378 if (gr->func->init_rop_active_fbps)
2379 gr->func->init_rop_active_fbps(gr);
2380 if (gr->func->init_bios_2)
2381 gr->func->init_bios_2(gr);
2382 if (gr->func->init_swdx_pes_mask)
2383 gr->func->init_swdx_pes_mask(gr);
2384 if (gr->func->init_fs)
2385 gr->func->init_fs(gr);
2386
2387 nvkm_wr32(device, 0x400500, 0x00010001);
2388
2389 nvkm_wr32(device, 0x400100, 0xffffffff);
2390 nvkm_wr32(device, 0x40013c, 0xffffffff);
2391 nvkm_wr32(device, 0x400124, 0x00000002);
2392
2393 gr->func->init_fecs_exceptions(gr);
2394
2395 if (gr->func->init_40a790)
2396 gr->func->init_40a790(gr);
2397
2398 if (gr->func->init_ds_hww_esr_2)
2399 gr->func->init_ds_hww_esr_2(gr);
2400
2401 nvkm_wr32(device, 0x404000, 0xc0000000);
2402 nvkm_wr32(device, 0x404600, 0xc0000000);
2403 nvkm_wr32(device, 0x408030, 0xc0000000);
2404
2405 if (gr->func->init_40601c)
2406 gr->func->init_40601c(gr);
2407
2408 nvkm_wr32(device, 0x406018, 0xc0000000);
2409 nvkm_wr32(device, 0x404490, 0xc0000000);
2410
2411 if (gr->func->init_sked_hww_esr)
2412 gr->func->init_sked_hww_esr(gr);
2413
2414 nvkm_wr32(device, 0x405840, 0xc0000000);
2415 nvkm_wr32(device, 0x405844, 0x00ffffff);
2416
2417 if (gr->func->init_419cc0)
2418 gr->func->init_419cc0(gr);
2419 if (gr->func->init_419eb4)
2420 gr->func->init_419eb4(gr);
2421 if (gr->func->init_419c9c)
2422 gr->func->init_419c9c(gr);
2423
2424 if (gr->func->init_ppc_exceptions)
2425 gr->func->init_ppc_exceptions(gr);
2426
2427 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2428 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
2429 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
2430 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
2431 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
2432 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
2433 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2434 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2435 if (gr->func->init_tex_hww_esr)
2436 gr->func->init_tex_hww_esr(gr, gpc, tpc);
2437 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2438 if (gr->func->init_504430)
2439 gr->func->init_504430(gr, gpc, tpc);
2440 gr->func->init_shader_exceptions(gr, gpc, tpc);
2441 }
2442 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2443 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
2444 }
2445
2446 gr->func->init_rop_exceptions(gr);
2447
2448 nvkm_wr32(device, 0x400108, 0xffffffff);
2449 nvkm_wr32(device, 0x400138, 0xffffffff);
2450 nvkm_wr32(device, 0x400118, 0xffffffff);
2451 nvkm_wr32(device, 0x400130, 0xffffffff);
2452 if (gr->func->init_exception2)
2453 gr->func->init_exception2(gr);
2454
2455 if (gr->func->init_400054)
2456 gr->func->init_400054(gr);
2457
2458 gf100_gr_zbc_init(gr);
2459
2460 if (gr->func->init_4188a4)
2461 gr->func->init_4188a4(gr);
2462
2463 return gf100_gr_init_ctxctl(gr);
2464 }
2465
2466 void
gf100_gr_fecs_reset(struct gf100_gr * gr)2467 gf100_gr_fecs_reset(struct gf100_gr *gr)
2468 {
2469 struct nvkm_device *device = gr->base.engine.subdev.device;
2470
2471 nvkm_wr32(device, 0x409614, 0x00000070);
2472 nvkm_usec(device, 10, NVKM_DELAY);
2473 nvkm_mask(device, 0x409614, 0x00000700, 0x00000700);
2474 nvkm_usec(device, 10, NVKM_DELAY);
2475 nvkm_rd32(device, 0x409614);
2476 }
2477
2478 #include "fuc/hubgf100.fuc3.h"
2479
2480 struct gf100_gr_ucode
2481 gf100_gr_fecs_ucode = {
2482 .code.data = gf100_grhub_code,
2483 .code.size = sizeof(gf100_grhub_code),
2484 .data.data = gf100_grhub_data,
2485 .data.size = sizeof(gf100_grhub_data),
2486 };
2487
2488 #include "fuc/gpcgf100.fuc3.h"
2489
2490 struct gf100_gr_ucode
2491 gf100_gr_gpccs_ucode = {
2492 .code.data = gf100_grgpc_code,
2493 .code.size = sizeof(gf100_grgpc_code),
2494 .data.data = gf100_grgpc_data,
2495 .data.size = sizeof(gf100_grgpc_data),
2496 };
2497
2498 static int
gf100_gr_nonstall(struct nvkm_gr * base)2499 gf100_gr_nonstall(struct nvkm_gr *base)
2500 {
2501 struct gf100_gr *gr = gf100_gr(base);
2502
2503 if (gr->func->nonstall)
2504 return gr->func->nonstall(gr);
2505
2506 return -EINVAL;
2507 }
2508
2509 static const struct nvkm_gr_func
2510 gf100_gr_ = {
2511 .dtor = gf100_gr_dtor,
2512 .oneinit = gf100_gr_oneinit,
2513 .init = gf100_gr_init_,
2514 .fini = gf100_gr_fini,
2515 .nonstall = gf100_gr_nonstall,
2516 .reset = gf100_gr_reset,
2517 .units = gf100_gr_units,
2518 .chan_new = gf100_gr_chan_new,
2519 .object_get = gf100_gr_object_get,
2520 .chsw_load = gf100_gr_chsw_load,
2521 .ctxsw.pause = gf100_gr_fecs_stop_ctxsw,
2522 .ctxsw.resume = gf100_gr_fecs_start_ctxsw,
2523 .ctxsw.inst = gf100_gr_ctxsw_inst,
2524 };
2525
2526 static const struct gf100_gr_func
2527 gf100_gr = {
2528 .oneinit_tiles = gf100_gr_oneinit_tiles,
2529 .oneinit_sm_id = gf100_gr_oneinit_sm_id,
2530 .init = gf100_gr_init,
2531 .init_gpc_mmu = gf100_gr_init_gpc_mmu,
2532 .init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
2533 .init_zcull = gf100_gr_init_zcull,
2534 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
2535 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
2536 .init_40601c = gf100_gr_init_40601c,
2537 .init_419cc0 = gf100_gr_init_419cc0,
2538 .init_419eb4 = gf100_gr_init_419eb4,
2539 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
2540 .init_shader_exceptions = gf100_gr_init_shader_exceptions,
2541 .init_rop_exceptions = gf100_gr_init_rop_exceptions,
2542 .init_exception2 = gf100_gr_init_exception2,
2543 .init_400054 = gf100_gr_init_400054,
2544 .trap_mp = gf100_gr_trap_mp,
2545 .mmio = gf100_gr_pack_mmio,
2546 .fecs.ucode = &gf100_gr_fecs_ucode,
2547 .fecs.reset = gf100_gr_fecs_reset,
2548 .gpccs.ucode = &gf100_gr_gpccs_ucode,
2549 .rops = gf100_gr_rops,
2550 .grctx = &gf100_grctx,
2551 .zbc = &gf100_gr_zbc,
2552 .sclass = {
2553 { -1, -1, FERMI_TWOD_A },
2554 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2555 { -1, -1, FERMI_A, &gf100_fermi },
2556 { -1, -1, FERMI_COMPUTE_A },
2557 {}
2558 }
2559 };
2560
2561 int
gf100_gr_nofw(struct gf100_gr * gr,int ver,const struct gf100_gr_fwif * fwif)2562 gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
2563 {
2564 gr->firmware = false;
2565 return 0;
2566 }
2567
2568 static int
gf100_gr_load_fw(struct gf100_gr * gr,const char * name,struct nvkm_blob * blob)2569 gf100_gr_load_fw(struct gf100_gr *gr, const char *name,
2570 struct nvkm_blob *blob)
2571 {
2572 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
2573 struct nvkm_device *device = subdev->device;
2574 const struct firmware *fw;
2575 char f[32];
2576 int ret;
2577
2578 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name);
2579 ret = request_firmware(&fw, f, device->dev);
2580 if (ret) {
2581 snprintf(f, sizeof(f), "nouveau/%s", name);
2582 ret = request_firmware(&fw, f, device->dev);
2583 if (ret) {
2584 nvkm_error(subdev, "failed to load %s\n", name);
2585 return ret;
2586 }
2587 }
2588
2589 blob->size = fw->size;
2590 blob->data = kmemdup(fw->data, blob->size, GFP_KERNEL);
2591 release_firmware(fw);
2592 return (blob->data != NULL) ? 0 : -ENOMEM;
2593 }
2594
2595 int
gf100_gr_load(struct gf100_gr * gr,int ver,const struct gf100_gr_fwif * fwif)2596 gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
2597 {
2598 struct nvkm_device *device = gr->base.engine.subdev.device;
2599
2600 if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false))
2601 return -EINVAL;
2602
2603 if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) ||
2604 gf100_gr_load_fw(gr, "fuc409d", &gr->fecs.data) ||
2605 gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) ||
2606 gf100_gr_load_fw(gr, "fuc41ad", &gr->gpccs.data))
2607 return -ENOENT;
2608
2609 gr->firmware = true;
2610 return 0;
2611 }
2612
2613 static const struct gf100_gr_fwif
2614 gf100_gr_fwif[] = {
2615 { -1, gf100_gr_load, &gf100_gr },
2616 { -1, gf100_gr_nofw, &gf100_gr },
2617 {}
2618 };
2619
2620 int
gf100_gr_new_(const struct gf100_gr_fwif * fwif,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_gr ** pgr)2621 gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device,
2622 enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
2623 {
2624 struct gf100_gr *gr;
2625 int ret;
2626
2627 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
2628 return -ENOMEM;
2629 *pgr = &gr->base;
2630
2631 ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base);
2632 if (ret)
2633 return ret;
2634
2635 fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr);
2636 if (IS_ERR(fwif))
2637 return PTR_ERR(fwif);
2638
2639 gr->func = fwif->func;
2640
2641 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev,
2642 "fecs", 0x409000, &gr->fecs.falcon);
2643 if (ret)
2644 return ret;
2645
2646 mutex_init(&gr->fecs.mutex);
2647
2648 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev,
2649 "gpccs", 0x41a000, &gr->gpccs.falcon);
2650 if (ret)
2651 return ret;
2652
2653 return 0;
2654 }
2655
2656 int
gf100_gr_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_gr ** pgr)2657 gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
2658 {
2659 return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr);
2660 }
2661