1 /*
2 * Coherent Processing System emulation.
3 *
4 * Copyright (c) 2016 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/module.h"
23 #include "hw/mips/cps.h"
24 #include "hw/mips/mips.h"
25 #include "hw/qdev-clock.h"
26 #include "hw/qdev-properties.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/reset.h"
29
get_cps_irq(MIPSCPSState * s,int pin_number)30 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
31 {
32 assert(pin_number < s->num_irq);
33 return s->gic.irq_state[pin_number].irq;
34 }
35
mips_cps_init(Object * obj)36 static void mips_cps_init(Object *obj)
37 {
38 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
39 MIPSCPSState *s = MIPS_CPS(obj);
40
41 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0);
42 /*
43 * Cover entire address space as there do not seem to be any
44 * constraints for the base address of CPC and GIC.
45 */
46 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
47 sysbus_init_mmio(sbd, &s->container);
48 }
49
main_cpu_reset(void * opaque)50 static void main_cpu_reset(void *opaque)
51 {
52 MIPSCPU *cpu = opaque;
53 CPUState *cs = CPU(cpu);
54
55 cpu_reset(cs);
56 }
57
cpu_mips_itu_supported(CPUMIPSState * env)58 static bool cpu_mips_itu_supported(CPUMIPSState *env)
59 {
60 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
61
62 return is_mt && !kvm_enabled();
63 }
64
mips_cps_realize(DeviceState * dev,Error ** errp)65 static void mips_cps_realize(DeviceState *dev, Error **errp)
66 {
67 MIPSCPSState *s = MIPS_CPS(dev);
68 target_ulong gcr_base;
69 bool itu_present = false;
70
71 if (!clock_get(s->clock)) {
72 error_setg(errp, "CPS input clock is not connected to an output clock");
73 return;
74 }
75
76 for (int i = 0; i < s->num_vp; i++) {
77 MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
78 CPUMIPSState *env = &cpu->env;
79
80 /* All VPs are halted on reset. Leave powering up to CPC. */
81 object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
82 &error_abort);
83
84 /* All cores use the same clock tree */
85 qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
86
87 if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
88 return;
89 }
90
91 /* Init internal devices */
92 cpu_mips_irq_init_cpu(cpu);
93 cpu_mips_clock_init(cpu);
94
95 if (cpu_mips_itu_supported(env)) {
96 itu_present = true;
97 /* Attach ITC Tag to the VP */
98 env->itc_tag = mips_itu_get_tag_region(&s->itu);
99 }
100 qemu_register_reset(main_cpu_reset, cpu);
101 }
102
103 /* Inter-Thread Communication Unit */
104 if (itu_present) {
105 object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
106 object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
107 &error_abort);
108 object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
109 &error_abort);
110 if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
111 return;
112 }
113
114 memory_region_add_subregion(&s->container, 0,
115 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
116 }
117
118 /* Cluster Power Controller */
119 object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
120 object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp,
121 &error_abort);
122 object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
123 &error_abort);
124 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
125 return;
126 }
127
128 memory_region_add_subregion(&s->container, 0,
129 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
130
131 /* Global Interrupt Controller */
132 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
133 object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp,
134 &error_abort);
135 object_property_set_uint(OBJECT(&s->gic), "num-irq", 128,
136 &error_abort);
137 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
138 return;
139 }
140
141 memory_region_add_subregion(&s->container, 0,
142 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
143
144 /* Global Configuration Registers */
145 gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
146
147 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
148 object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
149 &error_abort);
150 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
151 &error_abort);
152 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
153 &error_abort);
154 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
155 &error_abort);
156 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
157 &error_abort);
158 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
159 return;
160 }
161
162 memory_region_add_subregion(&s->container, gcr_base,
163 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
164 }
165
166 static Property mips_cps_properties[] = {
167 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
168 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
169 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
170 DEFINE_PROP_END_OF_LIST()
171 };
172
mips_cps_class_init(ObjectClass * klass,void * data)173 static void mips_cps_class_init(ObjectClass *klass, void *data)
174 {
175 DeviceClass *dc = DEVICE_CLASS(klass);
176
177 dc->realize = mips_cps_realize;
178 device_class_set_props(dc, mips_cps_properties);
179 }
180
181 static const TypeInfo mips_cps_info = {
182 .name = TYPE_MIPS_CPS,
183 .parent = TYPE_SYS_BUS_DEVICE,
184 .instance_size = sizeof(MIPSCPSState),
185 .instance_init = mips_cps_init,
186 .class_init = mips_cps_class_init,
187 };
188
mips_cps_register_types(void)189 static void mips_cps_register_types(void)
190 {
191 type_register_static(&mips_cps_info);
192 }
193
194 type_init(mips_cps_register_types)
195